├── .gitignore ├── 2019DD_lab12Finalv4.pdf ├── DD_FIR ├── .ngc2edfcache │ ├── system_axi_ahblite_bridge_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_clkgen_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_dma_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_hdmi_tx_16b_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_iic_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_interconnect_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_interconnect_1_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_interconnect_2_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_interconnect_3_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_spdif_tx_0_wrapper_ngc_98fdbe1c.edif │ ├── system_axi_vdma_0_wrapper_ngc_98fdbe1c.edif │ ├── system_clock_generator_0_wrapper_ngc_98fdbe1c.edif │ ├── system_processing_system7_0_wrapper_ngc_98fdbe1c.edif │ ├── system_util_vector_logic_0_wrapper_ngc_98fdbe1c.edif │ └── system_vga_flyinglogo_0_wrapper_ngc_98fdbe1c.edif ├── DD_FIR.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml ├── DD_FIR.hw │ ├── DD_FIR.lpr │ ├── hw_1 │ │ └── hw.xml │ └── webtalk │ │ ├── .xsim_webtallk.info │ │ ├── labtool_webtalk.log │ │ ├── usage_statistics_ext_labtool.html │ │ └── usage_statistics_ext_labtool.xml ├── DD_FIR.ip_user_files │ └── README.txt ├── DD_FIR.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_26.xml │ │ ├── vrs_config_27.xml │ │ ├── vrs_config_28.xml │ │ ├── vrs_config_29.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_30.xml │ │ ├── vrs_config_31.xml │ │ ├── vrs_config_32.xml │ │ ├── vrs_config_33.xml │ │ ├── vrs_config_34.xml │ │ ├── vrs_config_35.xml │ │ ├── vrs_config_36.xml │ │ ├── vrs_config_37.xml │ │ ├── vrs_config_38.xml │ │ ├── vrs_config_39.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_40.xml │ │ ├── vrs_config_41.xml │ │ ├── vrs_config_42.xml │ │ ├── vrs_config_43.xml │ │ ├── vrs_config_44.xml │ │ ├── vrs_config_45.xml │ │ ├── vrs_config_46.xml │ │ ├── vrs_config_47.xml │ │ ├── vrs_config_48.xml │ │ ├── vrs_config_49.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_50.xml │ │ ├── vrs_config_51.xml │ │ ├── vrs_config_52.xml │ │ ├── vrs_config_53.xml │ │ ├── vrs_config_54.xml │ │ ├── vrs_config_55.xml │ │ ├── vrs_config_56.xml │ │ ├── vrs_config_57.xml │ │ ├── vrs_config_58.xml │ │ ├── vrs_config_59.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_60.xml │ │ ├── vrs_config_61.xml │ │ ├── vrs_config_62.xml │ │ ├── vrs_config_63.xml │ │ ├── vrs_config_64.xml │ │ ├── vrs_config_65.xml │ │ ├── vrs_config_66.xml │ │ ├── vrs_config_67.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── system.bit │ │ ├── system.tcl │ │ ├── system.vdi │ │ ├── system_bus_skew_routed.pb │ │ ├── system_bus_skew_routed.rpt │ │ ├── system_bus_skew_routed.rpx │ │ ├── system_clock_utilization_routed.rpt │ │ ├── system_control_sets_placed.rpt │ │ ├── system_drc_opted.pb │ │ ├── system_drc_opted.rpt │ │ ├── system_drc_opted.rpx │ │ ├── system_drc_routed.pb │ │ ├── system_drc_routed.rpt │ │ ├── system_drc_routed.rpx │ │ ├── system_io_placed.rpt │ │ ├── system_methodology_drc_routed.pb │ │ ├── system_methodology_drc_routed.rpt │ │ ├── system_methodology_drc_routed.rpx │ │ ├── system_opt.dcp │ │ ├── system_placed.dcp │ │ ├── system_power_routed.rpt │ │ ├── system_power_routed.rpx │ │ ├── system_power_summary_routed.pb │ │ ├── system_route_status.pb │ │ ├── system_route_status.rpt │ │ ├── system_routed.dcp │ │ ├── system_timing_summary_routed.pb │ │ ├── system_timing_summary_routed.rpt │ │ ├── system_timing_summary_routed.rpx │ │ ├── system_utilization_placed.pb │ │ ├── system_utilization_placed.rpt │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── system_propImpl.xdc │ │ ├── .ngc2edfcache │ │ ├── system_axi_ahblite_bridge_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_clkgen_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_dma_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_hdmi_tx_16b_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_iic_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_interconnect_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_interconnect_1_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_interconnect_2_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_interconnect_3_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_spdif_tx_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_axi_vdma_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_clock_generator_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_processing_system7_0_wrapper_ngc_98fdbe1c.edif │ │ ├── system_util_vector_logic_0_wrapper_ngc_98fdbe1c.edif │ │ └── system_vga_flyinglogo_0_wrapper_ngc_98fdbe1c.edif │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── planAhead.ngc2edif.log │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── system.dcp │ │ ├── system.tcl │ │ ├── system.vds │ │ ├── system_utilization_synth.pb │ │ ├── system_utilization_synth.rpt │ │ ├── vivado.jou │ │ └── vivado.pb ├── DD_FIR.srcs │ ├── constrs_1 │ │ └── imports │ │ │ └── project_1 │ │ │ └── system.xdc │ └── sources_1 │ │ ├── imports │ │ └── vivado_demo │ │ │ ├── code │ │ │ ├── MYIP_TOP.v │ │ │ ├── Param.v │ │ │ ├── accumulator.v │ │ │ ├── crom.v │ │ │ ├── dbuf.v │ │ │ ├── fir.v │ │ │ ├── fp16_align.v │ │ │ ├── fp16_cal.v │ │ │ ├── fp16_norm.v │ │ │ ├── multi.v │ │ │ ├── multiplier16.v │ │ │ ├── sysctrl.v │ │ │ └── system.v │ │ │ └── imple │ │ │ ├── system_axi_ahblite_bridge_0_wrapper.ngc │ │ │ ├── system_axi_clkgen_0_wrapper.ngc │ │ │ ├── system_axi_dma_0_wrapper.ngc │ │ │ ├── system_axi_hdmi_tx_16b_0_wrapper.ngc │ │ │ ├── system_axi_iic_0_wrapper.ngc │ │ │ ├── system_axi_interconnect_0_wrapper.ngc │ │ │ ├── system_axi_interconnect_1_wrapper.ngc │ │ │ ├── system_axi_interconnect_2_wrapper.ngc │ │ │ ├── system_axi_interconnect_3_wrapper.ngc │ │ │ ├── system_axi_spdif_tx_0_wrapper.ngc │ │ │ ├── system_axi_vdma_0_wrapper.ngc │ │ │ ├── system_clock_generator_0_wrapper.ngc │ │ │ ├── system_processing_system7_0_wrapper.ngc │ │ │ ├── system_util_vector_logic_0_wrapper.ngc │ │ │ └── system_vga_flyinglogo_0_wrapper.ngc │ │ └── ip │ │ └── clkwiz │ │ ├── clkwiz.veo │ │ ├── clkwiz.xci │ │ └── clkwiz.xml ├── DD_FIR.xpr ├── FIR ├── FIR.c ├── FIR_ex ├── planAhead.ngc2edif.log ├── vivado.jou ├── vivado.log ├── vivado_10632.backup.jou ├── vivado_10632.backup.log ├── vivado_12184.backup.jou ├── vivado_12184.backup.log ├── vivado_2060.backup.jou ├── vivado_2060.backup.log ├── vivado_2200.backup.jou ├── vivado_2200.backup.log ├── vivado_6816.backup.jou └── vivado_6816.backup.log ├── LICENSE ├── README.md ├── coeficent_generation ├── 16_to_IEEE ├── 16_to_IEEE.cpp ├── cidx.txt ├── cidx_formatter ├── cidx_formatter.c ├── crom.txt └── merge.txt ├── main.cpp ├── merge.txt ├── moc_mywindow.cpp ├── mywindow.cpp └── mywindow.h /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/joycenerd/DNN-accelerator-on-zynq/HEAD/.gitignore -------------------------------------------------------------------------------- /2019DD_lab12Finalv4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/joycenerd/DNN-accelerator-on-zynq/HEAD/2019DD_lab12Finalv4.pdf -------------------------------------------------------------------------------- /DD_FIR/.ngc2edfcache/system_axi_ahblite_bridge_0_wrapper_ngc_98fdbe1c.edif: -------------------------------------------------------------------------------- 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