├── tut.fi ├── other │ ├── lorem_ipsum │ │ └── 1.0 │ │ │ ├── content │ │ │ ├── Bot.txt │ │ │ ├── MidLevelB.txt │ │ │ ├── MidLevelA.txt │ │ │ ├── TopDog.txt │ │ │ └── LoremIpsum.txt │ │ │ └── lorem_ipsum.1.0.xml │ └── sample_ip │ │ └── 1.0 │ │ ├── main.c │ │ └── sample_ip.1.0.xml ├── cpu.subsystem.test │ └── core_example.setup │ │ └── 1.0 │ │ ├── bin │ │ ├── branchProgram.hex │ │ ├── memoryProgram.hex │ │ └── aluProgram.hex │ │ ├── src │ │ ├── branchProgram.asm │ │ ├── memoryProgram.asm │ │ └── aluProgram.asm │ │ ├── core_example.setup.verilog.designcfg.1.0.xml │ │ └── core_example.setup.1.0.xml ├── cpu.structure.test │ └── cpu_example.setup │ │ └── 1.0 │ │ ├── bin │ │ ├── sumProgram.hex │ │ ├── storageProgram.hex │ │ └── spiProgram.hex │ │ ├── src │ │ ├── sumProgram.asm │ │ ├── spiProgram.asm │ │ └── storageProgram.asm │ │ ├── cpu_example.setup.verilog.designcfg.1.0.xml │ │ └── cpu_example.setup.1.0.xml ├── other.subsystem.test │ ├── wb_example.setup │ │ └── 1.0 │ │ │ ├── header.hh │ │ │ ├── main.cpp │ │ │ ├── wb_example.setup.verilog.designcfg.1.0.xml │ │ │ ├── Makefile │ │ │ ├── wb_example.setup.1.0.xml │ │ │ ├── test_setup.v │ │ │ └── hierarchical_wb_slave_0.v │ └── wb_example.bench │ │ └── 1.0 │ │ ├── TestInitializer.cpp │ │ ├── TestInitializer.hh │ │ └── TestInitializer.v ├── interface │ ├── spi │ │ └── 1.0 │ │ │ ├── spi.1.0.xml │ │ │ └── spi.absDef.1.0.xml │ ├── peripheral_control │ │ └── 1.0 │ │ │ ├── peripheral_control.1.0.xml │ │ │ └── peripheral_control.absDef.1.0.xml │ ├── local_memory │ │ └── 1.1 │ │ │ ├── local_memory.1.1.xml │ │ │ └── local_memory.absDef.1.1.xml │ └── intra_cpu │ │ └── 1.0 │ │ └── intra_cpu.1.0.xml ├── peripheral.subsystem │ └── hierarchical_wb_slave │ │ └── 1.0 │ │ ├── hierarchical_wb_slave.verilog.designcfg.1.0.xml │ │ ├── hierarchical_wb_slave.systemc.designcfg.1.0.xml │ │ ├── hier_slave.hh │ │ └── hierarchical_wb_slave.design.1.0.xml ├── examples │ ├── SampleImporter │ │ └── 1.0 │ │ │ └── SampleImporter.1.0.xml │ ├── MemoryDesign │ │ └── 1.0 │ │ │ └── MemoryDesign.1.0.xml │ ├── SampleSourceAnalyzer │ │ └── 1.0 │ │ │ └── SampleSourceAnalyzer.1.0.xml │ ├── DesignEditor │ │ └── 1.0 │ │ │ └── DesignEditor.1.0.xml │ ├── BusDefinition │ │ └── 1.0 │ │ │ └── BusDefinition.1.0.xml │ ├── GettingStarted │ │ └── 1.0 │ │ │ └── GettingStarted.1.0.xml │ ├── ComponentEditor │ │ └── 1.0 │ │ │ └── ComponentEditor.1.0.xml │ ├── SampleGenerator │ │ └── 1.0 │ │ │ └── SampleGenerator.1.0.xml │ ├── VerilogGeneration │ │ └── 1.0 │ │ │ └── VerilogGeneration.1.0.xml │ └── SimulationSupport │ │ └── 1.0 │ │ └── SimulationSupport.1.0.xml ├── communication.template │ ├── wb_slave │ │ └── 1.0 │ │ │ ├── wb_slave.hh │ │ │ ├── wb_slave.cpp │ │ │ └── wb_slave.v │ ├── spi_slave │ │ └── 1.0 │ │ │ └── spi_slave.v │ └── spi_master │ │ └── 1.0 │ │ └── spi_master.v ├── other.test │ └── clock_generator │ │ └── 1.1 │ │ ├── clock_generator.v │ │ └── clock_generator.1.1.xml ├── peripheral.logic │ └── wb_dual_master │ │ └── 1.0 │ │ ├── wb_master.hh │ │ ├── master.hh │ │ ├── master.v │ │ └── wb_master.cpp ├── cpu.logic │ ├── clock │ │ └── 1.0 │ │ │ └── clock.v │ ├── register_bank │ │ └── 1.0 │ │ │ └── register_bank.v │ └── alu │ │ └── 1.0 │ │ └── alu.v ├── other.subsystem │ ├── GenerationSample │ │ └── 1.0 │ │ │ ├── generation_sample.designcfg.1.0.xml │ │ │ ├── generation_sample.1.0.xml │ │ │ └── generation_sample.design.1.0.xml │ ├── spi_example │ │ └── 1.0 │ │ │ ├── spi_example.designcfg.1.0_bus.xml │ │ │ ├── spi_example.designcfg.1.0_adhoc.xml │ │ │ ├── spi_example.1.0.xml │ │ │ └── spi_example.design.1.0_bus.xml │ ├── wb_example │ │ └── 1.0 │ │ │ └── wb_example.verilog.designcfg.1.0.xml │ ├── spi_example.documents │ │ └── 1.0 │ │ │ └── spi_example.documents.1.0.xml │ └── wb_example.documents │ │ └── 1.0 │ │ └── wb_example.documents.1.0.xml ├── communication.template.test │ ├── spi.setup │ │ └── 1.0 │ │ │ ├── spi.setup.verilog.designcfg.1.0.xml │ │ │ ├── spi.setup.1.0.xml │ │ │ ├── spi.setup.design.1.0.xml │ │ │ └── test_setup.v │ └── wb_slave.setup │ │ └── 1.0 │ │ ├── wb_slave.setup.verilog.designcfg.1.0.xml │ │ ├── wb_slave.setup.1.0.xml │ │ └── wb_slave.setup.design.1.0.xml ├── communication.bridge.test │ └── wb_cpu.setup │ │ └── 1.0 │ │ ├── wb_cpu.setup.verilog.designcfg.1.0.xml │ │ ├── wb_cpu.setup.1.0.xml │ │ └── wb_cpu.setup.design.1.0.xml ├── cpu.subsystem │ ├── core_example │ │ └── 1.0 │ │ │ └── core_example.verilog.designcfg.1.0.xml │ └── core_example.documents │ │ └── 1.0 │ │ └── core_example.documents.1.0.xml ├── cpu.structure │ ├── cpu_example │ │ └── 1.0 │ │ │ └── cpu_example.verilog.designcfg.1.0.xml │ └── cpu_example.documents │ │ └── 1.0 │ │ └── cpu_example.documents.1.0.xml ├── cpu.logic.test │ ├── instruction_memory │ │ └── 1.0 │ │ │ └── instruction_memory.v │ └── data_memory │ │ └── 1.0 │ │ └── data_memory.v └── communication.bus │ └── wishbone │ └── 1.0 │ └── wishbone_bus.hh ├── README.md ├── LICENSE └── opencores.org └── interface └── wishbone └── b4 └── wishbone.b4.xml /tut.fi/other/lorem_ipsum/1.0/content/Bot.txt: -------------------------------------------------------------------------------- 1 | Bot says beep. -------------------------------------------------------------------------------- /tut.fi/other/lorem_ipsum/1.0/content/MidLevelB.txt: -------------------------------------------------------------------------------- 1 | needs LoremIpsum.txt 2 | needs Bot.txt -------------------------------------------------------------------------------- /tut.fi/other/lorem_ipsum/1.0/content/MidLevelA.txt: -------------------------------------------------------------------------------- 1 | needs MidLevelB.txt 2 | needs LoremIpsum.txt -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/bin/branchProgram.hex: -------------------------------------------------------------------------------- 1 | 0000000 2 | 1400001 3 | 1300007 4 | 9340000 5 | 5000003 6 | 4000002 7 | 0000000 8 | 0000000 9 | F000000 -------------------------------------------------------------------------------- /tut.fi/other/sample_ip/1.0/main.c: -------------------------------------------------------------------------------- 1 | int baz() 2 | { 3 | return 0xB105; 4 | } 5 | 6 | int main() 7 | { 8 | int foobar = baz(); 9 | 10 | return 0; 11 | } -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/src/branchProgram.asm: -------------------------------------------------------------------------------- 1 | nop 2 | set 4 1 3 | set 3 0x7 @start 4 | minus 3 4 @target 5 | bne target 6 | bra start 7 | nop 8 | nop 9 | end -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/bin/sumProgram.hex: -------------------------------------------------------------------------------- 1 | 0000000 2 | 0000000 3 | 1000002 4 | 1100003 5 | 1200230 6 | 1300232 7 | 1400001 8 | 150001E 9 | 3120000 10 | 8100000 11 | 2630000 12 | 9540000 13 | 5000008 14 | F000000 -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/src/sumProgram.asm: -------------------------------------------------------------------------------- 1 | nop 2 | nop 3 | set 0 2 4 | set 1 3 5 | set 2 0x230 6 | set 3 0x232 7 | set 4 1 8 | set 5 30 9 | store 1 2 @bufferoi 10 | plus 1 0 11 | load 6 3 12 | minus 5 4 13 | bne bufferoi 14 | end -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/bin/memoryProgram.hex: -------------------------------------------------------------------------------- 1 | 0000000 2 | 170BEEF 3 | 1600040 4 | 150DEAD 5 | 1400050 6 | 3760000 7 | 3540000 8 | 2360000 9 | 2240000 10 | 3740000 11 | 2140000 12 | 0000000 13 | 0000000 14 | 0000000 15 | F000000 -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/src/memoryProgram.asm: -------------------------------------------------------------------------------- 1 | nop 2 | set 7 0xBEEF 3 | set 6 0x40 4 | set 5 0xDEAD 5 | set 4 0x50 6 | store 7 6 7 | store 5 4 8 | load 3 6 9 | load 2 4 10 | store 7 4 11 | load 1 4 12 | nop 13 | nop 14 | nop 15 | end -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/bin/aluProgram.hex: -------------------------------------------------------------------------------- 1 | 0000000 2 | 1300004 3 | 1400006 4 | 9340000 5 | 11000AA 6 | 12000AA 7 | 9120000 8 | 0000000 9 | B210000 10 | 150FFFF 11 | 160FFFF 12 | 8560000 13 | 0000000 14 | 0000000 15 | C560000 16 | C120000 17 | 0000000 18 | F000000 -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/src/aluProgram.asm: -------------------------------------------------------------------------------- 1 | nop 2 | set 3 0x4 3 | set 4 0x6 4 | minus 3 4 5 | set 1 0xAA 6 | set 2 0xAA 7 | minus 1 2 8 | nop 9 | div 2 1 10 | set 5 0xFFFF 11 | set 6 0xFFFF 12 | plus 5 6 13 | nop 14 | nop 15 | cmp 5 6 16 | cmp 1 2 17 | nop 18 | end -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/header.hh: -------------------------------------------------------------------------------- 1 | #ifndef HEADER_HH 2 | #define HEADER_HH 3 | 4 | #include "systemc.h" 5 | 6 | #define DATA_WIDTH 32 7 | #define ADDR_WIDTH 32 8 | #define WAIT_TIME 120 9 | #define BASE_ADDRESS 0x10 10 | #define DATA_COUNT 16 11 | #define SLAVE_SPLIT DATA_COUNT/2 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/bin/storageProgram.hex: -------------------------------------------------------------------------------- 1 | 0000000 2 | 0000000 3 | 1000002 4 | 1100120 5 | 12001A0 6 | 3110000 7 | 8100000 8 | C120000 9 | 5000005 10 | 11001A0 11 | 12001E0 12 | 3110000 13 | 8100000 14 | C120000 15 | 500000B 16 | 11001A0 17 | 1200220 18 | 2310000 19 | 8100000 20 | C120000 21 | 5000011 22 | 0000000 23 | F000000 -------------------------------------------------------------------------------- /tut.fi/other/lorem_ipsum/1.0/content/TopDog.txt: -------------------------------------------------------------------------------- 1 | TopDog 2 | | 3 | ----------- 4 | / | 5 | MidLevelA -> MidLevelB 6 | | / | 7 | | / Bot 8 | | / 9 | LoremIpsum 10 | 11 | needs MidLevelA.txt 12 | needs MidLevelB.txt 13 | -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/bin/spiProgram.hex: -------------------------------------------------------------------------------- 1 | 0000000 2 | 0000000 3 | 1000001 4 | 11002B1 5 | 12002C1 6 | 3110000 7 | 8100000 8 | C120000 9 | 5000005 10 | 1300001 11 | 12002C1 12 | 3320000 13 | 12002B0 14 | 1400000 15 | 2420000 16 | C400000 17 | 500000E 18 | 11002A0 19 | 12002B0 20 | 2510000 21 | 8100000 22 | C120000 23 | 5000013 24 | 0000000 25 | F000000 -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/src/spiProgram.asm: -------------------------------------------------------------------------------- 1 | nop 2 | nop 3 | set 0 1 4 | set 1 0x2B1 5 | set 2 0x2C1 6 | store 1 1 @bufferoi 7 | plus 1 0 8 | cmp 1 2 9 | bne bufferoi 10 | set 3 1 11 | set 2 0x2C1 12 | store 3 2 13 | set 2 0x2B0 14 | set 4 0 15 | load 4 2 @pollaa 16 | cmp 4 0 17 | bne pollaa 18 | set 1 0x2A0 19 | set 2 0x2B0 20 | load 5 1 @lue 21 | plus 1 0 22 | cmp 1 2 23 | bne lue 24 | nop 25 | end -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/src/storageProgram.asm: -------------------------------------------------------------------------------- 1 | nop 2 | nop 3 | set 0 2 4 | set 1 0x120 5 | set 2 0x1A0 6 | store 1 1 @isoSailoo 7 | plus 1 0 8 | cmp 1 2 9 | bne isoSailoo 10 | set 1 0x1A0 11 | set 2 0x1E0 12 | store 1 1 @hashSailoo 13 | plus 1 0 14 | cmp 1 2 15 | bne hashSailoo 16 | set 1 0x1A0 17 | set 2 0x220 18 | load 3 1 @hashLukee 19 | plus 1 0 20 | cmp 1 2 21 | bne hashLukee 22 | nop 23 | end -------------------------------------------------------------------------------- /tut.fi/other/lorem_ipsum/1.0/content/LoremIpsum.txt: -------------------------------------------------------------------------------- 1 | Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum. -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.bench/1.0/TestInitializer.cpp: -------------------------------------------------------------------------------- 1 | #include "TestIntitializer.hh" 2 | #include "header.hh" 3 | 4 | void TestIntitializer::init() 5 | { 6 | start = 0; 7 | // Assert reset 8 | rst = 0; 9 | wait(); 10 | // Deassert reset 11 | wait(); 12 | wait(); 13 | rst = 1; 14 | wait(); 15 | start = 1; 16 | wait(); 17 | wait(); 18 | wait(); 19 | start = 0; 20 | 21 | wait(WAIT_TIME); 22 | 23 | if ( done == 0 ) 24 | printf("not done!"); 25 | else 26 | printf("done high"); 27 | sc_stop(); 28 | } -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.bench/1.0/TestInitializer.hh: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | SC_MODULE (TestIntitializer) 4 | { 5 | sc_in_clk clk; // The mandatory clock, as this is synchronous logic. 6 | sc_out rst; // The mandatory reset, as this is synchronous logic. 7 | sc_out start; // Input used to signal that is is ok to start the masters. 8 | sc_in done; // Output used to signal that the masters are done sending. 9 | 10 | void init(); 11 | 12 | SC_CTOR(TestIntitializer) 13 | { 14 | //Initialize processes as threads, with reset active high 15 | SC_CTHREAD(init,clk.pos()); 16 | } 17 | }; 18 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ipxactexamplelib 2 | Contains examples to get started with Kactus2. 3 | VLNV naming recommendation: http://funbase.cs.tut.fi/doc/Kactus2_vlnv.pdf 4 | See video tutorials at: https://www.youtube.com/user/Kactus2Tutorial 5 | 6 | ## The IP-XACT documents for the plugin templates are listed in the following catalogs: 7 | * Sample Generator: tut.fi:examples:SampleGenerator:1.0 8 | * Sample Importer: tut.fi:examples:SampleImporter:1.0 9 | * Sample Source Analyzer: tut.fi:examples:SampleSourceAnalyzer:1.0 10 | 11 | ## The IP-XACT documents for the video tutorials are listed in the following catalogs: 12 | * Getting Started: tut.fi:examples:GettingStarted:1.0 13 | * Component Editor: tut.fi:examples:ComponentEditor:1.0 14 | * Design Editor: tut.fi:examples:DesignEditor:1.0 15 | * Verilog Generation: tut.fi:examples:VerilogGeneration:1.0 16 | * Simulation Support: tut.fi:examples:SimulationSupport:1.0 17 | * Bus Definition: tut.fi:examples:BusDefinition:1.0 18 | * Memory Design: tut.fi:examples:MemoryDesign:1.0 -------------------------------------------------------------------------------- /tut.fi/interface/spi/1.0/spi.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | spi 6 | 1.0 7 | true 8 | true 9 | false 10 | 1 11 | Serial Peripheral Interface bus for multislave full duplex communication. 12 | 13 | 3,3,515,0 14 | 15 | 16 | -------------------------------------------------------------------------------- /tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | peripheral.subsystem 5 | hierarchical_wb_slave.verilog.designcfg 6 | 1.0 7 | 8 | 9 | 3,0,114,0 10 | 11 | HW 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /tut.fi/interface/peripheral_control/1.0/peripheral_control.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | peripheral_control 6 | 1.0 7 | true 8 | true 9 | 1 10 | 1 11 | Defines a one-to-one access from memory controller to more dedicated peripherals controllers, i.e a bridge between CPU core and peripheral bus. 12 | 13 | 3,4,4,0 14 | 15 | 16 | -------------------------------------------------------------------------------- /tut.fi/examples/SampleImporter/1.0/SampleImporter.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | SampleImporter 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the example generator plugin "Sample Importer" 8 | 9 | 10 | 11 | ../../../other/sample_ip/1.0/sample_ip.1.0.xml 12 | 13 | 14 | 15 | 3,3,323,0 16 | 17 | 18 | -------------------------------------------------------------------------------- /tut.fi/examples/MemoryDesign/1.0/MemoryDesign.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | MemoryDesign 6 | 1.0 7 | This catalog contains all the IP-XACT files used in th eMemory Design video tutorial for Kactus2. 8 | 9 | 10 | 11 | ../../../cpu.structure/cpu_example.documents/1.0/cpu_example.documents.1.0.xml 12 | 13 | 14 | 15 | 3,4,108,0 16 | 17 | 18 | -------------------------------------------------------------------------------- /tut.fi/examples/SampleSourceAnalyzer/1.0/SampleSourceAnalyzer.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | SampleSourceAnalyzer 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the example generator plugin "Sample Source Analyzer" 8 | 9 | 10 | 11 | ../../../other/lorem_ipsum/1.0/lorem_ipsum.1.0.xml 12 | 13 | 14 | 15 | 3,3,323,0 16 | 17 | 18 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2017 Tampere University of Technology 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /tut.fi/examples/DesignEditor/1.0/DesignEditor.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | DesignEditor 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the Design Editor video tutorial for Kactus2. 8 | 9 | 10 | 11 | ../../../other.subsystem/wb_example.documents/1.0/wb_example.documents.1.0.xml 12 | 13 | 14 | 15 | 3,3,279,0 16 | 17 | 18 | -------------------------------------------------------------------------------- /tut.fi/examples/BusDefinition/1.0/BusDefinition.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | BusDefinition 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the Bus Definition video tutorial for Kactus2. 8 | 9 | 10 | 11 | ../../../other.subsystem/spi_example.documents/1.0/spi_example.documents.1.0.xml 12 | 13 | 14 | 15 | 3,3,318,0 16 | 17 | 18 | -------------------------------------------------------------------------------- /tut.fi/examples/GettingStarted/1.0/GettingStarted.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | GettingStarted 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the Getting Started video tutorial for Kactus2. 8 | 9 | 10 | 11 | ../../../other.subsystem/wb_example.documents/1.0/wb_example.documents.1.0.xml 12 | 13 | 14 | 15 | 3,3,279,0 16 | 17 | 18 | -------------------------------------------------------------------------------- /tut.fi/interface/local_memory/1.1/local_memory.1.1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | local_memory 6 | 1.1 7 | true 8 | false 9 | true 10 | 1 11 | 1 12 | A one-to-one memory access, which is assumed to work without missing cycles: The data in the current address is available at the next clock cycle. 13 | 14 | The clock and reset are ommitted from this interface: It is assumed that both slave and master are on the same clock domain. 15 | 16 | -------------------------------------------------------------------------------- /tut.fi/communication.template/wb_slave/1.0/wb_slave.hh: -------------------------------------------------------------------------------- 1 | #include "header.hh" 2 | #include "systemc.h" 3 | 4 | SC_MODULE (wb_slave) 5 | { 6 | sc_in_clk clk; // The mandatory clock, as this is synchronous logic. 7 | sc_in rst; // The mandatory reset, as this is synchronous logic. 8 | 9 | sc_in cyc_i; // Asserted by master for transfer. 10 | sc_in stb_i; // Asserted, when this specific slave is selected. 11 | sc_out ack_o; // Slave asserts acknowledge. 12 | sc_in we_i; // Write = 1, Read = 0. 13 | sc_out > dat_o; // Data from slave to master. 14 | sc_in > dat_i; //Data from master to slave. 15 | sc_in > adr_i; // The address of the data. 16 | 17 | void run(); 18 | 19 | SC_CTOR(wb_slave) 20 | { 21 | //Initialize process as a thread, with reset active high 22 | SC_CTHREAD(run, clk.pos()); 23 | reset_signal_is(rst, false); 24 | } 25 | }; -------------------------------------------------------------------------------- /tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.systemc.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | peripheral.subsystem 5 | hierarchical_wb_slave.systemc.designcfg 6 | 1.0 7 | 8 | 9 | sub_slave 10 | 11 | 12 | 13 | 3,1,6,0 14 | 15 | HW 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /tut.fi/other.test/clock_generator/1.1/clock_generator.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : clock_generator.v 3 | // Creation date : 26.04.2017 4 | // Creation time : 16:30:51 5 | // Description : A clock source for simulations. Will also assert and deassert reset and terminate the simulation after WAIT_TIME has passed since the deassertion. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.74 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:testBench:clock_generator:1.1 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/testBench/clock_generator/1.1/clock_generator.1.1.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module clock_generator( 14 | // Interface: wb_system 15 | output reg clk_o, // The mandatory clock, as this is synchronous logic. 16 | output reg rst_o // The mandatory reset, as this is synchronous logic. 17 | ); 18 | 19 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 20 | initial begin 21 | clk_o = 1'b0; 22 | rst_o = 1'b1; // assert reset 23 | repeat(4) #5 clk_o = ~clk_o; 24 | rst_o = 1'b0; // deassert reset 25 | forever #5 clk_o = ~clk_o; // generate a clock 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /tut.fi/peripheral.logic/wb_dual_master/1.0/wb_master.hh: -------------------------------------------------------------------------------- 1 | #include "header.hh" 2 | #include "systemc.h" 3 | 4 | SC_MODULE (wb_master) 5 | { 6 | sc_in_clk clk; // The mandatory clock, as this is synchronous logic. 7 | sc_in rst; // The mandatory reset, as this is synchronous logic. 8 | sc_in start; // Input used to signal that is is ok to start the masters. 9 | sc_out done; // Output used to signal that the masters are done sending. 10 | 11 | sc_out cyc_o; // Asserted by master for transfer. 12 | sc_out stb_o; // Asserted by master for transfer. 13 | sc_in ack_i; // Slave asserts acknowledge. 14 | sc_out we_o; // Write = 1, Read = 0. 15 | sc_out > dat_o; // Data from master to slave. 16 | sc_in > dat_i; // Data from slave to master. 17 | sc_out > adr_o; // The address of the data. 18 | 19 | void run(); 20 | 21 | SC_CTOR(wb_master) 22 | { 23 | //Initialize process as a thread, with reset active high 24 | SC_CTHREAD(run, clk.pos()); 25 | reset_signal_is(rst, false); 26 | } 27 | }; -------------------------------------------------------------------------------- /opencores.org/interface/wishbone/b4/wishbone.b4.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | opencores.org 4 | interface 5 | wishbone 6 | b4 7 | true 8 | false 9 | true 10 | 11 | ClockSource 12 | ClockSink 13 | 14 | Specification of wishbone bus is available at: http://cdn.opencores.org/downloads/wbspec_b4.pdf 15 | 16 | Clock and reset signals are not specifically master-to-slave signals nor vice versa, but instead they come from a third party that assumes neither mode. 17 | 18 | Notice that while multiple slaves and masters are supported, broadcasts are not. Thus an arbiter will be required, unless it is a single master to single slave connection. 19 | 20 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/main.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | #include "header.hh" 3 | #include "SampleHW.hh" 4 | #include "TestIntitializer.hh" 5 | 6 | // The clock 7 | sc_clock the_clock("my_the_clock",1,SC_NS); 8 | 9 | // Variables and signals shared with the process 10 | sc_signal reset; //Reset, active high 11 | 12 | sc_signal start; // Input used to signal that is is ok to start the masters. 13 | sc_signal done; // Output used to signal that the masters are done sending. 14 | 15 | int sc_main (int argc, char* argv[]) 16 | { 17 | //Disable false positives 18 | sc_core::sc_report_handler::set_actions( "/IEEE_Std_1666/deprecated", 19 | sc_core::SC_DO_NOTHING ); 20 | sc_core::sc_report_handler::set_actions( SC_ID_END_MODULE_NOT_CALLED_, 21 | SC_DO_NOTHING); 22 | 23 | //Initialization of the test bench 24 | TestIntitializer* tb = new TestIntitializer("TestIntitializer"); 25 | tb->clk(the_clock); 26 | tb->rst(reset); 27 | tb->start(start); 28 | tb->done(done); 29 | 30 | //Initialization of the DUT 31 | SampleHW* shw = new SampleHW( "SampleHW" ); 32 | shw->clk(the_clock); 33 | shw->rst(reset); 34 | shw->start(start); 35 | shw->done(done); 36 | 37 | //Start the simulation 38 | sc_start(); 39 | 40 | return 0; 41 | } 42 | -------------------------------------------------------------------------------- /tut.fi/cpu.logic/clock/1.0/clock.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : clock.v 3 | // Creation date : 03.04.2017 4 | // Creation time : 11:15:26 5 | // Description : 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.18 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:core:clock:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/core/clock/1.0/clock.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module clock #( 14 | parameter SCALE = 2 // Divides the input clock by this value. 15 | ) ( 16 | // Interface: cpu_clk_source 17 | // The clock that is divided to other components. 18 | output clk_o, // The clock that is divided to other components. 19 | output rst_o, // The reset that is divided to other components. 20 | 21 | // These ports are not in any interface 22 | input clk_i, // The reference clock for this component. 23 | input rst_i // The reference reset for this component. 24 | ); 25 | 26 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 27 | assign clk_o = clk_i; 28 | assign rst_o = rst_i; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hier_slave.hh: -------------------------------------------------------------------------------- 1 | #include "header.hh" 2 | #include "systemc.h" 3 | 4 | SC_MODULE (hier_slave) 5 | { 6 | sc_in_clk clk; // The mandatory clock, as this is synchronous logic. 7 | sc_in rst; // The mandatory reset, as this is synchronous logic. 8 | 9 | sc_in cyc_i; // Asserted by master for transfer. 10 | sc_in stb_i; // Asserted, when this specific slave is selected. 11 | sc_out ack_o; // Slave asserts acknowledge. 12 | sc_in we_i; // Write = 1, Read = 0. 13 | sc_out > dat_o; // Data from slave to master. 14 | sc_in > dat_i; //Data from master to slave. 15 | sc_in > adr_i; // The address of the data. 16 | 17 | wb_slave* slave; 18 | 19 | SC_CTOR(hier_slave) 20 | { 21 | slave = new wb_slave("slave"); 22 | slave->clk(clk); 23 | slave->rst(rst); 24 | 25 | slave->cyc_i(cyc_i); 26 | slave->stb_i(stb_i); 27 | slave->ack_o(ack_o); 28 | slave->we_i(we_i); 29 | slave->dat_o(dat_o); 30 | slave->dat_i(dat_i); 31 | slave->adr_i(adr_i); 32 | } 33 | }; -------------------------------------------------------------------------------- /tut.fi/other/sample_ip/1.0/sample_ip.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other 5 | sample_ip 6 | 1.0 7 | 8 | 9 | 10 | rtl 11 | 12 | 13 | 14 | 15 | 16 | src 17 | 18 | main.c 19 | cSource 20 | 21 | 22 | 23 | Used to demonstrate workings of some sample plugins. 24 | 25 | 3,0,66,0 26 | 27 | IP 28 | HW 29 | Fixed 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/GenerationSample/1.0/generation_sample.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | generation_sample.designcfg 6 | 1.0 7 | 8 | 9 | sample_ip_0 10 | 11 | 12 | 13 | sample_ip_1 14 | 15 | 16 | 17 | sample_ip_2 18 | 19 | 20 | 21 | 3,0,66,0 22 | 23 | HW 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/spi.setup/1.0/spi.setup.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.template.test 5 | spi.setup.verilog.designcfg 6 | 1.0 7 | 8 | 9 | spi_master_0 10 | 11 | 12 | 13 | spi_slave_0 14 | 15 | 16 | 17 | clock_generator_0 18 | 19 | 20 | 21 | 3,4,107,0 22 | 23 | HW 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.bridge.test 5 | wb_cpu.setup.verilog.designcfg 6 | 1.0 7 | 8 | 9 | wb_cpu.bench_0 10 | 11 | 12 | 13 | clock_generator_0 14 | 15 | 16 | 17 | wb_master_cpu_slave_0 18 | 19 | 20 | 21 | 3,4,104,0 22 | 23 | HW 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/wb_slave.setup/1.0/wb_slave.setup.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.template.test 5 | wb_slave.setup.verilog.designcfg 6 | 1.0 7 | 8 | 9 | wb_slave_0 10 | 11 | 12 | 13 | clock_generator_0 14 | 15 | 16 | 17 | wb_master_0 18 | 19 | 20 | 21 | 3,4,107,0 22 | 23 | HW 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/wb_example.setup.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem.test 5 | wb_example.setup.verilog.designcfg 6 | 1.0 7 | 8 | 9 | clock_generator_0 10 | 11 | 12 | 13 | wb_example_0 14 | 15 | 16 | 17 | wb_example.bench_0 18 | 19 | 20 | 21 | 3,4,107,0 22 | 23 | HW 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/spi_example/1.0/spi_example.designcfg.1.0_bus.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | spi_example.designcfg 6 | 1.0_bus 7 | 8 | 9 | spi_master_0 10 | 11 | 12 | 13 | spi_slave_0 14 | 15 | 16 | 17 | spi_slave_1 18 | 19 | 20 | 21 | spi_slave_2 22 | 23 | 24 | 25 | 3,3,506,0 26 | 27 | HW 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/spi_example/1.0/spi_example.designcfg.1.0_adhoc.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | spi_example.designcfg 6 | 1.0_adhoc 7 | 8 | 9 | spi_master_0 10 | 11 | 12 | 13 | spi_slave_0 14 | 15 | 16 | 17 | spi_slave_1 18 | 19 | 20 | 21 | spi_slave_2 22 | 23 | 24 | 25 | 3,3,506,0 26 | 27 | HW 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/core_example.setup.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.subsystem.test 5 | core_example.setup.verilog.designcfg 6 | 1.0 7 | 8 | 9 | core_example_0 10 | 11 | 12 | 13 | instruction_memory_0 14 | 15 | 16 | 17 | clock_generator_0 18 | 19 | 20 | 21 | data_memory_0 22 | 23 | 24 | 25 | 3,4,123,0 26 | 27 | HW 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /tut.fi/communication.template/wb_slave/1.0/wb_slave.cpp: -------------------------------------------------------------------------------- 1 | #include "wb_slave.hh" 2 | 3 | #define S_WAIT 0 // Waiting for cyc_i & stb_i 4 | #define S_DEASSERT 1 // Deassert acknowledgement. 5 | 6 | void wb_slave::run() 7 | { 8 | // We have as much memory as parameterized. 9 | sc_uint dat[DATA_COUNT]; 10 | 11 | ack_o = 0; // Obviously, there is nothing to acknowledge by default. 12 | dat_o = 0; // No output by default. 13 | int state = S_WAIT; // Wait signals from the masters at reset. 14 | 15 | while( true ) 16 | { 17 | if (state == S_WAIT) 18 | { 19 | // Wait signal from the master. 20 | if ( cyc_i == 1 && stb_i == 1 ) 21 | { 22 | // Master ok, acknowledge. 23 | ack_o = 1; 24 | 25 | if ( we_i == 1 ) 26 | { 27 | // Writing means we set data to the specified address, offsetted by the base address. 28 | dat[adr_i.read() - BASE_ADDRESS] = dat_i.read(); 29 | } 30 | else 31 | { 32 | // Reading means we output dat from the specified address, offsetted by the base address. 33 | dat_o = dat[adr_i.read() - BASE_ADDRESS]; 34 | } 35 | 36 | // Next thing is to deassert. 37 | state = S_DEASSERT; 38 | } 39 | } 40 | else if (state == S_DEASSERT) 41 | { 42 | // Deassert acknowlegement, get ready to receive next one. 43 | ack_o = 0; 44 | state = S_WAIT; 45 | } 46 | else 47 | printf("ERROR: Unkown state: %d\n", state); 48 | 49 | // Proceed to the next cycle. 50 | wait(); 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /tut.fi/interface/intra_cpu/1.0/intra_cpu.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | intra_cpu 6 | 1.0 7 | true 8 | true 9 | false 10 | 0 11 | 0 12 | 13 | Decoder 14 | MemoryControl 15 | ALU 16 | RegisterBank 17 | ClockSource 18 | ClockSink 19 | 20 | Bus definition that bundles signals in our example CPU core. Each system group corresponds an element in the core, so that each signal with a group is accessed by the element corresponding the group. 21 | 22 | Notice that even though the abstraction definition contains a signal that passes addresses, this is not addressable bus as no memory maps may be traced through this interface. 23 | 24 | 3,4,4,0 25 | 26 | 27 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/GenerationSample/1.0/generation_sample.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | generation_sample 6 | 1.0 7 | 8 | 9 | 10 | flat 11 | :: 12 | 13 | 14 | SampleHardware 15 | :: 16 | GenerationSample.designcfg_1.0 17 | 18 | 19 | 20 | 21 | GenerationSample.designcfg_1.0 22 | 23 | 24 | 25 | 26 | 27 | 3,0,66,0 28 | 29 | Product 30 | HW 31 | Mutable 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem/core_example/1.0/core_example.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.subsystem 5 | core_example.verilog.designcfg 6 | 1.0 7 | 8 | 9 | register_bank 10 | 11 | 12 | 13 | clock 14 | 15 | 16 | 17 | memory_controller 18 | 19 | 20 | 21 | alu 22 | 23 | 24 | 25 | instruction_decoder 26 | 27 | 28 | 29 | 3,4,4,0 30 | 31 | HW 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /tut.fi/examples/ComponentEditor/1.0/ComponentEditor.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | ComponentEditor 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the Component Editor video tutorial for Kactus2. The top-level component is tut.fi:communication.template:wb_slave:1.0. 8 | 9 | 10 | 11 | ../../../../opencores.org/interface/wishbone/b4/wishbone.b4.xml 12 | 13 | 14 | 15 | 16 | 17 | ../../../../opencores.org/interface/wishbone/b4/wishbone.absDef.b4.xml 18 | 19 | 20 | 21 | 22 | 23 | ../../../communication.template/wb_slave/1.0/wb_slave.1.0.xml 24 | 25 | 26 | 27 | 3,3,318,0 28 | 29 | 30 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/wb_example/1.0/wb_example.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | wb_example.verilog.designcfg 6 | 1.0 7 | 8 | 9 | wishbone_0 10 | 11 | 12 | 13 | hierarchical_wb_slave_0 14 | 15 | 16 | 17 | wb_dual_master_0 18 | 19 | 20 | 21 | wb_slave_1 22 | 23 | 24 | 25 | wb_slave_0 26 | 27 | 28 | 29 | 3,4,104,0 30 | 31 | HW 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /tut.fi/other/lorem_ipsum/1.0/lorem_ipsum.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other 5 | lorem_ipsum 6 | 1.0 7 | 8 | 9 | content 10 | 11 | content/Bot.txt 12 | user 13 | 14 | 15 | content/LoremIpsum.txt 16 | user 17 | 18 | 19 | content/MidLevelA.txt 20 | user 21 | 22 | 23 | content/MidLevelB.txt 24 | user 25 | 26 | 27 | content/TopDog.txt 28 | user 29 | 30 | 31 | 32 | Used to illustrate workings of the sample code analyzer plugin. 33 | 34 | 3,0,66,0 35 | 36 | SW 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/cpu_example.setup.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.structure.test 5 | cpu_example.setup.verilog.designcfg 6 | 1.0 7 | 8 | 9 | spi_slave_0 10 | 11 | 12 | 13 | clock_generator_0 14 | 15 | 16 | 17 | instruction_memory_0 18 | 19 | 20 | 21 | data_memory_0 22 | 23 | 24 | 25 | cpu_example_0 26 | 27 | 28 | 29 | 3,4,123,0 30 | 31 | HW 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/spi_example/1.0/spi_example.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | spi_example 6 | 1.0 7 | 8 | 9 | 10 | adhoc_design 11 | adhoc_design_configuration 12 | 13 | 14 | bus_design 15 | bus_design_configuration 16 | 17 | 18 | 19 | 20 | adhoc_design_configuration 21 | 22 | 23 | 24 | bus_design_configuration 25 | 26 | 27 | 28 | 29 | 30 | 3,3,506,0 31 | 32 | IP 33 | HW 34 | Mutable 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /tut.fi/examples/SampleGenerator/1.0/SampleGenerator.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | SampleGenerator 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the example generator plugin "Sample Generator". The top-level component is tut.fi:other.subsystem:generation_sample:1.0. 8 | 9 | 10 | 11 | ../../../other.subsystem/GenerationSample/1.0/generation_sample.1.0.xml 12 | 13 | 14 | 15 | ../../../other/sample_ip/1.0/sample_ip.1.0.xml 16 | 17 | 18 | 19 | 20 | 21 | ../../../other.subsystem/GenerationSample/1.0/generation_sample.design.1.0.xml 22 | 23 | 24 | 25 | 26 | 27 | ../../../other.subsystem/GenerationSample/1.0/generation_sample.designcfg.1.0.xml 28 | 29 | 30 | 31 | 3,3,318,0 32 | 33 | 34 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.bench/1.0/TestInitializer.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : TestInitializer.v 3 | // Creation date : 10.05.2017 4 | // Creation time : 16:20:32 5 | // Description : A bare bones verilog test bench, which is used to assert reset, generate clock, give start signal and finally check after WAIT_TIME, if the done is asserted. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.107 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:other.subsystem.test:wb_example.bench:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/other.subsystem.test/wb_example.bench/1.0/wb_example.bench.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module TestInitializer #( 14 | parameter WAIT_TIME = 100, // How long to wait after reset is deassereted. 15 | parameter V_WAIT_TIME = WAIT_TIME // How long to wait after reset is deassereted. 16 | ) ( 17 | // These ports are not in any interface 18 | input clk_i, // The mandatory clock, as this is synchronous logic. 19 | input done, // Output used to signal that the masters are done sending. 20 | input rst_i, // The mandatory reset, as this is synchronous logic. 21 | output reg start // Input used to signal that is is ok to start the masters. 22 | ); 23 | 24 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 25 | initial begin 26 | start = 0; 27 | @(posedge rst_i); // wait for reset 28 | start = 1; 29 | @(posedge clk_i); 30 | @(posedge clk_i); 31 | @(posedge clk_i); 32 | start =0; // generate the falling edge 33 | #V_WAIT_TIME 34 | if ( done == 1'b0 ) 35 | $display("not done!"); 36 | else 37 | $display("done high"); 38 | 39 | $stop; 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /tut.fi/cpu.structure/cpu_example/1.0/cpu_example.verilog.designcfg.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.structure 5 | cpu_example.verilog.designcfg 6 | 1.0 7 | 8 | 9 | wishbone_bridge 10 | 11 | 12 | 13 | wishbone_bus 14 | 15 | 16 | 17 | sum_buffer 18 | 19 | 20 | 21 | wb_slave_spi_master 22 | 23 | 24 | 25 | core 26 | 27 | 28 | 29 | external_mem_hash 30 | 31 | 32 | 33 | external_mem_large 34 | 35 | 36 | 37 | 3,4,3,0 38 | 39 | HW 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/GenerationSample/1.0/generation_sample.design.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | generation_sample.design 6 | 1.0 7 | 8 | 9 | sample_ip_0 10 | 11 | 12 | {ab1c4e95-836a-40dc-b1b9-cf03b32144b1} 13 | 14 | 15 | 16 | 17 | sample_ip_1 18 | 19 | 20 | {b3cd7664-2026-446b-9760-c68232cc686e} 21 | 22 | 23 | 24 | 25 | sample_ip_2 26 | 27 | 28 | {21a8cd2c-a427-4bb8-9cca-50e71d5f128e} 29 | 30 | 31 | 32 | 33 | 34 | 3,0,66,0 35 | 36 | HW 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/Makefile: -------------------------------------------------------------------------------- 1 | _INCLUDES= ../../../soc/SampleHW/1.0/ ../../../chip/SampleTB/1.0/ ../../../ip.hw/TestIntitializer/1.0/ ../../../ip.hw/master/1.0/ ../../../ip.hw/wb_slave/1.0/ ../../../ip.hw/hierarchical_wb_slave/1.0/ ../../../ip.com/wishbone_bus/1.0/ 2 | INCLUDES=$(patsubst %, -I%, $(_INCLUDES)) 3 | 4 | DEPS= Makefile 5 | 6 | ENAME= SampleTBSimulation 7 | EFLAGS= $(INCLUDES) $(DEBUG_FLAGS) $(PROFILE_FLAGS) -DhwB -L$(SYSTEMC_HOME)/lib-linux -lsystemc 8 | EBUILDER= g++ 9 | _OBJ= main.cpp.o TestIntitializer.cpp.o wb_master.cpp.o wb_slave.cpp.o 10 | ODIR= obj 11 | OBJ= $(patsubst %,$(ODIR)/%,$(_OBJ)) 12 | 13 | $(ENAME): $(OBJ) 14 | $(EBUILDER) -o $(ENAME) $(OBJ) $(EFLAGS) 15 | 16 | clean: 17 | rm -f $(OBJ:%.o=%.d); 18 | rm -f $(OBJ); 19 | 20 | all: $(OBJ) 21 | 22 | $(OBJ): | $(ODIR) 23 | 24 | $(ODIR): 25 | mkdir -p $(ODIR) 26 | 27 | DEBUG_FLAGS += 28 | debug: DEBUG_FLAGS += -ggdb -fno-omit-frame-pointer -fno-inline-functions -fno-inline-functions-called-once -fno-optimize-sibling-calls 29 | debug: $(ENAME) 30 | 31 | PROFILE_FLAGS += 32 | profile: PROFILE_FLAGS += -pg -fno-omit-frame-pointer -fno-inline-functions -fno-inline-functions-called-once -fno-optimize-sibling-calls 33 | profile: $(ENAME) 34 | 35 | -include $(OBJ:%.o=%.d) 36 | 37 | $(ODIR)/main.cpp.o: $(DEPS) main.cpp 38 | g++ -MMD -MP -c -o $(ODIR)/main.cpp.o main.cpp $(INCLUDES) $(DEBUG_FLAGS) $(PROFILE_FLAGS) -I$(SYSTEMC_HOME)/include -L$(SYSTEMC_HOME)/lib-linux -lsystemc -DhwB 39 | 40 | $(ODIR)/TestIntitializer.cpp.o: $(DEPS) ../../../ip.hw/TestIntitializer/1.0/TestIntitializer.cpp 41 | g++ -MMD -MP -c -o $(ODIR)/TestIntitializer.cpp.o ../../../ip.hw/TestIntitializer/1.0/TestIntitializer.cpp $(INCLUDES) $(DEBUG_FLAGS) $(PROFILE_FLAGS) -I$(SYSTEMC_HOME)/include -L$(SYSTEMC_HOME)/lib-linux -lsystemc -DhwB 42 | 43 | $(ODIR)/wb_master.cpp.o: $(DEPS) ../../../ip.hw/master/1.0/wb_master.cpp 44 | g++ -MMD -MP -c -o $(ODIR)/wb_master.cpp.o ../../../ip.hw/master/1.0/wb_master.cpp $(INCLUDES) $(DEBUG_FLAGS) $(PROFILE_FLAGS) -I$(SYSTEMC_HOME)/include -L$(SYSTEMC_HOME)/lib-linux -lsystemc -DhwB 45 | 46 | $(ODIR)/wb_slave.cpp.o: $(DEPS) ../../../ip.hw/wb_slave/1.0/wb_slave.cpp 47 | g++ -MMD -MP -c -o $(ODIR)/wb_slave.cpp.o ../../../ip.hw/wb_slave/1.0/wb_slave.cpp $(INCLUDES) $(DEBUG_FLAGS) $(PROFILE_FLAGS) -I$(SYSTEMC_HOME)/include -L$(SYSTEMC_HOME)/lib-linux -lsystemc -DhwB 48 | -------------------------------------------------------------------------------- /tut.fi/cpu.logic.test/instruction_memory/1.0/instruction_memory.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : instruction_memory.v 3 | // Creation date : 28.11.2017 4 | // Creation time : 12:45:25 5 | // Description : Used to supplant instruction memory in simulations. NOTICE: Ports are described in interfaces.local_memory. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.1184 32-bit 8 | // Plugin : Verilog generator 2.1 9 | // This file was generated based on IP-XACT component tut.fi:cpu.logic.test:instruction_memory:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic.test/instruction_memory/1.0/instruction_memory.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module instruction_memory #( 14 | parameter INSTRUCTION_ADDRESS_WIDTH = 8, // Width of an instruction address. 15 | parameter INSTRUCTION_WIDTH = 28 // Total width of an instruction 16 | ) ( 17 | // Interface: slave 18 | input [INSTRUCTION_ADDRESS_WIDTH-1:0] iaddr_i, 19 | output reg [INSTRUCTION_WIDTH-1:0] instruction_feed, 20 | 21 | // These ports are not in any interface 22 | input clk_i, // The mandatory clock, as this is synchronous logic. 23 | input rst_i // The mandatory reset, as this is synchronous logic. 24 | ); 25 | 26 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 27 | localparam MAX_CLOCKS = 10000; 28 | 29 | reg [INSTRUCTION_WIDTH-1:0] instruction_memory [(2**INSTRUCTION_ADDRESS_WIDTH)-1:0]; 30 | 31 | integer total_clk; 32 | 33 | initial begin 34 | $readmemh("program.hex", instruction_memory); 35 | end 36 | 37 | initial begin 38 | instruction_feed = 0; 39 | total_clk = 0; 40 | @(negedge rst_i); // wait for reset 41 | 42 | forever begin 43 | instruction_feed = instruction_memory[iaddr_i]; 44 | @(posedge clk_i); 45 | 46 | total_clk = total_clk + 1; 47 | 48 | if (total_clk >= MAX_CLOCKS || instruction_feed[27:24] == 'hF) 49 | $stop; 50 | end 51 | 52 | @(posedge clk_i); 53 | $stop; 54 | end 55 | endmodule 56 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/spi.setup/1.0/spi.setup.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.template.test 5 | spi.setup 6 | 1.0 7 | 8 | 9 | 10 | hierarchical_verilog 11 | verilog_implementation 12 | verilog_design_configuration 13 | 14 | 15 | 16 | 17 | verilog_implementation 18 | Verilog 19 | test_setup 20 | 21 | verilogSource 22 | 23 | 24 | 25 | verilog_design_configuration 26 | 27 | 28 | 29 | 30 | 31 | 32 | verilogSource 33 | generatedFiles 34 | 35 | test_setup.v 36 | verilogSource 37 | Generated at 15:57:45 on 28.11.2017 by Kactus2. 38 | 39 | 40 | 41 | Test arrangement for verifying the SPI examples. 42 | 43 | 3,4,107,0 44 | 45 | IP 46 | HW 47 | Mutable 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.bridge.test 5 | wb_cpu.setup 6 | 1.0 7 | 8 | 9 | 10 | hierarchical_verilog 11 | verilog_implementation 12 | verilog_design_configuration 13 | 14 | 15 | 16 | 17 | verilog_implementation 18 | Verilog 19 | test_setup 20 | 21 | verilogSource 22 | 23 | 24 | 25 | verilog_design_configuration 26 | 27 | 28 | 29 | 30 | 31 | 32 | verilogSource 33 | generatedFiles 34 | 35 | test_setup.v 36 | verilogSource 37 | Generated at 16:08:37 on 28.11.2017 by Kactus2. 38 | 39 | 40 | 41 | Test arrangement for verifying wishbone-to-CPU bridge. 42 | 43 | 3,4,104,0 44 | 45 | IP 46 | HW 47 | Fixed 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/wb_slave.setup/1.0/wb_slave.setup.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.template.test 5 | wb_slave.setup 6 | 1.0 7 | 8 | 9 | 10 | hierarchical_verilog 11 | verilog_implementation 12 | verilog_design_configuration 13 | 14 | 15 | 16 | 17 | verilog_implementation 18 | Verilog 19 | test_setup 20 | 21 | verilogSource 22 | 23 | 24 | 25 | verilog_design_configuration 26 | 27 | 28 | 29 | 30 | 31 | 32 | verilogSource 33 | generatedFiles 34 | 35 | test_setup.v 36 | verilogSource 37 | Generated at 16:01:37 on 28.11.2017 by Kactus2. 38 | 39 | 40 | 41 | Test arrangement for verifying the wishbone slave template. 42 | 43 | 3,4,107,0 44 | 45 | IP 46 | HW 47 | Mutable 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /tut.fi/cpu.logic.test/data_memory/1.0/data_memory.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : data_memory.v 3 | // Creation date : 16.05.2017 4 | // Creation time : 10:33:36 5 | // Description : 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.106 32-bit 8 | // Plugin : Verilog generator 2.0e 9 | // This file was generated based on IP-XACT component tut.fi:cpu.logic.test:data_memory:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic.test/data_memory/1.0/data_memory.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module data_memory #( 14 | parameter DATA_WIDTH = 32, // Width for data. 15 | parameter ADDR_WIDTH = 9, // Width of the addresses. 16 | parameter MEMORY_SIZE = 128, 17 | parameter AUB = 8 18 | ) ( 19 | // Interface: slave 20 | input [ADDR_WIDTH-1:0] adr_i, 21 | input write, 22 | input [DATA_WIDTH-1:0] write_data, 23 | output reg [DATA_WIDTH-1:0] read_data, 24 | 25 | // These ports are not in any interface 26 | input clk_i, // The mandatory clock, as this is synchronous logic. 27 | input rst_i // The mandatory reset, as this is synchronous logic. 28 | ); 29 | 30 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 31 | reg [AUB-1:0] data_memory [MEMORY_SIZE-1:0]; 32 | 33 | localparam AU_IN_DATA = DATA_WIDTH/AUB; 34 | 35 | // Used to index AUBs to data io. 36 | integer index; 37 | 38 | always @(posedge clk_i or posedge rst_i) begin 39 | if(rst_i == 1'b1) begin 40 | read_data <= 0; 41 | end 42 | else begin 43 | if (adr_i < MEMORY_SIZE && adr_i >= 0) begin 44 | if (write == 1) begin 45 | // Writing: Pick every byte from the input and place them to correct addresses. 46 | for (index = 0; index < AU_IN_DATA; index = index + 1) begin 47 | data_memory[adr_i + index] <= write_data[(index*AUB)+:AUB]; 48 | end 49 | end 50 | 51 | // Reading: Pick every byte from correct addresses and place them to the output. 52 | for (index = 0; index < AU_IN_DATA; index = index + 1) begin 53 | read_data[(index*AUB)+:AUB] <= data_memory[adr_i + index]; 54 | end 55 | end 56 | end 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /tut.fi/interface/spi/1.0/spi.absDef.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | spi.absDef 6 | 1.0 7 | 8 | 9 | 10 | MISO 11 | Master input, slave output. 12 | 13 | 14 | 1 15 | in 16 | 17 | 18 | 1 19 | out 20 | 21 | 22 | 23 | 24 | MOSI 25 | Master output, slave input. 26 | 27 | 28 | 1 29 | out 30 | 31 | 32 | 1 33 | in 34 | 35 | 36 | 37 | 38 | SCLK 39 | Clock from master to slave. 40 | 41 | 42 | 1 43 | out 44 | 45 | 46 | 1 47 | in 48 | 49 | 50 | 51 | 52 | SS 53 | Slave select, may have variable number of bits. 54 | 55 | 56 | out 57 | 58 | 59 | in 60 | 61 | 62 | 63 | 64 | 65 | 3,3,515,0 66 | 67 | 68 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/wb_example.setup.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem.test 5 | wb_example.setup 6 | 1.0 7 | 8 | 9 | 10 | hierarchical_verilog 11 | verilog_implementation 12 | verilog_design_configuration 13 | 14 | 15 | 16 | 17 | verilog_implementation 18 | Verilog 19 | test_setup 20 | 21 | verilogSource 22 | 23 | 24 | 25 | verilog_design_configuration 26 | 27 | 28 | 29 | 30 | 31 | 32 | verilogSource 33 | generatedFiles 34 | 35 | hierarchical_wb_slave_0.v 36 | verilogSource 37 | Generated at 16:51:36 on 28.11.2017 by Kactus2. 38 | 39 | 40 | test_setup.v 41 | verilogSource 42 | Generated at 16:51:36 on 28.11.2017 by Kactus2. 43 | 44 | 45 | wb_example_0.v 46 | verilogSource 47 | Generated at 16:51:36 on 28.11.2017 by Kactus2. 48 | 49 | 50 | 51 | Test arrangement for verifying the wishbone example design. 52 | 53 | 3,4,107,0 54 | 55 | IP 56 | HW 57 | Fixed 58 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /tut.fi/interface/local_memory/1.1/local_memory.absDef.1.1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | local_memory.absDef 6 | 1.1 7 | 8 | 9 | 10 | address 11 | The address of write_data of the current clock cycle and read_data in the next clock cycle. 12 | 13 | 14 | required 15 | out 16 | 17 | 18 | required 19 | in 20 | 21 | 22 | 23 | 24 | read_data 25 | The contents of memory in the address of the previous cycle. 26 | 27 | 28 | optional 29 | in 30 | 31 | 32 | optional 33 | out 34 | 35 | 36 | 37 | 38 | write 39 | 1 = Write write_data, 0 = Do not write 40 | 41 | 42 | optional 43 | 1 44 | out 45 | 46 | 47 | optional 48 | 1 49 | in 50 | 51 | 0 52 | 53 | 54 | 55 | write_data 56 | The data that will be written, if enabled. 57 | 58 | 59 | optional 60 | out 61 | 62 | 63 | optional 64 | in 65 | 66 | 0 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /tut.fi/peripheral.logic/wb_dual_master/1.0/master.hh: -------------------------------------------------------------------------------- 1 | #include "header.hh" 2 | #include "systemc.h" 3 | #include "wb_master.hh" 4 | 5 | SC_MODULE (master) 6 | { 7 | sc_in_clk clk; // The mandatory clock, as this is synchronous logic. 8 | sc_in rst; // The mandatory reset, as this is synchronous logic. 9 | sc_in start; // Input used to signal that is is ok to start the masters. 10 | sc_out done; // Output used to signal that the masters are done sending. 11 | 12 | sc_out cyc_o0; // Asserted by master for transfer. 13 | sc_out stb_o0; // Asserted by master for transfer. 14 | sc_in ack_i0; // Slave asserts acknowledge. 15 | sc_out we_o0; // Write = 1, Read = 0. 16 | sc_out > dat_o0; // Data from master to slave. 17 | sc_in > dat_i0; // Data from slave to master. 18 | sc_out > adr_o0; // The address of the data 19 | 20 | sc_out cyc_o1; // Asserted by master for transfer. 21 | sc_out stb_o1; // Asserted by master for transfer. 22 | sc_in ack_i1; // Slave asserts acknowledge. 23 | sc_out we_o1; // Write = 1, Read = 0. 24 | sc_out > dat_o1; // Data from master to slave. 25 | sc_in > dat_i1; // Data from slave to master. 26 | sc_out > adr_o1; // The address of the data. 27 | 28 | sc_signal done0; 29 | sc_signal done1; 30 | 31 | wb_master* master0; 32 | wb_master* master1; 33 | 34 | void run() 35 | { 36 | while( true ) 37 | { 38 | done = done0 & done1; 39 | wait(); 40 | } 41 | } 42 | 43 | SC_CTOR(master) 44 | { 45 | master0 = new wb_master("master0"); 46 | master0->clk(clk); 47 | master0->rst(rst); 48 | master0->start(start); 49 | master0->done(done0); 50 | 51 | master0->cyc_o(cyc_o0); 52 | master0->stb_o(stb_o0); 53 | master0->ack_i(ack_i0); 54 | master0->we_o(we_o0); 55 | master0->dat_i(dat_i0); 56 | master0->dat_o(dat_o0); 57 | master0->adr_o(adr_o0); 58 | 59 | master1 = new wb_master("master1"); 60 | master1->clk(clk); 61 | master1->rst(rst); 62 | master1->start(start); 63 | master1->done(done1); 64 | 65 | master1->cyc_o(cyc_o1); 66 | master1->stb_o(stb_o1); 67 | master1->ack_i(ack_i1); 68 | master1->we_o(we_o1); 69 | master1->dat_i(dat_i1); 70 | master1->dat_o(dat_o1); 71 | master1->adr_o(adr_o1); 72 | 73 | //Initialize process as a thread, with reset active high 74 | SC_CTHREAD(run, clk.pos()); 75 | reset_signal_is(rst, false); 76 | } 77 | }; -------------------------------------------------------------------------------- /tut.fi/examples/VerilogGeneration/1.0/VerilogGeneration.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | VerilogGeneration 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the Verilog Generation video tutorial for Kactus2. The top-level component is tut.fi:other.subsystem.test:wb_example.setup:1.0. 8 | 9 | 10 | 11 | ../../../other.subsystem/wb_example.documents/1.0/wb_example.documents.1.0.xml 12 | 13 | 14 | 15 | 16 | 17 | ../../../../opencores.org/interface/wishbone/b4/wishbone.b4.xml 18 | 19 | 20 | 21 | 22 | 23 | ../../../../opencores.org/interface/wishbone/b4/wishbone.absDef.b4.xml 24 | 25 | 26 | 27 | 28 | 29 | ../../../other.subsystem.test/wb_example.bench/1.0/wb_example.bench.1.0.xml 30 | 31 | 32 | 33 | ../../../other.subsystem.test/wb_example.setup/1.0/wb_example.setup.1.0.xml 34 | 35 | 36 | 37 | ../../../other.test/clock_generator/1.1/clock_generator.1.1.xml 38 | 39 | 40 | 41 | 42 | 43 | ../../../other.subsystem.test/wb_example.setup/1.0/wb_example.setup.design.1.0.xml 44 | 45 | 46 | 47 | 48 | 49 | ../../../other.subsystem.test/wb_example.setup/1.0/wb_example.setup.verilog.designcfg.1.0.xml 50 | 51 | 52 | 53 | 3,3,279,0 54 | 55 | 56 | -------------------------------------------------------------------------------- /tut.fi/communication.template/spi_slave/1.0/spi_slave.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : spi_slave.v 3 | // Creation date : 10.04.2017 4 | // Creation time : 16:16:13 5 | // Description : A minimalistic example for SPI slave IP-XACT document. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.20 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:template:spi_slave:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/template/spi_slave/1.0/spi_slave.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module spi_slave #( 14 | parameter SLAVE_ID = 0 15 | ) ( 16 | // Interface: slave_if 17 | input clk_in, 18 | input data_in, 19 | input slave_select_in, 20 | output reg data_out, 21 | 22 | // These ports are not in any interface 23 | input rst_in // General reset, independent from master. 24 | ); 25 | 26 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 27 | 28 | localparam BYTE_SIZE = 8; // How many bits are transferred per transaction 29 | localparam BYTE_INDEX_SIZE = $clog2(BYTE_SIZE); // How many bits are needed to index a byte. 30 | 31 | // Input and output bytes. 32 | reg [BYTE_SIZE-1:0] data_recv; 33 | reg [BYTE_SIZE-1:0] data_send; 34 | 35 | // Used to iterate through the bytes. 36 | reg [BYTE_INDEX_SIZE-1:0] send_iterator; 37 | reg [BYTE_INDEX_SIZE-1:0] recv_iterator; 38 | 39 | reg transferring; 40 | reg transferred; 41 | 42 | always @(posedge clk_in or posedge rst_in) begin 43 | if(rst_in == 1'b1) begin 44 | data_recv <= 0; 45 | data_send <= 8'hAA; 46 | send_iterator <= 1; 47 | recv_iterator <= 0; 48 | data_out <= 1'bz; 49 | transferring <= 1; 50 | transferred <= 0; 51 | end 52 | else begin 53 | if (transferring == 1'b0) begin 54 | data_out <= data_send[send_iterator]; 55 | 56 | if (!transferred) begin 57 | data_recv[recv_iterator] <= data_in; 58 | recv_iterator <= recv_iterator + 1; 59 | end 60 | else 61 | data_send <= data_recv; 62 | 63 | if (send_iterator < BYTE_SIZE - 1) begin 64 | send_iterator <= send_iterator + 1; 65 | end 66 | 67 | if (recv_iterator >= BYTE_SIZE - 1) begin 68 | transferred <= 1; 69 | end 70 | end 71 | else begin 72 | if (slave_select_in == 1'b0) begin 73 | data_out <= data_send[0]; 74 | transferred <= 0; 75 | send_iterator <= 1; 76 | recv_iterator <= 0; 77 | end 78 | else begin 79 | data_out <= 1'bz; 80 | end 81 | end 82 | 83 | transferring <= slave_select_in; 84 | end 85 | end 86 | endmodule 87 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/spi_example.documents/1.0/spi_example.documents.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | spi_example.documents 6 | 1.0 7 | List of IP-XACT documents in the SPI example.The top-level component is tut.fi:other.subsystem:spi_example:1.0. 8 | 9 | 10 | 11 | ../../../interface/spi/1.0/spi.1.0.xml 12 | 13 | 14 | 15 | 16 | 17 | ../../../interface/spi/1.0/spi.absDef.1.0.xml 18 | 19 | 20 | 21 | 22 | 23 | ../../../communication.template/spi_master/1.0/spi_master.1.0.xml 24 | 25 | 26 | 27 | ../../../communication.template/spi_slave/1.0/spi_slave.1.0.xml 28 | 29 | 30 | 31 | ../../../other.subsystem/spi_example/1.0/spi_example.1.0.xml 32 | 33 | 34 | 35 | 36 | 37 | ../../../other.subsystem/spi_example/1.0/spi_example.design.1.0_adhoc.xml 38 | 39 | 40 | 41 | ../../../other.subsystem/spi_example/1.0/spi_example.design.1.0_bus.xml 42 | 43 | 44 | 45 | 46 | 47 | ../../../other.subsystem/spi_example/1.0/spi_example.designcfg.1.0_adhoc.xml 48 | 49 | 50 | 51 | ../../../other.subsystem/spi_example/1.0/spi_example.designcfg.1.0_bus.xml 52 | 53 | 54 | 55 | 3,3,318,0 56 | 57 | 58 | -------------------------------------------------------------------------------- /tut.fi/communication.bus/wishbone/1.0/wishbone_bus.hh: -------------------------------------------------------------------------------- 1 | #include "header.hh" 2 | #include "systemc.h" 3 | 4 | SC_MODULE (wishbone_bus) 5 | { 6 | sc_out cyc_i_0; // Asserted by master for transfer. 7 | sc_out stb_i_0; // Asserted, when this specific slave is selected. 8 | sc_in ack_o_0; // Slave asserts acknowledge. 9 | sc_out we_i_0; // Write = 1, Read = 0. 10 | sc_in > dat_o_0; // Data from master to slave. 11 | sc_out > dat_i_0; // Data from slave to master. 12 | sc_out > adr_i_0; // The address of the data. 13 | 14 | sc_out cyc_i_1; // Asserted by master for transfer. 15 | sc_out stb_i_1; // Asserted, when this specific slave is selected. 16 | sc_in ack_o_1; // Slave asserts acknowledge. 17 | sc_out we_i_1; // Write = 1, Read = 0. 18 | sc_in > dat_o_1; // Data from master to slave. 19 | sc_out > dat_i_1; // Data from slave to master. 20 | sc_out > adr_i_1; // The address of the data. 21 | 22 | sc_in cyc_o_master; // Asserted by master for transfer. 23 | sc_in stb_o_master; // Asserted by master for transfer. 24 | sc_out ack_i_master; // Slave asserts acknowledge. 25 | sc_in we_o_master; // Write = 1, Read = 0. 26 | sc_in > dat_o_master; // Data from master to slave. 27 | sc_out > dat_i_master; // Data from slave to master. 28 | sc_in > adr_o_master; // The address of the data 29 | 30 | void run() 31 | { 32 | // Assign most of the master outputs directly to slave inputs. 33 | adr_i_0 = adr_o_master; 34 | cyc_i_0 = cyc_o_master; 35 | dat_i_0 = dat_o_master; 36 | we_i_0 = we_o_master; 37 | 38 | adr_i_1 = adr_o_master; 39 | cyc_i_1 = cyc_o_master; 40 | dat_i_1 = dat_o_master; 41 | we_i_1 = we_o_master; 42 | 43 | // The strobes are a wee exception: It is decided based on the address, which one is active. 44 | if ( adr_o_master.read() >= SLAVE_SPLIT + BASE_ADDRESS ) 45 | { 46 | stb_i_0 = 0; 47 | stb_i_1 = stb_o_master; 48 | } 49 | else 50 | { 51 | stb_i_1 = 0; 52 | stb_i_0 = stb_o_master; 53 | } 54 | 55 | // For master inputs, outputs of the selected slave is chosen. Again, based on the address. 56 | if ( adr_o_master.read() >= SLAVE_SPLIT + BASE_ADDRESS ) 57 | { 58 | dat_i_master = dat_o_1; 59 | ack_i_master = ack_o_1; 60 | } 61 | else 62 | { 63 | dat_i_master = dat_o_0; 64 | ack_i_master = ack_o_0; 65 | } 66 | } 67 | 68 | SC_CTOR(wishbone_bus) 69 | { 70 | // Initialize process as a method. 71 | SC_METHOD(run); 72 | // Run ANY TIME ANY INPUT changes. This is module is combinatoric! 73 | sensitive << adr_o_master << cyc_o_master << dat_o_master << we_o_master << stb_o_master 74 | << dat_o_0 << ack_o_0 << dat_o_1 << ack_o_1; 75 | } 76 | }; -------------------------------------------------------------------------------- /tut.fi/cpu.logic/register_bank/1.0/register_bank.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : register_bank.v 3 | // Creation date : 16.05.2017 4 | // Creation time : 11:39:39 5 | // Description : Stores registers and the logic needed to access them. In case of multiple simultaenous writes, the one with most priority is done. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.106 32-bit 8 | // Plugin : Verilog generator 2.0e 9 | // This file was generated based on IP-XACT component tut.fi:cpu.logic:register_bank:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic/register_bank/1.0/register_bank.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module register_bank #( 14 | parameter DATA_WIDTH = 16, // Width for data in registers and instructions. 15 | parameter REGISTER_ID_WIDTH = 4, // Bits reserved for identification a single register. 16 | parameter REGISTER_COUNT = 8 // How many registers are supported in the core. 17 | ) ( 18 | // Interface: cpu_clk_sink 19 | input clk_i, // The mandatory clock, as this is synchronous logic. 20 | input rst_i, // The mandatory reset, as this is synchronous logic. 21 | 22 | // Interface: cpu_system 23 | input alu_active_i, 24 | input [DATA_WIDTH-1:0] alu_result_i, 25 | input [REGISTER_ID_WIDTH-1:0] choose_register_i1, 26 | input [REGISTER_ID_WIDTH-1:0] choose_register_i2, 27 | input [DATA_WIDTH-1:0] load_value_i, 28 | input mem_read_rdy_i, 29 | input register_active_i, 30 | input [DATA_WIDTH-1:0] register_input, 31 | output reg [DATA_WIDTH-1:0] register_output1, 32 | output reg [DATA_WIDTH-1:0] register_output2 33 | ); 34 | 35 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 36 | 37 | // The registers. 38 | reg [DATA_WIDTH-1:0] registers [REGISTER_COUNT-1:0]; 39 | // Iterator for the reset 40 | integer index; 41 | 42 | always @* begin 43 | // Select new output when ever registers are activated. 44 | register_output1 <= registers[choose_register_i1]; 45 | register_output2 <= registers[choose_register_i2]; 46 | end 47 | 48 | always @(posedge clk_i or posedge rst_i) begin 49 | if(rst_i == 1'b1) begin 50 | for (index = 0; index < REGISTER_COUNT; index = index + 1) begin 51 | registers[index] <= 0; 52 | end 53 | end 54 | else begin 55 | if (alu_active_i) begin 56 | // Alu is expected to yield a value: Save to the register. 57 | registers[choose_register_i1] <= alu_result_i; 58 | end 59 | else if (mem_read_rdy_i) begin 60 | // Alu is expected to yield a value: Save to the register. 61 | registers[choose_register_i1] <= load_value_i; 62 | end 63 | else if (register_active_i) begin 64 | // Alu is expected to yield a value: Save to the register. 65 | registers[choose_register_i1] <= register_input[DATA_WIDTH-1:0]; 66 | end 67 | end 68 | end 69 | endmodule 70 | -------------------------------------------------------------------------------- /tut.fi/cpu.logic/alu/1.0/alu.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : alu.v 3 | // Creation date : 18.04.2017 4 | // Creation time : 14:44:52 5 | // Description : 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.79 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:core:alu:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/core/alu/1.0/alu.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module alu #( 14 | parameter DATA_WIDTH = 16, // Width for data in registers and instructions. 15 | parameter ALU_OP_WIDTH = 3 // Bits reserved for identification of alu operation 16 | ) ( 17 | // Interface: cpu_system 18 | input [ALU_OP_WIDTH-1:0] alu_op_i, 19 | input [DATA_WIDTH-1:0] register_value_i1, 20 | input [DATA_WIDTH-1:0] register_value_i2, 21 | output reg [DATA_WIDTH-1:0] alu_result_o, 22 | output reg [DATA_WIDTH-1:0] alu_status_o 23 | ); 24 | 25 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 26 | // The available operations. 27 | parameter [ALU_OP_WIDTH-1:0] 28 | OP_PLUS = 3'b000, 29 | OP_MINUS = 3'b001, 30 | OP_MUL = 3'b010, 31 | OP_DIV = 3'b011, 32 | OP_CMP = 3'b100; 33 | 34 | // The available status bits. 35 | parameter [1:0] 36 | C_OUT = 2'd3, 37 | NEGATIVE = 2'd2, 38 | ZERO = 2'd1, 39 | DIV_ZERO = 2'd0; 40 | 41 | // Result of the operation. 42 | reg [DATA_WIDTH*2-1:0] operation_result; 43 | // 1 = Division with zero attempted. 44 | integer div_zero; 45 | 46 | always @* begin 47 | // By default, it did not happen. 48 | div_zero = 0; 49 | 50 | // Select a case depending on operation. Most are pretty straightforward execution. 51 | case(alu_op_i) 52 | OP_PLUS: operation_result <= register_value_i1 + register_value_i2; 53 | OP_MINUS: operation_result <= register_value_i1 - register_value_i2; 54 | OP_MUL: operation_result <= register_value_i1 * register_value_i2; 55 | OP_DIV: begin 56 | if (register_value_i2 == 0) begin 57 | // Tried division by zero. Also result is then zero. 58 | operation_result <= 0; 59 | div_zero = 1; 60 | end 61 | else begin 62 | operation_result <= register_value_i1 / register_value_i2; 63 | end 64 | end 65 | OP_CMP : operation_result <= register_value_i1 != register_value_i2; 66 | default: begin 67 | // Unsupported opcode -> Result is zero. 68 | $display("ERROR: Unknown ALU operation: %d", alu_op_i); 69 | operation_result <= 0; 70 | end 71 | endcase 72 | 73 | // Output the result. 74 | alu_result_o <= operation_result[DATA_WIDTH-1:0]; 75 | 76 | // Undefined status bits are always zero. 77 | alu_status_o[DATA_WIDTH-1:C_OUT+1] = 0; 78 | // Carry out is always the least significant overflow bit. 79 | alu_status_o[C_OUT] = operation_result[DATA_WIDTH]; 80 | // If applicable, the most significant output bit is the sign. 81 | alu_status_o[NEGATIVE] = operation_result[DATA_WIDTH-1]; 82 | // Zero bit should be obvious. 83 | alu_status_o[ZERO] = (operation_result == 0); 84 | // Division by zero is was resolved earlier. 85 | alu_status_o[DIV_ZERO] = div_zero; 86 | end 87 | endmodule 88 | -------------------------------------------------------------------------------- /tut.fi/communication.template/spi_master/1.0/spi_master.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : spi_master.v 3 | // Creation date : 10.04.2017 4 | // Creation time : 15:38:03 5 | // Description : A minimalistic example for SPI master IP-XACT document. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.20 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:template:spi_master:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/template/spi_master/1.0/spi_master.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module spi_master( 14 | // Interface: master_if 15 | input data_in, 16 | output clk_out, 17 | output reg data_out, 18 | output reg slave_select1_out, 19 | output reg slave_select2_out, 20 | output reg slave_select3_out, 21 | 22 | // These ports are not in any interface 23 | input clk_in, // The mandatory clock, as this is synchronous logic. 24 | input rst_in // The mandatory reset, as this is synchronous logic. 25 | ); 26 | 27 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 28 | 29 | localparam BYTE_SIZE = 8; // How many bits are transferred per transaction 30 | localparam BYTE_INDEX_SIZE = $clog2(BYTE_SIZE); // How many bits are needed to index a byte. 31 | 32 | // Input and output bytes. 33 | reg [BYTE_SIZE-1:0] data_recv; 34 | reg [BYTE_SIZE-1:0] data_send; 35 | 36 | // Used to iterate through the bytes. 37 | reg [BYTE_INDEX_SIZE-1:0] send_iterator; 38 | reg [BYTE_INDEX_SIZE-1:0] recv_iterator; 39 | 40 | // The state. 41 | reg [1:0] state; 42 | 43 | // The available states. 44 | parameter [1:0] 45 | S_WAIT = 2'd0, 46 | S_TRANSFER = 2'd1, 47 | S_DEASSERT = 2'd2; 48 | 49 | assign clk_out = clk_in; 50 | 51 | always @(posedge clk_in or posedge rst_in) begin 52 | if(rst_in == 1'b1) begin 53 | state <= S_WAIT; // Wait signals from the masters at reset. 54 | data_recv <= 0; 55 | data_send <= 8'h55; 56 | data_out <= 1'bz; 57 | send_iterator <= 0; 58 | recv_iterator <= 0; 59 | 60 | // These are active low -> Initiallty high. 61 | slave_select1_out <= 1; 62 | slave_select2_out <= 1; 63 | slave_select3_out <= 1; 64 | end 65 | else begin 66 | if (state == S_WAIT) begin 67 | slave_select1_out <= 0; 68 | state <= S_TRANSFER; 69 | end 70 | else if (state == S_TRANSFER) begin 71 | data_out <= data_send[send_iterator]; 72 | 73 | if (send_iterator > 0 && recv_iterator < BYTE_SIZE-1) begin 74 | data_recv[recv_iterator] <= data_in; 75 | recv_iterator = recv_iterator +1; 76 | end 77 | 78 | if (recv_iterator >= BYTE_SIZE-1) begin 79 | state <= S_DEASSERT; 80 | end 81 | else 82 | send_iterator <= send_iterator + 1; 83 | end 84 | else if (state == S_DEASSERT) begin 85 | data_recv[BYTE_SIZE-1] <= data_in; 86 | state <= S_WAIT; 87 | slave_select1_out <= 1; 88 | data_out <= 1'bz; 89 | send_iterator <= 0; 90 | recv_iterator <= 0; 91 | @(posedge clk_in); 92 | end 93 | else 94 | $display("ERROR: Unkown state: %d", state); 95 | end 96 | end 97 | endmodule 98 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/wb_example.documents/1.0/wb_example.documents.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | wb_example.documents 6 | 1.0 7 | List of IP-XACT documents in the wishbone example. The top-level component is tut.fi:other.subsystem:wb_example:1.0. 8 | 9 | 10 | 11 | ../../../../opencores.org/interface/wishbone/b4/wishbone.b4.xml 12 | 13 | 14 | 15 | 16 | 17 | ../../../../opencores.org/interface/wishbone/b4/wishbone.absDef.b4.xml 18 | 19 | 20 | 21 | 22 | 23 | ../../wb_example/1.0/wb_example.1.0.xml 24 | 25 | 26 | 27 | ../../../communication.bus/wishbone/1.0/wishbone.1.0.xml 28 | 29 | 30 | 31 | ../../../peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.1.0.xml 32 | 33 | 34 | 35 | ../../../peripheral.logic/wb_dual_master/1.0/wb_dual_master.1.0.xml 36 | 37 | 38 | 39 | ../../../communication.template/wb_slave/1.0/wb_slave.1.0.xml 40 | 41 | 42 | 43 | 44 | 45 | ../../wb_example/1.0/wb_example.design.1.0.xml 46 | 47 | 48 | 49 | ../../../peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.design.1.0.xml 50 | 51 | 52 | 53 | 54 | 55 | ../../wb_example/1.0/wb_example.verilog.designcfg.1.0.xml 56 | 57 | 58 | 59 | ../../../peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.systemc.designcfg.1.0.xml 60 | 61 | 62 | 63 | 3,4,108,0 64 | 65 | 66 | -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem/core_example.documents/1.0/core_example.documents.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.subsystem 5 | core_example.documents 6 | 1.0 7 | List of IP-XACT documents in the example cpu core. The top-level component is tut.fi:cpu.subsystem:core_example:1.0. 8 | 9 | 10 | 11 | 12 | ../../../interface/local_memory/1.1/local_memory.1.1.xml 13 | 14 | 15 | 16 | ../../../interface/peripheral_control/1.0/peripheral_control.1.0.xml 17 | 18 | 19 | 20 | 21 | 22 | ../../../interface/local_memory/1.1/local_memory.absDef.1.1.xml 23 | 24 | 25 | 26 | ../../../interface/peripheral_control/1.0/peripheral_control.absDef.1.0.xml 27 | 28 | 29 | 30 | 31 | 32 | ../../core_example/1.0/core_example.1.0.xml 33 | 34 | 35 | 36 | ../../../cpu.logic/alu/1.0/alu.1.0.xml 37 | 38 | 39 | 40 | ../../../cpu.logic/clock/1.0/clock.1.0.xml 41 | 42 | 43 | 44 | ../../../cpu.logic/instruction_decoder/1.0/instruction_decoder.1.0.xml 45 | 46 | 47 | 48 | ../../../cpu.logic/memory_controller/1.0/memory_controller.1.0.xml 49 | 50 | 51 | 52 | ../../../cpu.logic/register_bank/1.0/register_bank.1.0.xml 53 | 54 | 55 | 56 | 57 | 58 | ../../core_example/1.0/core_example.design.1.0.xml 59 | 60 | 61 | 62 | 63 | 64 | ../../core_example/1.0/core_example.verilog.designcfg.1.0.xml 65 | 66 | 67 | 68 | 3,4,108,0 69 | 70 | 71 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/test_setup.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : test_setup.v 3 | // Creation date : 28.11.2017 4 | // Creation time : 16:51:22 5 | // Description : Test arrangement for verifying the wishbone example design. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.1176 32-bit 8 | // Plugin : Verilog generator 2.1 9 | // This file was generated based on IP-XACT component tut.fi:other.subsystem.test:wb_example.setup:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/other.subsystem.test/wb_example.setup/1.0/wb_example.setup.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module test_setup(); 14 | 15 | // clock_generator_0_wb_system_to_wb_example_0_wb_system wires: 16 | wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk; 17 | wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst; 18 | 19 | // Ad-hoc wires: 20 | wire wb_example_0_start_to_wb_example_bench_0_start; 21 | wire wb_example_0_done_to_wb_example_bench_0_done; 22 | wire wb_example_bench_0_clk_i_to_clock_generator_0_clk_o; 23 | wire wb_example_bench_0_rst_i_to_clock_generator_0_rst_o; 24 | 25 | // clock_generator_0 port wires: 26 | wire clock_generator_0_clk_o; 27 | wire clock_generator_0_rst_o; 28 | // wb_example.bench_0 port wires: 29 | wire wb_example_bench_0_clk_i; 30 | wire wb_example_bench_0_done; 31 | wire wb_example_bench_0_rst_i; 32 | wire wb_example_bench_0_start; 33 | // wb_example_0 port wires: 34 | wire wb_example_0_clk_i; 35 | wire wb_example_0_done; 36 | wire wb_example_0_rst_i; 37 | wire wb_example_0_start; 38 | 39 | // clock_generator_0 assignments: 40 | assign clock_generator_0_wb_system_to_wb_example_0_wb_systemclk = clock_generator_0_clk_o; 41 | assign wb_example_bench_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o; 42 | assign clock_generator_0_wb_system_to_wb_example_0_wb_systemrst = clock_generator_0_rst_o; 43 | assign wb_example_bench_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o; 44 | // wb_example.bench_0 assignments: 45 | assign wb_example_bench_0_clk_i = wb_example_bench_0_clk_i_to_clock_generator_0_clk_o; 46 | assign wb_example_bench_0_done = wb_example_0_done_to_wb_example_bench_0_done; 47 | assign wb_example_bench_0_rst_i = wb_example_bench_0_rst_i_to_clock_generator_0_rst_o; 48 | assign wb_example_0_start_to_wb_example_bench_0_start = wb_example_bench_0_start; 49 | // wb_example_0 assignments: 50 | assign wb_example_0_clk_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemclk; 51 | assign wb_example_0_done_to_wb_example_bench_0_done = wb_example_0_done; 52 | assign wb_example_0_rst_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemrst; 53 | assign wb_example_0_start = wb_example_0_start_to_wb_example_bench_0_start; 54 | 55 | // IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1 56 | clock_generator clock_generator_0( 57 | // Interface: wb_system 58 | .clk_o (clock_generator_0_clk_o), 59 | .rst_o (clock_generator_0_rst_o)); 60 | 61 | // IP-XACT VLNV: tut.fi:other.subsystem.test:wb_example.bench:1.0 62 | TestInitializer #( 63 | .WAIT_TIME (1200)) 64 | wb_example_bench_0( 65 | // These ports are not in any interface 66 | .clk_i (wb_example_bench_0_clk_i), 67 | .done (wb_example_bench_0_done), 68 | .rst_i (wb_example_bench_0_rst_i), 69 | .start (wb_example_bench_0_start)); 70 | 71 | // IP-XACT VLNV: tut.fi:other.subsystem:wb_example:1.0 72 | wb_example_0 wb_example_0( 73 | // Interface: wb_system 74 | .clk_i (wb_example_0_clk_i), 75 | .rst_i (wb_example_0_rst_i), 76 | // These ports are not in any interface 77 | .start (wb_example_0_start), 78 | .done (wb_example_0_done)); 79 | 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /tut.fi/examples/SimulationSupport/1.0/SimulationSupport.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | examples 5 | SimulationSupport 6 | 1.0 7 | This catalog contains all the IP-XACT files used in the Simulation Support video tutorial for Kactus2. The top-level component is tut.fi:cpu.structure.test:cpu_example.setup:1.0. 8 | 9 | 10 | 11 | ../../../cpu.structure/cpu_example.documents/1.0/cpu_example.documents.1.0.xml 12 | 13 | 14 | 15 | 16 | 17 | ../../../interface/local_memory/1.1/local_memory.1.1.xml 18 | 19 | 20 | 21 | ../../../interface/spi/1.0/spi.1.0.xml 22 | 23 | 24 | 25 | 26 | 27 | ../../../interface/local_memory/1.1/local_memory.absDef.1.1.xml 28 | 29 | 30 | 31 | ../../../interface/spi/1.0/spi.absDef.1.0.xml 32 | 33 | 34 | 35 | 36 | 37 | ../../../cpu.subsystem.test/core_example.setup/1.0/core_example.setup.1.0.xml 38 | 39 | 40 | 41 | ../../../cpu.subsystem/core_example/1.0/core_example.1.0.xml 42 | 43 | 44 | 45 | ../../../cpu.logic.test/instruction_memory/1.0/instruction_memory.1.0.xml 46 | 47 | 48 | 49 | ../../../other.test/clock_generator/1.1/clock_generator.1.1.xml 50 | 51 | 52 | 53 | ../../../cpu.logic.test/data_memory/1.0/data_memory.1.0.xml 54 | 55 | 56 | 57 | 58 | 59 | ../../../cpu.subsystem.test/core_example.setup/1.0/core_example.setup.design.1.0.xml 60 | 61 | 62 | 63 | 64 | 65 | ../../../cpu.subsystem.test/core_example.setup/1.0/core_example.setup.verilog.designcfg.1.0.xml 66 | 67 | 68 | 69 | 3,4,108,0 70 | 71 | 72 | -------------------------------------------------------------------------------- /tut.fi/interface/peripheral_control/1.0/peripheral_control.absDef.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | interface 5 | peripheral_control.absDef 6 | 1.0 7 | 8 | 9 | 10 | address 11 | Target address of the transfer. 12 | 13 | 14 | true 15 | 16 | 17 | required 18 | out 19 | 20 | 21 | required 22 | in 23 | 24 | 25 | 26 | 27 | data_ms 28 | Data from controller to slave module. 29 | 30 | 31 | true 32 | 33 | 34 | required 35 | out 36 | 37 | 38 | required 39 | in 40 | 41 | 42 | 43 | 44 | data_sm 45 | Data from slave module to controller. 46 | 47 | 48 | true 49 | 50 | 51 | required 52 | in 53 | 54 | 55 | required 56 | out 57 | 58 | 59 | 60 | 61 | we 62 | 1 = Controller writes to the address. 0 = Controller reads from the address. 63 | 64 | 65 | required 66 | 1 67 | out 68 | 69 | 70 | required 71 | 1 72 | in 73 | 74 | 75 | 76 | 77 | slave_rdy 78 | Signifies that the slave has executed the transfer. 79 | 80 | 81 | required 82 | 1 83 | in 84 | 85 | 86 | required 87 | 1 88 | out 89 | 90 | 91 | 92 | 93 | master_rdy 94 | Signifies that master has provided data needed to execute the transfer. 95 | 96 | 97 | required 98 | 1 99 | out 100 | 101 | 102 | required 103 | 1 104 | in 105 | 106 | 107 | 108 | 109 | 110 | 3,4,4,0 111 | 112 | 113 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/spi.setup/1.0/spi.setup.design.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.template.test 5 | spi.setup.design 6 | 1.0 7 | 8 | 9 | spi_master_0 10 | 11 | 12 | {25e41c64-da11-48af-9f1c-0b44b312db07} 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | spi_slave_0 21 | 22 | 23 | {4abf9796-807a-490e-a798-6b5676a1fd52} 24 | 25 | 26 | 27 | 28 | clock_generator_0 29 | 30 | 31 | {3aae3c8f-f66b-4bbc-a31d-bf7e8243e10d} 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | spi_slave_0_slave_if_to_spi_master_0_master_if 43 | 44 | 45 | 46 | 47 | 48 | 49 | spi_master_0_clk_in_to_clock_generator_0_clk_o 50 | 51 | 52 | 53 | 54 | 55 | 56 | clock_generator_0_rst_o_to_spi_slave_0_rst_in 57 | 58 | 59 | 60 | 61 | 62 | 63 | clock_generator_0_rst_o_to_spi_master_0_rst_in 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 3,4,107,0 72 | 73 | HW 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/wb_slave.setup/1.0/wb_slave.setup.design.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.template.test 5 | wb_slave.setup.design 6 | 1.0 7 | 8 | 9 | wb_slave_0 10 | 11 | 12 | {bc5ec88d-3255-4bcb-b5b5-e3cd1eff7352} 13 | 14 | 15 | 16 | 17 | clock_generator_0 18 | 19 | 20 | {01af2f11-f390-442a-9aad-c5585f79abcd} 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | wb_master_0 29 | 30 | 31 | 1 32 | 33 | 34 | 35 | {b14d74fb-ab18-4961-89a9-4900b4a5a6f8} 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | wb_slave_0_wb_system_to_clock_generator_0_wb_system 47 | 48 | 49 | 50 | 51 | clock_generator_0_wb_system_to_wb_master_0_wb_system 52 | 53 | 54 | 55 | 56 | wb_master_0_wb_master_to_wb_slave_0_wb_slave 57 | 58 | 59 | 60 | 61 | 62 | 3,4,107,0 63 | 64 | HW 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | -------------------------------------------------------------------------------- /tut.fi/communication.template.test/spi.setup/1.0/test_setup.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : test_setup.v 3 | // Creation date : 28.11.2017 4 | // Creation time : 15:57:44 5 | // Description : Test arrangement for verifying the SPI examples. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.1184 32-bit 8 | // Plugin : Verilog generator 2.1 9 | // This file was generated based on IP-XACT component tut.fi:communication.template.test:spi.setup:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.template.test/spi.setup/1.0/spi.setup.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module test_setup(); 14 | 15 | // spi_slave_0_slave_if_to_spi_master_0_master_if wires: 16 | wire spi_slave_0_slave_if_to_spi_master_0_master_ifMISO; 17 | wire spi_slave_0_slave_if_to_spi_master_0_master_ifMOSI; 18 | wire spi_slave_0_slave_if_to_spi_master_0_master_ifSCLK; 19 | wire [2:0] spi_slave_0_slave_if_to_spi_master_0_master_ifSS; 20 | 21 | // Ad-hoc wires: 22 | wire spi_master_0_clk_in_to_clock_generator_0_clk_o; 23 | wire clock_generator_0_rst_o_to_spi_slave_0_rst_in; 24 | wire clock_generator_0_rst_o_to_spi_master_0_rst_in; 25 | 26 | // clock_generator_0 port wires: 27 | wire clock_generator_0_clk_o; 28 | wire clock_generator_0_rst_o; 29 | // spi_master_0 port wires: 30 | wire spi_master_0_clk_in; 31 | wire spi_master_0_clk_out; 32 | wire spi_master_0_data_in; 33 | wire spi_master_0_data_out; 34 | wire spi_master_0_rst_in; 35 | wire spi_master_0_slave_select1_out; 36 | wire spi_master_0_slave_select2_out; 37 | wire spi_master_0_slave_select3_out; 38 | // spi_slave_0 port wires: 39 | wire spi_slave_0_clk_in; 40 | wire spi_slave_0_data_in; 41 | wire spi_slave_0_data_out; 42 | wire spi_slave_0_rst_in; 43 | wire spi_slave_0_slave_select_in; 44 | 45 | // clock_generator_0 assignments: 46 | assign spi_master_0_clk_in_to_clock_generator_0_clk_o = clock_generator_0_clk_o; 47 | assign clock_generator_0_rst_o_to_spi_master_0_rst_in = clock_generator_0_rst_o; 48 | assign clock_generator_0_rst_o_to_spi_slave_0_rst_in = clock_generator_0_rst_o; 49 | // spi_master_0 assignments: 50 | assign spi_master_0_clk_in = spi_master_0_clk_in_to_clock_generator_0_clk_o; 51 | assign spi_slave_0_slave_if_to_spi_master_0_master_ifSCLK = spi_master_0_clk_out; 52 | assign spi_master_0_data_in = spi_slave_0_slave_if_to_spi_master_0_master_ifMISO; 53 | assign spi_slave_0_slave_if_to_spi_master_0_master_ifMOSI = spi_master_0_data_out; 54 | assign spi_master_0_rst_in = clock_generator_0_rst_o_to_spi_master_0_rst_in; 55 | assign spi_slave_0_slave_if_to_spi_master_0_master_ifSS[0] = spi_master_0_slave_select1_out; 56 | assign spi_slave_0_slave_if_to_spi_master_0_master_ifSS[1] = spi_master_0_slave_select2_out; 57 | assign spi_slave_0_slave_if_to_spi_master_0_master_ifSS[2] = spi_master_0_slave_select3_out; 58 | // spi_slave_0 assignments: 59 | assign spi_slave_0_clk_in = spi_slave_0_slave_if_to_spi_master_0_master_ifSCLK; 60 | assign spi_slave_0_data_in = spi_slave_0_slave_if_to_spi_master_0_master_ifMOSI; 61 | assign spi_slave_0_slave_if_to_spi_master_0_master_ifMISO = spi_slave_0_data_out; 62 | assign spi_slave_0_rst_in = clock_generator_0_rst_o_to_spi_slave_0_rst_in; 63 | assign spi_slave_0_slave_select_in = spi_slave_0_slave_if_to_spi_master_0_master_ifSS[0]; 64 | 65 | // IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1 66 | clock_generator clock_generator_0( 67 | // Interface: wb_system 68 | .clk_o (clock_generator_0_clk_o), 69 | .rst_o (clock_generator_0_rst_o)); 70 | 71 | // IP-XACT VLNV: tut.fi:communication.template:spi_master:1.0 72 | spi_master spi_master_0( 73 | // Interface: master_if 74 | .data_in (spi_master_0_data_in), 75 | .clk_out (spi_master_0_clk_out), 76 | .data_out (spi_master_0_data_out), 77 | .slave_select1_out (spi_master_0_slave_select1_out), 78 | .slave_select2_out (spi_master_0_slave_select2_out), 79 | .slave_select3_out (spi_master_0_slave_select3_out), 80 | // These ports are not in any interface 81 | .clk_in (spi_master_0_clk_in), 82 | .rst_in (spi_master_0_rst_in)); 83 | 84 | // IP-XACT VLNV: tut.fi:communication.template:spi_slave:1.0 85 | spi_slave #( 86 | .SLAVE_ID (0)) 87 | spi_slave_0( 88 | // Interface: slave_if 89 | .clk_in (spi_slave_0_clk_in), 90 | .data_in (spi_slave_0_data_in), 91 | .slave_select_in (spi_slave_0_slave_select_in), 92 | .data_out (spi_slave_0_data_out), 93 | // These ports are not in any interface 94 | .rst_in (spi_slave_0_rst_in)); 95 | 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /tut.fi/peripheral.logic/wb_dual_master/1.0/master.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : master.v 3 | // Creation date : 15.05.2017 4 | // Creation time : 11:13:06 5 | // Description : A component containing two wishbone master interfaces and thus two wishbone master module instantiations. Its operation is governed by external start signal, and will send a done signal after both master modules have sent and received everything. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.109 32-bit 8 | // Plugin : Verilog generator 2.0e 9 | // This file was generated based on IP-XACT component tut.fi:peripheral.logic:wb_dual_master:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/peripheral.logic/wb_dual_master/1.0/wb_dual_master.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module master #( 14 | parameter ADDR_WIDTH = 16, // The width of the address. 15 | parameter MASTER_1_BASE_ADDRESS = 64, // The first referred address of master1. 16 | parameter DATA_COUNT = 8, // How many values there are in the register array. 17 | parameter DATA_WIDTH = 16, // The width of the both transferred and inputted data. 18 | parameter MASTER_0_BASE_ADDRESS = 0, // The first referred address of master0. 19 | parameter AUB = 8, // Addressable unit bits of the memory. 20 | parameter VERILOG_SPECIFIC = 'hEE // A verilog specific parameter 21 | ) ( 22 | // Interface: master_0 23 | input ack_i_0, // Slave asserts acknowledge. 24 | input [DATA_WIDTH-1:0] dat_i_0, // Data from slave to master. 25 | input err_i_0, // Indicates abnormal cycle termination. 26 | output [ADDR_WIDTH-1:0] adr_o_0, // The address of the data. 27 | output cyc_o_0, // Asserted by master for transfer. 28 | output [DATA_WIDTH-1:0] dat_o_0, // Data from master to slave. 29 | output stb_o_0, // Asserted by master for transfer. 30 | output we_o_0, // Write = 1, Read = 0. 31 | 32 | // Interface: master_1 33 | input ack_i_1, // Slave asserts acknowledge. 34 | input [DATA_WIDTH-1:0] dat_i_1, // Data from slave to master. 35 | input err_i_1, // Indicates abnormal cycle termination. 36 | output [ADDR_WIDTH-1:0] adr_o_1, // The address of the data. 37 | output cyc_o_1, // Asserted by master for transfer. 38 | output [DATA_WIDTH-1:0] dat_o_1, // Data from master to slave. 39 | output stb_o_1, // Asserted by master for transfer. 40 | output we_o_1, // Write = 1, Read = 0. 41 | 42 | // Interface: wb_system 43 | input clk_i, // The mandatory clock, as this is synchronous logic. 44 | input rst_i, // The mandatory reset, as this is synchronous logic. 45 | 46 | // These ports are not in any interface 47 | input start, // Input used to signal that is is ok to start the masters. 48 | output done // Output used to signal that the masters are done sending. 49 | ); 50 | 51 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 52 | 53 | // Needs "done" from both masters. 54 | wire done_0; 55 | wire done_1; 56 | assign done = done_0 & done_1; 57 | 58 | wb_master #( 59 | .DATA_COUNT (DATA_COUNT), 60 | .BASE_ADDRESS (MASTER_0_BASE_ADDRESS), 61 | .DATA_WIDTH (DATA_WIDTH), 62 | .ADDR_WIDTH (ADDR_WIDTH)) 63 | wb_master_0( 64 | .clk_i(clk_i), 65 | .rst_i(rst_i), 66 | .cyc_o(cyc_o_0), 67 | .stb_o(stb_o_0), 68 | .ack_i(ack_i_0), 69 | .we_o(we_o_0), 70 | .dat_o(dat_o_0), 71 | .dat_i(dat_i_0), 72 | .adr_o(adr_o_0), 73 | .err_i(err_i_0), 74 | 75 | .start(start), 76 | .done(done_0) 77 | ); 78 | 79 | wb_master #( 80 | .DATA_COUNT (DATA_COUNT), 81 | .BASE_ADDRESS (MASTER_1_BASE_ADDRESS), 82 | .DATA_WIDTH (DATA_WIDTH), 83 | .ADDR_WIDTH (ADDR_WIDTH)) 84 | wb_master_1( 85 | .clk_i(clk_i), 86 | .rst_i(rst_i), 87 | .cyc_o(cyc_o_1), 88 | .stb_o(stb_o_1), 89 | .ack_i(ack_i_1), 90 | .we_o(we_o_1), 91 | .dat_o(dat_o_1), 92 | .dat_i(dat_i_1), 93 | .adr_o(adr_o_1), 94 | .err_i(err_i_1), 95 | 96 | .start(start), 97 | .done(done_1) 98 | ); 99 | endmodule 100 | -------------------------------------------------------------------------------- /tut.fi/communication.template/wb_slave/1.0/wb_slave.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : wb_slave.v 3 | // Creation date : 30.03.2017 4 | // Creation time : 12:18:42 5 | // Description : Template component for wishbone slave. Address space is assumed to be contiguous. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.6 32-bit 8 | // Plugin : Verilog generator 2.0d 9 | // This file was generated based on IP-XACT component tut.fi:ip.hw:wb_slave_template:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/ip.hw/wb_slave_template/1.0/wb_slave_template.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module wb_slave #( 14 | parameter ADDR_WIDTH = 16, // The width of the address. 15 | parameter DATA_WIDTH = 32, // The width of the both transferred and inputted data. 16 | parameter DATA_COUNT = 8, // How many values there are in the register array. 17 | parameter BASE_ADDRESS = 'h0F00 // The first referred address of the master. 18 | ) ( 19 | // Interface: wb_slave 20 | // The address of the data. 21 | input [ADDR_WIDTH-1:0] adr_i, // The address of the data. 22 | input cyc_i, // Asserted by master for transfer. 23 | input [DATA_WIDTH-1:0] dat_i, // Data from master to slave. 24 | input stb_i, // Asserted, when this specific slave is selected. 25 | input we_i, // Write = 1, Read = 0. 26 | output reg ack_o, // Slave asserts acknowledge. 27 | output reg [DATA_WIDTH-1:0] dat_o, // Data from slave to master. 28 | output reg err_o, // Indicates abnormal cycle termination. 29 | 30 | // Interface: wb_system 31 | // The mandatory clock, as this is synchronous logic. 32 | input clk_i, // The mandatory clock, as this is synchronous logic. 33 | input rst_i // The mandatory reset, as this is synchronous logic. 34 | ); 35 | 36 | // WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!! 37 | 38 | localparam AUB = 8; 39 | localparam AU_IN_DATA = DATA_WIDTH/AUB; 40 | localparam MEMORY_SIZE = DATA_COUNT*4; 41 | reg [AUB-1:0] memory [MEMORY_SIZE-1:0]; 42 | 43 | // Used to index AUBs to data io. 44 | integer index; 45 | 46 | // The state. 47 | reg [0:0] state; 48 | 49 | // The available states. 50 | parameter [0:0] 51 | S_WAIT = 1'd0, // Waiting for cyc_i & stb_i 52 | S_DEASSERT = 1'd1; // Deassert acknowledgement. 53 | 54 | always @(posedge clk_i or posedge rst_i) begin 55 | if(rst_i == 1'b1) begin 56 | ack_o <= 0; // Obviously, there is nothing to acknowledge by default. 57 | dat_o <= 0; // No output by default. 58 | err_o <= 0; // No error by default. 59 | state <= S_WAIT; // Wait signals from the masters at reset. 60 | end 61 | else begin 62 | if (state == S_WAIT) begin 63 | // Wait signal from the master. 64 | if ( cyc_i == 1 && stb_i == 1 ) begin 65 | // Master ok, check the address. 66 | if (adr_i < BASE_ADDRESS + MEMORY_SIZE && adr_i >= BASE_ADDRESS) begin 67 | // The specified address in accessible -> proceed. 68 | ack_o <= 1; 69 | 70 | if ( we_i == 1 ) begin 71 | // Writing: Pick every byte from the input and place them to correct addresses. 72 | for (index = 0; index < AU_IN_DATA; index = index + 1) begin 73 | memory[adr_i - BASE_ADDRESS + index] <= dat_i[(index*AUB)+:AUB]; 74 | end 75 | end 76 | else begin 77 | // Reading: Pick every byte from correct addresses and place them to the output. 78 | for (index = 0; index < AU_IN_DATA; index = index + 1) begin 79 | dat_o[(index*AUB)+:AUB] <= memory[adr_i - BASE_ADDRESS + index]; 80 | end 81 | end 82 | end 83 | else begin 84 | // The specified address out-of-scope -> error! 85 | err_o <= 1; 86 | end 87 | 88 | // Next thing is to deassert. 89 | state <= S_DEASSERT; 90 | end 91 | end 92 | else if (state == S_DEASSERT) begin 93 | // Deassert acknowlegement, get ready to receive next one. 94 | ack_o <= 0; 95 | err_o <= 0; 96 | state <= S_WAIT; 97 | end 98 | else 99 | $display("ERROR: Unkown state: %d", state); 100 | end 101 | end 102 | endmodule 103 | -------------------------------------------------------------------------------- /tut.fi/peripheral.logic/wb_dual_master/1.0/wb_master.cpp: -------------------------------------------------------------------------------- 1 | #include "wb_master.hh" 2 | 3 | #define S_WAIT_START 0 // Waiting for start-signal 4 | #define S_WRITE_INIT 1 // Initiating a write to slave. 5 | #define S_WAIT_WRITE_ACK 2 // Waiting ack for wrtite from slave. 6 | #define S_READ_INIT 3 // Initiating a read to slave. 7 | #define S_WAIT_READ_ACK 4 // Waiting ack for wrtite from slave. 8 | 9 | #define DATA_COUNT 16 10 | 11 | void wb_master::run() 12 | { 13 | sc_uint dat[DATA_COUNT]; 14 | 15 | // Initialize dat with data. 16 | dat[0] = 0x00000000; 17 | dat[1] = 0x11111111; 18 | dat[2] = 0x22222222; 19 | dat[3] = 0x33333333; 20 | dat[4] = 0x44444444; 21 | dat[5] = 0x55555555; 22 | dat[6] = 0x66666666; 23 | dat[7] = 0x77777777; 24 | dat[8] = 0x88888888; 25 | dat[9] = 0x99999999; 26 | dat[10] = 0xAAAAAAAA; 27 | dat[11] = 0xBBBBBBBB; 28 | dat[12] = 0xCCCCCCCC; 29 | dat[13] = 0xDDDDDDDD; 30 | dat[14] = 0xEEEEEEEE; 31 | dat[15] = 0xFFFFFFFF; 32 | 33 | // Initally waiting for start signal. 34 | int state = S_WAIT_START; 35 | // Everything else is zero. 36 | dat_o = 0; 37 | cyc_o = 0; 38 | stb_o = 0; 39 | we_o = 0; 40 | done = 0; 41 | unsigned int iterator = 0; 42 | adr_o = 0; 43 | bool start_old = 0; 44 | 45 | while( true ) 46 | { 47 | switch( state ) 48 | { 49 | case S_WAIT_START: 50 | // Wait for the falling edge of the start. 51 | if (start == 0 && start_old == 1) 52 | { 53 | // Once it has started, initiate a write. 54 | state = S_WRITE_INIT; 55 | // Nothing is done yet. 56 | done = 0; 57 | // Reset iterator, so that we may go through the array. 58 | iterator = 0; 59 | } 60 | break; 61 | case S_WRITE_INIT: 62 | // Assert signals indicating we are ready to transfer. 63 | cyc_o = 1; 64 | stb_o = 1; 65 | // We are writing to slave. 66 | we_o = 1; 67 | // Take output data from the register array. 68 | dat_o = dat[iterator]; 69 | // Offset our base address by the iterator, thus placing each iteration on separate location on slave. 70 | adr_o = iterator + BASE_ADDRESS; 71 | // Next we shall wait for acknowledgement. 72 | state = S_WAIT_WRITE_ACK; 73 | break; 74 | case S_WAIT_WRITE_ACK: 75 | if (ack_i == 1) 76 | { 77 | // Acknowledgement received! Deassert initiator signals. 78 | cyc_o = 0; 79 | stb_o = 0; 80 | we_o = 0; 81 | // Next we will read. 82 | state = S_READ_INIT; 83 | } 84 | break; 85 | case S_READ_INIT: 86 | // Assert signals indicating we are ready to transfer. 87 | cyc_o = 1; 88 | stb_o = 1; 89 | // We are reading from slave. 90 | we_o = 0; 91 | // Next we shall wait for acknowledgement. 92 | state = S_WAIT_READ_ACK; 93 | break; 94 | case S_WAIT_READ_ACK: 95 | if (ack_i == 1) 96 | { 97 | // Acknowledgement received! Deassert initiator signals. 98 | cyc_o = 0; 99 | stb_o = 0; 100 | we_o = 0; 101 | 102 | uint32_t value1 = dat_i.read(); 103 | uint32_t value2 = dat[iterator]; 104 | 105 | // It was read from the same address as was written, so it should be the same data. 106 | if (value1 != value2) 107 | { 108 | printf("ERROR: Wrong answer from slave: %X Expected: %X Iterator: %u\n", 109 | value1, value2, iterator); 110 | sc_stop(); 111 | } 112 | 113 | if (iterator == DATA_COUNT-1) 114 | { 115 | // We have gone through the whole register array, means we are done. 116 | done = 1; 117 | // But we will wait for signal to start again. 118 | state = S_WAIT_START; 119 | } 120 | else 121 | { 122 | // More data to send, means we increase iterator... 123 | iterator = iterator + 1; 124 | // ...and initiate next write. 125 | state = S_WRITE_INIT; 126 | } 127 | } 128 | break; 129 | default: 130 | printf("ERROR: Unkown state: %d\n", state); 131 | } 132 | 133 | // "New" old is the current value. 134 | start_old = start; 135 | 136 | // Proceed to the next cycle. 137 | wait(); 138 | } 139 | } 140 | -------------------------------------------------------------------------------- /tut.fi/other.test/clock_generator/1.1/clock_generator.1.1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.test 5 | clock_generator 6 | 1.1 7 | 8 | 9 | wb_system 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | rst 18 | 19 | 20 | rst_o 21 | 22 | 23 | 24 | 25 | clk 26 | 27 | 28 | clk_o 29 | 30 | 31 | 32 | 33 | 34 | 35 | ClockSource 36 | 37 | 38 | 39 | 40 | 41 | 42 | flat_verilog 43 | verilog:Kactus2: 44 | verilog_implementation 45 | 46 | 47 | 48 | 49 | verilog_implementation 50 | verilog 51 | 52 | verilogSource 53 | 54 | 55 | 56 | 57 | 58 | clk_o 59 | The generated clock. 60 | 61 | out 62 | 63 | 64 | reg 65 | 66 | 67 | 68 | 69 | 70 | rst_o 71 | The asserted reset. 72 | 73 | out 74 | 75 | 76 | reg 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | verilogSource 86 | generatedFiles 87 | 88 | clock_generator.v 89 | verilogSource 90 | Generated at 16:30:55 on 26.04.2017 by Kactus2. 91 | 92 | 93 | 94 | A clock source for simulations. Will also assert and deassert reset and terminate the simulation after WAIT_TIME has passed since the deassertion. 95 | 96 | 97 | 98 | TestIntitializer.cpp 99 | TestIntitializer.hh 100 | 101 | 102 | 103 | TestIntitializer.cpp 104 | $External$/header.hh 105 | 106 | 107 | 108 | TestIntitializer.hh 109 | $External$/systemc.h 110 | 111 | 112 | 113 | 3,0,111,0 114 | 115 | IP 116 | HW 117 | Fixed 118 | 119 | 120 | 121 | -------------------------------------------------------------------------------- /tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.design.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | communication.bridge.test 5 | wb_cpu.setup.design 6 | 1.0 7 | 8 | 9 | wb_cpu.bench_0 10 | 11 | 12 | {8b213746-9fd5-4e18-acf7-7856f432c61c} 13 | 14 | 15 | 16 | 17 | clock_generator_0 18 | 19 | 20 | {25915abb-c307-48fb-8c4d-69652d658e0a} 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | wb_master_cpu_slave_0 29 | 30 | 31 | {5c3f8e87-f4d0-4952-b8cb-af844c40fbcc} 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | wb_master_cpu_slave_0_wb_master_to_wb_cpu.bench_0_wb_slave 44 | 45 | 46 | 47 | 48 | wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_system 49 | 50 | 51 | 52 | 53 | clock_generator_0_wb_system_to_wb_cpu.bench_0_wb_system 54 | 55 | 56 | 57 | 58 | wb_master_cpu_slave_0_contoller_to_wb_cpu.bench_0_memory_interface 59 | 60 | 61 | 62 | 63 | 64 | 3,4,104,0 65 | 66 | HW 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem.test/wb_example.setup/1.0/hierarchical_wb_slave_0.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // File : hierarchical_wb_slave_0.v 3 | // Creation date : 28.11.2017 4 | // Creation time : 16:51:22 5 | // Description : A wishbone slave containing another wishbone slave, so now you can use a wishbone slave while using a wishbone slave. 6 | // Created by : TermosPullo 7 | // Tool : Kactus2 3.4.1176 32-bit 8 | // Plugin : Verilog generator 2.1 9 | // This file was generated based on IP-XACT component tut.fi:peripheral.subsystem:hierarchical_wb_slave:1.0 10 | // whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.1.0.xml 11 | //----------------------------------------------------------------------------- 12 | 13 | module hierarchical_wb_slave_0 #( 14 | parameter ADDR_WIDTH = 32, // The width of the address. 15 | parameter BASE_ADDRESS = 128, // The first referred address of the master. 16 | parameter DATA_COUNT = 8, // How many values there are in the register array. 17 | parameter DATA_WIDTH = 32 // The width of the both transferred and inputted data. 18 | ) ( 19 | // Interface: wb_slave 20 | input [31:0] adr_i, // The address of the data. 21 | input cyc_i, // Asserted by master for transfer. 22 | input [31:0] dat_i, // Data from slave to master. 23 | input stb_i, // Asserted, when this specific slave is selected. 24 | input we_i, // Write = 1, Read = 0. 25 | output ack_o, // Slave asserts acknowledge. 26 | output [31:0] dat_o, // Data from master to slave. 27 | 28 | // Interface: wb_system 29 | input clk_i, // The mandatory clock, as this is synchronous logic. 30 | input rst_i // The mandatory reset, as this is synchronous logic. 31 | ); 32 | 33 | // sub_slave_wb_system_to_wb_system wires: 34 | wire sub_slave_wb_system_to_wb_systemclk; 35 | wire sub_slave_wb_system_to_wb_systemrst; 36 | // sub_slave_wb_slave_to_wb_slave wires: 37 | wire sub_slave_wb_slave_to_wb_slaveack; 38 | wire [31:0] sub_slave_wb_slave_to_wb_slaveadr; 39 | wire sub_slave_wb_slave_to_wb_slavecyc; 40 | wire [31:0] sub_slave_wb_slave_to_wb_slavedat_ms; 41 | wire [31:0] sub_slave_wb_slave_to_wb_slavedat_sm; 42 | wire sub_slave_wb_slave_to_wb_slaveerr; 43 | wire sub_slave_wb_slave_to_wb_slavestb; 44 | wire sub_slave_wb_slave_to_wb_slavewe; 45 | 46 | // sub_slave port wires: 47 | wire sub_slave_ack_o; 48 | wire [31:0] sub_slave_adr_i; 49 | wire sub_slave_clk_i; 50 | wire sub_slave_cyc_i; 51 | wire [31:0] sub_slave_dat_i; 52 | wire [31:0] sub_slave_dat_o; 53 | wire sub_slave_err_o; 54 | wire sub_slave_rst_i; 55 | wire sub_slave_stb_i; 56 | wire sub_slave_we_i; 57 | 58 | // Assignments for the ports of the encompassing component: 59 | assign ack_o = sub_slave_wb_slave_to_wb_slaveack; 60 | assign sub_slave_wb_slave_to_wb_slaveadr[31:0] = adr_i[31:0]; 61 | assign sub_slave_wb_system_to_wb_systemclk = clk_i; 62 | assign sub_slave_wb_slave_to_wb_slavecyc = cyc_i; 63 | assign sub_slave_wb_slave_to_wb_slavedat_ms[31:0] = dat_i[31:0]; 64 | assign dat_o[31:0] = sub_slave_wb_slave_to_wb_slavedat_sm[31:0]; 65 | assign sub_slave_wb_system_to_wb_systemrst = rst_i; 66 | assign sub_slave_wb_slave_to_wb_slavestb = stb_i; 67 | assign sub_slave_wb_slave_to_wb_slavewe = we_i; 68 | 69 | // sub_slave assignments: 70 | assign sub_slave_wb_slave_to_wb_slaveack = sub_slave_ack_o; 71 | assign sub_slave_adr_i[31:0] = sub_slave_wb_slave_to_wb_slaveadr[31:0]; 72 | assign sub_slave_clk_i = sub_slave_wb_system_to_wb_systemclk; 73 | assign sub_slave_cyc_i = sub_slave_wb_slave_to_wb_slavecyc; 74 | assign sub_slave_dat_i[31:0] = sub_slave_wb_slave_to_wb_slavedat_ms[31:0]; 75 | assign sub_slave_wb_slave_to_wb_slavedat_sm[31:0] = sub_slave_dat_o[31:0]; 76 | assign sub_slave_rst_i = sub_slave_wb_system_to_wb_systemrst; 77 | assign sub_slave_stb_i = sub_slave_wb_slave_to_wb_slavestb; 78 | assign sub_slave_we_i = sub_slave_wb_slave_to_wb_slavewe; 79 | 80 | // An instantiation of the same wishbone slave as used in wb_example design. 81 | // IP-XACT VLNV: tut.fi:communication.template:wb_slave:1.0 82 | wb_slave #( 83 | .ADDR_WIDTH (32), 84 | .DATA_WIDTH (32), 85 | .DATA_COUNT (8), 86 | .BASE_ADDRESS (128)) 87 | sub_slave( 88 | // Interface: wb_slave 89 | .adr_i (sub_slave_adr_i), 90 | .cyc_i (sub_slave_cyc_i), 91 | .dat_i (sub_slave_dat_i), 92 | .stb_i (sub_slave_stb_i), 93 | .we_i (sub_slave_we_i), 94 | .ack_o (sub_slave_ack_o), 95 | .dat_o (sub_slave_dat_o), 96 | .err_o (sub_slave_err_o), 97 | // Interface: wb_system 98 | .clk_i (sub_slave_clk_i), 99 | .rst_i (sub_slave_rst_i)); 100 | 101 | 102 | endmodule 103 | -------------------------------------------------------------------------------- /tut.fi/cpu.structure/cpu_example.documents/1.0/cpu_example.documents.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.structure 5 | cpu_example.documents 6 | 1.0 7 | List of IP-XACT documents in the example cpu, along the peripherals. The top-level component is tut.fi:cpu.structure:cpu_example:1.0. 8 | 9 | 10 | 11 | 12 | ../../../cpu.subsystem/core_example.documents/1.0/core_example.documents.1.0.xml 13 | 14 | 15 | 16 | 17 | 18 | ../../../interface/spi/1.0/spi.1.0.xml 19 | 20 | 21 | 22 | ../../../../opencores.org/interface/wishbone/b4/wishbone.b4.xml 23 | 24 | 25 | 26 | ../../../interface/local_memory/1.1/local_memory.1.1.xml 27 | 28 | 29 | 30 | ../../../interface/peripheral_control/1.0/peripheral_control.1.0.xml 31 | 32 | 33 | 34 | 35 | 36 | ../../../interface/spi/1.0/spi.absDef.1.0.xml 37 | 38 | 39 | 40 | ../../../../opencores.org/interface/wishbone/b4/wishbone.absDef.b4.xml 41 | 42 | 43 | 44 | ../../../interface/local_memory/1.1/local_memory.absDef.1.1.xml 45 | 46 | 47 | 48 | ../../../interface/peripheral_control/1.0/peripheral_control.absDef.1.0.xml 49 | 50 | 51 | 52 | 53 | 54 | ../../cpu_example/1.0/cpu_example.1.0.xml 55 | 56 | 57 | 58 | ../../../communication.bridge/wb_slave_spi_master/1.0/wb_slave_spi_master.1.0.xml 59 | 60 | 61 | 62 | ../../../cpu.subsystem/core_example/1.0/core_example.1.0.xml 63 | 64 | 65 | 66 | ../../../communication.bus/wishbone/1.0/wishbone.1.0.xml 67 | 68 | 69 | 70 | ../../../peripheral.logic/sum_buffer/1.0/sum_buffer.1.0.xml 71 | 72 | 73 | 74 | ../../../peripheral.logic/wb_external_mem/1.0/wb_external_mem.1.0.xml 75 | 76 | 77 | 78 | ../../../communication.bridge/wb_master_cpu_slave/1.0/wb_master_cpu_slave.1.0.xml 79 | 80 | 81 | 82 | 83 | 84 | ../../cpu_example/1.0/cpu_example.design.1.0.xml 85 | 86 | 87 | 88 | 89 | 90 | ../../cpu_example/1.0/cpu_example.verilog.designcfg.1.0.xml 91 | 92 | 93 | 94 | 3,4,108,0 95 | 96 | 97 | -------------------------------------------------------------------------------- /tut.fi/other.subsystem/spi_example/1.0/spi_example.design.1.0_bus.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | other.subsystem 5 | spi_example.design 6 | 1.0_bus 7 | 8 | 9 | spi_master_0 10 | 11 | 12 | {c606df0e-793f-4cd8-8b96-357b585d0df1} 13 | 14 | 15 | 16 | 17 | spi_slave_0 18 | 19 | 20 | {5dd0c57c-f4d8-4336-b7b0-c5ad0bb3ed4f} 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | spi_slave_1 29 | 30 | 31 | 1 32 | 33 | 34 | 35 | {756b8b6f-4345-451e-83e3-d81b43e7fb89} 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | spi_slave_2 44 | 45 | 46 | 2 47 | 48 | 49 | 50 | {a7b77f03-94db-4cc2-8966-ea33c2fb71e0} 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | spi_master_0_master_if_to_spi_slave_0_slave_if 61 | 62 | 63 | 64 | 65 | spi_master_0_master_if_to_spi_slave_1_slave_if 66 | 67 | 68 | 69 | 70 | spi_master_0_master_if_to_spi_slave_2_slave_if 71 | 72 | 73 | 74 | 75 | 76 | 3,3,506,0 77 | 78 | HW 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | -------------------------------------------------------------------------------- /tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.design.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | peripheral.subsystem 5 | hierarchical_wb_slave.design 6 | 1.0 7 | 8 | 9 | sub_slave 10 | An instantiation of the same wishbone slave as used in wb_example design. 11 | 12 | 13 | uuid_b2a4a188_8e2a_41a0_92e6_9f68cbc52754 14 | uuid_94aa5f42_98a7_4d9a_a31b_6a3420978709 15 | uuid_c42a49ae_903e_4ac6_8421_1c89bc724d4e 16 | uuid_0bf6bb47_d25d_475a_a71a_1e9428663443 17 | 18 | 19 | 20 | {9b53ce56-eca5-44a1-b3ab-2b27a7e01c4e} 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | sub_slave_wb_system_to_wb_system 32 | 33 | 34 | 35 | 36 | sub_slave_wb_slave_to_wb_slave 37 | 38 | 39 | 40 | 41 | 42 | 43 | ADDR_WIDTH 44 | The width of the address. 45 | 16 46 | 47 | 48 | BASE_ADDRESS 49 | The first referred address of the master. 50 | 'h0F00 51 | 52 | 53 | DATA_COUNT 54 | How many values there are in the register array. 55 | 8 56 | 57 | 58 | DATA_WIDTH 59 | The width of the both transferred and inputted data. 60 | 16 61 | 62 | 63 | 64 | 3,0,114,0 65 | 66 | HW 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | bus_slave 84 | 85 | 86 | 87 | 88 | wb_slave 89 | 90 | 91 | 92 | 93 | wb_system 94 | 95 | 96 | 97 | 98 | 99 | 100 | -------------------------------------------------------------------------------- /tut.fi/cpu.subsystem.test/core_example.setup/1.0/core_example.setup.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.subsystem.test 5 | core_example.setup 6 | 1.0 7 | 8 | 9 | 10 | hierarchical_verilog 11 | verilog_implementation 12 | verilog_design_configuration 13 | 14 | 15 | 16 | 17 | verilog_implementation 18 | Verilog 19 | test_setup 20 | 21 | verilogSource 22 | 23 | 24 | 25 | verilog_design_configuration 26 | 27 | 28 | 29 | 30 | 31 | 32 | verilogSource 33 | The generated hierarchical Verilog modules used in the test arrangement. 34 | generatedFiles 35 | 36 | core_example_0.v 37 | verilogSource 38 | Generated at 12:45:35 on 28.11.2017 by Kactus2. 39 | 40 | 41 | test_setup.v 42 | verilogSource 43 | Generated at 12:45:35 on 28.11.2017 by Kactus2. 44 | 45 | 46 | 47 | testSource 48 | Contains the source code of the test programs in the custom assembly language of the tested core. 49 | 50 | src/aluProgram.asm 51 | asmSource 52 | Program containing ALU operations. 53 | 54 | dce78ae5072649227acbedc603578bb1 55 | 56 | 57 | 58 | src/branchProgram.asm 59 | asmSource 60 | Program containing loops. 61 | 62 | 30b060867936122d29983da6a107d4b0 63 | 64 | 65 | 66 | src/memoryProgram.asm 67 | asmSource 68 | Program containing memory operations. 69 | 70 | 44047942a5598072817c90c1c2bd3da5 71 | 72 | 73 | 74 | 75 | testBinary 76 | Contains the binary executables of the test programs in the custom binary format of the tested core. 77 | generatedFiles 78 | 79 | bin/aluProgram.hex 80 | user 81 | Program containing ALU operations. 82 | 83 | a035c03995f8849ec1580cecd4874501 84 | 85 | 86 | 87 | bin/branchProgram.hex 88 | user 89 | Program containing loops. 90 | 91 | d7e1582b9f4b2e445ca909b760b001ca 92 | 93 | 94 | 95 | bin/memoryProgram.hex 96 | user 97 | Program containing memory operations. 98 | 99 | a742fb641cadf08c8d655a921c492ed1 100 | 101 | 102 | 103 | 104 | Test arrangement for the example core with data memory, instuction memory and clock source. Peripheral access is unused, as it is tested in other setups. 105 | 106 | 3,4,123,0 107 | 108 | IP 109 | HW 110 | Fixed 111 | 112 | 113 | 114 | -------------------------------------------------------------------------------- /tut.fi/cpu.structure.test/cpu_example.setup/1.0/cpu_example.setup.1.0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tut.fi 4 | cpu.structure.test 5 | cpu_example.setup 6 | 1.0 7 | 8 | 9 | 10 | hierarchical_verilog 11 | verilog_implementation 12 | verilog_design_configuration 13 | 14 | 15 | 16 | 17 | verilog_implementation 18 | Verilog 19 | test_setup 20 | 21 | verilogSource 22 | 23 | 24 | 25 | verilog_design_configuration 26 | 27 | 28 | 29 | 30 | 31 | 32 | verilogSource 33 | The generated hierarchical Verilog modules used in the test arrangement. 34 | generatedFiles 35 | 36 | core_example_0.v 37 | verilogSource 38 | Generated at 16:31:25 on 28.11.2017 by Kactus2. 39 | 40 | 41 | cpu_example_0.v 42 | verilogSource 43 | Generated at 16:31:25 on 28.11.2017 by Kactus2. 44 | 45 | 46 | test_setup.v 47 | verilogSource 48 | Generated at 16:31:25 on 28.11.2017 by Kactus2. 49 | 50 | 51 | 52 | testSource 53 | Contains the source code of the test programs in the custom assembly language of the tested core. 54 | 55 | src/spiProgram.asm 56 | asmSource 57 | Program that executes an SPI transfer using the peripheral. 58 | 59 | 4448d89e1ad75a854d9c8cdcb2c30176 60 | 61 | 62 | 63 | src/storageProgram.asm 64 | asmSource 65 | Program that stores and loads from external memory. 66 | 67 | 7d0d27d297f81de5270b9b1b03c746d6 68 | 69 | 70 | 71 | src/sumProgram.asm 72 | asmSource 73 | Program that utilizes the sum accelerator. 74 | 75 | 3925ebd26b509a2494e5a1c76a97c57f 76 | 77 | 78 | 79 | 80 | testBinary 81 | Contains the binary executables of the test programs in the custom binary format of the tested core. 82 | 83 | bin/spiProgram.hex 84 | user 85 | Program that executes an SPI transfer using the peripheral. 86 | 87 | bf84e268a6194fff47b1f24dc6796637 88 | 89 | 90 | 91 | bin/storageProgram.hex 92 | user 93 | Program that stores and loads from external memory. 94 | 95 | cae2c883390274045b5ec9797539aa6a 96 | 97 | 98 | 99 | bin/sumProgram.hex 100 | user 101 | Program that utilizes the sum accelerator. 102 | 103 | 5a7071f71c980ee08e7f95c635c189eb 104 | 105 | 106 | 107 | 108 | Test arrangement for the example CPU with data memory, instuction memory, clock source, and SPI slave. 109 | 110 | 3,4,123,0 111 | 112 | IP 113 | HW 114 | Fixed 115 | 116 | 117 | 118 | --------------------------------------------------------------------------------