├── README.md ├── doc ├── riscv-privileged-20190608.pdf └── riscv-spec-20191213.pdf ├── riscv-cpu ├── RAM_1W2R.v ├── SimTop.v ├── axi_interconnect.v ├── fifo.v ├── if_axi_rw.v ├── interconnect.v ├── mem_axi_rw.v ├── mem_ctrl.v ├── riscv.v ├── riscv_adder.v ├── riscv_alu.v ├── riscv_alu_ctrl.v ├── riscv_branch.v ├── riscv_clint.v ├── riscv_csr.v ├── riscv_ctrl.v ├── riscv_define.vh ├── riscv_excep_detect_unit.v ├── riscv_ext.v ├── riscv_fwd_unit.v ├── riscv_hzd_detect_unit.v ├── riscv_imm_gen.v ├── riscv_jalr_hzd_detect_unit.v ├── riscv_load.v ├── riscv_rf.v ├── riscv_router.v ├── riscv_rs.v ├── riscv_store.v └── top_defines.v ├── src ├── riscv.sv ├── riscv_adder.sv ├── riscv_alu.sv ├── riscv_alu_ctrl.sv ├── riscv_ctrl.sv ├── riscv_define.svh ├── riscv_ext.sv ├── riscv_fwd_unit.sv ├── riscv_hzd_detect_unit.sv ├── riscv_imm_gen.sv ├── riscv_ram.sv ├── riscv_rf.sv ├── riscv_rs.sv ├── riscv_undef.svh └── vlogfiles.f └── test └── riscv_tb.sv /README.md: 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