├── Project1 ├── HyA.PNG ├── HyC.PNG ├── NTA.PNG ├── NTC.PNG ├── OrA.PNG ├── OrC.PNG ├── PRJ1.docx ├── PartA │ ├── sesc_raytrace.mipseb.HyA │ ├── sesc_raytrace.mipseb.NTA │ └── sesc_raytrace.mipseb.OrA ├── PartC │ ├── sesc_raytrace.mipseb.HyC │ ├── sesc_raytrace.mipseb.NTC │ └── sesc_raytrace.mipseb.OrC ├── PartJ │ ├── BPred.cpp │ ├── BPred.h │ ├── rt.out.Hybrid │ └── rt.out.NT ├── hybrid.PNG └── nottaken.PNG ├── Project2 ├── CacheCore.cpp ├── CacheCore.h ├── PRJ2.docx ├── SMPCache.cpp ├── SMPCache.h ├── sesc_fmm.mipseb.3CycL1 ├── sesc_fmm.mipseb.5CycL1 ├── sesc_fmm.mipseb.DMapL1 ├── sesc_fmm.mipseb.DefDM ├── sesc_fmm.mipseb.DefLRU ├── sesc_fmm.mipseb.DefNXLRU ├── sesc_fmm.mipseb.DefSmallLRU ├── sesc_fmm.mipseb.Default ├── sesc_fmm.mipseb.L1NXLRU └── sesc_fmm.mipseb.SmallL1 ├── Project3 ├── CacheCore.h ├── PRJ3.docx ├── SMPCache.cpp ├── SMPCache.h ├── SMPCacheState.h ├── sesc_lu.mipseb.Ap1 ├── sesc_lu.mipseb.Ap16 ├── sesc_lu.mipseb.Ap4 ├── sesc_lu.mipseb.Hp1 ├── sesc_lu.mipseb.Hp16 └── sesc_lu.mipseb.Hp4 └── README.md /Project1/HyA.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/HyA.PNG -------------------------------------------------------------------------------- /Project1/HyC.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/HyC.PNG -------------------------------------------------------------------------------- /Project1/NTA.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/NTA.PNG -------------------------------------------------------------------------------- /Project1/NTC.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/NTC.PNG -------------------------------------------------------------------------------- /Project1/OrA.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/OrA.PNG -------------------------------------------------------------------------------- /Project1/OrC.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/OrC.PNG -------------------------------------------------------------------------------- /Project1/PRJ1.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/PRJ1.docx -------------------------------------------------------------------------------- /Project1/PartJ/BPred.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Jose Renau 6 | Smruti Sarangi 7 | Milos Prvulovic 8 | 9 | This file is part of SESC. 10 | 11 | SESC is free software; you can redistribute it and/or modify it under the terms 12 | of the GNU General Public License as published by the Free Software Foundation; 13 | either version 2, or (at your option) any later version. 14 | 15 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 17 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 18 | 19 | You should have received a copy of the GNU General Public License along with 20 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 21 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 | */ 23 | 24 | #include 25 | #include 26 | #include 27 | #include 28 | 29 | #include "ReportGen.h" 30 | #include "BPred.h" 31 | #include "OSSim.h" 32 | #include "SescConf.h" 33 | 34 | /***************************************** 35 | * BPred 36 | */ 37 | 38 | BPred::BPred(int32_t i, int32_t fetchWidth, const char *sec, const char *name) 39 | :id(i) 40 | ,nHit("BPred(%d)_%s:nHit",i,name) 41 | ,nMiss("BPred(%d)_%s:nMiss",i,name) 42 | { 43 | // bpred4CycleAddrShift 44 | if (SescConf->checkInt(sec, "bpred4Cycle")) { 45 | SescConf->isPower2(sec, "bpred4Cycle"); 46 | SescConf->isBetween(sec, "bpred4Cycle", 1, fetchWidth); 47 | bpred4Cycle = SescConf->getInt(sec, "bpred4Cycle"); 48 | } else { 49 | bpred4Cycle = fetchWidth; 50 | } 51 | bpred4CycleAddrShift = log2i(fetchWidth/bpred4Cycle); 52 | I(bpred4CycleAddrShift>=0 && 53 | (unsigned)bpred4CycleAddrShift<=roundUpPower2((unsigned)fetchWidth)); 54 | 55 | // Energy counters 56 | if (strstr(name,"RAS")==0 && strstr(name,"BTB")==0) { 57 | // RAS and BTB have their own energy counters (do not replicate counters) 58 | 59 | char cadena[100]; 60 | 61 | sprintf(cadena, "BPred(%d)_%s",i,name); 62 | bpredEnergy = new GStatsEnergy("bpredEnergy", cadena, i, FetchPower, EnergyMgr::get("bpredEnergy",i)); 63 | } else { 64 | bpredEnergy = 0; 65 | } 66 | /****************************************************************************************************/ 67 | //My code 68 | for(index = 0; index < 3000; index++){ 69 | correct[index] = 0; 70 | Miss[index] = 0; 71 | All[index] = 0; 72 | All_ID[index] = 0; 73 | } 74 | /****************************************************************************************************/ 75 | } 76 | 77 | BPred::~BPred() 78 | { 79 | /**********************************************************************************************************************************************************************/ 80 | //My Code 81 | count_1=count_2=count_3=count_4=0; 82 | correct_1=correct_2=correct_3=count_4 = 0; 83 | uinst_1 = uinst_2 = uinst_3 = uinst_4 = 0; 84 | for(int i = 0; i < 3000; i++){ 85 | All[i] = Miss[i] + correct[i]; 86 | } 87 | 88 | for(int i = 0; i < 3000; i++){ 89 | if(All[i] < 10 && All[i] > 0){ 90 | count_1 += All[i]; 91 | correct_1 += correct[i]; 92 | uinst_1++; 93 | } 94 | if(All[i] < 100 && All[i] >= 10){ 95 | count_2 += All[i]; 96 | correct_2 += correct[i]; 97 | uinst_2++; 98 | } 99 | if(All[i] < 1000 && All[i] >= 100){ 100 | count_3 += All[i]; 101 | correct_3 += correct[i]; 102 | uinst_3++; 103 | } 104 | if(All[i] >= 1000){ 105 | count_4 += All[i]; 106 | correct_4 += correct[i]; 107 | uinst_4++; 108 | } 109 | } 110 | //if(All[0] != 0){ 111 | std::cout << "1-9 All: " << count_1 <<" Correct: " << correct_1 << " Inst Number:" << uinst_1 << std::endl; 112 | std::cout << "10-99 All: " << count_2 <<" Correct: " << correct_2 << " Inst Number:" << uinst_2<< std::endl; 113 | std::cout << "100-999 All: " << count_3 <<" Correct: " << correct_3 << " Inst Number:" << uinst_3<< std::endl; 114 | std::cout << "1000+ All: " << count_4 <<" Correct: " << correct_4 << " Inst Number:" << uinst_4<< std::endl; 115 | if(All[0] != 0) 116 | //Output the overall Accuracy, should match lable "BPred" in the report of simulator 117 | std::cout << "Accuracy : " << double((correct_1 + correct_2 + correct_3 + correct_4))/double(count_1 + count_2 + count_3 + count_4) << std::endl; 118 | std::cout << "================================================================================" << std::endl; 119 | /**********************************************************************************************************************************************************************/ 120 | if(bpredEnergy) 121 | delete bpredEnergy; 122 | } 123 | 124 | /***************************************** 125 | * RAS 126 | */ 127 | BPRas::BPRas(int32_t i, int32_t fetchWidth, const char *section) 128 | :BPred(i, fetchWidth, section,"RAS") 129 | ,RasSize(SescConf->getInt(section,"rasSize")) 130 | { 131 | char cadena[100]; 132 | 133 | sprintf(cadena, "BPred(%d)_RAS", i); 134 | rasEnergy = new GStatsEnergy("rasEnergy", cadena, i, FetchPower , EnergyMgr::get("rasEnergy",i)); 135 | 136 | // Constraints 137 | SescConf->isInt(section, "rasSize"); 138 | SescConf->isBetween(section, "rasSize", 0, 128); // More than 128??? 139 | 140 | if(RasSize == 0) { 141 | stack = 0; 142 | return; 143 | } 144 | 145 | stack = new InstID[RasSize]; 146 | I(stack); 147 | 148 | index = 0; 149 | } 150 | 151 | BPRas::~BPRas() 152 | { 153 | delete rasEnergy; 154 | delete [] stack; 155 | } 156 | 157 | PredType BPRas::predict(const Instruction *inst, InstID oracleID, bool doUpdate) 158 | { 159 | // RAS is a little bit different than other predictors because it can update 160 | // the state without knowing the oracleID. All the other predictors update the 161 | // statistics when the branch is resolved. RAS automatically updates the 162 | // tables when predict is called. The update only actualizes the statistics. 163 | 164 | if(inst->isFuncRet()) { 165 | rasEnergy->inc(); 166 | if(stack == 0) 167 | return CorrectPrediction; 168 | 169 | // I(oracleID); 170 | if (doUpdate) { 171 | index--; 172 | if( index < 0 ) 173 | index = RasSize-1; 174 | } 175 | 176 | if( stack[index] == oracleID ) 177 | return CorrectPrediction; 178 | 179 | return MissPrediction; 180 | } else if(inst->isFuncCall() && stack) { 181 | rasEnergy->inc(); 182 | 183 | if (doUpdate) { 184 | stack[index] = inst->calcNextInstID(); 185 | index++; 186 | 187 | if( index >= RasSize ) 188 | index = 0; 189 | } 190 | } 191 | 192 | return NoPrediction; 193 | } 194 | 195 | void BPRas::switchIn(Pid_t pid) 196 | { 197 | // TODO: a task spawn passes the RAS. Copy it the first time (keep 198 | // it as processor migrates?) 199 | } 200 | 201 | void BPRas::switchOut(Pid_t pid) 202 | { 203 | // read BPRas::switchIn 204 | } 205 | 206 | /***************************************** 207 | * BTB 208 | */ 209 | BPBTB::BPBTB(int32_t i, int32_t fetchWidth,const char *section, const char *name) 210 | :BPred(i, fetchWidth, section, name ? name : "BTB") 211 | { 212 | char cadena[100]; 213 | 214 | sprintf(cadena, "BPred(%d)_%s",i, name ? name : "BTB"); 215 | btbEnergy = new GStatsEnergy("btbEnergy", cadena, i, FetchPower, EnergyMgr::get("btbEnergy",i)); 216 | 217 | if( SescConf->getInt(section,"btbSize") == 0 ) { 218 | // Oracle 219 | data = 0; 220 | return; 221 | } 222 | 223 | data = BTBCache::create(section,"btb","BPred_BTB(%d):",i); 224 | I(data); 225 | } 226 | 227 | BPBTB::~BPBTB() 228 | { 229 | delete btbEnergy; 230 | if( data ) 231 | data->destroy(); 232 | } 233 | 234 | void BPBTB::updateOnly(const Instruction *inst, InstID oracleID) 235 | { 236 | if( data == 0 ) 237 | return; 238 | 239 | bool ntaken = inst->calcNextInstID() == oracleID; 240 | uint32_t key = calcInstID(inst); 241 | 242 | // Update only in taken branches 243 | if( ntaken ) 244 | return; 245 | 246 | BTBCache::CacheLine *cl = data->fillLine(key); 247 | I( cl ); 248 | 249 | cl->inst = oracleID; 250 | } 251 | 252 | PredType BPBTB::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 253 | { 254 | bool ntaken = inst->calcNextInstID() == oracleID; 255 | 256 | btbEnergy->inc(); 257 | 258 | if (data == 0) { 259 | // required when BPOracle 260 | nHit.cinc(doUpdate); 261 | 262 | I(oracleID); 263 | if (ntaken) { 264 | // Trash result because it shouldn't have reach BTB. Otherwise, the 265 | // worse the predictor, the better the results. 266 | return NoBTBPrediction; 267 | } 268 | return CorrectPrediction; 269 | } 270 | 271 | uint32_t key = calcInstID(inst); 272 | 273 | if ( ntaken || !doUpdate ) { 274 | // The branch is not taken. Do not update the cache 275 | BTBCache::CacheLine *cl = data->readLine(key); 276 | 277 | if( cl == 0 ) { 278 | nMiss.cinc(doUpdate); 279 | return NoBTBPrediction; // NoBTBPrediction because BTAC would hide the prediction 280 | } 281 | 282 | if( cl->inst == oracleID ) { 283 | nHit.cinc(doUpdate); 284 | return CorrectPrediction; 285 | } 286 | 287 | nMiss.cinc(doUpdate); 288 | return NoBTBPrediction; 289 | } 290 | 291 | I(doUpdate); 292 | 293 | // The branch is taken. Update the cache 294 | 295 | BTBCache::CacheLine *cl = data->fillLine(key); 296 | I( cl ); 297 | 298 | InstID predictID = cl->inst; 299 | cl->inst = oracleID; 300 | 301 | if( predictID == oracleID ) { 302 | nHit.inc(); 303 | return CorrectPrediction; 304 | } 305 | 306 | nMiss.inc(); 307 | return NoBTBPrediction; 308 | } 309 | 310 | 311 | void BPBTB::switchIn(Pid_t pid) 312 | { 313 | // Nothing to back (history does not work after all) 314 | } 315 | 316 | void BPBTB::switchOut(Pid_t pid) 317 | { 318 | } 319 | 320 | /***************************************** 321 | * BPOracle 322 | */ 323 | 324 | PredType BPOracle::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 325 | { 326 | bpredEnergy->inc(); 327 | 328 | if( inst->calcNextInstID() == oracleID ) 329 | return CorrectPrediction; //NT 330 | 331 | return btb.predict(inst, oracleID, doUpdate); 332 | } 333 | 334 | void BPOracle::switchIn(Pid_t pid) 335 | { 336 | // Oracle, do nothing 337 | } 338 | 339 | void BPOracle::switchOut(Pid_t pid) 340 | { 341 | } 342 | 343 | /***************************************** 344 | * BPTaken 345 | */ 346 | 347 | PredType BPTaken::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 348 | { 349 | bpredEnergy->inc(); 350 | 351 | if( inst->calcNextInstID() == oracleID ) 352 | return MissPrediction; 353 | 354 | return btb.predict(inst, oracleID, doUpdate); 355 | } 356 | 357 | void BPTaken::switchIn(Pid_t pid) 358 | { 359 | // Static prediction. Do nothing 360 | } 361 | 362 | void BPTaken::switchOut(Pid_t pid) 363 | { 364 | } 365 | 366 | /***************************************** 367 | * BPNotTaken 368 | */ 369 | 370 | PredType BPNotTaken::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 371 | { 372 | bpredEnergy->inc(); 373 | 374 | return inst->calcNextInstID() == oracleID ? CorrectPrediction : MissPrediction; 375 | } 376 | 377 | void BPNotTaken::switchIn(Pid_t pid) 378 | { 379 | // Static prediction. Do nothing 380 | } 381 | 382 | void BPNotTaken::switchOut(Pid_t pid) 383 | { 384 | } 385 | 386 | /***************************************** 387 | * BPStatic 388 | */ 389 | 390 | PredType BPStatic::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 391 | { 392 | bpredEnergy->inc(); 393 | 394 | bool ptaken = inst->guessAsTaken(); 395 | 396 | bool taken = inst->calcNextInstID() != oracleID; 397 | 398 | if( taken != ptaken) { 399 | if (doUpdate) 400 | btb.updateOnly(inst, oracleID); 401 | return MissPrediction; 402 | } 403 | 404 | return ptaken ? btb.predict(inst, oracleID, doUpdate) : CorrectPrediction; 405 | } 406 | 407 | void BPStatic::switchIn(Pid_t pid) 408 | { 409 | // Static prediction. Do nothing 410 | } 411 | 412 | void BPStatic::switchOut(Pid_t pid) 413 | { 414 | } 415 | 416 | /***************************************** 417 | * BP2bit 418 | */ 419 | 420 | BP2bit::BP2bit(int32_t i, int32_t fetchWidth, const char *section) 421 | :BPred(i, fetchWidth, section, "2bit") 422 | ,btb( i, fetchWidth, section) 423 | ,table(i,section 424 | ,SescConf->getInt(section,"size") 425 | ,SescConf->getInt(section,"bits")) 426 | { 427 | // Constraints 428 | SescConf->isInt(section, "size"); 429 | SescConf->isPower2(section, "size"); 430 | SescConf->isGT(section, "size", 1); 431 | 432 | SescConf->isBetween(section, "bits", 1, 7); 433 | 434 | // Done 435 | } 436 | 437 | PredType BP2bit::predict(const Instruction *inst, InstID oracleID, bool doUpdate) 438 | { 439 | bpredEnergy->inc(); 440 | 441 | if( inst->isBranchTaken() ) 442 | return btb.predict(inst, oracleID, doUpdate); 443 | 444 | bool taken = (inst->calcNextInstID() != oracleID); 445 | 446 | bool ptaken; 447 | if (doUpdate) 448 | ptaken = table.predict(calcInstID(inst), taken); 449 | else 450 | ptaken = table.predict(calcInstID(inst)); 451 | 452 | if( taken != ptaken ) { 453 | if (doUpdate) 454 | btb.updateOnly(inst,oracleID); 455 | return MissPrediction; 456 | } 457 | 458 | return ptaken ? btb.predict(inst, oracleID, doUpdate) : CorrectPrediction; 459 | } 460 | 461 | void BP2bit::switchIn(Pid_t pid) 462 | { 463 | // No history to backup (local predictor use no history) 464 | } 465 | 466 | void BP2bit::switchOut(Pid_t pid) 467 | { 468 | } 469 | 470 | 471 | /***************************************** 472 | * BP2level 473 | */ 474 | 475 | BP2level::BP2level(int32_t i, int32_t fetchWidth, const char *section) 476 | :BPred(i, fetchWidth, section,"2level") 477 | ,btb( i, fetchWidth, section) 478 | ,l1Size(SescConf->getInt(section,"l1Size")) 479 | ,l1SizeMask(l1Size - 1) 480 | ,historySize(SescConf->getInt(section,"historySize")) 481 | ,historyMask((1 << historySize) - 1) 482 | ,globalTable(i,section 483 | ,SescConf->getInt(section,"l2Size") 484 | ,SescConf->getInt(section,"l2Bits")) 485 | { 486 | // Constraints 487 | SescConf->isInt(section, "l1Size"); 488 | SescConf->isPower2(section, "l1Size"); 489 | SescConf->isBetween(section, "l1Size", 0, 32768); 490 | 491 | SescConf->isInt(section, "historySize"); 492 | SescConf->isBetween(section, "historySize", 1, 63); 493 | 494 | SescConf->isInt(section, "l2Size"); 495 | SescConf->isPower2(section, "l2Size"); 496 | SescConf->isBetween(section, "l2Bits", 1, 7); 497 | 498 | I((l1Size & (l1Size - 1)) == 0); 499 | 500 | historyTable = new HistoryType[l1Size]; 501 | I(historyTable); 502 | } 503 | 504 | BP2level::~BP2level() 505 | { 506 | delete historyTable; 507 | } 508 | 509 | PredType BP2level::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 510 | { 511 | bpredEnergy->inc(); 512 | 513 | if( inst->isBranchTaken() ) 514 | return btb.predict(inst, oracleID, doUpdate); 515 | 516 | bool taken = (inst->calcNextInstID() != oracleID); 517 | HistoryType iID = calcInstID(inst); 518 | ushort l1Index = iID & l1SizeMask; 519 | HistoryType l2Index = historyTable[l1Index]; 520 | 521 | // update historyTable statistics 522 | if (doUpdate) 523 | historyTable[l1Index] = ((l2Index << 1) | ((iID>>2 & 1)^(taken?1:0))) & historyMask; 524 | 525 | // calculate Table possition 526 | l2Index = ((l2Index ^ iID) & historyMask ) | (iID<getInt(section,"historySize")) 559 | ,historyMask((1 << historySize) - 1) 560 | ,globalTable(i,section 561 | ,SescConf->getInt(section,"l2Size") 562 | ,SescConf->getInt(section,"l2Bits")) 563 | ,ghr(0) 564 | ,localTable(i,section 565 | ,SescConf->getInt(section,"localSize") 566 | ,SescConf->getInt(section,"localBits")) 567 | ,metaTable(i,section 568 | ,SescConf->getInt(section,"MetaSize") 569 | ,SescConf->getInt(section,"MetaBits")) 570 | 571 | { 572 | // Constraints 573 | SescConf->isInt(section, "localSize"); 574 | SescConf->isPower2(section, "localSize"); 575 | SescConf->isBetween(section, "localBits", 1, 7); 576 | 577 | SescConf->isInt(section , "MetaSize"); 578 | SescConf->isPower2(section , "MetaSize"); 579 | SescConf->isBetween(section , "MetaBits", 1, 7); 580 | 581 | SescConf->isInt(section, "historySize"); 582 | SescConf->isBetween(section, "historySize", 1, 63); 583 | 584 | SescConf->isInt(section, "l2Size"); 585 | SescConf->isPower2(section, "l2Size"); 586 | SescConf->isBetween(section,"l2Bits", 1, 7); 587 | 588 | } 589 | 590 | BPHybrid::~BPHybrid() 591 | { 592 | } 593 | 594 | PredType BPHybrid::predict(const Instruction *inst, InstID oracleID, bool doUpdate) 595 | { 596 | bpredEnergy->inc(); 597 | 598 | if( inst->isBranchTaken() ) 599 | return btb.predict(inst, oracleID, doUpdate); 600 | 601 | bool taken = (inst->calcNextInstID() != oracleID); 602 | HistoryType iID = calcInstID(inst); 603 | HistoryType l2Index = ghr; 604 | 605 | // update historyTable statistics 606 | if (doUpdate) { 607 | ghr = ((ghr << 1) | ((iID>>2 & 1)^(taken?1:0))) & historyMask; 608 | } 609 | 610 | // calculate Table possition 611 | l2Index = ((l2Index ^ iID) & historyMask ) | (iID<getInt(section,"BIMSize")) 671 | ,G0(i,section,SescConf->getInt(section,"G0Size")) 672 | ,G0HistorySize(SescConf->getInt(section,"G0HistorySize")) 673 | ,G0HistoryMask((1 << G0HistorySize) - 1) 674 | ,G1(i,section,SescConf->getInt(section,"G1Size")) 675 | ,G1HistorySize(SescConf->getInt(section,"G1HistorySize")) 676 | ,G1HistoryMask((1 << G1HistorySize) - 1) 677 | ,metaTable(i,section,SescConf->getInt(section,"MetaSize")) 678 | ,MetaHistorySize(SescConf->getInt(section,"MetaHistorySize")) 679 | ,MetaHistoryMask((1 << MetaHistorySize) - 1) 680 | { 681 | // Constraints 682 | SescConf->isInt(section , "BIMSize"); 683 | SescConf->isPower2(section , "BIMSize"); 684 | SescConf->isGT(section , "BIMSize", 1); 685 | 686 | SescConf->isInt(section , "G0Size"); 687 | SescConf->isPower2(section , "G0Size"); 688 | SescConf->isGT(section , "G0Size", 1); 689 | 690 | SescConf->isInt(section , "G0HistorySize"); 691 | SescConf->isBetween(section , "G0HistorySize", 1, 63); 692 | 693 | SescConf->isInt(section , "G1Size"); 694 | SescConf->isPower2(section , "G1Size"); 695 | SescConf->isGT(section , "G1Size", 1); 696 | 697 | SescConf->isInt(section , "G1HistorySize"); 698 | SescConf->isBetween(section , "G1HistorySize", 1, 63); 699 | 700 | SescConf->isInt(section , "MetaSize"); 701 | SescConf->isPower2(section , "MetaSize"); 702 | SescConf->isGT(section , "MetaSize", 1); 703 | 704 | SescConf->isInt(section , "MetaHistorySize"); 705 | SescConf->isBetween(section , "MetaHistorySize", 1, 63); 706 | 707 | history = 0x55555555; 708 | } 709 | 710 | BP2BcgSkew::~BP2BcgSkew() 711 | { 712 | // Nothing? 713 | } 714 | 715 | 716 | PredType BP2BcgSkew::predict(const Instruction * inst, InstID oracleID, bool doUpdate) 717 | { 718 | bpredEnergy->inc(); 719 | 720 | if (inst->isBranchTaken()) 721 | return btb.predict(inst, oracleID, doUpdate); 722 | 723 | HistoryType iID = calcInstID(inst); 724 | 725 | bool taken = (inst->calcNextInstID() != oracleID); 726 | 727 | HistoryType xorKey1 = history^iID; 728 | HistoryType xorKey2 = history^(iID>>2); 729 | HistoryType xorKey3 = history^(iID>>4); 730 | 731 | HistoryType metaIndex = (xorKey1 & MetaHistoryMask) | iID<= 2; 742 | 743 | bool ptaken = metaOut ? BIMOut : gskewOut; 744 | 745 | if (ptaken != taken) { 746 | if (!doUpdate) 747 | return MissPrediction; 748 | 749 | BIM.predict(iID,taken); 750 | G0.predict(G0Index,taken); 751 | G1.predict(G1Index,taken); 752 | 753 | BIMOut = BIM.predict(iID); 754 | G0Out = G0.predict(G0Index); 755 | G1Out = G1.predict(G1Index); 756 | 757 | gskewOut = (G0Out?1:0) + (G1Out?1:0) + (BIMOut?1:0) >= 2; 758 | if (BIMOut != gskewOut) 759 | metaTable.predict(metaIndex,(BIMOut == taken)); 760 | else 761 | metaTable.reset(metaIndex,(BIMOut == taken)); 762 | 763 | I(doUpdate); 764 | btb.updateOnly(inst, oracleID); 765 | return MissPrediction; 766 | } 767 | 768 | if (doUpdate) { 769 | if (metaOut) { 770 | BIM.predict(iID,taken); 771 | } else { 772 | if (BIMOut == taken) 773 | BIM.predict(iID,taken); 774 | if (G0Out == taken) 775 | G0.predict(G0Index,taken); 776 | if (G1Out == taken) 777 | G1.predict(G1Index,taken); 778 | } 779 | 780 | if (BIMOut != gskewOut) 781 | metaTable.predict(metaIndex,(BIMOut == taken)); 782 | 783 | history = history<<1 | ((iID>>2 & 1)^(taken?1:0)); 784 | } 785 | 786 | return ptaken ? btb.predict(inst, oracleID, doUpdate) : CorrectPrediction; 787 | } 788 | 789 | void BP2BcgSkew::switchIn(Pid_t pid) 790 | { 791 | } 792 | 793 | void BP2BcgSkew::switchOut(Pid_t pid) 794 | { 795 | } 796 | 797 | /***************************************** 798 | * YAGS 799 | * 800 | * Based on: 801 | * 802 | * "The YAGS Brnach Prediction Scheme" by A. N. Eden and T. Mudge 803 | * 804 | * Arguments to the predictor: 805 | * type = "yags" 806 | * l1size = (in power of 2) Taken Cache Size. 807 | * l2size = (in power of 2) Not-Taken Cache Size. 808 | * l1bits = Number of bits for Cache Taken Table counter (2). 809 | * l2bits = Number of bits for Cache NotTaken Table counter (2). 810 | * size = (in power of 2) Size of the Choice predictor. 811 | * bits = Number of bits for Choice predictor Table counter (2). 812 | * tagbits = Number of bits used for storing the address in 813 | * direction cache. 814 | * 815 | * Description: 816 | * 817 | * This predictor tries to address the conflict aliasing in the choice 818 | * predictor by having two direction caches. Depending on the 819 | * prediction, the address is looked up in the opposite direction and if 820 | * there is a cache hit then that predictor is used otherwise the choice 821 | * predictor is used. The choice predictor and the direction predictor 822 | * used are updated based on the outcome. 823 | * 824 | */ 825 | 826 | BPyags::BPyags(int32_t i, int32_t fetchWidth, const char *section) 827 | :BPred(i, fetchWidth, section, "yags") 828 | ,btb( i, fetchWidth, section) 829 | ,historySize(24) 830 | ,historyMask((1 << 24) - 1) 831 | ,table(i,section 832 | ,SescConf->getInt(section,"size") 833 | ,SescConf->getInt(section,"bits")) 834 | ,ctableTaken(i,section 835 | ,SescConf->getInt(section,"l1size") 836 | ,SescConf->getInt(section,"l1bits")) 837 | ,ctableNotTaken(i,section 838 | ,SescConf->getInt(section,"l2size") 839 | ,SescConf->getInt(section,"l2bits")) 840 | { 841 | // Constraints 842 | SescConf->isInt(section, "size"); 843 | SescConf->isPower2(section, "size"); 844 | SescConf->isGT(section, "size", 1); 845 | 846 | SescConf->isBetween(section, "bits", 1, 7); 847 | 848 | SescConf->isInt(section, "l1size"); 849 | SescConf->isPower2(section, "l1bits"); 850 | SescConf->isGT(section, "l1size", 1); 851 | 852 | SescConf->isBetween(section, "l1bits", 1, 7); 853 | 854 | SescConf->isInt(section, "l2size"); 855 | SescConf->isPower2(section, "l2bits"); 856 | SescConf->isGT(section, "size", 1); 857 | 858 | SescConf->isBetween(section, "l2bits", 1, 7); 859 | 860 | SescConf->isBetween(section, "tagbits", 1, 7); 861 | 862 | CacheTaken = new uchar[SescConf->getInt(section,"l1size")]; 863 | CacheTakenMask = SescConf->getInt(section,"l1size") - 1; 864 | CacheTakenTagMask = (1 << SescConf->getInt(section,"tagbits")) - 1; 865 | 866 | CacheNotTaken = new uchar[SescConf->getInt(section,"l2size")]; 867 | CacheNotTakenMask = SescConf->getInt(section,"l2size") - 1; 868 | CacheNotTakenTagMask = (1 << SescConf->getInt(section,"tagbits")) - 1; 869 | 870 | // Done 871 | } 872 | 873 | BPyags::~BPyags() 874 | { 875 | 876 | } 877 | 878 | PredType BPyags::predict(const Instruction *inst, InstID oracleID,bool doUpdate) 879 | { 880 | bpredEnergy->inc(); 881 | 882 | if( inst->isBranchTaken() ) 883 | return btb.predict(inst, oracleID, doUpdate); 884 | 885 | bool taken = (inst->calcNextInstID() != oracleID); 886 | HistoryType iID = calcInstID(inst); 887 | HistoryType iIDHist = ghr; 888 | 889 | 890 | bool choice; 891 | if (doUpdate) { 892 | ghr = ((ghr << 1) | ((iID>>2 & 1)^(taken?1:0))) & historyMask; 893 | choice = table.predict(iID, taken); 894 | } else 895 | choice = table.predict(iID); 896 | 897 | iIDHist = ((iIDHist ^ iID) & historyMask ) | (iID<getInt(section,"mtables")) 975 | ,glength(200) 976 | ,nentry(3) 977 | ,addwidth(8) 978 | ,logpred(log2i(SescConf->getInt(section,"tsize"))) 979 | ,THETA(SescConf->getInt(section,"mtables")) 980 | ,MAXTHETA(31) 981 | ,THETAUP(1 << (SescConf->getInt(section,"tcbits") - 1)) 982 | ,PREDUP(1 << (SescConf->getInt(section,"tbits") - 1)) 983 | ,TC(0) 984 | { 985 | SescConf->isInt(section, "tsize"); 986 | SescConf->isPower2(section, "tsize"); 987 | SescConf->isGT(section, "tsize", 1); 988 | SescConf->isBetween(section, "tbits", 1, 15); 989 | SescConf->isBetween(section, "tcbits", 1, 15); 990 | SescConf->isBetween(section, "mtables", 6, 32); 991 | 992 | pred = new char*[M_SIZ]; 993 | for (int32_t i = 0; i < M_SIZ; i++) { 994 | pred[i] = new char[1 << logpred]; 995 | for (int32_t j = 0; j < (1 << logpred); j++) 996 | pred[i][j] = 0; 997 | } 998 | 999 | T = new int[nentry * logpred + 1]; 1000 | ghist = new long long[(glength >> 6) + 1]; 1001 | MINITAG = new char[(1 << (logpred - 1))]; 1002 | 1003 | for (int32_t i = 0; i < (glength >> 6) + 1; i++) 1004 | ghist[i] = 0; 1005 | phist = 0; 1006 | 1007 | for (int32_t j = 0; j < (1 << (logpred - 1)); j++) 1008 | MINITAG[j] = 0; 1009 | AC=0; 1010 | 1011 | double initset = 3; 1012 | double tt = ((double)glength) / initset; 1013 | double Pow = pow(tt, 1.0/(M_SIZ + 1)); 1014 | 1015 | histLength = new int[M_SIZ + 3]; 1016 | usedHistLength = new int[M_SIZ]; 1017 | histLength[0] = 0; 1018 | histLength[1] = 3; 1019 | for (int32_t i = 2; i < M_SIZ + 3; i++) 1020 | histLength[i] = (int) ((initset * pow (Pow, (double) (i - 1))) + 0.5); 1021 | for (int32_t i = 0; i < M_SIZ; i++) { 1022 | usedHistLength[i] = histLength[i]; 1023 | } 1024 | } 1025 | 1026 | BPOgehl::~BPOgehl() 1027 | { 1028 | } 1029 | 1030 | PredType BPOgehl::predict(const Instruction *inst, InstID oracleID, bool doUpdate) 1031 | { 1032 | bpredEnergy->inc(); 1033 | 1034 | if( inst->isBranchTaken() ) 1035 | return btb.predict(inst, oracleID, doUpdate); 1036 | 1037 | bool taken = (inst->calcNextInstID() != oracleID); 1038 | bool ptaken = false; 1039 | 1040 | int32_t S = (M_SIZ/2); 1041 | HistoryType *iID = (HistoryType *)alloca(M_SIZ*sizeof(HistoryType)); 1042 | 1043 | // Prediction is sum of entries in M tables (table 1 is half-size to fit in 64k) 1044 | for (int32_t i = 0; i < M_SIZ; i++) { 1045 | if (i == 1) 1046 | logpred--; 1047 | iID[i] = geoidx(inst->currentID(), ghist, phist, usedHistLength[i], (i & 3) + 1); 1048 | if (i == 1) 1049 | logpred++; 1050 | S += pred[i][iID[i]]; 1051 | } 1052 | ptaken = (S >= 0); 1053 | 1054 | if( doUpdate ) { 1055 | 1056 | // Update theta (threshold) 1057 | if (taken != ptaken) { 1058 | TC++; 1059 | if (TC > THETAUP - 1) { 1060 | TC = THETAUP - 1; 1061 | if (THETA < MAXTHETA) { 1062 | TC = 0; 1063 | THETA++; 1064 | } 1065 | } 1066 | } else if (S < THETA && S >= -THETA) { 1067 | TC--; 1068 | if (TC < -THETAUP) { 1069 | TC = -THETAUP; 1070 | if (THETA > 0) { 1071 | TC = 0; 1072 | THETA--; 1073 | } 1074 | } 1075 | } 1076 | 1077 | if( taken != ptaken || (S < THETA && S >= -THETA)) { 1078 | 1079 | // Update M tables 1080 | for (int32_t i = 0; i < M_SIZ; i++) { 1081 | if (taken) { 1082 | if (pred[i][iID[i]] < PREDUP - 1) 1083 | pred[i][iID[i]]++; 1084 | } else { 1085 | if (pred[i][iID[i]] > -PREDUP) 1086 | pred[i][iID[i]]--; 1087 | } 1088 | } 1089 | btb.updateOnly(inst,oracleID); 1090 | 1091 | // Update history lengths 1092 | if ((iID[M_SIZ - 1] & 1) == 0) { 1093 | if (taken != ptaken) { 1094 | miniTag = MINITAG[iID[M_SIZ - 1] >> 1]; 1095 | if (miniTag != ((int)(inst->currentID() & 1))) { 1096 | AC -= 4; 1097 | if (AC < -256) { 1098 | AC = -256; 1099 | usedHistLength[6] = histLength[6]; 1100 | usedHistLength[4] = histLength[4]; 1101 | usedHistLength[2] = histLength[2]; 1102 | } 1103 | } else { 1104 | AC++; 1105 | if (AC > 256 - 1) { 1106 | AC = 256 - 1; 1107 | usedHistLength[6] = histLength[M_SIZ + 2]; 1108 | usedHistLength[4] = histLength[M_SIZ + 1]; 1109 | usedHistLength[2] = histLength[M_SIZ]; 1110 | } 1111 | } 1112 | } 1113 | MINITAG[iID[M_SIZ - 1] >> 1] = (char) (inst->currentID() & 1); 1114 | } 1115 | } 1116 | 1117 | // Update branch/path histories 1118 | phist = (phist << 1) + (inst->currentID() & 1); 1119 | for (int32_t i = (glength >> 6); i > 0; i--) 1120 | ghist[i] = (ghist[i] << 1) + (ghist[i - 1] < 0); 1121 | ghist[0] = ghist[0] << 1; 1122 | if (taken) 1123 | ghist[0]++; 1124 | } 1125 | 1126 | if (taken != ptaken) 1127 | return MissPrediction; 1128 | 1129 | return ptaken ? btb.predict(inst, oracleID, doUpdate) : CorrectPrediction; 1130 | } 1131 | 1132 | int32_t BPOgehl::geoidx(long long Add, long long *histo, long long phisto, int32_t m, int32_t funct) 1133 | { 1134 | long long inter, Hh, Res; 1135 | int32_t x, i, shift; 1136 | int32_t PT; 1137 | int32_t MinAdd; 1138 | int32_t FUNCT; 1139 | int32_t plength; 1140 | 1141 | if (m < 16) 1142 | plength = m; 1143 | else 1144 | plength = 16; 1145 | MinAdd = nentry * logpred - m - plength; 1146 | if (MinAdd > 20) 1147 | MinAdd = 20; 1148 | 1149 | if (MinAdd >= 8) { 1150 | inter = 1151 | ((histo[0] & ((1 << m) - 1)) << (MinAdd + plength)) + 1152 | ((Add & ((1 << MinAdd) - 1)) << plength) + 1153 | ((phisto & ((1 << plength) - 1))); 1154 | } else { 1155 | for (x = 0; x < nentry * logpred; x++) { 1156 | T[x] = ((x * (addwidth + m + plength - 1)) / (nentry * logpred - 1)); 1157 | } 1158 | 1159 | T[nentry * logpred] = addwidth + m + plength; 1160 | inter = 0; 1161 | 1162 | Hh = histo[0]; 1163 | Hh >>= T[0]; 1164 | inter = (Hh & 1); 1165 | PT = 1; 1166 | 1167 | for (i = 1; T[i] < m; i++) { 1168 | if ((T[i] & 0xffc0) == (T[i - 1] & 0xffc0)) { 1169 | shift = T[i] - T[i - 1]; 1170 | } else { 1171 | Hh = histo[PT]; 1172 | PT++; 1173 | shift = T[i] & 63; 1174 | } 1175 | 1176 | inter = (inter << 1); 1177 | Hh = Hh >> shift; 1178 | inter ^= (Hh & 1); 1179 | } 1180 | 1181 | Hh = Add; 1182 | for (; T[i] < m + addwidth; i++) { 1183 | shift = T[i] - m; 1184 | inter = (inter << 1); 1185 | inter ^= ((Hh >> shift) & 1); 1186 | } 1187 | 1188 | Hh = phisto; 1189 | for (; T[i] < m + plength + addwidth; i++) { 1190 | shift = T[i] - (m + addwidth); 1191 | inter = (inter << 1); 1192 | inter ^= ((Hh >> shift) & 1); 1193 | } 1194 | } 1195 | 1196 | FUNCT = funct; 1197 | Res = inter & ((1 << logpred) - 1); 1198 | for (i = 1; i < nentry; i++) { 1199 | inter = inter >> logpred; 1200 | Res ^= 1201 | ((inter & ((1 << logpred) - 1)) >> FUNCT) ^ 1202 | ((inter & ((1 << FUNCT) - 1)) << ((logpred - FUNCT))); 1203 | FUNCT = (FUNCT + 1) % logpred; 1204 | } 1205 | 1206 | return ((int) Res); 1207 | } 1208 | 1209 | void BPOgehl::switchIn(Pid_t pid) 1210 | { 1211 | } 1212 | 1213 | void BPOgehl::switchOut(Pid_t pid) 1214 | { 1215 | } 1216 | 1217 | /***************************************** 1218 | * BPredictor 1219 | */ 1220 | 1221 | 1222 | BPred *BPredictor::getBPred(int32_t id, int32_t fetchWidth, const char *sec) 1223 | { 1224 | BPred *pred=0; 1225 | 1226 | const char *type = SescConf->getCharPtr(sec, "type"); 1227 | // Normal Predictor 1228 | if (strcasecmp(type, "oracle") == 0) { 1229 | pred = new BPOracle(id, fetchWidth, sec); 1230 | } else if (strcasecmp(type, "NotTaken") == 0) { 1231 | pred = new BPNotTaken(id, fetchWidth, sec); 1232 | } else if (strcasecmp(type, "Taken") == 0) { 1233 | pred = new BPTaken(id, fetchWidth, sec); 1234 | } else if (strcasecmp(type, "2bit") == 0) { 1235 | pred = new BP2bit(id, fetchWidth, sec); 1236 | } else if (strcasecmp(type, "2level") == 0) { 1237 | pred = new BP2level(id, fetchWidth, sec); 1238 | } else if (strcasecmp(type, "Static") == 0) { 1239 | pred = new BPStatic(id, fetchWidth, sec); 1240 | } else if (strcasecmp(type, "2BcgSkew") == 0) { 1241 | pred = new BP2BcgSkew(id, fetchWidth, sec); 1242 | } else if (strcasecmp(type, "Hybrid") == 0) { 1243 | pred = new BPHybrid(id, fetchWidth, sec); 1244 | } else if (strcasecmp(type, "yags") == 0) { 1245 | pred = new BPyags(id, fetchWidth, sec); 1246 | } else if (strcasecmp(type, "ogehl") == 0) { 1247 | pred = new BPOgehl(id, fetchWidth, sec); 1248 | } else { 1249 | MSG("BPredictor::BPredictor Invalid branch predictor type [%s] in section [%s]", type,sec); 1250 | exit(0); 1251 | } 1252 | I(pred); 1253 | return pred; 1254 | } 1255 | 1256 | BPredictor::BPredictor(int32_t i, int32_t fetchWidth, const char *sec, BPredictor *bpred) 1257 | :id(i) 1258 | ,SMTcopy(bpred != 0) 1259 | ,ras(i, fetchWidth, sec) 1260 | ,nBranches("BPred(%d):nBranches", i) 1261 | ,nTaken("BPred(%d):nTaken", i) 1262 | ,nMiss("BPred(%d):nMiss", i) 1263 | ,section(strdup(sec ? sec : "null" )) 1264 | { 1265 | 1266 | // Threads in SMT system share the predictor. Only the Ras is duplicated 1267 | if (bpred) 1268 | pred = bpred->pred; 1269 | else 1270 | pred = getBPred(id, fetchWidth, section); 1271 | } 1272 | 1273 | BPredictor::~BPredictor() 1274 | { 1275 | dump(section); 1276 | 1277 | if (!SMTcopy) 1278 | delete pred; 1279 | 1280 | free(section); 1281 | } 1282 | 1283 | void BPredictor::dump(const char *str) const 1284 | { 1285 | // nothing? 1286 | } 1287 | -------------------------------------------------------------------------------- /Project1/PartJ/BPred.h: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Jose Renau 6 | Smruti Sarangi 7 | Milos Prvulovic 8 | 9 | This file is part of SESC. 10 | 11 | SESC is free software; you can redistribute it and/or modify it under the terms 12 | of the GNU General Public License as published by the Free Software Foundation; 13 | either version 2, or (at your option) any later version. 14 | 15 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 17 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 18 | 19 | You should have received a copy of the GNU General Public License along with 20 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 21 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 | */ 23 | 24 | #ifndef BPRED_H 25 | #define BPRED_H 26 | 27 | /* 28 | * The original Branch predictor code was inspired in simplescalar-3.0, but 29 | * heavily modified to make it more OOO. Now, it supports more branch predictors 30 | * that the standard simplescalar distribution. 31 | * 32 | * Supported branch predictors models: 33 | * 34 | * Oracle, NotTaken, Taken, 2bit, 2Level, 2BCgSkew 35 | * 36 | */ 37 | 38 | #include "nanassert.h" 39 | #include "estl.h" 40 | 41 | #include "GStats.h" 42 | #include "libll/Instruction.h" // InstID 43 | #include "CacheCore.h" 44 | #include "EnergyMgr.h" 45 | #include "SCTable.h" 46 | 47 | #define RAP_T_NT_ONLY 1 48 | 49 | enum PredType { 50 | CorrectPrediction = 0, 51 | NoPrediction, 52 | NoBTBPrediction, 53 | MissPrediction 54 | }; 55 | 56 | class BPred { 57 | public: 58 | typedef unsigned long long HistoryType; 59 | class Hash4HistoryType { 60 | public: 61 | size_t operator()(const HistoryType &addr) const { 62 | return ((addr) ^ (addr>>16)); 63 | } 64 | }; 65 | 66 | protected: 67 | const int32_t id; 68 | 69 | GStatsCntr nHit; // N.B. predictors should not update these counters directly 70 | GStatsCntr nMiss; // in their predict() function. 71 | /****************************************************************************************************/ 72 | //My para 73 | uint index; 74 | uint count_1; 75 | uint count_2; 76 | uint count_3; 77 | uint count_4; 78 | uint correct_1; 79 | uint correct_2; 80 | uint correct_3; 81 | uint correct_4; 82 | uint uinst_1; 83 | uint uinst_2; 84 | uint uinst_3; 85 | uint uinst_4; 86 | uint correct[3000]; 87 | uint All[3000]; 88 | uint Miss[3000]; 89 | InstID All_ID[3000]; 90 | /****************************************************************************************************/ 91 | GStatsEnergy *bpredEnergy; 92 | int32_t bpred4Cycle; 93 | int32_t bpred4CycleAddrShift; 94 | 95 | HistoryType calcInstID(const Instruction *inst) const { 96 | HistoryType cid = inst->currentID(); // psudo-PC works, no need addr (slower) 97 | 98 | // Remove used bits (restrict predictions per cycle) 99 | cid = cid>>bpred4CycleAddrShift; 100 | // randomize it 101 | cid = (cid >> 17) ^ (cid); 102 | 103 | return cid; 104 | } 105 | protected: 106 | public: 107 | BPred(int32_t i, int32_t fetchWidth, const char *section, const char *name); 108 | virtual ~BPred(); 109 | 110 | // If oracleID is not passed, the predictor is not updaed 111 | virtual PredType predict(const Instruction *inst, InstID oracleID, bool doUpdate) = 0; 112 | 113 | PredType doPredict(const Instruction *inst, InstID oracleID, bool doUpdate) { 114 | PredType pred = predict(inst, oracleID, doUpdate); 115 | if (!doUpdate || pred == NoPrediction) 116 | return pred; 117 | 118 | nHit.cinc(pred == CorrectPrediction); 119 | nMiss.cinc(pred != CorrectPrediction); 120 | /****************************************************************************************************/ 121 | //My code 122 | for(int i = 0; i < 2500; i++){ 123 | //Old IDS 124 | if(All_ID[i] == inst->currentID()){ 125 | if(pred != CorrectPrediction) 126 | Miss[i]++; 127 | if(pred == CorrectPrediction) 128 | correct[i]++; 129 | break; 130 | } 131 | //New ID 132 | else if(All_ID[i] == 0){ 133 | All_ID[i] = inst->currentID(); 134 | if(pred != CorrectPrediction) 135 | Miss[i]++; 136 | 137 | if(pred == CorrectPrediction) 138 | correct[i]++; 139 | break; 140 | } 141 | } 142 | /****************************************************************************************************/ 143 | return pred; 144 | } 145 | virtual void switchIn(Pid_t pid) = 0; 146 | virtual void switchOut(Pid_t pid) = 0; 147 | }; 148 | 149 | 150 | class BPRas : public BPred { 151 | private: 152 | const ushort RasSize; 153 | 154 | InstID *stack; 155 | int32_t index; 156 | GStatsEnergy *rasEnergy; 157 | protected: 158 | public: 159 | BPRas(int32_t i, int32_t fetchWidth, const char *section); 160 | ~BPRas(); 161 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 162 | 163 | void switchIn(Pid_t pid); 164 | void switchOut(Pid_t pid); 165 | }; 166 | 167 | class BPBTB : public BPred { 168 | private: 169 | GStatsEnergy *btbEnergy; 170 | 171 | class BTBState : public StateGeneric<> { 172 | public: 173 | BTBState() { 174 | inst = 0; 175 | } 176 | 177 | InstID inst; 178 | 179 | bool operator==(BTBState s) const { 180 | return inst == s.inst; 181 | } 182 | }; 183 | 184 | typedef CacheGeneric BTBCache; 185 | 186 | BTBCache *data; 187 | 188 | protected: 189 | public: 190 | BPBTB(int32_t i, int32_t fetchWidth, const char *section, const char *name=0); 191 | ~BPBTB(); 192 | 193 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 194 | void updateOnly(const Instruction * inst, InstID oracleID); 195 | 196 | void switchIn(Pid_t pid); 197 | void switchOut(Pid_t pid); 198 | }; 199 | 200 | class BPOracle : public BPred { 201 | private: 202 | BPBTB btb; 203 | 204 | protected: 205 | public: 206 | BPOracle(int32_t i, int32_t fetchWidth, const char *section) 207 | :BPred(i, fetchWidth, section, "Oracle") 208 | ,btb(i, fetchWidth, section) { 209 | } 210 | 211 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 212 | 213 | void switchIn(Pid_t pid); 214 | void switchOut(Pid_t pid); 215 | }; 216 | 217 | class BPNotTaken : public BPred { 218 | private: 219 | protected: 220 | public: 221 | BPNotTaken(int32_t i, int32_t fetchWidth, const char *section) 222 | :BPred(i, fetchWidth, section, "NotTaken") { 223 | // Done 224 | } 225 | 226 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 227 | 228 | void switchIn(Pid_t pid); 229 | void switchOut(Pid_t pid); 230 | }; 231 | 232 | class BPTaken : public BPred { 233 | private: 234 | BPBTB btb; 235 | 236 | protected: 237 | public: 238 | BPTaken(int32_t i, int32_t fetchWidth, const char *section) 239 | :BPred(i, fetchWidth, section, "Taken") 240 | ,btb( i, fetchWidth, section) { 241 | // Done 242 | } 243 | 244 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 245 | 246 | void switchIn(Pid_t pid); 247 | void switchOut(Pid_t pid); 248 | }; 249 | 250 | class BPStatic:public BPred { 251 | private: 252 | BPBTB btb; 253 | 254 | protected: 255 | public: 256 | BPStatic(int32_t i, int32_t fetchWidth, const char *section) 257 | :BPred(i, fetchWidth, section, "Static") 258 | ,btb( i, fetchWidth, section) { 259 | // Done 260 | } 261 | 262 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 263 | 264 | void switchIn(Pid_t pid); 265 | void switchOut(Pid_t pid); 266 | }; 267 | 268 | class BP2bit:public BPred { 269 | private: 270 | BPBTB btb; 271 | 272 | SCTable table; 273 | protected: 274 | public: 275 | BP2bit(int32_t i, int32_t fetchWidth, const char *section); 276 | 277 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 278 | 279 | void switchIn(Pid_t pid); 280 | void switchOut(Pid_t pid); 281 | }; 282 | 283 | class BP2level:public BPred { 284 | private: 285 | BPBTB btb; 286 | 287 | const ushort l1Size; 288 | const uint32_t l1SizeMask; 289 | 290 | const ushort historySize; 291 | const HistoryType historyMask; 292 | 293 | SCTable globalTable; 294 | 295 | HistoryType *historyTable; // LHR 296 | protected: 297 | public: 298 | BP2level(int32_t i, int32_t fetchWidth, const char *section); 299 | ~BP2level(); 300 | 301 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 302 | 303 | void switchIn(Pid_t pid); 304 | void switchOut(Pid_t pid); 305 | }; 306 | 307 | class BPHybrid:public BPred { 308 | private: 309 | BPBTB btb; 310 | 311 | const ushort historySize; 312 | const HistoryType historyMask; 313 | 314 | SCTable globalTable; 315 | 316 | HistoryType ghr; // Global History Register 317 | 318 | SCTable localTable; 319 | SCTable metaTable; 320 | 321 | protected: 322 | public: 323 | BPHybrid(int32_t i, int32_t fetchWidth, const char *section); 324 | ~BPHybrid(); 325 | 326 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 327 | 328 | void switchIn(Pid_t pid); 329 | void switchOut(Pid_t pid); 330 | }; 331 | 332 | class BP2BcgSkew : public BPred { 333 | private: 334 | BPBTB btb; 335 | 336 | SCTable BIM; 337 | 338 | SCTable G0; 339 | const ushort G0HistorySize; 340 | const HistoryType G0HistoryMask; 341 | 342 | SCTable G1; 343 | const ushort G1HistorySize; 344 | const HistoryType G1HistoryMask; 345 | 346 | SCTable metaTable; 347 | const ushort MetaHistorySize; 348 | const HistoryType MetaHistoryMask; 349 | 350 | HistoryType history; 351 | protected: 352 | public: 353 | BP2BcgSkew(int32_t i, int32_t fetchWidth, const char *section); 354 | ~BP2BcgSkew(); 355 | 356 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 357 | 358 | void switchIn(Pid_t pid); 359 | void switchOut(Pid_t pid); 360 | }; 361 | 362 | class BPyags : public BPred { 363 | private: 364 | BPBTB btb; 365 | 366 | const ushort historySize; 367 | const HistoryType historyMask; 368 | 369 | SCTable table; 370 | SCTable ctableTaken; 371 | SCTable ctableNotTaken; 372 | 373 | HistoryType ghr; // Global History Register 374 | 375 | uchar *CacheTaken; 376 | HistoryType CacheTakenMask; 377 | HistoryType CacheTakenTagMask; 378 | 379 | uchar *CacheNotTaken; 380 | HistoryType CacheNotTakenMask; 381 | HistoryType CacheNotTakenTagMask; 382 | 383 | protected: 384 | public: 385 | BPyags(int32_t i, int32_t fetchWidth, const char *section); 386 | ~BPyags(); 387 | 388 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 389 | 390 | void switchIn(Pid_t pid); 391 | void switchOut(Pid_t pid); 392 | }; 393 | 394 | class BPOgehl : public BPred { 395 | private: 396 | BPBTB btb; 397 | 398 | const int32_t M_SIZ; 399 | const int32_t glength; 400 | const int32_t nentry; 401 | const int32_t addwidth; 402 | int32_t logpred; 403 | 404 | int32_t THETA; 405 | int32_t MAXTHETA; 406 | int32_t THETAUP; 407 | int32_t PREDUP; 408 | 409 | long long phist; 410 | long long *ghist; 411 | int32_t *histLength; 412 | int32_t *usedHistLength; 413 | 414 | int32_t *T; 415 | int32_t AC; 416 | int32_t miniTag; 417 | char *MINITAG; 418 | 419 | char **pred; 420 | int32_t TC; 421 | protected: 422 | int32_t geoidx(long long Add, long long *histo, long long phisto, int32_t m, int32_t funct); 423 | public: 424 | BPOgehl(int32_t i, int32_t fetchWidth, const char *section); 425 | ~BPOgehl(); 426 | 427 | PredType predict(const Instruction * inst, InstID oracleID, bool doUpdate); 428 | 429 | void switchIn(Pid_t pid); 430 | void switchOut(Pid_t pid); 431 | }; 432 | 433 | class BPredictor { 434 | private: 435 | const int32_t id; 436 | const bool SMTcopy; 437 | 438 | BPRas ras; 439 | BPred *pred; 440 | 441 | GStatsCntr nBranches; 442 | GStatsCntr nTaken; 443 | GStatsCntr nMiss; // hits == nBranches - nMiss 444 | 445 | char *section; 446 | 447 | protected: 448 | public: 449 | BPredictor(int32_t i, int32_t fetchWidth, const char *section, BPredictor *bpred=0); 450 | ~BPredictor(); 451 | 452 | static BPred *getBPred(int32_t id, int32_t fetchWidth, const char *sec); 453 | 454 | PredType predict(const Instruction *inst, InstID oracleID, bool doUpdate) { 455 | I(inst->isBranch()); 456 | 457 | nBranches.cinc(doUpdate); 458 | nTaken.cinc(inst->calcNextInstID() != oracleID); 459 | 460 | PredType p= ras.doPredict(inst, oracleID, doUpdate); 461 | if( p != NoPrediction ) { 462 | nMiss.cinc(p != CorrectPrediction && doUpdate); 463 | return p; 464 | } 465 | 466 | p = pred->doPredict(inst, oracleID, doUpdate); 467 | 468 | nMiss.cinc(p != CorrectPrediction && doUpdate); 469 | 470 | return p; 471 | } 472 | 473 | void dump(const char *str) const; 474 | 475 | void switchIn(Pid_t pid) { 476 | pred->switchIn(pid); 477 | } 478 | 479 | void switchOut(Pid_t pid) { 480 | pred->switchOut(pid); 481 | } 482 | }; 483 | 484 | #endif // BPRED_H 485 | -------------------------------------------------------------------------------- /Project1/PartJ/rt.out.Hybrid: -------------------------------------------------------------------------------- 1 | [0] Thread 0 (0) Create 2 | Begin skipping: requested 0 instructions 3 | 4 | End skipping: requested 0 skipped 0 5 | 6 | [156074563] Thread 0 (0) Exit 7 | 8 | 9 | ======================= Coherence message stat ====================== 10 | 11 | ReadRequest 471426 12 | ExclusiveReply 529134 13 | IntervSharedRequest 0 14 | SpeculativeReply 0 15 | SharedReply 0 16 | SharedResponse 0 17 | SharingWriteBack 0 18 | SharedAck 0 19 | SharingTransfer 0 20 | WriteRequest 57708 21 | Invalidation 0 22 | InvalidationAck 0 23 | ExclusiveReplyInv 0 24 | IntervExRequest 0 25 | ExclusiveResponse 0 26 | DirtyTransfer 0 27 | ExclusiveAck 0 28 | UpgradeRequest 0 29 | ExclusiveReplyInvND 0 30 | WriteBackExAck 528110 31 | WriteBackBusyAck 0 32 | WriteBackRequest 528110 33 | TokenBackRequest 0 34 | NAK 0 35 | MeshMemPush 70626 36 | MeshMemAccess 87200 37 | MeshMemAccessReply 0 38 | NOP 0 39 | 40 | 41 | 42 | 43 | ======================= Network selection stat ====================== 44 | 45 | SIZE : 72610832 46 | 47 | 48 | ======================= Message per Network selection stat ====================== 49 | 50 | ReadRequest 334917 51 | ExclusiveReply 378820 52 | IntervSharedRequest 0 53 | SpeculativeReply 0 54 | SharedReply 0 55 | SharedResponse 0 56 | SharingWriteBack 0 57 | SharedAck 0 58 | SharingTransfer 0 59 | WriteRequest 43903 60 | Invalidation 0 61 | InvalidationAck 0 62 | ExclusiveReplyInv 0 63 | IntervExRequest 0 64 | ExclusiveResponse 0 65 | DirtyTransfer 0 66 | ExclusiveAck 0 67 | UpgradeRequest 0 68 | ExclusiveReplyInvND 0 69 | WriteBackExAck 378052 70 | WriteBackBusyAck 0 71 | WriteBackRequest 378052 72 | TokenBackRequest 0 73 | NAK 0 74 | MeshMemPush 70626 75 | MeshMemAccess 87200 76 | MeshMemAccessReply 87200 77 | NOP 0 78 | 79 | 80 | MultipleDestInvalidation : 0 81 | TotDestInvalidation : 0 82 | 83 | 84 | 1-9 All: 0 Correct: 0 Inst Number:0 85 | 10-99 All: 0 Correct: 0 Inst Number:0 86 | 100-999 All: 0 Correct: 0 Inst Number:0 87 | 1000+ All: 0 Correct: 0 Inst Number:0 88 | ================================================================================ 89 | 1-9 All: 2075 Correct: 811 Inst Number:1028 90 | 10-99 All: 7361 Correct: 4934 Inst Number:153 91 | 100-999 All: 87770 Correct: 45634 Inst Number:428 92 | 1000+ All: 16563443 Correct: 14060983 Inst Number:725 93 | Accuracy : 0.847048 94 | ================================================================================ 95 | 1-9 All: 321 Correct: 317 Inst Number:148 96 | 10-99 All: 873 Correct: 873 Inst Number:15 97 | 100-999 All: 2154 Correct: 2154 Inst Number:12 98 | 1000+ All: 1473561 Correct: 1473561 Inst Number:73 99 | Accuracy : 0.999997 100 | ================================================================================ 101 | 1-9 All: 0 Correct: 0 Inst Number:0 102 | 10-99 All: 0 Correct: 0 Inst Number:0 103 | 100-999 All: 0 Correct: 0 Inst Number:0 104 | 1000+ All: 0 Correct: 0 Inst Number:0 105 | ================================================================================ 106 | 1-9 All: 0 Correct: 0 Inst Number:0 107 | 10-99 All: 0 Correct: 0 Inst Number:0 108 | 100-999 All: 0 Correct: 0 Inst Number:0 109 | 1000+ All: 0 Correct: 0 Inst Number:0 110 | ================================================================================ 111 | 1-9 All: 0 Correct: 0 Inst Number:0 112 | 10-99 All: 0 Correct: 0 Inst Number:0 113 | 100-999 All: 0 Correct: 0 Inst Number:0 114 | 1000+ All: 0 Correct: 0 Inst Number:0 115 | ================================================================================ 116 | 1-9 All: 0 Correct: 0 Inst Number:0 117 | 10-99 All: 0 Correct: 0 Inst Number:0 118 | 100-999 All: 0 Correct: 0 Inst Number:0 119 | 1000+ All: 0 Correct: 0 Inst Number:0 120 | ================================================================================ 121 | 1-9 All: 0 Correct: 0 Inst Number:0 122 | 10-99 All: 0 Correct: 0 Inst Number:0 123 | 100-999 All: 0 Correct: 0 Inst Number:0 124 | 1000+ All: 0 Correct: 0 Inst Number:0 125 | ================================================================================ 126 | 1-9 All: 0 Correct: 0 Inst Number:0 127 | 10-99 All: 0 Correct: 0 Inst Number:0 128 | 100-999 All: 0 Correct: 0 Inst Number:0 129 | 1000+ All: 0 Correct: 0 Inst Number:0 130 | ================================================================================ 131 | 1-9 All: 0 Correct: 0 Inst Number:0 132 | 10-99 All: 0 Correct: 0 Inst Number:0 133 | 100-999 All: 0 Correct: 0 Inst Number:0 134 | 1000+ All: 0 Correct: 0 Inst Number:0 135 | ================================================================================ 136 | 1-9 All: 0 Correct: 0 Inst Number:0 137 | 10-99 All: 0 Correct: 0 Inst Number:0 138 | 100-999 All: 0 Correct: 0 Inst Number:0 139 | 1000+ All: 0 Correct: 0 Inst Number:0 140 | ================================================================================ 141 | 1-9 All: 0 Correct: 0 Inst Number:0 142 | 10-99 All: 0 Correct: 0 Inst Number:0 143 | 100-999 All: 0 Correct: 0 Inst Number:0 144 | 1000+ All: 0 Correct: 0 Inst Number:0 145 | ================================================================================ 146 | -------------------------------------------------------------------------------- /Project1/PartJ/rt.out.NT: -------------------------------------------------------------------------------- 1 | [0] Thread 0 (0) Create 2 | Begin skipping: requested 0 instructions 3 | 4 | End skipping: requested 0 skipped 0 5 | 6 | [218303713] Thread 0 (0) Exit 7 | 8 | 9 | ======================= Coherence message stat ====================== 10 | 11 | ReadRequest 471477 12 | ExclusiveReply 529184 13 | IntervSharedRequest 0 14 | SpeculativeReply 0 15 | SharedReply 0 16 | SharedResponse 0 17 | SharingWriteBack 0 18 | SharedAck 0 19 | SharingTransfer 0 20 | WriteRequest 57707 21 | Invalidation 0 22 | InvalidationAck 0 23 | ExclusiveReplyInv 0 24 | IntervExRequest 0 25 | ExclusiveResponse 0 26 | DirtyTransfer 0 27 | ExclusiveAck 0 28 | UpgradeRequest 0 29 | ExclusiveReplyInvND 0 30 | WriteBackExAck 528160 31 | WriteBackBusyAck 0 32 | WriteBackRequest 528160 33 | TokenBackRequest 0 34 | NAK 0 35 | MeshMemPush 70623 36 | MeshMemAccess 87198 37 | MeshMemAccessReply 0 38 | NOP 0 39 | 40 | 41 | 42 | 43 | ======================= Network selection stat ====================== 44 | 45 | SIZE : 72619256 46 | 47 | 48 | ======================= Message per Network selection stat ====================== 49 | 50 | ReadRequest 334974 51 | ExclusiveReply 378875 52 | IntervSharedRequest 0 53 | SpeculativeReply 0 54 | SharedReply 0 55 | SharedResponse 0 56 | SharingWriteBack 0 57 | SharedAck 0 58 | SharingTransfer 0 59 | WriteRequest 43901 60 | Invalidation 0 61 | InvalidationAck 0 62 | ExclusiveReplyInv 0 63 | IntervExRequest 0 64 | ExclusiveResponse 0 65 | DirtyTransfer 0 66 | ExclusiveAck 0 67 | UpgradeRequest 0 68 | ExclusiveReplyInvND 0 69 | WriteBackExAck 378107 70 | WriteBackBusyAck 0 71 | WriteBackRequest 378107 72 | TokenBackRequest 0 73 | NAK 0 74 | MeshMemPush 70623 75 | MeshMemAccess 87198 76 | MeshMemAccessReply 87198 77 | NOP 0 78 | 79 | 80 | MultipleDestInvalidation : 0 81 | TotDestInvalidation : 0 82 | 83 | 84 | 1-9 All: 2075 Correct: 906 Inst Number:1028 85 | 10-99 All: 7361 Correct: 2696 Inst Number:153 86 | 100-999 All: 87770 Correct: 31986 Inst Number:428 87 | 1000+ All: 16563443 Correct: 7731533 Inst Number:725 88 | Accuracy : 0.466196 89 | ================================================================================ 90 | 1-9 All: 321 Correct: 317 Inst Number:148 91 | 10-99 All: 873 Correct: 873 Inst Number:15 92 | 100-999 All: 2154 Correct: 2154 Inst Number:12 93 | 1000+ All: 1473561 Correct: 1473561 Inst Number:73 94 | Accuracy : 0.999997 95 | ================================================================================ 96 | 1-9 All: 0 Correct: 0 Inst Number:0 97 | 10-99 All: 0 Correct: 0 Inst Number:0 98 | 100-999 All: 0 Correct: 0 Inst Number:0 99 | 1000+ All: 0 Correct: 0 Inst Number:0 100 | ================================================================================ 101 | 1-9 All: 0 Correct: 0 Inst Number:0 102 | 10-99 All: 0 Correct: 0 Inst Number:0 103 | 100-999 All: 0 Correct: 0 Inst Number:0 104 | 1000+ All: 0 Correct: 0 Inst Number:0 105 | ================================================================================ 106 | 1-9 All: 0 Correct: 0 Inst Number:0 107 | 10-99 All: 0 Correct: 0 Inst Number:0 108 | 100-999 All: 0 Correct: 0 Inst Number:0 109 | 1000+ All: 0 Correct: 0 Inst Number:0 110 | ================================================================================ 111 | 1-9 All: 0 Correct: 0 Inst Number:0 112 | 10-99 All: 0 Correct: 0 Inst Number:0 113 | 100-999 All: 0 Correct: 0 Inst Number:0 114 | 1000+ All: 0 Correct: 0 Inst Number:0 115 | ================================================================================ 116 | 1-9 All: 0 Correct: 0 Inst Number:0 117 | 10-99 All: 0 Correct: 0 Inst Number:0 118 | 100-999 All: 0 Correct: 0 Inst Number:0 119 | 1000+ All: 0 Correct: 0 Inst Number:0 120 | ================================================================================ 121 | 1-9 All: 0 Correct: 0 Inst Number:0 122 | 10-99 All: 0 Correct: 0 Inst Number:0 123 | 100-999 All: 0 Correct: 0 Inst Number:0 124 | 1000+ All: 0 Correct: 0 Inst Number:0 125 | ================================================================================ 126 | -------------------------------------------------------------------------------- /Project1/hybrid.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/hybrid.PNG -------------------------------------------------------------------------------- /Project1/nottaken.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project1/nottaken.PNG -------------------------------------------------------------------------------- /Project2/CacheCore.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Jose Renau 6 | Basilio Fraguela 7 | James Tuck 8 | Smruti Sarangi 9 | Luis Ceze 10 | Karin Strauss 11 | 12 | This file is part of SESC. 13 | 14 | SESC is free software; you can redistribute it and/or modify it under the terms 15 | of the GNU General Public License as published by the Free Software Foundation; 16 | either version 2, or (at your option) any later version. 17 | 18 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 19 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 20 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 21 | 22 | You should have received a copy of the GNU General Public License along with 23 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 24 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 | */ 26 | 27 | #define CACHECORE_CPP 28 | 29 | #include 30 | #include 31 | #include 32 | #include 33 | 34 | #include "CacheCore.h" 35 | #include "SescConf.h" 36 | #include "libcore/EnergyMgr.h" 37 | 38 | #define k_RANDOM "RANDOM" 39 | #define k_LRU "LRU" 40 | #define k_NXLRU "NXLRU" 41 | 42 | // 43 | // Class CacheGeneric, the combinational logic of Cache 44 | // 45 | template 46 | CacheGeneric *CacheGeneric::create(int32_t size, int32_t assoc, int32_t bsize, int32_t addrUnit, const char *pStr, bool skew) 47 | { 48 | CacheGeneric *cache; 49 | 50 | if (skew) { 51 | I(assoc=1); // Skew cache should be direct map 52 | cache = new CacheDMSkew(size, bsize, addrUnit, pStr); 53 | } else if (assoc==1) { 54 | // Direct Map cache 55 | cache = new CacheDM(size, bsize, addrUnit, pStr); 56 | } else if(size == (assoc * bsize)) { 57 | // TODO: Fully assoc can use STL container for speed 58 | cache = new CacheAssoc(size, assoc, bsize, addrUnit, pStr); 59 | } else { 60 | // Associative Cache 61 | cache = new CacheAssoc(size, assoc, bsize, addrUnit, pStr); 62 | } 63 | 64 | I(cache); 65 | return cache; 66 | } 67 | 68 | template 69 | PowerGroup CacheGeneric::getRightStat(const char* type) 70 | { 71 | if(strcasecmp(type,"icache")==0) 72 | return FetchPower; 73 | 74 | if(strcasecmp(type,"itlb")==0) 75 | return FetchPower; 76 | 77 | if(strcasecmp(type,"cache")==0) 78 | return MemPower; 79 | 80 | if(strcasecmp(type,"tlb")==0) 81 | return MemPower; 82 | 83 | if(strcasecmp(type,"dir")==0) 84 | return MemPower; 85 | 86 | if(strcasecmp(type,"revLVIDTable")==0) 87 | return MemPower; 88 | 89 | if(strcasecmp(type,"nicecache")==0) 90 | return MemPower; 91 | 92 | MSG("Unknown power group for [%s], add it to CacheCore", type); 93 | I(0); 94 | 95 | // default case 96 | return MemPower; 97 | } 98 | 99 | template 100 | void CacheGeneric::createStats(const char *section, const char *name) 101 | { 102 | // get the type 103 | bool typeExists = SescConf->checkCharPtr(section, "deviceType"); 104 | const char *type = 0; 105 | if (typeExists) 106 | type = SescConf->getCharPtr(section, "deviceType"); 107 | 108 | int32_t procId = 0; 109 | if ( name[0] == 'P' && name[1] == '(' ) { 110 | // This structure is assigned to an specific processor 111 | const char *number = &name[2]; 112 | procId = atoi(number); 113 | } 114 | if (Energy) { 115 | PowerGroup pg; 116 | pg = getRightStat(type); 117 | rdEnergy[0] = new GStatsEnergy("rdHitEnergy",name 118 | ,procId 119 | ,pg 120 | ,EnergyMgr::get(section,"rdHitEnergy")); 121 | 122 | rdEnergy[1] = new GStatsEnergy("rdMissEnergy",name 123 | ,procId 124 | ,pg 125 | ,EnergyMgr::get(section,"rdMissEnergy")); 126 | 127 | wrEnergy[0] = new GStatsEnergy("wrHitEnergy",name 128 | ,procId 129 | ,pg 130 | ,EnergyMgr::get(section,"wrHitEnergy")); 131 | 132 | wrEnergy[1] = new GStatsEnergy("wrMissEnergy",name 133 | ,procId 134 | ,pg 135 | ,EnergyMgr::get(section,"wrMissEnergy")); 136 | 137 | } else { 138 | rdEnergy[0] = 0; 139 | rdEnergy[1] = 0; 140 | wrEnergy[0] = 0; 141 | wrEnergy[1] = 0; 142 | } 143 | } 144 | 145 | template 146 | CacheGeneric *CacheGeneric::create(const char *section, const char *append, const char *format, ...) 147 | { 148 | CacheGeneric *cache=0; 149 | char size[STR_BUF_SIZE]; 150 | char bsize[STR_BUF_SIZE]; 151 | char addrUnit[STR_BUF_SIZE]; 152 | char assoc[STR_BUF_SIZE]; 153 | char repl[STR_BUF_SIZE]; 154 | char skew[STR_BUF_SIZE]; 155 | 156 | snprintf(size ,STR_BUF_SIZE,"%sSize" ,append); 157 | snprintf(bsize,STR_BUF_SIZE,"%sBsize",append); 158 | snprintf(addrUnit,STR_BUF_SIZE,"%sAddrUnit",append); 159 | snprintf(assoc,STR_BUF_SIZE,"%sAssoc",append); 160 | snprintf(repl ,STR_BUF_SIZE,"%sReplPolicy",append); 161 | snprintf(skew ,STR_BUF_SIZE,"%sSkew",append); 162 | 163 | int32_t s = SescConf->getInt(section, size); 164 | int32_t a = SescConf->getInt(section, assoc); 165 | int32_t b = SescConf->getInt(section, bsize); 166 | bool sk = false; 167 | if (SescConf->checkBool(section, skew)) 168 | sk = SescConf->getBool(section, skew); 169 | 170 | //For now, tolerate caches that don't have this defined. 171 | int32_t u; 172 | if ( SescConf->checkInt(section,addrUnit) ) { 173 | if ( SescConf->isBetween(section, addrUnit, 0, b) && 174 | SescConf->isPower2(section, addrUnit) ) 175 | u = SescConf->getInt(section,addrUnit); 176 | else 177 | u = 1; 178 | } else { 179 | u = 1; 180 | } 181 | 182 | const char *pStr = SescConf->getCharPtr(section, repl); 183 | 184 | if(SescConf->isGT(section, size, 0) && 185 | SescConf->isGT(section, bsize, 0) && 186 | SescConf->isGT(section, assoc, 0) && 187 | SescConf->isPower2(section, size) && 188 | SescConf->isPower2(section, bsize) && 189 | SescConf->isPower2(section, assoc) && 190 | SescConf->isInList(section, repl, k_RANDOM, k_LRU, k_NXLRU)) { 191 | 192 | cache = create(s, a, b, u, pStr, sk); 193 | } else { 194 | // this is just to keep the configuration going, 195 | // sesc will abort before it begins 196 | cache = new CacheAssoc(2, 197 | 1, 198 | 1, 199 | 1, 200 | pStr); 201 | } 202 | 203 | I(cache); 204 | 205 | char cacheName[STR_BUF_SIZE]; 206 | { 207 | va_list ap; 208 | 209 | va_start(ap, format); 210 | vsprintf(cacheName, format, ap); 211 | va_end(ap); 212 | } 213 | 214 | cache->createStats(section, cacheName); 215 | 216 | return cache; 217 | } 218 | 219 | /********************************************************* 220 | * CacheAssoc 221 | *********************************************************/ 222 | 223 | template 224 | CacheAssoc::CacheAssoc(int32_t size, int32_t assoc, int32_t blksize, int32_t addrUnit, const char *pStr) 225 | : CacheGeneric(size, assoc, blksize, addrUnit) 226 | { 227 | I(numLines>0); 228 | 229 | if (strcasecmp(pStr, k_RANDOM) == 0) 230 | policy = RANDOM; 231 | else if (strcasecmp(pStr, k_LRU) == 0) 232 | policy = LRU; 233 | else if (strcasecmp(pStr, k_NXLRU) == 0) 234 | policy = NXLRU; 235 | else { 236 | MSG("Invalid cache policy [%s]",pStr); 237 | exit(0); 238 | } 239 | 240 | mem = new Line [numLines + 1]; 241 | content = new Line* [numLines + 1]; 242 | 243 | for(uint32_t i = 0; i < numLines; i++) { 244 | mem[i].initialize(this); 245 | mem[i].invalidate(); 246 | content[i] = &mem[i]; 247 | } 248 | 249 | irand = 0; 250 | } 251 | 252 | template 253 | typename CacheAssoc::Line *CacheAssoc::findLinePrivate(Addr_t addr) 254 | { 255 | Addr_t tag = calcTag(addr); 256 | 257 | GI(Energy, goodInterface); // If modeling energy. Do not use this 258 | // interface directly. use readLine and 259 | // writeLine instead. If it is called 260 | // inside debugging only use 261 | // findLineDebug instead 262 | 263 | Line **theSet = &content[calcIndex4Tag(tag)]; 264 | 265 | // Check most typical case 266 | if ((*theSet)->getTag() == tag) { 267 | //this assertion is not true for SMP; it is valid to return invalid line 268 | #if !defined(SESC_SMP) && !defined(SESC_CRIT) 269 | I((*theSet)->isValid()); 270 | #endif 271 | return *theSet; 272 | } 273 | 274 | Line **lineHit=0; 275 | Line **setEnd = theSet + assoc; 276 | 277 | // For sure that position 0 is not (short-cut) 278 | { 279 | Line **l = theSet + 1; 280 | while(l < setEnd) { 281 | if ((*l)->getTag() == tag) { 282 | lineHit = l; 283 | break; 284 | } 285 | l++; 286 | } 287 | } 288 | 289 | if (lineHit == 0) 290 | return 0; 291 | 292 | I((*lineHit)->isValid()); 293 | 294 | // No matter what is the policy, move lineHit to the *theSet. This 295 | // increases locality 296 | Line *tmp = *lineHit; 297 | { 298 | Line **l = lineHit; 299 | while(l > theSet) { 300 | Line **prev = l - 1; 301 | *l = *prev;; 302 | l = prev; 303 | } 304 | *theSet = tmp; 305 | } 306 | 307 | return tmp; 308 | } 309 | 310 | template 311 | typename CacheAssoc::Line 312 | *CacheAssoc::findLine2Replace(Addr_t addr, bool ignoreLocked) 313 | { 314 | Addr_t tag = calcTag(addr); 315 | Line **theSet = &content[calcIndex4Tag(tag)]; 316 | 317 | // Check most typical case 318 | if ((*theSet)->getTag() == tag) { 319 | GI(tag,(*theSet)->isValid()); 320 | return *theSet; 321 | } 322 | 323 | Line **lineHit=0; 324 | Line **lineFree=0; // Order of preference, invalid, locked 325 | Line **setEnd = theSet + assoc; 326 | int count = 0; 327 | Line **buf = 0; 328 | 329 | // Start in reverse order so that get the youngest invalid possible, 330 | // and the oldest isLocked possible (lineFree) 331 | { 332 | Line **l = setEnd -1; 333 | while(l >= theSet && (policy == RANDOM || policy == LRU)) { 334 | if ((*l)->getTag() == tag) { 335 | lineHit = l; 336 | break; 337 | } 338 | if (!(*l)->isValid()) 339 | lineFree = l; 340 | else if (lineFree == 0 && !(*l)->isLocked()) 341 | lineFree = l; 342 | 343 | // If line is invalid, isLocked must be false 344 | GI(!(*l)->isValid(), !(*l)->isLocked()); 345 | l--; 346 | } 347 | 348 | while(l >= theSet && policy == NXLRU) { 349 | if ((*l)->getTag() == tag) { 350 | lineHit = l; 351 | break; 352 | } 353 | if (!(*l)->isValid()) 354 | lineFree = l; 355 | else if (lineFree == 0 && !(*l)->isLocked()) { 356 | count++; 357 | buf = l; 358 | if (count == 2) 359 | lineFree = l; 360 | } 361 | 362 | // If line is invalid, isLocked must be false 363 | GI(!(*l)->isValid(), !(*l)->isLocked()); 364 | l--; 365 | } 366 | if ((policy == NXLRU) && count == 1 && lineFree == 0) 367 | lineFree = buf; 368 | } 369 | GI(lineFree, !(*lineFree)->isValid() || !(*lineFree)->isLocked()); 370 | 371 | if (lineHit) 372 | return *lineHit; 373 | 374 | I(lineHit==0); 375 | 376 | if(lineFree == 0 && !ignoreLocked) 377 | return 0; 378 | 379 | if (lineFree == 0) { 380 | I(ignoreLocked); 381 | if (policy == RANDOM) { 382 | lineFree = &theSet[irand]; 383 | irand = (irand + 1) & maskAssoc; 384 | } else if (policy == LRU) { 385 | I(policy == LRU); 386 | // Get the oldest line possible 387 | lineFree = setEnd-1; 388 | } else if ((policy == NXLRU)) { 389 | I(policy == NXLRU); 390 | // Get the second oldest line 391 | lineFree = setEnd - 2; 392 | } 393 | } else if(ignoreLocked) { 394 | if (policy == RANDOM && (*lineFree)->isValid()) { 395 | lineFree = &theSet[irand]; 396 | irand = (irand + 1) & maskAssoc; 397 | } else { 398 | // I(policy == LRU); 399 | // Do nothing. lineFree is the oldest 400 | } 401 | } 402 | 403 | I(lineFree); 404 | GI(!ignoreLocked, !(*lineFree)->isValid() || !(*lineFree)->isLocked()); 405 | 406 | if (lineFree == theSet) 407 | return *lineFree; // Hit in the first possition 408 | 409 | // No matter what is the policy, move lineHit to the *theSet. This 410 | // increases locality 411 | Line *tmp = *lineFree; 412 | { 413 | Line **l = lineFree; 414 | while(l > theSet) { 415 | Line **prev = l - 1; 416 | *l = *prev;; 417 | l = prev; 418 | } 419 | *theSet = tmp; 420 | } 421 | 422 | return tmp; 423 | } 424 | 425 | /********************************************************* 426 | * CacheDM 427 | *********************************************************/ 428 | 429 | template 430 | CacheDM::CacheDM(int32_t size, int32_t blksize, int32_t addrUnit, const char *pStr) 431 | : CacheGeneric(size, 1, blksize, addrUnit) 432 | { 433 | I(numLines>0); 434 | 435 | mem = new Line[numLines + 1]; 436 | content = new Line* [numLines + 1]; 437 | 438 | for(uint32_t i = 0; i < numLines; i++) { 439 | mem[i].initialize(this); 440 | mem[i].invalidate(); 441 | content[i] = &mem[i]; 442 | } 443 | } 444 | 445 | template 446 | typename CacheDM::Line *CacheDM::findLinePrivate(Addr_t addr) 447 | { 448 | Addr_t tag = calcTag(addr); 449 | 450 | GI(Energy, goodInterface); // If modeling energy. Do not use this 451 | // interface directly. use readLine and 452 | // writeLine instead. If it is called 453 | // inside debugging only use 454 | // findLineDebug instead 455 | 456 | Line *line = content[calcIndex4Tag(tag)]; 457 | 458 | if (line->getTag() == tag) { 459 | I(line->isValid()); 460 | return line; 461 | } 462 | 463 | return 0; 464 | //return l; 465 | } 466 | 467 | template 468 | typename CacheDM::Line 469 | *CacheDM::findLine2Replace(Addr_t addr, bool ignoreLocked) 470 | { 471 | Addr_t tag = calcTag(addr); 472 | Line *line = content[calcIndex4Tag(tag)]; 473 | 474 | if (ignoreLocked) 475 | return line; 476 | 477 | if (line->getTag() == tag) { 478 | GI(tag,line->isValid()); 479 | return line; 480 | } 481 | 482 | if (line->isLocked()) 483 | return 0; 484 | 485 | return line; 486 | } 487 | 488 | /********************************************************* 489 | * CacheDMSkew 490 | *********************************************************/ 491 | 492 | template 493 | CacheDMSkew::CacheDMSkew(int32_t size, int32_t blksize, int32_t addrUnit, const char *pStr) 494 | : CacheGeneric(size, 1, blksize, addrUnit) 495 | { 496 | I(numLines>0); 497 | 498 | mem = new Line[numLines + 1]; 499 | content = new Line* [numLines + 1]; 500 | 501 | for(uint32_t i = 0; i < numLines; i++) { 502 | mem[i].initialize(this); 503 | mem[i].invalidate(); 504 | content[i] = &mem[i]; 505 | } 506 | } 507 | 508 | template 509 | typename CacheDMSkew::Line *CacheDMSkew::findLinePrivate(Addr_t addr) 510 | { 511 | Addr_t tag = calcTag(addr); 512 | 513 | GI(Energy, goodInterface); // If modeling energy. Do not use this 514 | // interface directly. use readLine and 515 | // writeLine instead. If it is called 516 | // inside debugging only use 517 | // findLineDebug instead 518 | 519 | Line *line = content[calcIndex4Tag(tag)]; 520 | 521 | if (line->getTag() == tag) { 522 | I(line->isValid()); 523 | return line; 524 | } 525 | 526 | // BEGIN Skew cache 527 | Addr_t tag2 = calcTag(addr ^ (addr>>7)); 528 | line = content[calcIndex4Tag(tag2)]; 529 | 530 | if (line->getTag() == tag) { 531 | I(line->isValid()); 532 | return line; 533 | } 534 | // END Skew cache 535 | 536 | return 0; 537 | } 538 | 539 | template 540 | typename CacheDMSkew::Line 541 | *CacheDMSkew::findLine2Replace(Addr_t addr, bool ignoreLocked) 542 | { 543 | Addr_t tag = calcTag(addr); 544 | Line *line = content[calcIndex4Tag(tag)]; 545 | 546 | if (ignoreLocked) 547 | return line; 548 | 549 | if (line->getTag() == tag) { 550 | GI(tag,line->isValid()); 551 | return line; 552 | } 553 | 554 | if (line->isLocked()) 555 | return 0; 556 | 557 | // BEGIN Skew cache 558 | Addr_t tag2 = calcTag(addr ^ (addr>>7)); 559 | Line *line2 = content[calcIndex4Tag(tag2)]; 560 | 561 | if (line2->getTag() == tag) { 562 | I(line2->isValid()); 563 | return line2; 564 | } 565 | static int32_t rand_number =0; 566 | if (rand_number++ & 1) 567 | return line; 568 | else 569 | return line2; 570 | // END Skew cache 571 | 572 | return line; 573 | } 574 | -------------------------------------------------------------------------------- /Project2/CacheCore.h: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Jose Renau 6 | Basilio Fraguela 7 | James Tuck 8 | Milos Prvulovic 9 | Smruti Sarangi 10 | 11 | This file is part of SESC. 12 | 13 | SESC is free software; you can redistribute it and/or modify it under the terms 14 | of the GNU General Public License as published by the Free Software Foundation; 15 | either version 2, or (at your option) any later version. 16 | 17 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 18 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 19 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 20 | 21 | You should have received a copy of the GNU General Public License along with 22 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 23 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 | */ 25 | 26 | #ifndef CACHECORE_H 27 | #define CACHECORE_H 28 | 29 | #include "GEnergy.h" 30 | #include "nanassert.h" 31 | #include "Snippets.h" 32 | #include "GStats.h" 33 | 34 | enum ReplacementPolicy {LRU, RANDOM, NXLRU}; 35 | 36 | #ifdef SESC_ENERGY 37 | template 38 | #else 39 | template 40 | #endif 41 | class CacheGeneric { 42 | private: 43 | static const int32_t STR_BUF_SIZE=1024; 44 | 45 | static PowerGroup getRightStat(const char* type); 46 | 47 | protected: 48 | const uint32_t size; 49 | const uint32_t lineSize; 50 | const uint32_t addrUnit; //Addressable unit: for most caches = 1 byte 51 | const uint32_t assoc; 52 | const uint32_t log2Assoc; 53 | const uint64_t log2AddrLs; 54 | const uint64_t maskAssoc; 55 | const uint32_t sets; 56 | const uint32_t maskSets; 57 | const uint32_t numLines; 58 | 59 | GStatsEnergy *rdEnergy[2]; // 0 hit, 1 miss 60 | GStatsEnergy *wrEnergy[2]; // 0 hit, 1 miss 61 | 62 | //GStatsCntr test; 63 | 64 | bool goodInterface; 65 | 66 | public: 67 | class CacheLine : public State { 68 | public: 69 | // Pure virtual class defines interface 70 | // 71 | // Tag included in state. Accessed through: 72 | // 73 | // Addr_t getTag() const; 74 | // void setTag(Addr_t a); 75 | // void clearTag(); 76 | // 77 | // 78 | // bool isValid() const; 79 | // void invalidate(); 80 | // 81 | // bool isLocked() const; 82 | }; 83 | 84 | // findLine returns a cache line that has tag == addr, NULL otherwise 85 | virtual CacheLine *findLinePrivate(Addr_t addr)=0; 86 | protected: 87 | 88 | CacheGeneric(uint32_t s, uint32_t a, uint32_t b, uint32_t u) 89 | : size(s) 90 | ,lineSize(b) 91 | ,addrUnit(u) 92 | ,assoc(a) 93 | ,log2Assoc(log2i(a)) 94 | ,log2AddrLs(log2i(b/u)) 95 | ,maskAssoc(a-1) 96 | ,sets((s/b)/a) 97 | ,maskSets(sets-1) 98 | ,numLines(s/b) 99 | //,test(":test") 100 | { 101 | // TODO : assoc and sets must be a power of 2 102 | } 103 | 104 | virtual ~CacheGeneric() {} 105 | 106 | GStatsEnergy *getEnergy(const char *section, PowerGroup grp, const char *format, const char *name); 107 | void createStats(const char *section, const char *name); 108 | 109 | public: 110 | // Do not use this interface, use other create 111 | static CacheGeneric *create(int32_t size, int32_t assoc, int32_t blksize, int32_t addrUnit, const char *pStr, bool skew); 112 | static CacheGeneric *create(const char *section, const char *append, const char *format, ...); 113 | void destroy() { 114 | delete this; 115 | } 116 | 117 | // If there are not free lines, it would return an existing cache line unless 118 | // all the possible cache lines are locked State must implement isLocked API 119 | // 120 | // when locked parameter is false, it would try to remove even locked lines 121 | 122 | virtual CacheLine *findLine2Replace(Addr_t addr, bool ignoreLocked=false)=0; 123 | 124 | // TO DELETE if flush from Cache.cpp is cleared. At least it should have a 125 | // cleaner interface so that Cache.cpp does not touch the internals. 126 | // 127 | // Access the line directly without checking TAG 128 | virtual CacheLine *getPLine(uint32_t l) = 0; 129 | 130 | //ALL USERS OF THIS CLASS PLEASE READ: 131 | // 132 | //readLine and writeLine MUST have the same functionality as findLine. The only 133 | //difference is that readLine and writeLine update power consumption 134 | //statistics. So, only use these functions when you want to model a physical 135 | //read or write operation. 136 | 137 | // Use this is for debug checks. Otherwise, a bad interface can be detected 138 | CacheLine *findLineDebug(Addr_t addr) { 139 | IS(goodInterface=true); 140 | CacheLine *line = findLine(addr); 141 | IS(goodInterface=false); 142 | return line; 143 | } 144 | 145 | // Use this when you need to change the line state but 146 | // do not want to account for energy 147 | CacheLine *findLineNoEffect(Addr_t addr) { 148 | IS(goodInterface=true); 149 | CacheLine *line = findLine(addr); 150 | IS(goodInterface=false); 151 | return line; 152 | } 153 | 154 | CacheLine *findLine(Addr_t addr) { 155 | return findLinePrivate(addr); 156 | } 157 | 158 | CacheLine *readLine(Addr_t addr) { 159 | 160 | IS(goodInterface=true); 161 | CacheLine *line = findLine(addr); 162 | IS(goodInterface=false); 163 | 164 | if(!Energy) 165 | return line; 166 | 167 | rdEnergy[line != 0 ? 0 : 1]->inc(); 168 | 169 | return line; 170 | } 171 | 172 | CacheLine *writeLine(Addr_t addr) { 173 | 174 | IS(goodInterface=true); 175 | CacheLine *line = findLine(addr); 176 | IS(goodInterface=false); 177 | 178 | if(!Energy) 179 | return line; 180 | 181 | wrEnergy[line != 0 ? 0 : 1]->inc(); 182 | 183 | return line; 184 | } 185 | 186 | CacheLine *fillLine(Addr_t addr) { 187 | CacheLine *l = findLine2Replace(addr); 188 | if (l==0) 189 | return 0; 190 | 191 | l->setTag(calcTag(addr)); 192 | 193 | return l; 194 | } 195 | 196 | CacheLine *fillLine(Addr_t addr, Addr_t &rplcAddr, bool ignoreLocked=false) { 197 | CacheLine *l = findLine2Replace(addr, ignoreLocked); 198 | rplcAddr = 0; 199 | if (l==0) 200 | return 0; 201 | 202 | Addr_t newTag = calcTag(addr); 203 | if (l->isValid()) { 204 | Addr_t curTag = l->getTag(); 205 | if (curTag != newTag) { 206 | rplcAddr = calcAddr4Tag(curTag); 207 | } 208 | } 209 | 210 | l->setTag(newTag); 211 | 212 | return l; 213 | } 214 | //My code 215 | // CacheLine *getrealline(Addr_t addr) { 216 | // CacheLine *l = 217 | // } 218 | 219 | uint32_t getLineSize() const { 220 | return lineSize; 221 | } 222 | uint32_t getAssoc() const { 223 | return assoc; 224 | } 225 | uint32_t getLog2AddrLs() const { 226 | return log2AddrLs; 227 | } 228 | uint32_t getLog2Assoc() const { 229 | return log2Assoc; 230 | } 231 | uint32_t getMaskSets() const { 232 | return maskSets; 233 | } 234 | uint32_t getNumLines() const { 235 | return numLines; 236 | } 237 | uint32_t getNumSets() const { 238 | return sets; 239 | } 240 | 241 | Addr_t calcTag(Addr_t addr) const { 242 | return (addr >> log2AddrLs); 243 | } 244 | 245 | uint32_t calcSet4Tag(Addr_t tag) const { 246 | return (tag & maskSets); 247 | } 248 | uint32_t calcSet4Addr(Addr_t addr) const { 249 | return calcSet4Tag(calcTag(addr)); 250 | } 251 | 252 | uint32_t calcIndex4Set(uint32_t set) const { 253 | return (set << log2Assoc); 254 | } 255 | uint32_t calcIndex4Tag(uint32_t tag) const { 256 | return calcIndex4Set(calcSet4Tag(tag)); 257 | } 258 | uint32_t calcIndex4Addr(Addr_t addr) const { 259 | return calcIndex4Set(calcSet4Addr(addr)); 260 | } 261 | 262 | Addr_t calcAddr4Tag(Addr_t tag) const { 263 | return (tag << log2AddrLs); 264 | } 265 | }; 266 | 267 | #ifdef SESC_ENERGY 268 | template 269 | #else 270 | template 271 | #endif 272 | class CacheAssoc : public CacheGeneric { 273 | using CacheGeneric::numLines; 274 | using CacheGeneric::assoc; 275 | using CacheGeneric::maskAssoc; 276 | using CacheGeneric::goodInterface; 277 | 278 | private: 279 | public: 280 | typedef typename CacheGeneric::CacheLine Line; 281 | 282 | protected: 283 | 284 | Line *mem; 285 | Line **content; 286 | ushort irand; 287 | ReplacementPolicy policy; 288 | 289 | friend class CacheGeneric; 290 | CacheAssoc(int32_t size, int32_t assoc, int32_t blksize, int32_t addrUnit, const char *pStr); 291 | 292 | Line *findLinePrivate(Addr_t addr); 293 | public: 294 | virtual ~CacheAssoc() { 295 | delete [] content; 296 | delete [] mem; 297 | } 298 | 299 | // TODO: do an iterator. not this junk!! 300 | Line *getPLine(uint32_t l) { 301 | // Lines [l..l+assoc] belong to the same set 302 | I(l 311 | #else 312 | template 313 | #endif 314 | class CacheDM : public CacheGeneric { 315 | using CacheGeneric::numLines; 316 | using CacheGeneric::goodInterface; 317 | 318 | private: 319 | public: 320 | typedef typename CacheGeneric::CacheLine Line; 321 | 322 | protected: 323 | 324 | Line *mem; 325 | Line **content; 326 | 327 | friend class CacheGeneric; 328 | CacheDM(int32_t size, int32_t blksize, int32_t addrUnit, const char *pStr); 329 | 330 | Line *findLinePrivate(Addr_t addr); 331 | public: 332 | virtual ~CacheDM() { 333 | delete [] content; 334 | delete [] mem; 335 | }; 336 | 337 | // TODO: do an iterator. not this junk!! 338 | Line *getPLine(uint32_t l) { 339 | // Lines [l..l+assoc] belong to the same set 340 | I(l 349 | #else 350 | template 351 | #endif 352 | class CacheDMSkew : public CacheGeneric { 353 | using CacheGeneric::numLines; 354 | using CacheGeneric::goodInterface; 355 | 356 | private: 357 | public: 358 | typedef typename CacheGeneric::CacheLine Line; 359 | 360 | protected: 361 | 362 | Line *mem; 363 | Line **content; 364 | 365 | friend class CacheGeneric; 366 | CacheDMSkew(int32_t size, int32_t blksize, int32_t addrUnit, const char *pStr); 367 | 368 | Line *findLinePrivate(Addr_t addr); 369 | public: 370 | virtual ~CacheDMSkew() { 371 | delete [] content; 372 | delete [] mem; 373 | }; 374 | 375 | // TODO: do an iterator. not this junk!! 376 | Line *getPLine(uint32_t l) { 377 | // Lines [l..l+assoc] belong to the same set 378 | I(l 387 | class StateGeneric { 388 | private: 389 | Addr_t tag; 390 | 391 | public: 392 | virtual ~StateGeneric() { 393 | tag = 0; 394 | } 395 | 396 | Addr_t getTag() const { 397 | return tag; 398 | } 399 | void setTag(Addr_t a) { 400 | I(a); 401 | tag = a; 402 | } 403 | void clearTag() { 404 | tag = 0; 405 | } 406 | void initialize(void *c) { 407 | clearTag(); 408 | } 409 | 410 | virtual bool isValid() const { 411 | return tag; 412 | } 413 | 414 | virtual void invalidate() { 415 | clearTag(); 416 | } 417 | 418 | virtual bool isLocked() const { 419 | return false; 420 | } 421 | 422 | virtual void dump(const char *str) { 423 | } 424 | }; 425 | 426 | #ifndef CACHECORE_CPP 427 | #include "CacheCore.cpp" 428 | #endif 429 | 430 | #endif // CACHECORE_H 431 | -------------------------------------------------------------------------------- /Project2/PRJ2.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project2/PRJ2.docx -------------------------------------------------------------------------------- /Project2/SMPCache.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Karin Strauss 6 | 7 | This file is part of SESC. 8 | 9 | SESC is free software; you can redistribute it and/or modify it under the terms 10 | of the GNU General Public License as published by the Free Software Foundation; 11 | either version 2, or (at your option) any later version. 12 | 13 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License along with 18 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 19 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 | */ 21 | 22 | #include "SMPCache.h" 23 | #include "SMPCacheState.h" 24 | #include "libmem/Cache.h" 25 | 26 | #include "MESIProtocol.h" 27 | 28 | // This cache works under the assumption that caches above it in the memory 29 | // hierarchy are write-through caches 30 | 31 | // There is a major simplifying assumption for this cache subsystem: 32 | // if there are two requests to the same cache line at the same time, 33 | // only one of them is propagated to the lower levels. Once this 34 | // request is serviced, the other one will be allowed to proceed. This 35 | // is implemented by the mutExclBuffer. 36 | 37 | // When this cache is not used as the last level of caching before 38 | // memory, we are assuming all levels between this cache and memory 39 | // are not necessarily inclusive. This does not mean they are 40 | // exclusive. 41 | 42 | // Another important assumption is that every cache line in the memory 43 | // subsystem is the same size. This is not hard to fix, though. Any 44 | // candidates? 45 | 46 | MSHR *SMPCache::mutExclBuffer = NULL; 47 | 48 | #ifdef SESC_ENERGY 49 | unsigned SMPCache::cacheID = 0; 50 | #endif 51 | 52 | SMPCache::SMPCache(SMemorySystem *dms, const char *section, const char *name) 53 | : MemObj(section, name) 54 | , readHit("%s:readHit", name) 55 | , writeHit("%s:writeHit", name) 56 | , readMiss("%s:readMiss", name) 57 | , writeMiss("%s:writeMiss", name) 58 | , readHalfMiss("%s:readHalfMiss", name) 59 | , writeHalfMiss("%s:writeHalfMiss", name) 60 | , writeBack("%s:writeBack", name) 61 | , linePush("%s:linePush", name) 62 | , lineFill("%s:lineFill", name) 63 | , readRetry("%s:readRetry", name) 64 | , writeRetry("%s:writeRetry", name) 65 | , invalDirty("%s:invalDirty", name) 66 | , allocDirty("%s:allocDirty", name) 67 | { 68 | MemObj *lowerLevel = NULL; 69 | 70 | I(dms); 71 | lowerLevel = dms->declareMemoryObj(section, "lowerLevel"); 72 | 73 | if (lowerLevel != NULL) 74 | addLowerLevel(lowerLevel); 75 | 76 | cache = CacheType::create(section, "", name); 77 | I(cache); 78 | 79 | const char *prot = SescConf->getCharPtr(section, "protocol"); 80 | if(!strcasecmp(prot, "MESI")) { 81 | protocol = new MESIProtocol(this, name); 82 | } else { 83 | MSG("unknown protocol, using MESI"); 84 | protocol = new MESIProtocol(this, name); 85 | } 86 | 87 | SescConf->isInt(section, "numPorts"); 88 | SescConf->isInt(section, "portOccp"); 89 | 90 | cachePort = PortGeneric::create(name, 91 | SescConf->getInt(section, "numPorts"), 92 | SescConf->getInt(section, "portOccp")); 93 | 94 | // MSHR is used as an outstanding request buffer 95 | // even hits are added to MSHR 96 | char *outsReqName = (char *) malloc(strlen(name) + 2); 97 | sprintf(outsReqName, "%s", name); 98 | 99 | const char *mshrSection = SescConf->getCharPtr(section,"MSHR"); 100 | 101 | outsReq = MSHR::create(outsReqName, mshrSection); 102 | 103 | if (mutExclBuffer == NULL) 104 | mutExclBuffer = MSHR::create("mutExclBuffer", 105 | SescConf->getCharPtr(mshrSection, "type"), 106 | 32000, 107 | SescConf->getInt(mshrSection, "bsize")); 108 | 109 | SescConf->isInt(section, "hitDelay"); 110 | hitDelay = SescConf->getInt(section, "hitDelay"); 111 | 112 | SescConf->isInt(section, "missDelay"); 113 | missDelay = SescConf->getInt(section, "missDelay"); 114 | 115 | #ifdef SESC_ENERGY 116 | 117 | myID = cacheID; 118 | cacheID++; 119 | 120 | rdEnergy[0] = new GStatsEnergy("rdHitEnergy",name 121 | ,myID 122 | ,MemPower 123 | ,EnergyMgr::get(section,"rdHitEnergy")); 124 | 125 | rdEnergy[1] = new GStatsEnergy("rdMissEnergy",name 126 | ,myID 127 | ,MemPower 128 | ,EnergyMgr::get(section,"rdMissEnergy")); 129 | 130 | wrEnergy[0] = new GStatsEnergy("wrHitEnergy",name 131 | ,myID 132 | ,MemPower 133 | ,EnergyMgr::get(section,"wrHitEnergy")); 134 | 135 | wrEnergy[1] = new GStatsEnergy("wrMissEnergy",name 136 | ,myID 137 | ,MemPower 138 | ,EnergyMgr::get(section,"wrMissEnergy")); 139 | #endif 140 | } 141 | 142 | SMPCache::~SMPCache() 143 | { 144 | // do nothing 145 | } 146 | 147 | Time_t SMPCache::getNextFreeCycle() const 148 | { 149 | return cachePort->calcNextSlot(); 150 | } 151 | 152 | bool SMPCache::canAcceptStore(PAddr addr) 153 | { 154 | return outsReq->canAcceptRequest(addr); 155 | } 156 | 157 | void SMPCache::access(MemRequest *mreq) 158 | { 159 | PAddr addr; 160 | IS(addr = mreq->getPAddr()); 161 | 162 | GMSG(mreq->getPAddr() < 1024, 163 | "mreq dinst=0x%p paddr=0x%x vaddr=0x%x memOp=%d ignored", 164 | mreq->getDInst(), 165 | (uint32_t) mreq->getPAddr(), 166 | (uint32_t) mreq->getVaddr(), 167 | mreq->getMemOperation()); 168 | 169 | I(addr >= 1024); 170 | 171 | switch(mreq->getMemOperation()) { 172 | case MemRead: 173 | read(mreq); 174 | break; 175 | case MemWrite: /*I(cache->findLine(mreq->getPAddr())); will be transformed 176 | to MemReadW later */ 177 | case MemReadW: 178 | write(mreq); 179 | break; 180 | case MemPush: 181 | I(0); 182 | break; // assumed write-through upperlevel 183 | default: 184 | specialOp(mreq); 185 | break; 186 | } 187 | 188 | // for reqs coming from upper level: 189 | // MemRead means "I want to read" 190 | // MemReadW means "I want to write, and I missed" 191 | // MemWrite means "I want to write, and I hit" 192 | // MemPush means "I am writing data back" 193 | // (this will never happen if upper level is write-through cache, 194 | // which is what we are assuming) 195 | } 196 | 197 | void SMPCache::read(MemRequest *mreq) 198 | { 199 | PAddr addr = mreq->getPAddr(); 200 | 201 | if (!outsReq->issue(addr)) { 202 | outsReq->addEntry(addr, doReadCB::create(this, mreq), 203 | doReadCB::create(this, mreq)); 204 | readHalfMiss.inc(); 205 | return; 206 | } 207 | 208 | doReadCB::scheduleAbs(nextSlot(), this, mreq); 209 | } 210 | 211 | void SMPCache::doRead(MemRequest *mreq) 212 | { 213 | PAddr addr = mreq->getPAddr(); 214 | Line *l = cache->readLine(addr); 215 | 216 | if (l && l->canBeRead()) { 217 | readHit.inc(); 218 | #ifdef SESC_ENERGY 219 | rdEnergy[0]->inc(); 220 | #endif 221 | outsReq->retire(addr); 222 | mreq->goUp(hitDelay); 223 | return; 224 | } 225 | 226 | if (l && l->isLocked()) { 227 | readRetry.inc(); 228 | Time_t nextTry = nextSlot(); 229 | if (nextTry == globalClock) 230 | nextTry++; 231 | doReadCB::scheduleAbs(nextTry, this, mreq); 232 | return; 233 | } 234 | 235 | GI(l, !l->isLocked()); 236 | 237 | readMiss.inc(); 238 | 239 | #ifdef SESC_ENERGY 240 | rdEnergy[1]->inc(); 241 | #endif 242 | 243 | if (!mutExclBuffer->issue(addr)) { 244 | mutExclBuffer->addEntry(addr, sendReadCB::create(this, mreq), 245 | sendReadCB::create(this, mreq)); 246 | return; 247 | } 248 | 249 | sendRead(mreq); 250 | } 251 | 252 | void SMPCache::sendRead(MemRequest* mreq) 253 | { 254 | protocol->read(mreq); 255 | } 256 | 257 | void SMPCache::write(MemRequest *mreq) 258 | { 259 | PAddr addr = mreq->getPAddr(); 260 | 261 | if (!outsReq->issue(addr)) { 262 | outsReq->addEntry(addr, doWriteCB::create(this, mreq), 263 | doWriteCB::create(this, mreq)); 264 | writeHalfMiss.inc(); 265 | return; 266 | } 267 | 268 | doWriteCB::scheduleAbs(nextSlot(), this, mreq); 269 | } 270 | 271 | void SMPCache::doWrite(MemRequest *mreq) 272 | { 273 | PAddr addr = mreq->getPAddr(); 274 | Line *l = cache->writeLine(addr); 275 | 276 | if (l && l->canBeWritten()) { 277 | writeHit.inc(); 278 | #ifdef SESC_ENERGY 279 | wrEnergy[0]->inc(); 280 | #endif 281 | protocol->makeDirty(l); 282 | outsReq->retire(addr); 283 | mreq->goUp(hitDelay); 284 | return; 285 | } 286 | 287 | if (l && l->isLocked()) { 288 | writeRetry.inc(); 289 | mreq->mutateWriteToRead(); 290 | Time_t nextTry = nextSlot(); 291 | if (nextTry == globalClock) 292 | nextTry++; 293 | doWriteCB::scheduleAbs(nextTry, this, mreq); 294 | return; 295 | } 296 | 297 | GI(l, !l->isLocked()); 298 | 299 | // this should never happen unless this is highest level because 300 | // SMPCache is inclusive of all other caches closer to the 301 | // processor; there is only one case in which this could happen when 302 | // SMPCache is used as an L2: 1) line is written in L1 and scheduled 303 | // to go down to L2 2) line is invalidated in both L1 and L2 3) 304 | // doWrite in L2 is executed after line is invalidated 305 | if(!l && mreq->getMemOperation() == MemWrite) { 306 | mreq->mutateWriteToRead(); 307 | } 308 | 309 | writeMiss.inc(); 310 | 311 | #ifdef SESC_ENERGY 312 | wrEnergy[1]->inc(); 313 | #endif 314 | 315 | if (!mutExclBuffer->issue(addr)) { 316 | mutExclBuffer->addEntry(addr, sendWriteCB::create(this, mreq), 317 | sendWriteCB::create(this, mreq)); 318 | return; 319 | } 320 | 321 | sendWrite(mreq); 322 | } 323 | 324 | void SMPCache::sendWrite(MemRequest* mreq) 325 | { 326 | protocol->write(mreq); 327 | } 328 | 329 | void SMPCache::doWriteBack(PAddr addr) 330 | { 331 | // FIXME: right now we are assuming cache line sizes are same in every cache 332 | 333 | writeBack.inc(); 334 | protocol->sendWriteBack(addr, concludeWriteBackCB::create(this, globalClock)); 335 | } 336 | 337 | void SMPCache::concludeWriteBack(Time_t initialTime) 338 | { 339 | // add here actions that need to be performed after writeback is 340 | // acknoledged by memory 341 | } 342 | 343 | void SMPCache::specialOp(MemRequest *mreq) 344 | { 345 | mreq->goUp(1); 346 | } 347 | 348 | void SMPCache::invalidate(PAddr addr, ushort size, MemObj *oc) 349 | { 350 | Line *l = cache->findLine(addr); 351 | 352 | I(oc); 353 | I(pendInvTable.find(addr) == pendInvTable.end()); 354 | pendInvTable[addr].outsResps = getNumCachesInUpperLevels(); 355 | pendInvTable[addr].cb = doInvalidateCB::create(oc, addr, size); 356 | pendInvTable[addr].invalidate = true; 357 | // pendInvTable[addr].writeback = true; 358 | 359 | if (l) 360 | protocol->preInvalidate(l); 361 | 362 | if (!isHighestLevel()) { 363 | invUpperLevel(addr, size, this); 364 | return; 365 | } 366 | 367 | doInvalidate(addr, size); 368 | } 369 | 370 | void SMPCache::doInvalidate(PAddr addr, ushort size) 371 | { 372 | I(pendInvTable.find(addr) != pendInvTable.end()); 373 | CallbackBase *cb = 0; 374 | bool invalidate = false; 375 | bool writeBack = false; 376 | 377 | PendInvTable::iterator it = pendInvTable.find(addr); 378 | Entry *record = &(it->second); 379 | if(--(record->outsResps) <= 0) { 380 | cb = record->cb; 381 | invalidate = record->invalidate; 382 | writeBack = record->writeback; 383 | pendInvTable.erase(addr); 384 | } 385 | 386 | if(invalidate) 387 | realInvalidate(addr, size, writeBack); 388 | 389 | if(cb) 390 | EventScheduler::schedule((TimeDelta_t) 2, cb); 391 | } 392 | 393 | void SMPCache::realInvalidate(PAddr addr, ushort size, bool writeBack) 394 | { 395 | while(size) { 396 | 397 | Line *l = cache->findLine(addr); 398 | 399 | if (l) { 400 | nextSlot(); // counts for occupancy to invalidate line 401 | I(l->isValid()); 402 | if (l->isDirty()) { 403 | invalDirty.inc(); 404 | if(writeBack) 405 | doWriteBack(addr); 406 | } 407 | l->invalidate(); 408 | } 409 | addr += cache->getLineSize(); 410 | size -= cache->getLineSize(); 411 | } 412 | } 413 | 414 | // interface with protocol 415 | 416 | // sends a request to lower level 417 | void SMPCache::sendBelow(SMPMemRequest *sreq) 418 | { 419 | sreq->goDown(missDelay, lowerLevel[0]); 420 | } 421 | 422 | // sends a response to lower level 423 | // writes data back if protocol determines so 424 | void SMPCache::respondBelow(SMPMemRequest *sreq) 425 | { 426 | PAddr addr = sreq->getPAddr(); 427 | 428 | if(sreq->getSupplier() == this && sreq->needsWriteDown()) { 429 | doWriteBack(addr); 430 | } 431 | 432 | lowerLevel[0]->access(sreq); 433 | } 434 | 435 | // receives requests from other caches 436 | void SMPCache::receiveFromBelow(SMPMemRequest *sreq) { 437 | doReceiveFromBelowCB::scheduleAbs(nextSlot() + missDelay, this, sreq); 438 | } 439 | 440 | void SMPCache::doReceiveFromBelow(SMPMemRequest *sreq) 441 | { 442 | MemOperation memOp = sreq->getMemOperation(); 443 | 444 | // request from other caches, need to process them accordingly 445 | 446 | if(memOp == MemRead) { 447 | protocol->readMissHandler(sreq); 448 | return; 449 | } 450 | 451 | if(memOp == MemReadW) { 452 | if(sreq->needsData()) 453 | protocol->writeMissHandler(sreq); 454 | else 455 | protocol->invalidateHandler(sreq); 456 | return; 457 | } 458 | 459 | if(memOp == MemWrite) { 460 | I(!sreq->needsData()); 461 | protocol->invalidateHandler(sreq); 462 | return; 463 | } 464 | 465 | I(0); // this routine should not be called for any other memory request 466 | } 467 | 468 | void SMPCache::returnAccess(MemRequest *mreq) 469 | { 470 | SMPMemRequest *sreq = static_cast(mreq); 471 | MemOperation memOp = sreq->getMemOperation(); 472 | 473 | if(sreq->getRequestor() == this) { 474 | // request from this cache (response is ready) 475 | 476 | if(memOp == MemRead) { 477 | protocol->readMissAckHandler(sreq); 478 | } 479 | else if(memOp == MemReadW) { 480 | if(sreq->needsData()) { 481 | protocol->writeMissAckHandler(sreq); 482 | } else { 483 | I(sreq->needsSnoop()); 484 | protocol->invalidateAckHandler(sreq); 485 | } 486 | } 487 | else if(memOp == MemWrite) { 488 | I(!sreq->needsData()); 489 | I(sreq->needsSnoop()); 490 | protocol->invalidateAckHandler(sreq); 491 | } 492 | else if(memOp == MemPush) { 493 | protocol->writeBackAckHandler(sreq); 494 | } 495 | } else { 496 | receiveFromBelow(sreq); 497 | } 498 | } 499 | 500 | void SMPCache::concludeAccess(MemRequest *mreq) 501 | { 502 | PAddr addr = mreq->getPAddr(); 503 | 504 | mreq->mutateReadToWrite(); /* 505 | Hack justification: It makes things much 506 | nicer if we can call mutateWriteToRead() 507 | in write() if the line is displaced from 508 | the cache between the time the write is 509 | processed in the L1 to the time it is 510 | processed in the L2. 511 | 512 | BUT from the L2, we don't call 513 | mreq->goDown(), so we can't rely on 514 | mreq->goUp() to restore the memOp. 515 | */ 516 | mreq->goUp(0); 517 | 518 | outsReq->retire(addr); 519 | mutExclBuffer->retire(addr); 520 | 521 | } 522 | 523 | SMPCache::Line *SMPCache::allocateLine(PAddr addr, CallbackBase *cb, 524 | bool canDestroyCB) 525 | { 526 | PAddr rpl_addr = 0; 527 | I(cache->findLineDebug(addr) == 0); 528 | Line *l = cache->findLine2Replace(addr); 529 | 530 | if(!l) { 531 | // need to schedule allocate line for next cycle 532 | doAllocateLineCB::scheduleAbs(globalClock+1, this, addr, 0, cb); 533 | return 0; 534 | } 535 | 536 | rpl_addr = cache->calcAddr4Tag(l->getTag()); 537 | lineFill.inc(); 538 | 539 | nextSlot(); // have to do an access to check which line is free 540 | 541 | if(!l->isValid()) { 542 | if(canDestroyCB) 543 | cb->destroy(); 544 | l->setTag(cache->calcTag(addr)); 545 | return l; 546 | } 547 | 548 | if(isHighestLevel()) { 549 | if(l->isDirty()) { 550 | allocDirty.inc(); 551 | doWriteBack(rpl_addr); 552 | } 553 | 554 | if(canDestroyCB) 555 | cb->destroy(); 556 | l->invalidate(); 557 | l->setTag(cache->calcTag(addr)); 558 | return l; 559 | } 560 | 561 | I(pendInvTable.find(rpl_addr) == pendInvTable.end()); 562 | pendInvTable[rpl_addr].outsResps = getNumCachesInUpperLevels(); 563 | pendInvTable[rpl_addr].cb = doAllocateLineCB::create(this, addr, rpl_addr, cb); 564 | pendInvTable[rpl_addr].invalidate = false; 565 | pendInvTable[rpl_addr].writeback = true; 566 | 567 | protocol->preInvalidate(l); 568 | 569 | invUpperLevel(rpl_addr, cache->getLineSize(), this); 570 | 571 | return 0; 572 | } 573 | 574 | void SMPCache::doAllocateLine(PAddr addr, PAddr rpl_addr, CallbackBase *cb) 575 | { 576 | // this is very dangerous (don't do it at home) if rpl_addr is zero, 577 | // it means allocateLine was not able to allocate a line at its last 578 | // try probably because all lines in the set were 579 | // locked. allocateLine has scheduled a callback to doAllocateLine 580 | // in the next cycle, with rpl_addr zero. The code below will call 581 | // allocateLine again, which will schedule another doAllocateLine if 582 | // necessary. If that happens, allocateLine will return 0, which 583 | // means doAllocateLine shouldn't do anything else. If allocateLine 584 | // returns a line, then the line was successfully allocated, and all 585 | // that's left is to call the callback allocateLine has initially 586 | // received as a parameter 587 | if(!rpl_addr) { 588 | Line *l = allocateLine(addr, cb, false); 589 | 590 | if(l) { 591 | I(cb); 592 | l->setTag(calcTag(addr)); 593 | l->changeStateTo(SMP_TRANS_RSV); 594 | cb->call(); 595 | } 596 | 597 | return; 598 | } 599 | 600 | Line *l = cache->findLine(rpl_addr); 601 | I(l && l->isLocked()); 602 | 603 | if(l->isDirty()) { 604 | allocDirty.inc(); 605 | doWriteBack(rpl_addr); 606 | } 607 | 608 | I(cb); 609 | l->setTag(cache->calcTag(addr)); 610 | l->changeStateTo(SMP_TRANS_RSV); 611 | cb->call(); 612 | } 613 | 614 | SMPCache::Line *SMPCache::getLine(PAddr addr) 615 | { 616 | nextSlot(); 617 | return cache->findLine(addr); 618 | } 619 | 620 | void SMPCache::writeLine(PAddr addr) { 621 | Line *l = cache->writeLine(addr); 622 | I(l); 623 | } 624 | 625 | void SMPCache::invalidateLine(PAddr addr, CallbackBase *cb, bool writeBack) 626 | { 627 | Line *l = cache->findLine(addr); 628 | 629 | I(l); 630 | 631 | I(pendInvTable.find(addr) == pendInvTable.end()); 632 | pendInvTable[addr].outsResps = getNumCachesInUpperLevels(); 633 | pendInvTable[addr].cb = cb; 634 | pendInvTable[addr].invalidate = true; 635 | pendInvTable[addr].writeback = writeBack; 636 | 637 | protocol->preInvalidate(l); 638 | 639 | if(!isHighestLevel()) { 640 | invUpperLevel(addr, cache->getLineSize(), this); 641 | return; 642 | } 643 | 644 | doInvalidate(addr, cache->getLineSize()); 645 | } 646 | 647 | #ifdef SESC_SMP_DEBUG 648 | void SMPCache::inclusionCheck(PAddr addr) { 649 | const LevelType* la = getUpperLevel(); 650 | MemObj* c = (*la)[0]; 651 | 652 | const LevelType* lb = c->getUpperLevel(); 653 | MemObj* cc = (*lb)[0]; 654 | 655 | I(!((Cache*)cc)->isInCache(addr)); 656 | } 657 | #endif 658 | -------------------------------------------------------------------------------- /Project2/SMPCache.h: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Karin Strauss 6 | 7 | This file is part of SESC. 8 | 9 | SESC is free software; you can redistribute it and/or modify it under the terms 10 | of the GNU General Public License as published by the Free Software Foundation; 11 | either version 2, or (at your option) any later version. 12 | 13 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License along with 18 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 19 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 | */ 21 | 22 | #ifndef SMPCACHE_H 23 | #define SMPCACHE_H 24 | 25 | #include "libcore/MemObj.h" 26 | #include "SMemorySystem.h" 27 | #include "SMPProtocol.h" 28 | #include "SMPMemRequest.h" 29 | #include "SMPCacheState.h" 30 | #include "SMPSystemBus.h" 31 | #include "MSHR.h" 32 | #include "Port.h" 33 | 34 | #ifdef SESC_ENERGY 35 | #include "GEnergy.h" 36 | #endif 37 | 38 | #include "vector" 39 | #include "estl.h" 40 | 41 | class SMPCache : public MemObj { 42 | public: 43 | typedef CacheGeneric CacheType; 44 | typedef CacheGeneric::CacheLine Line; 45 | 46 | private: 47 | protected: 48 | CacheType *cache; 49 | 50 | PortGeneric *cachePort; 51 | TimeDelta_t missDelay; 52 | TimeDelta_t hitDelay; 53 | 54 | MSHR *outsReq; // buffer for requests coming from upper levels 55 | static MSHR *mutExclBuffer; 56 | 57 | class Entry { 58 | public: 59 | int32_t outsResps; // outstanding responses: number of caches 60 | // that still need to acknowledge invalidates 61 | bool invalidate; 62 | bool writeback; 63 | CallbackBase *cb; 64 | Entry() { 65 | outsResps = 0; 66 | cb = 0; 67 | invalidate = false; 68 | writeback = false; 69 | } 70 | }; 71 | 72 | typedef HASH_MAP PendInvTable; 73 | 74 | PendInvTable pendInvTable; // pending invalidate table 75 | 76 | // BEGIN statistics 77 | GStatsCntr readHit; 78 | GStatsCntr writeHit; 79 | GStatsCntr readMiss; 80 | GStatsCntr writeMiss; 81 | GStatsCntr readHalfMiss; // attention: these half misses have a != semantic 82 | GStatsCntr writeHalfMiss; // than Cache.cpp: these counts are included in 83 | // other counters because MSHR is used differently 84 | GStatsCntr writeBack; 85 | GStatsCntr linePush; 86 | GStatsCntr lineFill; 87 | GStatsCntr readRetry; 88 | GStatsCntr writeRetry; 89 | 90 | GStatsCntr invalDirty; 91 | GStatsCntr allocDirty; 92 | 93 | #ifdef SESC_ENERGY 94 | static unsigned cacheID; 95 | unsigned myID; 96 | GStatsEnergy *rdEnergy[2]; // 0 hit, 1 miss 97 | GStatsEnergy *wrEnergy[2]; // 0 hit, 1 miss 98 | #endif 99 | 100 | // END statistics 101 | 102 | SMPProtocol *protocol; 103 | 104 | // interface with upper level 105 | void read(MemRequest *mreq); 106 | void write(MemRequest *mreq); 107 | void pushline(MemRequest *mreq); 108 | void specialOp(MemRequest *mreq); 109 | 110 | typedef CallbackMember1 readCB; 112 | typedef CallbackMember1 writeCB; 114 | typedef CallbackMember1 specialOpCB; 116 | 117 | // port usage accounting 118 | Time_t nextSlot() { 119 | return cachePort->nextSlot(); 120 | } 121 | 122 | // local routines 123 | void doRead(MemRequest *mreq); 124 | void doWrite(MemRequest *mreq); 125 | void doPushLine(MemRequest *mreq); 126 | void doWriteBack(PAddr addr); 127 | void concludeWriteBack(Time_t initialTime); 128 | void sendRead(MemRequest* mreq); 129 | void sendWrite(MemRequest* mreq); 130 | 131 | typedef CallbackMember1 doReadCB; 133 | typedef CallbackMember1 doWriteCB; 135 | typedef CallbackMember1 doPushLineCB; 137 | typedef CallbackMember1 sendReadCB; 139 | typedef CallbackMember1 sendWriteCB; 141 | typedef CallbackMember1 concludeWriteBackCB; 143 | 144 | public: 145 | SMPCache(SMemorySystem *gms, const char *section, const char *name); 146 | ~SMPCache(); 147 | 148 | // BEGIN MemObj interface 149 | 150 | bool isCache() const { 151 | return true; 152 | } 153 | //const bool isCache() const { return true; } 154 | 155 | // port availability 156 | Time_t getNextFreeCycle() const; 157 | 158 | // interface with upper level 159 | bool canAcceptStore(PAddr addr); 160 | void access(MemRequest *mreq); 161 | 162 | // interface with lower level 163 | void returnAccess(MemRequest *mreq); 164 | 165 | void invalidate(PAddr addr, ushort size, MemObj *oc); 166 | void doInvalidate(PAddr addr, ushort size); 167 | void realInvalidate(PAddr addr, ushort size, bool writeBack); 168 | 169 | // END MemObj interface 170 | 171 | // BEGIN protocol interface 172 | 173 | // interface used by protocol to access lower level 174 | void sendBelow(SMPMemRequest *sreq); 175 | void respondBelow(SMPMemRequest *sreq); 176 | void receiveFromBelow(SMPMemRequest *sreq); 177 | void doReceiveFromBelow(SMPMemRequest *sreq); 178 | 179 | typedef CallbackMember1 doReceiveFromBelowCB; 181 | 182 | // interface used by protocol to access upper level 183 | void concludeAccess(MemRequest *mreq); 184 | 185 | // interface used by protocol to operate on cache lines 186 | Line *getLine(PAddr addr); 187 | void writeLine(PAddr addr); 188 | void invalidateLine(PAddr addr, CallbackBase *cb, bool writeBack = false); 189 | Line *allocateLine(PAddr addr, CallbackBase *cb, bool canDestroyCB = true); 190 | void doAllocateLine(PAddr addr, PAddr rpl_addr, CallbackBase *cb); 191 | 192 | typedef CallbackMember3 doAllocateLineCB; 194 | 195 | PAddr calcTag(PAddr addr) { 196 | return cache->calcTag(addr); 197 | } 198 | 199 | // END protocol interface 200 | 201 | // debug function 202 | #ifdef SESC_SMP_DEBUG 203 | Line* findLine(PAddr addr) { 204 | return cache->findLine(addr); 205 | } 206 | void inclusionCheck(PAddr addr); 207 | #endif 208 | }; 209 | 210 | 211 | #endif // SMPCACHE_H 212 | -------------------------------------------------------------------------------- /Project2/sesc_fmm.mipseb.3CycL1: -------------------------------------------------------------------------------- 1 | #BEGIN Configuration used. Extracted from "/home/cs6290/sesc/confs/cmp4-noc.conf": 2 | cpucore[0:3]='issueX' 3 | NoMigration=true 4 | pageSize =4096 5 | procsPerNode=4 6 | technology='techParam' 7 | [BPredIssueX] 8 | Metasize =2048 9 | MetaBits =2 10 | l2Bits =1 11 | btbAssoc =2 12 | l2size =2048 13 | btbBsize =1 14 | btbSize =256 15 | localSize =2048 16 | btbReplPolicy='LRU' 17 | localBits =2 18 | BTACDelay =0 19 | historySize=8 20 | type ='Hybrid' 21 | rasSize =32 22 | [L2Slice] 23 | numPorts =2 24 | assoc =16 25 | numPortsDir=1 26 | inclusive =false 27 | writePolicy='WB' 28 | size =1048576 29 | deviceType='slicecache' 30 | hitDelayDir=1 31 | MSHR ='L2MSHR' 32 | missDelay =12 33 | lowerLevel="Router RTR sharedBy 1" 34 | portOccp =1 35 | replPolicy='LRU' 36 | hitDelay =12 37 | portOccpDir=1 38 | bsize =64 39 | [FPClusterIssueX] 40 | fpDivLat =20 41 | wakeupDelay=2 42 | schedPortOccp=1 43 | fpMultUnit='FPIssueX' 44 | recycleAt ='Execute' 45 | wakeUpPortOccp=1 46 | fpALUUnit ='FPIssueX' 47 | fpDivUnit ='FPIssueX' 48 | schedDelay=1 49 | fpALULat =1 50 | fpMultLat =8 51 | wakeUpNumPorts=4 52 | winSize =16 53 | schedNumPorts=4 54 | [issueX] 55 | renameDelay=1 56 | frequency =1.000000e+09 57 | bpred ='BPredIssueX' 58 | interClusterLat=2 59 | dtlb ='FXDTLB' 60 | maxBranches=32 61 | intRegs =64 62 | fetchWidth=2 63 | instQueueSize=32 64 | itlb ='FXITLB' 65 | bb4Cycle =1 66 | decodeDelay=2 67 | dataSource="DMemory DL1" 68 | inorder =false 69 | enableICache=true 70 | retireWidth=2 71 | robSize =64 72 | maxLoads =44 73 | instrSource="IMemory IL1" 74 | fpRegs =64 75 | maxIRequests=4 76 | issueWidth=2 77 | regFileDelay=1 78 | OSType ='dummy' 79 | stForwardDelay=1 80 | cluster[1:1]='FPClusterIssueX' 81 | cluster ='FXClusterIssueX' 82 | maxStores =36 83 | [NOC] 84 | booksim_output='booksim.log' 85 | deviceType='booksim' 86 | booksim_sample=1000000 87 | booksim_config='mesh22.booksim' 88 | lowerLevel="MemoryCtrl MemCtrl shared" 89 | [FXITLB] 90 | size =512 91 | assoc =4 92 | replPolicy='LRU' 93 | bsize =8 94 | deviceType='cache' 95 | [DMemory] 96 | bsize =64 97 | hitDelay =3 98 | deviceType='smpcache' 99 | assoc =4 100 | lowerLevel="Router RTR sharedBy 1" 101 | sideLowerLevel="L2Slice L2S" 102 | MSHR ='DMSHR' 103 | size =32768 104 | portOccp =1 105 | protocol ='DMESI' 106 | missDelay =3 107 | numPorts =2 108 | replPolicy='LRU' 109 | [MemoryCtrl] 110 | numPorts =8 111 | lowerLevel="MemoryBus MemoryBus" 112 | delay =1 113 | deviceType='memoryController' 114 | portOccp =1 115 | [Memory] 116 | size =64 117 | replPolicy='LRU' 118 | MSHR ='NoMSHR' 119 | portOccp =1 120 | assoc =1 121 | bsize =64 122 | deviceType='niceCache' 123 | numPorts =1 124 | lowerLevel='voidDevice' 125 | missDelay =10000 126 | hitDelay =200 127 | [IMemory] 128 | lowerLevel="Router RTR sharedBy 1" 129 | bsize =64 130 | protocol ='DMESI' 131 | portOccp =1 132 | size =32768 133 | MSHR ='iMSHR' 134 | hitDelay =1 135 | replPolicy='LRU' 136 | assoc =4 137 | numPorts =1 138 | deviceType='icache' 139 | sideLowerLevel='' 140 | missDelay =1 141 | [MemoryBus] 142 | lowerLevel="Memory Memory" 143 | deviceType='bus' 144 | numPorts =8 145 | portOccp =8 146 | delay =5 147 | [FXDTLB] 148 | deviceType='cache' 149 | bsize =8 150 | assoc =4 151 | replPolicy='LRU' 152 | size =512 153 | [FXClusterIssueX] 154 | wakeUpPortOccp=1 155 | iBJUnit ='ALUIssueX' 156 | iStoreUnit='LDSTIssueX' 157 | iDivLat =12 158 | winSize =56 159 | iALUUnit ='ALUIssueX' 160 | iALULat =1 161 | schedNumPorts=4 162 | schedDelay=1 163 | iLoadLat =1 164 | iLoadUnit ='LDSTIssueX' 165 | iMultLat =4 166 | wakeUpNumPorts=4 167 | iBJLat =1 168 | iStoreLat =1 169 | iMultUnit ='ALUIssueX' 170 | iDivUnit ='ALUIssueX' 171 | recycleAt ='Execute' 172 | schedPortOccp=1 173 | wakeupDelay=2 174 | [NoMSHR] 175 | bsize =64 176 | size =128 177 | type ='none' 178 | [L2MSHR] 179 | bsize =64 180 | size =64 181 | type ='single' 182 | [DMSHR] 183 | bsize =64 184 | type ='single' 185 | size =64 186 | [Router] 187 | dimY =2 188 | numPorts =2 189 | deviceType='router' 190 | lowerLevel="NOC NOC shared" 191 | portOccp =1 192 | delay =1 193 | dimX =2 194 | [iMSHR] 195 | type ='single' 196 | size =32 197 | bsize =64 198 | [FPIssueX] 199 | Num =2 200 | Occ =1 201 | [voidDevice] 202 | deviceType='void' 203 | [LDSTIssueX] 204 | Occ =1 205 | Num =1 206 | [FileSys] 207 | mount ='/bin=/mipsroot/tools/bin:/lib=/mipsroot/tools/lib:/tools=/mipsroot/tools' 208 | [ALUIssueX] 209 | Num =1 210 | Occ =1 211 | [techParam] 212 | frequency =1.000000e+09 213 | #END Configuration used. Extracted from "/home/cs6290/sesc/confs/cmp4-noc.conf": 214 | OSSim:beginTime=Sun Oct 22 01:46:10 2017 215 | 216 | OSSim:bench=/home/cs6290/sesc/sesc.opt -f 3CycL1 -c /home/cs6290/sesc/confs/cmp4-noc.conf -iInput/input.256 -ofmm.out -efmm.err fmm.mipseb -p 1 217 | OSSim:benchName=fmm.mipseb 218 | ProcessId(0):totalTime=16444067:waitTime=0:spawnTime=0:exitTime=16444067:Switchs=1 219 | ProcessId(0):cpu=0:migrable=false:pinned=true:pid=0:ppid=-1:parentId=-1 220 | ProcessId:nSwitchs=1:nSpawns=0:nGradInsts=13743661:nWPathInsts=0 221 | Proc(0):clockTicks=16444090 222 | Proc(1):clockTicks=0 223 | Proc(2):clockTicks=0 224 | Proc(3):clockTicks=0 225 | OSSim:reportName=Final 226 | OSSim:msecs= 30.75:nCPUs=4:nCycles=16444091 227 | OSSim:pseudoreset=0 228 | BEGIN GStats::report Final 229 | Read_U=0 230 | Read_S=0 231 | Read_E=0 232 | Read_bS=0 233 | Read_bE=0 234 | Read_bS_H=0 235 | Read_bE_H=0 236 | Write_U=0 237 | Write_S=0 238 | Write_E=0 239 | Write_bS=0 240 | Write_bE=0 241 | Write_bS_H=0 242 | Write_bE_H=0 243 | P(0)_DL1:readHit=2120837 244 | P(0)_DL1:writeHit=612984 245 | P(0)_DL1:readMiss=23891 246 | P(0)_DL1:writeMiss=5831 247 | P(0)_DL1:readHalfMiss=74244 248 | P(0)_DL1:writeHalfMiss=48585 249 | P(0)_DL1:writeBack=13442 250 | P(0)_DL1:linePush=0 251 | P(0)_DL1:lineFill=29722 252 | P(0)_DL1:readRetry=28 253 | P(0)_DL1:writeRetry=0 254 | P(0)_DL1:invalDirty=0 255 | P(0)_DL1:allocDirty=13442 256 | P(0)_RTR_CTRLmsgCntHist(1)=15846 257 | P(0)_RTR_CTRLmsgCntHist(2)=15284 258 | P(0)_RTR_CTRLmsgCntHist(3)=7842 259 | P(0)_RTR_CTRLmsgCntHist_MaxKey=3 260 | P(0)_RTR_CTRLmsgCntHist_Avg=1.794622 261 | P(0)_RTR_CTRLmsgCntHist_Samples=38972 262 | P(0)_RTR_CTRLmsgS1Hist(1)=0 263 | P(0)_RTR_CTRLmsgS1Hist(2)=138434 264 | P(0)_RTR_CTRLmsgS1Hist(3)=94505 265 | P(0)_RTR_CTRLmsgS1Hist_MaxKey=3 266 | P(0)_RTR_CTRLmsgS1Hist_Avg=2.405707 267 | P(0)_RTR_CTRLmsgS1Hist_Samples=232939 268 | P(0)_RTR_CTRLmsgS2Hist(1)=0 269 | P(0)_RTR_CTRLmsgS2Hist(2)=1256896 270 | P(0)_RTR_CTRLmsgS2Hist(3)=1140055 271 | P(0)_RTR_CTRLmsgS2Hist_MaxKey=3 272 | P(0)_RTR_CTRLmsgS2Hist_Avg=2.475627 273 | P(0)_RTR_CTRLmsgS2Hist_Samples=2396951 274 | P(0)_RTR_DATAmsgCntHist(1)=15846 275 | P(0)_RTR_DATAmsgCntHist(2)=15796 276 | P(0)_RTR_DATAmsgCntHist(3)=8098 277 | P(0)_RTR_DATAmsgCntHist_MaxKey=3 278 | P(0)_RTR_DATAmsgCntHist_Avg=1.805033 279 | P(0)_RTR_DATAmsgCntHist_Samples=39740 280 | P(0)_RTR_DATAmsgS1Hist(1)=0 281 | P(0)_RTR_DATAmsgS1Hist(2)=207074 282 | P(0)_RTR_DATAmsgS1Hist(3)=130142 283 | P(0)_RTR_DATAmsgS1Hist_MaxKey=3 284 | P(0)_RTR_DATAmsgS1Hist_Avg=2.385931 285 | P(0)_RTR_DATAmsgS1Hist_Samples=337216 286 | P(0)_RTR_DATAmsgS2Hist(1)=0 287 | P(0)_RTR_DATAmsgS2Hist(2)=2720926 288 | P(0)_RTR_DATAmsgS2Hist(3)=2092608 289 | P(0)_RTR_DATAmsgS2Hist_MaxKey=3 290 | P(0)_RTR_DATAmsgS2Hist_Avg=2.434734 291 | P(0)_RTR_DATAmsgS2Hist_Samples=4813534 292 | NOC_MESH_CTRLmsgCntHist(2)=31080 293 | NOC_MESH_CTRLmsgCntHist(3)=15940 294 | NOC_MESH_CTRLmsgCntHist_MaxKey=3 295 | NOC_MESH_CTRLmsgCntHist_Avg=2.339005 296 | NOC_MESH_CTRLmsgCntHist_Samples=47020 297 | NOC_MESH_CTRLmsgS1Hist(2)=249267 298 | NOC_MESH_CTRLmsgS1Hist(3)=175530 299 | NOC_MESH_CTRLmsgS1Hist_MaxKey=3 300 | NOC_MESH_CTRLmsgS1Hist_Avg=2.413209 301 | NOC_MESH_CTRLmsgS1Hist_Samples=424797 302 | NOC_MESH_CTRLmsgS2Hist(2)=2001155 303 | NOC_MESH_CTRLmsgS2Hist(3)=1933270 304 | NOC_MESH_CTRLmsgS2Hist_MaxKey=3 305 | NOC_MESH_CTRLmsgS2Hist_Avg=2.491373 306 | NOC_MESH_CTRLmsgS2Hist_Samples=3934425 307 | NOC_MESH_DATAmsgCntHist(2)=31080 308 | NOC_MESH_DATAmsgCntHist(3)=15940 309 | NOC_MESH_DATAmsgCntHist_MaxKey=3 310 | NOC_MESH_DATAmsgCntHist_Avg=2.339005 311 | NOC_MESH_DATAmsgCntHist_Samples=47020 312 | NOC_MESH_DATAmsgS1Hist(2)=374590 313 | NOC_MESH_DATAmsgS1Hist(3)=239617 314 | NOC_MESH_DATAmsgS1Hist_MaxKey=3 315 | NOC_MESH_DATAmsgS1Hist_Avg=2.390124 316 | NOC_MESH_DATAmsgS1Hist_Samples=614207 317 | NOC_MESH_DATAmsgS2Hist(2)=4520732 318 | NOC_MESH_DATAmsgS2Hist(3)=3602975 319 | NOC_MESH_DATAmsgS2Hist_MaxKey=3 320 | NOC_MESH_DATAmsgS2Hist_Avg=2.443514 321 | NOC_MESH_DATAmsgS2Hist_Samples=8123707 322 | DataP(0)_MemoryBus_occ:v=0:n=5045 323 | CmdP(0)_MemoryBus_occ:v=0:n=5045 324 | P(0)_Memory:readHalfMiss=0 325 | P(0)_Memory:writeHalfMiss=0 326 | P(0)_Memory:writeMiss=0 327 | P(0)_Memory:readMiss=0 328 | P(0)_Memory:readHit=5045 329 | P(0)_Memory:writeHit=0 330 | P(0)_Memory:writeBack=0 331 | P(0)_Memory:lineFill=0 332 | P(0)_Memory:linePush=0 333 | P(0)_Memory:nForwarded=0 334 | P(0)_Memory:nWBFull=0 335 | P(0)_Memory_avgPendingWrites:v=0:n=0 336 | P(0)_Memory_avgMissLat:v=0:n=0 337 | P(0)_Memory:rejected=0 338 | P(0)_Memory:rejectedHits=0 339 | P(0)_Memory_MSHR0_MSHR:nUse=0 340 | P(0)_Memory_MSHR0_MSHR:nUseReads=0 341 | P(0)_Memory_MSHR0_MSHR:nUseWrites=0 342 | P(0)_Memory_MSHR0_MSHR:nOverflows=0 343 | P(0)_Memory_MSHR0_MSHR_maxUsedEntries:max=0:n=0 344 | P(0)_Memory_MSHR0_MSHR:nCanAccept=0 345 | P(0)_Memory_MSHR0_MSHR:nCanNotAccept=0 346 | P(0)_Memory_MSHR0_MSHR:nCanNotAcceptConv=0 347 | P(0)_Memory_MSHR0_MSHR:blockingCycles_AutoAvg=0.000000 348 | P(0)_Memory_B0:nAccesses=5045 349 | P(0)_Memory_occ:v=0:n=0 350 | P(0)_Memory_B0_occ:v=0:n=0 351 | P(0)_Memory_MSHR_B0_occ:v=0:n=0 352 | P(0)_MemoryBus_AvgTime_MemRead:v=2.5:n=4830 353 | P(0)_MemoryBus_AvgTime_MemWrite:v=0:n=0 354 | P(0)_MemoryBus_AvgTime_MemPush:v=0:n=0 355 | P(0)_MemoryBus_AvgTime_MemReadW:v=2.5:n=5260 356 | MemCtrl_bus_occ:v=0:n=5045 357 | P(0)_RTR_bus_occ:v=0.000137485:n=80009 358 | P(0)_L2S:readHalfMiss=0 359 | P(0)_L2S:writeHalfMiss=0 360 | P(0)_L2S:writeMiss=0 361 | P(0)_L2S:readMiss=1297 362 | P(0)_L2S:readHit=6754 363 | P(0)_L2S:writeHit=0 364 | P(0)_L2S:writeBack=0 365 | P(0)_L2S:lineFill=1297 366 | P(0)_L2S:linePush=7795 367 | P(0)_L2S:nForwarded=0 368 | P(0)_L2S:nWBFull=0 369 | P(0)_L2S_avgPendingWrites:v=0:n=0 370 | P(0)_L2S_avgMissLat:v=210.001:n=1297 371 | P(0)_L2S:rejected=0 372 | P(0)_L2S:rejectedHits=0 373 | P(0)_L2S_DIR_occ:v=0:n=7795 374 | P(0)_L2S_MSHR0_MSHR:nUse=1297 375 | P(0)_L2S_MSHR0_MSHR:nUseReads=1297 376 | P(0)_L2S_MSHR0_MSHR:nUseWrites=0 377 | P(0)_L2S_MSHR0_MSHR:nOverflows=0 378 | P(0)_L2S_MSHR0_MSHR_maxUsedEntries:max=3:n=1297 379 | P(0)_L2S_MSHR0_MSHR:nCanAccept=0 380 | P(0)_L2S_MSHR0_MSHR:nCanNotAccept=0 381 | P(0)_L2S_MSHR0_MSHR:nCanNotAcceptConv=0 382 | P(0)_L2S_MSHR0_MSHR:blockingCycles_AutoAvg=0.000000 383 | P(0)_L2S_MSHR0_MSHR_avgOverflowConsumptions:v=0:n=0 384 | P(0)_L2S_MSHR0_MSHR_maxOutsReqs:max=3:n=1297 385 | P(0)_L2S_MSHR0_MSHR_avgReqsPerLine:v=1:n=1297 386 | P(0)_L2S_MSHR0_MSHR:nIssuesNewEntry=1297 387 | P(0)_L2S_MSHR0_MSHR:nCanNotAcceptSubEntryFull=0 388 | P(0)_L2S_MSHR0_MSHR:nCanNotAcceptTooManyWrites=0 389 | P(0)_L2S_MSHR0_MSHR_avgQueueSize:v=0:n=1297 390 | P(0)_L2S_MSHR0_MSHR_avgWritesPerLine:v=0:n=1297 391 | P(0)_L2S_MSHR0_MSHR_avgWritesPerLineComb:v=0:n=1297 392 | P(0)_L2S_MSHR0_MSHR:nOnlyWrites=0 393 | P(0)_L2S_MSHR0_MSHR:nRetiredEntries=1297 394 | P(0)_L2S_MSHR0_MSHR:nRetiredEntriesWritten=0 395 | P(0)_L2S_B0:nAccesses=0 396 | P(0)_L2S_occ:v=0:n=15846 397 | P(0)_L2S_B0_occ:v=0:n=17143 398 | P(0)_L2S_MSHR_B0_occ:v=0.000257003:n=3891 399 | P(0)_DL1_occ:v=0.0329225:n=2765461 400 | P(0)_DL1_MSHR:nUse=2763543 401 | P(0)_DL1_MSHR:nUseReads=2763543 402 | P(0)_DL1_MSHR:nUseWrites=0 403 | P(0)_DL1_MSHR:nOverflows=32 404 | P(0)_DL1_MSHR_maxUsedEntries:max=13:n=2640746 405 | P(0)_DL1_MSHR:nCanAccept=618815 406 | P(0)_DL1_MSHR:nCanNotAccept=64296 407 | P(0)_DL1_MSHR:nCanNotAcceptConv=0 408 | P(0)_DL1_MSHR:blockingCycles(0)=16379758 409 | P(0)_DL1_MSHR:blockingCycles(1)=64333 410 | P(0)_DL1_MSHR:blockingCycles_AutoAvg=0.000000 411 | P(0)_DL1_MSHR_avgOverflowConsumptions:v=4:n=8 412 | P(0)_DL1_MSHR_maxOutsReqs:max=162:n=2763543 413 | P(0)_DL1_MSHR_avgReqsPerLine:v=1.0465:n=2640746 414 | P(0)_DL1_MSHR:nIssuesNewEntry=2640746 415 | P(0)_DL1_MSHR:nCanNotAcceptSubEntryFull=64266 416 | P(0)_DL1_MSHR:nCanNotAcceptTooManyWrites=0 417 | P(0)_DL1_MSHR_avgQueueSize:v=0.878423:n=2763543 418 | P(0)_DL1_MSHR_avgWritesPerLine:v=0:n=2640746 419 | P(0)_DL1_MSHR_avgWritesPerLineComb:v=0:n=2640746 420 | P(0)_DL1_MSHR:nOnlyWrites=0 421 | P(0)_DL1_MSHR:nRetiredEntries=2640746 422 | P(0)_DL1_MSHR:nRetiredEntriesWritten=0 423 | P(0)_IL1:readHit=7152210 424 | P(0)_IL1:writeHit=0 425 | P(0)_IL1:readMiss=2223 426 | P(0)_IL1:writeMiss=0 427 | P(0)_IL1:readHalfMiss=3955 428 | P(0)_IL1:writeHalfMiss=0 429 | P(0)_IL1:writeBack=0 430 | P(0)_IL1:linePush=0 431 | P(0)_IL1:lineFill=2223 432 | P(0)_IL1:readRetry=0 433 | P(0)_IL1:writeRetry=0 434 | P(0)_IL1:invalDirty=0 435 | P(0)_IL1:allocDirty=0 436 | P(0)_IL1_occ:v=0.00136171:n=7159370 437 | P(0)_IL1_MSHR:nUse=7154433 438 | P(0)_IL1_MSHR:nUseReads=7154433 439 | P(0)_IL1_MSHR:nUseWrites=0 440 | P(0)_IL1_MSHR:nOverflows=0 441 | P(0)_IL1_MSHR_maxUsedEntries:max=4:n=7150478 442 | P(0)_IL1_MSHR:nCanAccept=0 443 | P(0)_IL1_MSHR:nCanNotAccept=0 444 | P(0)_IL1_MSHR:nCanNotAcceptConv=0 445 | P(0)_IL1_MSHR:blockingCycles_AutoAvg=0.000000 446 | P(0)_IL1_MSHR_avgOverflowConsumptions:v=0:n=0 447 | P(0)_IL1_MSHR_maxOutsReqs:max=4:n=7154433 448 | P(0)_IL1_MSHR_avgReqsPerLine:v=1.00055:n=7150478 449 | P(0)_IL1_MSHR:nIssuesNewEntry=7150478 450 | P(0)_IL1_MSHR:nCanNotAcceptSubEntryFull=0 451 | P(0)_IL1_MSHR:nCanNotAcceptTooManyWrites=0 452 | P(0)_IL1_MSHR_avgQueueSize:v=0.00982999:n=7154433 453 | P(0)_IL1_MSHR_avgWritesPerLine:v=0:n=7150478 454 | P(0)_IL1_MSHR_avgWritesPerLineComb:v=0:n=7150478 455 | P(0)_IL1_MSHR:nOnlyWrites=0 456 | P(0)_IL1_MSHR:nRetiredEntries=7150478 457 | P(0)_IL1_MSHR:nRetiredEntriesWritten=0 458 | LDSTQ(0)_ldldViolations=82 459 | LDSTQ(0)_stldViolations=25 460 | LDSTQ(0)_ststViolations=171 461 | LDSTQ(0)_stldForwarding=6952 462 | Proc(0)_FXClusterIssueX:nReplay=4418 463 | Proc(0)_FXClusterIssueX_wakeUp_occ:v=0.0546907:n=14445970 464 | Proc(0)_FXClusterIssueX_sched_occ:v=0.00811616:n=6728057 465 | Proc(0)_FXClusterIssueX_winNotUsed:v=46.6956:n=6728057 466 | ALUIssueX(0)_occ:v=1.03707:n=3875296 467 | LDSTIssueX(0)_occ:v=2.70574:n=3471576 468 | FULoad(0)_ldqNotUsed:v=36.5449:n=2233946 469 | FULoad(0):nForwarded=89218 470 | FUStore(0)_stqNotUsed:v=27.5597:n=618815 471 | FUStore(0):nDeadStore=0 472 | FUStore(0):nFences=0 473 | FUStore(0):fenceStallCycles=0 474 | Proc(0)_FPClusterIssueX:nReplay=0 475 | Proc(0)_FPClusterIssueX_wakeUp_occ:v=0.0399478:n=13041350 476 | Proc(0)_FPClusterIssueX_sched_occ:v=0.00129768:n=7015603 477 | Proc(0)_FPClusterIssueX_winNotUsed:v=1.05714:n=7015603 478 | FPIssueX(0)_occ:v=0.115969:n=7015603 479 | Proc(0)_robUsed:v=34.0849:n=16444090 480 | Processor(0)_noFetch=0 481 | Processor(0)_noFetch2=9289657 482 | ExeEngine(0)_retired:v=0.852918:n=16113694 483 | ExeEngine(0):noRetOtherCause=0 484 | Processor(0):nLocks=0 485 | Processor(0):nLockContCycles=0 486 | ExeEngine(0):nSmallWin=15827692 487 | ExeEngine(0):nSmallROB=1259844 488 | ExeEngine(0):nSmallREG=0 489 | ExeEngine(0):nOutsLoads=0 490 | ExeEngine(0):nOutsStores=99108 491 | ExeEngine(0):nOutsBranches=0 492 | ExeEngine(0):nReplays=0 493 | ExeEngine(0):PortConflict=0 494 | ExeEngine(0):switch=0 495 | ExeEngine(0):noRetSelf_iOpInvalid_NotExecuted=0 496 | ExeEngine(0):noRetSelf_iALU_NotExecuted=227776 497 | ExeEngine(0):noRetSelf_iMult_NotExecuted=442 498 | ExeEngine(0):noRetSelf_iDiv_NotExecuted=2059 499 | ExeEngine(0):noRetSelf_iBJ_NotExecuted=122777 500 | ExeEngine(0):noRetSelf_iLoad_NotExecuted=947563 501 | ExeEngine(0):noRetSelf_iStore_NotExecuted=697234 502 | ExeEngine(0):noRetSelf_fpALU_NotExecuted=2326113 503 | ExeEngine(0):noRetSelf_fpMult_NotExecuted=5050306 504 | ExeEngine(0):noRetSelf_fpDiv_NotExecuted=642338 505 | ExeEngine(0):noRetSelf_iFence_NotExecuted=0 506 | ExeEngine(0):noRetSelf_iLoad_NotFinished=0 507 | ExeEngine(0):noRetSelf_iStore_NoCacheSpace=64296 508 | ExeEngine(0):noRetSelf_iStore_NoCachePorts=3831 509 | ExeEngine(0):noRetSelf_iStore_WaitForFence=0 510 | ExeEngine(0):noRetSelf_iFence_NoCacheSpace=0 511 | ExeEngine(0):noRetSelf_iFence_WaitForFence=0 512 | ExeEngine(0):noRetOther_iOpInvalid_NotExecuted=0 513 | ExeEngine(0):noRetOther_iALU_NotExecuted=175679 514 | ExeEngine(0):noRetOther_iMult_NotExecuted=348 515 | ExeEngine(0):noRetOther_iDiv_NotExecuted=1940 516 | ExeEngine(0):noRetOther_iBJ_NotExecuted=98947 517 | ExeEngine(0):noRetOther_iLoad_NotExecuted=899961 518 | ExeEngine(0):noRetOther_iStore_NotExecuted=597320 519 | ExeEngine(0):noRetOther_fpALU_NotExecuted=1530682 520 | ExeEngine(0):noRetOther_fpMult_NotExecuted=4461021 521 | ExeEngine(0):noRetOther_fpDiv_NotExecuted=563174 522 | ExeEngine(0):noRetOther_iFence_NotExecuted=0 523 | ExeEngine(0):noRetOther_iLoad_NotFinished=0 524 | ExeEngine(0):noRetOther_iStore_NoCacheSpace=64019 525 | ExeEngine(0):noRetOther_iStore_NoCachePorts=923 526 | ExeEngine(0):noRetOther_iStore_WaitForFence=0 527 | ExeEngine(0):noRetOther_iFence_NoCacheSpace=0 528 | ExeEngine(0):noRetOther_iFence_WaitForFence=0 529 | PendingWindow(0)_iOpInvalid:n=0 530 | PendingWindow(0)_iALU:n=2837141 531 | PendingWindow(0)_iComplex:n=562 532 | PendingWindow(0)_iBJ:n=1037593 533 | PendingWindow(0)_iLoad:n=2233946 534 | PendingWindow(0)_iStore:n=618815 535 | PendingWindow(0)_fpALU:n=3369338 536 | PendingWindow(0)_fpComplex:n=3646265 537 | PendingWindow(0)_other:n=0 538 | FetchEngine(0)_avgBranchTime:v=26.7411:n=45118 539 | FetchEngine(0)_avgInstsFetched:v=0:n=0 540 | FetchEngine(0):nDelayInst1=2413008 541 | FetchEngine(0):nDelayInst2=542812 542 | FetchEngine(0):nFetched=13743660 543 | FetchEngine(0):nBTAC=0 544 | FetchEngine(0):szBB(1)=12716 545 | FetchEngine(0):szBB(99)=89 546 | FetchEngine(0):szBB(2)=38495 547 | FetchEngine(0):szBB(3)=39781 548 | FetchEngine(0):szBB(4)=37267 549 | FetchEngine(0):szBB(5)=29795 550 | FetchEngine(0):szBB(6)=180915 551 | FetchEngine(0):szBB(7)=23962 552 | FetchEngine(0):szBB(8)=30500 553 | FetchEngine(0):szBB(106)=256 554 | FetchEngine(0):szBB(9)=19266 555 | FetchEngine(0):szBB(10)=12696 556 | FetchEngine(0):szBB(11)=177775 557 | FetchEngine(0):szBB(12)=5962 558 | FetchEngine(0):szBB(13)=55810 559 | FetchEngine(0):szBB(14)=57277 560 | FetchEngine(0):szBB(15)=6753 561 | FetchEngine(0):szBB(16)=3880 562 | FetchEngine(0):szBB(17)=1425 563 | FetchEngine(0):szBB(18)=917 564 | FetchEngine(0):szBB(213)=50 565 | FetchEngine(0):szBB(19)=1628 566 | FetchEngine(0):szBB(214)=80 567 | FetchEngine(0):szBB(20)=3007 568 | FetchEngine(0):szBB(215)=1 569 | FetchEngine(0):szBB(21)=98818 570 | FetchEngine(0):szBB(22)=3297 571 | FetchEngine(0):szBB(23)=140502 572 | FetchEngine(0):szBB(24)=1764 573 | FetchEngine(0):szBB(219)=70 574 | FetchEngine(0):szBB(25)=9330 575 | FetchEngine(0):szBB(220)=110 576 | FetchEngine(0):szBB(26)=5734 577 | FetchEngine(0):szBB(27)=50 578 | FetchEngine(0):szBB(28)=444 579 | FetchEngine(0):szBB(29)=7751 580 | FetchEngine(0):szBB(30)=353 581 | FetchEngine(0):szBB(31)=169 582 | FetchEngine(0):szBB(32)=247 583 | FetchEngine(0):szBB(33)=4182 584 | FetchEngine(0):szBB(34)=621 585 | FetchEngine(0):szBB(35)=40 586 | FetchEngine(0):szBB(36)=180 587 | FetchEngine(0):szBB(38)=631 588 | FetchEngine(0):szBB(39)=26 589 | FetchEngine(0):szBB(40)=147 590 | FetchEngine(0):szBB(41)=2126 591 | FetchEngine(0):szBB(42)=2796 592 | FetchEngine(0):szBB(43)=23 593 | FetchEngine(0):szBB(44)=109 594 | FetchEngine(0):szBB(45)=392 595 | FetchEngine(0):szBB(46)=502 596 | FetchEngine(0):szBB(47)=354 597 | FetchEngine(0):szBB(48)=1 598 | FetchEngine(0):szBB(56)=14388 599 | FetchEngine(0):szBB(57)=1 600 | FetchEngine(0):szBB(59)=137 601 | FetchEngine(0):szBB(66)=1192 602 | FetchEngine(0):szBB(70)=223 603 | FetchEngine(0):szBB(79)=580 604 | FetchEngine(0):szBB_MaxKey=220 605 | FetchEngine(0):szBB_Avg=13.245706 606 | FetchEngine(0):szBB_Samples=1037593 607 | FetchEngine(0):szFB(200)=1 608 | FetchEngine(0):szFB(1)=3344 609 | FetchEngine(0):szFB(201)=3 610 | FetchEngine(0):szFB(2)=14780 611 | FetchEngine(0):szFB(3)=8674 612 | FetchEngine(0):szFB(4)=18140 613 | FetchEngine(0):szFB(5)=13809 614 | FetchEngine(0):szFB(6)=19643 615 | FetchEngine(0):szFB(7)=18621 616 | FetchEngine(0):szFB(8)=8811 617 | FetchEngine(0):szFB(9)=13081 618 | FetchEngine(0):szFB(10)=14400 619 | FetchEngine(0):szFB(11)=95795 620 | FetchEngine(0):szFB(12)=6521 621 | FetchEngine(0):szFB(13)=48700 622 | FetchEngine(0):szFB(213)=50 623 | FetchEngine(0):szFB(14)=51384 624 | FetchEngine(0):szFB(214)=80 625 | FetchEngine(0):szFB(15)=5153 626 | FetchEngine(0):szFB(215)=1 627 | FetchEngine(0):szFB(16)=2628 628 | FetchEngine(0):szFB(17)=12185 629 | FetchEngine(0):szFB(18)=526 630 | FetchEngine(0):szFB(19)=3047 631 | FetchEngine(0):szFB(219)=70 632 | FetchEngine(0):szFB(20)=721 633 | FetchEngine(0):szFB(220)=110 634 | FetchEngine(0):szFB(21)=95965 635 | FetchEngine(0):szFB(22)=1838 636 | FetchEngine(0):szFB(23)=206572 637 | FetchEngine(0):szFB(24)=1631 638 | FetchEngine(0):szFB(25)=268 639 | FetchEngine(0):szFB(26)=4874 640 | FetchEngine(0):szFB(27)=470 641 | FetchEngine(0):szFB(28)=229 642 | FetchEngine(0):szFB(29)=66 643 | FetchEngine(0):szFB(30)=492 644 | FetchEngine(0):szFB(31)=7931 645 | FetchEngine(0):szFB(32)=3748 646 | FetchEngine(0):szFB(33)=8943 647 | FetchEngine(0):szFB(34)=578 648 | FetchEngine(0):szFB(35)=483 649 | FetchEngine(0):szFB(36)=5199 650 | FetchEngine(0):szFB(37)=46 651 | FetchEngine(0):szFB(38)=3097 652 | FetchEngine(0):szFB(39)=120 653 | FetchEngine(0):szFB(40)=981 654 | FetchEngine(0):szFB(41)=6662 655 | FetchEngine(0):szFB(42)=2795 656 | FetchEngine(0):szFB(43)=345 657 | FetchEngine(0):szFB(44)=107 658 | FetchEngine(0):szFB(45)=913 659 | FetchEngine(0):szFB(46)=493 660 | FetchEngine(0):szFB(47)=2299 661 | FetchEngine(0):szFB(48)=1423 662 | FetchEngine(0):szFB(49)=2327 663 | FetchEngine(0):szFB(50)=1 664 | FetchEngine(0):szFB(51)=3 665 | FetchEngine(0):szFB(52)=126 666 | FetchEngine(0):szFB(53)=106 667 | FetchEngine(0):szFB(54)=3 668 | FetchEngine(0):szFB(55)=7 669 | FetchEngine(0):szFB(56)=13289 670 | FetchEngine(0):szFB(57)=3 671 | FetchEngine(0):szFB(58)=37 672 | FetchEngine(0):szFB(59)=46 673 | FetchEngine(0):szFB(259)=1 674 | FetchEngine(0):szFB(60)=20 675 | FetchEngine(0):szFB(61)=13 676 | FetchEngine(0):szFB(261)=1 677 | FetchEngine(0):szFB(62)=13 678 | FetchEngine(0):szFB(63)=123 679 | FetchEngine(0):szFB(64)=1 680 | FetchEngine(0):szFB(65)=138 681 | FetchEngine(0):szFB(66)=1042 682 | FetchEngine(0):szFB(67)=149 683 | FetchEngine(0):szFB(68)=1 684 | FetchEngine(0):szFB(70)=789 685 | FetchEngine(0):szFB(868)=1 686 | FetchEngine(0):szFB(72)=120 687 | FetchEngine(0):szFB(75)=1109 688 | FetchEngine(0):szFB(877)=1 689 | FetchEngine(0):szFB(83)=1 690 | FetchEngine(0):szFB(86)=3 691 | FetchEngine(0):szFB(87)=350 692 | FetchEngine(0):szFB(88)=12 693 | FetchEngine(0):szFB(89)=9 694 | FetchEngine(0):szFB(90)=3 695 | FetchEngine(0):szFB(91)=1 696 | FetchEngine(0):szFB(93)=580 697 | FetchEngine(0):szFB(892)=1 698 | FetchEngine(0):szFB(96)=1 699 | FetchEngine(0):szFB(103)=3 700 | FetchEngine(0):szFB(104)=5 701 | FetchEngine(0):szFB(901)=1 702 | FetchEngine(0):szFB(110)=37 703 | FetchEngine(0):szFB(114)=4 704 | FetchEngine(0):szFB(115)=3 705 | FetchEngine(0):szFB(116)=6 706 | FetchEngine(0):szFB(117)=130 707 | FetchEngine(0):szFB(130)=68 708 | FetchEngine(0):szFB(131)=52 709 | FetchEngine(0):szFB(138)=132 710 | FetchEngine(0):szFB(141)=114 711 | FetchEngine(0):szFB(143)=3 712 | FetchEngine(0):szFB(144)=1 713 | FetchEngine(0):szFB(147)=1 714 | FetchEngine(0):szFB(151)=15 715 | FetchEngine(0):szFB(174)=2 716 | FetchEngine(0):szFB(175)=1 717 | FetchEngine(0):szFB(177)=3 718 | FetchEngine(0):szFB_MaxKey=901 719 | FetchEngine(0):szFB_Avg=18.576067 720 | FetchEngine(0):szFB_Samples=739858 721 | FetchEngine(0):szFS(1)=565206 722 | FetchEngine(0):szFS(2)=6589227 723 | FetchEngine(0):szFS_MaxKey=2 724 | FetchEngine(0):szFS_Avg=1.920999 725 | FetchEngine(0):szFS_Samples=7154433 726 | BPred(0)_RAS:nHit=41742 727 | BPred(0)_RAS:nMiss=4 728 | BPred(0):nBranches=1037593 729 | BPred(0):nTaken=739858 730 | BPred(0):nMiss=45118 731 | BPred(0)_Hybrid:nHit=950733 732 | BPred(0)_Hybrid:nMiss=45114 733 | BPred(0)_BTB:nHit=677826 734 | BPred(0)_BTB:nMiss=7485 735 | P(1)_DL1:readHit=0 736 | P(1)_DL1:writeHit=0 737 | P(1)_DL1:readMiss=0 738 | P(1)_DL1:writeMiss=0 739 | P(1)_DL1:readHalfMiss=0 740 | P(1)_DL1:writeHalfMiss=0 741 | P(1)_DL1:writeBack=0 742 | P(1)_DL1:linePush=0 743 | P(1)_DL1:lineFill=0 744 | P(1)_DL1:readRetry=0 745 | P(1)_DL1:writeRetry=0 746 | P(1)_DL1:invalDirty=0 747 | P(1)_DL1:allocDirty=0 748 | P(1)_RTR_CTRLmsgCntHist(2)=7900 749 | P(1)_RTR_CTRLmsgCntHist_MaxKey=2 750 | P(1)_RTR_CTRLmsgCntHist_Avg=2.000000 751 | P(1)_RTR_CTRLmsgCntHist_Samples=7900 752 | P(1)_RTR_CTRLmsgS1Hist(2)=72590 753 | P(1)_RTR_CTRLmsgS1Hist_MaxKey=2 754 | P(1)_RTR_CTRLmsgS1Hist_Avg=2.000000 755 | P(1)_RTR_CTRLmsgS1Hist_Samples=72590 756 | P(1)_RTR_CTRLmsgS2Hist(2)=673786 757 | P(1)_RTR_CTRLmsgS2Hist_MaxKey=2 758 | P(1)_RTR_CTRLmsgS2Hist_Avg=2.000000 759 | P(1)_RTR_CTRLmsgS2Hist_Samples=673786 760 | P(1)_RTR_DATAmsgCntHist(2)=7644 761 | P(1)_RTR_DATAmsgCntHist_MaxKey=2 762 | P(1)_RTR_DATAmsgCntHist_Avg=2.000000 763 | P(1)_RTR_DATAmsgCntHist_Samples=7644 764 | P(1)_RTR_DATAmsgS1Hist(2)=101432 765 | P(1)_RTR_DATAmsgS1Hist_MaxKey=2 766 | P(1)_RTR_DATAmsgS1Hist_Avg=2.000000 767 | P(1)_RTR_DATAmsgS1Hist_Samples=101432 768 | P(1)_RTR_DATAmsgS2Hist(2)=1353300 769 | P(1)_RTR_DATAmsgS2Hist_MaxKey=2 770 | P(1)_RTR_DATAmsgS2Hist_Avg=2.000000 771 | P(1)_RTR_DATAmsgS2Hist_Samples=1353300 772 | P(1)_RTR_bus_occ:v=0:n=16794 773 | P(1)_L2S:readHalfMiss=0 774 | P(1)_L2S:writeHalfMiss=0 775 | P(1)_L2S:writeMiss=0 776 | P(1)_L2S:readMiss=1250 777 | P(1)_L2S:readHit=6650 778 | P(1)_L2S:writeHit=0 779 | P(1)_L2S:writeBack=0 780 | P(1)_L2S:lineFill=1250 781 | P(1)_L2S:linePush=7644 782 | P(1)_L2S:nForwarded=0 783 | P(1)_L2S:nWBFull=0 784 | P(1)_L2S_avgPendingWrites:v=0:n=0 785 | P(1)_L2S_avgMissLat:v=210:n=1250 786 | P(1)_L2S:rejected=0 787 | P(1)_L2S:rejectedHits=0 788 | P(1)_L2S_DIR_occ:v=0:n=7644 789 | P(1)_L2S_MSHR0_MSHR:nUse=1250 790 | P(1)_L2S_MSHR0_MSHR:nUseReads=1250 791 | P(1)_L2S_MSHR0_MSHR:nUseWrites=0 792 | P(1)_L2S_MSHR0_MSHR:nOverflows=0 793 | P(1)_L2S_MSHR0_MSHR_maxUsedEntries:max=3:n=1250 794 | P(1)_L2S_MSHR0_MSHR:nCanAccept=0 795 | P(1)_L2S_MSHR0_MSHR:nCanNotAccept=0 796 | P(1)_L2S_MSHR0_MSHR:nCanNotAcceptConv=0 797 | P(1)_L2S_MSHR0_MSHR:blockingCycles_AutoAvg=0.000000 798 | P(1)_L2S_MSHR0_MSHR_avgOverflowConsumptions:v=0:n=0 799 | P(1)_L2S_MSHR0_MSHR_maxOutsReqs:max=3:n=1250 800 | P(1)_L2S_MSHR0_MSHR_avgReqsPerLine:v=1:n=1250 801 | P(1)_L2S_MSHR0_MSHR:nIssuesNewEntry=1250 802 | P(1)_L2S_MSHR0_MSHR:nCanNotAcceptSubEntryFull=0 803 | P(1)_L2S_MSHR0_MSHR:nCanNotAcceptTooManyWrites=0 804 | P(1)_L2S_MSHR0_MSHR_avgQueueSize:v=0:n=1250 805 | P(1)_L2S_MSHR0_MSHR_avgWritesPerLine:v=0:n=1250 806 | P(1)_L2S_MSHR0_MSHR_avgWritesPerLineComb:v=0:n=1250 807 | P(1)_L2S_MSHR0_MSHR:nOnlyWrites=0 808 | P(1)_L2S_MSHR0_MSHR:nRetiredEntries=1250 809 | P(1)_L2S_MSHR0_MSHR:nRetiredEntriesWritten=0 810 | P(1)_L2S_B0:nAccesses=0 811 | P(1)_L2S_occ:v=0:n=15544 812 | P(1)_L2S_B0_occ:v=0:n=16794 813 | P(1)_L2S_MSHR_B0_occ:v=0:n=3750 814 | P(1)_DL1_occ:v=0:n=0 815 | P(1)_DL1_MSHR:nUse=0 816 | P(1)_DL1_MSHR:nUseReads=0 817 | P(1)_DL1_MSHR:nUseWrites=0 818 | P(1)_DL1_MSHR:nOverflows=0 819 | P(1)_DL1_MSHR_maxUsedEntries:max=0:n=0 820 | P(1)_DL1_MSHR:nCanAccept=0 821 | P(1)_DL1_MSHR:nCanNotAccept=0 822 | P(1)_DL1_MSHR:nCanNotAcceptConv=0 823 | P(1)_DL1_MSHR:blockingCycles_AutoAvg=0.000000 824 | P(1)_DL1_MSHR_avgOverflowConsumptions:v=0:n=0 825 | P(1)_DL1_MSHR_maxOutsReqs:max=0:n=0 826 | P(1)_DL1_MSHR_avgReqsPerLine:v=0:n=0 827 | P(1)_DL1_MSHR:nIssuesNewEntry=0 828 | P(1)_DL1_MSHR:nCanNotAcceptSubEntryFull=0 829 | P(1)_DL1_MSHR:nCanNotAcceptTooManyWrites=0 830 | P(1)_DL1_MSHR_avgQueueSize:v=0:n=0 831 | P(1)_DL1_MSHR_avgWritesPerLine:v=0:n=0 832 | P(1)_DL1_MSHR_avgWritesPerLineComb:v=0:n=0 833 | P(1)_DL1_MSHR:nOnlyWrites=0 834 | P(1)_DL1_MSHR:nRetiredEntries=0 835 | P(1)_DL1_MSHR:nRetiredEntriesWritten=0 836 | P(1)_IL1:readHit=0 837 | P(1)_IL1:writeHit=0 838 | P(1)_IL1:readMiss=0 839 | P(1)_IL1:writeMiss=0 840 | P(1)_IL1:readHalfMiss=0 841 | P(1)_IL1:writeHalfMiss=0 842 | P(1)_IL1:writeBack=0 843 | P(1)_IL1:linePush=0 844 | P(1)_IL1:lineFill=0 845 | P(1)_IL1:readRetry=0 846 | P(1)_IL1:writeRetry=0 847 | P(1)_IL1:invalDirty=0 848 | P(1)_IL1:allocDirty=0 849 | P(1)_IL1_occ:v=0:n=0 850 | P(1)_IL1_MSHR:nUse=0 851 | P(1)_IL1_MSHR:nUseReads=0 852 | P(1)_IL1_MSHR:nUseWrites=0 853 | P(1)_IL1_MSHR:nOverflows=0 854 | P(1)_IL1_MSHR_maxUsedEntries:max=0:n=0 855 | P(1)_IL1_MSHR:nCanAccept=0 856 | P(1)_IL1_MSHR:nCanNotAccept=0 857 | P(1)_IL1_MSHR:nCanNotAcceptConv=0 858 | P(1)_IL1_MSHR:blockingCycles_AutoAvg=0.000000 859 | P(1)_IL1_MSHR_avgOverflowConsumptions:v=0:n=0 860 | P(1)_IL1_MSHR_maxOutsReqs:max=0:n=0 861 | P(1)_IL1_MSHR_avgReqsPerLine:v=0:n=0 862 | P(1)_IL1_MSHR:nIssuesNewEntry=0 863 | P(1)_IL1_MSHR:nCanNotAcceptSubEntryFull=0 864 | P(1)_IL1_MSHR:nCanNotAcceptTooManyWrites=0 865 | P(1)_IL1_MSHR_avgQueueSize:v=0:n=0 866 | P(1)_IL1_MSHR_avgWritesPerLine:v=0:n=0 867 | P(1)_IL1_MSHR_avgWritesPerLineComb:v=0:n=0 868 | P(1)_IL1_MSHR:nOnlyWrites=0 869 | P(1)_IL1_MSHR:nRetiredEntries=0 870 | P(1)_IL1_MSHR:nRetiredEntriesWritten=0 871 | LDSTQ(1)_ldldViolations=0 872 | LDSTQ(1)_stldViolations=0 873 | LDSTQ(1)_ststViolations=0 874 | LDSTQ(1)_stldForwarding=0 875 | Proc(1)_FXClusterIssueX:nReplay=0 876 | Proc(1)_FXClusterIssueX_wakeUp_occ:v=0:n=0 877 | Proc(1)_FXClusterIssueX_sched_occ:v=0:n=0 878 | Proc(1)_FXClusterIssueX_winNotUsed:v=0:n=0 879 | ALUIssueX(1)_occ:v=0:n=0 880 | LDSTIssueX(1)_occ:v=0:n=0 881 | FULoad(1)_ldqNotUsed:v=0:n=0 882 | FULoad(1):nForwarded=0 883 | FUStore(1)_stqNotUsed:v=0:n=0 884 | FUStore(1):nDeadStore=0 885 | FUStore(1):nFences=0 886 | FUStore(1):fenceStallCycles=0 887 | Proc(1)_FPClusterIssueX:nReplay=0 888 | Proc(1)_FPClusterIssueX_wakeUp_occ:v=0:n=0 889 | Proc(1)_FPClusterIssueX_sched_occ:v=0:n=0 890 | Proc(1)_FPClusterIssueX_winNotUsed:v=0:n=0 891 | FPIssueX(1)_occ:v=0:n=0 892 | Proc(1)_robUsed:v=0:n=0 893 | Processor(1)_noFetch=0 894 | Processor(1)_noFetch2=0 895 | ExeEngine(1)_retired:v=0:n=0 896 | ExeEngine(1):noRetOtherCause=0 897 | Processor(1):nLocks=0 898 | Processor(1):nLockContCycles=0 899 | ExeEngine(1):nSmallWin=0 900 | ExeEngine(1):nSmallROB=0 901 | ExeEngine(1):nSmallREG=0 902 | ExeEngine(1):nOutsLoads=0 903 | ExeEngine(1):nOutsStores=0 904 | ExeEngine(1):nOutsBranches=0 905 | ExeEngine(1):nReplays=0 906 | ExeEngine(1):PortConflict=0 907 | ExeEngine(1):switch=0 908 | ExeEngine(1):noRetSelf_iOpInvalid_NotExecuted=0 909 | ExeEngine(1):noRetSelf_iALU_NotExecuted=0 910 | ExeEngine(1):noRetSelf_iMult_NotExecuted=0 911 | ExeEngine(1):noRetSelf_iDiv_NotExecuted=0 912 | ExeEngine(1):noRetSelf_iBJ_NotExecuted=0 913 | ExeEngine(1):noRetSelf_iLoad_NotExecuted=0 914 | ExeEngine(1):noRetSelf_iStore_NotExecuted=0 915 | ExeEngine(1):noRetSelf_fpALU_NotExecuted=0 916 | ExeEngine(1):noRetSelf_fpMult_NotExecuted=0 917 | ExeEngine(1):noRetSelf_fpDiv_NotExecuted=0 918 | ExeEngine(1):noRetSelf_iFence_NotExecuted=0 919 | ExeEngine(1):noRetSelf_iLoad_NotFinished=0 920 | ExeEngine(1):noRetSelf_iStore_NoCacheSpace=0 921 | ExeEngine(1):noRetSelf_iStore_NoCachePorts=0 922 | ExeEngine(1):noRetSelf_iStore_WaitForFence=0 923 | ExeEngine(1):noRetSelf_iFence_NoCacheSpace=0 924 | ExeEngine(1):noRetSelf_iFence_WaitForFence=0 925 | ExeEngine(1):noRetOther_iOpInvalid_NotExecuted=0 926 | ExeEngine(1):noRetOther_iALU_NotExecuted=0 927 | ExeEngine(1):noRetOther_iMult_NotExecuted=0 928 | ExeEngine(1):noRetOther_iDiv_NotExecuted=0 929 | ExeEngine(1):noRetOther_iBJ_NotExecuted=0 930 | ExeEngine(1):noRetOther_iLoad_NotExecuted=0 931 | ExeEngine(1):noRetOther_iStore_NotExecuted=0 932 | ExeEngine(1):noRetOther_fpALU_NotExecuted=0 933 | ExeEngine(1):noRetOther_fpMult_NotExecuted=0 934 | ExeEngine(1):noRetOther_fpDiv_NotExecuted=0 935 | ExeEngine(1):noRetOther_iFence_NotExecuted=0 936 | ExeEngine(1):noRetOther_iLoad_NotFinished=0 937 | ExeEngine(1):noRetOther_iStore_NoCacheSpace=0 938 | ExeEngine(1):noRetOther_iStore_NoCachePorts=0 939 | ExeEngine(1):noRetOther_iStore_WaitForFence=0 940 | ExeEngine(1):noRetOther_iFence_NoCacheSpace=0 941 | ExeEngine(1):noRetOther_iFence_WaitForFence=0 942 | PendingWindow(1)_iOpInvalid:n=0 943 | PendingWindow(1)_iALU:n=0 944 | PendingWindow(1)_iComplex:n=0 945 | PendingWindow(1)_iBJ:n=0 946 | PendingWindow(1)_iLoad:n=0 947 | PendingWindow(1)_iStore:n=0 948 | PendingWindow(1)_fpALU:n=0 949 | PendingWindow(1)_fpComplex:n=0 950 | PendingWindow(1)_other:n=0 951 | FetchEngine(1)_avgBranchTime:v=0:n=0 952 | FetchEngine(1)_avgInstsFetched:v=0:n=0 953 | FetchEngine(1):nDelayInst1=0 954 | FetchEngine(1):nDelayInst2=0 955 | FetchEngine(1):nFetched=0 956 | FetchEngine(1):nBTAC=0 957 | FetchEngine(1):szBB_MaxKey=0 958 | FetchEngine(1):szBB_Avg=-nan 959 | FetchEngine(1):szBB_Samples=0 960 | FetchEngine(1):szFB_MaxKey=0 961 | FetchEngine(1):szFB_Avg=-nan 962 | FetchEngine(1):szFB_Samples=0 963 | FetchEngine(1):szFS_MaxKey=0 964 | FetchEngine(1):szFS_Avg=-nan 965 | FetchEngine(1):szFS_Samples=0 966 | BPred(1)_RAS:nHit=0 967 | BPred(1)_RAS:nMiss=0 968 | BPred(1):nBranches=0 969 | BPred(1):nTaken=0 970 | BPred(1):nMiss=0 971 | BPred(1)_Hybrid:nHit=0 972 | BPred(1)_Hybrid:nMiss=0 973 | BPred(1)_BTB:nHit=0 974 | BPred(1)_BTB:nMiss=0 975 | P(2)_DL1:readHit=0 976 | P(2)_DL1:writeHit=0 977 | P(2)_DL1:readMiss=0 978 | P(2)_DL1:writeMiss=0 979 | P(2)_DL1:readHalfMiss=0 980 | P(2)_DL1:writeHalfMiss=0 981 | P(2)_DL1:writeBack=0 982 | P(2)_DL1:linePush=0 983 | P(2)_DL1:lineFill=0 984 | P(2)_DL1:readRetry=0 985 | P(2)_DL1:writeRetry=0 986 | P(2)_DL1:invalDirty=0 987 | P(2)_DL1:allocDirty=0 988 | P(2)_RTR_CTRLmsgCntHist(2)=7896 989 | P(2)_RTR_CTRLmsgCntHist_MaxKey=2 990 | P(2)_RTR_CTRLmsgCntHist_Avg=2.000000 991 | P(2)_RTR_CTRLmsgCntHist_Samples=7896 992 | P(2)_RTR_CTRLmsgS1Hist(2)=71662 993 | P(2)_RTR_CTRLmsgS1Hist_MaxKey=2 994 | P(2)_RTR_CTRLmsgS1Hist_Avg=2.000000 995 | P(2)_RTR_CTRLmsgS1Hist_Samples=71662 996 | P(2)_RTR_CTRLmsgS2Hist(2)=652720 997 | P(2)_RTR_CTRLmsgS2Hist_MaxKey=2 998 | P(2)_RTR_CTRLmsgS2Hist_Avg=2.000000 999 | P(2)_RTR_CTRLmsgS2Hist_Samples=652720 1000 | P(2)_RTR_DATAmsgCntHist(2)=7640 1001 | P(2)_RTR_DATAmsgCntHist_MaxKey=2 1002 | P(2)_RTR_DATAmsgCntHist_Avg=2.000000 1003 | P(2)_RTR_DATAmsgCntHist_Samples=7640 1004 | P(2)_RTR_DATAmsgS1Hist(2)=101867 1005 | P(2)_RTR_DATAmsgS1Hist_MaxKey=2 1006 | P(2)_RTR_DATAmsgS1Hist_Avg=2.000000 1007 | P(2)_RTR_DATAmsgS1Hist_Samples=101867 1008 | P(2)_RTR_DATAmsgS2Hist(2)=1366951 1009 | P(2)_RTR_DATAmsgS2Hist_MaxKey=2 1010 | P(2)_RTR_DATAmsgS2Hist_Avg=2.000000 1011 | P(2)_RTR_DATAmsgS2Hist_Samples=1366951 1012 | P(2)_RTR_bus_occ:v=0:n=16788 1013 | P(2)_L2S:readHalfMiss=0 1014 | P(2)_L2S:writeHalfMiss=0 1015 | P(2)_L2S:writeMiss=0 1016 | P(2)_L2S:readMiss=1252 1017 | P(2)_L2S:readHit=6644 1018 | P(2)_L2S:writeHit=0 1019 | P(2)_L2S:writeBack=0 1020 | P(2)_L2S:lineFill=1252 1021 | P(2)_L2S:linePush=7640 1022 | P(2)_L2S:nForwarded=0 1023 | P(2)_L2S:nWBFull=0 1024 | P(2)_L2S_avgPendingWrites:v=0:n=0 1025 | P(2)_L2S_avgMissLat:v=210:n=1252 1026 | P(2)_L2S:rejected=0 1027 | P(2)_L2S:rejectedHits=0 1028 | P(2)_L2S_DIR_occ:v=0:n=7640 1029 | P(2)_L2S_MSHR0_MSHR:nUse=1252 1030 | P(2)_L2S_MSHR0_MSHR:nUseReads=1252 1031 | P(2)_L2S_MSHR0_MSHR:nUseWrites=0 1032 | P(2)_L2S_MSHR0_MSHR:nOverflows=0 1033 | P(2)_L2S_MSHR0_MSHR_maxUsedEntries:max=3:n=1252 1034 | P(2)_L2S_MSHR0_MSHR:nCanAccept=0 1035 | P(2)_L2S_MSHR0_MSHR:nCanNotAccept=0 1036 | P(2)_L2S_MSHR0_MSHR:nCanNotAcceptConv=0 1037 | P(2)_L2S_MSHR0_MSHR:blockingCycles_AutoAvg=0.000000 1038 | P(2)_L2S_MSHR0_MSHR_avgOverflowConsumptions:v=0:n=0 1039 | P(2)_L2S_MSHR0_MSHR_maxOutsReqs:max=3:n=1252 1040 | P(2)_L2S_MSHR0_MSHR_avgReqsPerLine:v=1:n=1252 1041 | P(2)_L2S_MSHR0_MSHR:nIssuesNewEntry=1252 1042 | P(2)_L2S_MSHR0_MSHR:nCanNotAcceptSubEntryFull=0 1043 | P(2)_L2S_MSHR0_MSHR:nCanNotAcceptTooManyWrites=0 1044 | P(2)_L2S_MSHR0_MSHR_avgQueueSize:v=0:n=1252 1045 | P(2)_L2S_MSHR0_MSHR_avgWritesPerLine:v=0:n=1252 1046 | P(2)_L2S_MSHR0_MSHR_avgWritesPerLineComb:v=0:n=1252 1047 | P(2)_L2S_MSHR0_MSHR:nOnlyWrites=0 1048 | P(2)_L2S_MSHR0_MSHR:nRetiredEntries=1252 1049 | P(2)_L2S_MSHR0_MSHR:nRetiredEntriesWritten=0 1050 | P(2)_L2S_B0:nAccesses=0 1051 | P(2)_L2S_occ:v=0:n=15536 1052 | P(2)_L2S_B0_occ:v=0:n=16788 1053 | P(2)_L2S_MSHR_B0_occ:v=0.000266241:n=3756 1054 | P(2)_DL1_occ:v=0:n=0 1055 | P(2)_DL1_MSHR:nUse=0 1056 | P(2)_DL1_MSHR:nUseReads=0 1057 | P(2)_DL1_MSHR:nUseWrites=0 1058 | P(2)_DL1_MSHR:nOverflows=0 1059 | P(2)_DL1_MSHR_maxUsedEntries:max=0:n=0 1060 | P(2)_DL1_MSHR:nCanAccept=0 1061 | P(2)_DL1_MSHR:nCanNotAccept=0 1062 | P(2)_DL1_MSHR:nCanNotAcceptConv=0 1063 | P(2)_DL1_MSHR:blockingCycles_AutoAvg=0.000000 1064 | P(2)_DL1_MSHR_avgOverflowConsumptions:v=0:n=0 1065 | P(2)_DL1_MSHR_maxOutsReqs:max=0:n=0 1066 | P(2)_DL1_MSHR_avgReqsPerLine:v=0:n=0 1067 | P(2)_DL1_MSHR:nIssuesNewEntry=0 1068 | P(2)_DL1_MSHR:nCanNotAcceptSubEntryFull=0 1069 | P(2)_DL1_MSHR:nCanNotAcceptTooManyWrites=0 1070 | P(2)_DL1_MSHR_avgQueueSize:v=0:n=0 1071 | P(2)_DL1_MSHR_avgWritesPerLine:v=0:n=0 1072 | P(2)_DL1_MSHR_avgWritesPerLineComb:v=0:n=0 1073 | P(2)_DL1_MSHR:nOnlyWrites=0 1074 | P(2)_DL1_MSHR:nRetiredEntries=0 1075 | P(2)_DL1_MSHR:nRetiredEntriesWritten=0 1076 | P(2)_IL1:readHit=0 1077 | P(2)_IL1:writeHit=0 1078 | P(2)_IL1:readMiss=0 1079 | P(2)_IL1:writeMiss=0 1080 | P(2)_IL1:readHalfMiss=0 1081 | P(2)_IL1:writeHalfMiss=0 1082 | P(2)_IL1:writeBack=0 1083 | P(2)_IL1:linePush=0 1084 | P(2)_IL1:lineFill=0 1085 | P(2)_IL1:readRetry=0 1086 | P(2)_IL1:writeRetry=0 1087 | P(2)_IL1:invalDirty=0 1088 | P(2)_IL1:allocDirty=0 1089 | P(2)_IL1_occ:v=0:n=0 1090 | P(2)_IL1_MSHR:nUse=0 1091 | P(2)_IL1_MSHR:nUseReads=0 1092 | P(2)_IL1_MSHR:nUseWrites=0 1093 | P(2)_IL1_MSHR:nOverflows=0 1094 | P(2)_IL1_MSHR_maxUsedEntries:max=0:n=0 1095 | P(2)_IL1_MSHR:nCanAccept=0 1096 | P(2)_IL1_MSHR:nCanNotAccept=0 1097 | P(2)_IL1_MSHR:nCanNotAcceptConv=0 1098 | P(2)_IL1_MSHR:blockingCycles_AutoAvg=0.000000 1099 | P(2)_IL1_MSHR_avgOverflowConsumptions:v=0:n=0 1100 | P(2)_IL1_MSHR_maxOutsReqs:max=0:n=0 1101 | P(2)_IL1_MSHR_avgReqsPerLine:v=0:n=0 1102 | P(2)_IL1_MSHR:nIssuesNewEntry=0 1103 | P(2)_IL1_MSHR:nCanNotAcceptSubEntryFull=0 1104 | P(2)_IL1_MSHR:nCanNotAcceptTooManyWrites=0 1105 | P(2)_IL1_MSHR_avgQueueSize:v=0:n=0 1106 | P(2)_IL1_MSHR_avgWritesPerLine:v=0:n=0 1107 | P(2)_IL1_MSHR_avgWritesPerLineComb:v=0:n=0 1108 | P(2)_IL1_MSHR:nOnlyWrites=0 1109 | P(2)_IL1_MSHR:nRetiredEntries=0 1110 | P(2)_IL1_MSHR:nRetiredEntriesWritten=0 1111 | LDSTQ(2)_ldldViolations=0 1112 | LDSTQ(2)_stldViolations=0 1113 | LDSTQ(2)_ststViolations=0 1114 | LDSTQ(2)_stldForwarding=0 1115 | Proc(2)_FXClusterIssueX:nReplay=0 1116 | Proc(2)_FXClusterIssueX_wakeUp_occ:v=0:n=0 1117 | Proc(2)_FXClusterIssueX_sched_occ:v=0:n=0 1118 | Proc(2)_FXClusterIssueX_winNotUsed:v=0:n=0 1119 | ALUIssueX(2)_occ:v=0:n=0 1120 | LDSTIssueX(2)_occ:v=0:n=0 1121 | FULoad(2)_ldqNotUsed:v=0:n=0 1122 | FULoad(2):nForwarded=0 1123 | FUStore(2)_stqNotUsed:v=0:n=0 1124 | FUStore(2):nDeadStore=0 1125 | FUStore(2):nFences=0 1126 | FUStore(2):fenceStallCycles=0 1127 | Proc(2)_FPClusterIssueX:nReplay=0 1128 | Proc(2)_FPClusterIssueX_wakeUp_occ:v=0:n=0 1129 | Proc(2)_FPClusterIssueX_sched_occ:v=0:n=0 1130 | Proc(2)_FPClusterIssueX_winNotUsed:v=0:n=0 1131 | FPIssueX(2)_occ:v=0:n=0 1132 | Proc(2)_robUsed:v=0:n=0 1133 | Processor(2)_noFetch=0 1134 | Processor(2)_noFetch2=0 1135 | ExeEngine(2)_retired:v=0:n=0 1136 | ExeEngine(2):noRetOtherCause=0 1137 | Processor(2):nLocks=0 1138 | Processor(2):nLockContCycles=0 1139 | ExeEngine(2):nSmallWin=0 1140 | ExeEngine(2):nSmallROB=0 1141 | ExeEngine(2):nSmallREG=0 1142 | ExeEngine(2):nOutsLoads=0 1143 | ExeEngine(2):nOutsStores=0 1144 | ExeEngine(2):nOutsBranches=0 1145 | ExeEngine(2):nReplays=0 1146 | ExeEngine(2):PortConflict=0 1147 | ExeEngine(2):switch=0 1148 | ExeEngine(2):noRetSelf_iOpInvalid_NotExecuted=0 1149 | ExeEngine(2):noRetSelf_iALU_NotExecuted=0 1150 | ExeEngine(2):noRetSelf_iMult_NotExecuted=0 1151 | ExeEngine(2):noRetSelf_iDiv_NotExecuted=0 1152 | ExeEngine(2):noRetSelf_iBJ_NotExecuted=0 1153 | ExeEngine(2):noRetSelf_iLoad_NotExecuted=0 1154 | ExeEngine(2):noRetSelf_iStore_NotExecuted=0 1155 | ExeEngine(2):noRetSelf_fpALU_NotExecuted=0 1156 | ExeEngine(2):noRetSelf_fpMult_NotExecuted=0 1157 | ExeEngine(2):noRetSelf_fpDiv_NotExecuted=0 1158 | ExeEngine(2):noRetSelf_iFence_NotExecuted=0 1159 | ExeEngine(2):noRetSelf_iLoad_NotFinished=0 1160 | ExeEngine(2):noRetSelf_iStore_NoCacheSpace=0 1161 | ExeEngine(2):noRetSelf_iStore_NoCachePorts=0 1162 | ExeEngine(2):noRetSelf_iStore_WaitForFence=0 1163 | ExeEngine(2):noRetSelf_iFence_NoCacheSpace=0 1164 | ExeEngine(2):noRetSelf_iFence_WaitForFence=0 1165 | ExeEngine(2):noRetOther_iOpInvalid_NotExecuted=0 1166 | ExeEngine(2):noRetOther_iALU_NotExecuted=0 1167 | ExeEngine(2):noRetOther_iMult_NotExecuted=0 1168 | ExeEngine(2):noRetOther_iDiv_NotExecuted=0 1169 | ExeEngine(2):noRetOther_iBJ_NotExecuted=0 1170 | ExeEngine(2):noRetOther_iLoad_NotExecuted=0 1171 | ExeEngine(2):noRetOther_iStore_NotExecuted=0 1172 | ExeEngine(2):noRetOther_fpALU_NotExecuted=0 1173 | ExeEngine(2):noRetOther_fpMult_NotExecuted=0 1174 | ExeEngine(2):noRetOther_fpDiv_NotExecuted=0 1175 | ExeEngine(2):noRetOther_iFence_NotExecuted=0 1176 | ExeEngine(2):noRetOther_iLoad_NotFinished=0 1177 | ExeEngine(2):noRetOther_iStore_NoCacheSpace=0 1178 | ExeEngine(2):noRetOther_iStore_NoCachePorts=0 1179 | ExeEngine(2):noRetOther_iStore_WaitForFence=0 1180 | ExeEngine(2):noRetOther_iFence_NoCacheSpace=0 1181 | ExeEngine(2):noRetOther_iFence_WaitForFence=0 1182 | PendingWindow(2)_iOpInvalid:n=0 1183 | PendingWindow(2)_iALU:n=0 1184 | PendingWindow(2)_iComplex:n=0 1185 | PendingWindow(2)_iBJ:n=0 1186 | PendingWindow(2)_iLoad:n=0 1187 | PendingWindow(2)_iStore:n=0 1188 | PendingWindow(2)_fpALU:n=0 1189 | PendingWindow(2)_fpComplex:n=0 1190 | PendingWindow(2)_other:n=0 1191 | FetchEngine(2)_avgBranchTime:v=0:n=0 1192 | FetchEngine(2)_avgInstsFetched:v=0:n=0 1193 | FetchEngine(2):nDelayInst1=0 1194 | FetchEngine(2):nDelayInst2=0 1195 | FetchEngine(2):nFetched=0 1196 | FetchEngine(2):nBTAC=0 1197 | FetchEngine(2):szBB_MaxKey=0 1198 | FetchEngine(2):szBB_Avg=-nan 1199 | FetchEngine(2):szBB_Samples=0 1200 | FetchEngine(2):szFB_MaxKey=0 1201 | FetchEngine(2):szFB_Avg=-nan 1202 | FetchEngine(2):szFB_Samples=0 1203 | FetchEngine(2):szFS_MaxKey=0 1204 | FetchEngine(2):szFS_Avg=-nan 1205 | FetchEngine(2):szFS_Samples=0 1206 | BPred(2)_RAS:nHit=0 1207 | BPred(2)_RAS:nMiss=0 1208 | BPred(2):nBranches=0 1209 | BPred(2):nTaken=0 1210 | BPred(2):nMiss=0 1211 | BPred(2)_Hybrid:nHit=0 1212 | BPred(2)_Hybrid:nMiss=0 1213 | BPred(2)_BTB:nHit=0 1214 | BPred(2)_BTB:nMiss=0 1215 | P(3)_DL1:readHit=0 1216 | P(3)_DL1:writeHit=0 1217 | P(3)_DL1:readMiss=0 1218 | P(3)_DL1:writeMiss=0 1219 | P(3)_DL1:readHalfMiss=0 1220 | P(3)_DL1:writeHalfMiss=0 1221 | P(3)_DL1:writeBack=0 1222 | P(3)_DL1:linePush=0 1223 | P(3)_DL1:lineFill=0 1224 | P(3)_DL1:readRetry=0 1225 | P(3)_DL1:writeRetry=0 1226 | P(3)_DL1:invalDirty=0 1227 | P(3)_DL1:allocDirty=0 1228 | P(3)_RTR_CTRLmsgCntHist(3)=8098 1229 | P(3)_RTR_CTRLmsgCntHist_MaxKey=3 1230 | P(3)_RTR_CTRLmsgCntHist_Avg=3.000000 1231 | P(3)_RTR_CTRLmsgCntHist_Samples=8098 1232 | P(3)_RTR_CTRLmsgS1Hist(3)=97652 1233 | P(3)_RTR_CTRLmsgS1Hist_MaxKey=3 1234 | P(3)_RTR_CTRLmsgS1Hist_Avg=3.000000 1235 | P(3)_RTR_CTRLmsgS1Hist_Samples=97652 1236 | P(3)_RTR_CTRLmsgS2Hist(3)=1179108 1237 | P(3)_RTR_CTRLmsgS2Hist_MaxKey=3 1238 | P(3)_RTR_CTRLmsgS2Hist_Avg=3.000000 1239 | P(3)_RTR_CTRLmsgS2Hist_Samples=1179108 1240 | P(3)_RTR_DATAmsgCntHist(3)=7842 1241 | P(3)_RTR_DATAmsgCntHist_MaxKey=3 1242 | P(3)_RTR_DATAmsgCntHist_Avg=3.000000 1243 | P(3)_RTR_DATAmsgCntHist_Samples=7842 1244 | P(3)_RTR_DATAmsgS1Hist(3)=127520 1245 | P(3)_RTR_DATAmsgS1Hist_MaxKey=3 1246 | P(3)_RTR_DATAmsgS1Hist_Avg=3.000000 1247 | P(3)_RTR_DATAmsgS1Hist_Samples=127520 1248 | P(3)_RTR_DATAmsgS2Hist(3)=2081086 1249 | P(3)_RTR_DATAmsgS2Hist_MaxKey=3 1250 | P(3)_RTR_DATAmsgS2Hist_Avg=3.000000 1251 | P(3)_RTR_DATAmsgS2Hist_Samples=2081086 1252 | P(3)_RTR_bus_occ:v=0:n=17186 1253 | P(3)_L2S:readHalfMiss=0 1254 | P(3)_L2S:writeHalfMiss=0 1255 | P(3)_L2S:writeMiss=0 1256 | P(3)_L2S:readMiss=1246 1257 | P(3)_L2S:readHit=6852 1258 | P(3)_L2S:writeHit=0 1259 | P(3)_L2S:writeBack=0 1260 | P(3)_L2S:lineFill=1246 1261 | P(3)_L2S:linePush=7842 1262 | P(3)_L2S:nForwarded=0 1263 | P(3)_L2S:nWBFull=0 1264 | P(3)_L2S_avgPendingWrites:v=0:n=0 1265 | P(3)_L2S_avgMissLat:v=210:n=1246 1266 | P(3)_L2S:rejected=0 1267 | P(3)_L2S:rejectedHits=0 1268 | P(3)_L2S_DIR_occ:v=0:n=7842 1269 | P(3)_L2S_MSHR0_MSHR:nUse=1246 1270 | P(3)_L2S_MSHR0_MSHR:nUseReads=1246 1271 | P(3)_L2S_MSHR0_MSHR:nUseWrites=0 1272 | P(3)_L2S_MSHR0_MSHR:nOverflows=0 1273 | P(3)_L2S_MSHR0_MSHR_maxUsedEntries:max=4:n=1246 1274 | P(3)_L2S_MSHR0_MSHR:nCanAccept=0 1275 | P(3)_L2S_MSHR0_MSHR:nCanNotAccept=0 1276 | P(3)_L2S_MSHR0_MSHR:nCanNotAcceptConv=0 1277 | P(3)_L2S_MSHR0_MSHR:blockingCycles_AutoAvg=0.000000 1278 | P(3)_L2S_MSHR0_MSHR_avgOverflowConsumptions:v=0:n=0 1279 | P(3)_L2S_MSHR0_MSHR_maxOutsReqs:max=4:n=1246 1280 | P(3)_L2S_MSHR0_MSHR_avgReqsPerLine:v=1:n=1246 1281 | P(3)_L2S_MSHR0_MSHR:nIssuesNewEntry=1246 1282 | P(3)_L2S_MSHR0_MSHR:nCanNotAcceptSubEntryFull=0 1283 | P(3)_L2S_MSHR0_MSHR:nCanNotAcceptTooManyWrites=0 1284 | P(3)_L2S_MSHR0_MSHR_avgQueueSize:v=0:n=1246 1285 | P(3)_L2S_MSHR0_MSHR_avgWritesPerLine:v=0:n=1246 1286 | P(3)_L2S_MSHR0_MSHR_avgWritesPerLineComb:v=0:n=1246 1287 | P(3)_L2S_MSHR0_MSHR:nOnlyWrites=0 1288 | P(3)_L2S_MSHR0_MSHR:nRetiredEntries=1246 1289 | P(3)_L2S_MSHR0_MSHR:nRetiredEntriesWritten=0 1290 | P(3)_L2S_B0:nAccesses=0 1291 | P(3)_L2S_occ:v=0:n=15940 1292 | P(3)_L2S_B0_occ:v=0:n=17186 1293 | P(3)_L2S_MSHR_B0_occ:v=0:n=3738 1294 | P(3)_DL1_occ:v=0:n=0 1295 | P(3)_DL1_MSHR:nUse=0 1296 | P(3)_DL1_MSHR:nUseReads=0 1297 | P(3)_DL1_MSHR:nUseWrites=0 1298 | P(3)_DL1_MSHR:nOverflows=0 1299 | P(3)_DL1_MSHR_maxUsedEntries:max=0:n=0 1300 | P(3)_DL1_MSHR:nCanAccept=0 1301 | P(3)_DL1_MSHR:nCanNotAccept=0 1302 | P(3)_DL1_MSHR:nCanNotAcceptConv=0 1303 | P(3)_DL1_MSHR:blockingCycles_AutoAvg=0.000000 1304 | P(3)_DL1_MSHR_avgOverflowConsumptions:v=0:n=0 1305 | P(3)_DL1_MSHR_maxOutsReqs:max=0:n=0 1306 | P(3)_DL1_MSHR_avgReqsPerLine:v=0:n=0 1307 | P(3)_DL1_MSHR:nIssuesNewEntry=0 1308 | P(3)_DL1_MSHR:nCanNotAcceptSubEntryFull=0 1309 | P(3)_DL1_MSHR:nCanNotAcceptTooManyWrites=0 1310 | P(3)_DL1_MSHR_avgQueueSize:v=0:n=0 1311 | P(3)_DL1_MSHR_avgWritesPerLine:v=0:n=0 1312 | P(3)_DL1_MSHR_avgWritesPerLineComb:v=0:n=0 1313 | P(3)_DL1_MSHR:nOnlyWrites=0 1314 | P(3)_DL1_MSHR:nRetiredEntries=0 1315 | P(3)_DL1_MSHR:nRetiredEntriesWritten=0 1316 | P(3)_IL1:readHit=0 1317 | P(3)_IL1:writeHit=0 1318 | P(3)_IL1:readMiss=0 1319 | P(3)_IL1:writeMiss=0 1320 | P(3)_IL1:readHalfMiss=0 1321 | P(3)_IL1:writeHalfMiss=0 1322 | P(3)_IL1:writeBack=0 1323 | P(3)_IL1:linePush=0 1324 | P(3)_IL1:lineFill=0 1325 | P(3)_IL1:readRetry=0 1326 | P(3)_IL1:writeRetry=0 1327 | P(3)_IL1:invalDirty=0 1328 | P(3)_IL1:allocDirty=0 1329 | P(3)_IL1_occ:v=0:n=0 1330 | P(3)_IL1_MSHR:nUse=0 1331 | P(3)_IL1_MSHR:nUseReads=0 1332 | P(3)_IL1_MSHR:nUseWrites=0 1333 | P(3)_IL1_MSHR:nOverflows=0 1334 | P(3)_IL1_MSHR_maxUsedEntries:max=0:n=0 1335 | P(3)_IL1_MSHR:nCanAccept=0 1336 | P(3)_IL1_MSHR:nCanNotAccept=0 1337 | P(3)_IL1_MSHR:nCanNotAcceptConv=0 1338 | P(3)_IL1_MSHR:blockingCycles_AutoAvg=0.000000 1339 | P(3)_IL1_MSHR_avgOverflowConsumptions:v=0:n=0 1340 | P(3)_IL1_MSHR_maxOutsReqs:max=0:n=0 1341 | P(3)_IL1_MSHR_avgReqsPerLine:v=0:n=0 1342 | P(3)_IL1_MSHR:nIssuesNewEntry=0 1343 | P(3)_IL1_MSHR:nCanNotAcceptSubEntryFull=0 1344 | P(3)_IL1_MSHR:nCanNotAcceptTooManyWrites=0 1345 | P(3)_IL1_MSHR_avgQueueSize:v=0:n=0 1346 | P(3)_IL1_MSHR_avgWritesPerLine:v=0:n=0 1347 | P(3)_IL1_MSHR_avgWritesPerLineComb:v=0:n=0 1348 | P(3)_IL1_MSHR:nOnlyWrites=0 1349 | P(3)_IL1_MSHR:nRetiredEntries=0 1350 | P(3)_IL1_MSHR:nRetiredEntriesWritten=0 1351 | LDSTQ(3)_ldldViolations=0 1352 | LDSTQ(3)_stldViolations=0 1353 | LDSTQ(3)_ststViolations=0 1354 | LDSTQ(3)_stldForwarding=0 1355 | Proc(3)_FXClusterIssueX:nReplay=0 1356 | Proc(3)_FXClusterIssueX_wakeUp_occ:v=0:n=0 1357 | Proc(3)_FXClusterIssueX_sched_occ:v=0:n=0 1358 | Proc(3)_FXClusterIssueX_winNotUsed:v=0:n=0 1359 | ALUIssueX(3)_occ:v=0:n=0 1360 | LDSTIssueX(3)_occ:v=0:n=0 1361 | FULoad(3)_ldqNotUsed:v=0:n=0 1362 | FULoad(3):nForwarded=0 1363 | FUStore(3)_stqNotUsed:v=0:n=0 1364 | FUStore(3):nDeadStore=0 1365 | FUStore(3):nFences=0 1366 | FUStore(3):fenceStallCycles=0 1367 | Proc(3)_FPClusterIssueX:nReplay=0 1368 | Proc(3)_FPClusterIssueX_wakeUp_occ:v=0:n=0 1369 | Proc(3)_FPClusterIssueX_sched_occ:v=0:n=0 1370 | Proc(3)_FPClusterIssueX_winNotUsed:v=0:n=0 1371 | FPIssueX(3)_occ:v=0:n=0 1372 | Proc(3)_robUsed:v=0:n=0 1373 | Processor(3)_noFetch=0 1374 | Processor(3)_noFetch2=0 1375 | ExeEngine(3)_retired:v=0:n=0 1376 | ExeEngine(3):noRetOtherCause=0 1377 | Processor(3):nLocks=0 1378 | Processor(3):nLockContCycles=0 1379 | ExeEngine(3):nSmallWin=0 1380 | ExeEngine(3):nSmallROB=0 1381 | ExeEngine(3):nSmallREG=0 1382 | ExeEngine(3):nOutsLoads=0 1383 | ExeEngine(3):nOutsStores=0 1384 | ExeEngine(3):nOutsBranches=0 1385 | ExeEngine(3):nReplays=0 1386 | ExeEngine(3):PortConflict=0 1387 | ExeEngine(3):switch=0 1388 | ExeEngine(3):noRetSelf_iOpInvalid_NotExecuted=0 1389 | ExeEngine(3):noRetSelf_iALU_NotExecuted=0 1390 | ExeEngine(3):noRetSelf_iMult_NotExecuted=0 1391 | ExeEngine(3):noRetSelf_iDiv_NotExecuted=0 1392 | ExeEngine(3):noRetSelf_iBJ_NotExecuted=0 1393 | ExeEngine(3):noRetSelf_iLoad_NotExecuted=0 1394 | ExeEngine(3):noRetSelf_iStore_NotExecuted=0 1395 | ExeEngine(3):noRetSelf_fpALU_NotExecuted=0 1396 | ExeEngine(3):noRetSelf_fpMult_NotExecuted=0 1397 | ExeEngine(3):noRetSelf_fpDiv_NotExecuted=0 1398 | ExeEngine(3):noRetSelf_iFence_NotExecuted=0 1399 | ExeEngine(3):noRetSelf_iLoad_NotFinished=0 1400 | ExeEngine(3):noRetSelf_iStore_NoCacheSpace=0 1401 | ExeEngine(3):noRetSelf_iStore_NoCachePorts=0 1402 | ExeEngine(3):noRetSelf_iStore_WaitForFence=0 1403 | ExeEngine(3):noRetSelf_iFence_NoCacheSpace=0 1404 | ExeEngine(3):noRetSelf_iFence_WaitForFence=0 1405 | ExeEngine(3):noRetOther_iOpInvalid_NotExecuted=0 1406 | ExeEngine(3):noRetOther_iALU_NotExecuted=0 1407 | ExeEngine(3):noRetOther_iMult_NotExecuted=0 1408 | ExeEngine(3):noRetOther_iDiv_NotExecuted=0 1409 | ExeEngine(3):noRetOther_iBJ_NotExecuted=0 1410 | ExeEngine(3):noRetOther_iLoad_NotExecuted=0 1411 | ExeEngine(3):noRetOther_iStore_NotExecuted=0 1412 | ExeEngine(3):noRetOther_fpALU_NotExecuted=0 1413 | ExeEngine(3):noRetOther_fpMult_NotExecuted=0 1414 | ExeEngine(3):noRetOther_fpDiv_NotExecuted=0 1415 | ExeEngine(3):noRetOther_iFence_NotExecuted=0 1416 | ExeEngine(3):noRetOther_iLoad_NotFinished=0 1417 | ExeEngine(3):noRetOther_iStore_NoCacheSpace=0 1418 | ExeEngine(3):noRetOther_iStore_NoCachePorts=0 1419 | ExeEngine(3):noRetOther_iStore_WaitForFence=0 1420 | ExeEngine(3):noRetOther_iFence_NoCacheSpace=0 1421 | ExeEngine(3):noRetOther_iFence_WaitForFence=0 1422 | PendingWindow(3)_iOpInvalid:n=0 1423 | PendingWindow(3)_iALU:n=0 1424 | PendingWindow(3)_iComplex:n=0 1425 | PendingWindow(3)_iBJ:n=0 1426 | PendingWindow(3)_iLoad:n=0 1427 | PendingWindow(3)_iStore:n=0 1428 | PendingWindow(3)_fpALU:n=0 1429 | PendingWindow(3)_fpComplex:n=0 1430 | PendingWindow(3)_other:n=0 1431 | FetchEngine(3)_avgBranchTime:v=0:n=0 1432 | FetchEngine(3)_avgInstsFetched:v=0:n=0 1433 | FetchEngine(3):nDelayInst1=0 1434 | FetchEngine(3):nDelayInst2=0 1435 | FetchEngine(3):nFetched=0 1436 | FetchEngine(3):nBTAC=0 1437 | FetchEngine(3):szBB_MaxKey=0 1438 | FetchEngine(3):szBB_Avg=-nan 1439 | FetchEngine(3):szBB_Samples=0 1440 | FetchEngine(3):szFB_MaxKey=0 1441 | FetchEngine(3):szFB_Avg=-nan 1442 | FetchEngine(3):szFB_Samples=0 1443 | FetchEngine(3):szFS_MaxKey=0 1444 | FetchEngine(3):szFS_Avg=-nan 1445 | FetchEngine(3):szFS_Samples=0 1446 | BPred(3)_RAS:nHit=0 1447 | BPred(3)_RAS:nMiss=0 1448 | BPred(3):nBranches=0 1449 | BPred(3):nTaken=0 1450 | BPred(3):nMiss=0 1451 | BPred(3)_Hybrid:nHit=0 1452 | BPred(3)_Hybrid:nMiss=0 1453 | BPred(3)_BTB:nHit=0 1454 | BPred(3)_BTB:nMiss=0 1455 | END GStats::report Final 1456 | OSSim:endTime=Sun Oct 22 01:46:41 2017 1457 | 1458 | -------------------------------------------------------------------------------- /Project3/CacheCore.h: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Jose Renau 6 | Basilio Fraguela 7 | James Tuck 8 | Milos Prvulovic 9 | Smruti Sarangi 10 | 11 | This file is part of SESC. 12 | 13 | SESC is free software; you can redistribute it and/or modify it under the terms 14 | of the GNU General Public License as published by the Free Software Foundation; 15 | either version 2, or (at your option) any later version. 16 | 17 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 18 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 19 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 20 | 21 | You should have received a copy of the GNU General Public License along with 22 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 23 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 | */ 25 | 26 | #ifndef CACHECORE_H 27 | #define CACHECORE_H 28 | 29 | #include "GEnergy.h" 30 | #include "nanassert.h" 31 | #include "Snippets.h" 32 | #include "GStats.h" 33 | 34 | enum ReplacementPolicy {LRU, RANDOM, NXLRU}; 35 | 36 | #ifdef SESC_ENERGY 37 | template 38 | #else 39 | template 40 | #endif 41 | class CacheGeneric { 42 | private: 43 | static const int32_t STR_BUF_SIZE=1024; 44 | 45 | static PowerGroup getRightStat(const char* type); 46 | 47 | protected: 48 | const uint32_t size; 49 | const uint32_t lineSize; 50 | const uint32_t addrUnit; //Addressable unit: for most caches = 1 byte 51 | const uint32_t assoc; 52 | const uint32_t log2Assoc; 53 | const uint64_t log2AddrLs; 54 | const uint64_t maskAssoc; 55 | const uint32_t sets; 56 | const uint32_t maskSets; 57 | const uint32_t numLines; 58 | 59 | GStatsEnergy *rdEnergy[2]; // 0 hit, 1 miss 60 | GStatsEnergy *wrEnergy[2]; // 0 hit, 1 miss 61 | 62 | //GStatsCntr test; 63 | 64 | bool goodInterface; 65 | 66 | public: 67 | class CacheLine : public State { 68 | public: 69 | // Pure virtual class defines interface 70 | // 71 | // Tag included in state. Accessed through: 72 | // 73 | // Addr_t getTag() const; 74 | // void setTag(Addr_t a); 75 | // void clearTag(); 76 | // 77 | // 78 | // bool isValid() const; 79 | // void invalidate(); 80 | // 81 | // bool isLocked() const; 82 | }; 83 | 84 | // findLine returns a cache line that has tag == addr, NULL otherwise 85 | virtual CacheLine *findLinePrivate(Addr_t addr)=0; 86 | protected: 87 | 88 | CacheGeneric(uint32_t s, uint32_t a, uint32_t b, uint32_t u) 89 | : size(s) 90 | ,lineSize(b) 91 | ,addrUnit(u) 92 | ,assoc(a) 93 | ,log2Assoc(log2i(a)) 94 | ,log2AddrLs(log2i(b/u)) 95 | ,maskAssoc(a-1) 96 | ,sets((s/b)/a) 97 | ,maskSets(sets-1) 98 | ,numLines(s/b) 99 | //,test(":test") 100 | { 101 | // TODO : assoc and sets must be a power of 2 102 | } 103 | 104 | virtual ~CacheGeneric() {} 105 | 106 | GStatsEnergy *getEnergy(const char *section, PowerGroup grp, const char *format, const char *name); 107 | void createStats(const char *section, const char *name); 108 | 109 | public: 110 | // Do not use this interface, use other create 111 | static CacheGeneric *create(int32_t size, int32_t assoc, int32_t blksize, int32_t addrUnit, const char *pStr, bool skew); 112 | static CacheGeneric *create(const char *section, const char *append, const char *format, ...); 113 | void destroy() { 114 | delete this; 115 | } 116 | 117 | // If there are not free lines, it would return an existing cache line unless 118 | // all the possible cache lines are locked State must implement isLocked API 119 | // 120 | // when locked parameter is false, it would try to remove even locked lines 121 | 122 | virtual CacheLine *findLine2Replace(Addr_t addr, bool ignoreLocked=false)=0; 123 | 124 | // TO DELETE if flush from Cache.cpp is cleared. At least it should have a 125 | // cleaner interface so that Cache.cpp does not touch the internals. 126 | // 127 | // Access the line directly without checking TAG 128 | virtual CacheLine *getPLine(uint32_t l) = 0; 129 | 130 | //ALL USERS OF THIS CLASS PLEASE READ: 131 | // 132 | //readLine and writeLine MUST have the same functionality as findLine. The only 133 | //difference is that readLine and writeLine update power consumption 134 | //statistics. So, only use these functions when you want to model a physical 135 | //read or write operation. 136 | 137 | // Use this is for debug checks. Otherwise, a bad interface can be detected 138 | CacheLine *findLineDebug(Addr_t addr) { 139 | IS(goodInterface=true); 140 | CacheLine *line = findLine(addr); 141 | IS(goodInterface=false); 142 | return line; 143 | } 144 | 145 | // Use this when you need to change the line state but 146 | // do not want to account for energy 147 | CacheLine *findLineNoEffect(Addr_t addr) { 148 | IS(goodInterface=true); 149 | CacheLine *line = findLine(addr); 150 | IS(goodInterface=false); 151 | return line; 152 | } 153 | 154 | CacheLine *findLine(Addr_t addr) { 155 | return findLinePrivate(addr); 156 | } 157 | 158 | CacheLine *readLine(Addr_t addr) { 159 | 160 | IS(goodInterface=true); 161 | CacheLine *line = findLine(addr); 162 | IS(goodInterface=false); 163 | 164 | if(!Energy) 165 | return line; 166 | 167 | rdEnergy[line != 0 ? 0 : 1]->inc(); 168 | 169 | return line; 170 | } 171 | 172 | CacheLine *writeLine(Addr_t addr) { 173 | 174 | IS(goodInterface=true); 175 | CacheLine *line = findLine(addr); 176 | IS(goodInterface=false); 177 | 178 | if(!Energy) 179 | return line; 180 | 181 | wrEnergy[line != 0 ? 0 : 1]->inc(); 182 | 183 | return line; 184 | } 185 | 186 | CacheLine *fillLine(Addr_t addr) { 187 | CacheLine *l = findLine2Replace(addr); 188 | if (l==0) 189 | return 0; 190 | 191 | l->setTag(calcTag(addr)); 192 | 193 | return l; 194 | } 195 | 196 | CacheLine *fillLine(Addr_t addr, Addr_t &rplcAddr, bool ignoreLocked=false) { 197 | CacheLine *l = findLine2Replace(addr, ignoreLocked); 198 | rplcAddr = 0; 199 | if (l==0) 200 | return 0; 201 | 202 | Addr_t newTag = calcTag(addr); 203 | if (l->isValid()) { 204 | Addr_t curTag = l->getTag(); 205 | if (curTag != newTag) { 206 | rplcAddr = calcAddr4Tag(curTag); 207 | } 208 | } 209 | 210 | l->setTag(newTag); 211 | 212 | return l; 213 | } 214 | //My code 215 | // CacheLine *getrealline(Addr_t addr) { 216 | // CacheLine *l = 217 | // } 218 | 219 | uint32_t getLineSize() const { 220 | return lineSize; 221 | } 222 | uint32_t getAssoc() const { 223 | return assoc; 224 | } 225 | uint32_t getLog2AddrLs() const { 226 | return log2AddrLs; 227 | } 228 | uint32_t getLog2Assoc() const { 229 | return log2Assoc; 230 | } 231 | uint32_t getMaskSets() const { 232 | return maskSets; 233 | } 234 | uint32_t getNumLines() const { 235 | return numLines; 236 | } 237 | uint32_t getNumSets() const { 238 | return sets; 239 | } 240 | 241 | Addr_t calcTag(Addr_t addr) const { 242 | return (addr >> log2AddrLs); 243 | } 244 | 245 | uint32_t calcSet4Tag(Addr_t tag) const { 246 | return (tag & maskSets); 247 | } 248 | uint32_t calcSet4Addr(Addr_t addr) const { 249 | return calcSet4Tag(calcTag(addr)); 250 | } 251 | 252 | uint32_t calcIndex4Set(uint32_t set) const { 253 | return (set << log2Assoc); 254 | } 255 | uint32_t calcIndex4Tag(uint32_t tag) const { 256 | return calcIndex4Set(calcSet4Tag(tag)); 257 | } 258 | uint32_t calcIndex4Addr(Addr_t addr) const { 259 | return calcIndex4Set(calcSet4Addr(addr)); 260 | } 261 | 262 | Addr_t calcAddr4Tag(Addr_t tag) const { 263 | return (tag << log2AddrLs); 264 | } 265 | }; 266 | 267 | #ifdef SESC_ENERGY 268 | template 269 | #else 270 | template 271 | #endif 272 | class CacheAssoc : public CacheGeneric { 273 | using CacheGeneric::numLines; 274 | using CacheGeneric::assoc; 275 | using CacheGeneric::maskAssoc; 276 | using CacheGeneric::goodInterface; 277 | 278 | private: 279 | public: 280 | typedef typename CacheGeneric::CacheLine Line; 281 | 282 | protected: 283 | 284 | Line *mem; 285 | Line **content; 286 | ushort irand; 287 | ReplacementPolicy policy; 288 | 289 | friend class CacheGeneric; 290 | CacheAssoc(int32_t size, int32_t assoc, int32_t blksize, int32_t addrUnit, const char *pStr); 291 | 292 | Line *findLinePrivate(Addr_t addr); 293 | public: 294 | virtual ~CacheAssoc() { 295 | delete [] content; 296 | delete [] mem; 297 | } 298 | 299 | // TODO: do an iterator. not this junk!! 300 | Line *getPLine(uint32_t l) { 301 | // Lines [l..l+assoc] belong to the same set 302 | I(l 311 | #else 312 | template 313 | #endif 314 | class CacheDM : public CacheGeneric { 315 | using CacheGeneric::numLines; 316 | using CacheGeneric::goodInterface; 317 | 318 | private: 319 | public: 320 | typedef typename CacheGeneric::CacheLine Line; 321 | 322 | protected: 323 | 324 | Line *mem; 325 | Line **content; 326 | 327 | friend class CacheGeneric; 328 | CacheDM(int32_t size, int32_t blksize, int32_t addrUnit, const char *pStr); 329 | 330 | Line *findLinePrivate(Addr_t addr); 331 | public: 332 | virtual ~CacheDM() { 333 | delete [] content; 334 | delete [] mem; 335 | }; 336 | 337 | // TODO: do an iterator. not this junk!! 338 | Line *getPLine(uint32_t l) { 339 | // Lines [l..l+assoc] belong to the same set 340 | I(l 349 | #else 350 | template 351 | #endif 352 | class CacheDMSkew : public CacheGeneric { 353 | using CacheGeneric::numLines; 354 | using CacheGeneric::goodInterface; 355 | 356 | private: 357 | public: 358 | typedef typename CacheGeneric::CacheLine Line; 359 | 360 | protected: 361 | 362 | Line *mem; 363 | Line **content; 364 | 365 | friend class CacheGeneric; 366 | CacheDMSkew(int32_t size, int32_t blksize, int32_t addrUnit, const char *pStr); 367 | 368 | Line *findLinePrivate(Addr_t addr); 369 | public: 370 | virtual ~CacheDMSkew() { 371 | delete [] content; 372 | delete [] mem; 373 | }; 374 | 375 | // TODO: do an iterator. not this junk!! 376 | Line *getPLine(uint32_t l) { 377 | // Lines [l..l+assoc] belong to the same set 378 | I(l 387 | class StateGeneric { 388 | private: 389 | //Addr_t tag; 390 | 391 | public: 392 | Addr_t tag; // My code, Put tag to public 393 | virtual ~StateGeneric() { 394 | tag = 0; 395 | } 396 | 397 | Addr_t getTag() const { 398 | return tag; 399 | } 400 | void setTag(Addr_t a) { 401 | I(a); 402 | tag = a; 403 | } 404 | void clearTag() { 405 | tag = 0; 406 | } 407 | void initialize(void *c) { 408 | clearTag(); 409 | } 410 | 411 | virtual bool isValid() const { 412 | return tag; 413 | } 414 | 415 | virtual void invalidate() { 416 | clearTag(); 417 | } 418 | 419 | virtual bool isLocked() const { 420 | return false; 421 | } 422 | 423 | virtual void dump(const char *str) { 424 | } 425 | }; 426 | 427 | #ifndef CACHECORE_CPP 428 | #include "CacheCore.cpp" 429 | #endif 430 | 431 | #endif // CACHECORE_H 432 | -------------------------------------------------------------------------------- /Project3/PRJ3.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/Project3/PRJ3.docx -------------------------------------------------------------------------------- /Project3/SMPCache.h: -------------------------------------------------------------------------------- 1 | /* 2 | SESC: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Karin Strauss 6 | 7 | This file is part of SESC. 8 | 9 | SESC is free software; you can redistribute it and/or modify it under the terms 10 | of the GNU General Public License as published by the Free Software Foundation; 11 | either version 2, or (at your option) any later version. 12 | 13 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License along with 18 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 19 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 | */ 21 | 22 | #ifndef SMPCACHE_H 23 | #define SMPCACHE_H 24 | 25 | #include "libcore/MemObj.h" 26 | #include "SMemorySystem.h" 27 | #include "SMPProtocol.h" 28 | #include "SMPMemRequest.h" 29 | #include "SMPCacheState.h" 30 | #include "SMPSystemBus.h" 31 | #include "MSHR.h" 32 | #include "Port.h" 33 | #include 34 | #include 35 | 36 | #ifdef SESC_ENERGY 37 | #include "GEnergy.h" 38 | #endif 39 | 40 | #include "vector" 41 | #include "estl.h" 42 | #include 43 | 44 | //My Code 45 | class LRUStack { 46 | std::vector tagList; // It serves as a fully asso cache 47 | uint cacheSize; 48 | 49 | public: 50 | LRUStack(uint size) { 51 | cacheSize = size; 52 | } 53 | 54 | void updateLRUStack(uint32_t tagNumber) { 55 | bool has = false; 56 | uint32_t elementsinFA = tagList.size(); 57 | std::vector::iterator position = tagList.begin(); 58 | for (; position != tagList.end();position++) { 59 | if (*position == tagNumber) { 60 | has = true; 61 | break; 62 | } 63 | } 64 | if (has) { // Update the position of the latest accessed block 65 | tagList.erase(position); 66 | tagList.push_back(tagNumber); 67 | } 68 | else { // The block is not in the list 69 | if (elementsinFA < cacheSize) // The list is not full 70 | tagList.push_back(tagNumber); 71 | else if (elementsinFA == cacheSize) { // The list is full 72 | //std::cout << *(tagList.begin()) << std::endl; 73 | tagList.erase(tagList.begin()); 74 | tagList.push_back(tagNumber); 75 | } 76 | else 77 | std::cout << "Error:LRU Stack Overflow" << std::endl; 78 | } 79 | } 80 | 81 | uint32_t access(uint32_t tagNumber) { 82 | //bool has = false; 83 | uint32_t elementsinFA = tagList.size(); 84 | std::vector::iterator position = tagList.begin(); 85 | for (; position != tagList.end();position++) { 86 | if (*position == tagNumber) { 87 | //has = true; 88 | //std::cout << elementsinFA << std::endl; 89 | return 0;// conf 90 | } 91 | } 92 | //std::cout << elementsinFA << std::endl; 93 | return 1; //cap 94 | } 95 | }; 96 | 97 | 98 | class CacheHelper { 99 | private: 100 | std::set accessed; // The Hash Set is to record the accessed block 101 | char *cacheName; 102 | 103 | public: 104 | LRUStack *lruStack; 105 | 106 | CacheHelper(const char *name) { 107 | cacheName = new char[50]; 108 | strcpy(cacheName, name); 109 | // 32kB size 110 | lruStack = new LRUStack(32*1024/64); 111 | // 2KB size 112 | //lruStack = new LRUStack(2*1024/64); 113 | } 114 | bool checkCompMiss(uint32_t tagNumber) { 115 | if(accessed.find(tagNumber) == accessed.end()) { // THe block first time comes in 116 | accessed.insert(tagNumber); 117 | return true; 118 | } 119 | return false; 120 | } 121 | }; 122 | 123 | 124 | 125 | class SMPCache : public MemObj { 126 | public: 127 | typedef CacheGeneric CacheType; 128 | typedef CacheGeneric::CacheLine Line; 129 | 130 | private: 131 | static const char *cohOutfile; 132 | 133 | void processReply(MemRequest *mreq); 134 | //void resolveSituation(SMPMemRequest *sreq); 135 | protected: 136 | 137 | 138 | CacheType *cache; 139 | CacheHelper *cacheHelper; 140 | std::set *listofInvalidTags; 141 | 142 | PortGeneric *cachePort; 143 | TimeDelta_t missDelay; 144 | TimeDelta_t hitDelay; 145 | 146 | MSHR *outsReq; // buffer for requests coming from upper levels 147 | //static MSHR *mutExclBuffer; 148 | 149 | 150 | class Entry { 151 | public: 152 | int32_t outsResps; // outstanding responses: number of caches 153 | // that still need to acknowledge invalidates 154 | bool invalidate; 155 | bool writeback; 156 | CallbackBase *cb; 157 | Entry() { 158 | outsResps = 0; 159 | cb = 0; 160 | invalidate = false; 161 | writeback = false; 162 | } 163 | }; 164 | 165 | typedef HASH_MAP PendInvTable; 166 | 167 | PendInvTable pendInvTable; // pending invalidate table 168 | 169 | // BEGIN statistics 170 | GStatsCntr readHit; 171 | GStatsCntr writeHit; 172 | GStatsCntr readMiss; 173 | GStatsCntr writeMiss; 174 | GStatsCntr readHalfMiss; // attention: these half misses have a != semantic 175 | GStatsCntr writeHalfMiss; // than Cache.cpp: these counts are included in 176 | // other counters because MSHR is used differently 177 | GStatsCntr writeBack; 178 | GStatsCntr linePush; 179 | GStatsCntr lineFill; 180 | GStatsCntr readRetry; 181 | GStatsCntr writeRetry; 182 | 183 | GStatsCntr invalDirty; 184 | GStatsCntr allocDirty; 185 | // Classification of Misses 186 | GStatsCntr rcompMiss; 187 | GStatsCntr wcompMiss; 188 | GStatsCntr rreplMiss; 189 | GStatsCntr wreplMiss; 190 | GStatsCntr rcoheMiss; 191 | GStatsCntr wcoheMiss; 192 | 193 | #ifdef SESC_ENERGY 194 | static unsigned cacheID; 195 | unsigned myID; 196 | GStatsEnergy *rdEnergy[2]; // 0 hit, 1 miss 197 | GStatsEnergy *wrEnergy[2]; // 0 hit, 1 miss 198 | #endif 199 | 200 | // END statistics 201 | 202 | SMPProtocol *protocol; 203 | 204 | // interface with upper level 205 | void read(MemRequest *mreq); 206 | void write(MemRequest *mreq); 207 | void pushline(MemRequest *mreq); 208 | void specialOp(MemRequest *mreq); 209 | 210 | typedef CallbackMember1 readCB; 212 | typedef CallbackMember1 writeCB; 214 | typedef CallbackMember1 specialOpCB; 216 | 217 | // port usage accounting 218 | Time_t nextSlot() { 219 | return cachePort->nextSlot(); 220 | } 221 | 222 | // local routines 223 | void doRead(MemRequest *mreq); 224 | // JJO 225 | void doReadRemote(MemRequest *mreq); 226 | void doWrite(MemRequest *mreq); 227 | void doPushLine(MemRequest *mreq); 228 | void doWriteBack(PAddr addr); 229 | void concludeWriteBack(Time_t initialTime); 230 | void sendRead(MemRequest* mreq); 231 | void sendWrite(MemRequest* mreq); 232 | 233 | typedef CallbackMember1 doReadCB; 235 | // JJO 236 | typedef CallbackMember1 doReadRemoteCB; 238 | typedef CallbackMember1 doWriteCB; 240 | typedef CallbackMember1 doPushLineCB; 242 | typedef CallbackMember1 sendReadCB; 244 | typedef CallbackMember1 sendWriteCB; 246 | typedef CallbackMember1 concludeWriteBackCB; 248 | 249 | public: 250 | 251 | typedef CallbackMember1 doReadAgainCB; 253 | typedef CallbackMember1 doWriteAgainCB; 255 | 256 | SMPCache(SMemorySystem *gms, const char *section, const char *name); 257 | ~SMPCache(); 258 | 259 | static void PrintStat(); 260 | 261 | #if (defined SIGDEBUG) 262 | void pStat(); 263 | 264 | #endif 265 | 266 | //static std::set detourSet; 267 | //static std::map replaceMap; 268 | 269 | // JJO 270 | //static bool msgPrinted; 271 | void doWriteAgain(MemRequest *mreq); 272 | 273 | //static HASH_MAP > pendingList; 274 | 275 | //static std::map mutInvReq; 276 | 277 | static unsigned int dlcnt; 278 | 279 | int32_t maxNodeID; 280 | int32_t maxNodeID_bit; 281 | int32_t nodeSelSht; 282 | inline int32_t getMaxNodeID() { return maxNodeID; } 283 | inline int32_t getMaxNodeID_bit() { return maxNodeID_bit; } 284 | inline int32_t getNodeID() { return nodeID; } 285 | int32_t getHomeNodeID(PAddr addr); 286 | int32_t getL2NodeID(PAddr addr); 287 | 288 | //std::map pendingWriteBackReq; 289 | std::map pendingInvCounter; 290 | std::map invCounter; 291 | //std::map pendingReplyFlag; 292 | std::map writeBackPending; 293 | std::set pendingInv; 294 | std::map replyReady; 295 | std::map replyReadyTime; 296 | HASH_MAP pendRemoteRead; 297 | 298 | 299 | //void updateDirectory(SMPMemRequest *sreq); 300 | //void sendUpdateDirectory(SMPMemRequest *sreq); 301 | //typedef CallbackMember1 doUpdateDirectoryCB; 303 | 304 | // BEGIN MemObj interface 305 | 306 | bool isCache() const { 307 | return true; 308 | } 309 | //const bool isCache() const { return true; } 310 | 311 | // port availability 312 | Time_t getNextFreeCycle() const; 313 | 314 | // interface with upper level 315 | bool canAcceptStore(PAddr addr); 316 | void access(MemRequest *mreq); 317 | // JJO 318 | void remoteAccess(MemRequest *mreq); 319 | void sendInvDirUpdate(PAddr addr, PAddr new_addr, CallbackBase *cb, bool wb, bool data); 320 | void processInvDirAck(SMPMemRequest *sreq); 321 | 322 | // interface with lower level 323 | void returnAccess(MemRequest *mreq); 324 | 325 | void invalidate(PAddr addr, ushort size, MemObj *oc); 326 | void doInvalidate(PAddr addr, ushort size); 327 | void realInvalidate(PAddr addr, ushort size, bool writeBack); 328 | 329 | // END MemObj interface 330 | 331 | // BEGIN protocol interface 332 | 333 | // interface used by protocol to access lower level 334 | void sendBelow(SMPMemRequest *sreq); 335 | void sendBelowI(SMPMemRequest *sreq); 336 | void respondBelow(SMPMemRequest *sreq); 337 | void receiveFromBelow(SMPMemRequest *sreq); 338 | void doReceiveFromBelow(SMPMemRequest *sreq); 339 | 340 | typedef CallbackMember1 doReceiveFromBelowCB; 342 | 343 | // interface used by protocol to access upper level 344 | void concludeAccess(MemRequest *mreq); 345 | 346 | // interface used by protocol to operate on cache lines 347 | Line *getLine(PAddr addr); 348 | void writeLine(PAddr addr); 349 | void invalidateLine(PAddr addr, CallbackBase *cb, bool writeBack = false); 350 | Line *allocateLine(PAddr addr, CallbackBase *cb, bool canDestroyCB = true); 351 | void doAllocateLine(PAddr addr, PAddr rpl_addr, CallbackBase *cb); 352 | 353 | typedef CallbackMember3 doAllocateLineCB; 355 | 356 | PAddr calcTag(PAddr addr) { 357 | return cache->calcTag(addr); 358 | } 359 | 360 | // END protocol interface 361 | 362 | // debug function 363 | #ifdef SESC_SMP_DEBUG 364 | Line* findLine(PAddr addr) { 365 | return cache->findLine(addr); 366 | } 367 | void inclusionCheck(PAddr addr); 368 | #endif 369 | }; 370 | 371 | 372 | #endif // SMPCACHE_H 373 | -------------------------------------------------------------------------------- /Project3/SMPCacheState.h: -------------------------------------------------------------------------------- 1 | /* 2 | Sesc: Super ESCalar simulator 3 | Copyright (C) 2003 University of Illinois. 4 | 5 | Contributed by Karin Strauss 6 | 7 | This file is part of SESC. 8 | 9 | SESC is free software; you can redistribute it and/or modify it under the terms 10 | of the GNU General Public License as published by the Free Software Foundation; 11 | either version 2, or (at your option) any later version. 12 | 13 | SESC is distributed in the hope that it will be useful, but WITHOUT ANY 14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 | PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License along with 18 | SESC; see the file COPYING. If not, write to the Free Software Foundation, 59 19 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 | */ 21 | 22 | #ifndef SMPCACHESTATE_H 23 | #define SMPCACHESTATE_H 24 | 25 | #include "CacheCore.h" 26 | 27 | // these states are the most basic ones you can have 28 | // all classes that inherit from this class should 29 | // have at least the following states and bits, with the same encoding 30 | 31 | enum SMPState_t { 32 | SMP_INVALID = 0x00000000, // data is invalid 33 | SMP_TRANS_BIT = 0x10000000, // all transient states start with 0x1 34 | SMP_TRANS_RSV = 0x14000000, // newly allocated line, reserved 35 | SMP_TRANS_INV = 0x18000000, // used while invalidating upper levels 36 | SMP_TRANS_INV_D = 0x18000001, // used while invalidating upper levels, 37 | // and data is dirty (needs writeback) 38 | 39 | SMP_INV_BIT = 0x08000000, // data is in the process of being invalidated 40 | SMP_VALID_BIT = 0x00100000, // all valid states start with 0x001 41 | 42 | // other masks 43 | SMP_DIRTY_BIT = 0x00000001, // data is different from memory 44 | SMP_READABLE_BIT = 0x00100000, // has permission to be read 45 | SMP_WRITEABLE_BIT = 0x00200000 // has permission to be written 46 | }; 47 | 48 | class SMPCacheState : public StateGeneric<> { 49 | 50 | private: 51 | protected: 52 | uint32_t state; 53 | // JJO 54 | bool TS; 55 | public: 56 | uint prevTag; 57 | SMPCacheState() 58 | : StateGeneric<>() { 59 | state = SMP_INVALID; 60 | // JJO 61 | TS=false; 62 | } 63 | 64 | // BEGIN CacheCore interface 65 | bool isValid() const { 66 | return (state != SMP_INVALID); 67 | } 68 | 69 | void invalidate() { 70 | // cannot invalidate if line is in transient state, 71 | // except when this is the end of an invalidate chain 72 | GI(isLocked(), (state & SMP_TRANS_BIT) && (state & SMP_INV_BIT)); 73 | clearTag(); 74 | state = SMP_INVALID; 75 | TS = false; 76 | } 77 | 78 | bool isLocked() const { 79 | return (state & SMP_TRANS_BIT); 80 | } 81 | 82 | // END CacheCore interface 83 | 84 | unsigned getState() const { 85 | return state; 86 | } 87 | 88 | void changeStateTo(unsigned newstate) { 89 | 90 | // not supposed to invalidate through this interface 91 | I(newstate != SMP_INVALID); 92 | 93 | state = newstate; 94 | } 95 | /* My Code*/ 96 | void clearTag() { 97 | prevTag = tag; 98 | tag = 0; 99 | } 100 | 101 | void setTag(uint a) { 102 | I(a); 103 | prevTag = tag; 104 | tag = a; 105 | } 106 | /**/ 107 | // all these functions rely on the fact that 108 | // the rules described above are followed by all protocols 109 | bool isDirty() const { 110 | return (state & SMP_DIRTY_BIT); 111 | } 112 | 113 | bool canBeRead() const { 114 | return (state & SMP_READABLE_BIT); 115 | } 116 | 117 | bool canBeWritten() const { 118 | return (state & SMP_WRITEABLE_BIT); 119 | } 120 | }; 121 | 122 | #endif //SMPCACHESTATE_H 123 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kasakun/High-Performance-Computer-Architecture/a275aa732d58f4c81ac54fe80c555c2d67156546/README.md --------------------------------------------------------------------------------