├── i5ether ├── HX5008.bck ├── HX5008.dcm ├── MJ406541.bck ├── MJ406541.dcm ├── i5ether.ods ├── sym-lib-table ├── fp-lib-table ├── HX5008.lib ├── MJ406541.lib ├── HX5008.pretty │ └── HX5008NL.kicad_mod ├── MJ406541.pretty │ └── 1-406541-1.kicad_mod ├── i5ether.pro ├── i5ether-cache.lib ├── i5ether.xml └── i5ether.sch ├── images ├── netboot.png ├── uSD-pmod.jpg ├── video-fb.png ├── telnet-app.png ├── boot-on-sdcard.png ├── flash-cmd-added.jpg ├── i5ether-adaptor.jpg ├── uSD-pmod-pullup.jpg └── video-terminal.png ├── streams └── colorlight_i5.bit ├── linux ├── boot.json ├── opensbi-config-fixmap.patch ├── linux-litex-vexriscv-rebase-mmc.patch ├── linux-on-litex-vexriscv-mmc.patch ├── rv32-eth.dts ├── rv32-mmc.dts ├── defconfig-colorlight-i5-mmc └── defconfig-colorlight-i5-eth ├── patches └── litex-bios-new-flash-commands.patch └── README.md /i5ether/HX5008.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /i5ether/HX5008.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /i5ether/MJ406541.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /i5ether/MJ406541.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /i5ether/i5ether.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/i5ether/i5ether.ods -------------------------------------------------------------------------------- /images/netboot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/netboot.png -------------------------------------------------------------------------------- /images/uSD-pmod.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/uSD-pmod.jpg -------------------------------------------------------------------------------- /images/video-fb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/video-fb.png -------------------------------------------------------------------------------- /images/telnet-app.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/telnet-app.png -------------------------------------------------------------------------------- /images/boot-on-sdcard.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/boot-on-sdcard.png -------------------------------------------------------------------------------- /images/flash-cmd-added.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/flash-cmd-added.jpg -------------------------------------------------------------------------------- /images/i5ether-adaptor.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/i5ether-adaptor.jpg -------------------------------------------------------------------------------- /images/uSD-pmod-pullup.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/uSD-pmod-pullup.jpg -------------------------------------------------------------------------------- /images/video-terminal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/images/video-terminal.png -------------------------------------------------------------------------------- /streams/colorlight_i5.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kazkojima/colorlight-i5-tips/HEAD/streams/colorlight_i5.bit -------------------------------------------------------------------------------- /linux/boot.json: -------------------------------------------------------------------------------- 1 | { 2 | "Image": "0x40000000", 3 | "rv32.dtb": "0x40780000", 4 | "opensbi.bin": "0x407c0000" 5 | } 6 | -------------------------------------------------------------------------------- /i5ether/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name HX5008)(type Legacy)(uri ${KIPRJMOD}/HX5008.lib)(options "")(descr "")) 3 | (lib (name MJ406541)(type Legacy)(uri ${KIPRJMOD}/MJ406541.lib)(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /i5ether/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name HX5008)(type KiCad)(uri ${KIPRJMOD}/HX5008.pretty)(options "")(descr "")) 3 | (lib (name MJ406541)(type KiCad)(uri ${KIPRJMOD}/MJ406541.pretty)(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /linux/opensbi-config-fixmap.patch: -------------------------------------------------------------------------------- 1 | diff --git a/platform/litex/vexriscv/config.mk b/platform/litex/vexriscv/config.mk 2 | index 5b89a1d..5c96c42 100644 3 | --- a/platform/litex/vexriscv/config.mk 4 | +++ b/platform/litex/vexriscv/config.mk 5 | @@ -20,11 +20,11 @@ PLATFORM_RISCV_ISA = rv32ima 6 | PLATFORM_RISCV_CODE_MODEL = medany 7 | 8 | # Blobs to build 9 | -FW_TEXT_START=0x40F00000 10 | +FW_TEXT_START=0x407C0000 11 | FW_DYNAMIC=y 12 | FW_JUMP=y 13 | FW_JUMP_ADDR=0x40000000 14 | -FW_JUMP_FDT_ADDR=0x40EF0000 15 | +FW_JUMP_FDT_ADDR=0x40780000 16 | FW_PAYLOAD=y 17 | FW_PAYLOAD_OFFSET=0x40000000 18 | -FW_PAYLOAD_FDT_ADDR=0x40EF0000 19 | +FW_PAYLOAD_FDT_ADDR=0x40780000 20 | -------------------------------------------------------------------------------- /linux/linux-litex-vexriscv-rebase-mmc.patch: -------------------------------------------------------------------------------- 1 | diff --git a/drivers/mmc/host/litex_mmc.c b/drivers/mmc/host/litex_mmc.c 2 | index 9bdc088dd100..3b6b0b127aca 100644 3 | --- a/drivers/mmc/host/litex_mmc.c 4 | +++ b/drivers/mmc/host/litex_mmc.c 5 | @@ -281,6 +281,13 @@ static void litex_request(struct mmc_host *mmc, struct mmc_request *mrq) 6 | 7 | sg_copy_to_buffer(data->sg, data->sg_len, 8 | host->buffer, write_length); 9 | +#if 1 10 | + asm(".word 0x500F"); 11 | + unsigned int i; 12 | + for(i=0;i<2*2048/4;i++) { 13 | + ((volatile unsigned int *) 0xc0000000)[i]; 14 | + } 15 | +#endif 16 | 17 | litex_write8(host->sdwriter + 18 | LITEX_MMC_SDMEM2BLK_ENA_OFF, 0); 19 | @@ -343,6 +350,13 @@ static void litex_request(struct mmc_host *mmc, struct mmc_request *mrq) 20 | data->bytes_xfered = min(data->blksz * data->blocks, 21 | mmc->max_req_size); 22 | if (transfer == SDCARD_CTRL_DATA_TRANSFER_READ) { 23 | +#if 1 24 | + asm(".word 0x500F"); 25 | + unsigned int i; 26 | + for(i=0;i<2*2048/4;i++) { 27 | + ((volatile unsigned int *) 0xc0000000)[i]; 28 | + } 29 | +#endif 30 | sg_copy_from_buffer(data->sg, sg_nents(data->sg), 31 | host->buffer, data->bytes_xfered); 32 | } 33 | -------------------------------------------------------------------------------- /i5ether/HX5008.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # HX5008 5 | # 6 | DEF HX5008 T 0 40 Y Y 1 F N 7 | F0 "T" -250 650 50 H V C CNN 8 | F1 "HX5008" 0 650 50 H V C CNN 9 | F2 "HX5008:HX5008NL" 0 500 50 H I C CNN 10 | F3 "" 0 500 50 H I C CNN 11 | DRAW 12 | S -300 -750 250 550 0 1 0 f 13 | X TCT1 1 -400 450 100 R 50 50 1 1 I 14 | X TCT4 10 -400 -450 100 R 50 50 1 1 I 15 | X TD4+ 11 -400 -550 100 R 50 50 1 1 I 16 | X TD4- 12 -400 -650 100 R 50 50 1 1 I 17 | X MX4- 13 350 -650 100 L 50 50 1 1 I 18 | X MX4+ 14 350 -550 100 L 50 50 1 1 I 19 | X MCT4 15 350 -450 100 L 50 50 1 1 I 20 | X MX3- 16 350 -350 100 L 50 50 1 1 I 21 | X MX3+ 17 350 -250 100 L 50 50 1 1 I 22 | X MCT3 18 350 -150 100 L 50 50 1 1 I 23 | X MX2- 19 350 -50 100 L 50 50 1 1 I 24 | X TD1+ 2 -400 350 100 R 50 50 1 1 I 25 | X MX2+ 20 350 50 100 L 50 50 1 1 I 26 | X MCT2 21 350 150 100 L 50 50 1 1 I 27 | X MX1- 22 350 250 100 L 50 50 1 1 I 28 | X MX1+ 23 350 350 100 L 50 50 1 1 I 29 | X MCT1 24 350 450 100 L 50 50 1 1 I 30 | X TD1- 3 -400 250 100 R 50 50 1 1 I 31 | X TCT2 4 -400 150 100 R 50 50 1 1 I 32 | X TD2+ 5 -400 50 100 R 50 50 1 1 I 33 | X TD2- 6 -400 -50 100 R 50 50 1 1 I 34 | X TCT3 7 -400 -150 100 R 50 50 1 1 I 35 | X TD3+ 8 -400 -250 100 R 50 50 1 1 I 36 | X TD3- 9 -400 -350 100 R 50 50 1 1 I 37 | ENDDRAW 38 | ENDDEF 39 | # 40 | #End Library 41 | -------------------------------------------------------------------------------- /linux/linux-on-litex-vexriscv-mmc.patch: -------------------------------------------------------------------------------- 1 | diff --git a/make.py b/make.py 2 | index 220e216..1752c06 100755 3 | --- a/make.py 4 | +++ b/make.py 5 | @@ -362,7 +362,7 @@ class ECPIX5(Board): 6 | class Colorlight_i5(Board): 7 | soc_kwargs = { 8 | "sys_clk_freq": int(50e6), # 48MHz default. 9 | - "integrated_rom_size": 0xa000, # Reduce integrated_rom_size. 10 | + "integrated_rom_size": 0xc000, # Reduce integrated_rom_size. 11 | "l2_size" : 2048, # Use Wishbone and L2 for memory accesses. 12 | } 13 | def __init__(self): 14 | @@ -371,6 +371,8 @@ class Colorlight_i5(Board): 15 | # Communication 16 | "serial", 17 | "ethernet", 18 | + # Storage 19 | + "sdcard", 20 | }, bitstream_ext=".svf") 21 | 22 | #--------------------------------------------------------------------------------------------------- 23 | @@ -542,6 +544,10 @@ def main(): 24 | from litex_boards.platforms.arty import _sdcard_pmod_io 25 | board.platform.add_extension(_sdcard_pmod_io) 26 | 27 | + if board_name in ["colorlight_i5"]: 28 | + from litex_boards.platforms.colorlight_i5 import _sdcard_pmod_io 29 | + board.platform.add_extension(_sdcard_pmod_io) 30 | + 31 | if board_name in ["orangecrab"]: 32 | from litex_boards.platforms.orangecrab import feather_i2c 33 | board.platform.add_extension(feather_i2c) 34 | -------------------------------------------------------------------------------- /i5ether/MJ406541.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # 1-406541-1 5 | # 6 | DEF 1-406541-1 J 0 10 Y N 1 L N 7 | F0 "J" 350 250 60 H V C CNN 8 | F1 "1-406541-1" 400 -400 60 H V C CNN 9 | F2 "CONN8_406541_TEC" 400 -460 60 H I C CNN 10 | F3 "" 0 0 60 H V C CNN 11 | $FPLIST 12 | CONN8_406541_TEC 13 | $ENDFPLIST 14 | DRAW 15 | S 500 -1000 200 100 0 1 8 f 16 | P 2 1 1 5 200 -1000 500 -1000 N 17 | P 2 1 1 5 200 100 200 -1000 N 18 | P 2 1 1 5 400 -700 200 -700 N 19 | P 2 1 1 5 400 -700 350 -733 N 20 | P 2 1 1 5 400 -700 350 -667 N 21 | P 2 1 1 5 400 -600 200 -600 N 22 | P 2 1 1 5 400 -600 350 -633 N 23 | P 2 1 1 5 400 -600 350 -567 N 24 | P 2 1 1 5 400 -500 200 -500 N 25 | P 2 1 1 5 400 -500 350 -533 N 26 | P 2 1 1 5 400 -500 350 -467 N 27 | P 2 1 1 5 400 -400 200 -400 N 28 | P 2 1 1 5 400 -400 350 -433 N 29 | P 2 1 1 5 400 -400 350 -367 N 30 | P 2 1 1 5 400 -300 200 -300 N 31 | P 2 1 1 5 400 -300 350 -333 N 32 | P 2 1 1 5 400 -300 350 -267 N 33 | P 2 1 1 5 400 -200 200 -200 N 34 | P 2 1 1 5 400 -200 350 -233 N 35 | P 2 1 1 5 400 -200 350 -167 N 36 | P 2 1 1 5 400 -100 200 -100 N 37 | P 2 1 1 5 400 -100 350 -133 N 38 | P 2 1 1 5 400 -100 350 -67 N 39 | P 2 1 1 5 400 0 200 0 N 40 | P 2 1 1 5 400 0 350 -33 N 41 | P 2 1 1 5 400 0 350 33 N 42 | P 2 1 1 5 500 -1000 500 100 N 43 | P 2 1 1 5 500 100 200 100 N 44 | X 1 1 0 0 200 R 59 59 1 1 O 45 | X SHIELD 10 0 -900 200 R 59 59 1 1 I 46 | X 2 2 0 -100 200 R 59 59 1 1 O 47 | X 3 3 0 -200 200 R 59 59 1 1 O 48 | X 4 4 0 -300 200 R 59 59 1 1 O 49 | X 5 5 0 -400 200 R 59 59 1 1 O 50 | X 6 6 0 -500 200 R 59 59 1 1 O 51 | X 7 7 0 -600 200 R 59 59 1 1 O 52 | X 8 8 0 -700 200 R 59 59 1 1 O 53 | X SHIELD 9 0 -800 200 R 59 59 1 1 I 54 | ENDDRAW 55 | ENDDEF 56 | # 57 | #End Library 58 | -------------------------------------------------------------------------------- /linux/rv32-eth.dts: -------------------------------------------------------------------------------- 1 | 2 | /dts-v1/; 3 | 4 | / { 5 | #address-cells = <1>; 6 | #size-cells = <1>; 7 | 8 | chosen { 9 | bootargs = "mem=8M@0x40000000 rootwait console=liteuart earlycon=sbi root=/dev/nfs nfsroot=10.253.253.8:/srv/nfs,rsize=16384,wsize=4096 ethaddr=10:e2:d5:00:00:00 ip=dhcp init=/sbin/init swiotlb=32"; 10 | }; 11 | 12 | cpus { 13 | #address-cells = <1>; 14 | #size-cells = <0>; 15 | timebase-frequency = <50000000>; 16 | 17 | cpu@0 { 18 | device_type = "cpu"; 19 | compatible = "riscv"; 20 | riscv,isa = "rv32ima"; 21 | mmu-type = "riscv,sv32"; 22 | reg = <0>; 23 | clock-frequency = <50000000>; 24 | status = "okay"; 25 | L0: interrupt-controller { 26 | #interrupt-cells = <0x00000001>; 27 | interrupt-controller; 28 | compatible = "riscv,cpu-intc"; 29 | }; 30 | }; 31 | 32 | }; 33 | 34 | memory@40000000 { 35 | device_type = "memory"; 36 | reg = <0x40000000 0x7c0000>; 37 | }; 38 | 39 | reserved-memory { 40 | #address-cells = <1>; 41 | #size-cells = <1>; 42 | ranges; 43 | vexriscv_emulator@407c0000 { 44 | reg = <0x407c0000 0x20000>; 45 | }; 46 | }; 47 | 48 | soc { 49 | #address-cells = <1>; 50 | #size-cells = <1>; 51 | bus-frequency = <50000000>; 52 | compatible = "simple-bus"; 53 | ranges; 54 | 55 | soc_ctrl0: soc_controller@f0000000 { 56 | compatible = "litex,soc_controller"; 57 | reg = <0xf0000000 0xc>; 58 | status = "okay"; 59 | }; 60 | 61 | intc0: interrupt-controller@f0c00000 { 62 | compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; 63 | reg = <0xf0c00000 0x400000>; 64 | #interrupt-cells = <1>; 65 | interrupt-controller; 66 | interrupts-extended = < 67 | &L0 11 &L0 9>; 68 | riscv,ndev = <32>; 69 | }; 70 | 71 | liteuart0: serial@f0001000 { 72 | device_type = "serial"; 73 | compatible = "litex,liteuart"; 74 | reg = <0xf0001000 0x100>; 75 | status = "okay"; 76 | }; 77 | 78 | mac0: mac@f0005000 { 79 | compatible = "litex,liteeth"; 80 | reg = <0xf0005000 0x7c>, 81 | <0xf0004800 0x10>, 82 | <0xb0000000 0x4000>; 83 | tx-fifo-depth = <2>; 84 | rx-fifo-depth = <2>; 85 | interrupt-parent = <&intc0>; 86 | interrupts = <2>; 87 | mac-address = [10 e2 d5 00 00 00]; 88 | }; 89 | 90 | litespiflash: spiflash@f0003800 { 91 | #address-cells = <1>; 92 | #size-cells = <1>; 93 | compatible = "litex,spiflash"; 94 | reg = <0xf0003800 0x100>; 95 | flash: flash@0 { 96 | compatible = "jedec,spi-nor"; 97 | reg = <0x0 0x1000000>; 98 | }; 99 | }; 100 | 101 | leds: gpio@f0003000 { 102 | compatible = "litex,gpio"; 103 | reg = <0xf0003000 0x4>; 104 | litex,direction = "out"; 105 | status = "disabled"; 106 | }; 107 | 108 | }; 109 | 110 | aliases { 111 | 112 | serial0 = &liteuart0; 113 | 114 | spiflash = &litespiflash; 115 | 116 | }; 117 | 118 | }; 119 | 120 | &leds { 121 | litex,ngpio = <4>; 122 | status = "okay"; 123 | }; 124 | -------------------------------------------------------------------------------- /i5ether/HX5008.pretty/HX5008NL.kicad_mod: -------------------------------------------------------------------------------- 1 | (module HX5008NL (layer F.Cu) (tedit 5F63518B) 2 | (descr "Transformer Ethernet SMD, https://www.haloelectronics.com/pdf/discrete-genesus.pdf") 3 | (tags "Transformer Ethernet SMD") 4 | (attr smd) 5 | (fp_text reference REF** (at 5.16 -8.53) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value HX5008NL (at 5.11 9.01) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_text user %R (at 4.61 0.14) (layer F.Fab) 12 | (effects (font (size 1 1) (thickness 0.15))) 13 | ) 14 | (fp_line (start -6 7.61) (end 14.4 7.61) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start 14.4 7.61) (end 14.4 -7.61) (layer F.CrtYd) (width 0.05)) 16 | (fp_line (start 14.4 -7.61) (end -6 -7.61) (layer F.CrtYd) (width 0.05)) 17 | (fp_line (start -6 7.61) (end -6 -7.61) (layer F.CrtYd) (width 0.05)) 18 | (fp_line (start -3.2 -7.39) (end -4.08 -7.39) (layer F.SilkS) (width 0.12)) 19 | (fp_line (start -4.08 -7.39) (end -4.08 -6.52) (layer F.SilkS) (width 0.12)) 20 | (fp_line (start -3.92 6.03) (end -3.92 7.22) (layer F.SilkS) (width 0.12)) 21 | (fp_line (start 12.32 6.03) (end 12.32 7.22) (layer F.SilkS) (width 0.12)) 22 | (fp_line (start -3.81 7.11) (end 12.2 7.11) (layer F.Fab) (width 0.1)) 23 | (fp_line (start -3.81 7.11) (end -3.81 -6.49) (layer F.Fab) (width 0.1)) 24 | (fp_line (start 12.21 7.11) (end 12.21 -7.11) (layer F.Fab) (width 0.1)) 25 | (fp_line (start -3.19 -7.11) (end 12.21 -7.11) (layer F.Fab) (width 0.1)) 26 | (fp_line (start -3.19 -7.11) (end -3.81 -6.49) (layer F.Fab) (width 0.1)) 27 | (fp_line (start -3.91 -7.22) (end 12.32 -7.22) (layer F.SilkS) (width 0.12)) 28 | (fp_line (start -3.91 -7.22) (end -3.91 -6.03) (layer F.SilkS) (width 0.12)) 29 | (fp_line (start 12.32 -7.22) (end 12.32 -6.02) (layer F.SilkS) (width 0.12)) 30 | (fp_line (start -3.92 7.22) (end 12.32 7.22) (layer F.SilkS) (width 0.12)) 31 | (pad 1 smd rect (at -4.699 -5.4483 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 32 | (pad 4 smd rect (at -4.699 -2.4765 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 33 | (pad 7 smd rect (at -4.699 0.4953 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 34 | (pad 10 smd rect (at -4.699 3.4671 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 35 | (pad 15 smd rect (at 13.099 3.4671 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 36 | (pad 18 smd rect (at 13.099 0.4953 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 37 | (pad 21 smd rect (at 13.099 -2.4765 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 38 | (pad 24 smd rect (at 13.099 -5.4483 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 39 | (pad 22 smd rect (at 13.099 -3.4671 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 40 | (pad 23 smd rect (at 13.099 -4.4577 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 41 | (pad 19 smd rect (at 13.099 -0.4953 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 42 | (pad 20 smd rect (at 13.099 -1.4859 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 43 | (pad 16 smd rect (at 13.099 2.4765 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 44 | (pad 17 smd rect (at 13.099 1.4859 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 45 | (pad 13 smd rect (at 13.099 5.4483 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 46 | (pad 14 smd rect (at 13.099 4.4577 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 47 | (pad 3 smd rect (at -4.699 -3.4671 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 48 | (pad 2 smd rect (at -4.699 -4.4577 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 49 | (pad 6 smd rect (at -4.699 -0.4953 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 50 | (pad 5 smd rect (at -4.699 -1.4859 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 51 | (pad 9 smd rect (at -4.699 2.4765 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 52 | (pad 8 smd rect (at -4.699 1.4859 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 53 | (pad 12 smd rect (at -4.699 5.4483 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 54 | (pad 11 smd rect (at -4.699 4.4577 270) (size 0.64 2.03) (layers F.Cu F.Paste F.Mask)) 55 | (model ${KISYS3DMOD}/Transformer_SMD.3dshapes/Transformer_Ethernet_HALO_TG111-MSC13.wrl 56 | (at (xyz 0.16 0 0)) 57 | (scale (xyz 1.6 1 1)) 58 | (rotate (xyz 0 0 0)) 59 | ) 60 | ) 61 | -------------------------------------------------------------------------------- /linux/rv32-mmc.dts: -------------------------------------------------------------------------------- 1 | 2 | /dts-v1/; 3 | 4 | / { 5 | #address-cells = <1>; 6 | #size-cells = <1>; 7 | 8 | chosen { 9 | bootargs = "mem=8M@0x40000000 rootwait console=liteuart earlycon=sbi root=/dev/mmcblk0p2 init=/sbin/init swiotlb=32"; 10 | }; 11 | 12 | cpus { 13 | #address-cells = <1>; 14 | #size-cells = <0>; 15 | timebase-frequency = <50000000>; 16 | 17 | cpu@0 { 18 | device_type = "cpu"; 19 | compatible = "riscv"; 20 | riscv,isa = "rv32ima"; 21 | mmu-type = "riscv,sv32"; 22 | reg = <0>; 23 | clock-frequency = <50000000>; 24 | status = "okay"; 25 | L0: interrupt-controller { 26 | #interrupt-cells = <0x00000001>; 27 | interrupt-controller; 28 | compatible = "riscv,cpu-intc"; 29 | }; 30 | }; 31 | 32 | }; 33 | 34 | memory@40000000 { 35 | device_type = "memory"; 36 | reg = <0x40000000 0x7c0000>; 37 | }; 38 | 39 | reserved-memory { 40 | #address-cells = <1>; 41 | #size-cells = <1>; 42 | ranges; 43 | vexriscv_emulator@407c0000 { 44 | reg = <0x407c0000 0x20000>; 45 | }; 46 | }; 47 | 48 | soc { 49 | #address-cells = <1>; 50 | #size-cells = <1>; 51 | bus-frequency = <50000000>; 52 | compatible = "simple-bus"; 53 | ranges; 54 | 55 | soc_ctrl0: soc_controller@f0000000 { 56 | compatible = "litex,soc_controller"; 57 | reg = <0xf0000000 0xc>; 58 | status = "okay"; 59 | }; 60 | 61 | intc0: interrupt-controller@f0c00000 { 62 | compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; 63 | reg = <0xf0c00000 0x400000>; 64 | #interrupt-cells = <1>; 65 | interrupt-controller; 66 | interrupts-extended = < 67 | &L0 11 &L0 9>; 68 | riscv,ndev = <32>; 69 | }; 70 | 71 | liteuart0: serial@f0001000 { 72 | device_type = "serial"; 73 | compatible = "litex,liteuart"; 74 | reg = <0xf0001000 0x100>; 75 | status = "okay"; 76 | }; 77 | 78 | mac0: mac@f0005000 { 79 | compatible = "litex,liteeth"; 80 | interrupt-parent = <&intc0>; 81 | interrupts = <2>; 82 | reg = <0xf0005000 0x7c>, 83 | <0xf0004800 0x10>, 84 | <0xb0000000 0x4000>; 85 | tx-fifo-depth = <2>; 86 | rx-fifo-depth = <2>; 87 | mac-address = [10 e2 d5 00 00 00]; 88 | }; 89 | 90 | litespiflash: spiflash@f0003800 { 91 | #address-cells = <1>; 92 | #size-cells = <1>; 93 | compatible = "litex,spiflash"; 94 | reg = <0xf0003800 0x100>; 95 | flash: flash@0 { 96 | compatible = "jedec,spi-nor"; 97 | reg = <0x0 0x1000000>; 98 | }; 99 | }; 100 | 101 | mmc0: mmc@f0005800 { 102 | compatible = "litex,mmc"; 103 | reg = < 104 | 0xf0005800 0x100 105 | 0xf0006000 0x100 106 | 0xf0006800 0x100 107 | 0xf0007000 0x100>; 108 | bus-width = <0x04>; 109 | status = "okay"; 110 | }; 111 | 112 | leds: gpio@f0003000 { 113 | compatible = "litex,gpio"; 114 | reg = <0xf0003000 0x4>; 115 | litex,direction = "out"; 116 | status = "disabled"; 117 | }; 118 | 119 | }; 120 | 121 | aliases { 122 | 123 | serial0 = &liteuart0; 124 | 125 | spiflash = &litespiflash; 126 | 127 | }; 128 | 129 | }; 130 | 131 | &leds { 132 | litex,ngpio = <4>; 133 | status = "okay"; 134 | }; 135 | -------------------------------------------------------------------------------- /i5ether/MJ406541.pretty/1-406541-1.kicad_mod: -------------------------------------------------------------------------------- 1 | (module 1-406541-1 (layer F.Cu) 2 | (fp_text reference REF** (at 3.556 7.9248) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness .15))) 4 | ) 5 | (fp_text value CONN8_406541_TEC (at 3.556 7.9248) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness .15))) 7 | ) 8 | (fp_text user "Copyright 2016 Accelerated Designs. All rights reserved." (at 0 0) (layer Cmts.User) 9 | (effects (font (size .127 .127) (thickness .002))) 10 | ) 11 | (fp_text user "*" (at 0 0) (layer F.SilkS) 12 | (effects (font (size 1 1) (thickness .15))) 13 | ) 14 | (fp_text user "*" (at 0 0) (layer F.Fab) 15 | (effects (font (size 1 1) (thickness .15))) 16 | ) 17 | (fp_text user "1" (at -1.297 0) (layer F.SilkS) 18 | (effects (font (size 1 1) (thickness .15))) 19 | ) 20 | (fp_text user "2" (at -1.297 1.778) (layer F.SilkS) 21 | (effects (font (size 1 1) (thickness .15))) 22 | ) 23 | (fp_text user "7" (at 8.509 0) (layer F.SilkS) 24 | (effects (font (size 1 1) (thickness .15))) 25 | ) 26 | (fp_text user "8" (at 8.509 1.778) (layer F.SilkS) 27 | (effects (font (size 1 1) (thickness .15))) 28 | ) 29 | (fp_text user "1" (at -1.297 0) (layer F.Fab) 30 | (effects (font (size 1 1) (thickness .15))) 31 | ) 32 | (fp_text user "2" (at -1.297 1.778) (layer F.Fab) 33 | (effects (font (size 1 1) (thickness .15))) 34 | ) 35 | (fp_text user "7" (at 8.509 0) (layer F.Fab) 36 | (effects (font (size 1 1) (thickness .15))) 37 | ) 38 | (fp_text user "8" (at 8.509 1.778) (layer F.Fab) 39 | (effects (font (size 1 1) (thickness .15))) 40 | ) 41 | (fp_line (start .635 7.9248) (end 0 9.1948) (layer F.Fab) (width .1524)) 42 | (fp_line (start -.635 7.9248) (end 0 9.1948) (layer F.Fab) (width .1524)) 43 | (fp_line (start -5.207 8.0518) (end 12.319 8.0518) (layer F.SilkS) (width .1524)) 44 | (fp_line (start 12.319 -.635) (end 12.319 -7.9502) (layer F.SilkS) (width .1524)) 45 | (fp_line (start 12.319 -7.9502) (end -5.207 -7.9502) (layer F.SilkS) (width .1524)) 46 | (fp_line (start -5.207 -7.9502) (end -5.207 -.635) (layer F.SilkS) (width .1524)) 47 | (fp_line (start -5.08 7.9248) (end 12.192 7.9248) (layer F.Fab) (width .1524)) 48 | (fp_line (start 12.192 7.9248) (end 12.192 -7.8232) (layer F.Fab) (width .1524)) 49 | (fp_line (start 12.192 -7.8232) (end -5.08 -7.8232) (layer F.Fab) (width .1524)) 50 | (fp_line (start -5.08 -7.8232) (end -5.08 7.9248) (layer F.Fab) (width .1524)) 51 | (fp_line (start -5.207 8.0518) (end -5.207 2.54) (layer F.SilkS) (width .1524)) 52 | (fp_line (start 12.319 8.0518) (end 12.319 2.54) (layer F.SilkS) (width .1524)) 53 | (fp_line (start -5.969 8.1788) (end 13.081 8.1788) (layer F.CrtYd) (width .1524)) 54 | (fp_line (start 13.081 8.1788) (end 13.081 -8.0772) (layer F.CrtYd) (width .1524)) 55 | (fp_line (start 13.081 -8.0772) (end -5.969 -8.0772) (layer F.CrtYd) (width .1524)) 56 | (fp_line (start -5.969 -8.0772) (end -5.969 8.1788) (layer F.CrtYd) (width .1524)) 57 | (fp_arc (start 0 -8.89) (end -.1016 -8.89) (angle 0)(layer F.SilkS) (width .1524)) 58 | (pad 1 thru_hole circle (at 0 0) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 59 | (pad 2 thru_hole circle (at 1.016 1.778) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 60 | (pad 3 thru_hole circle (at 2.032 0) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 61 | (pad 4 thru_hole circle (at 3.048 1.778) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 62 | (pad 5 thru_hole circle (at 4.064 0) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 63 | (pad 6 thru_hole circle (at 5.08 1.778) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 64 | (pad 7 thru_hole circle (at 6.096 0) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 65 | (pad 8 thru_hole circle (at 7.112 1.778) (size 1.297 1.297) (drill .889) (layers *.Cu *.Mask)) 66 | (pad 11 np_thru_hole circle (at -2.794 -2.54) (size 3.2512 3.2512) (drill 3.2512) (layers *.Cu *.Mask)) 67 | (pad 12 np_thru_hole circle (at 9.906 -2.54) (size 3.2512 3.2512) (drill 3.2512) (layers *.Cu *.Mask)) 68 | (pad 10 thru_hole circle (at 11.684 .889) (size 2.0828 2.0828) (drill 1.5748) (layers *.Cu *.Mask)) 69 | (pad 9 thru_hole circle (at -4.572 .889) (size 2.0828 2.0828) (drill 1.5748) (layers *.Cu *.Mask)) 70 | ) 71 | -------------------------------------------------------------------------------- /patches/litex-bios-new-flash-commands.patch: -------------------------------------------------------------------------------- 1 | diff --git a/litex/soc/software/bios/cmds/cmd_spiflash.c b/litex/soc/software/bios/cmds/cmd_spiflash.c 2 | index 1038f7a7..1a969099 100644 3 | --- a/litex/soc/software/bios/cmds/cmd_spiflash.c 4 | +++ b/litex/soc/software/bios/cmds/cmd_spiflash.c 5 | @@ -73,3 +73,68 @@ static void flash_erase_handler(int nb_params, char **params) 6 | define_command(flash_erase, flash_erase_handler, "Erase whole flash", SPIFLASH_CMDS); 7 | #endif 8 | 9 | +/** 10 | + * Command "flash_readid" 11 | + * 12 | + * Read ID 13 | + * 14 | + */ 15 | +#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE) 16 | +static void flash_readid_handler(int nb_params, char **params) 17 | +{ 18 | + unsigned int id; 19 | + 20 | + id = flash_readid(); 21 | + printf("Flash id %08x\n", id); 22 | +} 23 | + 24 | +define_command(flash_readid, flash_readid_handler, "Read flash ID", SPIFLASH_CMDS); 25 | +#endif 26 | + 27 | +/** 28 | + * Command "flash_readsr" 29 | + * 30 | + * Read stauts register 31 | + * 32 | + */ 33 | +#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE) 34 | +static void flash_readsr_handler(int nb_params, char **params) 35 | +{ 36 | + unsigned char sr0, sr1; 37 | + 38 | + sr0 = flash_readsr(0); 39 | + sr1 = flash_readsr(1); 40 | + printf("Status %02x%02x\n", sr1, sr0); 41 | +} 42 | + 43 | +define_command(flash_readsr, flash_readsr_handler, "Read status register", SPIFLASH_CMDS); 44 | +#endif 45 | + 46 | +/** 47 | + * Command "flash_write_protect" 48 | + * 49 | + * Write block protect bits of status register 50 | + * 51 | + */ 52 | +#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE) 53 | +static void flash_write_protect_handler(int nb_params, char **params) 54 | +{ 55 | + unsigned int prot; 56 | + char *c; 57 | + 58 | + if (nb_params != 1) { 59 | + printf("flash_write_protect "); 60 | + return; 61 | + } 62 | + 63 | + prot = strtoul(params[0], &c, 0); 64 | + if (*c != 0 || prot > 31) { 65 | + printf("Incorrect bits"); 66 | + return; 67 | + } 68 | + 69 | + flash_write_protect(prot << 2); 70 | +} 71 | + 72 | +define_command(flash_write_protect, flash_write_protect_handler, "Write protect bits (0-31)", SPIFLASH_CMDS); 73 | +#endif 74 | diff --git a/litex/soc/software/libbase/spiflash.c b/litex/soc/software/libbase/spiflash.c 75 | index c1681c08..b8b6930e 100644 76 | --- a/litex/soc/software/libbase/spiflash.c 77 | +++ b/litex/soc/software/libbase/spiflash.c 78 | @@ -10,6 +10,9 @@ 79 | #define WREN_CMD 0x06 80 | #define CE_CMD 0xc7 81 | #define SE_CMD 0xd8 82 | +#define WRSR_CMD 0x01 83 | +#define RDSR1_CMD 0x35 84 | +#define RDID_CMD 0x9f 85 | 86 | #define BITBANG_CLK (1 << 1) 87 | #define BITBANG_CS_N (1 << 2) 88 | @@ -156,4 +159,73 @@ void write_to_flash(unsigned int addr, const unsigned char *c, unsigned int len) 89 | } 90 | } 91 | 92 | +unsigned int flash_readid(void) 93 | +{ 94 | + int i; 95 | + unsigned int id = 0; 96 | + 97 | + spiflash_bitbang_en_write(1); 98 | + 99 | + flash_write_byte(RDID_CMD); 100 | + spiflash_bitbang_write(BITBANG_DQ_INPUT); 101 | + for(i = 0; i < 24; i++) { 102 | + id <<= 1; 103 | + spiflash_bitbang_write(BITBANG_CLK | BITBANG_DQ_INPUT); 104 | + id |= spiflash_miso_read(); 105 | + spiflash_bitbang_write(0 | BITBANG_DQ_INPUT); 106 | + } 107 | + spiflash_bitbang_write(0); 108 | + spiflash_bitbang_write(BITBANG_CS_N); 109 | + 110 | + spiflash_bitbang_en_write(0); 111 | + 112 | + return id; 113 | +} 114 | + 115 | +unsigned char flash_readsr(int hi) 116 | +{ 117 | + int i; 118 | + unsigned char sr = 0; 119 | + 120 | + spiflash_bitbang_en_write(1); 121 | + 122 | + flash_write_byte(hi ? RDSR1_CMD : RDSR_CMD); 123 | + spiflash_bitbang_write(BITBANG_DQ_INPUT); 124 | + for(i = 0; i < 8; i++) { 125 | + sr <<= 1; 126 | + spiflash_bitbang_write(BITBANG_CLK | BITBANG_DQ_INPUT); 127 | + sr |= spiflash_miso_read(); 128 | + spiflash_bitbang_write(0 | BITBANG_DQ_INPUT); 129 | + } 130 | + spiflash_bitbang_write(0); 131 | + spiflash_bitbang_write(BITBANG_CS_N); 132 | + 133 | + spiflash_bitbang_en_write(0); 134 | + 135 | + return sr; 136 | +} 137 | + 138 | +unsigned int flash_write_protect(unsigned int bp) 139 | +{ 140 | + int i; 141 | + unsigned int id = 0; 142 | + 143 | + spiflash_bitbang_en_write(1); 144 | + wait_for_device_ready(); 145 | + 146 | + flash_write_byte(WREN_CMD); 147 | + spiflash_bitbang_write(BITBANG_CS_N); 148 | + 149 | + flash_write_byte(WRSR_CMD); 150 | + flash_write_byte(bp & 0x7c); 151 | + flash_write_byte(0); 152 | + 153 | + spiflash_bitbang_write(BITBANG_CS_N); 154 | + 155 | + wait_for_device_ready(); 156 | + spiflash_bitbang_en_write(0); 157 | + 158 | + return id; 159 | +} 160 | + 161 | #endif /* CSR_SPIFLASH_BASE && SPIFLASH_PAGE_SIZE */ 162 | -------------------------------------------------------------------------------- /i5ether/i5ether.pro: -------------------------------------------------------------------------------- 1 | update=2020年12月09日 10時33分40秒 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [schematic_editor] 16 | version=1 17 | PageLayoutDescrFile= 18 | PlotDirectoryName= 19 | SubpartIdSeparator=0 20 | SubpartFirstId=65 21 | NetFmtName=Pcbnew 22 | SpiceAjustPassiveValues=0 23 | LabSize=50 24 | ERC_TestSimilarLabels=1 25 | [pcbnew] 26 | version=1 27 | PageLayoutDescrFile= 28 | LastNetListRead=i5ether.net 29 | CopperLayerCount=2 30 | BoardThickness=1.6 31 | AllowMicroVias=0 32 | AllowBlindVias=0 33 | RequireCourtyardDefinitions=0 34 | ProhibitOverlappingCourtyards=1 35 | MinTrackWidth=0.2 36 | MinViaDiameter=0.4 37 | MinViaDrill=0.3 38 | MinMicroViaDiameter=0.2 39 | MinMicroViaDrill=0.09999999999999999 40 | MinHoleToHole=0.25 41 | TrackWidth1=0.25 42 | ViaDiameter1=0.8 43 | ViaDrill1=0.4 44 | dPairWidth1=0.2 45 | dPairGap1=0.25 46 | dPairViaGap1=0.25 47 | SilkLineWidth=0.12 48 | SilkTextSizeV=1 49 | SilkTextSizeH=1 50 | SilkTextSizeThickness=0.15 51 | SilkTextItalic=0 52 | SilkTextUpright=1 53 | CopperLineWidth=0.2 54 | CopperTextSizeV=1.5 55 | CopperTextSizeH=1.5 56 | CopperTextThickness=0.3 57 | CopperTextItalic=0 58 | CopperTextUpright=1 59 | EdgeCutLineWidth=0.05 60 | CourtyardLineWidth=0.05 61 | OthersLineWidth=0.15 62 | OthersTextSizeV=1 63 | OthersTextSizeH=1 64 | OthersTextSizeThickness=0.15 65 | OthersTextItalic=0 66 | OthersTextUpright=1 67 | SolderMaskClearance=0.051 68 | SolderMaskMinWidth=0.25 69 | SolderPasteClearance=0 70 | SolderPasteRatio=0 71 | [pcbnew/Layer.F.Cu] 72 | Name=F.Cu 73 | Type=0 74 | Enabled=1 75 | [pcbnew/Layer.In1.Cu] 76 | Name=In1.Cu 77 | Type=0 78 | Enabled=0 79 | [pcbnew/Layer.In2.Cu] 80 | Name=In2.Cu 81 | Type=0 82 | Enabled=0 83 | [pcbnew/Layer.In3.Cu] 84 | Name=In3.Cu 85 | Type=0 86 | Enabled=0 87 | [pcbnew/Layer.In4.Cu] 88 | Name=In4.Cu 89 | Type=0 90 | Enabled=0 91 | [pcbnew/Layer.In5.Cu] 92 | Name=In5.Cu 93 | Type=0 94 | Enabled=0 95 | [pcbnew/Layer.In6.Cu] 96 | Name=In6.Cu 97 | Type=0 98 | Enabled=0 99 | [pcbnew/Layer.In7.Cu] 100 | Name=In7.Cu 101 | Type=0 102 | Enabled=0 103 | [pcbnew/Layer.In8.Cu] 104 | Name=In8.Cu 105 | Type=0 106 | Enabled=0 107 | [pcbnew/Layer.In9.Cu] 108 | Name=In9.Cu 109 | Type=0 110 | Enabled=0 111 | [pcbnew/Layer.In10.Cu] 112 | Name=In10.Cu 113 | Type=0 114 | Enabled=0 115 | [pcbnew/Layer.In11.Cu] 116 | Name=In11.Cu 117 | Type=0 118 | Enabled=0 119 | [pcbnew/Layer.In12.Cu] 120 | Name=In12.Cu 121 | Type=0 122 | Enabled=0 123 | [pcbnew/Layer.In13.Cu] 124 | Name=In13.Cu 125 | Type=0 126 | Enabled=0 127 | [pcbnew/Layer.In14.Cu] 128 | Name=In14.Cu 129 | Type=0 130 | Enabled=0 131 | [pcbnew/Layer.In15.Cu] 132 | Name=In15.Cu 133 | Type=0 134 | Enabled=0 135 | [pcbnew/Layer.In16.Cu] 136 | Name=In16.Cu 137 | Type=0 138 | Enabled=0 139 | [pcbnew/Layer.In17.Cu] 140 | Name=In17.Cu 141 | Type=0 142 | Enabled=0 143 | [pcbnew/Layer.In18.Cu] 144 | Name=In18.Cu 145 | Type=0 146 | Enabled=0 147 | [pcbnew/Layer.In19.Cu] 148 | Name=In19.Cu 149 | Type=0 150 | Enabled=0 151 | [pcbnew/Layer.In20.Cu] 152 | Name=In20.Cu 153 | Type=0 154 | Enabled=0 155 | [pcbnew/Layer.In21.Cu] 156 | Name=In21.Cu 157 | Type=0 158 | Enabled=0 159 | [pcbnew/Layer.In22.Cu] 160 | Name=In22.Cu 161 | Type=0 162 | Enabled=0 163 | [pcbnew/Layer.In23.Cu] 164 | Name=In23.Cu 165 | Type=0 166 | Enabled=0 167 | [pcbnew/Layer.In24.Cu] 168 | Name=In24.Cu 169 | Type=0 170 | Enabled=0 171 | [pcbnew/Layer.In25.Cu] 172 | Name=In25.Cu 173 | Type=0 174 | Enabled=0 175 | [pcbnew/Layer.In26.Cu] 176 | Name=In26.Cu 177 | Type=0 178 | Enabled=0 179 | [pcbnew/Layer.In27.Cu] 180 | Name=In27.Cu 181 | Type=0 182 | Enabled=0 183 | [pcbnew/Layer.In28.Cu] 184 | Name=In28.Cu 185 | Type=0 186 | Enabled=0 187 | [pcbnew/Layer.In29.Cu] 188 | Name=In29.Cu 189 | Type=0 190 | Enabled=0 191 | [pcbnew/Layer.In30.Cu] 192 | Name=In30.Cu 193 | Type=0 194 | Enabled=0 195 | [pcbnew/Layer.B.Cu] 196 | Name=B.Cu 197 | Type=0 198 | Enabled=1 199 | [pcbnew/Layer.B.Adhes] 200 | Enabled=1 201 | [pcbnew/Layer.F.Adhes] 202 | Enabled=1 203 | [pcbnew/Layer.B.Paste] 204 | Enabled=1 205 | [pcbnew/Layer.F.Paste] 206 | Enabled=1 207 | [pcbnew/Layer.B.SilkS] 208 | Enabled=1 209 | [pcbnew/Layer.F.SilkS] 210 | Enabled=1 211 | [pcbnew/Layer.B.Mask] 212 | Enabled=1 213 | [pcbnew/Layer.F.Mask] 214 | Enabled=1 215 | [pcbnew/Layer.Dwgs.User] 216 | Enabled=1 217 | [pcbnew/Layer.Cmts.User] 218 | Enabled=1 219 | [pcbnew/Layer.Eco1.User] 220 | Enabled=1 221 | [pcbnew/Layer.Eco2.User] 222 | Enabled=1 223 | [pcbnew/Layer.Edge.Cuts] 224 | Enabled=1 225 | [pcbnew/Layer.Margin] 226 | Enabled=1 227 | [pcbnew/Layer.B.CrtYd] 228 | Enabled=1 229 | [pcbnew/Layer.F.CrtYd] 230 | Enabled=1 231 | [pcbnew/Layer.B.Fab] 232 | Enabled=1 233 | [pcbnew/Layer.F.Fab] 234 | Enabled=1 235 | [pcbnew/Layer.Rescue] 236 | Enabled=1 237 | [pcbnew/Netclasses] 238 | [pcbnew/Netclasses/Default] 239 | Name=Default 240 | Clearance=0.2 241 | TrackWidth=0.25 242 | ViaDiameter=0.8 243 | ViaDrill=0.4 244 | uViaDiameter=0.3 245 | uViaDrill=0.1 246 | dPairWidth=0.2 247 | dPairGap=0.25 248 | dPairViaGap=0.25 249 | -------------------------------------------------------------------------------- /i5ether/i5ether-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # Connector_Generic_Conn_02x15_Odd_Even 5 | # 6 | DEF Connector_Generic_Conn_02x15_Odd_Even J 0 40 Y N 1 F N 7 | F0 "J" 50 800 50 H V C CNN 8 | F1 "Connector_Generic_Conn_02x15_Odd_Even" 50 -800 50 H V C CNN 9 | F2 "" 0 0 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | $FPLIST 12 | Connector*:*_2x??_* 13 | $ENDFPLIST 14 | DRAW 15 | S -50 -695 0 -705 1 1 6 N 16 | S -50 -595 0 -605 1 1 6 N 17 | S -50 -495 0 -505 1 1 6 N 18 | S -50 -395 0 -405 1 1 6 N 19 | S -50 -295 0 -305 1 1 6 N 20 | S -50 -195 0 -205 1 1 6 N 21 | S -50 -95 0 -105 1 1 6 N 22 | S -50 5 0 -5 1 1 6 N 23 | S -50 105 0 95 1 1 6 N 24 | S -50 205 0 195 1 1 6 N 25 | S -50 305 0 295 1 1 6 N 26 | S -50 405 0 395 1 1 6 N 27 | S -50 505 0 495 1 1 6 N 28 | S -50 605 0 595 1 1 6 N 29 | S -50 705 0 695 1 1 6 N 30 | S -50 750 150 -750 1 1 10 f 31 | S 150 -695 100 -705 1 1 6 N 32 | S 150 -595 100 -605 1 1 6 N 33 | S 150 -495 100 -505 1 1 6 N 34 | S 150 -395 100 -405 1 1 6 N 35 | S 150 -295 100 -305 1 1 6 N 36 | S 150 -195 100 -205 1 1 6 N 37 | S 150 -95 100 -105 1 1 6 N 38 | S 150 5 100 -5 1 1 6 N 39 | S 150 105 100 95 1 1 6 N 40 | S 150 205 100 195 1 1 6 N 41 | S 150 305 100 295 1 1 6 N 42 | S 150 405 100 395 1 1 6 N 43 | S 150 505 100 495 1 1 6 N 44 | S 150 605 100 595 1 1 6 N 45 | S 150 705 100 695 1 1 6 N 46 | X Pin_1 1 -200 700 150 R 50 50 1 1 P 47 | X Pin_10 10 300 300 150 L 50 50 1 1 P 48 | X Pin_11 11 -200 200 150 R 50 50 1 1 P 49 | X Pin_12 12 300 200 150 L 50 50 1 1 P 50 | X Pin_13 13 -200 100 150 R 50 50 1 1 P 51 | X Pin_14 14 300 100 150 L 50 50 1 1 P 52 | X Pin_15 15 -200 0 150 R 50 50 1 1 P 53 | X Pin_16 16 300 0 150 L 50 50 1 1 P 54 | X Pin_17 17 -200 -100 150 R 50 50 1 1 P 55 | X Pin_18 18 300 -100 150 L 50 50 1 1 P 56 | X Pin_19 19 -200 -200 150 R 50 50 1 1 P 57 | X Pin_2 2 300 700 150 L 50 50 1 1 P 58 | X Pin_20 20 300 -200 150 L 50 50 1 1 P 59 | X Pin_21 21 -200 -300 150 R 50 50 1 1 P 60 | X Pin_22 22 300 -300 150 L 50 50 1 1 P 61 | X Pin_23 23 -200 -400 150 R 50 50 1 1 P 62 | X Pin_24 24 300 -400 150 L 50 50 1 1 P 63 | X Pin_25 25 -200 -500 150 R 50 50 1 1 P 64 | X Pin_26 26 300 -500 150 L 50 50 1 1 P 65 | X Pin_27 27 -200 -600 150 R 50 50 1 1 P 66 | X Pin_28 28 300 -600 150 L 50 50 1 1 P 67 | X Pin_29 29 -200 -700 150 R 50 50 1 1 P 68 | X Pin_3 3 -200 600 150 R 50 50 1 1 P 69 | X Pin_30 30 300 -700 150 L 50 50 1 1 P 70 | X Pin_4 4 300 600 150 L 50 50 1 1 P 71 | X Pin_5 5 -200 500 150 R 50 50 1 1 P 72 | X Pin_6 6 300 500 150 L 50 50 1 1 P 73 | X Pin_7 7 -200 400 150 R 50 50 1 1 P 74 | X Pin_8 8 300 400 150 L 50 50 1 1 P 75 | X Pin_9 9 -200 300 150 R 50 50 1 1 P 76 | ENDDRAW 77 | ENDDEF 78 | # 79 | # Device_C_Small 80 | # 81 | DEF Device_C_Small C 0 10 N N 1 F N 82 | F0 "C" 10 70 50 H V L CNN 83 | F1 "Device_C_Small" 10 -80 50 H V L CNN 84 | F2 "" 0 0 50 H I C CNN 85 | F3 "" 0 0 50 H I C CNN 86 | $FPLIST 87 | C_* 88 | $ENDFPLIST 89 | DRAW 90 | P 2 0 1 13 -60 -20 60 -20 N 91 | P 2 0 1 12 -60 20 60 20 N 92 | X ~ 1 0 100 80 D 50 50 1 1 P 93 | X ~ 2 0 -100 80 U 50 50 1 1 P 94 | ENDDRAW 95 | ENDDEF 96 | # 97 | # Device_R_Small 98 | # 99 | DEF Device_R_Small R 0 10 N N 1 F N 100 | F0 "R" 30 20 50 H V L CNN 101 | F1 "Device_R_Small" 30 -40 50 H V L CNN 102 | F2 "" 0 0 50 H I C CNN 103 | F3 "" 0 0 50 H I C CNN 104 | $FPLIST 105 | R_* 106 | $ENDFPLIST 107 | DRAW 108 | S -30 70 30 -70 0 1 8 N 109 | X ~ 1 0 100 30 D 50 50 1 1 P 110 | X ~ 2 0 -100 30 U 50 50 1 1 P 111 | ENDDRAW 112 | ENDDEF 113 | # 114 | # HX5008_HX5008 115 | # 116 | DEF HX5008_HX5008 T 0 40 Y Y 1 F N 117 | F0 "T" -250 650 50 H V C CNN 118 | F1 "HX5008_HX5008" 0 650 50 H V C CNN 119 | F2 "HX5008:HX5008NL" 0 500 50 H I C CNN 120 | F3 "" 0 500 50 H I C CNN 121 | DRAW 122 | S -300 -750 250 550 0 1 0 f 123 | X TCT1 1 -400 450 100 R 50 50 1 1 I 124 | X TCT4 10 -400 -450 100 R 50 50 1 1 I 125 | X TD4+ 11 -400 -550 100 R 50 50 1 1 I 126 | X TD4- 12 -400 -650 100 R 50 50 1 1 I 127 | X MX4- 13 350 -650 100 L 50 50 1 1 I 128 | X MX4+ 14 350 -550 100 L 50 50 1 1 I 129 | X MCT4 15 350 -450 100 L 50 50 1 1 I 130 | X MX3- 16 350 -350 100 L 50 50 1 1 I 131 | X MX3+ 17 350 -250 100 L 50 50 1 1 I 132 | X MCT3 18 350 -150 100 L 50 50 1 1 I 133 | X MX2- 19 350 -50 100 L 50 50 1 1 I 134 | X TD1+ 2 -400 350 100 R 50 50 1 1 I 135 | X MX2+ 20 350 50 100 L 50 50 1 1 I 136 | X MCT2 21 350 150 100 L 50 50 1 1 I 137 | X MX1- 22 350 250 100 L 50 50 1 1 I 138 | X MX1+ 23 350 350 100 L 50 50 1 1 I 139 | X MCT1 24 350 450 100 L 50 50 1 1 I 140 | X TD1- 3 -400 250 100 R 50 50 1 1 I 141 | X TCT2 4 -400 150 100 R 50 50 1 1 I 142 | X TD2+ 5 -400 50 100 R 50 50 1 1 I 143 | X TD2- 6 -400 -50 100 R 50 50 1 1 I 144 | X TCT3 7 -400 -150 100 R 50 50 1 1 I 145 | X TD3+ 8 -400 -250 100 R 50 50 1 1 I 146 | X TD3- 9 -400 -350 100 R 50 50 1 1 I 147 | ENDDRAW 148 | ENDDEF 149 | # 150 | # MJ406541_1-406541-1 151 | # 152 | DEF MJ406541_1-406541-1 J 0 10 Y N 1 L N 153 | F0 "J" 350 250 60 H V C CNN 154 | F1 "MJ406541_1-406541-1" 400 -400 60 H V C CNN 155 | F2 "CONN8_406541_TEC" 400 -460 60 H I C CNN 156 | F3 "" 0 0 60 H V C CNN 157 | $FPLIST 158 | CONN8_406541_TEC 159 | $ENDFPLIST 160 | DRAW 161 | S 500 -1000 200 100 0 1 8 f 162 | P 2 1 1 5 200 -1000 500 -1000 N 163 | P 2 1 1 5 200 100 200 -1000 N 164 | P 2 1 1 5 400 -700 200 -700 N 165 | P 2 1 1 5 400 -700 350 -733 N 166 | P 2 1 1 5 400 -700 350 -667 N 167 | P 2 1 1 5 400 -600 200 -600 N 168 | P 2 1 1 5 400 -600 350 -633 N 169 | P 2 1 1 5 400 -600 350 -567 N 170 | P 2 1 1 5 400 -500 200 -500 N 171 | P 2 1 1 5 400 -500 350 -533 N 172 | P 2 1 1 5 400 -500 350 -467 N 173 | P 2 1 1 5 400 -400 200 -400 N 174 | P 2 1 1 5 400 -400 350 -433 N 175 | P 2 1 1 5 400 -400 350 -367 N 176 | P 2 1 1 5 400 -300 200 -300 N 177 | P 2 1 1 5 400 -300 350 -333 N 178 | P 2 1 1 5 400 -300 350 -267 N 179 | P 2 1 1 5 400 -200 200 -200 N 180 | P 2 1 1 5 400 -200 350 -233 N 181 | P 2 1 1 5 400 -200 350 -167 N 182 | P 2 1 1 5 400 -100 200 -100 N 183 | P 2 1 1 5 400 -100 350 -133 N 184 | P 2 1 1 5 400 -100 350 -67 N 185 | P 2 1 1 5 400 0 200 0 N 186 | P 2 1 1 5 400 0 350 -33 N 187 | P 2 1 1 5 400 0 350 33 N 188 | P 2 1 1 5 500 -1000 500 100 N 189 | P 2 1 1 5 500 100 200 100 N 190 | X 1 1 0 0 200 R 59 59 1 1 O 191 | X SHIELD 10 0 -900 200 R 59 59 1 1 I 192 | X 2 2 0 -100 200 R 59 59 1 1 O 193 | X 3 3 0 -200 200 R 59 59 1 1 O 194 | X 4 4 0 -300 200 R 59 59 1 1 O 195 | X 5 5 0 -400 200 R 59 59 1 1 O 196 | X 6 6 0 -500 200 R 59 59 1 1 O 197 | X 7 7 0 -600 200 R 59 59 1 1 O 198 | X 8 8 0 -700 200 R 59 59 1 1 O 199 | X SHIELD 9 0 -800 200 R 59 59 1 1 I 200 | ENDDRAW 201 | ENDDEF 202 | # 203 | # power_Earth 204 | # 205 | DEF power_Earth #PWR 0 0 Y Y 1 F P 206 | F0 "#PWR" 0 -250 50 H I C CNN 207 | F1 "power_Earth" 0 -150 50 H I C CNN 208 | F2 "" 0 0 50 H I C CNN 209 | F3 "" 0 0 50 H I C CNN 210 | DRAW 211 | P 2 0 1 0 -25 -75 25 -75 N 212 | P 2 0 1 0 -5 -100 5 -100 N 213 | P 2 0 1 0 0 -50 0 0 N 214 | P 2 0 1 0 50 -50 -50 -50 N 215 | X Earth 1 0 0 0 D 50 50 1 1 W N 216 | ENDDRAW 217 | ENDDEF 218 | # 219 | # power_GND 220 | # 221 | DEF power_GND #PWR 0 0 Y Y 1 F P 222 | F0 "#PWR" 0 -250 50 H I C CNN 223 | F1 "power_GND" 0 -150 50 H V C CNN 224 | F2 "" 0 0 50 H I C CNN 225 | F3 "" 0 0 50 H I C CNN 226 | DRAW 227 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 228 | X GND 1 0 0 0 D 50 50 1 1 W N 229 | ENDDRAW 230 | ENDDEF 231 | # 232 | # power_PWR_FLAG 233 | # 234 | DEF power_PWR_FLAG #FLG 0 0 N N 1 F P 235 | F0 "#FLG" 0 75 50 H I C CNN 236 | F1 "power_PWR_FLAG" 0 150 50 H V C CNN 237 | F2 "" 0 0 50 H I C CNN 238 | F3 "" 0 0 50 H I C CNN 239 | DRAW 240 | P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N 241 | X pwr 1 0 0 0 U 50 50 0 0 w 242 | ENDDRAW 243 | ENDDEF 244 | # 245 | #End Library 246 | -------------------------------------------------------------------------------- /i5ether/i5ether.xml: -------------------------------------------------------------------------------- 1 | 2 | 3#0000004#0000ee5#0066006#3333337#8080808#9966009#c0c0c010#cc000011#ccffcc12#dddddd13#ffcccc14#ffffcc15#ffffff90001386024075FalseFalse