├── .gitignore ├── DDR3.csv ├── README.md ├── datasheet.txt ├── docs ├── phy_only_support_readme.txt ├── pic │ ├── arid==0.png │ ├── awid==0.png │ ├── awid==1.png │ ├── awvalid_change_config.png │ ├── axi_burst_length.png │ ├── axi_burst_size.png │ └── wid!=rid.png ├── ug586_7Series_MIS.pdf └── 记录.xlsx ├── example_design ├── log.txt ├── par │ ├── create_ise.bat │ ├── ddr_icon_cg.xco │ ├── ddr_ila_basic_cg.xco │ ├── ddr_ila_rdpath_cg.xco │ ├── ddr_ila_wrpath_cg.xco │ ├── ddr_vio_async_in_sync_out_cg.xco │ ├── ddr_vio_sync_async_out72_cg.xco │ ├── example_top.cpj │ ├── example_top.ucf │ ├── example_top.xdc │ ├── ise_flow.bat │ ├── makeproj.bat │ ├── readme.txt │ ├── rem_files.bat │ ├── rem_files.tcl │ ├── set_ise_prop.tcl │ └── xst_options.txt ├── rtl │ ├── example_top.v │ └── traffic_gen │ │ ├── mig_7series_v1_9_axi4_tg.v │ │ ├── mig_7series_v1_9_axi4_wrapper.v │ │ ├── mig_7series_v1_9_cmd_prbs_gen_axi.v │ │ ├── mig_7series_v1_9_data_gen_chk.v │ │ └── mig_7series_v1_9_tg.v ├── sim │ ├── ddr3_model.v │ ├── ddr3_model_parameters.vh │ ├── isim_files.prj │ ├── isim_options.tcl │ ├── isim_run.bat │ ├── readme.txt │ ├── sim.do │ ├── sim_tb_top.v │ ├── wiredly.v │ ├── xsim_files.prj │ ├── xsim_options.tcl │ └── xsim_run.bat └── synth │ ├── example_top.lso │ ├── example_top.prj │ └── synplify_pro.tcl ├── mig.prj ├── sim ├── axi_drive.v ├── demo.tcl └── wave.do └── user_design ├── constraints ├── DDR3.ucf └── DDR3.xdc ├── log.txt └── rtl ├── DDR3.v ├── axi ├── mig_7series_v1_9_axi_ctrl_addr_decode.v ├── mig_7series_v1_9_axi_ctrl_read.v ├── mig_7series_v1_9_axi_ctrl_reg.v ├── mig_7series_v1_9_axi_ctrl_reg_bank.v ├── mig_7series_v1_9_axi_ctrl_top.v ├── mig_7series_v1_9_axi_ctrl_write.v ├── mig_7series_v1_9_axi_mc.v ├── mig_7series_v1_9_axi_mc_ar_channel.v ├── mig_7series_v1_9_axi_mc_aw_channel.v ├── mig_7series_v1_9_axi_mc_b_channel.v ├── mig_7series_v1_9_axi_mc_cmd_arbiter.v ├── mig_7series_v1_9_axi_mc_cmd_fsm.v ├── mig_7series_v1_9_axi_mc_cmd_translator.v ├── mig_7series_v1_9_axi_mc_incr_cmd.v ├── mig_7series_v1_9_axi_mc_r_channel.v ├── mig_7series_v1_9_axi_mc_simple_fifo.v ├── mig_7series_v1_9_axi_mc_w_channel.v ├── mig_7series_v1_9_axi_mc_wr_cmd_fsm.v ├── mig_7series_v1_9_axi_mc_wrap_cmd.v ├── mig_7series_v1_9_ddr_a_upsizer.v ├── mig_7series_v1_9_ddr_axi_register_slice.v ├── mig_7series_v1_9_ddr_axi_upsizer.v ├── mig_7series_v1_9_ddr_axic_register_slice.v ├── mig_7series_v1_9_ddr_carry_and.v ├── mig_7series_v1_9_ddr_carry_latch_and.v ├── mig_7series_v1_9_ddr_carry_latch_or.v ├── mig_7series_v1_9_ddr_carry_or.v ├── mig_7series_v1_9_ddr_command_fifo.v ├── mig_7series_v1_9_ddr_comparator.v ├── mig_7series_v1_9_ddr_comparator_sel.v ├── mig_7series_v1_9_ddr_comparator_sel_static.v ├── mig_7series_v1_9_ddr_r_upsizer.v └── mig_7series_v1_9_ddr_w_upsizer.v ├── clocking ├── mig_7series_v1_9_clk_ibuf.v ├── mig_7series_v1_9_infrastructure.v ├── mig_7series_v1_9_iodelay_ctrl.v └── mig_7series_v1_9_tempmon.v ├── controller ├── mig_7series_v1_9_arb_mux.v ├── mig_7series_v1_9_arb_row_col.v ├── mig_7series_v1_9_arb_select.v ├── mig_7series_v1_9_bank_cntrl.v ├── mig_7series_v1_9_bank_common.v ├── mig_7series_v1_9_bank_compare.v ├── mig_7series_v1_9_bank_mach.v ├── mig_7series_v1_9_bank_queue.v ├── mig_7series_v1_9_bank_state.v ├── mig_7series_v1_9_col_mach.v ├── mig_7series_v1_9_mc.v ├── mig_7series_v1_9_rank_cntrl.v ├── mig_7series_v1_9_rank_common.v ├── mig_7series_v1_9_rank_mach.v └── mig_7series_v1_9_round_robin_arb.v ├── ecc ├── mig_7series_v1_9_ecc_buf.v ├── mig_7series_v1_9_ecc_dec_fix.v ├── mig_7series_v1_9_ecc_gen.v └── mig_7series_v1_9_ecc_merge_enc.v ├── ip_top ├── mig_7series_v1_9_mem_intfc.v └── mig_7series_v1_9_memc_ui_top_axi.v ├── phy ├── mig_7series_v1_9_ddr_byte_group_io.v ├── mig_7series_v1_9_ddr_byte_lane.v ├── mig_7series_v1_9_ddr_calib_top.v ├── mig_7series_v1_9_ddr_if_post_fifo.v ├── mig_7series_v1_9_ddr_mc_phy.v ├── mig_7series_v1_9_ddr_mc_phy_wrapper.v ├── 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