├── .gitignore ├── README.rst ├── doc ├── Makefile ├── _static │ ├── Kreon-Bold.woff2 │ ├── Kreon-Light.woff2 │ ├── Kreon-Regular.woff2 │ └── project.css ├── _templates │ ├── about.html │ ├── layout.html │ ├── page.html │ └── projects.html ├── conf.py ├── image │ ├── vhdl-extras-sm.png │ └── vhdl-extras.png ├── index.rst ├── make.bat └── rst │ ├── modules │ ├── arithmetic.rst │ ├── auto │ │ ├── arithmetic.rst │ │ ├── bcd_conversion.rst │ │ ├── binaryio.rst │ │ ├── bit_ops.rst │ │ ├── characters_handling.rst │ │ ├── characters_latin_1.rst │ │ ├── common_2008.rst │ │ ├── cordic.rst │ │ ├── crc_ops.rst │ │ ├── ddfs.rst │ │ ├── fifos.rst │ │ ├── filtering.rst │ │ ├── freq_gen.rst │ │ ├── glitch_filtering.rst │ │ ├── gray_code.rst │ │ ├── hamming_edac.rst │ │ ├── interrupt_ctl.rst │ │ ├── lcar_ops.rst │ │ ├── lfsr_ops.rst │ │ ├── memory.rst │ │ ├── muxing.rst │ │ ├── muxing_2008.rst │ │ ├── oscillator.rst │ │ ├── parity_ops.rst │ │ ├── pipelining.rst │ │ ├── pipelining_2008.rst │ │ ├── prng.rst │ │ ├── random.rst │ │ ├── random_20xx.rst │ │ ├── reg_file.rst │ │ ├── reg_file_2008.rst │ │ ├── secded_codec.rst │ │ ├── secded_edac.rst │ │ ├── sizing.rst │ │ ├── strings.rst │ │ ├── strings_bounded.rst │ │ ├── strings_fixed.rst │ │ ├── strings_maps.rst │ │ ├── strings_maps_constants.rst │ │ ├── strings_unbounded.rst │ │ ├── synchronizing.rst │ │ ├── text_buffering.rst │ │ ├── timing_ops.rst │ │ └── timing_ops_xilinx.rst │ ├── bcd_conversion.rst │ ├── binaryio.rst │ ├── bit_ops.rst │ ├── characters_handling.rst │ ├── characters_latin_1.rst │ ├── common_2008.rst │ ├── cordic.rst │ ├── crc_ops.rst │ ├── ddfs.rst │ ├── fifos.rst │ ├── filtering.rst │ ├── glitch_filtering.rst │ ├── gray_code.rst │ ├── hamming_edac.rst │ ├── interrupt_ctl.rst │ ├── lcar_ops.rst │ ├── lfsr_ops.rst │ ├── memory.rst │ ├── muxing.rst │ ├── oscillator.rst │ ├── parity_ops.rst │ ├── pipelining.rst │ ├── random.rst │ ├── reg_file.rst │ ├── secded_codec.rst │ ├── secded_edac.rst │ ├── sizing.rst │ ├── strings.rst │ ├── strings_bounded.rst │ ├── strings_fixed.rst │ ├── strings_maps.rst │ ├── strings_maps_constants.rst │ ├── strings_unbounded.rst │ ├── synchronizing.rst │ ├── text_buffering.rst │ └── timing_ops.rst │ └── packages.rst ├── makefile ├── modelsim.map ├── rtl ├── extras │ ├── arithmetic.vhdl │ ├── bcd_conversion.vhdl │ ├── binaryio.vhdl │ ├── bit_ops.vhdl │ ├── characters_handling.vhdl │ ├── characters_latin_1.vhdl │ ├── cordic.vhdl │ ├── crc_ops.vhdl │ ├── ddfs.vhdl │ ├── fifos.vhdl │ ├── glitch_filtering.vhdl │ ├── gray_code.vhdl │ ├── hamming_edac.vhdl │ ├── interrupt_ctl.vhdl │ ├── lcar_ops.vhdl │ ├── lfsr_ops.vhdl │ ├── memory.vhdl │ ├── muxing.vhdl │ ├── oscillator.vhdl │ ├── parity_ops.vhdl │ ├── pipelining.vhdl │ ├── random.vhdl │ ├── reg_file.vhdl │ ├── secded_codec.vhdl │ ├── secded_edac.vhdl │ ├── sizing.vhdl │ ├── strings.vhdl │ ├── strings_fixed.vhdl │ ├── strings_maps.vhdl │ ├── strings_maps_constants.vhdl │ ├── strings_unbounded.vhdl │ ├── synchronizing.vhdl │ ├── text_buffering.vhdl │ ├── timing_ops.vhdl │ └── timing_ops_xilinx.vhdl ├── extras_2008 │ ├── common_2008.vhdl │ ├── filtering.vhdl │ ├── muxing_2008.vhdl │ ├── pipelining_2008.vhdl │ ├── random_20xx.vhdl │ ├── reg_file_2008.vhdl │ ├── sizing_2008.vhdl │ └── strings_bounded.vhdl ├── test │ ├── test_array_glitch_filter.vhdl │ ├── test_bcd_conversion.vhdl │ ├── test_binaryio.vhdl │ ├── test_characters_handling.vhdl │ ├── test_crc_ops.vhdl │ ├── test_ddfs.vhdl │ ├── test_dual_port_ram.vhdl │ ├── test_fifo.vhdl │ ├── test_glitch_filter.vhdl │ ├── test_gray_code.vhdl │ ├── test_hamming_edac.vhdl │ ├── test_handshake_synchronizer.vhdl │ ├── test_interrupt_ctl.vhdl │ ├── test_lcar_ops.vhdl │ ├── test_lfsr_ops.vhdl │ ├── test_muxing.vhdl │ ├── test_packet_fifo.vhdl │ ├── test_parity_ops.vhdl │ ├── test_pipelined_adder.vhdl │ ├── test_random.vhdl │ ├── test_reg_file.vhdl │ ├── test_rom.vhdl │ ├── test_secded_codec.vhdl │ ├── test_secded_edac.vhdl │ ├── test_simple_fifo.vhdl │ ├── test_sizing.vhdl │ ├── test_strings_fixed.vhdl │ ├── test_strings_maps.vhdl │ ├── test_strings_unbounded.vhdl │ ├── test_text_buffering.vhdl │ └── test_timing_ops.vhdl └── test_2008 │ ├── test_muxing_2008.vhdl │ ├── test_random_20xx.vhdl │ ├── test_reg_file_2008.vhdl │ └── test_strings_bounded.vhdl ├── scripts ├── __init__.py ├── ada │ ├── smc_gen.sh │ ├── strings_maps_constants.head.vhdl │ └── vhdl_gen.adb ├── color.py ├── init_modelsim.py └── vdep.py ├── start_proj.sh └── test ├── __init__.py ├── eng.py ├── modelsim.py ├── test_support.py └── test_vhdl.py /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.pyc 3 | __pycache__/ 4 | opbasm.egg-info/ 5 | build/ 6 | dist/ 7 | _build 8 | test/test-output 9 | modelsim.ini 10 | -------------------------------------------------------------------------------- /doc/_static/Kreon-Bold.woff2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/doc/_static/Kreon-Bold.woff2 -------------------------------------------------------------------------------- /doc/_static/Kreon-Light.woff2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/doc/_static/Kreon-Light.woff2 -------------------------------------------------------------------------------- /doc/_static/Kreon-Regular.woff2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/doc/_static/Kreon-Regular.woff2 -------------------------------------------------------------------------------- /doc/_static/project.css: -------------------------------------------------------------------------------- 1 | 2 | @font-face { 3 | font-family: 'Kreon'; 4 | font-style: normal; 5 | font-weight: 300; 6 | src: local('Kreon Light'), local('Kreon-Light'), url('Kreon-Light.woff2') format('woff2'); 7 | } 8 | @font-face { 9 | font-family: 'Kreon'; 10 | font-style: normal; 11 | font-weight: 400; 12 | src: local('Kreon Regular'), local('Kreon-Regular'), url('Kreon-Regular.woff2') format('woff2'); 13 | } 14 | @font-face { 15 | font-family: 'Kreon'; 16 | font-style: normal; 17 | font-weight: 700; 18 | src: local('Kreon Bold'), local('Kreon-Bold'), url('Kreon-Bold.woff2') format('woff2'); 19 | } 20 | 21 | 22 | body { 23 | font-size: medium; 24 | background-color: white; 25 | color: #000; 26 | margin: 0; 27 | padding: 0 1.1em 0 0; 28 | } 29 | 30 | div.document { 31 | width: 100%; 32 | max-width: 1200px; 33 | margin: 0 auto 0 auto; 34 | padding: 0 0em 0 1em; 35 | } 36 | 37 | pre, code { 38 | font-size: small; 39 | } 40 | 41 | 42 | div.body h1, 43 | div.body h2, 44 | div.body h3, 45 | div.body h4 { 46 | font-family: "Kreon", "goudy old style", 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88 | 89 | pre { 90 | background: #E9ECF5; 91 | 92 | -webkit-box-shadow: 0 1px 3px rgba(0,0,0,0.12), 0 1px 2px rgba(0,0,0,0.24); 93 | -moz-box-shadow: 0 1px 3px rgba(0,0,0,0.12), 0 1px 2px rgba(0,0,0,0.24); 94 | box-shadow: 0 1px 3px rgba(0,0,0,0.12), 0 1px 2px rgba(0,0,0,0.24); 95 | } 96 | 97 | dl.macro { 98 | margin-top: 5em; 99 | } 100 | 101 | 102 | div.dl-button a, div.dl-button a:hover { 103 | display: block; 104 | height: 36px; 105 | background: #008c00; 106 | 107 | color: white; 108 | font: 16px/36px Helvetica, Verdana, sans-serif; 109 | text-decoration: none; 110 | text-align: center; 111 | text-transform: uppercase; 112 | 113 | border: 4px solid white; 114 | margin: 2px; 115 | 116 | -webkit-border-radius: 10px; 117 | -moz-border-radius: 10px; 118 | border-radius: 10px; 119 | 120 | -webkit-box-shadow: 0 2px 7px rgba(0,0,0,0.16), 0 3px 6px rgba(0,0,0,0.23); 121 | -moz-box-shadow: 0 2px 7px rgba(0,0,0,0.16), 0 3px 6px rgba(0,0,0,0.23); 122 | box-shadow: 0 2px 7px rgba(0,0,0,0.16), 0 3px 6px rgba(0,0,0,0.23); 123 | } 124 | 125 | div.dl-button a:hover { 126 | 127 | /* Permalink - use to edit and share this gradient: http://colorzilla.com/gradient-editor/#008c00+0,007200+100 */ 128 | background: #008c00; /* Old browsers */ 129 | background: -moz-linear-gradient(top, #008c00 0%, #007200 100%); /* FF3.6+ */ 130 | background: -webkit-gradient(linear, left top, left bottom, color-stop(0%,#008c00), color-stop(100%,#007200)); /* Chrome,Safari4+ */ 131 | background: -webkit-linear-gradient(top, #008c00 0%,#007200 100%); /* Chrome10+,Safari5.1+ */ 132 | background: -o-linear-gradient(top, #008c00 0%,#007200 100%); /* Opera 11.10+ */ 133 | background: -ms-linear-gradient(top, #008c00 0%,#007200 100%); /* IE10+ */ 134 | background: linear-gradient(to bottom, #008c00 0%,#007200 100%); /* W3C */ 135 | filter: progid:DXImageTransform.Microsoft.gradient( startColorstr='#008c00', endColorstr='#007200',GradientType=0 ); /* IE6-9 */ 136 | 137 | } 138 | 139 | p.caption { 140 | font-family: "Kreon", "goudy old style", "minion pro", "bell mt", Georgia, "Hiragino Mincho Pro", serif; 141 | font-size: medium; 142 | font-weight: bold; 143 | } 144 | -------------------------------------------------------------------------------- /doc/_templates/about.html: -------------------------------------------------------------------------------- 1 | {% if theme_logo %} 2 |

{{ project }}

7 | {% endif %} 8 | 9 |

10 | {% else %} 11 | 12 | {% endif %} 13 | 14 | {% if theme_description %} 15 |

{{ theme_description }}

16 | {% endif %} 17 | 18 | {% if theme_github_user and theme_github_repo %} 19 | {% if theme_github_button|lower == 'true' %} 20 |

21 | 23 |

24 | {% endif %} 25 | {% endif %} 26 | 27 | {% if theme_travis_button|lower != 'false' %} 28 | {% if theme_travis_button|lower == 'true' %} 29 | {% set path = theme_github_user + '/' + theme_github_repo %} 30 | {% else %} 31 | {% set path = theme_travis_button %} 32 | {% endif %} 33 |

34 | 35 | https://secure.travis-ci.org/{{ path }}.svg?branch=master 39 | 40 |

41 | {% endif %} 42 | -------------------------------------------------------------------------------- /doc/_templates/layout.html: -------------------------------------------------------------------------------- 1 | {% extends "!layout.html" %} 2 | 3 | {% block footer %} 4 | {{ super() }} 5 | 6 | {% endblock %} 7 | 8 | -------------------------------------------------------------------------------- /doc/_templates/page.html: -------------------------------------------------------------------------------- 1 | {% extends "!page.html" %} 2 | 3 | {% set css_files = css_files + ["_static/project.css"] %} 4 | 5 | 6 | -------------------------------------------------------------------------------- /doc/_templates/projects.html: -------------------------------------------------------------------------------- 1 |

Other projects

2 | 3 |
4 |

5 | {% if project|lower != "opbasm" %}Opbasm
{% endif %} 6 | {% if project|lower != "ripyl" %}Ripyl
{% endif %} 7 | {% if project|lower != "vertcl" %}Vertcl
{% endif %} 8 | {% if project|lower != "vhdl-extras" %}Vhdl-extras
{% endif %} 9 | {% if project|lower != "lecroy colorizer" %}Lecroy-colorizer{% endif %} 10 |

11 |
12 | 13 | 64 | -------------------------------------------------------------------------------- /doc/image/vhdl-extras-sm.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/doc/image/vhdl-extras-sm.png -------------------------------------------------------------------------------- /doc/image/vhdl-extras.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/doc/image/vhdl-extras.png -------------------------------------------------------------------------------- /doc/rst/modules/arithmetic.rst: -------------------------------------------------------------------------------- 1 | ========== 2 | arithmetic 3 | ========== 4 | 5 | `extras/arithmetic.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | :doc:`pipelining` 11 | 12 | Description 13 | ----------- 14 | 15 | This is an implementation of general purpose pipelined adder. It can be configured 16 | for any number of stages and bit widths. The adder is divided into a number of slices 17 | each of which is a conventional adder. The maximum carry chain length is reduced to 18 | ceil(bit-length / slices). 19 | 20 | .. parsed-literal:: 21 | 22 | --[]-[]-[Slice]--> Sum_3 23 | --[]-[Slice]-[]--> Sum_2 24 | --[Slice]-[]-[]--> Sum_1 25 | 26 | 27 | Example usage 28 | ~~~~~~~~~~~~~ 29 | 30 | .. code-block:: vhdl 31 | 32 | -- 16-bit adder partitioned into 4 4-bit slices 33 | signal A, B, Sum : unsigned(15 downto 0); 34 | 35 | pa: pipelined_adder 36 | generic map ( 37 | SLICES => 4, 38 | CONST_B_INPUT => false, 39 | RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL 40 | ) 41 | port map ( 42 | Clock => clock, 43 | Reset => reset, 44 | 45 | A => A, 46 | B => B, 47 | 48 | Sum => Sum 49 | ); 50 | 51 | 52 | .. include:: auto/arithmetic.rst 53 | 54 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/arithmetic.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/arithmetic.vhdl on 2018-06-28 23:37:28.806720 2 | .. vhdl:package:: extras.arithmetic 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | pipelined_adder 10 | ~~~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: arithmetic-pipelined_adder 14 | 15 | component pipelined_adder is 16 | generic ( 17 | SLICES : positive; 18 | CONST_B_INPUT : boolean; 19 | RESET_ACTIVE_LEVEL : std_ulogic 20 | ); 21 | port ( 22 | --# {{clocks|}} 23 | Clock : in std_ulogic; 24 | Reset : in std_ulogic; 25 | --# {{data|}} 26 | A : in unsigned; 27 | B : in unsigned; 28 | Sum : out unsigned 29 | ); 30 | end component; 31 | 32 | | 33 | 34 | 35 | .. vhdl:entity:: pipelined_adder 36 | 37 | Variable size pipelined adder. 38 | 39 | :generic SLICES: Number of pipeline stages 40 | :gtype SLICES: positive 41 | :generic CONST_B_INPUT: Optimize when the B input is constant 42 | :gtype CONST_B_INPUT: boolean 43 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 44 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 45 | 46 | :port Clock: System clock 47 | :ptype Clock: in std_ulogic 48 | :port Reset: Asynchronous reset 49 | :ptype Reset: in std_ulogic 50 | :port A: Addend A 51 | :ptype A: in unsigned 52 | :port B: Addend B 53 | :ptype B: in unsigned 54 | :port Sum: Result sum of A and B 55 | :ptype Sum: out unsigned 56 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/bcd_conversion.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/bcd_conversion.vhdl on 2018-06-28 23:37:29.130821 2 | .. vhdl:package:: extras.bcd_conversion 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | binary_to_bcd 10 | ~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: bcd_conversion-binary_to_bcd 14 | 15 | component binary_to_bcd is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic 18 | ); 19 | port ( 20 | --# {{clocks|}} 21 | Clock : in std_ulogic; 22 | Reset : in std_ulogic; 23 | --# {{control|}} 24 | Convert : in std_ulogic; 25 | Done : out std_ulogic; 26 | --# {{data|}} 27 | Binary : in unsigned; 28 | BCD : out unsigned 29 | ); 30 | end component; 31 | 32 | | 33 | 34 | 35 | .. vhdl:entity:: binary_to_bcd 36 | 37 | Convert a binary input to BCD encoding. A conversion by asserting ``Convert``. 38 | The ``BCD`` output is valid when the ``Done`` signal goes high. 39 | 40 | This component will operate with any size binary array of 4 bits or larger 41 | and produces a BCD array whose length is 4 times the value returned by the 42 | :vhdl:func:`~bcd_conversion.decimal_size` function. 43 | The conversion of an n-bit binary number will take n cycles to complete. 44 | 45 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 46 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 47 | 48 | :port Clock: System clock 49 | :ptype Clock: in std_ulogic 50 | :port Reset: Asynchronous reset 51 | :ptype Reset: in std_ulogic 52 | :port Convert: Start conversion when high 53 | :ptype Convert: in std_ulogic 54 | :port Done: Indicates completed conversion 55 | :ptype Done: out std_ulogic 56 | :port Binary: Binary data to convert 57 | :ptype Binary: in unsigned 58 | :port BCD: Converted output. Retained until next conversion 59 | :ptype BCD: out unsigned 60 | 61 | bcd_to_binary 62 | ~~~~~~~~~~~~~ 63 | 64 | .. symbolator:: 65 | :name: bcd_conversion-bcd_to_binary 66 | 67 | component bcd_to_binary is 68 | generic ( 69 | RESET_ACTIVE_LEVEL : std_ulogic 70 | ); 71 | port ( 72 | --# {{clocks|}} 73 | Clock : in std_ulogic; 74 | Reset : in std_ulogic; 75 | --# {{control|}} 76 | Convert : in std_ulogic; 77 | Done : out std_ulogic; 78 | --# {{data|}} 79 | BCD : in unsigned; 80 | Binary : out unsigned 81 | ); 82 | end component; 83 | 84 | | 85 | 86 | 87 | .. vhdl:entity:: bcd_to_binary 88 | 89 | Convert a BCD encoded input to binary. A conversion by asserting ``Convert``. 90 | The ``Binary`` output is valid when the ``Done`` signal goes high. 91 | 92 | The length of the input must be a multiple of four. The binary array produced will be 93 | large enough to hold the maximum decimal value of the BCD input. Its 94 | length will be ``bit_size(10**(Bcd'length/4) - 1)``. The conversion of a BCD 95 | number to an n-bit binary number will take n+3 cycles to complete. 96 | 97 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 98 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 99 | 100 | :port Clock: System clock 101 | :ptype Clock: in std_ulogic 102 | :port Reset: Asynchronous reset 103 | :ptype Reset: in std_ulogic 104 | :port Convert: Start conversion when high 105 | :ptype Convert: in std_ulogic 106 | :port Done: Indicates completed conversion 107 | :ptype Done: out std_ulogic 108 | :port BCD: BCD data to convert 109 | :ptype BCD: in unsigned 110 | :port Binary: Converted output. Retained until next conversion 111 | :ptype Binary: out unsigned 112 | 113 | Subprograms 114 | ----------- 115 | 116 | 117 | .. vhdl:function:: function decimal_size(n : natural) return natural; 118 | 119 | Calculate the number of decimal digits needed to represent a number n. 120 | 121 | :param n: Value to calculate digits for 122 | :type n: natural 123 | :returns: Decimal digits for n. 124 | 125 | 126 | 127 | .. vhdl:function:: function to_bcd(Binary : unsigned) return unsigned; 128 | 129 | Convert binary number to BCD encoding 130 | This uses the double-dabble algorithm to perform the BCD conversion. It 131 | will operate with any size binary array and return a BCD array whose 132 | length is 4 times the value returned by the decimal_size function. 133 | 134 | :param Binary: Binary encoded value 135 | :type Binary: unsigned 136 | :returns: BCD encoded result. 137 | 138 | 139 | 140 | .. vhdl:function:: function to_binary(Bcd : unsigned) return unsigned; 141 | 142 | Convert a BCD number to binary encoding 143 | This uses the double-dabble algorithm in reverse. The length of the 144 | input must be a multiple of four. The returned binary array will be 145 | large enough to hold the maximum decimal value of the BCD input. Its 146 | length will be bit_size(10**(Bcd'length/4) - 1). 147 | 148 | :param Bcd: BCD encoded value 149 | :type Bcd: unsigned 150 | :returns: Binary encoded result. 151 | 152 | 153 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/binaryio.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/binaryio.vhdl on 2018-06-28 23:37:28.459290 2 | .. vhdl:package:: extras.binaryio 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: octet_file 10 | 11 | File of 8-bit bytes. 12 | 13 | .. vhdl:type:: endianness 14 | 15 | Endianness of multi-byte words. 16 | 17 | * little-endian = least significant octet first : 1234, 123, etc. 18 | * big-endian = most significant octet first : 4321, 321, etc. 19 | 20 | Subprograms 21 | ----------- 22 | 23 | 24 | .. vhdl:procedure:: procedure read(Fh : octet_file; Octet_order : endianness; Word : out unsigned); 25 | 26 | Read binary data into an unsigned vector. 27 | 28 | :param Fh: File handle 29 | :type Fh: None octet_file 30 | :param Octet_order: Endianness of the octets 31 | :type Octet_order: None endianness 32 | :param Word: Data read from the file 33 | :type Word: out unsigned 34 | 35 | 36 | .. vhdl:procedure:: procedure read(Fh : octet_file; Octet_order : endianness; Word : out signed); 37 | 38 | Read binary data into a signed vector. 39 | 40 | :param Fh: File handle 41 | :type Fh: None octet_file 42 | :param Octet_order: Endianness of the octets 43 | :type Octet_order: None endianness 44 | :param Word: Data read from the file 45 | :type Word: out signed 46 | 47 | 48 | .. vhdl:procedure:: procedure write(Fh : octet_file; Octet_order : endianness; Word : unsigned); 49 | 50 | Write an unsigned vector to a file. 51 | 52 | :param Fh: File handle 53 | :type Fh: None octet_file 54 | :param Octet_order: Endianness of the octets 55 | :type Octet_order: None endianness 56 | :param Word: Data to write into the file 57 | :type Word: None unsigned 58 | 59 | 60 | .. vhdl:procedure:: procedure write(Fh : octet_file; Octet_order : endianness; Word : signed); 61 | 62 | Write a signed vector to a file. 63 | 64 | :param Fh: File handle 65 | :type Fh: None octet_file 66 | :param Octet_order: Endianness of the octets 67 | :type Octet_order: None endianness 68 | :param Word: Data to write into the file. Will be sign extended if not a multiple of 8-bits. 69 | :type Word: None signed 70 | 71 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/bit_ops.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/bit_ops.vhdl on 2018-06-28 23:37:29.004041 2 | .. vhdl:package:: extras.bit_ops 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: natural_vector 10 | 11 | Vector of natural numbers. 12 | 13 | Components 14 | ---------- 15 | 16 | 17 | count_ones 18 | ~~~~~~~~~~ 19 | 20 | .. symbolator:: 21 | :name: bit_ops-count_ones 22 | 23 | component count_ones is 24 | port ( 25 | --# {{data|}} 26 | Value : in unsigned; 27 | Ones_count : out unsigned 28 | ); 29 | end component; 30 | 31 | | 32 | 33 | 34 | .. vhdl:entity:: count_ones 35 | 36 | Count the number of set bits in a vector. 37 | 38 | :port Value: Vector to count set bits 39 | :ptype Value: in unsigned 40 | :port Ones_count: Number of set bits in ``Value`` 41 | :ptype Ones_count: out unsigned 42 | 43 | count_ones_chunked 44 | ~~~~~~~~~~~~~~~~~~ 45 | 46 | .. symbolator:: 47 | :name: bit_ops-count_ones_chunked 48 | 49 | component count_ones_chunked is 50 | generic ( 51 | TABLE_BITS : positive 52 | ); 53 | port ( 54 | --# {{data|}} 55 | Value : in unsigned; 56 | Ones_count : out unsigned 57 | ); 58 | end component; 59 | 60 | | 61 | 62 | 63 | .. vhdl:entity:: count_ones_chunked 64 | 65 | Count the number of set bits in a vector with a reduced constant table. 66 | 67 | :generic TABLE_BITS: Number of bits for constant table 68 | :gtype TABLE_BITS: positive 69 | 70 | :port Value: Vector to count set bits 71 | :ptype Value: in unsigned 72 | :port Ones_count: Number of set bits in ``Value`` 73 | :ptype Ones_count: out unsigned 74 | 75 | count_ones_sequential 76 | ~~~~~~~~~~~~~~~~~~~~~ 77 | 78 | .. symbolator:: 79 | :name: bit_ops-count_ones_sequential 80 | 81 | component count_ones_sequential is 82 | generic ( 83 | TABLE_BITS : positive; 84 | RESET_ACTIVE_LEVEL : std_ulogic 85 | ); 86 | port ( 87 | --# {{clocks|}} 88 | Clock : in std_ulogic; 89 | Reset : in std_ulogic; 90 | --# {{control|}} 91 | Start : in std_ulogic; 92 | Busy : out std_ulogic; 93 | Done : out std_ulogic; 94 | --# {{data|}} 95 | Value : in unsigned; 96 | Ones_count : out unsigned 97 | ); 98 | end component; 99 | 100 | | 101 | 102 | 103 | .. vhdl:entity:: count_ones_sequential 104 | 105 | Count the number of set bits in a vector with a reduced constant table. 106 | 107 | :generic TABLE_BITS: Number of bits for constant table 108 | :gtype TABLE_BITS: positive 109 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 110 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 111 | 112 | :port Clock: System clock 113 | :ptype Clock: in std_ulogic 114 | :port Reset: Asynchronous reset 115 | :ptype Reset: in std_ulogic 116 | :port Start: Start counting 117 | :ptype Start: in std_ulogic 118 | :port Busy: Count is in progress 119 | :ptype Busy: out std_ulogic 120 | :port Done: Count is done 121 | :ptype Done: out std_ulogic 122 | :port Value: Vector to count set bits 123 | :ptype Value: in unsigned 124 | :port Ones_count: Number of set bits in ``Value`` 125 | :ptype Ones_count: out unsigned 126 | 127 | Subprograms 128 | ----------- 129 | 130 | 131 | .. vhdl:function:: function gen_count_ones_table(Size : positive) return natural_vector; 132 | 133 | Create a precomputed table of bit counts. 134 | 135 | :param Size: Number of bits in vector 136 | :type Size: positive 137 | :returns: Array of bit count values with 2**Size entries. 138 | 139 | 140 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/characters_handling.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/characters_handling.vhdl on 2018-06-28 23:37:29.041308 2 | .. vhdl:package:: extras.characters_handling 3 | 4 | 5 | Subprograms 6 | ----------- 7 | 8 | 9 | .. vhdl:function:: function Is_Alphanumeric(Ch : character) return boolean; 10 | 11 | Alphanumeric character test. 12 | 13 | :param Ch: Character to test 14 | :type Ch: character 15 | :returns: true if alphanumeric character. 16 | 17 | 18 | 19 | .. vhdl:function:: function Is_Letter(Ch : character) return boolean; 20 | 21 | Letter character test. 22 | 23 | :param Ch: Character to test 24 | :type Ch: character 25 | :returns: true if letter character. 26 | 27 | 28 | 29 | .. vhdl:function:: function Is_Control(Ch : character) return boolean; 30 | 31 | Control character test. 32 | 33 | :param Ch: Character to test 34 | :type Ch: character 35 | :returns: true if control character. 36 | 37 | 38 | 39 | .. vhdl:function:: function Is_Digit(Ch : character) return boolean; 40 | 41 | Digit character test. 42 | 43 | :param Ch: Character to test 44 | :type Ch: character 45 | :returns: true if digit character. 46 | 47 | 48 | 49 | .. vhdl:function:: function Is_Hexadecimal_Digit(Ch : character) return boolean; 50 | 51 | Hexadecimal digit character test. 52 | 53 | :param Ch: Character to test 54 | :type Ch: character 55 | :returns: true if hexadecimal character. 56 | 57 | 58 | 59 | .. vhdl:function:: function Is_Basic(Ch : character) return boolean; 60 | 61 | Basic character test. 62 | 63 | :param Ch: Character to test 64 | :type Ch: character 65 | :returns: true if basic character. 66 | 67 | 68 | 69 | .. vhdl:function:: function Is_Graphic(Ch : character) return boolean; 70 | 71 | Graphic character test. 72 | 73 | :param Ch: Character to test 74 | :type Ch: character 75 | :returns: true if graphic character. 76 | 77 | 78 | 79 | .. vhdl:function:: function Is_Lower(Ch : character) return boolean; 80 | 81 | Lower-case character test. 82 | 83 | :param Ch: Character to test 84 | :type Ch: character 85 | :returns: true if lower-case character. 86 | 87 | 88 | 89 | .. vhdl:function:: function Is_Upper(Ch : character) return boolean; 90 | 91 | Upper-case character test. 92 | 93 | :param Ch: Character to test 94 | :type Ch: character 95 | :returns: true if upper-case character. 96 | 97 | 98 | 99 | .. vhdl:function:: function Is_Special(Ch : character) return boolean; 100 | 101 | Special character test. 102 | 103 | :param Ch: Character to test 104 | :type Ch: character 105 | :returns: true if special character. 106 | 107 | 108 | 109 | .. vhdl:function:: function To_Lower(Ch : character) return character; 110 | 111 | Convert a character to lower-case. 112 | 113 | :param Ch: Character to convert 114 | :type Ch: character 115 | :returns: Converted character. 116 | 117 | 118 | 119 | .. vhdl:function:: function To_Lower(Source : string) return string; 120 | 121 | Convert a string to lower-case. 122 | 123 | :param Source: String to convert 124 | :type Source: string 125 | :returns: Converted string. 126 | 127 | 128 | 129 | .. vhdl:function:: function To_Upper(Ch : character) return character; 130 | 131 | Convert a character to upper-case. 132 | 133 | :param Ch: Character to convert 134 | :type Ch: character 135 | :returns: Converted character. 136 | 137 | 138 | 139 | .. vhdl:function:: function To_Upper(Source : string) return string; 140 | 141 | Convert a string to upper-case. 142 | 143 | :param Source: String to convert 144 | :type Source: string 145 | :returns: Converted string. 146 | 147 | 148 | 149 | .. vhdl:function:: function To_Basic(Ch : character) return character; 150 | 151 | Convert a character to its basic (unaccented) form. 152 | 153 | :param Ch: Character to convert 154 | :type Ch: character 155 | :returns: Converted character. 156 | 157 | 158 | 159 | .. vhdl:function:: function To_Basic(Source : string) return string; 160 | 161 | Convert a string to its basic (unaccented) form. 162 | 163 | :param Source: String to convert 164 | :type Source: string 165 | :returns: Converted string. 166 | 167 | 168 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/common_2008.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras_2008/common_2008.vhdl on 2018-06-28 23:37:30.056215 2 | .. vhdl:package:: extras_2008.common 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: sulv_array 10 | 11 | Array of std_ulogic_vector. 12 | 13 | .. vhdl:type:: slv_array 14 | 15 | Array of std_logic_vector. 16 | 17 | .. vhdl:type:: unsigned_array 18 | 19 | Array of unsigned. 20 | 21 | .. vhdl:type:: signed_array 22 | 23 | Array of signed. 24 | 25 | Subprograms 26 | ----------- 27 | 28 | 29 | .. vhdl:function:: function to_slv_array(A : sulv_array) return slv_array; 30 | 31 | Convert std_ulogic_vector array to std_logic_vector array. 32 | 33 | :param A: Array to convert 34 | :type A: sulv_array 35 | :returns: Array with new type. 36 | 37 | 38 | 39 | .. vhdl:function:: function to_sulv_array(A : slv_array) return sulv_array; 40 | 41 | Convert std_logic_vector array to std_ulogic_vector array. 42 | 43 | :param A: Array to convert 44 | :type A: slv_array 45 | :returns: Array with new type. 46 | 47 | 48 | 49 | .. vhdl:function:: function to_unsigned_array(A : sulv_array) return unsigned_array; 50 | 51 | Convert std_ulogic_vector array to unsigned array. 52 | 53 | :param A: Array to convert 54 | :type A: sulv_array 55 | :returns: Array with new type. 56 | 57 | 58 | 59 | .. vhdl:function:: function to_sulv_array(A : unsigned_array) return sulv_array; 60 | 61 | Convert unsigned array to std_ulogic_vector array. 62 | 63 | :param A: Array to convert 64 | :type A: unsigned_array 65 | :returns: Array with new type. 66 | 67 | 68 | 69 | .. vhdl:function:: function to_signed_array(A : sulv_array) return signed_array; 70 | 71 | Convert std_ulogic_vector array to signed array. 72 | 73 | :param A: Array to convert 74 | :type A: sulv_array 75 | :returns: Array with new type. 76 | 77 | 78 | 79 | .. vhdl:function:: function to_sulv_array(A : signed_array) return sulv_array; 80 | 81 | Convert signed array to std_ulogic_vector array. 82 | 83 | :param A: Array to convert 84 | :type A: signed_array 85 | :returns: Array with new type. 86 | 87 | 88 | 89 | .. vhdl:function:: function to_unsigned_array(A : slv_array) return unsigned_array; 90 | 91 | Convert std_logic_vector array to unsigned array. 92 | 93 | :param A: Array to convert 94 | :type A: slv_array 95 | :returns: Array with new type. 96 | 97 | 98 | 99 | .. vhdl:function:: function to_slv_array(A : unsigned_array) return slv_array; 100 | 101 | Convert unsigned array to std_logic_vector array. 102 | 103 | :param A: Array to convert 104 | :type A: unsigned_array 105 | :returns: Array with new type. 106 | 107 | 108 | 109 | .. vhdl:function:: function to_signed_array(A : slv_array) return signed_array; 110 | 111 | Convert std_logic_vector array to signed array. 112 | 113 | :param A: Array to convert 114 | :type A: slv_array 115 | :returns: Array with new type. 116 | 117 | 118 | 119 | .. vhdl:function:: function to_slv_array(A : signed_array) return slv_array; 120 | 121 | Convert signed array to std_logic_vector array. 122 | 123 | :param A: Array to convert 124 | :type A: signed_array 125 | :returns: Array with new type. 126 | 127 | 128 | 129 | .. vhdl:function:: function to_signed_array(A : unsigned_array) return signed_array; 130 | 131 | Convert unsigned array to signed array. 132 | 133 | :param A: Array to convert 134 | :type A: unsigned_array 135 | :returns: Array with new type. 136 | 137 | 138 | 139 | .. vhdl:function:: function to_unsigned_array(A : signed_array) return unsigned_array; 140 | 141 | Convert signed array to unsigned array. 142 | 143 | :param A: Array to convert 144 | :type A: signed_array 145 | :returns: Array with new type. 146 | 147 | 148 | 149 | .. vhdl:function:: function to_sulv_array(A : std_ulogic_vector) return sulv_array; 150 | 151 | Convert a scaler std_ulogic_vector to a single element std_ulogic_vector array. 152 | 153 | :param A: Vector 154 | :type A: std_ulogic_vector 155 | :returns: Array with new type. 156 | 157 | 158 | 159 | .. vhdl:function:: function to_slv_array(A : std_logic_vector) return slv_array; 160 | 161 | Convert a scaler std_logic_vector to a single element std_logic_vector array. 162 | 163 | :param A: Vector 164 | :type A: std_logic_vector 165 | :returns: Array with new type. 166 | 167 | 168 | 169 | .. vhdl:function:: function to_unsigned_array(A : unsigned) return unsigned_array; 170 | 171 | Convert a scaler unsigned to a single element unsigned array. 172 | 173 | :param A: Vector 174 | :type A: unsigned 175 | :returns: Array with new type. 176 | 177 | 178 | 179 | .. vhdl:function:: function to_signed_array(A : signed) return signed_array; 180 | 181 | Convert a scaler signed to a single element signed array. 182 | 183 | :param A: Vector 184 | :type A: signed 185 | :returns: Array with new type. 186 | 187 | 188 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/crc_ops.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/crc_ops.vhdl on 2018-06-28 23:37:29.176993 2 | .. vhdl:package:: extras.crc_ops 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | crc 10 | ~~~ 11 | 12 | .. symbolator:: 13 | :name: crc_ops-crc 14 | 15 | component crc is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic 18 | ); 19 | port ( 20 | --# {{clocks|}} 21 | Clock : in std_ulogic; 22 | Reset : in std_ulogic; 23 | --# {{control|CRC configuration}} 24 | Poly : in std_ulogic_vector; 25 | Xor_in : in std_ulogic_vector; 26 | Xor_out : in std_ulogic_vector; 27 | Reflect_in : in boolean; 28 | Reflect_out : in boolean; 29 | Initialize : in std_ulogic; 30 | --# {{data|}} 31 | Enable : in std_ulogic; 32 | Data : in std_ulogic_vector; 33 | Checksum : out std_ulogic_vector 34 | ); 35 | end component; 36 | 37 | | 38 | 39 | 40 | .. vhdl:entity:: crc 41 | 42 | Calculate a CRC sequentially. 43 | 44 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 45 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 46 | 47 | :port Clock: System clock 48 | :ptype Clock: in std_ulogic 49 | :port Reset: Asynchronous reset 50 | :ptype Reset: in std_ulogic 51 | :port Poly: Polynomial 52 | :ptype Poly: in std_ulogic_vector 53 | :port Xor_in: Invert (XOR) initial state 54 | :ptype Xor_in: in std_ulogic_vector 55 | :port Xor_out: Invert (XOR) final state 56 | :ptype Xor_out: in std_ulogic_vector 57 | :port Reflect_in: Swap input bit order 58 | :ptype Reflect_in: in boolean 59 | :port Reflect_out: Swap output bit order 60 | :ptype Reflect_out: in boolean 61 | :port Initialize: Reset the CRC state 62 | :ptype Initialize: in std_ulogic 63 | :port Enable: Indicates data is valid for next CRC update 64 | :ptype Enable: in std_ulogic 65 | :port Data: New data (can be any width needed) 66 | :ptype Data: in std_ulogic_vector 67 | :port Checksum: Computed CRC 68 | :ptype Checksum: out std_ulogic_vector 69 | 70 | Subprograms 71 | ----------- 72 | 73 | 74 | .. vhdl:function:: function init_crc(Xor_in : bit_vector) return bit_vector; 75 | 76 | Initialize CRC state. 77 | 78 | :param Xor_in: Apply XOR to initial '0' state 79 | :type Xor_in: bit_vector 80 | :returns: New state of CRC. 81 | 82 | 83 | 84 | .. vhdl:function:: function next_crc(Crc : bit_vector; Poly : bit_vector; Reflect_in : boolean; Data : bit_vector) return bit_vector; 85 | 86 | Add new data to the CRC. 87 | 88 | :param Crc: Current CRC state 89 | :type Crc: bit_vector 90 | :param Poly: Polynomial for the CRC 91 | :type Poly: bit_vector 92 | :param Reflect_in: Reverse bits of Data when true 93 | :type Reflect_in: boolean 94 | :param Data: Next data word to add to CRC 95 | :type Data: bit_vector 96 | :returns: New state of CRC. 97 | 98 | 99 | 100 | .. vhdl:function:: function end_crc(Crc : bit_vector; Reflect_out : boolean; Xor_out : bit_vector) return bit_vector; 101 | 102 | Finalize the CRC. 103 | 104 | :param Crc: Current CRC state 105 | :type Crc: bit_vector 106 | :param Reflect_out: Reverse bits of result when true 107 | :type Reflect_out: boolean 108 | :param Xor_out: Apply XOR to final state (inversion) 109 | :type Xor_out: bit_vector 110 | :returns: Final CRC value 111 | 112 | 113 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/freq_gen.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/freq_gen.vhdl on 2017-08-02 00:26:37.695316 2 | .. vhdl:package:: extras.freq_gen_pkg 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | dynamic_oscillator_sequential 10 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: freq_gen_pkg-dynamic_oscillator_sequential 14 | 15 | component dynamic_oscillator_sequential is 16 | generic ( 17 | SYS_CLOCK_FREQ : real; 18 | MIN_TGT_FREQ : natural; 19 | TOLERANCE : real; 20 | SIZE : natural; 21 | ITERATIONS : positive; 22 | MAGNITUDE : real; 23 | CAPTURE_RESULT : boolean; 24 | RESET_ACTIVE_LEVEL : std_ulogic 25 | ); 26 | port ( 27 | Clock : in std_ulogic; 28 | Reset : in std_ulogic; 29 | Load_phase : in std_ulogic; 30 | New_phase : in unsigned; 31 | Dyn_freq : in unsigned; 32 | Sin : out signed(SIZE-1 downto 0); 33 | Cos : out signed(SIZE-1 downto 0); 34 | Angle : out signed(SIZE-1 downto 0); 35 | Synth_clock : out std_ulogic 36 | ); 37 | end component; 38 | 39 | | 40 | 41 | 42 | .. vhdl:entity:: dynamic_oscillator_sequential 43 | 44 | 45 | :generic SYS_CLOCK_FREQ: 46 | :gtype SYS_CLOCK_FREQ: real 47 | :generic MIN_TGT_FREQ: 48 | :gtype MIN_TGT_FREQ: natural 49 | :generic TOLERANCE: 50 | :gtype TOLERANCE: real 51 | :generic SIZE: 52 | :gtype SIZE: natural 53 | :generic ITERATIONS: 54 | :gtype ITERATIONS: positive 55 | :generic MAGNITUDE: 56 | :gtype MAGNITUDE: real 57 | :generic CAPTURE_RESULT: 58 | :gtype CAPTURE_RESULT: boolean 59 | :generic RESET_ACTIVE_LEVEL: 60 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 61 | 62 | :port Clock: None 63 | :ptype Clock: in std_ulogic 64 | :port Reset: None 65 | :ptype Reset: in std_ulogic 66 | :port Load_phase: Load a new phase angle 67 | :ptype Load_phase: in std_ulogic 68 | :port New_phase: Phase angle to load 69 | :ptype New_phase: in unsigned 70 | :port Dyn_freq: None 71 | :ptype Dyn_freq: in unsigned 72 | :port Sin: None 73 | :ptype Sin: out signed(SIZE-1 downto 0) 74 | :port Cos: None 75 | :ptype Cos: out signed(SIZE-1 downto 0) 76 | :port Angle: None 77 | :ptype Angle: out signed(SIZE-1 downto 0) 78 | :port Synth_clock: None 79 | :ptype Synth_clock: out std_ulogic 80 | 81 | freq_gen_pipelined 82 | ~~~~~~~~~~~~~~~~~~ 83 | 84 | .. symbolator:: 85 | :name: freq_gen_pkg-freq_gen_pipelined 86 | 87 | component freq_gen_pipelined is 88 | generic ( 89 | SYS_FREQ : real; 90 | DDFS_TOL : real; 91 | SIZE : natural; 92 | MIN_TGT_FREQ : natural; 93 | FREQ_SCALE : natural; 94 | MAGNITUDE : real; 95 | ITERATIONS : positive 96 | ); 97 | port ( 98 | Clock : in std_ulogic; 99 | Reset : in std_ulogic; 100 | Load_phase : in std_ulogic; 101 | New_phase : in unsigned; 102 | Dyn_freq : in unsigned; 103 | Sin : out signed(SIZE-1 downto 0); 104 | Cos : out signed(SIZE-1 downto 0); 105 | Angle : out signed(SIZE-1 downto 0) 106 | ); 107 | end component; 108 | 109 | | 110 | 111 | 112 | .. vhdl:entity:: freq_gen_pipelined 113 | 114 | 115 | :generic SYS_FREQ: 116 | :gtype SYS_FREQ: real 117 | :generic DDFS_TOL: 118 | :gtype DDFS_TOL: real 119 | :generic SIZE: 120 | :gtype SIZE: natural 121 | :generic MIN_TGT_FREQ: 122 | :gtype MIN_TGT_FREQ: natural 123 | :generic FREQ_SCALE: 124 | :gtype FREQ_SCALE: natural 125 | :generic MAGNITUDE: 126 | :gtype MAGNITUDE: real 127 | :generic ITERATIONS: 128 | :gtype ITERATIONS: positive 129 | 130 | :port Clock: None 131 | :ptype Clock: in std_ulogic 132 | :port Reset: None 133 | :ptype Reset: in std_ulogic 134 | :port Load_phase: Load a new phase angle 135 | :ptype Load_phase: in std_ulogic 136 | :port New_phase: Phase angle to load 137 | :ptype New_phase: in unsigned 138 | :port Dyn_freq: None 139 | :ptype Dyn_freq: in unsigned 140 | :port Sin: None 141 | :ptype Sin: out signed(SIZE-1 downto 0) 142 | :port Cos: None 143 | :ptype Cos: out signed(SIZE-1 downto 0) 144 | :port Angle: None 145 | :ptype Angle: out signed(SIZE-1 downto 0) 146 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/glitch_filtering.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/glitch_filtering.vhdl on 2018-06-28 23:37:28.660046 2 | .. vhdl:package:: extras.glitch_filtering 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | glitch_filter 10 | ~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: glitch_filtering-glitch_filter 14 | 15 | component glitch_filter is 16 | generic ( 17 | FILTER_CYCLES : positive; 18 | RESET_ACTIVE_LEVEL : std_ulogic 19 | ); 20 | port ( 21 | --# {{clocks|}} 22 | Clock : in std_ulogic; 23 | Reset : in std_ulogic; 24 | --# {{data|}} 25 | Noisy : in std_ulogic; 26 | Filtered : out std_ulogic 27 | ); 28 | end component; 29 | 30 | | 31 | 32 | 33 | .. vhdl:entity:: glitch_filter 34 | 35 | Basic glitch filter with a constant filter delay 36 | This version filters a single signal of std_ulogic 37 | 38 | :generic FILTER_CYCLES: Number of clock cycles to filter 39 | :gtype FILTER_CYCLES: positive 40 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 41 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 42 | 43 | :port Clock: System clock 44 | :ptype Clock: in std_ulogic 45 | :port Reset: Asynchronous reset 46 | :ptype Reset: in std_ulogic 47 | :port Noisy: Noisy input signal 48 | :ptype Noisy: in std_ulogic 49 | :port Filtered: Filtered output 50 | :ptype Filtered: out std_ulogic 51 | 52 | dynamic_glitch_filter 53 | ~~~~~~~~~~~~~~~~~~~~~ 54 | 55 | .. symbolator:: 56 | :name: glitch_filtering-dynamic_glitch_filter 57 | 58 | component dynamic_glitch_filter is 59 | generic ( 60 | RESET_ACTIVE_LEVEL : std_ulogic 61 | ); 62 | port ( 63 | --# {{clocks|}} 64 | Clock : in std_ulogic; 65 | Reset : in std_ulogic; 66 | --# {{control|}} 67 | Filter_cycles : in unsigned; 68 | --# {{data|}} 69 | Noisy : in std_ulogic; 70 | Filtered : out std_ulogic 71 | ); 72 | end component; 73 | 74 | | 75 | 76 | 77 | .. vhdl:entity:: dynamic_glitch_filter 78 | 79 | Glitch filter with a dynamically alterable filter delay 80 | This version filters a single signal of std_ulogic component dynamic_glitch_filter is 81 | 82 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 83 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 84 | 85 | :port Clock: System clock 86 | :ptype Clock: in std_ulogic 87 | :port Reset: Asynchronous reset 88 | :ptype Reset: in std_ulogic 89 | :port Filter_cycles: Number of clock cycles to filter 90 | :ptype Filter_cycles: in unsigned 91 | :port Noisy: Noisy input signal 92 | :ptype Noisy: in std_ulogic 93 | :port Filtered: Filtered output 94 | :ptype Filtered: out std_ulogic 95 | 96 | array_glitch_filter 97 | ~~~~~~~~~~~~~~~~~~~ 98 | 99 | .. symbolator:: 100 | :name: glitch_filtering-array_glitch_filter 101 | 102 | component array_glitch_filter is 103 | generic ( 104 | FILTER_CYCLES : positive; 105 | RESET_ACTIVE_LEVEL : std_ulogic 106 | ); 107 | port ( 108 | --# {{clocks|}} 109 | Clock : in std_ulogic; 110 | Reset : in std_ulogic; 111 | --# {{data|}} 112 | Noisy : in std_ulogic_vector; 113 | Filtered : out std_ulogic_vector 114 | ); 115 | end component; 116 | 117 | | 118 | 119 | 120 | .. vhdl:entity:: array_glitch_filter 121 | 122 | Basic glitch filter with a constant filter delay 123 | This version filters an array of std_ulogic 124 | 125 | :generic FILTER_CYCLES: Number of clock cycles to filter 126 | :gtype FILTER_CYCLES: positive 127 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 128 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 129 | 130 | :port Clock: System clock 131 | :ptype Clock: in std_ulogic 132 | :port Reset: Asynchronous reset 133 | :ptype Reset: in std_ulogic 134 | :port Noisy: Noisy input signals 135 | :ptype Noisy: in std_ulogic_vector 136 | :port Filtered: Filtered output 137 | :ptype Filtered: out std_ulogic_vector 138 | 139 | dynamic_array_glitch_filter 140 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 141 | 142 | .. symbolator:: 143 | :name: glitch_filtering-dynamic_array_glitch_filter 144 | 145 | component dynamic_array_glitch_filter is 146 | generic ( 147 | RESET_ACTIVE_LEVEL : std_ulogic 148 | ); 149 | port ( 150 | --# {{clocks|}} 151 | Clock : in std_ulogic; 152 | Reset : in std_ulogic; 153 | --# {{control|}} 154 | Filter_cycles : in unsigned; 155 | --# {{data|}} 156 | Noisy : in std_ulogic_vector; 157 | Filtered : out std_ulogic_vector 158 | ); 159 | end component; 160 | 161 | | 162 | 163 | 164 | .. vhdl:entity:: dynamic_array_glitch_filter 165 | 166 | Glitch filter with a dynamically alterable filter delay 167 | This version filters an array of std_ulogic 168 | 169 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 170 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 171 | 172 | :port Clock: System clock 173 | :ptype Clock: in std_ulogic 174 | :port Reset: Asynchronous reset 175 | :ptype Reset: in std_ulogic 176 | :port Filter_cycles: Number of clock cycles to filter 177 | :ptype Filter_cycles: in unsigned 178 | :port Noisy: Noisy input signals 179 | :ptype Noisy: in std_ulogic_vector 180 | :port Filtered: Filtered output 181 | :ptype Filtered: out std_ulogic_vector 182 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/gray_code.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/gray_code.vhdl on 2018-06-28 23:37:29.198622 2 | .. vhdl:package:: extras.gray_code 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | gray_counter 10 | ~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: gray_code-gray_counter 14 | 15 | component gray_counter is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic 18 | ); 19 | port ( 20 | --# {{clocks|}} 21 | Clock : in std_ulogic; 22 | Reset : in std_ulogic; 23 | --# {{control|}} 24 | Load : in std_ulogic; 25 | Enable : in std_ulogic; 26 | --# {{data|}} 27 | Binary_load : in unsigned; 28 | Binary : out unsigned; 29 | Gray : out unsigned 30 | ); 31 | end component; 32 | 33 | | 34 | 35 | 36 | .. vhdl:entity:: gray_counter 37 | 38 | An example Gray code counter implementation. This counter maintains an 39 | internal binary register and converts its output to Gray code stored in a 40 | separate register. 41 | 42 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 43 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 44 | 45 | :port Clock: System clock 46 | :ptype Clock: in std_ulogic 47 | :port Reset: Asynchronous reset 48 | :ptype Reset: in std_ulogic 49 | :port Load: Synchronous load, active high 50 | :ptype Load: in std_ulogic 51 | :port Enable: Synchronous enable, active high 52 | :ptype Enable: in std_ulogic 53 | :port Binary_load: Loadable binary value 54 | :ptype Binary_load: in unsigned 55 | :port Binary: Binary count 56 | :ptype Binary: out unsigned 57 | :port Gray: Gray code count 58 | :ptype Gray: out unsigned 59 | 60 | Subprograms 61 | ----------- 62 | 63 | 64 | .. vhdl:function:: function to_gray(Binary : std_ulogic_vector) return std_ulogic_vector; 65 | 66 | Convert binary to Gray code. 67 | 68 | :param Binary: Binary value 69 | :type Binary: std_ulogic_vector 70 | :returns: Gray-coded vector. 71 | 72 | 73 | 74 | .. vhdl:function:: function to_gray(Binary : std_logic_vector) return std_logic_vector; 75 | 76 | Convert binary to Gray code. 77 | 78 | :param Binary: Binary value 79 | :type Binary: std_logic_vector 80 | :returns: Gray-coded vector. 81 | 82 | 83 | 84 | .. vhdl:function:: function to_gray(Binary : unsigned) return unsigned; 85 | 86 | Convert binary to Gray code. 87 | 88 | :param Binary: Binary value 89 | :type Binary: unsigned 90 | :returns: Gray-coded vector. 91 | 92 | 93 | 94 | .. vhdl:function:: function to_binary(Gray : std_ulogic_vector) return std_ulogic_vector; 95 | 96 | Convert Gray code to binary. 97 | 98 | :param Binary: Gray-coded value 99 | :returns: Decoded binary value. 100 | 101 | 102 | 103 | .. vhdl:function:: function to_binary(Gray : std_logic_vector) return std_logic_vector; 104 | 105 | Convert Gray code to binary. 106 | 107 | :param Binary: Gray-coded value 108 | :returns: Decoded binary value. 109 | 110 | 111 | 112 | .. vhdl:function:: function to_binary(Gray : unsigned) return unsigned; 113 | 114 | Convert Gray code to binary. 115 | 116 | :param Binary: Gray-coded value 117 | :returns: Decoded binary value. 118 | 119 | 120 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/interrupt_ctl.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/interrupt_ctl.vhdl on 2018-06-28 23:37:29.166059 2 | .. vhdl:package:: extras.interrupt_ctl_pkg 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | interrupt_ctl 10 | ~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: interrupt_ctl_pkg-interrupt_ctl 14 | 15 | component interrupt_ctl is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic 18 | ); 19 | port ( 20 | --# {{clocks|}} 21 | Clock : in std_ulogic; 22 | Reset : in std_ulogic; 23 | --# {{control|}} 24 | Int_mask : in std_ulogic_vector; 25 | Int_request : in std_ulogic_vector; 26 | Pending : out std_ulogic_vector; 27 | Current : out std_ulogic_vector; 28 | Interrupt : out std_ulogic; 29 | Acknowledge : in std_ulogic; 30 | Clear_pending : in std_ulogic 31 | ); 32 | end component; 33 | 34 | | 35 | 36 | 37 | .. vhdl:entity:: interrupt_ctl 38 | 39 | Priority interrupt controller. 40 | 41 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 42 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 43 | 44 | :port Clock: System clock 45 | :ptype Clock: in std_ulogic 46 | :port Reset: Asynchronous reset 47 | :ptype Reset: in std_ulogic 48 | :port Int_mask: Set bits correspond to active interrupts 49 | :ptype Int_mask: in std_ulogic_vector 50 | :port Int_request: Controls used to activate new interrupts 51 | :ptype Int_request: in std_ulogic_vector 52 | :port Pending: Set bits indicate which interrupts are pending 53 | :ptype Pending: out std_ulogic_vector 54 | :port Current: Single set bit for the active interrupt 55 | :ptype Current: out std_ulogic_vector 56 | :port Interrupt: Flag indicating when an interrupt is pending 57 | :ptype Interrupt: out std_ulogic 58 | :port Acknowledge: Clear the active interupt 59 | :ptype Acknowledge: in std_ulogic 60 | :port Clear_pending: Clear all pending interrupts 61 | :ptype Clear_pending: in std_ulogic 62 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/lcar_ops.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/lcar_ops.vhdl on 2018-06-28 23:37:28.480199 2 | .. vhdl:package:: extras.lcar_ops 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | wolfram_lcar 10 | ~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: lcar_ops-wolfram_lcar 14 | 15 | component wolfram_lcar is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic 18 | ); 19 | port ( 20 | --# {{clocks|}} 21 | Clock : in std_ulogic; 22 | Reset : in std_ulogic; 23 | Enable : in std_ulogic; 24 | --# {{control|}} 25 | Rule_map : in std_ulogic_vector; 26 | --# {{data|}} 27 | Left_in : in std_ulogic; 28 | Right_in : in std_ulogic; 29 | State : out std_ulogic_vector 30 | ); 31 | end component; 32 | 33 | | 34 | 35 | 36 | .. vhdl:entity:: wolfram_lcar 37 | 38 | General purpose implementation of a rule 150/90 LCAR. 39 | 40 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 41 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 42 | 43 | :port Clock: System clock 44 | :ptype Clock: in std_ulogic 45 | :port Reset: Asynchronous reset 46 | :ptype Reset: in std_ulogic 47 | :port Enable: Synchronous enable 48 | :ptype Enable: in std_ulogic 49 | :port Rule_map: Rules for each cell '1' -> 150, '0' -> 90 50 | :ptype Rule_map: in std_ulogic_vector 51 | :port Left_in: Left side input to LCAR 52 | :ptype Left_in: in std_ulogic 53 | :port Right_in: Right side input to LCAR 54 | :ptype Right_in: in std_ulogic 55 | :port State: The state of each cell 56 | :ptype State: out std_ulogic_vector 57 | 58 | Subprograms 59 | ----------- 60 | 61 | 62 | .. vhdl:function:: function next_wolfram_lcar(State : std_ulogic_vector; Rule_map : std_ulogic_vector; Left_in : std_ulogic := '0'; Right_in : std_ulogic := '0') return std_ulogic_vector; 63 | 64 | Determine the next state of the LCAR defined by the Rule_map. 65 | 66 | 67 | :param State: Current state of the LCAR cells 68 | :type State: std_ulogic_vector 69 | :param Rule_map: Rules for each cell; '1' -> 150, '0' -> 90 70 | :type Rule_map: std_ulogic_vector 71 | :param Left_in: Left side input to LCAR 72 | :type Left_in: std_ulogic 73 | :param Right_in: Right side input to LCAR 74 | :type Right_in: std_ulogic 75 | :returns: Next iteration of the LCAR rules which becomes the new state 76 | 77 | 78 | 79 | .. vhdl:function:: function lcar_rule(Size : positive) return std_ulogic_vector; 80 | 81 | Lookup a predefined rule set from the table. 82 | 83 | :param Size: Number of LCAR cells 84 | :type Size: positive 85 | :returns: Rule map for a maximal length sequence. 86 | 87 | 88 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/memory.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/memory.vhdl on 2018-06-28 23:37:28.866907 2 | .. vhdl:package:: extras.memory 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: rom_format 10 | 11 | Data file format. Either binary or ASCII hex. 12 | 13 | Components 14 | ---------- 15 | 16 | 17 | dual_port_ram 18 | ~~~~~~~~~~~~~ 19 | 20 | .. symbolator:: 21 | :name: memory-dual_port_ram 22 | 23 | component dual_port_ram is 24 | generic ( 25 | MEM_SIZE : positive; 26 | SYNC_READ : boolean 27 | ); 28 | port ( 29 | --# {{data|Write port}} 30 | Wr_clock : in std_ulogic; 31 | We : in std_ulogic; 32 | Wr_addr : in natural; 33 | Wr_data : in std_ulogic_vector; 34 | --# {{Read port}} 35 | Rd_clock : in std_ulogic; 36 | Re : in std_ulogic; 37 | Rd_addr : in natural; 38 | Rd_data : out std_ulogic_vector 39 | ); 40 | end component; 41 | 42 | | 43 | 44 | 45 | .. vhdl:entity:: dual_port_ram 46 | 47 | A dual-ported RAM supporting writes and reads from separate clock domains. 48 | 49 | :generic MEM_SIZE: Number or words in memory 50 | :gtype MEM_SIZE: positive 51 | :generic SYNC_READ: Register outputs of read port memory 52 | :gtype SYNC_READ: boolean 53 | 54 | :port Wr_clock: Write port clock 55 | :ptype Wr_clock: in std_ulogic 56 | :port We: Write enable 57 | :ptype We: in std_ulogic 58 | :port Wr_addr: Write port address 59 | :ptype Wr_addr: in natural 60 | :port Wr_data: Write port data 61 | :ptype Wr_data: in std_ulogic_vector 62 | :port Rd_clock: Read port clock 63 | :ptype Rd_clock: in std_ulogic 64 | :port Re: Read enable 65 | :ptype Re: in std_ulogic 66 | :port Rd_addr: Read port address 67 | :ptype Rd_addr: in natural 68 | :port Rd_data: Read port data 69 | :ptype Rd_data: out std_ulogic_vector 70 | 71 | rom 72 | ~~~ 73 | 74 | .. symbolator:: 75 | :name: memory-rom 76 | 77 | component rom is 78 | generic ( 79 | ROM_FILE : string; 80 | FORMAT : rom_format; 81 | MEM_SIZE : positive; 82 | SYNC_READ : boolean 83 | ); 84 | port ( 85 | --# {{clocks|}} 86 | Clock : in std_ulogic; 87 | --# {{data|}} 88 | Re : in std_ulogic; 89 | Addr : in natural; 90 | Data : out std_ulogic_vector 91 | ); 92 | end component; 93 | 94 | | 95 | 96 | 97 | .. vhdl:entity:: rom 98 | 99 | A synthesizable ROM using a file to specify the contents. 100 | 101 | :generic ROM_FILE: Name of file with ROM data 102 | :gtype ROM_FILE: string 103 | :generic FORMAT: File encoding 104 | :gtype FORMAT: rom_format 105 | :generic MEM_SIZE: Number or words in memory 106 | :gtype MEM_SIZE: positive 107 | :generic SYNC_READ: Register outputs of read port memory 108 | :gtype SYNC_READ: boolean 109 | 110 | :port Clock: System clock 111 | :ptype Clock: in std_ulogic 112 | :port Re: Read enable 113 | :ptype Re: in std_ulogic 114 | :port Addr: Read address 115 | :ptype Addr: in natural 116 | :port Data: Data at current address 117 | :ptype Data: out std_ulogic_vector 118 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/muxing.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/muxing.vhdl on 2018-06-28 23:37:29.187662 2 | .. vhdl:package:: extras.muxing 3 | 4 | 5 | Subprograms 6 | ----------- 7 | 8 | 9 | .. vhdl:function:: function decode(Sel : unsigned) return std_ulogic_vector; 10 | 11 | Decoder with variable sized output (power of 2). 12 | 13 | :param Sel: Numeric value to decode (range 0 to 2**Sel'length-1) 14 | :type Sel: unsigned 15 | :returns: Decoded (one-hot) representation of Sel. 16 | 17 | 18 | 19 | .. vhdl:function:: function decode(Sel : unsigned; Size : positive) return std_ulogic_vector; 20 | 21 | Decoder with variable sized output (user specified). 22 | 23 | :param Sel: Numeric value to decode (range 0 to Size-1) 24 | :type Sel: unsigned 25 | :param Size: Number of bits in result (leftmost bits) 26 | :type Size: positive 27 | :returns: Decoded (one-hot) representation of Sel. 28 | 29 | 30 | 31 | .. vhdl:function:: function mux(Inputs : std_ulogic_vector; Sel : unsigned) return std_ulogic; 32 | 33 | Multiplexer with variable sized inputs. 34 | 35 | :param Inputs: Inputs to select from 36 | :type Inputs: std_ulogic_vector 37 | :param Sel: Input to select 38 | :type Sel: unsigned 39 | :returns: Selected input. 40 | 41 | 42 | 43 | .. vhdl:function:: function mux(Inputs : std_ulogic_vector; One_hot_sel : std_ulogic_vector) return std_ulogic; 44 | 45 | Multiplexer with variable sized inputs using external decoder. 46 | 47 | :param Inputs: Inputs to select from 48 | :type Inputs: std_ulogic_vector 49 | :param One_hot_sel: Input to select (generated by decode()) 50 | :type One_hot_sel: std_ulogic_vector 51 | :returns: Selected input. 52 | 53 | 54 | 55 | .. vhdl:function:: function demux(Input : std_ulogic; Sel : unsigned; Size : positive) return std_ulogic_vector; 56 | 57 | Demultiplexer with variable sized inputs. 58 | 59 | :param Input: Bit to demultiplex 60 | :type Input: std_ulogic 61 | :param Sel: Position of Bit in result 62 | :type Sel: unsigned 63 | :param Size: Length of the result 64 | :type Size: positive 65 | :returns: Vector with selected bit connected to the Input. 66 | 67 | 68 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/muxing_2008.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras_2008/muxing_2008.vhdl on 2018-06-28 23:37:30.069880 2 | .. vhdl:package:: extras_2008.muxing 3 | 4 | 5 | Subprograms 6 | ----------- 7 | 8 | 9 | .. vhdl:function:: function decode(Sel : unsigned) return std_ulogic_vector; 10 | 11 | Decoder with variable sized output (power of 2). 12 | 13 | :param Sel: Numeric value to decode (range 0 to 2**Sel'length-1) 14 | :type Sel: unsigned 15 | :returns: Decoded (one-hot) representation of Sel. 16 | 17 | 18 | 19 | .. vhdl:function:: function decode(Sel : unsigned; Size : positive) return std_ulogic_vector; 20 | 21 | Decoder with variable sized output (user specified). 22 | 23 | :param Sel: Numeric value to decode (range 0 to Size-1) 24 | :type Sel: unsigned 25 | :param Size: Number of bits in result (leftmost bits) 26 | :type Size: positive 27 | :returns: Decoded (one-hot) representation of Sel. 28 | 29 | 30 | 31 | .. vhdl:function:: function mux(Inputs : std_ulogic_vector; Sel : unsigned) return std_ulogic; 32 | 33 | Multiplexer with variable sized inputs. 34 | 35 | :param Inputs: Inputs to select from 36 | :type Inputs: std_ulogic_vector 37 | :param Sel: Input to select 38 | :type Sel: unsigned 39 | :returns: Selected input. 40 | 41 | 42 | 43 | .. vhdl:function:: function mux(Inputs : std_ulogic_vector; One_hot_sel : std_ulogic_vector) return std_ulogic; 44 | 45 | Multiplexer with variable sized inputs using external decoder. 46 | 47 | :param Inputs: Inputs to select from 48 | :type Inputs: std_ulogic_vector 49 | :param One_hot_sel: Input to select (generated by decode()) 50 | :type One_hot_sel: std_ulogic_vector 51 | :returns: Selected input. 52 | 53 | 54 | 55 | .. vhdl:function:: function demux(Input : std_ulogic; Sel : unsigned; Size : positive) return std_ulogic_vector; 56 | 57 | Demultiplexer with variable sized inputs. 58 | 59 | :param Input: Bit to demultiplex 60 | :type Input: std_ulogic 61 | :param Sel: Position of Bit in result 62 | :type Sel: unsigned 63 | :param Size: Length of the result 64 | :type Size: positive 65 | :returns: Vector with selected bit connected to the Input. 66 | 67 | 68 | 69 | .. vhdl:function:: function mux(Inputs : sulv_array; Sel : unsigned) return std_ulogic_vector; 70 | 71 | Multiplexer with variable sized, multi-bit inputs. 72 | 73 | :param Inputs: Inputs to select from 74 | :type Inputs: sulv_array 75 | :param Sel: Input to select 76 | :type Sel: unsigned 77 | :returns: Selected input. 78 | 79 | 80 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/parity_ops.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/parity_ops.vhdl on 2018-06-28 23:37:28.450478 2 | .. vhdl:package:: extras.parity_ops 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: parity_kind 10 | 11 | Identify the type of parity 12 | 13 | Subprograms 14 | ----------- 15 | 16 | 17 | .. vhdl:function:: function parity(Ptype : parity_kind; Val : std_ulogic_vector) return std_ulogic; 18 | 19 | Compute parity. 20 | 21 | :param Ptype: Type of parity; odd or even 22 | :type Ptype: parity_kind 23 | :param Val: Value to generate parity for 24 | :type Val: std_ulogic_vector 25 | :returns: Parity bit for Val. 26 | 27 | 28 | 29 | .. vhdl:function:: function check_parity(Ptype : parity_kind; Val : std_ulogic_vector; Parity_bit : std_ulogic) return boolean; 30 | 31 | Check parity for an error. 32 | 33 | :param Ptype: Type of parity; odd or even 34 | :type Ptype: parity_kind 35 | :param Val: Value to test parity for 36 | :type Val: std_ulogic_vector 37 | :param Parity_bit: Parity bit to check 38 | :type Parity_bit: std_ulogic 39 | :returns: true if Parity_bit is correct. 40 | 41 | 42 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/pipelining_2008.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras_2008/pipelining_2008.vhdl on 2018-06-28 23:37:30.074654 2 | .. vhdl:package:: extras_2008.pipelining 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | tapped_delay_line 10 | ~~~~~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: pipelining-tapped_delay_line 14 | 15 | component tapped_delay_line is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic; 18 | REGISTER_FIRST_STAGE : boolean 19 | ); 20 | port ( 21 | --# {{clocks|}} 22 | Clock : in std_ulogic; 23 | Reset : in std_ulogic; 24 | --# {{control|}} 25 | Enable : in std_ulogic; 26 | --# {{data|}} 27 | Data : in std_ulogic_vector; 28 | Taps : out sulv_array 29 | ); 30 | end component; 31 | 32 | | 33 | 34 | 35 | .. vhdl:entity:: tapped_delay_line 36 | 37 | Vector delay line with an output for each stage. 38 | 39 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 40 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 41 | :generic REGISTER_FIRST_STAGE: Register or pass through the first stage 42 | :gtype REGISTER_FIRST_STAGE: boolean 43 | 44 | :port Clock: System clock 45 | :ptype Clock: in std_ulogic 46 | :port Reset: Asynchronous reset 47 | :ptype Reset: in std_ulogic 48 | :port Enable: Enable delay line 49 | :ptype Enable: in std_ulogic 50 | :port Data: Input to the delay line 51 | :ptype Data: in std_ulogic_vector 52 | :port Taps: Taps from each stage 53 | :ptype Taps: out sulv_array 54 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/prng.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/prng.vhdl on 2018-06-28 23:37:28.675257 2 | .. vhdl:package:: extras.prng 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | weak_prng 10 | ~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: prng-weak_prng 14 | 15 | component weak_prng is 16 | generic ( 17 | STATE_BITS : positive; 18 | LCAR_RATIO : real; 19 | RESET_ACTIVE_LEVEL : std_ulogic 20 | ); 21 | port ( 22 | --# {{clocks|}} 23 | Clock : in std_ulogic; 24 | Reset : in std_ulogic; 25 | Enable : in std_ulogic; 26 | Load_seed : in std_ulogic; 27 | Seed : in std_ulogic_vector; 28 | Entropy_stream : in std_ulogic; 29 | Initialized : out std_ulogic; 30 | Result : out std_ulogic_vector 31 | ); 32 | end component; 33 | 34 | | 35 | 36 | 37 | .. vhdl:entity:: weak_prng 38 | 39 | 40 | :generic STATE_BITS: 41 | :gtype STATE_BITS: positive 42 | :generic LCAR_RATIO: 43 | :gtype LCAR_RATIO: real 44 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 45 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 46 | 47 | :port Clock: System clock 48 | :ptype Clock: in std_ulogic 49 | :port Reset: Asynchronous reset 50 | :ptype Reset: in std_ulogic 51 | :port Enable: None 52 | :ptype Enable: in std_ulogic 53 | :port Load_seed: None 54 | :ptype Load_seed: in std_ulogic 55 | :port Seed: None 56 | :ptype Seed: in std_ulogic_vector 57 | :port Entropy_stream: None 58 | :ptype Entropy_stream: in std_ulogic 59 | :port Initialized: None 60 | :ptype Initialized: out std_ulogic 61 | :port Result: None 62 | :ptype Result: out std_ulogic_vector 63 | 64 | xorshift128plus 65 | ~~~~~~~~~~~~~~~ 66 | 67 | .. symbolator:: 68 | :name: prng-xorshift128plus 69 | 70 | component xorshift128plus is 71 | generic ( 72 | RESET_ACTIVE_LEVEL : std_ulogic 73 | ); 74 | port ( 75 | --# {{clocks|}} 76 | Clock : in std_ulogic; 77 | Reset : in std_ulogic; 78 | Enable : in std_ulogic; 79 | Load_seed : in std_ulogic; 80 | Seed : in unsigned(127 downto 0); 81 | Result : out unsigned(63 downto 0) 82 | ); 83 | end component; 84 | 85 | | 86 | 87 | 88 | .. vhdl:entity:: xorshift128plus 89 | 90 | 91 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 92 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 93 | 94 | :port Clock: System clock 95 | :ptype Clock: in std_ulogic 96 | :port Reset: Asynchronous reset 97 | :ptype Reset: in std_ulogic 98 | :port Enable: None 99 | :ptype Enable: in std_ulogic 100 | :port Load_seed: None 101 | :ptype Load_seed: in std_ulogic 102 | :port Seed: None 103 | :ptype Seed: in unsigned(127 downto 0) 104 | :port Result: None 105 | :ptype Result: out unsigned(63 downto 0) 106 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/random.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/random.vhdl on 2018-06-28 23:37:28.740908 2 | .. vhdl:package:: extras.random 3 | 4 | 5 | Subprograms 6 | ----------- 7 | 8 | 9 | .. vhdl:procedure:: procedure seed(S : in positive); 10 | 11 | Seed the PRNG with a number. 12 | 13 | :param S: Seed value 14 | :type S: in positive 15 | 16 | 17 | .. vhdl:procedure:: procedure seed(S1 : in positive; S2 : in positive); 18 | 19 | Seed the PRNG with s1 and s2. This offers more 20 | random initialization than the one argument version 21 | of seed. 22 | 23 | :param S1: Seed value 1 24 | :type S1: in positive 25 | :param S2: Seed value 2 26 | :type S2: in positive 27 | 28 | 29 | .. vhdl:function:: function random return real; 30 | 31 | Generate a random real. 32 | :returns: Random value. 33 | 34 | 35 | 36 | .. vhdl:function:: function random return natural; 37 | 38 | Generate a random natural. 39 | :returns: Random value. 40 | 41 | 42 | 43 | .. vhdl:function:: function random return boolean; 44 | 45 | Generate a random boolean. 46 | :returns: Random value. 47 | 48 | 49 | 50 | .. vhdl:function:: function random return character; 51 | 52 | Generate a random character. 53 | :returns: Random value. 54 | 55 | 56 | 57 | .. vhdl:function:: function random(Size : positive) return bit_vector; 58 | 59 | Generate a random bit_vector of size bits. 60 | 61 | :param Size: Length of the random result 62 | :type Size: positive 63 | :returns: Random value. 64 | 65 | 66 | 67 | .. vhdl:function:: function randint(Min : integer; Max : integer) return integer; 68 | 69 | Generate a random integer between Min and Max inclusive. 70 | Note that the span Max - Min must be less than integer'high. 71 | 72 | :param Min: Minimum value 73 | :type Min: integer 74 | :param Max: Maximum value 75 | :type Max: integer 76 | :returns: Random value between Min and Max. 77 | 78 | 79 | 80 | .. vhdl:function:: function randtime(Min : time; Max : time) return time; 81 | 82 | Generate a random time between Min and Max inclusive. 83 | Note that the span Max - Min must be less than time'high. 84 | 85 | :param Min: Minimum value 86 | :type Min: time 87 | :param Max: Maximum value 88 | :type Max: time 89 | :returns: Random value between Min and Max. 90 | 91 | 92 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/random_20xx.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras_2008/random_20xx.vhdl on 2018-06-28 23:37:30.037475 2 | .. vhdl:package:: extras_2008.random 3 | 4 | 5 | Subprograms 6 | ----------- 7 | 8 | 9 | .. vhdl:procedure:: procedure seed(S : in positive); 10 | 11 | Seed the PRNG with a number. 12 | 13 | :param S: Seed value 14 | :type S: in positive 15 | 16 | 17 | .. vhdl:procedure:: procedure seed(S1 : in positive; S2 : in positive); 18 | 19 | Seed the PRNG with s1 and s2. This offers more 20 | random initialization than the one argument version 21 | of seed. 22 | 23 | :param S1: Seed value 1 24 | :type S1: in positive 25 | :param S2: Seed value 2 26 | :type S2: in positive 27 | 28 | 29 | .. vhdl:function:: function random return real; 30 | 31 | Generate a random real. 32 | :returns: Random value. 33 | 34 | 35 | 36 | .. vhdl:function:: function random return natural; 37 | 38 | Generate a random natural. 39 | :returns: Random value. 40 | 41 | 42 | 43 | .. vhdl:function:: function random return boolean; 44 | 45 | Generate a random boolean. 46 | :returns: Random value. 47 | 48 | 49 | 50 | .. vhdl:function:: function random return character; 51 | 52 | Generate a random character. 53 | :returns: Random value. 54 | 55 | 56 | 57 | .. vhdl:function:: function random(Size : positive) return bit_vector; 58 | 59 | Generate a random bit_vector of size bits. 60 | 61 | :param Size: Length of the random result 62 | :type Size: positive 63 | :returns: Random value. 64 | 65 | 66 | 67 | .. vhdl:function:: function randint(Min : integer; Max : integer) return integer; 68 | 69 | Generate a random integer between Min and Max inclusive. 70 | Note that the span Max - Min must be less than integer'high. 71 | 72 | :param Min: Minimum value 73 | :type Min: integer 74 | :param Max: Maximum value 75 | :type Max: integer 76 | :returns: Random value between Min and Max. 77 | 78 | 79 | 80 | .. vhdl:function:: function randtime(Min : time; Max : time) return time; 81 | 82 | Generate a random time between Min and Max inclusive. 83 | Note that the span Max - Min must be less than time'high. 84 | 85 | :param Min: Minimum value 86 | :type Min: time 87 | :param Max: Maximum value 88 | :type Max: time 89 | :returns: Random value between Min and Max. 90 | 91 | 92 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/reg_file.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/reg_file.vhdl on 2018-06-28 23:37:28.444060 2 | .. vhdl:package:: extras.reg_file_pkg 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: reg_array 10 | 11 | Array of register words. 12 | 13 | Subtypes 14 | -------- 15 | 16 | 17 | .. vhdl:subtype:: reg_word 18 | 19 | Register word vector. Modify this to use different word sizes. 20 | 21 | Components 22 | ---------- 23 | 24 | 25 | reg_file 26 | ~~~~~~~~ 27 | 28 | .. symbolator:: 29 | :name: reg_file_pkg-reg_file 30 | 31 | component reg_file is 32 | generic ( 33 | RESET_ACTIVE_LEVEL : std_ulogic; 34 | DIRECT_READ_BIT_MASK : reg_array; 35 | STROBE_BIT_MASK : reg_array; 36 | REGISTER_INPUTS : boolean 37 | ); 38 | port ( 39 | --# {{clocks|}} 40 | Clock : in std_ulogic; 41 | Reset : in std_ulogic; 42 | --# {{control|}} 43 | Clear : in std_ulogic; 44 | --# {{data|Addressed port}} 45 | Reg_sel : in unsigned; 46 | We : in std_ulogic; 47 | Wr_data : in reg_word; 48 | Rd_data : out reg_word; 49 | --# {{Registers}} 50 | Registers : out reg_array; 51 | Direct_read : in reg_array; 52 | Reg_written : out std_ulogic_vector 53 | ); 54 | end component; 55 | 56 | | 57 | 58 | 59 | .. vhdl:entity:: reg_file 60 | 61 | Flexible register file with support for strobed outputs. 62 | 63 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 64 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 65 | :generic DIRECT_READ_BIT_MASK: Masks indicating which register bits are directly read 66 | :gtype DIRECT_READ_BIT_MASK: reg_array 67 | :generic STROBE_BIT_MASK: Masks indicating which register bits clear themselves after a write of '1' 68 | :gtype STROBE_BIT_MASK: reg_array 69 | :generic REGISTER_INPUTS: Register the input ports when true 70 | :gtype REGISTER_INPUTS: boolean 71 | 72 | :port Clock: System clock 73 | :ptype Clock: in std_ulogic 74 | :port Reset: Asynchronous reset 75 | :ptype Reset: in std_ulogic 76 | :port Clear: Initialize all registers to '0' 77 | :ptype Clear: in std_ulogic 78 | :port Reg_sel: Register address for write and read 79 | :ptype Reg_sel: in unsigned 80 | :port We: Write to selected register 81 | :ptype We: in std_ulogic 82 | :port Wr_data: Write port 83 | :ptype Wr_data: in reg_word 84 | :port Rd_data: Read port 85 | :ptype Rd_data: out reg_word 86 | :port Registers: Register file contents 87 | :ptype Registers: out reg_array 88 | :port Direct_read: Read-only signals direct from external logic 89 | :ptype Direct_read: in reg_array 90 | :port Reg_written: Status flags indicating when each register is written 91 | :ptype Reg_written: out std_ulogic_vector 92 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/reg_file_2008.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras_2008/reg_file_2008.vhdl on 2018-06-28 23:37:30.084771 2 | .. vhdl:package:: extras_2008.reg_file_pkg 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | reg_file 10 | ~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: reg_file_pkg-reg_file 14 | 15 | component reg_file is 16 | generic ( 17 | RESET_ACTIVE_LEVEL : std_ulogic; 18 | DIRECT_READ_BIT_MASK : reg_array; 19 | STROBE_BIT_MASK : reg_array; 20 | REGISTER_INPUTS : boolean 21 | ); 22 | port ( 23 | --# {{clocks|}} 24 | Clock : in std_ulogic; 25 | Reset : in std_ulogic; 26 | --# {{control|}} 27 | Clear : in std_ulogic; 28 | --# {{data|Addressed port}} 29 | Reg_sel : in unsigned; 30 | We : in std_ulogic; 31 | Wr_data : in reg_word; 32 | Rd_data : out reg_word; 33 | --# {{Registers}} 34 | Registers : out reg_array; 35 | Direct_read : in reg_array; 36 | Reg_written : out std_ulogic_vector 37 | ); 38 | end component; 39 | 40 | | 41 | 42 | 43 | .. vhdl:entity:: reg_file 44 | 45 | Flexible register file with support for strobed outputs. This variant 46 | uses VHDL-2008 syntax to define the reg_array type as an unconstrained 47 | array-of-arrays. Any register width can be instantiated without needing 48 | to modify the library. 49 | 50 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 51 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 52 | :generic DIRECT_READ_BIT_MASK: Masks indicating which register bits are directly read 53 | :gtype DIRECT_READ_BIT_MASK: reg_array 54 | :generic STROBE_BIT_MASK: Masks indicating which register bits clear themselves after a write of '1' 55 | :gtype STROBE_BIT_MASK: reg_array 56 | :generic REGISTER_INPUTS: Register the input ports when true 57 | :gtype REGISTER_INPUTS: boolean 58 | 59 | :port Clock: System clock 60 | :ptype Clock: in std_ulogic 61 | :port Reset: Asynchronous reset 62 | :ptype Reset: in std_ulogic 63 | :port Clear: Initialize all registers to '0' 64 | :ptype Clear: in std_ulogic 65 | :port Reg_sel: Register address for write and read 66 | :ptype Reg_sel: in unsigned 67 | :port We: Write to selected register 68 | :ptype We: in std_ulogic 69 | :port Wr_data: Write port 70 | :ptype Wr_data: in reg_word 71 | :port Rd_data: Internal file contents 72 | :ptype Rd_data: out reg_word 73 | :port Registers: Register file contents 74 | :ptype Registers: out reg_array 75 | :port Direct_read: Read-only signals direct from external logic 76 | :ptype Direct_read: in reg_array 77 | :port Reg_written: Status flags indicating when each register is written 78 | :ptype Reg_written: out std_ulogic_vector 79 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/secded_codec.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/secded_codec.vhdl on 2018-06-28 23:37:28.760142 2 | .. vhdl:package:: extras.secded_codec_pkg 3 | 4 | 5 | Constants 6 | --------- 7 | 8 | 9 | .. vhdl:constant:: CODEC_ENCODE 10 | 11 | Select encoding mode 12 | 13 | .. vhdl:constant:: CODEC_DECODE 14 | 15 | Select decoding mode 16 | 17 | .. vhdl:constant:: INSERT_NONE 18 | 19 | No error injection 20 | 21 | .. vhdl:constant:: INSERT_SINGLE 22 | 23 | Single-bit error injection 24 | 25 | .. vhdl:constant:: INSERT_DOUBLE 26 | 27 | Double-bit error injection 28 | 29 | Components 30 | ---------- 31 | 32 | 33 | secded_codec 34 | ~~~~~~~~~~~~ 35 | 36 | .. symbolator:: 37 | :name: secded_codec_pkg-secded_codec 38 | 39 | component secded_codec is 40 | generic ( 41 | DATA_SIZE : positive; 42 | PIPELINE_STAGES : natural; 43 | RESET_ACTIVE_LEVEL : std_ulogic 44 | ); 45 | port ( 46 | --# {{clocks|}} 47 | Clock : in std_ulogic; 48 | Reset : in std_ulogic; 49 | --# {{control|}} 50 | Codec_mode : in std_ulogic; 51 | Insert_error : in std_ulogic_vector(1 downto 0); 52 | --# {{data|Encoding port}} 53 | Data : in std_ulogic_vector(DATA_SIZE-1 downto 0); 54 | Encoded_data : out ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right); 55 | --# {{Decoding port}} 56 | Ecc_data : in ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right); 57 | Decoded_data : out std_ulogic_vector(DATA_SIZE-1 downto 0); 58 | --# {{Error flags}} 59 | Single_bit_error : out std_ulogic; 60 | Double_bit_error : out std_ulogic 61 | ); 62 | end component; 63 | 64 | | 65 | 66 | 67 | .. vhdl:entity:: secded_codec 68 | 69 | 70 | :generic DATA_SIZE: Size of the ``Data`` input 71 | :gtype DATA_SIZE: positive 72 | :generic PIPELINE_STAGES: Number of pipeline stages appended to end 73 | :gtype PIPELINE_STAGES: natural 74 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 75 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 76 | 77 | :port Clock: System clock 78 | :ptype Clock: in std_ulogic 79 | :port Reset: Asynchronous reset 80 | :ptype Reset: in std_ulogic 81 | :port Codec_mode: OPerating mode: '0' = encode, '1' = decode 82 | :ptype Codec_mode: in std_ulogic 83 | :port Insert_error: Error injection 84 | :ptype Insert_error: in std_ulogic_vector(1 downto 0) 85 | :port Data: Data to encode 86 | :ptype Data: in std_ulogic_vector(DATA_SIZE-1 downto 0) 87 | :port Encoded_data: Data message with SECDED parity 88 | :ptype Encoded_data: out ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right) 89 | :port Ecc_data: Received data 90 | :ptype Ecc_data: in ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right) 91 | :port Decoded_data: Received data with errors corrected 92 | :ptype Decoded_data: out std_ulogic_vector(DATA_SIZE-1 downto 0) 93 | :port Single_bit_error: '1' when a single-bit error is detected (automatically corrected) 94 | :ptype Single_bit_error: out std_ulogic 95 | :port Double_bit_error: '1' when a double-bit error is detected 96 | :ptype Double_bit_error: out std_ulogic 97 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/secded_edac.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/secded_edac.vhdl on 2018-06-28 23:37:28.719963 2 | .. vhdl:package:: extras.secded_edac 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: secded_error_kind 10 | 11 | Type of SECDED errors. 12 | 13 | .. vhdl:type:: secded_errors 14 | 15 | Boolean bitfield for SECDED errors. 16 | 17 | Subprograms 18 | ----------- 19 | 20 | 21 | .. vhdl:function:: function secded_message_size(Data_size : positive) return positive; 22 | 23 | Determine the size of a message (data interleaved with parity) given 24 | the size of data to be protected. 25 | 26 | :param Data_size: Number of data bits 27 | :type Data_size: positive 28 | :returns: Message size. 29 | 30 | 31 | 32 | .. vhdl:function:: function secded_indices(Data_size : positive) return ecc_range; 33 | 34 | Return the left and right indices needed to declare an ecc_vector for the 35 | requested data size. 36 | 37 | :param Data_size: Number of data bits 38 | :type Data_size: positive 39 | :returns: Range with left and right. 40 | 41 | 42 | 43 | .. vhdl:function:: function secded_parity_size(Message_size : positive) return positive; 44 | 45 | Determine the number of parity bits for a given message size. 46 | 47 | :param Message_size: Number of bits in complete message 48 | :type Message_size: positive 49 | :returns: Parity size. 50 | 51 | 52 | 53 | .. vhdl:function:: function secded_data_size(Message_size : positive) return positive; 54 | 55 | Determine the number of data bits for a given message size. 56 | 57 | :param Message_size: Number of bits in complete message 58 | :type Message_size: positive 59 | :returns: Data size. 60 | 61 | 62 | 63 | .. vhdl:function:: function secded_encode(Data : std_ulogic_vector) return ecc_vector; 64 | 65 | Encode the supplied data into an ecc_vector using Hamming code for 66 | the parity and an additional overall parity for SECDED. This version 67 | uses self contained logic. 68 | 69 | :param Data: Raw data 70 | :type Data: std_ulogic_vector 71 | :returns: Encoded data with parity. 72 | 73 | 74 | 75 | .. vhdl:function:: function secded_encode(Data : std_ulogic_vector; Parity_bits : unsigned) return ecc_vector; 76 | 77 | Encode the supplied data into an ecc_vector using Hamming code for 78 | the parity and an additional overall parity for SECDED. This version 79 | depends on external logic to generate the Hamming parity bits. 80 | 81 | :param Data: Raw data 82 | :type Data: std_ulogic_vector 83 | :param Parity_bits: Number of parity bits 84 | :type Parity_bits: unsigned 85 | :returns: Encoded data with parity. 86 | 87 | 88 | 89 | .. vhdl:function:: function secded_decode(Encoded_data : ecc_vector) return std_ulogic_vector; 90 | 91 | Decode an ecc_vector into the plain data bits, potentially correcting 92 | a single-bit error if a bit has flipped. This version uses self 93 | contained logic. 94 | 95 | :param Encoded_data: Encoded (uninterleaved) message 96 | :type Encoded_data: ecc_vector 97 | :returns: Decoded data. 98 | 99 | 100 | 101 | .. vhdl:function:: function secded_has_errors(Encoded_data : ecc_vector) return secded_errors; 102 | 103 | Test for a single-bit and double-bit errors in an ecc_vector. Returns 104 | true for each error type. 105 | 106 | :param Encoded_data: Encoded (uninterleaved) message 107 | :type Encoded_data: ecc_vector 108 | :returns: true if message has a single or double-bit error. 109 | 110 | 111 | 112 | .. vhdl:function:: function secded_has_errors(Encoded_data : ecc_vector; Syndrome : unsigned) return secded_errors; 113 | 114 | Test for a single-bit and double-bit errors in an ecc_vector. Returns 115 | true for each error type. This version depends on external logic to 116 | generate a syndrome. 117 | 118 | :param Encoded_data: Encoded (uninterleaved) message 119 | :type Encoded_data: ecc_vector 120 | :param Syndrome: Syndrome generated by hamming_parity() 121 | :type Syndrome: unsigned 122 | :returns: true if message has a single or double-bit error. 123 | 124 | 125 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/sizing.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/sizing.vhdl on 2018-06-28 23:37:28.729892 2 | .. vhdl:package:: extras.sizing 3 | 4 | 5 | Subprograms 6 | ----------- 7 | 8 | 9 | .. vhdl:function:: function floor_log(n : positive; b : positive) return natural; 10 | 11 | Compute the integer result of the function floor(log(n)). 12 | 13 | 14 | :param n: Number to take logarithm of 15 | :type n: positive 16 | :param b: Base for the logarithm 17 | :type b: positive 18 | :returns: Approximate logarithm of n rounded down. 19 | 20 | 21 | .. rubric:: Example: 22 | 23 | .. code-block:: vhdl 24 | 25 | size := floor_log(20, 2); 26 | 27 | 28 | 29 | .. vhdl:function:: function ceil_log(n : positive; b : positive) return natural; 30 | 31 | Compute the integer result of the function ceil(log(n)) where b is the base. 32 | 33 | 34 | :param n: Number to take logarithm of 35 | :type n: positive 36 | :param b: Base for the logarithm 37 | :type b: positive 38 | :returns: Approximate logarithm of n rounded up. 39 | 40 | 41 | .. rubric:: Example: 42 | 43 | .. code-block:: vhdl 44 | 45 | size := ceil_log(20, 2); 46 | 47 | 48 | 49 | .. vhdl:function:: function floor_log2(n : positive) return natural; 50 | 51 | Compute the integer result of the function floor(log2(n)). 52 | 53 | 54 | :param n: Number to take logarithm of 55 | :type n: positive 56 | :returns: Approximate base-2 logarithm of n rounded down. 57 | 58 | 59 | 60 | .. vhdl:function:: function ceil_log2(n : positive) return natural; 61 | 62 | Compute the integer result of the function ceil(log2(n)). 63 | 64 | 65 | :param n: Number to take logarithm of 66 | :type n: positive 67 | :returns: Approximate base-2 logarithm of n rounded up. 68 | 69 | 70 | 71 | .. vhdl:function:: function bit_size(n : natural) return natural; 72 | 73 | Compute the total number of bits needed to represent a number in binary. 74 | 75 | 76 | :param n: Number to compute size from 77 | :type n: natural 78 | :returns: Number of bits. 79 | 80 | 81 | 82 | .. vhdl:function:: function encoding_size(n : positive) return natural; 83 | 84 | Compute the number of bits needed to encode n items. 85 | 86 | 87 | :param n: Number to compute size from 88 | :type n: positive 89 | :returns: Number of bits. 90 | 91 | 92 | 93 | .. vhdl:function:: function signed_size(n : integer) return natural; 94 | 95 | Compute the total number of bits to represent a 2's complement signed 96 | integer in binary. 97 | 98 | 99 | :param n: Number to compute size from 100 | :type n: integer 101 | :returns: Number of bits. 102 | 103 | 104 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/strings.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/strings.vhdl on 2018-06-28 23:37:29.201044 2 | .. vhdl:package:: extras.strings 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: alignment 10 | 11 | Horizontal alignment. 12 | 13 | .. vhdl:type:: truncation 14 | 15 | End to truncate when result is too long. 16 | 17 | .. vhdl:type:: membership 18 | 19 | Inside or outside of a character set. 20 | 21 | .. vhdl:type:: direction 22 | 23 | Scan direction. 24 | 25 | .. vhdl:type:: trim_end 26 | 27 | End to trim off. 28 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/strings_maps.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/strings_maps.vhdl on 2018-06-28 23:37:28.990407 2 | .. vhdl:package:: extras.strings_maps 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: character_set 10 | 11 | Array of boolean flag bits indexed by ``character``. 12 | 13 | .. vhdl:type:: character_range 14 | 15 | Inclusive range of characters within the Latin-1 set. 16 | 17 | .. vhdl:type:: character_ranges 18 | 19 | Collection of character ranges. 20 | 21 | .. vhdl:type:: character_mapping 22 | 23 | Mapping from one character to another. 24 | 25 | Subtypes 26 | -------- 27 | 28 | 29 | .. vhdl:subtype:: character_sequence 30 | 31 | Sequence of characters that compose a character set. 32 | 33 | Subprograms 34 | ----------- 35 | 36 | 37 | .. vhdl:function:: function to_set(ranges : character_ranges) return character_set; 38 | 39 | Convert ranges to a character set 40 | 41 | :param ranges: List of character ranges in the set 42 | :type ranges: character_ranges 43 | :returns: A character set with the requested ranges. 44 | 45 | 46 | 47 | .. vhdl:function:: function to_set(span : character_range) return character_set; 48 | 49 | Convert range to a character set 50 | 51 | :param span: Range to build into character set 52 | :type span: character_range 53 | :returns: A character set with the requested range. 54 | 55 | 56 | 57 | .. vhdl:function:: function to_ranges(set : character_set) return character_ranges; 58 | 59 | Convert a character set into a list of ranges 60 | 61 | :param set: Character set to extract ranges from 62 | :type set: character_set 63 | :returns: All contiguous ranges in the set. 64 | 65 | 66 | 67 | .. vhdl:function:: function "-"(left : character_set; right : character_set) return character_set; 68 | 69 | Difference between to character sets 70 | 71 | :param left: Set to subtract from 72 | :type left: character_set 73 | :param right: Set to subtract from left 74 | :type right: character_set 75 | :returns: All characters in left not in right. 76 | 77 | 78 | 79 | .. vhdl:function:: function is_in(element : character; set : character_set) return boolean; 80 | 81 | Test if a character is part of a character set 82 | 83 | :param element: Character to test for 84 | :type element: character 85 | :param set: Character set to test membership in 86 | :type set: character_set 87 | :returns: true if element is in the set. 88 | 89 | 90 | 91 | .. vhdl:function:: function is_subset(elements : character_set; set : character_set) return boolean; 92 | 93 | Test if a character set is a subset of a larget set 94 | 95 | :param elements: Character set to test for 96 | :type elements: character_set 97 | :param set: Character set to test membership in 98 | :type set: character_set 99 | :returns: true if elements are in the set. 100 | 101 | 102 | 103 | .. vhdl:function:: function to_set(sequence : character_sequence) return character_set; 104 | 105 | Convert a character sequence into a set. 106 | 107 | :param sequence: String of characters to build into a set 108 | :type sequence: character_sequence 109 | :returns: A character set with all unique characters from sequence. 110 | 111 | 112 | 113 | .. vhdl:function:: function to_set(singleton : character) return character_set; 114 | 115 | Convert a character into a set. 116 | 117 | :param singleton: Character to include in the set 118 | :type singleton: character 119 | :returns: A character set with one single character as its member. 120 | 121 | 122 | 123 | .. vhdl:function:: function to_sequence(set : character_set) return character_sequence; 124 | 125 | Convert a character set into a sequence string 126 | 127 | :param set: Character set to convert 128 | :type set: character_set 129 | :returns: A sequence string with each character from the set. 130 | 131 | 132 | 133 | .. vhdl:function:: function value(cmap : character_mapping; element : character) return character; 134 | 135 | Look up the mapping for a character. 136 | 137 | :param cmap: Map associating Latin-1 characters with a substitute 138 | :type cmap: character_mapping 139 | :param element: Character to lookup in the map 140 | :type element: character 141 | :returns: The mapped value of the element character. 142 | 143 | 144 | 145 | .. vhdl:function:: function to_mapping(from : character_sequence; to_seq : character_sequence) return character_mapping; 146 | 147 | Create a mapping from two sequences. 148 | 149 | :param from: Sequence string to use for map indices 150 | :type from: character_sequence 151 | :param to_seq: Sequence string to use from map values 152 | :type to_seq: character_sequence 153 | :returns: A new map to convert characters in the from sequence into the to_seq. 154 | 155 | 156 | 157 | .. vhdl:function:: function to_domain(cmap : character_mapping) return character_sequence; 158 | 159 | Return the from sequence for a mapping. 160 | 161 | :param cmap: Character map to extract domain from 162 | :type cmap: character_mapping 163 | :returns: The characters used to map from. 164 | 165 | 166 | 167 | .. vhdl:function:: function to_range(cmap : character_mapping) return character_sequence; 168 | 169 | Return the to_seq sequence for a mapping. 170 | 171 | :param cmap: Character map to extract range from 172 | :type cmap: character_mapping 173 | :returns: The characters used to map into. 174 | 175 | 176 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/strings_maps_constants.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/strings_maps_constants.vhdl on 2018-06-28 23:37:29.109320 2 | .. vhdl:package:: extras.strings_maps_constants 3 | 4 | 5 | Constants 6 | --------- 7 | 8 | 9 | .. vhdl:constant:: NULL_SET 10 | 11 | No characters. 12 | 13 | .. vhdl:constant:: IDENTITY 14 | 15 | Map all characters to themselves. 16 | 17 | .. vhdl:constant:: CONTROL_SET 18 | 19 | Control characters. 20 | 21 | .. vhdl:constant:: GRAPHIC_SET 22 | 23 | Graphical characters. 24 | 25 | .. vhdl:constant:: LETTER_SET 26 | 27 | Letters only. 28 | 29 | .. vhdl:constant:: LOWER_SET 30 | 31 | Lower-case letters. 32 | 33 | .. vhdl:constant:: UPPER_SET 34 | 35 | Upper-case letters. 36 | 37 | .. vhdl:constant:: BASIC_SET 38 | 39 | Plain and accented letters. 40 | 41 | .. vhdl:constant:: DECIMAL_DIGIT_SET 42 | 43 | Digits 0-9. 44 | 45 | .. vhdl:constant:: HEXADECIMAL_DIGIT_SET 46 | 47 | Hex digits 0-9 and A-F. 48 | 49 | .. vhdl:constant:: ALPHANUMERIC_SET 50 | 51 | Letters and numbers. 52 | 53 | .. vhdl:constant:: SPECIAL_SET 54 | 55 | Punctuation symbols. 56 | 57 | .. vhdl:constant:: ISO_646_SET 58 | 59 | ASCII subset of Latin-1. 60 | 61 | .. vhdl:constant:: LOWER_CASE_MAP 62 | 63 | Map letters to lower-case. 64 | 65 | .. vhdl:constant:: UPPER_CASE_MAP 66 | 67 | Map letters to upper-case. 68 | 69 | .. vhdl:constant:: BASIC_MAP 70 | 71 | Map accented characters to their basic form. 72 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/synchronizing.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/synchronizing.vhdl on 2018-06-28 23:37:28.909058 2 | .. vhdl:package:: extras.synchronizing 3 | 4 | 5 | Components 6 | ---------- 7 | 8 | 9 | bit_synchronizer 10 | ~~~~~~~~~~~~~~~~ 11 | 12 | .. symbolator:: 13 | :name: synchronizing-bit_synchronizer 14 | 15 | component bit_synchronizer is 16 | generic ( 17 | STAGES : natural; 18 | RESET_ACTIVE_LEVEL : std_ulogic 19 | ); 20 | port ( 21 | --# {{clocks|}} 22 | Clock : in std_ulogic; 23 | Reset : in std_ulogic; 24 | --# {{data|}} 25 | Bit_in : in std_ulogic; 26 | Sync : out std_ulogic 27 | ); 28 | end component; 29 | 30 | | 31 | 32 | 33 | .. vhdl:entity:: bit_synchronizer 34 | 35 | A basic synchronizer with a configurable number of stages. 36 | The ``Sync`` output is synchronized to the ``Clock`` domain. 37 | 38 | :generic STAGES: Number of flip-flops in the synchronizer 39 | :gtype STAGES: natural 40 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 41 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 42 | 43 | :port Clock: System clock 44 | :ptype Clock: in std_ulogic 45 | :port Reset: Asynchronous reset 46 | :ptype Reset: in std_ulogic 47 | :port Bit_in: Unsynchronized signal 48 | :ptype Bit_in: in std_ulogic 49 | :port Sync: Synchronized to Clock's domain 50 | :ptype Sync: out std_ulogic 51 | 52 | reset_synchronizer 53 | ~~~~~~~~~~~~~~~~~~ 54 | 55 | .. symbolator:: 56 | :name: synchronizing-reset_synchronizer 57 | 58 | component reset_synchronizer is 59 | generic ( 60 | STAGES : natural; 61 | RESET_ACTIVE_LEVEL : std_ulogic 62 | ); 63 | port ( 64 | --# {{clocks|}} 65 | Clock : in std_ulogic; 66 | Reset : in std_ulogic; 67 | --# {{data|}} 68 | Sync_reset : out std_ulogic 69 | ); 70 | end component; 71 | 72 | | 73 | 74 | 75 | .. vhdl:entity:: reset_synchronizer 76 | 77 | Synchronizer for generating a synchronized reset. 78 | The deactivating edge transition for the ``Sync_reset`` output 79 | is synchronized to the ``Clock`` domain. Its activating edge remains asynchronous. 80 | 81 | :generic STAGES: Number of flip-flops in the synchronizer 82 | :gtype STAGES: natural 83 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 84 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 85 | 86 | :port Clock: System clock 87 | :ptype Clock: in std_ulogic 88 | :port Reset: Asynchronous reset 89 | :ptype Reset: in std_ulogic 90 | :port Sync_reset: Synchronized reset 91 | :ptype Sync_reset: out std_ulogic 92 | 93 | handshake_synchronizer 94 | ~~~~~~~~~~~~~~~~~~~~~~ 95 | 96 | .. symbolator:: 97 | :name: synchronizing-handshake_synchronizer 98 | 99 | component handshake_synchronizer is 100 | generic ( 101 | STAGES : natural; 102 | RESET_ACTIVE_LEVEL : std_ulogic 103 | ); 104 | port ( 105 | --# {{clocks|}} 106 | Clock_tx : in std_ulogic; 107 | Reset_tx : in std_ulogic; 108 | Clock_rx : in std_ulogic; 109 | Reset_rx : in std_ulogic; 110 | --# {{data|Send port}} 111 | Tx_data : in std_ulogic_vector; 112 | Send_data : in std_ulogic; 113 | Sending : out std_ulogic; 114 | Data_sent : out std_ulogic; 115 | --# {{Receive port}} 116 | Rx_data : out std_ulogic_vector; 117 | New_data : out std_ulogic 118 | ); 119 | end component; 120 | 121 | | 122 | 123 | 124 | .. vhdl:entity:: handshake_synchronizer 125 | 126 | A handshaking synchronizer for sending an array between clock domains. 127 | This uses the four-phase handshake protocol. 128 | 129 | :generic STAGES: Number of flip-flops in the synchronizer 130 | :gtype STAGES: natural 131 | :generic RESET_ACTIVE_LEVEL: Asynch. reset control level 132 | :gtype RESET_ACTIVE_LEVEL: std_ulogic 133 | 134 | :port Clock_tx: Transmitting domain clock 135 | :ptype Clock_tx: in std_ulogic 136 | :port Reset_tx: Asynchronous reset for Clock_tx 137 | :ptype Reset_tx: in std_ulogic 138 | :port Clock_rx: Receiving domain clock 139 | :ptype Clock_rx: in std_ulogic 140 | :port Reset_rx: Asynchronous reset for Clock_rx 141 | :ptype Reset_rx: in std_ulogic 142 | :port Tx_data: Data to send 143 | :ptype Tx_data: in std_ulogic_vector 144 | :port Send_data: Control signal to send new data 145 | :ptype Send_data: in std_ulogic 146 | :port Sending: Active while TX is in process 147 | :ptype Sending: out std_ulogic 148 | :port Data_sent: Flag to indicate TX completion 149 | :ptype Data_sent: out std_ulogic 150 | :port Rx_data: Data received in clock_rx domain 151 | :ptype Rx_data: out std_ulogic_vector 152 | :port New_data: Flag to indicate new data 153 | :ptype New_data: out std_ulogic 154 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/text_buffering.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/text_buffering.vhdl on 2018-06-28 23:37:29.021524 2 | .. vhdl:package:: extras.text_buffering 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: buffer_line_acc 10 | 11 | Pointer to next node in list. 12 | 13 | .. vhdl:type:: buffer_line 14 | 15 | Linked list node of text lines. 16 | 17 | .. vhdl:type:: text_buffer 18 | 19 | Buffer of text lines. 20 | 21 | Subprograms 22 | ----------- 23 | 24 | 25 | .. vhdl:procedure:: procedure load_buffer(Fh : text; Buf : out text_buffer); 26 | 27 | Load a text file object into a buffer. 28 | 29 | :param Fh: File handle 30 | :type Fh: None text 31 | :param Buf: Buffer created from file contents 32 | :type Buf: out text_buffer 33 | 34 | 35 | .. vhdl:procedure:: procedure load_buffer(Fname : in string; Buf : out text_buffer); 36 | 37 | Load a file into a buffer. 38 | 39 | :param Fname: Name of text file to read 40 | :type Fname: in string 41 | :param Buf: Buffer created from file contents 42 | :type Buf: out text_buffer 43 | 44 | 45 | .. vhdl:procedure:: procedure append_file(Fh : text; Buf : inout text_buffer); 46 | 47 | Append a text file object to an existing buffer. 48 | 49 | :param Fh: File handle 50 | :type Fh: None text 51 | :param Buf: Buffer to append onto 52 | :type Buf: inout text_buffer 53 | 54 | 55 | .. vhdl:procedure:: procedure append_file(Fname : in string; Buf : inout text_buffer); 56 | 57 | Append a text file to an existing buffer. 58 | 59 | :param Fname: Name of text file to read 60 | :type Fname: in string 61 | :param Buf: Buffer to append onto 62 | :type Buf: inout text_buffer 63 | 64 | 65 | .. vhdl:procedure:: procedure append(One_line : in unbounded_string; Buf : inout text_buffer); 66 | 67 | Append an unbounded string to a buffer. 68 | 69 | :param One_line: String to append 70 | :type One_line: in unbounded_string 71 | :param Buf: Buffer to append onto 72 | :type Buf: inout text_buffer 73 | 74 | 75 | .. vhdl:procedure:: procedure append(One_line : in string; Buf : inout text_buffer); 76 | 77 | Append a string to a buffer 78 | 79 | :param One_line: String to append 80 | :type One_line: in string 81 | :param Buf: Buffer to append onto 82 | :type Buf: inout text_buffer 83 | 84 | 85 | .. vhdl:procedure:: procedure write(Fh : text; Buf : in text_buffer); 86 | 87 | Write a buffer to a text file object. 88 | 89 | :param Fh: File handle 90 | :type Fh: None text 91 | :param Buf: Buffer to write into the file 92 | :type Buf: in text_buffer 93 | 94 | 95 | .. vhdl:procedure:: procedure write(Fname : string; Buf : in text_buffer); 96 | 97 | Write a buffer to a text file. 98 | 99 | :param Fname: Name of text file to write 100 | :type Fname: None string 101 | :param Buf: Buffer to write into the file 102 | :type Buf: in text_buffer 103 | 104 | 105 | .. vhdl:procedure:: procedure nextline(Buf : inout text_buffer; Tl : inout unbounded_string); 106 | 107 | Retrieve the current line from a buffer. 108 | 109 | :param Buf: Buffer to get line from 110 | :type Buf: inout text_buffer 111 | :param Tl: Current line in the buffer 112 | :type Tl: inout unbounded_string 113 | 114 | 115 | .. vhdl:procedure:: procedure setline(Buf : inout text_buffer; N : in positive); 116 | 117 | Move to a specific line in the buffer. 118 | 119 | :param Buf: Buffer to seek into 120 | :type Buf: inout text_buffer 121 | :param N: Line number (zero based) 122 | :type N: in positive 123 | 124 | 125 | .. vhdl:procedure:: procedure endbuffer(Buf : in text_buffer; At_end : out boolean); 126 | 127 | Check if the end of the buffer has been reached. 128 | 129 | :param Buf: Buffer to test 130 | :type Buf: in text_buffer 131 | :param At_end: true when the buffer line pointer is at the end 132 | :type At_end: out boolean 133 | 134 | 135 | .. vhdl:procedure:: procedure free(Buf : inout text_buffer); 136 | 137 | Deallocate the buffer contents 138 | 139 | :param Buf: Buffer to free 140 | :type Buf: inout text_buffer 141 | 142 | -------------------------------------------------------------------------------- /doc/rst/modules/auto/timing_ops_xilinx.rst: -------------------------------------------------------------------------------- 1 | .. Generated from ../rtl/extras/timing_ops_xilinx.vhdl on 2018-06-28 23:37:28.823301 2 | .. vhdl:package:: extras.timing_ops 3 | 4 | 5 | Types 6 | ----- 7 | 8 | 9 | .. vhdl:type:: time_rounding 10 | 11 | 12 | Subtypes 13 | -------- 14 | 15 | 16 | .. vhdl:subtype:: clock_cycles 17 | 18 | 19 | .. vhdl:subtype:: duty_cycle 20 | 21 | 22 | Constants 23 | --------- 24 | 25 | 26 | .. vhdl:constant:: TIME_ROUND_STYLE 27 | 28 | 29 | Subprograms 30 | ----------- 31 | 32 | 33 | .. vhdl:function:: function resolution_limit return delay_length; 34 | 35 | Get the current simulation time resolution 36 | 37 | 38 | .. vhdl:function:: function to_real(Tval : time) return real; 39 | 40 | Convert time to real time 41 | 42 | 43 | .. vhdl:function:: function to_time(Rval : real) return time; 44 | 45 | Convert real time to time 46 | 47 | 48 | .. vhdl:function:: function to_period(Freq : real) return delay_length; 49 | 50 | Convert real frequency to period 51 | 52 | 53 | .. vhdl:function:: function to_clock_cycles(Secs : delay_length; Clock_freq : real; round_style : time_rounding := TIME_ROUND_STYLE) return clock_cycles; 54 | 55 | Compute clock cycles for the specified number of seconds using a clock 56 | frequency as the time base 57 | 58 | 59 | .. vhdl:function:: function to_clock_cycles(Secs : real; Clock_freq : real; round_style : time_rounding := TIME_ROUND_STYLE) return clock_cycles; 60 | 61 | 62 | 63 | .. vhdl:function:: function to_clock_cycles(Secs : delay_length; Clock_period : delay_length) return clock_cycles; 64 | 65 | Compute clock cycles for the specified number of seconds using a clock 66 | period as the time base 67 | 68 | 69 | .. vhdl:function:: function to_clock_cycles(Secs : real; Clock_period : delay_length; round_style : time_rounding := TIME_ROUND_STYLE) return clock_cycles; 70 | 71 | 72 | 73 | .. vhdl:function:: function time_duration(Cycles : clock_cycles; Clock_freq : real) return delay_length; 74 | 75 | Calculate the time span represented by a number of clock cycles 76 | 77 | 78 | .. vhdl:function:: function time_duration(Cycles : clock_cycles; Clock_period : delay_length) return delay_length; 79 | 80 | 81 | 82 | .. vhdl:function:: function time_duration(Cycles : clock_cycles; Clock_freq : real) return real; 83 | 84 | 85 | 86 | .. vhdl:procedure:: procedure report_time_precision(Identifier : in string; Cycles : in clock_cycles; Requested_secs : in real; Actual_secs : in real); 87 | 88 | Report statement for checking difference between requested time value 89 | and the output of to_clock_cycles 90 | 91 | 92 | .. vhdl:procedure:: procedure report_time_precision(Identifier : in string; Cycles : in clock_cycles; Requested_secs : in time; Actual_secs : in time); 93 | 94 | 95 | 96 | .. vhdl:procedure:: procedure clock_gen(Clock : out std_ulogic; Stop_clock : in boolean; Clock_period : in delay_length; Duty : duty_cycle := 0.5); 97 | 98 | Generate clock waveform for simulation only 99 | 100 | -------------------------------------------------------------------------------- /doc/rst/modules/bcd_conversion.rst: -------------------------------------------------------------------------------- 1 | ============== 2 | bcd_conversion 3 | ============== 4 | 5 | `extras/bcd_conversion.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | :doc:`sizing` 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides functions and components for performing conversion 16 | between binary and packed Binary Coded Decimal (BCD). The functions 17 | :vhdl:func:`~extras.bcd_conversion.to_bcd` and :vhdl:func:`~extras.bcd_conversion.to_binary` 18 | can be used to create synthesizable combinational 19 | logic for performing a conversion. In synthesized code they are best used 20 | with shorter arrays comprising only a few digits. For larger numbers, the 21 | components :vhdl:entity:`~extras.bcd_conversion.binary_to_bcd` and 22 | :vhdl:entity:`~extras.bcd_conversion.bcd_to_binary` can be used to perform a 23 | conversion over multiple clock cycles. The utility function :vhdl:func:`~extras.bcd_conversion.decimal_size` 24 | can be used to determine the number of decimal digits in a BCD array. Its 25 | result must be multiplied by 4 to get the length of a packed BCD array. 26 | 27 | Example usage 28 | ~~~~~~~~~~~~~ 29 | 30 | .. code-block:: vhdl 31 | 32 | signal binary : unsigned(7 downto 0); 33 | constant DSIZE : natural := decimal_size(2**binary'length - 1); 34 | signal bcd : unsigned(DSIZE*4-1 downto 0); 35 | ... 36 | bcd <= to_bcd(binary); 37 | 38 | 39 | .. include:: auto/bcd_conversion.rst 40 | 41 | -------------------------------------------------------------------------------- /doc/rst/modules/binaryio.rst: -------------------------------------------------------------------------------- 1 | ======== 2 | binaryio 3 | ======== 4 | 5 | `extras/binaryio.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | None 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides procedures to perform general purpose binary I/O on 17 | files. The number of bytes read or written is controlled by the width of 18 | array passed to the procedures. An endianness parameter determines the byte 19 | order. These procedures do not handle packed binary data. Reading and 20 | writing arrays that are not multiples of 8 in length will consume or 21 | produce additional padding bits in the file. Sign extension is performed 22 | when writing padded signed arrays. 23 | 24 | Example usage 25 | ~~~~~~~~~~~~~ 26 | 27 | .. code-block:: vhdl 28 | 29 | file fh : octet_file open read_mode is "foo.bin"; 30 | file fh2 : octet_file open write_mode is "out.bin"; 31 | signal uword : unsigned(15 downto 0); 32 | signal sword : signed(19 downto 0); 33 | ... 34 | read(fh, little_endian, uword); -- read 16 bits from two octets 35 | read(fh, big_endian, sword); -- read 20 bits from three octets 36 | ... 37 | write(fh2, little_endian, uword); 38 | write(fh2, big_endian, sword); 39 | 40 | 41 | .. include:: auto/binaryio.rst 42 | 43 | -------------------------------------------------------------------------------- /doc/rst/modules/bit_ops.rst: -------------------------------------------------------------------------------- 1 | ======= 2 | bit_ops 3 | ======= 4 | 5 | `extras/bit_ops.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`sizing ` 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides components that count the number of set bits in a 17 | vector. Multiple implementations are available with different performance 18 | characteristics. 19 | 20 | Example usage 21 | ~~~~~~~~~~~~~ 22 | 23 | .. code-block:: vhdl 24 | 25 | signal value : unsigned(11 downto 0); 26 | signal ones_count : unsigned(bit_size(value'length)-1 downto 0); 27 | 28 | -- Basic combinational circuit: 29 | basic: count_ones 30 | port map ( 31 | Value => value, 32 | Ones_count => ones_count 33 | ); 34 | 35 | -- Chunked combinational circuit: 36 | basic: count_ones_chunked 37 | generic map ( 38 | TABLE_BITS => 4 -- Constant table with 16 entries 39 | ) 40 | port map ( 41 | Value => value, 42 | Ones_count => ones_count 43 | ); 44 | 45 | -- Chunked sequential circuit: 46 | basic: count_ones_chunked 47 | generic map ( 48 | TABLE_BITS => 4 -- Constant table with 16 entries 49 | ) 50 | port map ( 51 | Clock => clock, 52 | Reset => reset, 53 | 54 | Start => start, 55 | Busy => busy, 56 | Done => done, 57 | 58 | Value => value, 59 | Ones_count => ones_count 60 | ); 61 | 62 | 63 | .. include:: auto/bit_ops.rst 64 | 65 | -------------------------------------------------------------------------------- /doc/rst/modules/characters_handling.rst: -------------------------------------------------------------------------------- 1 | =================== 2 | characters_handling 3 | =================== 4 | 5 | `extras/characters_handling.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`strings_maps_constants` 12 | 13 | Description 14 | ----------- 15 | 16 | This is a package of functions that replicate the behavior of the Ada 17 | standard library package ``Ada.Characters.Handling``. Included are functions 18 | to test for different character classifications and perform conversion 19 | of characters and strings to upper and lower case. 20 | 21 | 22 | .. include:: auto/characters_handling.rst 23 | 24 | -------------------------------------------------------------------------------- /doc/rst/modules/characters_latin_1.rst: -------------------------------------------------------------------------------- 1 | ================== 2 | characters_latin_1 3 | ================== 4 | 5 | `extras/characters_latin_1.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | None 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides Latin-1 character constants. These constants are 17 | adapted from the definitions in the Ada'95 ARM for the package 18 | ``Ada.Characters.Latin_1``. 19 | 20 | This package differs from the Ada implementation in that constants are not 21 | defined for the control characters to avoid ambiguity between the elements 22 | of the VHDL character enumeration. 23 | 24 | 25 | .. include:: auto/characters_latin_1.rst 26 | 27 | -------------------------------------------------------------------------------- /doc/rst/modules/common_2008.rst: -------------------------------------------------------------------------------- 1 | =========== 2 | common_2008 3 | =========== 4 | 5 | `extras/common_2008.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | None 12 | 13 | Description 14 | ----------- 15 | 16 | This is a set of common types defining unconstrained arrays of arrays in 17 | VHDL-2008 syntax. This provides a common set of types and conversion 18 | functions that can be used to interoperate between different library 19 | components that need to make use of fully unconstrained types. 20 | 21 | .. include:: auto/common_2008.rst 22 | 23 | 24 | -------------------------------------------------------------------------------- /doc/rst/modules/crc_ops.rst: -------------------------------------------------------------------------------- 1 | ======= 2 | crc_ops 3 | ======= 4 | 5 | `extras/crc_ops.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides a general purpose CRC implementation. It consists 16 | of a set of functions that can be used to iteratively process successive 17 | data vectors as well an an entity that combines the functions into a 18 | synthesizable form. The CRC can be readily specified using the Rocksoft 19 | notation described in `"A Painless Guide to CRC Error Detection Algorithms" `_, 20 | Williams 1993. A CRC specification consists of the following parameters: 21 | 22 | Poly 23 | The generator polynomial 24 | 25 | Xor_in 26 | The initialization vector "xored" with an all-'0's shift register 27 | 28 | Xor_out 29 | A vector xored with the shift register to produce the final value 30 | 31 | Reflect_in 32 | Process data bits from left to right (false) or right to left (true) 33 | 34 | Reflect_out 35 | Determine bit order of final crc result 36 | 37 | A CRC can be computed using a set of three functions :vhdl:func:`~extras.crc_ops.init_crc`, 38 | :vhdl:func:`~extras.crc_ops.next_crc`, and :vhdl:func:`~extras.crc_ops.end_crc`. 39 | All functions are assigned to a common variable/signal that maintans the shift 40 | register state between succesive calls. After initialization with ``init_crc``, data 41 | is processed by repeated calls to ``next_crc``. The width of the data vector is 42 | unconstrained allowing you to process bits in chunks of any desired size. Using 43 | a 1-bit array for data is equivalent to a bit-serial CRC implementation. When 44 | all data has been passed through the CRC it is completed with a call to ``end_crc`` to 45 | produce the final CRC value. 46 | 47 | 48 | Example usage 49 | ~~~~~~~~~~~~~ 50 | 51 | Implementing a CRC without depending on an external generator tool is easy and flexible by 52 | iteratively computing the CRC in a loop. This will synthesize into a combinational circuit: 53 | 54 | .. code-block:: vhdl 55 | 56 | -- CRC-16-USB 57 | constant poly : bit_vector := X"8005"; 58 | constant xor_in : bit_vector := X"FFFF"; 59 | constant xor_out : bit_vector := X"FFFF"; 60 | constant reflect_in : boolean := true; 61 | constant reflect_out : boolean := true; 62 | 63 | -- Implement CRC-16 with byte-wide inputs: 64 | subtype word is bit_vector(7 downto 0); 65 | type word_vec is array( natural range <> ) of word; 66 | variable data : word_vec(0 to 9); 67 | variable crc : bit_vector(poly'range); 68 | ... 69 | crc := init_crc(xor_in); 70 | for i in data'range loop 71 | crc := next_crc(crc, poly, reflect_in, data(i)); 72 | end loop; 73 | crc := end_crc(crc, reflect_out, xor_out); 74 | 75 | -- Implement CRC-16 with nibble-wide inputs: 76 | subtype nibble is bit_vector(3 downto 0); 77 | type nibble_vec is array( natural range <> ) of nibble; 78 | variable data : nibble_vec(0 to 9); 79 | variable crc : bit_vector(poly'range); 80 | ... 81 | crc := init_crc(xor_in); 82 | for i in data'range loop 83 | crc := next_crc(crc, poly, reflect_in, data(i)); 84 | end loop; 85 | crc := end_crc(crc, reflect_out, xor_out); 86 | 87 | 88 | 89 | A synthesizable component is provided to serve as a guide to using these 90 | functions in practical designs. The input data port has been left unconstrained 91 | to allow variable sized data to be fed into the CRC. Limiting its width to 92 | 1-bit will result in a bit-serial implementation. The synthesized logic will be 93 | minimized if all of the CRC configuration parameters are constants. 94 | 95 | .. code-block:: vhdl 96 | 97 | signal nibble : std_ulogic_vector(3 downto 0); -- Process 4-bits at a time 98 | signal checksum : std_ulogic_vector(15 downto 0); 99 | ... 100 | crc_16: crc 101 | port map ( 102 | Clock => clock, 103 | Reset => reset, 104 | 105 | -- CRC configuration parameters 106 | Poly => poly, 107 | Xor_in => xor_in, 108 | Xor_out => xor_out, 109 | Reflect_in => reflect_in, 110 | Reflect_out => reflect_out, 111 | 112 | Initialize => crc_init, -- Resets CRC register with init_crc function 113 | Enable => crc_en, -- Process next nibble 114 | 115 | Data => nibble, 116 | Checksum => checksum 117 | ); 118 | 119 | 120 | 121 | 122 | 123 | .. include:: auto/crc_ops.rst 124 | 125 | -------------------------------------------------------------------------------- /doc/rst/modules/ddfs.rst: -------------------------------------------------------------------------------- 1 | ==== 2 | ddfs 3 | ==== 4 | 5 | `extras/ddfs.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`sizing` 12 | :doc:`arithmetic` 13 | 14 | Description 15 | ----------- 16 | 17 | This package provides a set of functions and a component used for 18 | implementing a Direct Digital Frequency Synthesizer (DDFS). The DDFS 19 | component is a simple accumulator that increments by a pre computed value 20 | each cycle. The MSB of the accumulator switches at the requested frequency 21 | established by the :vhdl:func:`~extras.ddfs_pkg.ddfs_increment` function. The provided functions perform 22 | computations with real values and, as such, are only synthesizable when 23 | used to define constants. 24 | 25 | There are two sets of functions for generating the increment values needed 26 | by the DDFS accumulator. One set is used to compute static increments that 27 | are assigned to constants. The other functions work in conjunction with a 28 | procedure to dynamically generate the increment value using a single 29 | inferred multiplier. 30 | 31 | It is possible to generate multiple frequencies by computing more than one 32 | increment constant and multiplexing between them. The :vhdl:func:`~extras.ddfs_pkg.ddfs_size` function 33 | should be called with the smallest target frequency to be used to 34 | guarantee the requested tolerance is met. You can alternately set a fixed size and compute the 35 | effective tolerance with :vhdl:func:`~extras.ddfs_pkg.ddfs_tolerance`. 36 | 37 | 38 | For simulation reporting, you can compute the effective output frequency with the :vhdl:func:`~extras.ddfs_pkg.ddfs_frequency` function and the error ratio 39 | with :vhdl:func:`~extras.ddfs_pkg.ddfs_error`. 40 | 41 | The utility function :vhdl:func:`~extras.ddfs_pkg.resize_fractional` will truncate unwanted LSBs when downsizing the generated DDFS accumulator value. 42 | 43 | Example usage 44 | ~~~~~~~~~~~~~ 45 | 46 | The :vhdl:func:`~extras.ddfs_pkg.ddfs_size` and :vhdl:func:`~extras.ddfs_pkg.ddfs_increment` 47 | functions are used to compute static increment values: 48 | 49 | .. code-block:: vhdl 50 | 51 | constant SYS_FREQ : real := 50.0e6; -- 50 MHz 52 | constant TGT_FREQ : real := 2600.0; -- 2600 Hz 53 | constant DDFS_TOL : real := 0.001; -- 0.1% 54 | constant SIZE : natural := ddfs_size(SYS_FREQ, TGT_FREQ, DDFS_TOL); 55 | constant INCREMENT : unsigned(SIZE-1 downto 0) := 56 | ddfs_increment(SYS_FREQ, TGT_FREQ, SIZE); 57 | ... 58 | whistle: ddfs 59 | port map ( 60 | Clock => clock, 61 | Reset => reset, 62 | 63 | Enable => '1', 64 | Load_phase => '0', 65 | New_phase => unsigned'"", 66 | 67 | Increment => INCREMENT, 68 | Accumulator => accum, 69 | Synth_clock => synth_tone, -- Signal with ~2600 Hz clock 70 | Synth_pulse => open 71 | ); 72 | ... 73 | -- Report the DDFS precision (simulation only) 74 | report "True synthesized frequency: " 75 | & real'image(ddfs_frequency(SYS_FREQ, TGT_FREQ, SIZE) 76 | report "DDFS error: " & real'image(ddfs_error(SYS_FREQ, TGT_FREQ, SIZE) 77 | 78 | The alternate set of functions :vhdl:func:`~extras.ddfs_pkg.min_fraction_bits`, 79 | :vhdl:func:`~extras.ddfs_pkg.ddfs_dynamic_factor`, and :vhdl:func:`~extras.ddfs_pkg.ddfs_dynamic_inc` are used to precompute a multiplier factor 80 | that is used to dynamically generate an increment value in synthesizable logic: 81 | 82 | .. code-block:: vhdl 83 | 84 | constant MIN_TGT_FREQ : natural := 27; 85 | constant MAX_TGT_FREQ : natural := 4200; 86 | constant FRAC_BITS : natural := min_fraction_bits(SYS_FREQ, 87 | MIN_TGT_FREQ, SIZE, DDFS_TOL); 88 | constant DDFS_FACTOR : natural := ddfs_dynamic_factor(SYS_FREQ, SIZE, 89 | FRAC_BITS); 90 | signal dyn_freq : unsigned(bit_size(MAX_TGT_FREQ)-1 downto 0); 91 | signal dyn_inc : unsigned(SIZE-1 downto 0); 92 | ... 93 | dyn_freq <= to_unsigned(261, dyn_freq'length); -- Middle C 94 | ... 95 | dyn_freq <= to_unsigned(440, dyn_freq'length); -- Change to A4 96 | ... 97 | -- Wrap ddfs_dynamic_inc in a sequencial process to synthesize a 98 | -- multiplier with registered product. 99 | dyn: process(clock, reset) is 100 | begin 101 | if reset = '1' then 102 | dyn_inc <= (others => '0'); 103 | elsif rising_edge(clock) then 104 | ddfs_dynamic_inc(DDFS_FACTOR, FRAC_BITS, dyn_freq, dyn_inc); 105 | end if; 106 | end process; 107 | 108 | fsynth: ddfs 109 | port map ( 110 | Clock => clock, 111 | Reset => reset, 112 | 113 | Enable => '1', 114 | Load_phase => '0', 115 | New_phase => unsigned'"", 116 | 117 | Increment => dyn_inc, 118 | Accumulator => accum, 119 | Synth_clock => synth_tone, 120 | Synth_pulse => open 121 | ); 122 | 123 | 124 | .. include:: auto/ddfs.rst 125 | 126 | -------------------------------------------------------------------------------- /doc/rst/modules/filtering.rst: -------------------------------------------------------------------------------- 1 | ========= 2 | filtering 3 | ========= 4 | 5 | `extras_2008/filtering.vhdl `_ 6 | 7 | 8 | 9 | Dependencies 10 | ------------ 11 | 12 | :doc:`common_2008` 13 | :doc:`pipelining_2008 ` 14 | 15 | Description 16 | ----------- 17 | 18 | This package implements general purpose digital filters. 19 | 20 | Example usage 21 | ~~~~~~~~~~~~~ 22 | 23 | .. code-block:: vhdl 24 | 25 | TODO 26 | 27 | .. include:: auto/filtering.rst 28 | 29 | -------------------------------------------------------------------------------- /doc/rst/modules/glitch_filtering.rst: -------------------------------------------------------------------------------- 1 | ================ 2 | glitch_filtering 3 | ================ 4 | 5 | `extras/glitch_filtering.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`sizing` 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides glitch filter components that can be used to remove 17 | noise from digital input signals. This can be useful for debouncing 18 | switches directly connected to a device. 19 | The :vhdl:entity:`~extras.glitch_filtering.glitch_filter` component works 20 | with a single ``std_ulogic`` signal while 21 | :vhdl:entity:`~extras.glitch_filtering.array_glitch_filter` provides 22 | filtering for a ``std_ulogic_vector``. These components include synchronizing 23 | flip-flops and can be directly tied to input pads. 24 | 25 | It is assumed that the signal being recovered changes relatively slowly 26 | compared to the clock period. These filters come in two forms. One is 27 | controlled by a generic ``FILTER_CYCLES`` and the other dynamic versions (:vhdl:entity:`~extras.glitch_filtering.dynamic_glitch_filter` and 28 | :vhdl:entity:`~extras.glitch_filtering.dynamic_array_glitch_filter`) have 29 | a port signal ``Filter_cycles``. These controls indicate the number of clock cycles 30 | the input(s) must remain stable before the filtered output register(s) are 31 | updated. The filtered output will lag the inputs by ``Filter_cycles`` + 3 clock 32 | cycles. The dynamic versions can have their filter delay changed at any 33 | time if their ``Filter_cycles`` input is connected to a signal. The minimum 34 | pulse width that will pass through the filter will be ``Filter_cycles`` + 1 35 | clock cycles wide. 36 | 37 | Example usage 38 | ~~~~~~~~~~~~~ 39 | 40 | .. code-block:: vhdl 41 | 42 | library extras; 43 | use extras.glitch_filtering.all; use extras.timing_ops.all; 44 | ... 45 | constant CLOCK_FREQ : frequency := 100 MHz; 46 | constant FILTER_TIME : delay_length := 200 ns; 47 | constant FILTER_CYCLES : clock_cycles := 48 | to_clock_cycles(FILTER_TIME, CLOCK_FREQ); 49 | ... 50 | gf: glitch_filter 51 | generic map ( 52 | FILTER_CYCLES => FILTER_CYCLES 53 | ) port map ( 54 | Clock => clock, 55 | Reset => reset, 56 | Noisy => noisy, 57 | Filtered => filtered 58 | ); 59 | 60 | Xilinx XST doesn't support user defined physical types so the :vhdl:type:`~extras.timing_ops.frequency` 61 | type from timing_ops.vhdl can't be used with that synthesizer. An alternate 62 | solution using XST-compatible :doc:`timing_ops_xilinx.vhdl ` follows: 63 | 64 | .. code-block:: vhdl 65 | 66 | constant CLOCK_FREQ : real := 100.0e6; -- Using real in place of frequency 67 | constant FILTER_TIME : delay_length := 200 ns; 68 | constant FILTER_CYCLES : clock_cycles := 69 | to_clock_cycles(FILTER_TIME, CLOCK_FREQ) 70 | ... 71 | 72 | 73 | .. include:: auto/glitch_filtering.rst 74 | 75 | -------------------------------------------------------------------------------- /doc/rst/modules/gray_code.rst: -------------------------------------------------------------------------------- 1 | ========= 2 | gray_code 3 | ========= 4 | 5 | `extras/gray_code.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides functions to convert between Gray code and binary. 16 | An example implementation of a Gray code counter is also included. 17 | 18 | Example usage 19 | ~~~~~~~~~~~~~ 20 | 21 | .. code-block:: vhdl 22 | 23 | -- Conversion functions 24 | signal bin, gray, bin2 : std_ulogic_vector(7 downto 0); 25 | ... 26 | bin <= X"C5"; 27 | gray <= to_gray(bin); 28 | bin2 <= to_binary(gray); 29 | 30 | -- Gray code counter 31 | gc: gray_counter 32 | port map ( 33 | Clock => clock, 34 | Reset => reset, 35 | Load => '0', -- Not using load feature 36 | Enable => '1', -- Count continuously 37 | Binary_load => (binary_count'range => '0'), -- Unused load port 38 | Binary => binary_count, -- Internal binary count value 39 | Gray => gray_count -- Gray coded count 40 | ); 41 | 42 | 43 | 44 | 45 | .. include:: auto/gray_code.rst 46 | 47 | -------------------------------------------------------------------------------- /doc/rst/modules/interrupt_ctl.rst: -------------------------------------------------------------------------------- 1 | ============= 2 | interrupt_ctl 3 | ============= 4 | 5 | `extras/interrupt_ctl.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides a general purpose interrupt controller that handles 16 | the management of multiple interrupt sources. It uses unconstrained arrays 17 | to specify the interrupt vector signals. It can thus be sized as needed to 18 | suit required number of interrupts. 19 | 20 | The priority of the interrupts is fixed with the lowest index having the 21 | highest priority. You can use ascending or descending ranges for the 22 | control vectors. Multiple pending interrupts are serviced from highest to 23 | lowest priority. If a higher priority interrupt arrives when a lower 24 | priority interrupt is currently in service, the higher priority interrupt 25 | takes effect after the lower interrupt is acknowledged. If you disable a 26 | pending interrupt with its mask it will not return after reenabling the mask 27 | bit until the next interrupt arrives. 28 | 29 | Example usage 30 | ~~~~~~~~~~~~~ 31 | 32 | .. code-block:: vhdl 33 | 34 | -- Create an 8-bit interrupt controller 35 | signal int_mask, int_request, pending_int, current_int : 36 | std_ulogic_vector(7 downto 0); 37 | ... 38 | -- Disable interrupts 5, 6, and 7 39 | int_mask <= (7 downto 5 => '0', others => '1'); 40 | ic: interrupt_ctl 41 | port map ( 42 | Clock => clock, 43 | Reset => reset, 44 | 45 | Int_mask => int_mask, -- Mask to enable/disable interrupts 46 | Int_request => int_request, -- Interrupt sources 47 | Pending => pending_int, -- Current set of pending interrupts 48 | Current => current_int, -- Vector identifying which interrupt is active 49 | 50 | Interrupt => interrupt, -- Signal when an interrupt is ping 51 | Acknowledge => interrupt_ack, -- Acknowledge the interrupt has been serviced 52 | Clear_pending => clear_pending -- Optional control to clear all 53 | ); 54 | 55 | -- Assemble interrupt sources into a request vector 56 | int_request <= ( 57 | 0 => source1, -- Highest priority 58 | 1 => source2, 59 | 2 => source3, 60 | 3 => source4, -- Lowest priority 61 | others => '0'); -- The remaining sources are unused 62 | 63 | 64 | .. include:: auto/interrupt_ctl.rst 65 | 66 | -------------------------------------------------------------------------------- /doc/rst/modules/lcar_ops.rst: -------------------------------------------------------------------------------- 1 | ======== 2 | lcar_ops 3 | ======== 4 | 5 | `extras/lcar_ops.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides a component that implements the `Wolfram Linear 16 | Cellular Automata Register (LCAR) `_ 17 | as described in "Statistical Mechanics 18 | of Cellular Automata", Wolfram 1983. The LCAR implemented in :vhdl:entity:`~extras.lcar_ops.wolfram_lcar` 19 | uses rules 90 and 150 for each cell as defined by an input ``Rule_map`` where 20 | a '0' indicates rule 90 and '1' indicates rule 150 for the corresponding 21 | cell in the State register. 22 | 23 | The LCAR using rules 90 and 150 can produce output equivalent to maximal 24 | length LFSRs but with the advantage of less correlation between bits of 25 | the state register. This makes the LCAR more suitable for pseudo-random 26 | number generation. The predefined ``LCAR_*`` constants provide rule maps for 27 | maximal length sequences. 28 | 29 | For basic pseudo-random state generation it is sufficient to tie the 30 | ``Left_in`` and ``Right_in`` inputs to '0'. 31 | 32 | 33 | .. code-block:: vhdl 34 | 35 | library extras; 36 | use extras.lcar_ops.all; 37 | 38 | constant WIDTH : positive := 8; 39 | constant rule : std_ulogic_vector(WIDTH-1 downto 0) := lcar_rule(WIDTH); 40 | variable state : std_ulogic_vector(WIDTH-1 downto 0) := (others => '1'); 41 | ... 42 | -- Basic usage with default '0's shifting in from ends 43 | state := next_wolfram_lcar(state, rule); 44 | 45 | 46 | .. code-block:: vhdl 47 | 48 | library extras; 49 | use extras.lcar_ops.all; 50 | 51 | constant WIDTH : positive := 8; 52 | constant rule : std_ulogic_vector(WIDTH-1 downto 0) := lcar_rule(WIDTH); 53 | signal state : std_ulogic_vector(WIDTH-1 downto 0) := (others => '1'); 54 | ... 55 | 56 | wl: wolfram_lcar 57 | port map ( 58 | Clock => clock, 59 | Reset => reset, 60 | Enable => enable, 61 | 62 | Rule_map => rule 63 | Left_in => '0', 64 | Right_in => '0', 65 | 66 | State => state 67 | ); 68 | 69 | 70 | .. include:: auto/lcar_ops.rst 71 | 72 | -------------------------------------------------------------------------------- /doc/rst/modules/memory.rst: -------------------------------------------------------------------------------- 1 | ====== 2 | memory 3 | ====== 4 | 5 | `extras/memory.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | None 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides general purpose components for inferred RAM and ROM. 17 | These memories share a ``SYNC_READ`` generic which will optionally generate 18 | synchronous or asynchronous read ports for each instance. On Xilinx devices 19 | asynchronous read forces the synthesis of distributed RAM using LUTs rather 20 | than BRAMs. When ``SYNC_READ`` is false the Read enable input is unused and 21 | the read port clock can be tied to '0'. 22 | 23 | The ROM component gets its contents using synthesizable file IO to read a 24 | list of binary or hex values. 25 | 26 | 27 | Example usage 28 | ~~~~~~~~~~~~~ 29 | 30 | Create a 256-byte ROM with contents supplied by the binary image file "rom.img": 31 | 32 | .. code-block:: vhdl 33 | 34 | r: rom 35 | generic map ( 36 | ROM_FILE => "rom.img", 37 | FORMAT => BINARY_TEXT, 38 | MEM_SIZE => 256 39 | ) 40 | port map ( 41 | Clock => clock, 42 | Re => re, 43 | Addr => addr, 44 | Data => data 45 | ); 46 | 47 | 48 | .. include:: auto/memory.rst 49 | 50 | -------------------------------------------------------------------------------- /doc/rst/modules/muxing.rst: -------------------------------------------------------------------------------- 1 | ====== 2 | muxing 3 | ====== 4 | 5 | `extras/muxing.vhdl `_ 6 | 7 | `extras_2008/muxing_2008.vhdl `_ 8 | 9 | 10 | Dependencies 11 | ------------ 12 | 13 | :doc:`common_2008` (for muxing_2008) 14 | 15 | Description 16 | ----------- 17 | 18 | A set of routines for creating parameterized multiplexers, decoders, 19 | and demultiplexers. The VHDL-2008 version has an additional :vhdl:func:`~extras_2008.muxing.mux` 20 | function that can select from multi-bit inputs implemented in 21 | VHDL-2008 syntax. 22 | 23 | Example usage 24 | ~~~~~~~~~~~~~ 25 | 26 | .. code-block:: vhdl 27 | 28 | signal sel : unsigned(3 downto 0); 29 | signal d, data : std_ulogic_vector(0 to 2**sel'length-1); 30 | signal d2 : std_ulogic_vector(0 to 10); 31 | signal m : std_ulogic; 32 | ... 33 | d <= decode(sel); -- Full binary decode 34 | d2 <= decode(sel, d2'length); -- Partial decode 35 | 36 | m <= mux(data, sel); -- Mux with internal decoder 37 | m <= mux(data, d); -- Mux with external decoder 38 | 39 | d2 <= demux(m, sel, d2'length); 40 | 41 | Muxing vectors with VHDL-2008: 42 | 43 | .. code-block:: vhdl 44 | 45 | library extras_2008; 46 | use extras_2008.muxing.all; 47 | use extras_2008.common.sulv_array; 48 | 49 | signal sel : unsigned(3 downto 0); 50 | signal m : std_ulogic_vector(7 downto 0); 51 | signal data : sulv_array(0 to 2**sel'length-1)(m'range); 52 | ... 53 | m <= mux(data, sel); 54 | 55 | 56 | .. include:: auto/muxing.rst 57 | 58 | VHDL-2008 variant 59 | ----------------- 60 | 61 | .. include:: auto/muxing_2008.rst 62 | 63 | -------------------------------------------------------------------------------- /doc/rst/modules/oscillator.rst: -------------------------------------------------------------------------------- 1 | ========== 2 | oscillator 3 | ========== 4 | 5 | `extras/oscillator.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`ddfs`, 12 | :doc:`cordic`, 13 | :doc:`sizing`, 14 | :doc:`timing_ops` 15 | 16 | Description 17 | ----------- 18 | 19 | This package provides a set of components that implement arbitrary 20 | sinusoidal frequency generators. They come in two variants. One generates 21 | a fixed frequency that is specified at elaboration time as a generic 22 | parameter. The other generates a dynamic frequency that can be altered 23 | at run time. Each of these oscillator variants comes in two versions. One 24 | is based around a pipelined CORDIC unit that produces new valid output on 25 | every clock cycle. The other uses a more compact sequential CORDIC 26 | implementation that takes multiple clock cycles to produce each output. 27 | 28 | All oscillators output sine, cosine, the current phase angle, and a generated 29 | clock at the target frequency. 30 | 31 | Example usage 32 | ~~~~~~~~~~~~~ 33 | 34 | .. code-block:: vhdl 35 | 36 | TODO 37 | 38 | .. include:: auto/oscillator.rst 39 | 40 | -------------------------------------------------------------------------------- /doc/rst/modules/parity_ops.rst: -------------------------------------------------------------------------------- 1 | ========== 2 | parity_ops 3 | ========== 4 | 5 | `extras/parity_ops.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | Functions for calculating and checking parity. 16 | 17 | 18 | .. include:: auto/parity_ops.rst 19 | 20 | -------------------------------------------------------------------------------- /doc/rst/modules/pipelining.rst: -------------------------------------------------------------------------------- 1 | ========== 2 | pipelining 3 | ========== 4 | 5 | `extras/pipelining.vhdl `_ 6 | 7 | `extras_2008/pipelining_2008.vhdl `_ 8 | 9 | 10 | Dependencies 11 | ------------ 12 | 13 | :doc:`common_2008` (for pipelining_2008) 14 | 15 | Description 16 | ----------- 17 | 18 | This package provides configurable shift register components intended to 19 | be used as placeholders for register retiming during synthesis. These 20 | components can be placed after a section of combinational logic. With 21 | retiming activated in the synesis tool, the flip-flops will be distributed 22 | through the combinational logic to balance delays. The number of pipeline 23 | stages is controlled with the ``PIPELINE_STAGES`` generic. 24 | 25 | There are also components for general purpose delay lines with a fixed or variable number of stages. The VHDL-2008 package has a special :vhdl:entity:`~extras_2008.pipelining.tapped_delay_line` component that presents all stage outputs at once. 26 | 27 | Retiming 28 | ~~~~~~~~ 29 | Here are notes on how to activate retiming in various synthesis tools: 30 | 31 | Xilinx ISE 32 | register_balancing attributes are implemented in the design. 33 | In Project|Design Goals & Strategies set the Design Goal to 34 | "Timing Performance". The generic ``ATTR_REG_BALANCING`` is 35 | avaiable on each entity to control the direction of register 36 | balancing. Valid values are "yes", "no", "forward", and 37 | "backward". If the pipeline stages connect directly to I/O 38 | then set the strategy to "Performance without IOB packing". 39 | 40 | Xilinx Vivado 41 | phys_opt_design -retime 42 | 43 | Synplify Pro 44 | syn_allow_retiming attributes are implemented in the design 45 | 46 | Altera Quartus II 47 | Enable "Perform register retiming" in Assignments|Settings|Physical Synthesis Optimizations 48 | 49 | Synopsys Design Compiler 50 | Use the optimize_registers command 51 | 52 | Synopsys DC Ultra 53 | Same as DC or use set_optimize_registers in conjunction with compile_ultra -retime 54 | 55 | 56 | .. include:: auto/pipelining.rst 57 | 58 | VHDL-2008 variant 59 | ----------------- 60 | 61 | .. include:: auto/pipelining_2008.rst 62 | 63 | -------------------------------------------------------------------------------- /doc/rst/modules/random.rst: -------------------------------------------------------------------------------- 1 | ====== 2 | random 3 | ====== 4 | 5 | `extras/random.vhdl `_ 6 | 7 | `extras_2008/random_20xx.vhdl `_ 8 | 9 | 10 | Dependencies 11 | ------------ 12 | 13 | :doc:`timing_ops ` 14 | 15 | Description 16 | ----------- 17 | 18 | This package provides a general set of pseudo-random number functions. 19 | It is implemented as a wrapper around the ``ieee.math_real.uniform`` 20 | procedure and is only suitable for simulation not synthesis. See the 21 | :doc:`LCAR ` and :doc:`LFSR ` packages for synthesizable random generators. 22 | 23 | This package makes use of shared variables to keep track of the PRNG 24 | state more conveniently than calling uniform directly. Because 25 | VHDL-2002 broke forward compatability of shared variables there are 26 | two versions of this package. One (random.vhdl) is for VHDL-93 using 27 | the classic shared variable mechanism. The other (random_20xx.vhdl) 28 | is for VHDL-2002 and later using a protected type to manage the 29 | PRNG state. Both files define a package named "random" and only one 30 | can be in use at any time. The user visible subprograms are the same 31 | in both implementations. 32 | 33 | The package provides a number of overloaded subprograms for generating 34 | random numbers of various types. 35 | 36 | Example usage 37 | ~~~~~~~~~~~~~ 38 | 39 | .. code-block:: vhdl 40 | 41 | seed(12345); -- Initialize PRNG with a seed value 42 | seed(123, 456); -- Alternate seed procedure 43 | 44 | variable : r : real := random; -- Generate a random real 45 | variable : n : natural := random; -- Generate a random natural 46 | variable : b : boolean := random; -- Generate a random boolean 47 | -- Generate a random bit_vector of any size 48 | variable : bv : bit_vector(99 downto 0) := random(100); 49 | 50 | -- Generate a random integer within a specified range 51 | -- Number between 2 and 10 inclusive 52 | variable : i : natural := randint(2, 10); 53 | 54 | 55 | .. include:: auto/random.rst 56 | 57 | -------------------------------------------------------------------------------- /doc/rst/modules/secded_codec.rst: -------------------------------------------------------------------------------- 1 | ============ 2 | secded_codec 3 | ============ 4 | 5 | `extras/secded_codec.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | :doc:`sizing`, 11 | :doc:`pipelining`, 12 | :doc:`hamming_edac`, 13 | :doc:`secded_edac`, 14 | :doc:`parity_ops` 15 | 16 | Description 17 | ----------- 18 | 19 | This package provides a component that implements SECDED EDAC as a 20 | single unified codec. The codec can switch between encoding and decoding 21 | on each clock cycle with a minimum latency of two clock cycles through the 22 | input and output registers. The SECDED logic is capable of correcting 23 | single-bit errors and detecting double-bit errors. 24 | 25 | Optional pipelining is available to reduce the maximum delay through the 26 | internal logic. To be effective, you must activate the retiming feature of 27 | the synthesis tool being used. See the notes in :doc:`pipelining` for more 28 | information on how to accomplish this. The pipelining is controlled with 29 | the ``PIPELINE_STAGES`` generic. A value of 0 will disable pipelining. 30 | 31 | To facilitate testing, the codec includes an error generator that can 32 | insert single-bit and double-bit errors into the encoded output. When 33 | active, successive bits are flipped on each clock cycle. This feature 34 | provides for the testing of error handling logic in the decoding process. 35 | 36 | 37 | .. include:: auto/secded_codec.rst 38 | 39 | -------------------------------------------------------------------------------- /doc/rst/modules/secded_edac.rst: -------------------------------------------------------------------------------- 1 | =========== 2 | secded_edac 3 | =========== 4 | 5 | `extras/secded_edac.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | * :doc:`sizing`, 11 | * :doc:`hamming_edac`, 12 | * :doc:`parity_ops` 13 | 14 | Description 15 | ----------- 16 | 17 | This package implements Single Error Correction, Double Error Detection 18 | (SECDED) by extending the Hamming code with an extra overall parity bit. 19 | It is built on top of the functions implemented in :doc:`hamming_edac`. 20 | The :vhdl:type:`~extras.hamming_edac.ecc_vector` is extended with an additional 21 | parity bit to the right of the Hamming parity as shown below. 22 | 23 | SECDED ``ecc_vector`` layout: 24 | 25 | .. parsed-literal:: 26 | 27 | MSb LSb 28 | [(data'length - 1) <-> 0] [-1 <-> -(parity_size - 1)] [-parity_size] 29 | data Hamming parity SECDED parity bit 30 | 31 | Example usage 32 | ~~~~~~~~~~~~~ 33 | 34 | .. code-block:: vhdl 35 | 36 | signal word, corrected_word : std_ulogic_vector(15 downto 0); 37 | constant WORD_MSG_SIZE : positive := secded_message_size(word'length); 38 | signal secded_word : 39 | ecc_vector(word'high downto -secded_parity_size(WORD_MSG_SIZE)); 40 | ... 41 | secded_word <= secded_encode(word); 42 | ... 43 | corrected_word <= secded_decode(hamming_word); 44 | errors := secded_has_errors(secded_word); 45 | if errors(single_bit) or errors(double_bit) then ... -- check for error 46 | 47 | As with ``hamming_edac``, it is possible to share logic between the decoder 48 | and error checker and also between an encoder and decoder that don't 49 | operate simultaneously. Refer to :doc:`hamming_edac` and :doc:`secded_codec` 50 | for examples of this approach. 51 | 52 | 53 | .. include:: auto/secded_edac.rst 54 | 55 | -------------------------------------------------------------------------------- /doc/rst/modules/sizing.rst: -------------------------------------------------------------------------------- 1 | ====== 2 | sizing 3 | ====== 4 | 5 | `extras/sizing.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides functions used to compute integer approximations 16 | of logarithms. The primary use of these functions is to determine the 17 | size of arrays using the :vhdl:func:`~extras.sizing.bit_size[natural return natural]` and :vhdl:func:`~extras.sizing.encoding_size[positive return natural]` functions. When put to 18 | maximal use it is possible to create designs that eliminate hardcoded 19 | ranges and automatically resize their signals and variables by changing a 20 | few key constants or generics. 21 | 22 | These functions can be used in most synthesizers to compute ranges for 23 | arrays. The core functionality is provided in the :vhdl:func:`~extras.sizing.ceil_log[positive,positive return natural]` and 24 | :vhdl:func:`~extras.sizing.floor_log[positive,positive return natural]` subprograms. These compute the logarithm in any integer base. 25 | For convenenience, base-2 functions are also provided along with the array 26 | sizing functions. See the :doc:`bcd_conversion` implementation 27 | of :vhdl:func:`~extras.bcd_conversion.decimal_size` for a practical 28 | example of computing integer logs in base-10 using this package. 29 | 30 | Example usage 31 | ~~~~~~~~~~~~~ 32 | 33 | .. code-block:: vhdl 34 | 35 | constant MAX_COUNT : natural := 1000; 36 | constant COUNT_SIZE : natural := bit_size(MAX_COUNT); 37 | signal counter : unsigned(COUNT_SIZE-1 downto 0); 38 | ... 39 | counter <= to_unsigned(MAX_COUNT, COUNT_SIZE); 40 | -- counter will resize itself as MAX_COUNT is changed 41 | 42 | .. include:: auto/sizing.rst 43 | 44 | -------------------------------------------------------------------------------- /doc/rst/modules/strings.rst: -------------------------------------------------------------------------------- 1 | ======= 2 | strings 3 | ======= 4 | 5 | `extras/strings.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | None 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides common data types for the strings_fixed and 17 | strings_unbounded libraries. It is based on the equivalent Ada'95 package 18 | ``Ada.Strings``. 19 | 20 | 21 | .. include:: auto/strings.rst 22 | 23 | -------------------------------------------------------------------------------- /doc/rst/modules/strings_bounded.rst: -------------------------------------------------------------------------------- 1 | =============== 2 | strings_bounded 3 | =============== 4 | 5 | `extras_2008/strings_bounded.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`strings`, 12 | :doc:`strings_maps`, 13 | :doc:`strings_maps_constants`, 14 | :doc:`strings_fixed` 15 | 16 | 17 | Description 18 | ----------- 19 | 20 | This package provides a string library for operating on bounded length 21 | strings. This is a clone of the Ada'95 library ``Ada.Strings.Bounded``. It 22 | is a nearly complete implementation with only the procedures taking 23 | character mapping functions omitted because of VHDL limitations. 24 | This package requires support for VHDL-2008 package generics. The 25 | maximum size of a bounded string is established by instantiating a new 26 | package with the ``MAX`` generic set to the desired size. 27 | 28 | Unlike :doc:`fixed length strings ` which must always be 29 | padded to their full length, bounded strings can have any length up to the 30 | maximum set when the package is instantiated. 31 | 32 | Example usage 33 | ~~~~~~~~~~~~~ 34 | 35 | .. code-block:: vhdl 36 | 37 | -- Instantiate the package with a maximum length 38 | library extras_2008; 39 | package s20 is new extras_2008.strings_bounded 40 | generic map(MAX => 20); 41 | use work.s20.all; 42 | ... 43 | variable str : bounded_string; -- String with up to 20 characters 44 | variable l : natural; 45 | ... 46 | str := to_bounded_string("abc"); 47 | l := length(str); -- returns 3 48 | append(str, "def"); 49 | l := length(str); -- returns 6 50 | 51 | 52 | 53 | .. include:: auto/strings_bounded.rst 54 | 55 | -------------------------------------------------------------------------------- /doc/rst/modules/strings_fixed.rst: -------------------------------------------------------------------------------- 1 | ============= 2 | strings_fixed 3 | ============= 4 | 5 | `extras/strings_fixed.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`strings`, 12 | :doc:`strings_maps`, 13 | :doc:`strings_maps_constants` 14 | 15 | Description 16 | ----------- 17 | 18 | This package provides a string library for operating on fixed length 19 | strings. This is a clone of the Ada'95 library ``Ada.Strings.Fixed``. It is a 20 | nearly complete implementation with only the procedures taking character 21 | mapping functions omitted because of VHDL limitations. 22 | 23 | These are functions for operating on the native VHDL string type. Any operation 24 | that results in a shorter string must be padded with additional characters to fill 25 | out the entire string. 26 | 27 | 28 | .. include:: auto/strings_fixed.rst 29 | 30 | -------------------------------------------------------------------------------- /doc/rst/modules/strings_maps.rst: -------------------------------------------------------------------------------- 1 | ============ 2 | strings_maps 3 | ============ 4 | 5 | `extras/strings_maps.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | None 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides types and functions for manipulating character sets. 17 | It is a clone of the Ada'95 package ``Ada.Strings.Maps``. 18 | 19 | .. include:: auto/strings_maps.rst 20 | 21 | -------------------------------------------------------------------------------- /doc/rst/modules/strings_maps_constants.rst: -------------------------------------------------------------------------------- 1 | ====================== 2 | strings_maps_constants 3 | ====================== 4 | 5 | `extras/strings_maps_constants.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`strings_maps`, 12 | :doc:`characters_latin_1` 13 | 14 | Description 15 | ----------- 16 | 17 | This package provides constants for various character sets from the range 18 | of Latin-1 and mappings for upper case, lower case, and basic (unaccented) 19 | characters. It is a clone of the Ada'95 package 20 | ``Ada.Strings.Maps.Constants``. 21 | 22 | .. include:: auto/strings_maps_constants.rst 23 | 24 | -------------------------------------------------------------------------------- /doc/rst/modules/strings_unbounded.rst: -------------------------------------------------------------------------------- 1 | ================= 2 | strings_unbounded 3 | ================= 4 | 5 | `extras/strings_unbounded.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`strings`, 12 | :doc:`strings_maps`, 13 | :doc:`strings_fixed` 14 | 15 | Description 16 | ----------- 17 | 18 | This package provides a string library for operating on unbounded length 19 | strings. This is a clone of the Ada'95 library ``Ada.Strings.Unbounded``. Due 20 | to the VHDL restriction on using access types as function parameters only 21 | a limited subset of the Ada library is reproduced. The unbounded strings 22 | are represented by the subtype :vhdl:type:`~extras.strings_unbounded.unbounded_string` 23 | which is derived from line to ease interoperability with ``std.textio.line`` 24 | and :vhdl:type:`~extras.strings_unbounded.unbounded_string` are of 25 | type access to string. Their contents are dynamically allocated. Because 26 | operators cannot be provided, a new set of "copy" procedures are included 27 | to simplify duplication of an existing unbounded string. 28 | 29 | 30 | .. include:: auto/strings_unbounded.rst 31 | 32 | -------------------------------------------------------------------------------- /doc/rst/modules/synchronizing.rst: -------------------------------------------------------------------------------- 1 | ============= 2 | synchronizing 3 | ============= 4 | 5 | `extras/synchronizing.vhdl `_ 6 | 7 | Dependencies 8 | ------------ 9 | 10 | None 11 | 12 | Description 13 | ----------- 14 | 15 | This package provides a number of synchronizer components for managing 16 | data transmission between clock domains. There are three entities provided: 17 | 18 | * :vhdl:entity:`~extras.synchronizing.bit_synchronizer` -- Suitable for synchronizing individual bit-wide signals 19 | * :vhdl:entity:`~extras.synchronizing.reset_synchronizer` -- A special synchronizer for generating asyncronous resets that are synchronously released 20 | * :vhdl:entity:`~extras.synchronizing.handshake_synchronizer` -- A synchronizer using the four-phase protocol to transfer vectors between domains 21 | 22 | ``bit_synchronizer`` and ``reset_synchronizer`` have a configurable number of stages with a default of 2. 23 | 24 | 25 | If you need to synchronize a vector of bits together you should use the :vhdl:entity:`~extras.synchronizing.handshake_synchronizer` component. If you generate an array of 26 | :vhdl:entity:`~extras.synchronizing.bit_synchronizer` components instead, there is a risk that some bits will take longer than others and invalid values will appear at the outputs. This is particularly problematic if the vector represents a numeric value. :vhdl:entity:`~extras.synchronizing.bit_synchronizer` can be used safely in an array only if you know the input signal comes from an isochronous domain (same period, different phase). 27 | 28 | Synthesis 29 | ~~~~~~~~~ 30 | 31 | Vendor specific synthesis attributes have been included to help prevent undesirable 32 | results. It is important to know that, ideally, synchronizing flip-flops should be placed 33 | as close together as possible. It is also desirable to have the first stage flip-flop 34 | incorporated into the input buffer to minimize input delay. Because of this these components 35 | do not have attributes to guide relative placement of flip-flops to make them contiguous. 36 | Instead you should apply timing constraints to the components that will force the synthesizer into 37 | using an optimal placement. 38 | 39 | 40 | .. include:: auto/synchronizing.rst 41 | 42 | -------------------------------------------------------------------------------- /doc/rst/modules/text_buffering.rst: -------------------------------------------------------------------------------- 1 | ============== 2 | text_buffering 3 | ============== 4 | 5 | `extras/text_buffering.vhdl `_ 6 | 7 | 8 | Dependencies 9 | ------------ 10 | 11 | :doc:`strings_unbounded` 12 | 13 | Description 14 | ----------- 15 | 16 | This package provides a facility for storing buffered text. It can be used 17 | to represent the contents of a text file as a linked list of dynamically 18 | allocated strings for each line. A text file can be read into a buffer and 19 | the resulting data structure can be incorporated into records passable 20 | to procedures without having to maintain a separate file handle. 21 | 22 | Example usage 23 | ~~~~~~~~~~~~~ 24 | 25 | .. code-block:: vhdl 26 | 27 | variable buf : text_buffer; 28 | variable at_end : boolean; 29 | variable tl : unbounded_string; 30 | 31 | -- Add lines of text to a buffer 32 | append("First line", buf); 33 | append("Second line", buf); 34 | write("example.txt", buf); 35 | free(buf); 36 | 37 | -- Read a file into a buffer and iterate over its lines 38 | load_buffer("example.txt", buf); 39 | endbuffer(buf, at_end); 40 | while not at_end loop 41 | nextline(buf, tl); 42 | endbuffer(buf, at_end); 43 | end loop; 44 | free(buf); 45 | 46 | 47 | 48 | .. include:: auto/text_buffering.rst 49 | 50 | -------------------------------------------------------------------------------- /doc/rst/modules/timing_ops.rst: -------------------------------------------------------------------------------- 1 | ========== 2 | timing_ops 3 | ========== 4 | 5 | `extras/timing_ops.vhdl `_ 6 | 7 | `extras/timing_ops_xilinx.vhdl `_ 8 | 9 | Dependencies 10 | ------------ 11 | 12 | :doc:`sizing ` 13 | 14 | Description 15 | ----------- 16 | 17 | This is a package of functions to perform calculations on time 18 | and convert between different representations. The :vhdl:func:`~extras.timing_ops.clock_gen` procedures 19 | can be used to create a clock signal for simulation. 20 | 21 | A new physical type :vhdl:type:`~extras.timing_ops.frequency` is introduced and conversions between time, 22 | frequency, and real (time and frequency) are provided. Functions to 23 | convert from time in these three forms to integer :vhdl:type:`~extras.timing_ops.clock_cycles` are also 24 | included. The conversion from time to real uses an integer intermediate 25 | representation of time. It is designed to compensate for tools that use 26 | 64-bit time and 32-bit integers but only 31-bits of precision will be 27 | maintained in such cases. 28 | 29 | For all conversion functions, real values of time are expressed in units 30 | of seconds and real frequencies are in 1/sec. e.g. 1 ns = 1.0e-9, 31 | 1 MHz = 1.0e6. 32 | 33 | User defined physical types are limited to the range of ``integer``. On 32-bit 34 | platforms ``frequency'high`` = (2**31)-1 Hz = 2.14 GHz. Real numbers must be 35 | used to represent higher frequencies. 36 | 37 | The :vhdl:func:`~extras.timing_ops.to_clock_cycles` functions can introduce rounding errors and produce a 38 | result that is different from what would be expected assuming infinite 39 | precision. The magnitude of any errors will depend on how close the 40 | converted time is to the clock period. To assist in controlling the 41 | errors, a :vhdl:type:`~extras.timing_ops.time_rounding` parameter is available on all forms of 42 | ``to_clock_cycles`` that use real as an intermediate type for the calculation. 43 | It is set by default to round up toward infinity in anticipation that 44 | these functions will most often be used to compute the minium number of 45 | cycles for a delay. You can override this behavior to either round down or 46 | maintain normal round to nearest for the conversion from ``real`` to 47 | :vhdl:type:`~extras.timing_ops.clock_cycles`. 48 | 49 | To help detect the effect of rounding errors the :vhdl:func:`~extras.timing_ops.time_duration` and 50 | :vhdl:func:`~extras.timing_ops.report_time_precision` routines can be used in simulation to indicate 51 | deviation from the requested time span. 52 | 53 | Xilinx note 54 | ~~~~~~~~~~~ 55 | 56 | The Xilinx version of `timing_ops `_ is needed for synthesis with 57 | Xilinx XST. The physical type :vhdl:type:`~extras.timing_ops.frequency` and any associated functions have 58 | been removed. The standard ``timing_ops`` package will work with Xilinx Vivado 59 | and most third party synthesizers so consider using it instead if XST is 60 | not being used. 61 | 62 | 63 | Example usage 64 | ~~~~~~~~~~~~~ 65 | 66 | .. code-block:: vhdl 67 | 68 | library extras; use extras.sizing.bit_size; use extras.timing_ops.all; 69 | 70 | constant SYS_CLOCK_FREQ : frequency := 50 MHz; 71 | constant COUNT_1US : clock_cycles 72 | := to_clock_cycles(1 us, SYS_CLOCK_FREQ); 73 | signal counter : unsigned(bit_size(COUNT_1US)-1 downto 0); 74 | ... 75 | counter <= to_unsigned(COUNT_1US, counter'length); -- initialize counter 76 | report_time_precision("COUNT_1US", COUNT_1US, 1 us, 77 | time_duration(COUNT_1US, SYS_CLOCK_FREQ)); 78 | 79 | The value of the ``COUNT_1US`` constant will change to reflect any change in 80 | the system clock frequency and the size of the signal ``counter`` will now 81 | automatically adapt to guarantee it can represent the count for 1 us. 82 | 83 | The :vhdl:func:`~extras.timing_ops.clock_gen` procedure can be called from a process to generate a clock 84 | in simulation with the requested frequency or period and an optional duty 85 | cycle specification: 86 | 87 | .. code-block:: vhdl 88 | 89 | sys_clock_gen: process 90 | begin 91 | clock_gen(sys_clock, stop_clock, SYS_CLOCK_FREQ); 92 | wait; 93 | end process; 94 | 95 | 96 | 97 | .. include:: auto/timing_ops.rst 98 | 99 | -------------------------------------------------------------------------------- /makefile: -------------------------------------------------------------------------------- 1 | # VHDL make file 2 | 3 | RTL_ROOT := rtl 4 | VCOM_FLAGS := -source -quiet 5 | BUILD_DIR := build 6 | TAG_DIR := $(BUILD_DIR)/tags 7 | LIB_BASE_DIR := $(BUILD_DIR)/lib 8 | 9 | VERSION := $(shell grep -e "^version" doc/conf.py | sed -e "s/.*'\([^']*\)'/\1/") 10 | DIST_NAME := vhdl-extras-$(VERSION) 11 | DIST_DIR := $(BUILD_DIR)/dist/$(DIST_NAME) 12 | 13 | NO_COLOR=\x1b[0m 14 | SUCC_COLOR=\x1b[32;01m 15 | ERROR_COLOR=\x1b[31;01m 16 | WARN_COLOR=\x1b[33;01m 17 | 18 | OK=$(OK_COLOR)[OK]$(NO_COLOR) 19 | 20 | # Find the RTL source files 21 | RTL_DIRS := $(wildcard $(RTL_ROOT)/*) 22 | LIB_DIRS := $(foreach sdir, $(RTL_DIRS), $(LIB_BASE_DIR)/$(notdir $(sdir)) ) 23 | 24 | VPATH = $(RTL_DIRS) 25 | VPATH += $(TAG_DIR) 26 | 27 | # Skip XST specific timing package 28 | EXCLUDE_RTL := timing_ops_xilinx.vhdl 29 | RTL := $(filter-out $(EXCLUDE_RTL), $(foreach sdir, $(RTL_DIRS), $(notdir $(wildcard $(sdir)/*.vhd*)))) 30 | RTL := $(filter %.vhd %.vhdl, $(RTL)) 31 | 32 | TAG_OBJS := $(foreach fname, $(RTL), $(basename $(notdir $(fname))).tag) 33 | 34 | .SUFFIXES: 35 | .SUFFIXES: .vhdl .vhd 36 | 37 | define BUILD_VHDL 38 | @dir=`dirname $<`; \ 39 | if [ -z $${dir##*_*} ]; then \ 40 | std=$${dir##*_}; \ 41 | else \ 42 | std=93; \ 43 | fi; \ 44 | echo "** Compiling:" std=$$std lib=`basename $$dir` $<; \ 45 | vcom $(VCOM_FLAGS) -$$std -work `basename $$dir` $< 46 | @touch $(TAG_DIR)/$@ 47 | endef 48 | 49 | %.tag: %.vhdl 50 | $(BUILD_VHDL) 51 | 52 | %.tag: %.vhd 53 | $(BUILD_VHDL) 54 | 55 | 56 | .PHONY: compile clean dist 57 | 58 | compile: $(TAG_OBJS) 59 | 60 | clean: 61 | rm -rf $(BUILD_DIR) 62 | 63 | dist: $(DIST_DIR) 64 | rm -rf $(DIST_DIR)/* $(DIST_DIR)/.* 2>&-; hg clone . $(DIST_DIR) 65 | cd $(BUILD_DIR)/dist; tar czf $(DIST_NAME).tgz $(DIST_NAME); zip -q -r $(DIST_NAME).zip $(DIST_NAME) 66 | 67 | # Generate dependency rules 68 | RULES := auto_rules.mk 69 | 70 | $(BUILD_DIR)/$(RULES): $(RTL) | $(BUILD_DIR) 71 | @echo Making rules 72 | @python scripts/vdep.py $^ > $@ 73 | 74 | include $(BUILD_DIR)/$(RULES) 75 | 76 | 77 | 78 | $(BUILD_DIR): 79 | mkdir $(BUILD_DIR) 80 | 81 | $(TAG_DIR): | $(BUILD_DIR) 82 | mkdir $(TAG_DIR) 83 | 84 | 85 | $(LIB_BASE_DIR): | $(BUILD_DIR) 86 | mkdir $(LIB_BASE_DIR) 87 | 88 | $(LIB_DIRS): | $(LIB_BASE_DIR) 89 | @echo $(LIB_DIRS) | xargs -n 1 vlib 90 | 91 | 92 | 93 | $(TAG_OBJS): | $(TAG_DIR) $(LIB_DIRS) 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17 | 18 | architecture test of test_interrupt_ctl is 19 | constant CLOCK_FREQ : frequency := 100 MHz; 20 | constant CPERIOD : delay_length := to_period(CLOCK_FREQ); 21 | signal sim_done : boolean := false; 22 | 23 | signal int_mask, int_request, pending_int, current_int : std_ulogic_vector(7 downto 0); 24 | signal clock, reset, interrupt, interrupt_ack, clear_pending : std_ulogic; 25 | begin 26 | 27 | 28 | stim: process 29 | begin 30 | report "Seed: " & integer'image(TEST_SEED); 31 | seed(TEST_SEED); 32 | 33 | int_request <= (others => '0'); 34 | int_mask <= (others => '1'); 35 | interrupt_ack <= '0'; 36 | clear_pending <= '0'; 37 | 38 | reset <= '1', '0' after CPERIOD; 39 | 40 | wait for CPERIOD * 2; 41 | wait until falling_edge(clock); 42 | 43 | -- Assert single interrupt 44 | int_request(7) <= '1', '0' after CPERIOD; 45 | wait for CPERIOD * 2; 46 | assert interrupt = '1' and current_int = "10000000" 47 | report "Unexpected interrupt 1" severity failure; 48 | interrupt_ack <= '1', '0' after CPERIOD; 49 | wait for CPERIOD * 2; 50 | 51 | -- Assert simultaneous interrupts 52 | int_request(6) <= '1', '0' after CPERIOD; 53 | int_request(5) <= '1', '0' after CPERIOD; 54 | wait for CPERIOD * 2; 55 | assert interrupt = '1' and current_int = "00100000" 56 | report "Unexpected interrupt 2" severity failure; 57 | interrupt_ack <= '1', '0' after CPERIOD; 58 | wait for CPERIOD * 2; 59 | 60 | assert interrupt = '1' and current_int = "01000000" 61 | report "Unexpected interrupt 3" severity failure; 62 | interrupt_ack <= '1', '0' after CPERIOD; 63 | wait for CPERIOD * 2; 64 | 65 | assert interrupt = '0' and current_int = "00000000" 66 | report "Unexpected interrupt 4" severity failure; 67 | wait for CPERIOD * 2; 68 | 69 | -- Clear all pending interrupts 70 | int_request(3) <= '1', '0' after CPERIOD; 71 | int_request(2) <= '1', '0' after CPERIOD; 72 | int_request(1) <= '1', '0' after CPERIOD; 73 | wait for CPERIOD * 2; 74 | assert interrupt = '1' and pending_int = "00001110" 75 | report "Unexpected interrupt 4.5" severity failure; 76 | 77 | clear_pending <= '1', '0' after CPERIOD; 78 | wait for CPERIOD * 2; 79 | assert interrupt = '0' and pending_int = "00000000" 80 | report "Unexpected interrupt 4.6" severity failure; 81 | wait for CPERIOD * 2; 82 | 83 | 84 | -- Assert lower priority followed by higher priority 85 | int_request(4) <= '1', '0' after CPERIOD; 86 | wait for CPERIOD * 2; 87 | 88 | int_request(3) <= '1', '0' after CPERIOD; 89 | wait for CPERIOD * 2; 90 | 91 | assert interrupt = '1' and current_int = "00010000" 92 | report "Unexpected interrupt 5" severity failure; 93 | interrupt_ack <= '1', '0' after CPERIOD; 94 | wait for CPERIOD * 2; 95 | 96 | assert interrupt = '1' and current_int = "00001000" 97 | report "Unexpected interrupt 6" severity failure; 98 | interrupt_ack <= '1', '0' after CPERIOD; 99 | wait for CPERIOD * 2; 100 | 101 | -- Assert masked interrupt 102 | int_mask(2) <= '0'; 103 | int_request(2) <= '1', '0' after CPERIOD; 104 | wait for CPERIOD; 105 | assert interrupt = '0' 106 | report "Mask failure" severity failure; 107 | wait for CPERIOD * 2; 108 | 109 | -- Generate random interrupts 110 | for i in 1 to 20 loop 111 | int_request <= to_stdulogicvector(random(int_request'length)), 112 | (others => '0') after CPERIOD*2; 113 | wait for CPERIOD; 114 | 115 | assert pending_int = (int_request and int_mask) 116 | report "Missing interrupts" severity failure; 117 | 118 | wait for CPERIOD; 119 | 120 | while interrupt = '1' loop 121 | interrupt_ack <= '1', '0' after CPERIOD; 122 | wait for CPERIOD * 2; 123 | end loop; 124 | end loop; 125 | 126 | sim_done <= true; 127 | wait; 128 | 129 | end process; 130 | 131 | ic: interrupt_ctl 132 | port map ( 133 | Clock => clock, 134 | Reset => reset, 135 | 136 | Int_mask => int_mask, 137 | Int_request => int_request, 138 | Pending => pending_int, 139 | Current => current_int, 140 | 141 | Interrupt => interrupt, 142 | Acknowledge => interrupt_ack, 143 | Clear_pending => clear_pending 144 | ); 145 | 146 | cgen: process 147 | begin 148 | clock_gen(clock, sim_done, CLOCK_FREQ); 149 | wait; 150 | end process; 151 | 152 | end architecture; 153 | -------------------------------------------------------------------------------- /rtl/test/test_lcar_ops.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/rtl/test/test_lcar_ops.vhdl -------------------------------------------------------------------------------- /rtl/test/test_lfsr_ops.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/rtl/test/test_lfsr_ops.vhdl -------------------------------------------------------------------------------- /rtl/test/test_muxing.vhdl: -------------------------------------------------------------------------------- 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ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | library extras; 7 | use extras.arithmetic.all; 8 | use extras.timing_ops.all; 9 | use extras.sizing.bit_size; 10 | 11 | entity test_pipelined_adder is 12 | end entity; 13 | 14 | architecture sim of test_pipelined_adder is 15 | constant SYS_CLOCK_FREQ : frequency := 50 MHz; 16 | constant SYS_CLOCK_PERIOD : delay_length := to_period(SYS_CLOCK_FREQ); 17 | 18 | signal clock, reset : std_ulogic; 19 | signal done : boolean := false; 20 | 21 | constant WORD_SIZE : positive := 13; 22 | signal a, const : unsigned(WORD_SIZE-1 downto 0); 23 | signal sum : unsigned(WORD_SIZE downto 0); 24 | 25 | constant SLICES : positive := 1; 26 | begin 27 | 28 | stim: process 29 | begin 30 | a <= (others => '0'); 31 | const <= (others => '0'); 32 | 33 | reset <= '1', '0' after SYS_CLOCK_PERIOD * 4; 34 | 35 | wait until reset = '0'; 36 | wait until falling_edge(clock); 37 | 38 | a <= to_unsigned(33, a'length); 39 | const <= to_unsigned(10, const'length); 40 | 41 | wait for SYS_CLOCK_PERIOD * SLICES; 42 | a <= to_unsigned(254, a'length); 43 | const <= to_unsigned(1, const'length); 44 | 45 | wait for SYS_CLOCK_PERIOD * SLICES; 46 | a <= to_unsigned(255, a'length); 47 | --const <= to_unsigned(1, const'length); 48 | 49 | wait for SYS_CLOCK_PERIOD; 50 | a <= to_unsigned(15, a'length); 51 | --const <= to_unsigned(1, const'length); 52 | 53 | wait for SYS_CLOCK_PERIOD; 54 | a <= to_unsigned(2**WORD_SIZE - 10, a'length); 55 | 56 | wait for SYS_CLOCK_PERIOD; 57 | a <= to_unsigned(200, a'length); 58 | const <= to_unsigned(300, a'length); 59 | 60 | 61 | wait for SYS_CLOCK_PERIOD * 30; 62 | 63 | done <= true; 64 | end process; 65 | 66 | pa: pipelined_adder 67 | generic map ( 68 | SLICES => SLICES, 69 | CONST_B_INPUT => false 70 | ) 71 | port map ( 72 | Clock => clock, 73 | Reset => reset, 74 | 75 | A => a, 76 | B => const, 77 | 78 | Sum => sum 79 | ); 80 | 81 | sys_clock_gen: process 82 | begin 83 | clock_gen(clock, done, SYS_CLOCK_FREQ); 84 | wait; 85 | end process; 86 | 87 | end architecture; 88 | -------------------------------------------------------------------------------- /rtl/test/test_random.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/rtl/test/test_random.vhdl -------------------------------------------------------------------------------- /rtl/test/test_reg_file.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/rtl/test/test_reg_file.vhdl -------------------------------------------------------------------------------- /rtl/test/test_rom.vhdl: -------------------------------------------------------------------------------- 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| 27 | variable mux_in_array : sulv_array(0 to 2**SEL_WIDTH-1)(7 downto 0); 28 | variable expect_array : std_ulogic_vector(7 downto 0); 29 | begin 30 | 31 | -- Test decode functions 32 | for i in 0 to 2**SEL_WIDTH-1 loop 33 | sel := to_unsigned(i, sel'length); 34 | 35 | full := decode(sel); 36 | fmatch := (others => '0'); 37 | fmatch(i) := '1'; 38 | 39 | assert full = fmatch 40 | report "Mismatch in decode[unsigned]: " & integer'image(i) 41 | severity failure; 42 | 43 | partial := decode(sel, partial'length); 44 | pmatch := (others => '0'); 45 | if i <= partial'high then 46 | pmatch(i) := '1'; 47 | end if; 48 | 49 | assert partial = pmatch 50 | report "Mismatch in decode[unsigned, positive]: " & integer'image(i) 51 | severity failure; 52 | 53 | end loop; 54 | 55 | 56 | -- Test mux functions 57 | for i in 0 to 2**SEL_WIDTH-1 loop 58 | sel := to_unsigned(i, sel'length); 59 | 60 | for j in mux_in'range loop 61 | mux_in := (others => '0'); 62 | mux_in(j) := '1'; 63 | 64 | if j = i then 65 | expect := '1'; 66 | else 67 | expect := '0'; 68 | end if; 69 | 70 | assert mux(mux_in, sel) = expect 71 | report "Mismatch in mux[sulv, unsigned]: sel = " & integer'image(i) & " j = " & integer'image(j) 72 | severity failure; 73 | 74 | assert mux(mux_in, decode(sel)) = expect 75 | report "Mismatch in mux[sulv, sulv]: sel = " & integer'image(i) & " j = " & integer'image(j) 76 | severity failure; 77 | 78 | end loop; 79 | end loop; 80 | 81 | 82 | -- Test demux 83 | for i in 0 to 2**SEL_WIDTH-1 loop 84 | sel := to_unsigned(i, sel'length); 85 | fmatch := (others => '0'); 86 | fmatch(i) := '1'; 87 | 88 | assert demux('1', sel, 2**SEL_WIDTH) = fmatch 89 | report "Mismatch in demux: sel = " & integer'image(i) 90 | severity failure; 91 | end loop; 92 | 93 | 94 | --#### 2008 additions 95 | 96 | -- Test mux functions 97 | for i in 0 to 2**SEL_WIDTH-1 loop 98 | sel := to_unsigned(i, sel'length); 99 | 100 | for j in mux_in_array'range loop 101 | mux_in_array := (others => (others => '0')); 102 | mux_in_array(j) := (others => '1'); 103 | 104 | if j = i then 105 | expect_array := (others => '1'); 106 | else 107 | expect_array := (others => '0'); 108 | end if; 109 | 110 | assert mux(mux_in_array, sel) = expect_array 111 | report "Mismatch in mux[sulv_array, unsigned]: sel = " & integer'image(i) & " j = " & integer'image(j) 112 | severity failure; 113 | 114 | end loop; 115 | end loop; 116 | 117 | 118 | wait; 119 | end process; 120 | 121 | end architecture; 122 | -------------------------------------------------------------------------------- /rtl/test_2008/test_random_20xx.vhdl: -------------------------------------------------------------------------------- 1 | 2 | library extras_2008; 3 | use extras_2008.random.all; 4 | 5 | entity test_random_20xx is 6 | end entity; 7 | 8 | architecture test of test_random_20xx is 9 | signal bv : bit_vector(29 downto 0); 10 | begin 11 | test: process 12 | variable r : real; 13 | variable i : integer; 14 | variable b : boolean; 15 | begin 16 | seed(42, 12); 17 | 18 | r := random; 19 | report "Random: " & real'image(r); 20 | 21 | r := random; 22 | report "Random: " & real'image(r); 23 | 24 | r := random; 25 | report "Random: " & real'image(r); 26 | 27 | for j in 1 to 20 loop 28 | i := randint(0, 5); 29 | report "Randint: " & integer'image(i); 30 | end loop; 31 | 32 | for j in 1 to 20 loop 33 | b := random; 34 | report "Randbool: " & boolean'image(b); 35 | end loop; 36 | 37 | wait; 38 | end process; 39 | 40 | bv_rand: process 41 | begin 42 | for i in 0 to 20 loop 43 | bv <= random(bv'length); 44 | wait for 1 ns; 45 | end loop; 46 | 47 | wait; 48 | end process; 49 | end architecture; 50 | -------------------------------------------------------------------------------- /rtl/test_2008/test_reg_file_2008.vhdl: -------------------------------------------------------------------------------- 1 | 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | use std.textio.all; 6 | use ieee.std_logic_textio.all; 7 | 8 | library extras; 9 | use extras.random.all; 10 | use extras.sizing.bit_size; 11 | use extras.timing_ops.all; 12 | 13 | entity test_reg_file is 14 | generic ( 15 | TEST_SEED : positive := 1234; 16 | NUM_REGS : positive := 4; 17 | 18 | -- Modelsim is braindead and doesn't allow passing generic composite types 19 | -- from the command line so we have to flatten them into a bit_vector. 20 | -- Modelsim also limits command line plain generic strings to 64 chars but 21 | -- not apparently for bit string literals. 22 | --STROBE_BIT_MASK : reg_array := (X"0003", X"3000", X"0000", X"0000"); 23 | --DIRECT_READ_BIT_MASK : reg_array := (X"0000", X"0FF0", X"0000", X"0000") 24 | STROBE_BIT_MASK_BV : bit_vector := (X"0003_3000_0000_0000"); 25 | DIRECT_READ_BIT_MASK_BV : bit_vector := (X"0000_0FF0_0000_0000") 26 | ); 27 | end entity; 28 | 29 | 30 | library extras_2008; 31 | use extras_2008.reg_file_pkg.all; 32 | 33 | architecture test of test_reg_file is 34 | 35 | subtype my_reg_word is std_ulogic_vector(15 downto 0); 36 | subtype my_reg_array is reg_array(0 to NUM_REGS-1)(my_reg_word'range); 37 | 38 | signal clock, reset : std_ulogic; 39 | 40 | signal sim_done : boolean := false; 41 | constant CLOCK_FREQ : frequency := 50 MHz; 42 | constant CPERIOD : delay_length := to_period(CLOCK_FREQ); 43 | 44 | signal reg_sel : unsigned(bit_size(NUM_REGS)-1 downto 0); 45 | signal we, clear : std_ulogic; 46 | signal wr_data, rd_data : my_reg_word; 47 | signal registers, direct_read : my_reg_array; 48 | signal reg_written : std_ulogic_vector(my_reg_array'range); 49 | 50 | 51 | function split_mask(m : bit_vector) return my_reg_array is 52 | alias m2 : bit_vector(m'length-1 downto 0) is m; 53 | variable r : my_reg_array; 54 | begin 55 | for i in 0 to NUM_REGS-1 loop 56 | r(i) := to_stdulogicvector(m2((i+1)*my_reg_word'length-1 downto i*my_reg_word'length)); 57 | end loop; 58 | return r; 59 | end function; 60 | 61 | 62 | constant DRBM : reg_array := split_mask(DIRECT_READ_BIT_MASK_BV); 63 | constant SBM : reg_array := split_mask(STROBE_BIT_MASK_BV); 64 | begin 65 | 66 | stim: process 67 | variable expect : my_reg_word; 68 | variable l : line; 69 | 70 | variable wr_log : my_reg_array; 71 | begin 72 | report "Seed: " & integer'image(TEST_SEED); 73 | seed(TEST_SEED); 74 | 75 | we <= '0'; 76 | clear <= '0'; 77 | wr_data <= (others => '0'); 78 | reg_sel <= (others => '0'); 79 | direct_read <= (others => (others => '0')); 80 | 81 | reset <= '1', '0' after CPERIOD; 82 | 83 | wait for CPERIOD * 2; 84 | 85 | -- Write all '1's to registers and verify all non-strobes are '1' 86 | -- and all strobes are '0' 87 | 88 | wait until falling_edge(clock); 89 | 90 | 91 | for j in 1 to 10 loop 92 | 93 | we <= '1'; 94 | 95 | for i in registers'range loop 96 | reg_sel <= to_unsigned(i, reg_sel'length); 97 | wr_log(i) := to_stdulogicvector(random(my_reg_word'length)); 98 | wr_data <= wr_log(i); 99 | direct_read(i) <= to_stdulogicvector(random(my_reg_word'length)); 100 | wait for CPERIOD; 101 | end loop; 102 | 103 | we <= '0'; 104 | wait for CPERIOD; 105 | 106 | 107 | for i in registers'range loop 108 | reg_sel <= to_unsigned(i, reg_sel'length); 109 | wait for CPERIOD; 110 | 111 | expect := wr_log(i) and not SBM(i); 112 | hwrite(l, registers(i)); 113 | write(l, string'(" != ")); 114 | hwrite(l, expect); 115 | 116 | --report "Register: " & integer'image(i) & " = " & l.all; 117 | 118 | assert registers(i) = expect 119 | report "Register mismatch: " & integer'image(i) & " " & l.all 120 | severity failure; 121 | 122 | wait for CPERIOD; 123 | 124 | expect := (expect and not DRBM(i)) 125 | or (direct_read(i) and DRBM(i)); 126 | assert rd_data = expect 127 | report "rd_data mismatch: " & integer'image(i) 128 | severity failure; 129 | 130 | deallocate(l); 131 | 132 | end loop; 133 | 134 | 135 | -- Clear all registers 136 | clear <= '1', '0' after CPERIOD; 137 | wait for CPERIOD; 138 | 139 | assert registers = my_reg_array'(others => (others => '0')) 140 | report "Clear failure" 141 | severity failure; 142 | 143 | end loop; 144 | 145 | sim_done <= true; 146 | wait; 147 | end process; 148 | 149 | 150 | rf : reg_file 151 | generic map ( 152 | DIRECT_READ_BIT_MASK => split_mask(DIRECT_READ_BIT_MASK_BV), 153 | STROBE_BIT_MASK => split_mask(STROBE_BIT_MASK_BV) 154 | ) 155 | port map ( 156 | Clock => clock, 157 | Reset => reset, 158 | 159 | Clear => clear, 160 | 161 | Reg_sel => reg_sel, 162 | We => we, 163 | Wr_data => wr_data, 164 | Rd_data => rd_data, 165 | 166 | Registers => registers, 167 | Direct_Read => direct_read, 168 | Reg_written => reg_written 169 | ); 170 | 171 | cgen: process 172 | begin 173 | clock_gen(clock, sim_done, CLOCK_FREQ); 174 | wait; 175 | end process; 176 | 177 | end architecture; 178 | 179 | 180 | -------------------------------------------------------------------------------- /scripts/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/scripts/__init__.py -------------------------------------------------------------------------------- /scripts/ada/smc_gen.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ./vhdl_gen | cat strings_maps_constants.head.vhdl - > strings_maps_constants.vhdl 4 | -------------------------------------------------------------------------------- /scripts/ada/strings_maps_constants.head.vhdl: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- _ __ __ __ ____ __ = -- 3 | -- | | / // / / // __ \ / / = -- 4 | -- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ -- 5 | -- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` -- 6 | -- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) -- 7 | -- ===== / -- 8 | -- === -- 9 | ----------------------------- = ---------------------------------- 10 | --# strings_maps_constants.vhdl - Constants for use with character mapping 11 | --# $Id$ 12 | --# Freely available from VHDL-extras (http://code.google.com/p/vhdl-extras) 13 | --# 14 | --# Copyright © 2014 Kevin Thibedeau 15 | --# (kevin 'period' thibedeau 'at' gmail 'punto' com) 16 | --# 17 | --# Permission is hereby granted, free of charge, to any person obtaining a 18 | --# copy of this software and associated documentation files (the "Software"), 19 | --# to deal in the Software without restriction, including without limitation 20 | --# the rights to use, copy, modify, merge, publish, distribute, sublicense, 21 | --# and/or sell copies of the Software, and to permit persons to whom the 22 | --# Software is furnished to do so, subject to the following conditions: 23 | --# 24 | --# The above copyright notice and this permission notice shall be included in 25 | --# all copies or substantial portions of the Software. 26 | --# 27 | --# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 | --# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 | --# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 30 | --# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 31 | --# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 32 | --# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 33 | --# DEALINGS IN THE SOFTWARE. 34 | --# 35 | --# DEPENDENCIES: strings_maps, characters_latin_1 36 | --# 37 | --# DESCRIPTION: 38 | --# This package provides constants for various character sets from the range 39 | --# of Latin-1 and mappings for upper case, lower case, and basic (unaccented) 40 | --# characters. It is a clone of the Ada'95 package 41 | --# Ada.Strings.Maps.Constants. 42 | -------------------------------------------------------------------- 43 | 44 | library extras; 45 | use extras.strings_maps.all; 46 | 47 | package strings_maps_constants is 48 | 49 | constant NULL_SET : character_set := (others => false); 50 | constant IDENTITY : character_mapping; 51 | 52 | constant CONTROL_SET : character_set; 53 | constant GRAPHIC_SET : character_set; 54 | constant LETTER_SET : character_set; 55 | constant LOWER_SET : character_set; 56 | constant UPPER_SET : character_set; 57 | constant BASIC_SET : character_set; 58 | constant DECIMAL_DIGIT_SET : character_set; 59 | constant HEXADECIMAL_DIGIT_SET : character_set; 60 | constant ALPHANUMERIC_SET : character_set; 61 | constant SPECIAL_SET : character_set; 62 | constant ISO_646_SET : character_set; 63 | 64 | constant LOWER_CASE_MAP : character_mapping; 65 | constant UPPER_CASE_MAP : character_mapping; 66 | constant BASIC_MAP : character_mapping; 67 | 68 | end package; 69 | 70 | library extras; 71 | use extras.characters_latin_1.all; 72 | 73 | package body strings_maps_constants is 74 | 75 | function generate_identity_mapping return character_mapping is 76 | variable result : character_mapping; 77 | begin 78 | for ch in character_mapping'range loop 79 | result(ch) := ch; 80 | end loop; 81 | 82 | return result; 83 | end function; 84 | 85 | constant IDENTITY : character_mapping := generate_identity_mapping; 86 | 87 | 88 | 89 | -------------------------------------------------------------------------------- /scripts/color.py: -------------------------------------------------------------------------------- 1 | #!usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | 4 | '''Color formatting 5 | ''' 6 | 7 | from __future__ import print_function, division 8 | 9 | try: 10 | import colorama 11 | colorama.init() 12 | 13 | from colorama import Fore, Back, Style 14 | 15 | except ImportError: 16 | 17 | def note(t): return t 18 | def success(t): return t 19 | def warn(t): return t 20 | def error(t): return t 21 | 22 | else: 23 | import os 24 | _no_color = os.getenv('NO_COLOR', 'false') 25 | _no_color = True if _no_color.lower() in ['1', 'true', 't', 'y', 'yes'] else False 26 | 27 | def stdout_redirected(): 28 | return os.fstat(0) != os.fstat(1) 29 | 30 | _redir_stdout = stdout_redirected() 31 | 32 | def colorize(t, code): 33 | if _no_color or _redir_stdout: 34 | return t 35 | 36 | return ''.join([code, t, Style.RESET_ALL]) 37 | 38 | def note(t): 39 | return colorize(t, Fore.BLUE) 40 | 41 | def success(t): 42 | return colorize(t, Fore.GREEN) 43 | 44 | def warn(t): 45 | return colorize(t, Fore.YELLOW + Style.BRIGHT) 46 | 47 | def error(t): 48 | return colorize(t, Fore.RED + Style.BRIGHT) 49 | 50 | 51 | if __name__ == '__main__': 52 | print('Colorized text:\n') 53 | print('note("foobar") : ' + note('foobar')) 54 | print('success("foobar") : ' + success('foobar')) 55 | print('warn("foobar") : ' + warn('foobar')) 56 | print('error("foobar") : ' + error('foobar')) 57 | 58 | #import os 59 | #print('redir?', os.fstat(0) == os.fstat(1)) 60 | -------------------------------------------------------------------------------- /scripts/init_modelsim.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | 4 | '''Modelsim init script 5 | ''' 6 | 7 | # Copyright © 2013 Kevin Thibedeau 8 | 9 | from __future__ import print_function, division 10 | 11 | import subprocess as subp 12 | import os 13 | import sys 14 | import copy 15 | 16 | 17 | def new_modelsim_ini(): 18 | # Attempt a vmap in the cwd. This will create a new modelsim.ini file 19 | env = { 'MGC_WD': os.getcwd(), 'PATH': os.environ['PATH'] } 20 | p = subp.Popen(['vmap', 'foo', 'bar'], env=env, stderr=subp.STDOUT, stdout=subp.PIPE) 21 | p.communicate() 22 | 23 | 24 | # Check if modelsim.ini already exists 25 | ini_path = os.path.join(os.getcwd(), 'modelsim.ini') 26 | if os.path.exists(ini_path): 27 | print('modelsim.ini exists: Doing nothing') 28 | sys.exit(0) 29 | 30 | print('Generating modelsim.ini...') 31 | 32 | new_modelsim_ini() 33 | 34 | # Check that we succeeded in making a fresh modelsim.ini 35 | if not os.path.exists(ini_path): 36 | print('ERROR: Could not create modelsim.ini') 37 | sys.exit(1) 38 | 39 | # Modify the library section of this new ini file 40 | 41 | lines = [] 42 | with open(ini_path, 'r') as fh: 43 | lines = fh.readlines() 44 | 45 | if len(lines) == 0: 46 | print('ERROR: Empty modelsim.ini file') 47 | sys.exit(1) 48 | 49 | def modify_ini(lines): 50 | # We will replace everything between the [Library] header 51 | # and our dummy map foo = bar. 52 | 53 | # Find library section 54 | lib_start = 0 55 | lib_end = 0 56 | for i, l in enumerate(lines): 57 | if '[Library]' in l: 58 | lib_start = i 59 | 60 | if 'foo = bar' in l: 61 | lib_end = i 62 | break 63 | 64 | if lib_end == lib_start: # Nothing found 65 | return lines 66 | 67 | new_lib = \ 68 | '''[Library] 69 | std = $MODEL_TECH/../std 70 | ieee = $MODEL_TECH/../ieee 71 | vital2000 = $MODEL_TECH/../vital2000 72 | modelsim_lib = $MODEL_TECH/../modelsim_lib 73 | 74 | others=$MGC_WD/modelsim.map 75 | 76 | ''' 77 | new_lines = copy.copy(lines) 78 | del new_lines[lib_start:lib_end+1] 79 | new_lines.insert(lib_start, new_lib) 80 | 81 | return new_lines 82 | 83 | lines = modify_ini(lines) 84 | 85 | with open(ini_path, 'w') as fh: 86 | fh.writelines(lines) 87 | 88 | print('success') 89 | 90 | 91 | -------------------------------------------------------------------------------- /scripts/vdep.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | 4 | '''VHDL Dependency tool 5 | ''' 6 | 7 | # Copyright © 2013 Kevin Thibedeau 8 | 9 | from __future__ import print_function, division 10 | 11 | import os 12 | import sys 13 | import re 14 | from color import error 15 | 16 | class FileInfo(object): 17 | def __init__(self, fname): 18 | self.name = fname 19 | self.lib = os.path.split(os.path.dirname(fname))[1] 20 | 21 | self.packages = [] 22 | self.pkg_body_defs = [] 23 | self.uses = [] 24 | self.depends = set() 25 | 26 | use_re = re.compile('^ *use +(.+);') 27 | pkg_re = re.compile('^ *package +(.+) +is') 28 | generic_pkg_re = re.compile('^ *package.*is +new +(.+)') 29 | 30 | def parse(self): 31 | uses = [] 32 | pkg_defs = [] 33 | pkg_body_defs = [] 34 | 35 | try: 36 | with open(self.name, 'r') as fh: 37 | for line in fh: 38 | # Find use statements 39 | m = self.use_re.match(line) 40 | if m: 41 | # FIX: VHDL may allow use statements without a library: use pkg.foo; 42 | #print('# use:', m.group(1).split('.')[:2]) 43 | #m.group(1).split('.')[:2] 44 | uses.append(m.group(1).split('.')[:2]) 45 | 46 | # Find generic package instances 47 | m = self.generic_pkg_re.match(line) 48 | if m: 49 | uses.append(m.group(1).split('.')[:2]) 50 | 51 | m = self.pkg_re.match(line) 52 | if m: 53 | fields = m.group(1).split() 54 | if fields[0].lower() == 'body': 55 | pkg_body_defs.append(fields[1]) 56 | else: 57 | #print('## pkg:', fields[0]) 58 | pkg_defs.append(self.lib + '.' + fields[0]) 59 | except IOError: 60 | pass 61 | 62 | self.uses = uses 63 | self.packages = pkg_defs 64 | self.pkg_body_defs = pkg_body_defs 65 | 66 | 67 | 68 | 69 | def find_dependencies(dep_infos): 70 | all_packages = {} 71 | std_libs = ['std', 'ieee'] 72 | 73 | for fi in dep_infos: 74 | for p in fi.packages: 75 | all_packages[p] = fi.name 76 | 77 | for fi in dep_infos: 78 | for u in fi.uses: 79 | if u[0] in std_libs: 80 | continue 81 | 82 | lib_name = u[0] + '.' + u[1] 83 | if lib_name in all_packages: 84 | dep_name = all_packages[lib_name] 85 | if dep_name != fi.name: 86 | fi.depends.add(dep_name) 87 | else: 88 | print(error('ERROR: unsatisfied dependency: {} in {}'.format(\ 89 | '.'.join(u), fi.name)), file=sys.stderr) 90 | 91 | 92 | def sort_dependencies(dep_infos): 93 | targets = set() 94 | new_infos = [] 95 | # put all leaf nodes first 96 | for fi in dep_infos: 97 | if not fi.depends: 98 | targets.add(fi.name) 99 | new_infos.append(fi) 100 | 101 | #print('### targets', targets) 102 | 103 | while len(targets) < len(dep_infos): 104 | for fi in dep_infos: 105 | if fi.name in targets: 106 | continue 107 | 108 | satisfied = all([d in targets for d in fi.depends]) 109 | if satisfied: 110 | targets.add(fi.name) 111 | new_infos.append(fi) 112 | 113 | return new_infos 114 | 115 | 116 | def find_source(path): 117 | sources = [] 118 | for root, dirs, files in os.walk(path): 119 | for f in files: 120 | if f.endswith('.vhdl'): 121 | sources.append(os.path.join(root, f)) 122 | 123 | return sources 124 | 125 | #files = find_source('src/extras') 126 | 127 | 128 | files = sys.argv[1:] 129 | 130 | dep_infos = [] 131 | for f in files: 132 | fi = FileInfo(f) 133 | fi.parse() 134 | dep_infos.append(fi) 135 | 136 | 137 | find_dependencies(dep_infos) 138 | dep_infos = sort_dependencies(dep_infos) 139 | 140 | for fi in dep_infos: 141 | target = os.path.basename(os.path.splitext(fi.name)[0]) + '.tag' 142 | dep_tags = [os.path.basename(os.path.splitext(d)[0]) + '.tag' for d in fi.depends] 143 | print('{}: {}'.format(target, ' '.join(dep_tags))) 144 | 145 | 146 | 147 | 148 | -------------------------------------------------------------------------------- /start_proj.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | export MGC_WD=`pwd` 3 | 4 | # Create default modelsim.ini with altered library mapping 5 | if [ ! -f modelsim.ini ]; then 6 | python scripts/init_modelsim.py 7 | fi 8 | 9 | # Create build directory and Modelsim libs if they don't exist 10 | if [ ! -d build ]; then 11 | mkdir -p build/lib 12 | vlib build/lib/extras 13 | vlib build/lib/test 14 | fi 15 | -------------------------------------------------------------------------------- /test/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinpt/vhdl-extras/b8916c4942e99d02fac04e25799cb2c996eb5870/test/__init__.py -------------------------------------------------------------------------------- /test/eng.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | 4 | '''Engineering unit string formatting 5 | ''' 6 | 7 | # Copyright © 2013 Kevin Thibedeau 8 | 9 | # This file is part of Ripyl. 10 | 11 | # Ripyl is free software: you can redistribute it and/or modify 12 | # it under the terms of the GNU Lesser General Public License as 13 | # published by the Free Software Foundation, either version 3 of 14 | # the License, or (at your option) any later version. 15 | 16 | # Ripyl is distributed in the hope that it will be useful, 17 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | # GNU Lesser General Public License for more details. 20 | 21 | # You should have received a copy of the GNU Lesser General Public 22 | # License along with Ripyl. If not, see . 23 | 24 | import math 25 | 26 | class Eng(object): 27 | '''Base class for engineering unit string formatting''' 28 | def __init__(self, f, frac_digits=3): 29 | ''' 30 | f (number) 31 | The number to represent in engineering units. 32 | 33 | frac_digits (int) 34 | The number of fractional digits to display in a string. 35 | ''' 36 | self.f = f 37 | self.frac_digits = frac_digits 38 | if frac_digits < 0: 39 | raise ValueError('frac_digits must be a positive integer') 40 | 41 | def __float__(self): 42 | return self.f 43 | 44 | def __repr__(self): 45 | return 'Eng({}, {})'.format(self.f, self.frac_digits) 46 | 47 | def _to_eng(self): 48 | exp = int(math.log10(abs(self.f))) 49 | e_exp = exp - exp % 3 50 | if e_exp <= 0 and self.f < 10.0**e_exp: 51 | e_exp -= 3 52 | e_num = self.f / 10**e_exp 53 | return e_num, e_exp 54 | 55 | def __str__(self): 56 | e_num, e_exp = self._to_eng() 57 | digits = '{0:.{1}f}'.format(e_num, self.frac_digits) 58 | return digits + 'e' + str(e_exp) 59 | 60 | 61 | si_prefixes = { 62 | 21: 'Y', 63 | 18: 'Z', 64 | 15: 'E', 65 | 12: 'P', 66 | 9: 'G', 67 | 6: 'M', 68 | 3: 'k', 69 | 0: '', 70 | -3: 'm', 71 | -6: 'u', 72 | -9: 'n', 73 | -12: 'p', 74 | -15: 'f', 75 | -18: 'a', 76 | -21: 'z', 77 | -24: 'y' 78 | } 79 | 80 | class EngSI(Eng): 81 | '''Class for engineering unit string formatting with SI units''' 82 | def __init__(self, f, units='', frac_digits=3, unit_sep=' '): 83 | ''' 84 | f (number) 85 | The number to represent in engineering units. 86 | 87 | units (string) 88 | The units that the number represents. 89 | 90 | frac_digits (int) 91 | The number of fractional digits to display in a string. 92 | 93 | unit_sep (string) 94 | The separator between the number and the units string 95 | ''' 96 | Eng.__init__(self, f, frac_digits) 97 | self.units = units 98 | self.unit_sep = unit_sep 99 | self.prefixes = si_prefixes 100 | 101 | def __repr__(self): 102 | return 'EngSI({}, {}, {}, {})'.format(self.f, self.units, self.frac_digits, self.unit_sep) 103 | 104 | def __str__(self): 105 | e_num, e_exp = self._to_eng() 106 | digits = '{0:.{1}f}'.format(e_num, self.frac_digits) 107 | 108 | if e_exp in self.prefixes: 109 | str_exp = self.unit_sep + self.prefixes[e_exp] + self.units 110 | else: 111 | str_exp = 'e' + str(e_exp) 112 | 113 | return digits + str_exp 114 | 115 | 116 | 117 | si_uc_prefixes = { 118 | 21: 'Y', 119 | 18: 'Z', 120 | 15: 'E', 121 | 12: 'P', 122 | 9: 'G', 123 | 6: 'M', 124 | 3: 'k', 125 | 0: '', 126 | -3: 'm', 127 | -6: u'\u03bc', # Greek small-mu 128 | -9: 'n', 129 | -12: 'p', 130 | -15: 'f', 131 | -18: 'a', 132 | -21: 'z', 133 | -24: 'y' 134 | } 135 | 136 | class EngUSI(EngSI): 137 | '''Class for engineering unit string formatting with SI units with unicode characters''' 138 | def __init__(self, f, units='', frac_digits=3, unit_sep=' '): 139 | EngSI.__init__(self, f, units, frac_digits, unit_sep) 140 | self.prefixes = si_uc_prefixes 141 | 142 | def __repr__(self): 143 | return 'EngUSI({}, {}, {}, {})'.format(self.f, self.units, self.frac_digits, self.unit_sep) 144 | 145 | 146 | 147 | def eng(f, frac_digits=3): 148 | '''Create engineering formatted string''' 149 | return str(Eng(f, frac_digits)) 150 | 151 | def eng_si(f, units='', frac_digits=3, unit_sep=' '): 152 | '''Create engineering formatted string with SI units''' 153 | return str(EngSI(f, units, frac_digits, unit_sep)) 154 | 155 | def eng_usi(f, units='', frac_digits=3, unit_sep=' '): 156 | '''Create engineering formatted string with unicode SI units''' 157 | return str(EngUSI(f, units, frac_digits, unit_sep)) 158 | 159 | -------------------------------------------------------------------------------- /test/modelsim.py: -------------------------------------------------------------------------------- 1 | from __future__ import print_function, division 2 | 3 | import os 4 | import time 5 | import subprocess as subp 6 | import threading 7 | from threading import Thread 8 | import Queue as queue 9 | import scripts.color as color 10 | 11 | 12 | def enqueue_pipe(pipe, queue): 13 | try: 14 | for ln in iter(pipe.readline, b''): 15 | queue.put(ln) 16 | except: 17 | pass 18 | 19 | pipe.close() 20 | 21 | 22 | def get_output(outq): 23 | out = '' 24 | try: 25 | while True: # Add output from the queue until it is empty 26 | out += outq.get_nowait() 27 | except queue.Empty: 28 | return out 29 | 30 | 31 | class Modelsim(object): 32 | def __init__(self, log_file='vsim.log'): 33 | self.log_file = log_file 34 | self.p = None 35 | self.outq = None 36 | self.errq = None 37 | 38 | self._setup_vsim_process() 39 | 40 | def _setup_vsim_process(self): 41 | print('\n' + color.success('*** Starting Modelsim ***')) 42 | env = { 'MGC_WD': os.getcwd(), 'PATH': os.environ['PATH'] } 43 | self.p = subp.Popen(['vsim', '-c', '-l', self.log_file], env=env, stdin=subp.PIPE, stderr=subp.PIPE, stdout=subp.PIPE) 44 | 45 | self.outq = queue.Queue() 46 | self.errq = queue.Queue() 47 | 48 | out_thread = Thread(target=enqueue_pipe, args=(self.p.stdout, self.outq)) 49 | err_thread = Thread(target=enqueue_pipe, args=(self.p.stderr, self.errq)) 50 | out_thread.daemon = True 51 | err_thread.daemon = True 52 | out_thread.start() 53 | err_thread.start() 54 | 55 | # Keep the process from dying on an elaboration error 56 | self.p.stdin.write('onElabError resume\n') 57 | 58 | # Define a dummy sentinel proc 59 | self.p.stdin.write('proc sentinel {} {}\n') 60 | self.p.stdin.flush() 61 | 62 | # Wait for Modelsim to start and process our commands 63 | while True: 64 | out = get_output(self.outq) 65 | if 'sentinel' in out: break 66 | 67 | 68 | def restart(self): 69 | del self.outq 70 | del self.errq 71 | self._setup_vsim_process() 72 | 73 | 74 | def exec_tcl(self, cmd, verbose=False): 75 | '''Execute a TCL command in the Modelsim interpreter. 76 | 77 | We want to execute a command and wait until it is complete 78 | before proceeding. This can be done by waiting for the prompt 79 | to appear but a complication arises because we use blocking I/O 80 | (readline) to fill the queues. Python doesn't provide platform 81 | independent non-blocking I/O so we cannot see when an incomplete 82 | line with a prompt is output. 83 | 84 | As a hack we call the dummy "sentinel" command after every 85 | requested command. This ceates a complete line with a signature 86 | we can look for. When sentinel shows up in the output stream we 87 | know that the previous command finished. 88 | ''' 89 | 90 | #print('### PID:', self.p.pid) 91 | 92 | self.p.stdin.write(cmd + '\n') 93 | self.p.stdin.write('sentinel\n') 94 | self.p.stdin.flush() 95 | 96 | out = [] 97 | while True: 98 | if self.process_done(): break # The process died 99 | 100 | out.append(get_output(self.outq)) 101 | if '> sentinel' in out[-1]: break # Stop when we see the prompt with the sentinel 102 | 103 | result = '\n'.join(''.join(out).split('\n')[:-2]) 104 | if verbose: print(result) 105 | return result 106 | 107 | def process_done(self): 108 | return self.p.poll() is not None 109 | 110 | 111 | def quit(self): 112 | print('\n\n' + color.note('*** Stopping Modelsim ***')) 113 | err = get_output(self.errq); 114 | #print('### Threads:', threading.enumerate()) 115 | self.p.stdin.write('quit\n') 116 | self.p.kill() 117 | self.p = None 118 | 119 | if len(err) > 0: 120 | print('#### Errors:\n', err) 121 | 122 | # Strip sentinel commands from the log 123 | with open(self.log_file, 'r') as fh: 124 | fh.readline() # Toss out first line with sentinel proc definition 125 | clean_log = [ln for ln in fh if not ln.startswith('sentinel')] 126 | 127 | with open(self.log_file, 'w') as fh: 128 | fh.writelines(clean_log) 129 | 130 | def __del__(self): 131 | if self.p is not None: 132 | self.quit() 133 | 134 | 135 | --------------------------------------------------------------------------------