├── Basys-3 ├── Basys3_Master.xdc └── README.md ├── Cmod-A7 ├── Cmod-A7-Master.xdc └── README.md ├── DE0-CV ├── DE0_CV_golden_top.v ├── Full_Adder.vhd └── README.md ├── Genesys-ZU └── README.md ├── Intel └── README.md ├── Nexys-2 ├── Lab-1 │ ├── README.md │ ├── counter.vhd │ ├── hexcount.ucf │ ├── hexcount.vhd │ ├── leddec.ucf │ └── leddec.vhd ├── Lab-2 │ ├── README.md │ ├── counter.vhd │ ├── hexcount.ucf │ ├── hexcount.vhd │ └── leddec.vhd ├── Lab-3 │ ├── README.md │ ├── ball.vhd │ ├── vga_sync.vhd │ ├── vga_top.ucf │ └── vga_top.vhd ├── Lab-4 │ ├── README.md │ ├── hexcalc.ucf │ ├── hexcalc.vhd │ ├── keypad.vhd │ └── leddec16.vhd ├── Lab-5 │ ├── README.md │ ├── dac_if.vhd │ ├── siren.ucf │ ├── siren.vhd │ ├── tone.vhd │ └── wail.vhd ├── Lab-6 │ ├── README.md │ ├── adc_if.vhd │ ├── bat_n_ball.vhd │ ├── pong.ucf │ ├── pong.vhd │ └── vga_sync.vhd └── README.md ├── Nexys-4-DDR ├── Nexys-4-DDR-Master.xdc └── README.md ├── Nexys-A7 ├── Lab-1 │ ├── 7s.png │ ├── Modifications │ │ ├── README.md │ │ ├── leddec_1.vhd │ │ └── leddec_1.xdc │ ├── README.md │ ├── a7.png │ ├── cnt.png │ ├── counter.vhd │ ├── hexcount.vhd │ ├── hexcount.xdc │ ├── leddec.vhd │ └── leddec.xdc ├── Lab-2 │ ├── Modifications │ │ ├── README.md │ │ ├── counter_1.vhd │ │ ├── hexcount_1.vhd │ │ ├── hexcount_1.xdc │ │ └── leddec_1.vhd │ ├── README.md │ ├── counter.png │ ├── counter.vhd │ ├── hexcount.png │ ├── hexcount.vhd │ ├── hexcount.xdc │ ├── hexcounter.gif │ ├── leddec.vhd │ └── mpx.png ├── Lab-3 │ ├── Modifications │ │ ├── README.md │ │ └── ball_1.vhd │ ├── README.md │ ├── ball.vhd │ ├── clk_wiz_0.vhd │ ├── clk_wiz_0_clk_wiz.vhd │ ├── vga_sync.vhd │ ├── vga_top.vhd │ └── vga_top.xdc ├── Lab-4 │ ├── Modifications │ │ ├── README.md │ │ ├── hexcalc_1.vhd │ │ ├── hexcalc_1.xdc │ │ └── leddec16_1.vhd │ ├── README.md │ ├── hexcalc.png │ ├── hexcalc.vhd │ ├── hexcalc.xdc │ ├── keypad.vhd │ ├── kypd.png │ └── leddec16.vhd ├── Lab-5 │ ├── Modifications │ │ ├── README.md │ │ ├── siren_1.vhd │ │ ├── siren_1.xdc │ │ ├── tone_1.vhd │ │ └── wail_1.vhd │ ├── README.md │ ├── dac_if.vhd │ ├── i2s.png │ ├── i2s2.jpg │ ├── siren.vhd │ ├── siren.xdc │ ├── tone.vhd │ ├── wail.vhd │ └── wave.png ├── Lab-6 │ ├── Alternative │ │ ├── README.md │ │ ├── pong_2.vhd │ │ └── pong_2.xdc │ ├── Modifications │ │ ├── README.md │ │ ├── bat_n_ball_1.vhd │ │ ├── leddec16.vhd │ │ ├── pong_1.vhd │ │ └── pong_1.xdc │ ├── README.md │ ├── ad1.jpg │ ├── adc.png │ ├── adc_if.vhd │ ├── bat_n_ball.vhd │ ├── clk_wiz_0.vhd │ ├── clk_wiz_0_clk_wiz.vhd │ ├── knob.jpg │ ├── pong.vhd │ ├── pong.xdc │ ├── potentiometer.jpg │ └── vga_sync.vhd ├── Nexys-A7-100T-Master.xdc ├── Nexys-A7-50T-Master.xdc ├── README.md ├── install-1.png └── install-2.png ├── README.md ├── TinyFPGA-BX ├── README.md ├── boot.gif ├── sos.gif └── top.v ├── Xilinx ├── Genesys-ZU-5EV-D-Master.xdc ├── README.md ├── genesys-zu-5ev │ └── C.0 │ │ ├── board.xml │ │ ├── changelog.txt │ │ ├── part0_pins.xml │ │ └── preset.xml ├── zcu104.xdc ├── zcu106-hpc0.xdc ├── zcu106-hpc1.xdc └── zcu106_rev1.0_20180210.xdc ├── algorithms └── README.md ├── audio └── README.md ├── board_files └── README.md ├── chips └── README.md ├── circuit └── README.md ├── code ├── README.md ├── fullAdder.v ├── fullAdder_tb.v ├── half_adder.v └── half_adder_tb.v ├── communications └── README.md ├── computing └── README.md ├── control └── README.md ├── dsp └── README.md ├── free_range_vhdl_2013.pdf ├── free_range_vhdl_2018.pdf ├── free_range_vhdl_2019.pdf ├── ghdl ├── README.md ├── adder.png ├── adder.vcd ├── adder.vhdl ├── adder_tb.vhdl ├── demux.png ├── demux.vcd ├── demux.vhdl ├── demux_tb.vhdl ├── dff.png ├── dff.vcd ├── dff.vhdl ├── dff_tb.vhdl ├── ha.png ├── ha.vcd ├── ha.vhdl ├── ha_tb.vhdl ├── hello.vhdl ├── mux.png ├── mux.vcd ├── mux.vhdl ├── mux_tb.vhdl ├── my_sys.vhd ├── sqrt8.out ├── sqrt8.vcd ├── sqrt8.vhdl ├── sr_ff.vcd ├── sr_ff.vhdl ├── sr_ff_tb.vhdl ├── tff.png ├── tff.vcd ├── tff.vhdl └── tff_tb.vhdl ├── industry └── README.md ├── power └── README.md ├── projects └── README.md ├── smartsim ├── README.md ├── addition │ ├── 4 bit addition.ssc │ ├── 4 bit addition.ssp │ ├── full adder.ssc │ └── half adder.ssc ├── division │ ├── 2 to 1.ssc │ ├── 3 bit up counter.ssc │ ├── 8 bit 2 to 1.ssc │ ├── 8 bit addition using full adder.ssc │ ├── 8 bit d flipflop array.ssc │ ├── divider.ssc │ ├── division.ssc │ ├── division.ssp │ ├── full adder.ssc │ └── up count bit.ssc ├── division_b │ ├── 3-bit down-counter with load (DCNT3L).ssc │ ├── 8-bit adder (ADD8).ssc │ ├── 8-bit divider (DIV8).ssc │ ├── 8-bit divider circuit.ssp │ ├── 8-bit divider test circuit.ssc │ ├── 8-bit register (REG8).ssc │ ├── 8-bit select or clear (SELCLR8).ssc │ ├── 8-bit shift register (SHIFT8).ssc │ ├── 8-bit synchronous up-counter with enable (CNTR8).ssc │ ├── D flip-flop with clear and preset (DFFCP).ssc │ ├── Delay (DLY).ssc │ ├── Divider FSM control logic (DIVFSM).ssc │ ├── Full-adder (FA).ssc │ └── T flip-flop with preset (TFFP).ssc ├── flipflops │ ├── flipflops.ssc │ ├── flipflops.ssp │ ├── gated d latch.ssc │ ├── jk flipflop.ssc │ ├── pe d flipflop.ssc │ └── sr nor latch.ssc └── sbn oisc │ ├── 16 bit 2 to 1.ssc │ ├── 16 bit addition using full adder.ssc │ ├── 16 bit bidirectional controller.ssc │ ├── 16 bit d flipflop array.ssc │ ├── 16 bit tristate.ssc │ ├── 16 state selector.ssc │ ├── bidirectional controller.ssc │ ├── computer.ssc │ ├── delay 2.ssc │ ├── full adder.ssc │ ├── half adder.ssc │ ├── memory controller fsm.ssc │ ├── memory controller.ssc │ ├── processor fsm.ssc │ ├── processor.ssc │ ├── programs │ ├── count11.bin │ └── fibonacci.bin │ ├── readme.txt │ ├── sbn oisc.ssp │ ├── state selector bit.ssc │ └── up set counter 16.ssc ├── standards └── README.md ├── tools └── README.md └── video └── README.md /Basys-3/README.md: -------------------------------------------------------------------------------- 1 | # NI Digilent Basys 3 Artix-7 FPGA Trainer Board 2 | 3 | * The [Basys 3](https://digilent.com/shop/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/) is an entry-level development board built around a Xilinx Artix-7 FPGA 4 | * Xilinx Design Constraints ([XDC](https://github.com/Digilent/digilent-xdc)) 5 | * [FPGA Based Motor Control](https://www.hackster.io/adam-taylor/fpga-based-motor-control-cd47e7) by [Adam Taylor](https://www.hackster.io/adam-taylor) 6 | -------------------------------------------------------------------------------- /Cmod-A7/README.md: -------------------------------------------------------------------------------- 1 | # NI Digilent Cmod A7-35T Breadboardable Artix-7 FPGA Module 2 | 3 | * The Digilent Carrier Module [Cmod A7-35T](https://digilent.com/shop/cmod-a7-35t-breadboardable-artix-7-fpga-module/) is a 48-pin [dual in-line](https://en.wikipedia.org/wiki/Dual_in-line_package) (DIP) [form factor](https://en.wikipedia.org/wiki/Form_factor_(design)) board built around a Xilinx Artix-7 FPGA that brings FPGA power and prototyping to a solderless [breadboard](https://en.wikipedia.org/wiki/Breadboard) 4 | * The [Cmod S7](https://digilent.com/shop/cmod-s7-breadboardable-spartan-7-fpga-module/) is a 48-pin DIP form factor board, populated with 36 pins, built around a Xilinx Spartan-7 5 | * Xilinx Design Constraints ([XDC](https://github.com/Digilent/digilent-xdc)) 6 | -------------------------------------------------------------------------------- /DE0-CV/Full_Adder.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | 4 | Entity Full_Adder is 5 | PORT (a,b,carry_in: IN STD_LOGIC ; 6 | sum,carry_out: OUT STD_LOGIC ) ; 7 | END Full_Adder ; 8 | 9 | Architecture Add OF Full_Adder is 10 | 11 | Begin 12 | sum <= a XOR b XOR carry_in ; 13 | carry_out <= (a AND b) OR (carry_in AND a) OR (carry_in AND b) ; 14 | END Add ; 15 | -------------------------------------------------------------------------------- /Genesys-ZU/README.md: -------------------------------------------------------------------------------- 1 | # Genesys ZU 2 | * NI Digilent [Genesys ZU](https://digilent.com/reference/programmable-logic/genesys-zu/start) is a stand-alone [Zynq UltraScale+ MPSoC](https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html) development board 3 | * Download and extract [board files](https://github.com/Digilent/vivado-boards/archive/master.zip) 4 | * The ZIP file has a folder called new/board_files including a folder called [genesys-zu-5ev](https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys-zu-5ev/C.0) 5 | * [genesys-zu-5ev/C.0](/Xilinx/genesys-zu-5ev/C.0) 6 | * Digilent [XDC](https://github.com/Digilent/digilent-xdc) 7 | * [Master XDC file](https://github.com/Digilent/digilent-xdc/blob/master/Genesys-ZU-5EV-D-Master.xdc) 8 | * [Genesys-ZU-5EV-D-Master.xdc](/Xilinx/Genesys-ZU-5EV-D-Master.xdc) 9 | * [Resource center](https://digilent.com/reference/programmable-logic/genesys-zu/start) 10 | * [Repository](https://github.com/Digilent/genesys-zu) 11 | * [Getting started](https://digilent.com/reference/programmable-logic/genesys-zu/getting-started) 12 | * [Reference manual](https://digilent.com/reference/programmable-logic/genesys-zu/reference-manual) 13 | * [Creating a Genesys ZU Vitis Acceleration Platform](https://digilent.com/blog/creating-a-genesys-zu-vitis-acceleration-platform/) 14 | * [Adam Taylor](https://www.hackster.io/adam-taylor) 15 | * [Genesys ZU Vitis Accleration Platform](https://www.hackster.io/adam-taylor/genesys-zu-vitis-accleration-platform-2e86d4) 16 | * [Different memory types available within Xilinx FPGAs including UltraRAM](https://www.hackster.io/news/microzed-chronicles-ultraram-what-is-it-how-should-we-use-it-f73e1d1ebf85) 17 | * [Installing Vivado, Xilinx SDK, and Digilent Board Files](https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-sdk) 18 | * [Releases](https://github.com/Digilent/Genesys-ZU/releases) 19 | * [Example projects](https://digilent.com/reference/programmable-logic/genesys-zu/demos/start) 20 | * [HDMI demo](https://digilent.com/reference/programmable-logic/genesys-zu/demos/hdmi) 21 | * [Camera Serial Interface](https://en.wikipedia.org/wiki/Camera_Serial_Interface) (CSI) 22 | * [Getting Started with Vivado IP Integrator](https://digilent.com/reference/vivado/getting-started-with-ipi/start) 23 | * [Advanced Video Coding](https://en.wikipedia.org/wiki/Advanced_Video_Coding) (AVC or H.264) 24 | * [High Efficiency Video Coding](https://en.wikipedia.org/wiki/High_Efficiency_Video_Coding) (HEVC or H.265) 25 | * [Xilinx Zynq UltraScale+ MPSoC Video Codec Unit](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842546/Xilinx+Zynq+UltraScale+MPSoC+Video+Codec+Unit) 26 | * [Xilinx LogiCORE H.264/H.265 Video Codec Unit](https://www.xilinx.com/products/intellectual-property/v-vcu.html) 27 | * CAST [JPEG Image Compression](https://www.cast-inc.com/compression/jpeg-image-compression) 28 | * CAST [JPEG-EX-F](https://www.xilinx.com/products/intellectual-property/1-gfeqs7.html) 4K/8K JPEG encoder 29 | -------------------------------------------------------------------------------- /Intel/README.md: -------------------------------------------------------------------------------- 1 | # Intel FPGAs 2 | * [Altera](https://en.wikipedia.org/wiki/Altera) 3 | * [DE0-CV](/DE0-CV) 4 | * [Nios II](https://en.wikipedia.org/wiki/Nios_II) 5 | * [List of Intel FPGAs](https://www.intel.com/content/www/us/en/products/details/fpga.html) 6 | -------------------------------------------------------------------------------- /Nexys-2/Lab-1/README.md: -------------------------------------------------------------------------------- 1 | # Lab 1: Seven-Segment Decoder 2 | -------------------------------------------------------------------------------- /Nexys-2/Lab-1/counter.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY counter IS 6 | PORT ( 7 | clk : IN STD_LOGIC; 8 | count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 9 | ); 10 | END counter; 11 | 12 | ARCHITECTURE Behavioral OF counter IS 13 | SIGNAL cnt : STD_LOGIC_VECTOR (28 DOWNTO 0); -- 29 bit counter 14 | BEGIN 15 | PROCESS (clk) 16 | BEGIN 17 | IF clk'EVENT AND clk = '1' THEN -- on rising edge of clock 18 | cnt <= cnt + 1; -- increment counter 19 | END IF; 20 | END PROCESS; 21 | count <= cnt (28 DOWNTO 25); 22 | END Behavioral; 23 | -------------------------------------------------------------------------------- /Nexys-2/Lab-1/hexcount.ucf: -------------------------------------------------------------------------------- 1 | #FPGA I/O Pin Locations 2 | 3 | NET "clk_50MHz" LOC = B8; 4 | 5 | NET "seg[0]" LOC = H14; 6 | NET "seg[1]" LOC = J17; 7 | NET "seg[2]" LOC = G14; 8 | NET "seg[3]" LOC = D16; 9 | NET "seg[4]" LOC = D17; 10 | NET "seg[5]" LOC = F18; 11 | NET "seg[6]" LOC = L18; 12 | 13 | NET "anode[0]" LOC = F17; 14 | NET "anode[1]" LOC = H17; 15 | NET "anode[2]" LOC = C18; 16 | NET "anode[3]" LOC = F15; 17 | -------------------------------------------------------------------------------- /Nexys-2/Lab-1/hexcount.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY hexcount IS 5 | PORT ( 6 | clk_50MHz : IN STD_LOGIC; 7 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 9 | ); 10 | END hexcount; 11 | 12 | ARCHITECTURE Behavioral OF hexcount IS 13 | COMPONENT counter IS 14 | PORT ( 15 | clk : IN STD_LOGIC; 16 | count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 17 | ); 18 | END COMPONENT; 19 | COMPONENT leddec IS 20 | PORT ( 21 | dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 22 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 23 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 24 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 25 | ); 26 | END COMPONENT; 27 | SIGNAL S : STD_LOGIC_VECTOR (3 DOWNTO 0); 28 | BEGIN 29 | C1 : counter 30 | PORT MAP(clk => clk_50MHz, count => S); 31 | L1 : leddec 32 | PORT MAP(dig => "00", data => S, anode => anode, seg => seg); 33 | END Behavioral; 34 | -------------------------------------------------------------------------------- /Nexys-2/Lab-1/leddec.ucf: -------------------------------------------------------------------------------- 1 | #FPGA I/O Pin Locations 2 | 3 | NET "data[0]" LOC = G18; 4 | NET "data[1]" LOC = H18; 5 | NET "data[2]" LOC = K18; 6 | NET "data[3]" LOC = K17; 7 | 8 | NET "dig[0]" LOC = N17; 9 | NET "dig[1]" LOC = R17; 10 | 11 | NET "seg[0]" LOC = H14; 12 | NET "seg[1]" LOC = J17; 13 | NET "seg[2]" LOC = G14; 14 | NET "seg[3]" LOC = D16; 15 | NET "seg[4]" LOC = D17; 16 | NET "seg[5]" LOC = F18; 17 | NET "seg[6]" LOC = L18; 18 | 19 | NET "anode[0]" LOC = F17; 20 | NET "anode[1]" LOC = H17; 21 | NET "anode[2]" LOC = C18; 22 | NET "anode[3]" LOC = F15; 23 | -------------------------------------------------------------------------------- /Nexys-2/Lab-1/leddec.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 7 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 10 | ); 11 | END leddec; 12 | 13 | ARCHITECTURE Behavioral OF leddec IS 14 | BEGIN 15 | -- Turn on segments corresponding to 4-bit data word 16 | seg <= "0000001" WHEN data = "0000" ELSE --0 17 | "1001111" WHEN data = "0001" ELSE --1 18 | "0010010" WHEN data = "0010" ELSE --2 19 | "0000110" WHEN data = "0011" ELSE --3 20 | "1001100" WHEN data = "0100" ELSE --4 21 | "0100100" WHEN data = "0101" ELSE --5 22 | "0100000" WHEN data = "0110" ELSE --6 23 | "0001111" WHEN data = "0111" ELSE --7 24 | "0000000" WHEN data = "1000" ELSE --8 25 | "0000100" WHEN data = "1001" ELSE --9 26 | "0001000" WHEN data = "1010" ELSE --A 27 | "1100000" WHEN data = "1011" ELSE --B 28 | "0110001" WHEN data = "1100" ELSE --C 29 | "1000010" WHEN data = "1101" ELSE --D 30 | "0110000" WHEN data = "1110" ELSE --E 31 | "0111000" WHEN data = "1111" ELSE --F 32 | "1111111"; 33 | -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig 34 | anode <= "1110" WHEN dig = "00" ELSE --0 35 | "1101" WHEN dig = "01" ELSE --1 36 | "1011" WHEN dig = "10" ELSE --2 37 | "0111" WHEN dig = "11" ELSE --3 38 | "1111"; 39 | END Behavioral; 40 | -------------------------------------------------------------------------------- /Nexys-2/Lab-2/README.md: -------------------------------------------------------------------------------- 1 | # Lab 2: Four-Digit Hex Counter 2 | -------------------------------------------------------------------------------- /Nexys-2/Lab-2/counter.vhd: -------------------------------------------------------------------------------- 1 | -- counter.vhd -- 2 | 3 | LIBRARY IEEE; 4 | USE IEEE.STD_LOGIC_1164.ALL; 5 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | 7 | ENTITY counter IS 8 | PORT ( 9 | clk : IN STD_LOGIC; 10 | count : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); --NEED REVISE! 16 bits 11 | mpx : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)); --NEW ONE ADD! send signal to select displays 12 | END counter; 13 | 14 | ARCHITECTURE Behavioral OF counter IS 15 | SIGNAL cnt : STD_LOGIC_VECTOR (38 DOWNTO 0); -- 39 bit counter 16 | BEGIN 17 | PROCESS (clk) 18 | BEGIN 19 | IF clk'EVENT AND clk = '1' THEN -- on rising edge of clock 20 | cnt <= cnt + 1; -- increment counter 21 | END IF; 22 | END PROCESS; 23 | count <= cnt (38 DOWNTO 23); -- 16bits 24 | mpx <= cnt (18 DOWNTO 17); -- 2bits 25 | END Behavioral; 26 | -------------------------------------------------------------------------------- /Nexys-2/Lab-2/hexcount.ucf: -------------------------------------------------------------------------------- 1 | # FPGA I/O Pin Locations 2 | 3 | NET "clk_50MHz" LOC = B8; 4 | 5 | NET "seg[0]" LOC = H14; 6 | NET "seg[1]" LOC = J17; 7 | NET "seg[2]" LOC = G14; 8 | NET "seg[3]" LOC = D16; 9 | NET "seg[4]" LOC = D17; 10 | NET "seg[5]" LOC = F18; 11 | NET "seg[6]" LOC = L18; 12 | 13 | NET "anode[0]" LOC = F17; 14 | NET "anode[1]" LOC = H17; 15 | NET "anode[2]" LOC = C18; 16 | NET "anode[3]" LOC = F15; 17 | -------------------------------------------------------------------------------- /Nexys-2/Lab-2/hexcount.vhd: -------------------------------------------------------------------------------- 1 | -- hexcount.vhd -- 2 | 3 | LIBRARY IEEE; 4 | USE IEEE.STD_LOGIC_1164.ALL; 5 | 6 | ENTITY hexcount IS 7 | PORT ( 8 | clk_50MHz : IN STD_LOGIC; 9 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 10 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 11 | ); 12 | END hexcount; 13 | 14 | ARCHITECTURE Behavioral OF hexcount IS 15 | 16 | COMPONENT counter IS 17 | PORT ( 18 | clk : IN STD_LOGIC; 19 | count : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); --NEED CHANGE! counter now output 16 bits for all 4 displays 20 | mpx : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) 21 | ); 22 | END COMPONENT; 23 | 24 | COMPONENT leddec IS 25 | PORT ( 26 | dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 27 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); --DONT change, data is fixed 4 bits in leddec for each displays 28 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 29 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 30 | ); 31 | END COMPONENT; 32 | 33 | SIGNAL S : STD_LOGIC_VECTOR (15 DOWNTO 0); -- connect C1 and L1 for values of 4 digits 34 | SIGNAL md : STD_LOGIC_VECTOR (1 DOWNTO 0); -- mpx selects displays 35 | SIGNAL display : STD_LOGIC_VECTOR (3 DOWNTO 0); -- send digit for only one display to leddec 36 | 37 | BEGIN 38 | C1 : counter 39 | PORT MAP(clk => clk_50MHz, count => S, mpx => md); 40 | L1 : leddec 41 | PORT MAP(dig => md, data => display, anode => anode, seg => seg); 42 | --mpx 43 | --process(md) 44 | --begin 45 | -- if md = "00" then 46 | -- display <= S(3 downto 0); 47 | -- elsif md = "01" then 48 | -- display <= S(7 downto 4); 49 | -- elsif md = "10" then 50 | -- display <= S(11 downto 8); 51 | -- elsif md = "11" then 52 | -- display <= S(15 downto 12); 53 | -- end if; 54 | --end process; 55 | 56 | display <= S(3 DOWNTO 0) WHEN md = "00" ELSE 57 | S(7 DOWNTO 4) WHEN md = "01" ELSE 58 | S(11 DOWNTO 8) WHEN md = "10" ELSE 59 | S(15 DOWNTO 12); 60 | 61 | END Behavioral; 62 | -------------------------------------------------------------------------------- /Nexys-2/Lab-2/leddec.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 7 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 10 | ); 11 | END leddec; 12 | 13 | ARCHITECTURE Behavioral OF leddec IS 14 | BEGIN 15 | -- Turn on segments corresponding to 4-bit data word 16 | seg <= "0000001" WHEN data = "0000" ELSE --0 17 | "1001111" WHEN data = "0001" ELSE --1 18 | "0010010" WHEN data = "0010" ELSE --2 19 | "0000110" WHEN data = "0011" ELSE --3 20 | "1001100" WHEN data = "0100" ELSE --4 21 | "0100100" WHEN data = "0101" ELSE --5 22 | "0100000" WHEN data = "0110" ELSE --6 23 | "0001111" WHEN data = "0111" ELSE --7 24 | "0000000" WHEN data = "1000" ELSE --8 25 | "0000100" WHEN data = "1001" ELSE --9 26 | "0001000" WHEN data = "1010" ELSE --A 27 | "1100000" WHEN data = "1011" ELSE --B 28 | "0110001" WHEN data = "1100" ELSE --C 29 | "1000010" WHEN data = "1101" ELSE --D 30 | "0110000" WHEN data = "1110" ELSE --E 31 | "0111000" WHEN data = "1111" ELSE --F 32 | "1111111"; 33 | -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig 34 | anode <= "1110" WHEN dig = "00" ELSE --0 35 | "1101" WHEN dig = "01" ELSE --1 36 | "1011" WHEN dig = "10" ELSE --2 37 | "0111" WHEN dig = "11" ELSE --3 38 | "1111"; 39 | END Behavioral; 40 | -------------------------------------------------------------------------------- /Nexys-2/Lab-3/README.md: -------------------------------------------------------------------------------- 1 | # Lab 3: Bouncing Ball I 2 | 3 | VGA display 4 | -------------------------------------------------------------------------------- /Nexys-2/Lab-3/ball.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_ARITH.ALL; 4 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | ENTITY ball IS 7 | PORT ( 8 | v_sync : IN STD_LOGIC; 9 | pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 10 | pixel_col : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 11 | red : OUT STD_LOGIC; 12 | green : OUT STD_LOGIC; 13 | blue : OUT STD_LOGIC 14 | ); 15 | END ball; 16 | 17 | ARCHITECTURE Behavioral OF ball IS 18 | CONSTANT size : INTEGER := 8; 19 | SIGNAL ball_on : STD_LOGIC; -- indicates whether ball is over current pixel position 20 | -- current ball position - intitialized to center of screen 21 | SIGNAL ball_x : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(320, 10); 22 | SIGNAL ball_y : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(240, 10); 23 | -- current ball motion - initialized to +4 pixels/frame 24 | SIGNAL ball_y_motion : STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000100"; 25 | BEGIN 26 | red <= '1'; -- color setup for red ball on white background 27 | green <= NOT ball_on; 28 | blue <= NOT ball_on; 29 | -- process to draw ball current pixel address is covered by ball position 30 | bdraw : PROCESS (ball_x, ball_y, pixel_row, pixel_col) IS 31 | BEGIN 32 | IF (pixel_col >= ball_x - size) AND 33 | (pixel_col <= ball_x + size) AND 34 | (pixel_row >= ball_y - size) AND 35 | (pixel_row <= ball_y + size) THEN 36 | ball_on <= '1'; 37 | ELSE 38 | ball_on <= '0'; 39 | END IF; 40 | END PROCESS; 41 | -- process to move ball once every frame (i.e. once every vsync pulse) 42 | mball : PROCESS 43 | BEGIN 44 | WAIT UNTIL rising_edge(v_sync); 45 | -- allow for bounce off top or bottom of screen 46 | IF ball_y + size >= 480 THEN 47 | ball_y_motion <= "1111111100"; -- -4 pixels 48 | ELSIF ball_y <= size THEN 49 | ball_y_motion <= "0000000100"; -- +4 pixels 50 | END IF; 51 | ball_y <= ball_y + ball_y_motion; -- compute next ball position 52 | END PROCESS; 53 | END Behavioral; 54 | -------------------------------------------------------------------------------- /Nexys-2/Lab-3/vga_sync.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY vga_sync IS 6 | PORT ( 7 | clock_25MHz : IN STD_LOGIC; 8 | red : IN STD_LOGIC; 9 | green : IN STD_LOGIC; 10 | blue : IN STD_LOGIC; 11 | red_out : OUT STD_LOGIC; 12 | green_out : OUT STD_LOGIC; 13 | blue_out : OUT STD_LOGIC; 14 | hsync : OUT STD_LOGIC; 15 | vsync : OUT STD_LOGIC; 16 | pixel_row : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); 17 | pixel_col : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 18 | ); 19 | END vga_sync; 20 | 21 | ARCHITECTURE Behavioral OF vga_sync IS 22 | SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (9 DOWNTO 0); 23 | BEGIN 24 | sync_pr : PROCESS 25 | VARIABLE video_on : STD_LOGIC; 26 | BEGIN 27 | WAIT UNTIL rising_edge(clock_25MHz); 28 | -- Generate Horizontal Timing Signals for Video Signal 29 | -- h_cnt counts pixels across line (800 total = 640 active + extras for sync and blanking) 30 | -- Active picture for 0 <= h_cnt <= 639 31 | -- Hsync for 659 <= h_cnt <= 755 32 | IF h_cnt >= 799 THEN 33 | h_cnt <= "0000000000"; 34 | ELSE 35 | h_cnt <= h_cnt + 1; 36 | END IF; 37 | IF (h_cnt >= 659) AND (h_cnt <= 755) THEN 38 | hsync <= '0'; 39 | ELSE 40 | hsync <= '1'; 41 | END IF; 42 | -- Generate Vertical Timing Signals for Video Signal 43 | -- v_cnt counts lines down screen (525 total = 480 active + extras for sync and blanking) 44 | -- Active picture for 0 <= v_cnt <= 479 45 | -- Vsync for 493 <= h_cnt <= 494 46 | IF (v_cnt >= 524) AND (h_cnt = 699) THEN 47 | v_cnt <= "0000000000"; 48 | ELSIF h_cnt = 699 THEN 49 | v_cnt <= v_cnt + 1; 50 | END IF; 51 | IF (v_cnt >= 493) AND (v_cnt <= 494) THEN 52 | vsync <= '0'; 53 | ELSE 54 | vsync <= '1'; 55 | END IF; 56 | -- Generate Video Signals and Pixel Address 57 | IF (h_cnt <= 639) AND (v_cnt <= 479) THEN 58 | video_on := '1'; 59 | ELSE 60 | video_on := '0'; 61 | END IF; 62 | pixel_col <= h_cnt; 63 | pixel_row <= v_cnt; 64 | -- Register video to clock edge and suppress video during blanking and sync periods 65 | red_out <= red AND video_on; 66 | green_out <= green AND video_on; 67 | blue_out <= blue AND video_on; 68 | END PROCESS; 69 | END Behavioral; 70 | -------------------------------------------------------------------------------- /Nexys-2/Lab-3/vga_top.ucf: -------------------------------------------------------------------------------- 1 | NET "clk_50MHz" LOC = B8; 2 | 3 | NET "vga_hsync" LOC = T4; 4 | NET "vga_vsync" LOC = U3; 5 | 6 | NET "vga_red[0]" LOC = R9; 7 | NET "vga_red[1]" LOC = T8; 8 | NET "vga_red[2]" LOC = R8; 9 | NET "vga_green[0]" LOC = N8; 10 | NET "vga_green[1]" LOC = P8; 11 | NET "vga_green[2]" LOC = P6; 12 | NET "vga_blue[0]" LOC = U5; 13 | NET "vga_blue[1]" LOC = U4; 14 | 15 | NET "ck_25" TNM_NET = ck_25_net; 16 | TIMESPEC TS_ck_25 = PERIOD "ck_25_net" 40 ns HIGH 50%; 17 | -------------------------------------------------------------------------------- /Nexys-2/Lab-3/vga_top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY vga_top IS 6 | PORT ( 7 | clk_50MHz : IN STD_LOGIC; 8 | vga_red : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); 9 | vga_green : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); 10 | vga_blue : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); 11 | vga_hsync : OUT STD_LOGIC; 12 | vga_vsync : OUT STD_LOGIC 13 | ); 14 | END vga_top; 15 | 16 | ARCHITECTURE Behavioral OF vga_top IS 17 | SIGNAL ck_25 : STD_LOGIC; 18 | -- internal signals to connect modules 19 | SIGNAL S_red, S_green, S_blue : STD_LOGIC; 20 | SIGNAL S_vsync : STD_LOGIC; 21 | SIGNAL S_pixel_row, S_pixel_col : STD_LOGIC_VECTOR (9 DOWNTO 0); 22 | COMPONENT ball IS 23 | PORT ( 24 | v_sync : IN STD_LOGIC; 25 | pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 26 | pixel_col : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 27 | red : OUT STD_LOGIC; 28 | green : OUT STD_LOGIC; 29 | blue : OUT STD_LOGIC 30 | ); 31 | END COMPONENT; 32 | COMPONENT vga_sync IS 33 | PORT ( 34 | clock_25MHz : IN STD_LOGIC; 35 | red : IN STD_LOGIC; 36 | green : IN STD_LOGIC; 37 | blue : IN STD_LOGIC; 38 | red_out : OUT STD_LOGIC; 39 | green_out : OUT STD_LOGIC; 40 | blue_out : OUT STD_LOGIC; 41 | hsync : OUT STD_LOGIC; 42 | vsync : OUT STD_LOGIC; 43 | pixel_row : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); 44 | pixel_col : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 45 | ); 46 | END COMPONENT; 47 | BEGIN 48 | -- Process to generate 25 MHz clock from 50 MHz system clock 49 | ckp : PROCESS 50 | BEGIN 51 | WAIT UNTIL rising_edge(clk_50MHz); 52 | ck_25 <= NOT ck_25; 53 | END PROCESS; 54 | -- vga_driver only drives MSB of red, green & blue 55 | -- so set other bits to zero 56 | vga_red(1 DOWNTO 0) <= "00"; 57 | vga_green(1 DOWNTO 0) <= "00"; 58 | vga_blue(0) <= '0'; 59 | add_ball : ball 60 | PORT MAP(--instantiate ball component 61 | v_sync => S_vsync, 62 | pixel_row => S_pixel_row, 63 | pixel_col => S_pixel_col, 64 | red => S_red, 65 | green => S_green, 66 | blue => S_blue 67 | ); 68 | vga_driver : vga_sync 69 | PORT MAP(--instantiate vga_sync component 70 | clock_25MHz => ck_25, 71 | red => S_red, 72 | green => S_green, 73 | blue => S_blue, 74 | red_out => vga_red(2), 75 | green_out => vga_green(2), 76 | blue_out => vga_blue(1), 77 | pixel_row => S_pixel_row, 78 | pixel_col => S_pixel_col, 79 | hsync => vga_hsync, 80 | vsync => S_vsync 81 | ); 82 | vga_vsync <= S_vsync; --connect output vsync 83 | END Behavioral; 84 | -------------------------------------------------------------------------------- /Nexys-2/Lab-4/README.md: -------------------------------------------------------------------------------- 1 | # Lab 4: Hex Calculator 2 | 3 | Pmod KYPD 4 | -------------------------------------------------------------------------------- /Nexys-2/Lab-4/hexcalc.ucf: -------------------------------------------------------------------------------- 1 | NET "clk_50MHz" LOC = B8; 2 | 3 | NET "KB_col(1)" LOC = M15; 4 | NET "KB_col(2)" LOC = L17; 5 | NET "KB_col(3)" LOC = K12; 6 | NET "KB_col(4)" LOC = L15; 7 | 8 | NET "KB_row(1)" LOC = M16; 9 | NET "KB_row(2)" LOC = M14; 10 | NET "KB_row(3)" LOC = L16; 11 | NET "KB_row(4)" LOC = K13; 12 | 13 | NET "bt_clr" LOC = H13; # BTN3 14 | NET "bt_plus" LOC = B18; # BTN0 15 | NET "bt_eq" LOC = D18; # BTN1 16 | 17 | NET "SEG7_seg[0]" LOC = H14; 18 | NET "SEG7_seg[1]" LOC = J17; 19 | NET "SEG7_seg[2]" LOC = G14; 20 | NET "SEG7_seg[3]" LOC = D16; 21 | NET "SEG7_seg[4]" LOC = D17; 22 | NET "SEG7_seg[5]" LOC = F18; 23 | NET "SEG7_seg[6]" LOC = L18; 24 | 25 | NET "SEG7_anode[0]" LOC = F17; 26 | NET "SEG7_anode[1]" LOC = H17; 27 | NET "SEG7_anode[2]" LOC = C18; 28 | NET "SEG7_anode[3]" LOC = F15; 29 | -------------------------------------------------------------------------------- /Nexys-2/Lab-4/keypad.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY keypad IS 5 | PORT ( 6 | samp_ck : IN STD_LOGIC; -- clock to strobe columns 7 | col : OUT STD_LOGIC_VECTOR (4 DOWNTO 1); -- output column lines 8 | row : IN STD_LOGIC_VECTOR (4 DOWNTO 1); -- input row lines 9 | value : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- hex value of key depressed 10 | hit : OUT STD_LOGIC); -- indicates when a key has been pressed 11 | END keypad; 12 | 13 | ARCHITECTURE Behavioral OF keypad IS 14 | SIGNAL CV1, CV2, CV3, CV4 : std_logic_vector (4 DOWNTO 1) := "1111"; -- column vector of each row 15 | SIGNAL curr_col : std_logic_vector (4 DOWNTO 1) := "1110"; -- current column code 16 | BEGIN 17 | -- This process synchronously tests the state of the keypad buttons. On each edge of samp_ck, 18 | -- this module outputs a column code to the keypad in which one column line is held low while the 19 | -- other three column lines are held high. The row outputs of that column are then read 20 | -- into the corresponding column vector. The current column is then updated ready for the next 21 | -- clock edge. Remember that curr_col is not updated until the process suspends. 22 | strobe_proc : PROCESS 23 | BEGIN 24 | WAIT UNTIL rising_edge(samp_ck); 25 | CASE curr_col IS 26 | WHEN "1110" => 27 | CV1 <= row; 28 | curr_col <= "1101"; 29 | WHEN "1101" => 30 | CV2 <= row; 31 | curr_col <= "1011"; 32 | WHEN "1011" => 33 | CV3 <= row; 34 | curr_col <= "0111"; 35 | WHEN "0111" => 36 | CV4 <= row; 37 | curr_col <= "1110"; 38 | WHEN OTHERS => 39 | curr_col <= "1110"; 40 | END CASE; 41 | END PROCESS; 42 | -- This process runs whenever any of the column vectors change. Each vector is tested to see 43 | -- if there are any '0's in the vector. This would indicate that a button had been pushed in 44 | -- that column. If so, the value of the button is output and the hit signal is assereted. If 45 | -- not button is pushed, the hit signal is cleared 46 | out_proc : PROCESS (CV1, CV2, CV3, CV4) 47 | BEGIN 48 | hit <= '1'; 49 | IF CV1(1) = '0' THEN 50 | value <= X"1"; 51 | ELSIF CV1(2) = '0' THEN 52 | value <= X"4"; 53 | ELSIF CV1(3) = '0' THEN 54 | value <= X"7"; 55 | ELSIF CV1(4) = '0' THEN 56 | value <= X"0"; 57 | ELSIF CV2(1) = '0' THEN 58 | value <= X"2"; 59 | ELSIF CV2(2) = '0' THEN 60 | value <= X"5"; 61 | ELSIF CV2(3) = '0' THEN 62 | value <= X"8"; 63 | ELSIF CV2(4) = '0' THEN 64 | value <= X"F"; 65 | ELSIF CV3(1) = '0' THEN 66 | value <= X"3"; 67 | ELSIF CV3(2) = '0' THEN 68 | value <= X"6"; 69 | ELSIF CV3(3) = '0' THEN 70 | value <= X"9"; 71 | ELSIF CV3(4) = '0' THEN 72 | value <= X"E"; 73 | ELSIF CV4(1) = '0' THEN 74 | value <= X"A"; 75 | ELSIF CV4(2) = '0' THEN 76 | value <= X"B"; 77 | ELSIF CV4(3) = '0' THEN 78 | value <= X"C"; 79 | ELSIF CV4(4) = '0' THEN 80 | value <= X"D"; 81 | ELSE 82 | hit <= '0'; 83 | value <= X"0"; 84 | END IF; 85 | END PROCESS; 86 | col <= curr_col; 87 | END Behavioral; 88 | -------------------------------------------------------------------------------- /Nexys-2/Lab-4/leddec16.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec16 IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- which digit to currently display 7 | data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit (4-digit) data 8 | anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- which anode to turn on 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- segment code for current digit 10 | END leddec16; 11 | 12 | ARCHITECTURE Behavioral OF leddec16 IS 13 | SIGNAL data4 : STD_LOGIC_VECTOR (3 DOWNTO 0); -- binary value of current digit 14 | BEGIN 15 | -- Select digit data to be displayed in this mpx period 16 | data4 <= data(3 DOWNTO 0) WHEN dig = "00" ELSE --digit 0 17 | data(7 DOWNTO 4) WHEN dig = "01" ELSE --digit 1 18 | data(11 DOWNTO 8) WHEN dig = "10" ELSE --digit 2 19 | data(15 DOWNTO 12); --digit 3 20 | -- Turn on segments corresponding to 4-bit data word 21 | seg <= "0000001" WHEN data4 = "0000" ELSE --0 22 | "1001111" WHEN data4 = "0001" ELSE --1 23 | "0010010" WHEN data4 = "0010" ELSE --2 24 | "0000110" WHEN data4 = "0011" ELSE --3 25 | "1001100" WHEN data4 = "0100" ELSE --4 26 | "0100100" WHEN data4 = "0101" ELSE --5 27 | "0100000" WHEN data4 = "0110" ELSE --6 28 | "0001111" WHEN data4 = "0111" ELSE --7 29 | "0000000" WHEN data4 = "1000" ELSE --8 30 | "0000100" WHEN data4 = "1001" ELSE --9 31 | "0001000" WHEN data4 = "1010" ELSE --A 32 | "1100000" WHEN data4 = "1011" ELSE --B 33 | "0110001" WHEN data4 = "1100" ELSE --C 34 | "1000010" WHEN data4 = "1101" ELSE --D 35 | "0110000" WHEN data4 = "1110" ELSE --E 36 | "0111000" WHEN data4 = "1111" ELSE --F 37 | "1111111"; 38 | -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig 39 | anode <= "1110" WHEN dig = "00" ELSE -- digit 0 40 | "1101" WHEN dig = "01" ELSE -- digit 1 41 | "1011" WHEN dig = "10" ELSE -- digit 2 42 | "0111" WHEN dig = "11" ELSE -- digit 3 43 | "1111"; 44 | END Behavioral; 45 | -------------------------------------------------------------------------------- /Nexys-2/Lab-5/README.md: -------------------------------------------------------------------------------- 1 | # Lab 5: DAC Siren 2 | 3 | Pmod I2S and headphone 4 | -------------------------------------------------------------------------------- /Nexys-2/Lab-5/dac_if.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | ENTITY dac_if IS 6 | PORT ( 7 | SCLK : IN STD_LOGIC; -- serial clock (1.56 MHz) 8 | L_start : IN STD_LOGIC; -- strobe to load LEFT data 9 | R_start : IN STD_LOGIC; -- strobe to load RIGHT data 10 | L_data : IN SIGNED (15 DOWNTO 0); -- LEFT data (15-bit signed) 11 | R_data : IN SIGNED (15 DOWNTO 0); -- RIGHT data (15-bit signed) 12 | SDATA : OUT STD_LOGIC); -- serial data stream to DAC 13 | END dac_if; 14 | 15 | ARCHITECTURE Behavioral OF dac_if IS 16 | SIGNAL sreg : STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit shift register to do 17 | -- parallel to serial conversion 18 | BEGIN 19 | -- SREG is used to serially shift data out to DAC, MSBit first. 20 | -- Left data is loaded into SREG on falling edge of SCLK when L_start is active. 21 | -- Right data is loaded into SREG on falling edge of SCLK when R_start is active. 22 | -- At other times, falling edge of SCLK causes REG to logically shift one bit left 23 | -- Serial data to DAC is MSBit of SREG 24 | dac_proc : PROCESS 25 | BEGIN 26 | WAIT UNTIL falling_edge(SCLK); 27 | IF L_start = '1' THEN 28 | sreg <= std_logic_vector (L_data); -- load LEFT data into SREG 29 | ELSIF R_start = '1' THEN 30 | sreg <= std_logic_vector (R_data); -- load RIGHT data into SREG 31 | ELSE 32 | sreg <= sreg(14 DOWNTO 0) & '0'; -- logically shift SREG one bit left 33 | END IF; 34 | END PROCESS; 35 | SDATA <= sreg(15); -- serial data to DAC is MSBit of SREG 36 | END Behavioral; 37 | -------------------------------------------------------------------------------- /Nexys-2/Lab-5/siren.ucf: -------------------------------------------------------------------------------- 1 | NET "clk_50MHZ" LOC = B8; 2 | 3 | NET "dac_SDIN" LOC = M15; 4 | NET "dac_SCLK" LOC = L17; 5 | NET "dac_LRCK" LOC = K12; 6 | NET "dac_MCLK" LOC = L15; 7 | 8 | NET "clk_50MHZ" TNM_NET = ck_50_net; 9 | TIMESPEC TS_ck_50 = PERIOD "ck_50_net" 20 ns HIGH 50%; 10 | -------------------------------------------------------------------------------- /Nexys-2/Lab-5/siren.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | ENTITY siren IS 6 | PORT ( 7 | clk_50MHz : IN STD_LOGIC; -- system clock (50 MHz) 8 | dac_MCLK : OUT STD_LOGIC; -- outputs to PMODI2L DAC 9 | dac_LRCK : OUT STD_LOGIC; 10 | dac_SCLK : OUT STD_LOGIC; 11 | dac_SDIN : OUT STD_LOGIC 12 | ); 13 | END siren; 14 | 15 | ARCHITECTURE Behavioral OF siren IS 16 | CONSTANT lo_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (344, 14); -- lower limit of siren = 256 Hz 17 | CONSTANT hi_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (687, 14); -- upper limit of siren = 512 Hz 18 | CONSTANT wail_speed : UNSIGNED (7 DOWNTO 0) := to_unsigned (8, 8); -- sets wailing speed 19 | COMPONENT dac_if IS 20 | PORT ( 21 | SCLK : IN STD_LOGIC; 22 | L_start : IN STD_LOGIC; 23 | R_start : IN STD_LOGIC; 24 | L_data : IN signed (15 DOWNTO 0); 25 | R_data : IN signed (15 DOWNTO 0); 26 | SDATA : OUT STD_LOGIC 27 | ); 28 | END COMPONENT; 29 | COMPONENT wail IS 30 | PORT ( 31 | lo_pitch : IN UNSIGNED (13 DOWNTO 0); 32 | hi_pitch : IN UNSIGNED (13 DOWNTO 0); 33 | wspeed : IN UNSIGNED (7 DOWNTO 0); 34 | wclk : IN STD_LOGIC; 35 | audio_clk : IN STD_LOGIC; 36 | audio_data : OUT SIGNED (15 DOWNTO 0) 37 | ); 38 | END COMPONENT; 39 | SIGNAL tcount : unsigned (19 DOWNTO 0) := (OTHERS => '0'); -- timing counter 40 | SIGNAL data_L, data_R : SIGNED (15 DOWNTO 0); -- 16-bit signed audio data 41 | SIGNAL dac_load_L, dac_load_R : STD_LOGIC; -- timing pulses to load DAC shift reg. 42 | SIGNAL slo_clk, sclk, audio_CLK : STD_LOGIC; 43 | BEGIN 44 | -- this process sets up a 20 bit binary counter clocked at 50MHz. This is used 45 | -- to generate all necessary timing signals. dac_load_L and dac_load_R are pulses 46 | -- sent to dac_if to load parallel data into shift register for serial clocking 47 | -- out to DAC 48 | tim_pr : PROCESS 49 | BEGIN 50 | WAIT UNTIL rising_edge(clk_50MHz); 51 | IF (tcount(9 DOWNTO 0) >= X"00F") AND (tcount(9 DOWNTO 0) < X"02E") THEN 52 | dac_load_L <= '1'; 53 | ELSE 54 | dac_load_L <= '0'; 55 | END IF; 56 | IF (tcount(9 DOWNTO 0) >= X"20F") AND (tcount(9 DOWNTO 0) < X"22E") THEN 57 | dac_load_R <= '1'; 58 | ELSE dac_load_R <= '0'; 59 | END IF; 60 | tcount <= tcount + 1; 61 | END PROCESS; 62 | dac_MCLK <= NOT tcount(1); -- DAC master clock (12.5 MHz) 63 | audio_CLK <= tcount(9); -- audio sampling rate (48.8 kHz) 64 | dac_LRCK <= audio_CLK; -- also sent to DAC as left/right clock 65 | sclk <= tcount(4); -- serial data clock (1.56 MHz) 66 | dac_SCLK <= sclk; -- also sent to DAC as SCLK 67 | slo_clk <= tcount(19); -- clock to control wailing of tone (47.6 Hz) 68 | dac : dac_if 69 | PORT MAP( 70 | SCLK => sclk, -- instantiate parallel to serial DAC interface 71 | L_start => dac_load_L, 72 | R_start => dac_load_R, 73 | L_data => data_L, 74 | R_data => data_R, 75 | SDATA => dac_SDIN 76 | ); 77 | w1 : wail 78 | PORT MAP( 79 | lo_pitch => lo_tone, -- instantiate wailing siren 80 | hi_pitch => hi_tone, 81 | wspeed => wail_speed, 82 | wclk => slo_clk, 83 | audio_clk => audio_clk, 84 | audio_data => data_L 85 | ); 86 | data_R <= data_L; -- duplicate data on right channel 87 | END Behavioral; 88 | -------------------------------------------------------------------------------- /Nexys-2/Lab-5/tone.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | -- Generates a 16-bit signed triangle wave sequence at a sampling rate determined 6 | -- by input clk and with a frequency of (clk*pitch)/65,536 7 | ENTITY tone IS 8 | PORT ( 9 | clk : IN STD_LOGIC; -- 48.8 kHz audio sampling clock 10 | pitch : IN UNSIGNED (13 DOWNTO 0); -- frequency (in units of 0.745 Hz) 11 | data : OUT SIGNED (15 DOWNTO 0)); -- signed triangle wave out 12 | END tone; 13 | 14 | ARCHITECTURE Behavioral OF tone IS 15 | SIGNAL count : unsigned (15 DOWNTO 0); -- represents current phase of waveform 16 | SIGNAL quad : std_logic_vector (1 DOWNTO 0); -- current quadrant of phase 17 | SIGNAL index : signed (15 DOWNTO 0); -- index into current quadrant 18 | BEGIN 19 | -- This process adds "pitch" to the current phase every sampling period. Generates 20 | -- an unsigned 16-bit sawtooth waveform. Frequency is determined by pitch. For 21 | -- example when pitch=1, then frequency will be 0.745 Hz. When pitch=16,384, frequency 22 | -- will be 12.2 kHz. 23 | cnt_pr : PROCESS 24 | BEGIN 25 | WAIT UNTIL rising_edge(clk); 26 | count <= count + pitch; 27 | END PROCESS; 28 | quad <= std_logic_vector (count (15 DOWNTO 14)); -- splits count range into 4 phases 29 | index <= signed ("00" & count (13 DOWNTO 0)); -- 14-bit index into the current phase 30 | -- This select statement converts an unsigned 16-bit sawtooth that ranges from 65,535 31 | -- into a signed 12-bit triangle wave that ranges from -16,383 to +16,383 32 | WITH quad SELECT 33 | data <= index WHEN "00", -- 1st quadrant 34 | 16383 - index WHEN "01", -- 2nd quadrant 35 | 0 - index WHEN "10", -- 3rd quadrant 36 | index - 16383 WHEN OTHERS; -- 4th quadrant 37 | END Behavioral; 38 | -------------------------------------------------------------------------------- /Nexys-2/Lab-5/wail.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | -- Generates a "wailing siren" sound by instancing a "tone" module and modulating 6 | -- the pitch of the tone. The pitch is increased until it reaches hi_pitch and then 7 | -- decreased until it reaches lo_pitch and then increased again, etc. 8 | ENTITY wail IS 9 | PORT ( 10 | lo_pitch : IN UNSIGNED (13 DOWNTO 0); -- lowest pitch (in units of 0.745 Hz) 11 | hi_pitch : IN UNSIGNED (13 DOWNTO 0); -- highest pitch (in units of 0.745 Hz) 12 | wspeed : IN UNSIGNED (7 DOWNTO 0); -- speed of wail in pitch units/wclk 13 | wclk : IN STD_LOGIC; -- wailing clock (47.6 Hz) 14 | audio_clk : IN STD_LOGIC; -- audio sampling clock (48.8 kHz) 15 | audio_data : OUT SIGNED (15 DOWNTO 0)); -- output audio sequence (wailing tone) 16 | END wail; 17 | 18 | ARCHITECTURE Behavioral OF wail IS 19 | COMPONENT tone IS 20 | PORT ( 21 | clk : IN STD_LOGIC; 22 | pitch : IN UNSIGNED (13 DOWNTO 0); 23 | data : OUT SIGNED (15 DOWNTO 0) 24 | ); 25 | END COMPONENT; 26 | SIGNAL curr_pitch : UNSIGNED (13 DOWNTO 0); -- current wailing pitch 27 | BEGIN 28 | -- this process modulates the current pitch. It keep a variable updn to indicate 29 | -- whether tone is currently rising or falling. Each wclk period it increments 30 | -- (or decrements) the current pitch by wspeed. When it reaches hi_pitch, it 31 | -- starts counting down. When it reaches lo_pitch, it starts counting up 32 | wp : PROCESS 33 | VARIABLE updn : std_logic; 34 | BEGIN 35 | WAIT UNTIL rising_edge(wclk); 36 | IF curr_pitch >= hi_pitch THEN 37 | updn := '0'; -- check to see if still in range 38 | ELSIF curr_pitch <= lo_pitch THEN 39 | updn := '1'; -- if not, adjust updn 40 | END IF; 41 | IF updn = '1' THEN 42 | curr_pitch <= curr_pitch + wspeed; -- modulate pitch according to 43 | ELSE 44 | curr_pitch <= curr_pitch - wspeed; -- current value of updn 45 | END IF; 46 | END PROCESS; 47 | tgen : tone 48 | PORT MAP( 49 | clk => audio_clk, -- instance a tone module 50 | pitch => curr_pitch, -- use curr-pitch to modulate tone 51 | data => audio_data 52 | ); 53 | END Behavioral; 54 | -------------------------------------------------------------------------------- /Nexys-2/Lab-6/README.md: -------------------------------------------------------------------------------- 1 | # Lab 6: Video Game "PONG" 2 | 3 | Pmod AD1, potentiometer, and VGA display 4 | -------------------------------------------------------------------------------- /Nexys-2/Lab-6/adc_if.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY adc_if IS 6 | PORT ( 7 | SCK : IN STD_LOGIC; -- serial clock that goes to ADC 8 | SDATA1 : IN STD_LOGIC; -- serial data channel 1 9 | SDATA2 : IN STD_LOGIC; -- serial data channel 2 10 | CS : IN STD_LOGIC; -- chip select that initiates A/D conversion 11 | data_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- parallel 12-bit data ch1 12 | data_2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); -- parallel 12-bit data ch2 13 | END adc_if; 14 | 15 | ARCHITECTURE Behavioral OF adc_if IS 16 | SIGNAL pdata1, pdata2 : std_logic_vector (11 DOWNTO 0); -- 12-bit shift registers 17 | BEGIN 18 | -- this process waits for CS=0 and then clocks serial data from ADC into shift register 19 | -- MSBit first. After 16 SCK's, four leading zeros will have fallen out of the most significant 20 | -- end of the shift register and the register will contain the parallel12-bit data 21 | adpr : PROCESS 22 | BEGIN 23 | WAIT UNTIL falling_edge (SCK); 24 | IF CS = '0' THEN 25 | pdata1 <= pdata1 (10 DOWNTO 0) & SDATA1; 26 | pdata2 <= pdata2 (10 DOWNTO 0) & SDATA2; 27 | END IF; 28 | END PROCESS; 29 | -- this process waits for rising edge of CS and then loads parallel data 30 | -- from shift register into appropriate output port 31 | sync : PROCESS 32 | BEGIN 33 | WAIT UNTIL rising_edge (CS); 34 | data_1 <= pdata1; 35 | data_2 <= pdata2; 36 | END PROCESS; 37 | END Behavioral; 38 | -------------------------------------------------------------------------------- /Nexys-2/Lab-6/pong.ucf: -------------------------------------------------------------------------------- 1 | NET "clk_50MHz" LOC = B8; 2 | 3 | NET "vga_hsync" LOC = T4; 4 | NET "vga_vsync" LOC = U3; 5 | 6 | NET "vga_red[0]" LOC = R9; 7 | NET "vga_red[1]" LOC = T8; 8 | NET "vga_red[2]" LOC = R8; 9 | NET "vga_green[0]" LOC = N8; 10 | NET "vga_green[1]" LOC = P8; 11 | NET "vga_green[2]" LOC = P6; 12 | NET "vga_blue[0]" LOC = U5; 13 | NET "vga_blue[1]" LOC = U4; 14 | 15 | NET "ADC_SDATA1" LOC = K12; 16 | NET "ADC_SDATA2" LOC = L17; 17 | NET "ADC_SCLK" LOC = M15; 18 | NET "ADC_CS" LOC = L15; 19 | 20 | NET "btn0" LOC = B18; 21 | 22 | NET "ck_25" TNM_NET = ck_25_net; 23 | TIMESPEC TS_ck_25 = PERIOD "ck_25_net" 40 ns HIGH 50%; 24 | -------------------------------------------------------------------------------- /Nexys-2/Lab-6/vga_sync.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY vga_sync IS 6 | PORT ( 7 | clock_25MHz : IN STD_LOGIC; 8 | red : IN STD_LOGIC; 9 | green : IN STD_LOGIC; 10 | blue : IN STD_LOGIC; 11 | red_out : OUT STD_LOGIC; 12 | green_out : OUT STD_LOGIC; 13 | blue_out : OUT STD_LOGIC; 14 | hsync : OUT STD_LOGIC; 15 | vsync : OUT STD_LOGIC; 16 | pixel_row : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); 17 | pixel_col : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 18 | ); 19 | END vga_sync; 20 | 21 | ARCHITECTURE Behavioral OF vga_sync IS 22 | SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (9 DOWNTO 0); 23 | BEGIN 24 | sync_pr : PROCESS 25 | VARIABLE video_on : STD_LOGIC; 26 | BEGIN 27 | WAIT UNTIL rising_edge(clock_25MHz); 28 | -- Generate Horizontal Timing Signals for Video Signal 29 | -- h_cnt counts pixels across line (800 total = 640 active + extras for sync and blanking) 30 | -- Active picture for 0 <= h_cnt <= 639 31 | -- Hsync for 659 <= h_cnt <= 755 32 | IF h_cnt >= 799 THEN 33 | h_cnt <= "0000000000"; 34 | ELSE 35 | h_cnt <= h_cnt + 1; 36 | END IF; 37 | IF (h_cnt >= 659) AND (h_cnt <= 755) THEN 38 | hsync <= '0'; 39 | ELSE 40 | hsync <= '1'; 41 | END IF; 42 | -- Generate Vertical Timing Signals for Video Signal 43 | -- v_cnt counts lines down screen (525 total = 480 active + extras for sync and blanking) 44 | -- Active picture for 0 <= v_cnt <= 479 45 | -- Vsync for 493 <= h_cnt <= 494 46 | IF (v_cnt >= 524) AND (h_cnt = 699) THEN 47 | v_cnt <= "0000000000"; 48 | ELSIF h_cnt = 699 THEN 49 | v_cnt <= v_cnt + 1; 50 | END IF; 51 | IF (v_cnt >= 493) AND (v_cnt <= 494) THEN 52 | vsync <= '0'; 53 | ELSE 54 | vsync <= '1'; 55 | END IF; 56 | -- Generate Video Signals and Pixel Address 57 | IF (h_cnt <= 639) AND (v_cnt <= 479) THEN 58 | video_on := '1'; 59 | ELSE 60 | video_on := '0'; 61 | END IF; 62 | pixel_col <= h_cnt; 63 | pixel_row <= v_cnt; 64 | -- Register video to clock edge and suppress video during blanking and sync periods 65 | red_out <= red AND video_on; 66 | green_out <= green AND video_on; 67 | blue_out <= blue AND video_on; 68 | END PROCESS; 69 | END Behavioral; 70 | -------------------------------------------------------------------------------- /Nexys-2/README.md: -------------------------------------------------------------------------------- 1 | # NI Digilent Nexys 2 Spartan-3E FPGA Trainer Board 2 | * The NI Digilent Nexys 2 [Reference Manual](https://reference.digilentinc.com/reference/programmable-logic/nexys-2/reference-manual) 3 | * [Xilinx Integrated Synthesis Environment](https://en.wikipedia.org/wiki/Xilinx_ISE) (ISE) 4 | * [ISE Design Suite](https://www.xilinx.com/products/design-tools/ise-design-suite.html) 5 | * [ISE WebPACK Design Software](https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html) for Windows and Linux 6 | * [User Constraints File](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/platform_studio/ps_p_hdw_setting_up_your_ucf.htm) (UCF) 7 | * [Lab resources](https://personal.stevens.edu/~backland/Courses/Course487_Spring_18.htm) by Prof. [Bryan Ackland](https://ieee-ceda.org/contact/bryan-ackland) 8 | -------------------------------------------------------------------------------- /Nexys-4-DDR/README.md: -------------------------------------------------------------------------------- 1 | # NI Digilent Nexys 4 DDR FPGA Trainer Board 2 | 3 | * The NI Digilent Nexys 4 DDR board is functionally dentical to the Nexys A7-100T. 4 | * [Double data rate](https://en.wikipedia.org/wiki/Double_data_rate) (DDR) 5 | * Proceed to the Nexys A7 [folder](/Nexys-A7). 6 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/7s.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-1/7s.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/Modifications/README.md: -------------------------------------------------------------------------------- 1 | # Modified Design 2 | 3 | * Turn on the anode of one of the eight-digit 7-segment display by 3-bit digit selector dig 4 | 5 | * Slide switches 6, 7, and 8 to determine which display is illuminated 6 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/Modifications/leddec_1.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 7 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 10 | ); 11 | END leddec; 12 | 13 | ARCHITECTURE Behavioral OF leddec IS 14 | BEGIN 15 | -- Turn on segments corresponding to 4-bit data word 16 | seg <= "0000001" WHEN data = "0000" ELSE --0 17 | "1001111" WHEN data = "0001" ELSE --1 18 | "0010010" WHEN data = "0010" ELSE --2 19 | "0000110" WHEN data = "0011" ELSE --3 20 | "1001100" WHEN data = "0100" ELSE --4 21 | "0100100" WHEN data = "0101" ELSE --5 22 | "0100000" WHEN data = "0110" ELSE --6 23 | "0001111" WHEN data = "0111" ELSE --7 24 | "0000000" WHEN data = "1000" ELSE --8 25 | "0000100" WHEN data = "1001" ELSE --9 26 | "0001000" WHEN data = "1010" ELSE --A 27 | "1100000" WHEN data = "1011" ELSE --B 28 | "0110001" WHEN data = "1100" ELSE --C 29 | "1000010" WHEN data = "1101" ELSE --D 30 | "0110000" WHEN data = "1110" ELSE --E 31 | "0111000" WHEN data = "1111" ELSE --F 32 | "1111111"; 33 | -- Turn on anode of 7-segment display addressed by 3-bit digit selector dig 34 | anode <= "11111110" WHEN dig = "000" ELSE --0 35 | "11111101" WHEN dig = "001" ELSE --1 36 | "11111011" WHEN dig = "010" ELSE --2 37 | "11110111" WHEN dig = "011" ELSE --3 38 | "11101111" WHEN dig = "100" ELSE --4 39 | "11011111" WHEN dig = "101" ELSE --5 40 | "10111111" WHEN dig = "110" ELSE --6 41 | "01111111" WHEN dig = "111" ELSE --7 42 | "11111111"; 43 | END Behavioral; 44 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/Modifications/leddec_1.xdc: -------------------------------------------------------------------------------- 1 | #FPGA I/O Pin Locations 2 | 3 | set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {dig[0]}] 4 | set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {dig[1]}] 5 | set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dig[2]}] 6 | 7 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {data[0]}] 8 | set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {data[1]}] 9 | set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {data[2]}] 10 | set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {data[3]}] 11 | 12 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}] 13 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}] 14 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}] 15 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}] 16 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}] 17 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}] 18 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}] 19 | 20 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[7]}] 21 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[6]}] 22 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[5]}] 23 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[4]}] 24 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}] 25 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {anode[2]}] 26 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {anode[1]}] 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {anode[0]}] 28 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/a7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-1/a7.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/cnt.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-1/cnt.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/counter.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY counter IS 6 | PORT ( 7 | clk : IN STD_LOGIC; 8 | count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 9 | ); 10 | END counter; 11 | 12 | ARCHITECTURE Behavioral OF counter IS 13 | SIGNAL cnt : STD_LOGIC_VECTOR (28 DOWNTO 0); -- 29 bit counter 14 | BEGIN 15 | PROCESS (clk) 16 | BEGIN 17 | IF clk'EVENT AND clk = '1' THEN -- on rising edge of clock 18 | cnt <= cnt + 1; -- increment counter 19 | END IF; 20 | END PROCESS; 21 | count <= cnt (28 DOWNTO 25); 22 | END Behavioral; 23 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/hexcount.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY hexcount IS 5 | PORT ( 6 | clk_100MHz : IN STD_LOGIC; 7 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 8 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 9 | ); 10 | END hexcount; 11 | 12 | ARCHITECTURE Behavioral OF hexcount IS 13 | COMPONENT counter IS 14 | PORT ( 15 | clk : IN STD_LOGIC; 16 | count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 17 | ); 18 | END COMPONENT; 19 | COMPONENT leddec IS 20 | PORT ( 21 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 22 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 23 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 24 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 25 | ); 26 | END COMPONENT; 27 | SIGNAL S : STD_LOGIC_VECTOR (3 DOWNTO 0); 28 | BEGIN 29 | C1 : counter 30 | PORT MAP(clk => clk_100MHz, count => S); 31 | L1 : leddec 32 | PORT MAP(dig => "000", data => S, anode => anode, seg => seg); 33 | END Behavioral; 34 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/hexcount.xdc: -------------------------------------------------------------------------------- 1 | #FPGA I/0 Locations 2 | 3 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk_100MHz] 4 | 5 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}] 6 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}] 7 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}] 8 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}] 9 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}] 10 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}] 11 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}] 12 | 13 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[7]}] 14 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[6]}] 15 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[5]}] 16 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[4]}] 17 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}] 18 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {anode[2]}] 19 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {anode[1]}] 20 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {anode[0]}] 21 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/leddec.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 7 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 10 | ); 11 | END leddec; 12 | 13 | ARCHITECTURE Behavioral OF leddec IS 14 | BEGIN 15 | -- Turn on segments corresponding to 4-bit data word 16 | seg <= "0000001" WHEN data = "0000" ELSE -- 0 17 | "1001111" WHEN data = "0001" ELSE -- 1 18 | "0010010" WHEN data = "0010" ELSE -- 2 19 | "0000110" WHEN data = "0011" ELSE -- 3 20 | "1001100" WHEN data = "0100" ELSE -- 4 21 | "0100100" WHEN data = "0101" ELSE -- 5 22 | "0100000" WHEN data = "0110" ELSE -- 6 23 | "0001111" WHEN data = "0111" ELSE -- 7 24 | "0000000" WHEN data = "1000" ELSE -- 8 25 | "0000100" WHEN data = "1001" ELSE -- 9 26 | "0001000" WHEN data = "1010" ELSE -- A 27 | "1100000" WHEN data = "1011" ELSE -- B 28 | "0110001" WHEN data = "1100" ELSE -- C 29 | "1000010" WHEN data = "1101" ELSE -- D 30 | "0110000" WHEN data = "1110" ELSE -- E 31 | "0111000" WHEN data = "1111" ELSE -- F 32 | "1111111"; 33 | -- Turn on anode of 7-segment display addressed by 3-bit digit selector dig 34 | anode <= "11111110" WHEN dig = "000" ELSE -- 0 35 | "11111101" WHEN dig = "001" ELSE -- 1 36 | "11111011" WHEN dig = "010" ELSE -- 2 37 | "11110111" WHEN dig = "011" ELSE -- 3 38 | "11101111" WHEN dig = "100" ELSE -- 4 39 | "11011111" WHEN dig = "101" ELSE -- 5 40 | "10111111" WHEN dig = "110" ELSE -- 6 41 | "01111111" WHEN dig = "111" ELSE -- 7 42 | "11111111"; 43 | END Behavioral; 44 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-1/leddec.xdc: -------------------------------------------------------------------------------- 1 | #FPGA I/O Pin Locations 2 | 3 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {dig[0]}] 4 | set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {dig[1]}] 5 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {dig[2]}] 6 | 7 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {data[0]}] 8 | set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {data[1]}] 9 | set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {data[2]}] 10 | set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {data[3]}] 11 | 12 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}] 13 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}] 14 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}] 15 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}] 16 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}] 17 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}] 18 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}] 19 | 20 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[7]}] 21 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[6]}] 22 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[5]}] 23 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[4]}] 24 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}] 25 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {anode[2]}] 26 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {anode[1]}] 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {anode[0]}] 28 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/Modifications/README.md: -------------------------------------------------------------------------------- 1 | # Modified Design 2 | 3 | * Build an eight-digit (32-bit) counter 4 | 5 | * Create a new RTL project called **_hex8count_** in Vivado Quick Start 6 | 7 | * The 3-bit mpx signal is used to select which 4-bits of the 32-bit count output should be sent to the data input of the leddec module 8 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/Modifications/counter_1.vhd: -------------------------------------------------------------------------------- 1 | -- counter.vhd -- 2 | 3 | LIBRARY IEEE; 4 | USE IEEE.STD_LOGIC_1164.ALL; 5 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | 7 | ENTITY counter IS 8 | PORT ( 9 | clk : IN STD_LOGIC; 10 | count : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- NEED REVISE! 32 bits 11 | mpx : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); -- NEW ONE ADD! send signal to select displays 12 | END counter; 13 | 14 | ARCHITECTURE Behavioral OF counter IS 15 | SIGNAL cnt : STD_LOGIC_VECTOR (54 DOWNTO 0); -- 55-bit counter 16 | BEGIN 17 | PROCESS (clk) 18 | BEGIN 19 | IF clk'EVENT AND clk = '1' THEN -- on rising edge of clock 20 | cnt <= cnt + 1; -- increment counter 21 | END IF; 22 | END PROCESS; 23 | count <= cnt (54 DOWNTO 23); -- 32 bits 24 | mpx <= cnt (19 DOWNTO 17); -- 3 bits 25 | END Behavioral; 26 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/Modifications/hexcount_1.vhd: -------------------------------------------------------------------------------- 1 | -- hexcount.vhd -- 2 | 3 | LIBRARY IEEE; 4 | USE IEEE.STD_LOGIC_1164.ALL; 5 | 6 | ENTITY hexcount IS 7 | PORT ( 8 | clk_100MHz : IN STD_LOGIC; 9 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 10 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 11 | ); 12 | END hexcount; 13 | 14 | ARCHITECTURE Behavioral OF hexcount IS 15 | 16 | COMPONENT counter IS 17 | PORT ( 18 | clk : IN STD_LOGIC; 19 | count : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- NEED CHANGE! counter now output 32 bits for all 8 displays 20 | mpx : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) 21 | ); 22 | END COMPONENT; 23 | 24 | COMPONENT leddec IS 25 | PORT ( 26 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 27 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- DON'T change, data is fixed 4 bits in leddec for each displays 28 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 29 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 30 | ); 31 | END COMPONENT; 32 | 33 | SIGNAL S : STD_LOGIC_VECTOR (31 DOWNTO 0); -- Connect C1 and L1 for values of 8 digits 34 | SIGNAL md : STD_LOGIC_VECTOR (2 DOWNTO 0); -- mpx selects displays 35 | SIGNAL display : STD_LOGIC_VECTOR (3 DOWNTO 0); -- Send digit for only one display to leddec 36 | 37 | BEGIN 38 | C1 : counter 39 | PORT MAP(clk => clk_100MHz, count => S, mpx => md); 40 | L1 : leddec 41 | PORT MAP(dig => md, data => display, anode => anode, seg => seg); 42 | --mpx 43 | --process(md) 44 | --begin 45 | -- if md = "00" then 46 | -- display <= S(3 downto 0); 47 | -- elsif md = "01" then 48 | -- display <= S(7 downto 4); 49 | -- elsif md = "10" then 50 | -- display <= S(11 downto 8); 51 | -- elsif md = "11" then 52 | -- display <= S(15 downto 12); 53 | -- end if; 54 | --end process; 55 | 56 | display <= S(3 DOWNTO 0) WHEN md = "000" ELSE 57 | S(7 DOWNTO 4) WHEN md = "001" ELSE 58 | S(11 DOWNTO 8) WHEN md = "010" ELSE 59 | S(15 DOWNTO 12) WHEN md = "011" ELSE 60 | S(19 DOWNTO 16) WHEN md = "100" ELSE 61 | S(23 DOWNTO 20) WHEN md = "101" ELSE 62 | S(27 DOWNTO 24) WHEN md = "110" ELSE 63 | S(31 DOWNTO 28); 64 | 65 | END Behavioral; 66 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/Modifications/hexcount_1.xdc: -------------------------------------------------------------------------------- 1 | #FPGA I/0 Locations 2 | 3 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk_100MHz] 4 | 5 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}] 6 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}] 7 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}] 8 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}] 9 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}] 10 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}] 11 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}] 12 | 13 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[7]}] 14 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[6]}] 15 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[5]}] 16 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[4]}] 17 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}] 18 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {anode[2]}] 19 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {anode[1]}] 20 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {anode[0]}] 21 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/Modifications/leddec_1.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 7 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 10 | ); 11 | END leddec; 12 | 13 | ARCHITECTURE Behavioral OF leddec IS 14 | BEGIN 15 | -- Turn on segments corresponding to 4-bit data word 16 | seg <= "0000001" WHEN data = "0000" ELSE -- 0 17 | "1001111" WHEN data = "0001" ELSE -- 1 18 | "0010010" WHEN data = "0010" ELSE -- 2 19 | "0000110" WHEN data = "0011" ELSE -- 3 20 | "1001100" WHEN data = "0100" ELSE -- 4 21 | "0100100" WHEN data = "0101" ELSE -- 5 22 | "0100000" WHEN data = "0110" ELSE -- 6 23 | "0001111" WHEN data = "0111" ELSE -- 7 24 | "0000000" WHEN data = "1000" ELSE -- 8 25 | "0000100" WHEN data = "1001" ELSE -- 9 26 | "0001000" WHEN data = "1010" ELSE -- A 27 | "1100000" WHEN data = "1011" ELSE -- B 28 | "0110001" WHEN data = "1100" ELSE -- C 29 | "1000010" WHEN data = "1101" ELSE -- D 30 | "0110000" WHEN data = "1110" ELSE -- E 31 | "0111000" WHEN data = "1111" ELSE -- F 32 | "1111111"; 33 | -- Turn on anode of 7-segment display addressed by 3-bit digit selector dig 34 | anode <= "11111110" WHEN dig = "000" ELSE -- 0 35 | "11111101" WHEN dig = "001" ELSE -- 1 36 | "11111011" WHEN dig = "010" ELSE -- 2 37 | "11110111" WHEN dig = "011" ELSE -- 3 38 | "11101111" WHEN dig = "100" ELSE -- 4 39 | "11011111" WHEN dig = "101" ELSE -- 5 40 | "10111111" WHEN dig = "110" ELSE -- 6 41 | "01111111" WHEN dig = "111" ELSE -- 7 42 | "11111111"; 43 | END Behavioral; 44 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/counter.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-2/counter.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/counter.vhd: -------------------------------------------------------------------------------- 1 | -- counter.vhd -- 2 | 3 | LIBRARY IEEE; 4 | USE IEEE.STD_LOGIC_1164.ALL; 5 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | 7 | ENTITY counter IS 8 | PORT ( 9 | clk : IN STD_LOGIC; 10 | count : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- NEED REVISE! 16 bits 11 | mpx : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); -- NEW ONE ADD! send signal to select displays 12 | END counter; 13 | 14 | ARCHITECTURE Behavioral OF counter IS 15 | SIGNAL cnt : STD_LOGIC_VECTOR (38 DOWNTO 0); -- 39-bit counter 16 | BEGIN 17 | PROCESS (clk) 18 | BEGIN 19 | IF clk'EVENT AND clk = '1' THEN -- on rising edge of clock 20 | cnt <= cnt + 1; -- increment counter 21 | END IF; 22 | END PROCESS; 23 | count <= cnt (38 DOWNTO 23); -- 16 bits 24 | mpx <= cnt (19 DOWNTO 17); -- 3 bits 25 | END Behavioral; 26 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/hexcount.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-2/hexcount.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/hexcount.vhd: -------------------------------------------------------------------------------- 1 | -- hexcount.vhd -- 2 | 3 | LIBRARY IEEE; 4 | USE IEEE.STD_LOGIC_1164.ALL; 5 | 6 | ENTITY hexcount IS 7 | PORT ( 8 | clk_100MHz : IN STD_LOGIC; 9 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 10 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 11 | ); 12 | END hexcount; 13 | 14 | ARCHITECTURE Behavioral OF hexcount IS 15 | 16 | COMPONENT counter IS 17 | PORT ( 18 | clk : IN STD_LOGIC; 19 | count : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- NEED CHANGE! counter now output 16 bits for all 4 displays 20 | mpx : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) 21 | ); 22 | END COMPONENT; 23 | 24 | COMPONENT leddec IS 25 | PORT ( 26 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 27 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- DON'T change, data is fixed 4 bits in leddec for each displays 28 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 29 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 30 | ); 31 | END COMPONENT; 32 | 33 | SIGNAL S : STD_LOGIC_VECTOR (15 DOWNTO 0); -- Connect C1 and L1 for values of 4 digits 34 | SIGNAL md : STD_LOGIC_VECTOR (2 DOWNTO 0); -- mpx selects displays 35 | SIGNAL display : STD_LOGIC_VECTOR (3 DOWNTO 0); -- Send digit for only one display to leddec 36 | 37 | BEGIN 38 | C1 : counter 39 | PORT MAP(clk => clk_100MHz, count => S, mpx => md); 40 | L1 : leddec 41 | PORT MAP(dig => md, data => display, anode => anode, seg => seg); 42 | --mpx 43 | --process(md) 44 | --begin 45 | -- if md = "00" then 46 | -- display <= S(3 downto 0); 47 | -- elsif md = "01" then 48 | -- display <= S(7 downto 4); 49 | -- elsif md = "10" then 50 | -- display <= S(11 downto 8); 51 | -- elsif md = "11" then 52 | -- display <= S(15 downto 12); 53 | -- end if; 54 | --end process; 55 | 56 | display <= S(3 DOWNTO 0) WHEN md = "000" ELSE 57 | S(7 DOWNTO 4) WHEN md = "001" ELSE 58 | S(11 DOWNTO 8) WHEN md = "010" ELSE 59 | S(15 DOWNTO 12); 60 | 61 | END Behavioral; 62 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/hexcount.xdc: -------------------------------------------------------------------------------- 1 | #FPGA I/0 Locations 2 | 3 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk_100MHz] 4 | 5 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}] 6 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}] 7 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}] 8 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}] 9 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}] 10 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}] 11 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}] 12 | 13 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[7]}] 14 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[6]}] 15 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[5]}] 16 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[4]}] 17 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}] 18 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {anode[2]}] 19 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {anode[1]}] 20 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {anode[0]}] 21 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/hexcounter.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-2/hexcounter.gif -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/leddec.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 7 | data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) 10 | ); 11 | END leddec; 12 | 13 | ARCHITECTURE Behavioral OF leddec IS 14 | BEGIN 15 | -- Turn on segments corresponding to 4-bit data word 16 | seg <= "0000001" WHEN data = "0000" ELSE -- 0 17 | "1001111" WHEN data = "0001" ELSE -- 1 18 | "0010010" WHEN data = "0010" ELSE -- 2 19 | "0000110" WHEN data = "0011" ELSE -- 3 20 | "1001100" WHEN data = "0100" ELSE -- 4 21 | "0100100" WHEN data = "0101" ELSE -- 5 22 | "0100000" WHEN data = "0110" ELSE -- 6 23 | "0001111" WHEN data = "0111" ELSE -- 7 24 | "0000000" WHEN data = "1000" ELSE -- 8 25 | "0000100" WHEN data = "1001" ELSE -- 9 26 | "0001000" WHEN data = "1010" ELSE -- A 27 | "1100000" WHEN data = "1011" ELSE -- B 28 | "0110001" WHEN data = "1100" ELSE -- C 29 | "1000010" WHEN data = "1101" ELSE -- D 30 | "0110000" WHEN data = "1110" ELSE -- E 31 | "0111000" WHEN data = "1111" ELSE -- F 32 | "1111111"; 33 | -- Turn on anode of 7-segment display addressed by 3-bit digit selector dig 34 | anode <= "11111110" WHEN dig = "000" ELSE -- 0 35 | "11111101" WHEN dig = "001" ELSE -- 1 36 | "11111011" WHEN dig = "010" ELSE -- 2 37 | "11110111" WHEN dig = "011" ELSE -- 3 38 | -- "11101111" WHEN dig = "100" ELSE -- 4 39 | -- "11011111" WHEN dig = "101" ELSE -- 5 40 | -- "10111111" WHEN dig = "110" ELSE -- 6 41 | -- "01111111" WHEN dig = "111" ELSE -- 7 42 | "11111111"; 43 | END Behavioral; 44 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-2/mpx.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-2/mpx.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-3/Modifications/README.md: -------------------------------------------------------------------------------- 1 | # Modified Design 2 | 3 | ball_1.vhd 4 | 5 | * Change the size and color of the ball 6 | 7 | * Change the square ball to a round ball 8 | 9 | * Introduce a new signal ball_x_motion to allow the ball to move both horizontally and vertically 10 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-3/Modifications/ball_1.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_ARITH.ALL; 4 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | ENTITY ball IS 7 | PORT ( 8 | v_sync : IN STD_LOGIC; 9 | pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 10 | pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 11 | red : OUT STD_LOGIC; 12 | green : OUT STD_LOGIC; 13 | blue : OUT STD_LOGIC 14 | ); 15 | END ball; 16 | 17 | ARCHITECTURE Behavioral OF ball IS 18 | CONSTANT size : INTEGER := 16; -- modify ball size from 8 19 | SIGNAL ball_on : STD_LOGIC; -- indicates whether ball is over current pixel position 20 | -- current ball position - intitialized to center of screen 21 | SIGNAL ball_x : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(400, 11); 22 | SIGNAL ball_y : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(300, 11); 23 | -- current ball motion - initialized to +4 pixels/frame 24 | SIGNAL ball_x_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000100"; 25 | SIGNAL ball_y_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000100"; 26 | BEGIN 27 | red <= '1'; -- color setup for red ball on white background 28 | green <= NOT ball_on; 29 | blue <= '1'; -- modify ball color from red to magenta 30 | -- process to draw ball current pixel address is covered by ball position 31 | bdraw : PROCESS (ball_x, ball_y, pixel_row, pixel_col) IS 32 | BEGIN 33 | IF ((((CONV_INTEGER(pixel_col)-CONV_INTEGER(ball_x))* 34 | (CONV_INTEGER(pixel_col)-CONV_INTEGER(ball_x)))+ 35 | ((CONV_INTEGER(pixel_row)-CONV_INTEGER(ball_y))* 36 | (CONV_INTEGER(pixel_row)-CONV_INTEGER(ball_y)))) <= (size*size)) THEN 37 | -- IF (pixel_col >= ball_x - size) AND 38 | -- (pixel_col <= ball_x + size) AND 39 | -- (pixel_row >= ball_y - size) AND 40 | -- (pixel_row <= ball_y + size) THEN 41 | ball_on <= '1'; 42 | ELSE 43 | ball_on <= '0'; 44 | END IF; 45 | END PROCESS; 46 | -- process to move ball once every frame (i.e. once every vsync pulse) 47 | mball : PROCESS 48 | BEGIN 49 | WAIT UNTIL rising_edge(v_sync); 50 | IF ball_x + size >= 800 THEN 51 | ball_x_motion <= "11111111100"; -- -4 pixels 52 | ELSIF ball_x <= size THEN 53 | ball_x_motion <= "00000000100"; -- +4 pixels 54 | END IF; 55 | -- allow for bounce off top or bottom of screen 56 | IF ball_y + size >= 600 THEN 57 | ball_y_motion <= "11111111100"; -- -4 pixels 58 | ELSIF ball_y <= size THEN 59 | ball_y_motion <= "00000000100"; -- +4 pixels 60 | END IF; 61 | ball_x <= ball_x + ball_x_motion; 62 | ball_y <= ball_y + ball_y_motion; -- compute next ball position 63 | END PROCESS; 64 | END Behavioral; 65 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-3/ball.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_ARITH.ALL; 4 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | ENTITY ball IS 7 | PORT ( 8 | v_sync : IN STD_LOGIC; 9 | pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 10 | pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 11 | red : OUT STD_LOGIC; 12 | green : OUT STD_LOGIC; 13 | blue : OUT STD_LOGIC 14 | ); 15 | END ball; 16 | 17 | ARCHITECTURE Behavioral OF ball IS 18 | CONSTANT size : INTEGER := 8; 19 | SIGNAL ball_on : STD_LOGIC; -- indicates whether ball is over current pixel position 20 | -- current ball position - intitialized to center of screen 21 | SIGNAL ball_x : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(400, 11); 22 | SIGNAL ball_y : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(300, 11); 23 | -- current ball motion - initialized to +4 pixels/frame 24 | SIGNAL ball_y_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000100"; 25 | BEGIN 26 | red <= '1'; -- color setup for red ball on white background 27 | green <= NOT ball_on; 28 | blue <= NOT ball_on; 29 | -- process to draw ball current pixel address is covered by ball position 30 | bdraw : PROCESS (ball_x, ball_y, pixel_row, pixel_col) IS 31 | BEGIN 32 | IF (pixel_col >= ball_x - size) AND 33 | (pixel_col <= ball_x + size) AND 34 | (pixel_row >= ball_y - size) AND 35 | (pixel_row <= ball_y + size) THEN 36 | ball_on <= '1'; 37 | ELSE 38 | ball_on <= '0'; 39 | END IF; 40 | END PROCESS; 41 | -- process to move ball once every frame (i.e. once every vsync pulse) 42 | mball : PROCESS 43 | BEGIN 44 | WAIT UNTIL rising_edge(v_sync); 45 | -- allow for bounce off top or bottom of screen 46 | IF ball_y + size >= 600 THEN 47 | ball_y_motion <= "11111111100"; -- -4 pixels 48 | ELSIF ball_y <= size THEN 49 | ball_y_motion <= "00000000100"; -- +4 pixels 50 | END IF; 51 | ball_y <= ball_y + ball_y_motion; -- compute next ball position 52 | END PROCESS; 53 | END Behavioral; 54 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-3/vga_sync.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY vga_sync IS 6 | PORT ( 7 | pixel_clk : IN STD_LOGIC; 8 | red_in : IN STD_LOGIC; 9 | green_in : IN STD_LOGIC; 10 | blue_in : IN STD_LOGIC; 11 | red_out : OUT STD_LOGIC; 12 | green_out : OUT STD_LOGIC; 13 | blue_out : OUT STD_LOGIC; 14 | hsync : OUT STD_LOGIC; 15 | vsync : OUT STD_LOGIC; 16 | pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); 17 | pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) 18 | ); 19 | END vga_sync; 20 | 21 | ARCHITECTURE Behavioral OF vga_sync IS 22 | SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (10 DOWNTO 0); 23 | 24 | CONSTANT H : INTEGER := 800; 25 | CONSTANT V : INTEGER := 600; 26 | CONSTANT H_FP : INTEGER := 40; 27 | CONSTANT H_BP : INTEGER := 88; 28 | CONSTANT H_SYNC : INTEGER := 128; 29 | CONSTANT V_FP : INTEGER := 1; 30 | CONSTANT V_BP : INTEGER := 23; 31 | CONSTANT V_SYNC : INTEGER := 4; 32 | 33 | CONSTANT FREQ : INTEGER := 60; 34 | 35 | BEGIN 36 | sync_pr : PROCESS 37 | VARIABLE video_on : STD_LOGIC; 38 | BEGIN 39 | WAIT UNTIL rising_edge(pixel_clk); 40 | -- Generate Horizontal Timing Signals for Video Signal 41 | -- total horizontal line width = H + H_FP + H_SYNC + H_BP 42 | -- Reset h_cnt when at end of line 43 | IF (h_cnt >= H + H_FP + H_SYNC + H_BP - 1) THEN 44 | h_cnt <= (others => '0'); 45 | ELSE 46 | h_cnt <= h_cnt + 1; 47 | END IF; 48 | -- Pull down hsync after front porch 49 | IF (h_cnt >= H + H_FP) AND (h_cnt <= H + H_FP + H_SYNC) THEN 50 | hsync <= '0'; 51 | ELSE 52 | hsync <= '1'; 53 | END IF; 54 | 55 | IF (v_cnt >= V + V_FP + V_SYNC + V_BP - 1) AND (h_cnt = H + FREQ - 1) THEN 56 | v_cnt <= (others => '0'); 57 | ELSIF (h_cnt = H + FREQ - 1) THEN 58 | v_cnt <= v_cnt + 1; 59 | END IF; 60 | IF (v_cnt >= V + V_FP) AND (v_cnt <= V + V_FP + V_SYNC) THEN 61 | vsync <= '0'; 62 | ELSE 63 | vsync <= '1'; 64 | END IF; 65 | -- Generate Video Signals and Pixel Address 66 | IF (h_cnt < H) AND (v_cnt < V) THEN 67 | video_on := '1'; 68 | ELSE 69 | video_on := '0'; 70 | END IF; 71 | pixel_col <= h_cnt; 72 | pixel_row <= v_cnt; 73 | -- Register video to clock edge and suppress video during blanking and sync periods 74 | red_out <= red_in AND video_on; 75 | green_out <= green_in AND video_on; 76 | blue_out <= blue_in AND video_on; 77 | END PROCESS; 78 | END Behavioral; 79 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-3/vga_top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY vga_top IS 6 | PORT ( 7 | clk_in : IN STD_LOGIC; 8 | vga_red : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); 9 | vga_green : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); 10 | vga_blue : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); 11 | vga_hsync : OUT STD_LOGIC; 12 | vga_vsync : OUT STD_LOGIC 13 | ); 14 | END vga_top; 15 | 16 | ARCHITECTURE Behavioral OF vga_top IS 17 | SIGNAL pxl_clk : STD_LOGIC; 18 | -- internal signals to connect modules 19 | SIGNAL S_red, S_green, S_blue : STD_LOGIC; 20 | SIGNAL S_vsync : STD_LOGIC; 21 | SIGNAL S_pixel_row, S_pixel_col : STD_LOGIC_VECTOR (10 DOWNTO 0); 22 | COMPONENT ball IS 23 | PORT ( 24 | v_sync : IN STD_LOGIC; 25 | pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 26 | pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 27 | red : OUT STD_LOGIC; 28 | green : OUT STD_LOGIC; 29 | blue : OUT STD_LOGIC 30 | ); 31 | END COMPONENT; 32 | COMPONENT vga_sync IS 33 | PORT ( 34 | pixel_clk : IN STD_LOGIC; 35 | red_in : IN STD_LOGIC; 36 | green_in : IN STD_LOGIC; 37 | blue_in : IN STD_LOGIC; 38 | red_out : OUT STD_LOGIC; 39 | green_out : OUT STD_LOGIC; 40 | blue_out : OUT STD_LOGIC; 41 | hsync : OUT STD_LOGIC; 42 | vsync : OUT STD_LOGIC; 43 | pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); 44 | pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) 45 | ); 46 | END COMPONENT; 47 | 48 | component clk_wiz_0 is 49 | port ( 50 | clk_in1 : in std_logic; 51 | clk_out1 : out std_logic 52 | ); 53 | end component; 54 | 55 | 56 | BEGIN 57 | -- vga_driver only drives MSB of red, green & blue 58 | -- so set other bits to zero 59 | vga_red(1 DOWNTO 0) <= "00"; 60 | vga_green(1 DOWNTO 0) <= "00"; 61 | vga_blue(0) <= '0'; 62 | 63 | add_ball : ball 64 | PORT MAP( 65 | --instantiate ball component 66 | v_sync => S_vsync, 67 | pixel_row => S_pixel_row, 68 | pixel_col => S_pixel_col, 69 | red => S_red, 70 | green => S_green, 71 | blue => S_blue 72 | ); 73 | 74 | vga_driver : vga_sync 75 | PORT MAP( 76 | --instantiate vga_sync component 77 | pixel_clk => pxl_clk, 78 | red_in => S_red, 79 | green_in => S_green, 80 | blue_in => S_blue, 81 | red_out => vga_red(2), 82 | green_out => vga_green(2), 83 | blue_out => vga_blue(1), 84 | pixel_row => S_pixel_row, 85 | pixel_col => S_pixel_col, 86 | hsync => vga_hsync, 87 | vsync => S_vsync 88 | ); 89 | vga_vsync <= S_vsync; --connect output vsync 90 | 91 | clk_wiz_0_inst : clk_wiz_0 92 | port map ( 93 | clk_in1 => clk_in, 94 | clk_out1 => pxl_clk 95 | ); 96 | 97 | END Behavioral; 98 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-3/vga_top.xdc: -------------------------------------------------------------------------------- 1 | ## Clock signal 2 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 3 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_in }]; 4 | 5 | ##VGA Connector 6 | 7 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 8 | set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 9 | set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 10 | 11 | set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 12 | set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 13 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 14 | 15 | set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 16 | set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 17 | 18 | set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hsync }]; #IO_L4P_T0_15 Sch=vga_hs 19 | set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 20 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/Modifications/README.md: -------------------------------------------------------------------------------- 1 | # Modified Design 2 | 3 | * leddec16_1.vhd: leading zero suppression 4 | 5 | * hexcalc_1.vhd: subtraction operations 6 | 7 | * hexcalc_1.xdc: the BTND (P18) button for substraction 8 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/Modifications/hexcalc_1.xdc: -------------------------------------------------------------------------------- 1 | 2 | ## Clock signal 3 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_50MHz }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_50MHz}]; 5 | 6 | ##Buttons 7 | 8 | #set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn 9 | 10 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { bt_clr }]; #IO_L9P_T1_DQS_14 Sch=btnc 11 | set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { bt_plus }]; #IO_L4N_T0_D05_14 Sch=btnu 12 | set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { bt_eq }]; #IO_L12P_T1_MRCC_14 Sch=btnl 13 | #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr 14 | set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { bt_sub }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd 15 | 16 | ##Pmod Header JA 17 | 18 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { KB_col[4] }]; #IO_L20N_T3_A19_15 Sch=ja[1] 19 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { KB_col[3] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 20 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { KB_col[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 21 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { KB_col[1] }]; #IO_L18N_T2_A23_15 Sch=ja[4] 22 | set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { KB_row[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] 23 | set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { KB_row[3] }]; #IO_L16P_T2_A28_15 Sch=ja[8] 24 | set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { KB_row[2] }]; #IO_L22N_T3_A16_15 Sch=ja[9] 25 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { KB_row[1] }]; #IO_L22P_T3_A17_15 Sch=ja[10] 26 | 27 | ##7-Segment Display 28 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[0]}] 29 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[1]}] 30 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[2]}] 31 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[3]}] 32 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[4]}] 33 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[5]}] 34 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[6]}] 35 | 36 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[7]}] 37 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[6]}] 38 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[5]}] 39 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[4]}] 40 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[3]}] 41 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[2]}] 42 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[1]}] 43 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[0]}] 44 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/Modifications/leddec16_1.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec16 IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- which digit to currently display 7 | data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit (4-digit) data 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- which anode to turn on 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- segment code for current digit 10 | END leddec16; 11 | 12 | ARCHITECTURE Behavioral OF leddec16 IS 13 | SIGNAL data4 : STD_LOGIC_VECTOR (3 DOWNTO 0); -- binary value of current digit 14 | BEGIN 15 | -- Select digit data to be displayed in this mpx period 16 | data4 <= data(3 DOWNTO 0) WHEN dig = "000" ELSE --digit 0 17 | data(7 DOWNTO 4) WHEN dig = "001" ELSE --digit 1 18 | data(11 DOWNTO 8) WHEN dig = "010" ELSE --digit 2 19 | data(15 DOWNTO 12); --digit 3 20 | -- Turn on segments corresponding to 4-bit data word 21 | seg <= "0000001" WHEN data4 = "0000" ELSE -- 0 22 | "1001111" WHEN data4 = "0001" ELSE -- 1 23 | "0010010" WHEN data4 = "0010" ELSE -- 2 24 | "0000110" WHEN data4 = "0011" ELSE -- 3 25 | "1001100" WHEN data4 = "0100" ELSE -- 4 26 | "0100100" WHEN data4 = "0101" ELSE -- 5 27 | "0100000" WHEN data4 = "0110" ELSE -- 6 28 | "0001111" WHEN data4 = "0111" ELSE -- 7 29 | "0000000" WHEN data4 = "1000" ELSE -- 8 30 | "0000100" WHEN data4 = "1001" ELSE -- 9 31 | "0001000" WHEN data4 = "1010" ELSE -- A 32 | "1100000" WHEN data4 = "1011" ELSE -- B 33 | "0110001" WHEN data4 = "1100" ELSE -- C 34 | "1000010" WHEN data4 = "1101" ELSE -- D 35 | "0110000" WHEN data4 = "1110" ELSE -- E 36 | "0111000" WHEN data4 = "1111" ELSE -- F 37 | "1111111"; 38 | -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig 39 | anode <= "11111110" WHEN dig = "000" and data /= X"0000" ELSE -- digit 0 40 | "11111101" WHEN dig = "001" and data(15 downto 4) /= X"000" ELSE -- digit 1 41 | "11111011" WHEN dig = "010" and data(15 downto 8) /= X"00" ELSE -- digit 2 42 | "11110111" WHEN dig = "011" and data(15 downto 12) /= X"0" ELSE -- digit 3 43 | "11111111"; 44 | END Behavioral; 45 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/hexcalc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-4/hexcalc.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/hexcalc.xdc: -------------------------------------------------------------------------------- 1 | ## Clock signal 2 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_50MHz }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 3 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_50MHz}]; 4 | 5 | ##Buttons 6 | 7 | #set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn 8 | 9 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { bt_clr }]; #IO_L9P_T1_DQS_14 Sch=btnc 10 | set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { bt_plus }]; #IO_L4N_T0_D05_14 Sch=btnu 11 | set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { bt_eq }]; #IO_L12P_T1_MRCC_14 Sch=btnl 12 | #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr 13 | #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd 14 | 15 | ##Pmod Header JA 16 | 17 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { KB_col[4] }]; #IO_L20N_T3_A19_15 Sch=ja[1] 18 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { KB_col[3] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 19 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { KB_col[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 20 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { KB_col[1] }]; #IO_L18N_T2_A23_15 Sch=ja[4] 21 | set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { KB_row[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] 22 | set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { KB_row[3] }]; #IO_L16P_T2_A28_15 Sch=ja[8] 23 | set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { KB_row[2] }]; #IO_L22N_T3_A16_15 Sch=ja[9] 24 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { KB_row[1] }]; #IO_L22P_T3_A17_15 Sch=ja[10] 25 | 26 | ##7-Segment Display 27 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[0]}] 28 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[1]}] 29 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[2]}] 30 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[3]}] 31 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[4]}] 32 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[5]}] 33 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[6]}] 34 | 35 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[7]}] 36 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[6]}] 37 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[5]}] 38 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[4]}] 39 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[3]}] 40 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[2]}] 41 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[1]}] 42 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[0]}] 43 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/keypad.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY keypad IS 5 | PORT ( 6 | samp_ck : IN STD_LOGIC; -- clock to strobe columns 7 | col : OUT STD_LOGIC_VECTOR (4 DOWNTO 1); -- output column lines 8 | row : IN STD_LOGIC_VECTOR (4 DOWNTO 1); -- input row lines 9 | value : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- hex value of key depressed 10 | hit : OUT STD_LOGIC); -- indicates when a key has been pressed 11 | END keypad; 12 | 13 | ARCHITECTURE Behavioral OF keypad IS 14 | SIGNAL CV1, CV2, CV3, CV4 : std_logic_vector (4 DOWNTO 1) := "1111"; -- column vector of each row 15 | SIGNAL curr_col : std_logic_vector (4 DOWNTO 1) := "1110"; -- current column code 16 | BEGIN 17 | -- This process synchronously tests the state of the keypad buttons. On each edge of samp_ck, 18 | -- this module outputs a column code to the keypad in which one column line is held low while the 19 | -- other three column lines are held high. The row outputs of that column are then read 20 | -- into the corresponding column vector. The current column is then updated ready for the next 21 | -- clock edge. Remember that curr_col is not updated until the process suspends. 22 | strobe_proc : PROCESS 23 | BEGIN 24 | WAIT UNTIL rising_edge(samp_ck); 25 | CASE curr_col IS 26 | WHEN "1110" => 27 | CV1 <= row; 28 | curr_col <= "1101"; 29 | WHEN "1101" => 30 | CV2 <= row; 31 | curr_col <= "1011"; 32 | WHEN "1011" => 33 | CV3 <= row; 34 | curr_col <= "0111"; 35 | WHEN "0111" => 36 | CV4 <= row; 37 | curr_col <= "1110"; 38 | WHEN OTHERS => 39 | curr_col <= "1110"; 40 | END CASE; 41 | END PROCESS; 42 | -- This process runs whenever any of the column vectors change. Each vector is tested to see 43 | -- if there are any '0's in the vector. This would indicate that a button had been pushed in 44 | -- that column. If so, the value of the button is output and the hit signal is assereted. If 45 | -- not button is pushed, the hit signal is cleared 46 | out_proc : PROCESS (CV1, CV2, CV3, CV4) 47 | BEGIN 48 | hit <= '1'; 49 | IF CV1(1) = '0' THEN 50 | value <= X"1"; 51 | ELSIF CV1(2) = '0' THEN 52 | value <= X"4"; 53 | ELSIF CV1(3) = '0' THEN 54 | value <= X"7"; 55 | ELSIF CV1(4) = '0' THEN 56 | value <= X"0"; 57 | ELSIF CV2(1) = '0' THEN 58 | value <= X"2"; 59 | ELSIF CV2(2) = '0' THEN 60 | value <= X"5"; 61 | ELSIF CV2(3) = '0' THEN 62 | value <= X"8"; 63 | ELSIF CV2(4) = '0' THEN 64 | value <= X"F"; 65 | ELSIF CV3(1) = '0' THEN 66 | value <= X"3"; 67 | ELSIF CV3(2) = '0' THEN 68 | value <= X"6"; 69 | ELSIF CV3(3) = '0' THEN 70 | value <= X"9"; 71 | ELSIF CV3(4) = '0' THEN 72 | value <= X"E"; 73 | ELSIF CV4(1) = '0' THEN 74 | value <= X"A"; 75 | ELSIF CV4(2) = '0' THEN 76 | value <= X"B"; 77 | ELSIF CV4(3) = '0' THEN 78 | value <= X"C"; 79 | ELSIF CV4(4) = '0' THEN 80 | value <= X"D"; 81 | ELSE 82 | hit <= '0'; 83 | value <= X"0"; 84 | END IF; 85 | END PROCESS; 86 | col <= curr_col; 87 | END Behavioral; 88 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/kypd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-4/kypd.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-4/leddec16.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec16 IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- which digit to currently display 7 | data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit (4-digit) data 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- which anode to turn on 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- segment code for current digit 10 | END leddec16; 11 | 12 | ARCHITECTURE Behavioral OF leddec16 IS 13 | SIGNAL data4 : STD_LOGIC_VECTOR (3 DOWNTO 0); -- binary value of current digit 14 | BEGIN 15 | -- Select digit data to be displayed in this mpx period 16 | data4 <= data(3 DOWNTO 0) WHEN dig = "000" ELSE -- digit 0 17 | data(7 DOWNTO 4) WHEN dig = "001" ELSE -- digit 1 18 | data(11 DOWNTO 8) WHEN dig = "010" ELSE -- digit 2 19 | data(15 DOWNTO 12); -- digit 3 20 | -- Turn on segments corresponding to 4-bit data word 21 | seg <= "0000001" WHEN data4 = "0000" ELSE -- 0 22 | "1001111" WHEN data4 = "0001" ELSE -- 1 23 | "0010010" WHEN data4 = "0010" ELSE -- 2 24 | "0000110" WHEN data4 = "0011" ELSE -- 3 25 | "1001100" WHEN data4 = "0100" ELSE -- 4 26 | "0100100" WHEN data4 = "0101" ELSE -- 5 27 | "0100000" WHEN data4 = "0110" ELSE -- 6 28 | "0001111" WHEN data4 = "0111" ELSE -- 7 29 | "0000000" WHEN data4 = "1000" ELSE -- 8 30 | "0000100" WHEN data4 = "1001" ELSE -- 9 31 | "0001000" WHEN data4 = "1010" ELSE -- A 32 | "1100000" WHEN data4 = "1011" ELSE -- B 33 | "0110001" WHEN data4 = "1100" ELSE -- C 34 | "1000010" WHEN data4 = "1101" ELSE -- D 35 | "0110000" WHEN data4 = "1110" ELSE -- E 36 | "0111000" WHEN data4 = "1111" ELSE -- F 37 | "1111111"; 38 | -- Turn on anode of 7-segment display addressed by 3-bit digit selector dig 39 | anode <= "11111110" WHEN dig = "000" ELSE -- 0 40 | "11111101" WHEN dig = "001" ELSE -- 1 41 | "11111011" WHEN dig = "010" ELSE -- 2 42 | "11110111" WHEN dig = "011" ELSE -- 3 43 | -- "11101111" WHEN dig = "100" ELSE -- 4 44 | -- "11011111" WHEN dig = "101" ELSE -- 5 45 | -- "10111111" WHEN dig = "110" ELSE -- 6 46 | -- "01111111" WHEN dig = "111" ELSE -- 7 47 | "11111111"; 48 | END Behavioral; 49 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/Modifications/README.md: -------------------------------------------------------------------------------- 1 | # Modified Design 2 | 3 | * tone_1.vhd: tone_select, btn_press, data_sq 4 | 5 | * wail_1.vhd: btn_press 6 | 7 | * siren_1.vhd: left and right channels 8 | 9 | * siren_1.xdc: BTNU (M18), SW0-SW7 10 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/Modifications/siren_1.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | entity siren is 6 | Port ( clk_50MHz : in STD_LOGIC; -- system clock (50 MHz) 7 | BTN0 : in STD_LOGIC; 8 | SW0 : IN STD_LOGIC; 9 | SW1 : IN STD_LOGIC; 10 | SW2 : IN STD_LOGIC; 11 | SW3 : IN STD_LOGIC; 12 | SW4 : IN STD_LOGIC; 13 | SW5 : IN STD_LOGIC; 14 | SW6 : IN STD_LOGIC; 15 | SW7 : IN STD_LOGIC; 16 | dac_MCLK : out STD_LOGIC; -- outputs to PMODI2L DAC 17 | dac_LRCK : out STD_LOGIC; 18 | dac_SCLK : out STD_LOGIC; 19 | dac_SDIN : out STD_LOGIC); 20 | end siren; 21 | 22 | architecture Behavioral of siren is 23 | 24 | constant lo_tone: UNSIGNED (13 downto 0) := to_unsigned (50, 14); -- lower limit of siren = 256 Hz 25 | constant hi_tone: UNSIGNED (13 downto 0) := to_unsigned (1000, 14); -- upper limit of siren = 512 Hz 26 | signal wail_speed: UNSIGNED (7 downto 0) := to_unsigned (8, 8); -- sets wailing speed 27 | 28 | 29 | component dac_if is 30 | Port ( SCLK : in STD_LOGIC; 31 | L_start: in STD_LOGIC; 32 | R_start: in STD_LOGIC; 33 | L_data : in signed (15 downto 0); 34 | R_data : in signed (15 downto 0); 35 | SDATA : out STD_LOGIC); 36 | end component; 37 | 38 | component wail is 39 | Port ( lo_pitch : in UNSIGNED (13 downto 0); 40 | hi_pitch : in UNSIGNED (13 downto 0); 41 | wspeed : in UNSIGNED (7 downto 0); 42 | wclk : in STD_LOGIC; 43 | audio_clk : in STD_LOGIC; 44 | button_press : in STD_LOGIC; 45 | audio_data : out SIGNED (15 downto 0)); 46 | end component; 47 | 48 | signal tcount: unsigned (19 downto 0) := (others=>'0'); -- timing counter 49 | signal data_L, data_R: SIGNED (15 downto 0); -- 16-bit signed audio data 50 | signal dac_load_L, dac_load_R: STD_LOGIC; -- timing pulses to load DAC shift reg. 51 | signal slo_clk, sclk, audio_CLK: STD_LOGIC; 52 | 53 | begin 54 | 55 | -- this process sets up a 20 bit binary counter clocked at 50MHz. This is used 56 | -- to generate all necessary timing signals. dac_load_L and dac_load_R are pulses 57 | -- sent to dac_if to load parallel data into shift register for serial clocking 58 | -- out to DAC 59 | tim_pr: process 60 | begin 61 | wait until rising_edge(clk_50MHz); 62 | if (tcount(9 downto 0) >= X"00F") and (tcount(9 downto 0) < X"02E") then 63 | dac_load_L <= '1'; else dac_load_L <= '0'; 64 | end if; 65 | if (tcount(9 downto 0) >= X"20F") and (tcount(9 downto 0) < X"22E") then 66 | dac_load_R <= '1'; else dac_load_R <= '0'; 67 | end if; 68 | tcount <= tcount+1; 69 | end process; 70 | 71 | dac_MCLK <= not tcount(1); -- DAC master clock (12.5 MHz) 72 | audio_CLK <= tcount(9); -- audio sampling rate (48.8 kHz) 73 | dac_LRCK <= audio_CLK; -- also sent to DAC as left/right clock 74 | sclk <= tcount(4); -- serial data clock (1.56 MHz) 75 | dac_SCLK <= sclk; -- also sent to DAC as SCLK 76 | slo_clk <= tcount(19); -- clock to control wailing of tone (47.6 Hz) 77 | wail_speed(0) <= SW0; 78 | wail_speed(1) <= SW1; 79 | wail_speed(2) <= SW2; 80 | wail_speed(3) <= SW3; 81 | wail_speed(4) <= SW4; 82 | wail_speed(5) <= SW5; 83 | wail_speed(6) <= SW6; 84 | wail_speed(7) <= SW7; 85 | dac: dac_if port map ( SCLK => sclk, -- instantiate parallel to serial DAC interface 86 | L_start => dac_load_L, 87 | R_start => dac_load_R, 88 | L_data => data_L, 89 | R_data => data_R, 90 | SDATA => dac_SDIN ); 91 | 92 | w1: wail port map( lo_pitch => lo_tone, -- instantiate wailing siren 93 | hi_pitch => hi_tone, 94 | wspeed => wail_speed, 95 | wclk => slo_clk, 96 | button_press => BTN0, 97 | audio_clk => audio_clk, 98 | audio_data => data_L); 99 | w2: wail port map( lo_pitch => hi_tone, -- instantiate wailing siren 100 | hi_pitch => lo_tone, 101 | wspeed => wail_speed, 102 | wclk => slo_clk, 103 | button_press => BTN0, 104 | audio_clk => audio_clk, 105 | audio_data => data_R); 106 | --data_R <= data_L; -- duplicate data on right channel 107 | 108 | end Behavioral; 109 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/Modifications/siren_1.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk_50MHz -period 20.00 [get_ports clk_50MHz] 2 | 3 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports clk_50MHz] 4 | 5 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { dac_LRCK }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 6 | 7 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { dac_SCLK }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 8 | 9 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { dac_SDIN }]; #IO_L18N_T2_A23_15 Sch=ja[4] 10 | 11 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { dac_MCLK }]; #IO_L20N_T3_A19_15 Sch=ja[1] 12 | 13 | 14 | set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTN0 }]; #IO_L4N_T0_D05_14 Sch=btnu 15 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW0 }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 16 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW1 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 17 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW2 }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 18 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW3 }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 19 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW4 }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 20 | set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW5 }]; #IO_L7N_T1_D10_14 Sch=sw[5] 21 | set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW6 }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] 22 | set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW7 }]; #IO_L5N_T0_D07_14 Sch=sw[7] 23 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/Modifications/tone_1.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | -- Generates a 16-bit signed triangle wave sequence at a sampling rate determined 6 | -- by input clk and with a frequency of (clk*pitch)/65,536 7 | entity tone is 8 | Port ( clk : in STD_LOGIC; -- 48.8 kHz audio sampling clock 9 | pitch : in UNSIGNED (13 downto 0); -- frequency (in units of 0.745 Hz) 10 | btn_press : in STD_LOGIC; 11 | data : out SIGNED (15 downto 0)); -- signed triangle wave out 12 | end tone; 13 | 14 | architecture Behavioral of tone is 15 | 16 | signal count: unsigned (15 downto 0); -- represents current phase of waveform 17 | signal quad: std_logic_vector (1 downto 0); -- current quadrant of phase 18 | signal index: signed (15 downto 0); -- index into current quadrant 19 | 20 | signal data_sq:SIGNED(15 downto 0); 21 | signal data_tri:SIGNED(15 downto 0); 22 | 23 | begin 24 | 25 | -- This process adds "pitch" to the current phase every sampling period. Generates 26 | -- an unsigned 16-bit sawtooth waveform. Frequency is determined by pitch. For 27 | -- example when pitch=1, then frequency will be 0.745 Hz. When pitch=16,384, frequency 28 | -- will be 12.2 kHz. 29 | cnt_pr: process 30 | begin 31 | wait until rising_edge(clk); 32 | count <= count + pitch; 33 | end process; 34 | 35 | quad <= std_logic_vector (count (15 downto 14)); -- splits count range into 4 phases 36 | index <= signed ("00" & count (13 downto 0)); -- 14-bit index into the current phase 37 | 38 | -- This select statement converts an unsigned 16-bit sawtooth that ranges from 65,535 39 | -- into a signed 12-bit triangle wave that ranges from -16,383 to +16,383 40 | 41 | with quad select 42 | data_sq <= to_signed(16383,16) when "00", 43 | to_signed(-16383,16) when "01", 44 | to_signed(16383,16) when "10", 45 | to_signed(-16383,16) when others; 46 | with quad select 47 | data_tri <= index when "00", 48 | 16383 - index when "01", 49 | 0 - index when "10", 50 | index - 16383 when others; 51 | --with quad select 52 | --data <= index when "00", -- 1st quadrant 53 | --16383 - index when "01", -- 2nd quadrant 54 | --0 - index when "10", -- 3rd quadrant 55 | --index - 16383 when others; -- 4th quadrant 56 | 57 | tone_select: process 58 | begin 59 | if btn_press = '1' then 60 | data <= data_sq; 61 | else 62 | data <= data_tri; 63 | end if; 64 | end process; 65 | 66 | end Behavioral; 67 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/Modifications/wail_1.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | -- Generates a "wailing siren" sound by instancing a "tone" module and modulating 6 | -- the pitch of the tone. The pitch is increased until it reaches hi_pitch and then 7 | -- decreased until it reaches lo_pitch and then increased again, etc. 8 | entity wail is 9 | Port ( lo_pitch : in UNSIGNED (13 downto 0); -- lowest pitch (in units of 0.745 Hz) 10 | hi_pitch : in UNSIGNED (13 downto 0); -- highest pitch (in units of 0.745 Hz) 11 | wspeed : in UNSIGNED (7 downto 0); -- speed of wail in pitch units/wclk 12 | button_press : in STD_LOGIC; 13 | wclk : in STD_LOGIC; -- wailing clock (47.6 Hz) 14 | audio_clk : in STD_LOGIC; -- audio sampling clock (48.8 kHz) 15 | audio_data : out SIGNED (15 downto 0)); -- output audio sequence (wailing tone) 16 | end wail; 17 | 18 | architecture Behavioral of wail is 19 | 20 | component tone is 21 | Port ( clk : in STD_LOGIC; 22 | pitch : in UNSIGNED (13 downto 0); 23 | btn_press : in STD_LOGIC; 24 | data : out SIGNED (15 downto 0)); 25 | end component; 26 | 27 | signal curr_pitch: UNSIGNED (13 downto 0); -- current wailing pitch 28 | 29 | begin 30 | 31 | -- this process modulates the current pitch. It keep a variable updn to indicate 32 | -- whether tone is currently rising or falling. Each wclk period it increments 33 | -- (or decrements) the current pitch by wspeed. When it reaches hi_pitch, it 34 | -- starts counting down. When it reaches lo_pitch, it starts counting up 35 | wp: process 36 | variable updn: std_logic; 37 | begin 38 | wait until rising_edge(wclk); 39 | if curr_pitch >= hi_pitch then updn :='0'; -- check to see if still in range 40 | elsif curr_pitch <= lo_pitch then updn := '1'; -- if not, adjust updn 41 | end if; 42 | if updn = '1' then curr_pitch <= curr_pitch + wspeed; -- modulate pitch according to 43 | else curr_pitch <= curr_pitch - wspeed; -- current value of updn 44 | end if; 45 | end process; 46 | 47 | tgen: tone port map(clk => audio_clk, -- instance a tone module 48 | btn_press => button_press, 49 | pitch => curr_pitch, -- use curr-pitch to modulate tone 50 | data => audio_data); 51 | 52 | end Behavioral; 53 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/dac_if.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | ENTITY dac_if IS 6 | PORT ( 7 | SCLK : IN STD_LOGIC; -- serial clock (1.56 MHz) 8 | L_start : IN STD_LOGIC; -- strobe to load LEFT data 9 | R_start : IN STD_LOGIC; -- strobe to load RIGHT data 10 | L_data : IN SIGNED (15 DOWNTO 0); -- LEFT data (15-bit signed) 11 | R_data : IN SIGNED (15 DOWNTO 0); -- RIGHT data (15-bit signed) 12 | SDATA : OUT STD_LOGIC); -- serial data stream to DAC 13 | END dac_if; 14 | 15 | ARCHITECTURE Behavioral OF dac_if IS 16 | SIGNAL sreg : STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit shift register to do 17 | -- parallel to serial conversion 18 | BEGIN 19 | -- SREG is used to serially shift data out to DAC, MSBit first. 20 | -- Left data is loaded into SREG on falling edge of SCLK when L_start is active. 21 | -- Right data is loaded into SREG on falling edge of SCLK when R_start is active. 22 | -- At other times, falling edge of SCLK causes REG to logically shift one bit left 23 | -- Serial data to DAC is MSBit of SREG 24 | dac_proc : PROCESS 25 | BEGIN 26 | WAIT UNTIL falling_edge(SCLK); 27 | IF L_start = '1' THEN 28 | sreg <= std_logic_vector (L_data); -- load LEFT data into SREG 29 | ELSIF R_start = '1' THEN 30 | sreg <= std_logic_vector (R_data); -- load RIGHT data into SREG 31 | ELSE 32 | sreg <= sreg(14 DOWNTO 0) & '0'; -- logically shift SREG one bit left 33 | END IF; 34 | END PROCESS; 35 | SDATA <= sreg(15); -- serial data to DAC is MSBit of SREG 36 | END Behavioral; 37 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/i2s.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-5/i2s.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/i2s2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-5/i2s2.jpg -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/siren.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | ENTITY siren IS 6 | PORT ( 7 | clk_50MHz : IN STD_LOGIC; -- system clock (50 MHz) 8 | dac_MCLK : OUT STD_LOGIC; -- outputs to PMODI2L DAC 9 | dac_LRCK : OUT STD_LOGIC; 10 | dac_SCLK : OUT STD_LOGIC; 11 | dac_SDIN : OUT STD_LOGIC 12 | ); 13 | END siren; 14 | 15 | ARCHITECTURE Behavioral OF siren IS 16 | CONSTANT lo_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (344, 14); -- lower limit of siren = 256 Hz 17 | CONSTANT hi_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (687, 14); -- upper limit of siren = 512 Hz 18 | CONSTANT wail_speed : UNSIGNED (7 DOWNTO 0) := to_unsigned (8, 8); -- sets wailing speed 19 | COMPONENT dac_if IS 20 | PORT ( 21 | SCLK : IN STD_LOGIC; 22 | L_start : IN STD_LOGIC; 23 | R_start : IN STD_LOGIC; 24 | L_data : IN signed (15 DOWNTO 0); 25 | R_data : IN signed (15 DOWNTO 0); 26 | SDATA : OUT STD_LOGIC 27 | ); 28 | END COMPONENT; 29 | COMPONENT wail IS 30 | PORT ( 31 | lo_pitch : IN UNSIGNED (13 DOWNTO 0); 32 | hi_pitch : IN UNSIGNED (13 DOWNTO 0); 33 | wspeed : IN UNSIGNED (7 DOWNTO 0); 34 | wclk : IN STD_LOGIC; 35 | audio_clk : IN STD_LOGIC; 36 | audio_data : OUT SIGNED (15 DOWNTO 0) 37 | ); 38 | END COMPONENT; 39 | SIGNAL tcount : unsigned (19 DOWNTO 0) := (OTHERS => '0'); -- timing counter 40 | SIGNAL data_L, data_R : SIGNED (15 DOWNTO 0); -- 16-bit signed audio data 41 | SIGNAL dac_load_L, dac_load_R : STD_LOGIC; -- timing pulses to load DAC shift reg. 42 | SIGNAL slo_clk, sclk, audio_CLK : STD_LOGIC; 43 | BEGIN 44 | -- this process sets up a 20 bit binary counter clocked at 50MHz. This is used 45 | -- to generate all necessary timing signals. dac_load_L and dac_load_R are pulses 46 | -- sent to dac_if to load parallel data into shift register for serial clocking 47 | -- out to DAC 48 | tim_pr : PROCESS 49 | BEGIN 50 | WAIT UNTIL rising_edge(clk_50MHz); 51 | IF (tcount(9 DOWNTO 0) >= X"00F") AND (tcount(9 DOWNTO 0) < X"02E") THEN 52 | dac_load_L <= '1'; 53 | ELSE 54 | dac_load_L <= '0'; 55 | END IF; 56 | IF (tcount(9 DOWNTO 0) >= X"20F") AND (tcount(9 DOWNTO 0) < X"22E") THEN 57 | dac_load_R <= '1'; 58 | ELSE dac_load_R <= '0'; 59 | END IF; 60 | tcount <= tcount + 1; 61 | END PROCESS; 62 | dac_MCLK <= NOT tcount(1); -- DAC master clock (12.5 MHz) 63 | audio_CLK <= tcount(9); -- audio sampling rate (48.8 kHz) 64 | dac_LRCK <= audio_CLK; -- also sent to DAC as left/right clock 65 | sclk <= tcount(4); -- serial data clock (1.56 MHz) 66 | dac_SCLK <= sclk; -- also sent to DAC as SCLK 67 | slo_clk <= tcount(19); -- clock to control wailing of tone (47.6 Hz) 68 | dac : dac_if 69 | PORT MAP( 70 | SCLK => sclk, -- instantiate parallel to serial DAC interface 71 | L_start => dac_load_L, 72 | R_start => dac_load_R, 73 | L_data => data_L, 74 | R_data => data_R, 75 | SDATA => dac_SDIN 76 | ); 77 | w1 : wail 78 | PORT MAP( 79 | lo_pitch => lo_tone, -- instantiate wailing siren 80 | hi_pitch => hi_tone, 81 | wspeed => wail_speed, 82 | wclk => slo_clk, 83 | audio_clk => audio_clk, 84 | audio_data => data_L 85 | ); 86 | data_R <= data_L; -- duplicate data on right channel 87 | END Behavioral; 88 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/siren.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk_50MHz -period 20.00 [get_ports clk_50MHz] 2 | 3 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports clk_50MHz] 4 | 5 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { dac_LRCK }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 6 | 7 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { dac_SCLK }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 8 | 9 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { dac_SDIN }]; #IO_L18N_T2_A23_15 Sch=ja[4] 10 | 11 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { dac_MCLK }]; #IO_L20N_T3_A19_15 Sch=ja[1] 12 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/tone.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | -- Generates a 16-bit signed triangle wave sequence at a sampling rate determined 6 | -- by input clk and with a frequency of (clk*pitch)/65,536 7 | ENTITY tone IS 8 | PORT ( 9 | clk : IN STD_LOGIC; -- 48.8 kHz audio sampling clock 10 | pitch : IN UNSIGNED (13 DOWNTO 0); -- frequency (in units of 0.745 Hz) 11 | data : OUT SIGNED (15 DOWNTO 0)); -- signed triangle wave out 12 | END tone; 13 | 14 | ARCHITECTURE Behavioral OF tone IS 15 | SIGNAL count : unsigned (15 DOWNTO 0); -- represents current phase of waveform 16 | SIGNAL quad : std_logic_vector (1 DOWNTO 0); -- current quadrant of phase 17 | SIGNAL index : signed (15 DOWNTO 0); -- index into current quadrant 18 | BEGIN 19 | -- This process adds "pitch" to the current phase every sampling period. Generates 20 | -- an unsigned 16-bit sawtooth waveform. Frequency is determined by pitch. For 21 | -- example when pitch=1, then frequency will be 0.745 Hz. When pitch=16,384, frequency 22 | -- will be 12.2 kHz. 23 | cnt_pr : PROCESS 24 | BEGIN 25 | WAIT UNTIL rising_edge(clk); 26 | count <= count + pitch; 27 | END PROCESS; 28 | quad <= std_logic_vector (count (15 DOWNTO 14)); -- splits count range into 4 phases 29 | index <= signed ("00" & count (13 DOWNTO 0)); -- 14-bit index into the current phase 30 | -- This select statement converts an unsigned 16-bit sawtooth that ranges from 65,535 31 | -- into a signed 12-bit triangle wave that ranges from -16,383 to +16,383 32 | WITH quad SELECT 33 | data <= index WHEN "00", -- 1st quadrant 34 | 16383 - index WHEN "01", -- 2nd quadrant 35 | 0 - index WHEN "10", -- 3rd quadrant 36 | index - 16383 WHEN OTHERS; -- 4th quadrant 37 | END Behavioral; 38 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/wail.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.NUMERIC_STD.ALL; 4 | 5 | -- Generates a "wailing siren" sound by instancing a "tone" module and modulating 6 | -- the pitch of the tone. The pitch is increased until it reaches hi_pitch and then 7 | -- decreased until it reaches lo_pitch and then increased again, etc. 8 | ENTITY wail IS 9 | PORT ( 10 | lo_pitch : IN UNSIGNED (13 DOWNTO 0); -- lowest pitch (in units of 0.745 Hz) 11 | hi_pitch : IN UNSIGNED (13 DOWNTO 0); -- highest pitch (in units of 0.745 Hz) 12 | wspeed : IN UNSIGNED (7 DOWNTO 0); -- speed of wail in pitch units/wclk 13 | wclk : IN STD_LOGIC; -- wailing clock (47.6 Hz) 14 | audio_clk : IN STD_LOGIC; -- audio sampling clock (48.8 kHz) 15 | audio_data : OUT SIGNED (15 DOWNTO 0)); -- output audio sequence (wailing tone) 16 | END wail; 17 | 18 | ARCHITECTURE Behavioral OF wail IS 19 | COMPONENT tone IS 20 | PORT ( 21 | clk : IN STD_LOGIC; 22 | pitch : IN UNSIGNED (13 DOWNTO 0); 23 | data : OUT SIGNED (15 DOWNTO 0) 24 | ); 25 | END COMPONENT; 26 | SIGNAL curr_pitch : UNSIGNED (13 DOWNTO 0); -- current wailing pitch 27 | BEGIN 28 | -- this process modulates the current pitch. It keep a variable updn to indicate 29 | -- whether tone is currently rising or falling. Each wclk period it increments 30 | -- (or decrements) the current pitch by wspeed. When it reaches hi_pitch, it 31 | -- starts counting down. When it reaches lo_pitch, it starts counting up 32 | wp : PROCESS 33 | VARIABLE updn : std_logic; 34 | BEGIN 35 | WAIT UNTIL rising_edge(wclk); 36 | IF curr_pitch >= hi_pitch THEN 37 | updn := '0'; -- check to see if still in range 38 | ELSIF curr_pitch <= lo_pitch THEN 39 | updn := '1'; -- if not, adjust updn 40 | END IF; 41 | IF updn = '1' THEN 42 | curr_pitch <= curr_pitch + wspeed; -- modulate pitch according to 43 | ELSE 44 | curr_pitch <= curr_pitch - wspeed; -- current value of updn 45 | END IF; 46 | END PROCESS; 47 | tgen : tone 48 | PORT MAP( 49 | clk => audio_clk, -- instance a tone module 50 | pitch => curr_pitch, -- use curr-pitch to modulate tone 51 | data => audio_data 52 | ); 53 | END Behavioral; 54 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-5/wave.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-5/wave.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/Alternative/README.md: -------------------------------------------------------------------------------- 1 | # Alternative Design 2 | 3 | ## Using BTNL and BTNR instead of Pmod AD1 and potentiometer 4 | 5 | * pong_2.vhd 6 | * Set bat position and speed 7 | * Need bat_n_ball_1.vhd and leddec16.vhd 8 | * No need for adc_if.vhd 9 | 10 | * pong_2.xdc 11 | * Add ports btnl and btnr 12 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/Alternative/pong_2.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {clk_in}]; 2 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_in}]; 3 | 4 | set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_hsync }]; #IO_L4P_T0_15 Sch=vga_hs 5 | set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 6 | 7 | set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 8 | set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 9 | set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[2] }]; 10 | set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[3] }]; 11 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 12 | set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 13 | set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 14 | set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[3] }]; 15 | set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 16 | set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 17 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 18 | set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[3] }]; 19 | 20 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L9P_T1_DQS_14 Sch=btnc 21 | set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl 22 | set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr 23 | 24 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 25 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 26 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 27 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 28 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 29 | 30 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[0]}] 31 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[1]}] 32 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[2]}] 33 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[3]}] 34 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[4]}] 35 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[5]}] 36 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[6]}] 37 | 38 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[7]}] 39 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[6]}] 40 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[5]}] 41 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[4]}] 42 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[3]}] 43 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[2]}] 44 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[1]}] 45 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[0]}] 46 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/Modifications/README.md: -------------------------------------------------------------------------------- 1 | # Modified Design 2 | 3 | * bat_n_ball_1.vhd 4 | 5 | * The bat width decreases one pixel each time successfully hitting the ball and then resets to starting width when missing the ball 6 | 7 | * Count the number of successful hits after each serve and display the count on the 7-segment displays 8 | 9 | * Leddec16.vhd 10 | 11 | * pong_1.vhd 12 | 13 | * Use the slide switches on the board to program the ball speed 14 | 15 | * **WARNING: Avoid setting the speed to zero as the ball will then never reach the bat or wall** 16 | 17 | * pong_1.xdc: 7-segment displays 18 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/Modifications/leddec16.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | 4 | ENTITY leddec16 IS 5 | PORT ( 6 | dig : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- which digit to currently display 7 | data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit (4-digit) data 8 | anode : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- which anode to turn on 9 | seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- segment code for current digit 10 | END leddec16; 11 | 12 | ARCHITECTURE Behavioral OF leddec16 IS 13 | SIGNAL data4 : STD_LOGIC_VECTOR (3 DOWNTO 0); -- binary value of current digit 14 | BEGIN 15 | -- Select digit data to be displayed in this mpx period 16 | data4 <= data(3 DOWNTO 0) WHEN dig = "000" ELSE -- digit 0 17 | data(7 DOWNTO 4) WHEN dig = "001" ELSE -- digit 1 18 | data(11 DOWNTO 8) WHEN dig = "010" ELSE -- digit 2 19 | data(15 DOWNTO 12); --digit 3 20 | -- Turn on segments corresponding to 4-bit data word 21 | seg <= "0000001" WHEN data4 = "0000" ELSE -- 0 22 | "1001111" WHEN data4 = "0001" ELSE -- 1 23 | "0010010" WHEN data4 = "0010" ELSE -- 2 24 | "0000110" WHEN data4 = "0011" ELSE -- 3 25 | "1001100" WHEN data4 = "0100" ELSE -- 4 26 | "0100100" WHEN data4 = "0101" ELSE -- 5 27 | "0100000" WHEN data4 = "0110" ELSE -- 6 28 | "0001111" WHEN data4 = "0111" ELSE -- 7 29 | "0000000" WHEN data4 = "1000" ELSE -- 8 30 | "0000100" WHEN data4 = "1001" ELSE -- 9 31 | "0001000" WHEN data4 = "1010" ELSE -- A 32 | "1100000" WHEN data4 = "1011" ELSE -- B 33 | "0110001" WHEN data4 = "1100" ELSE -- C 34 | "1000010" WHEN data4 = "1101" ELSE -- D 35 | "0110000" WHEN data4 = "1110" ELSE -- E 36 | "0111000" WHEN data4 = "1111" ELSE -- F 37 | "1111111"; 38 | -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig 39 | anode <= "11111110" WHEN dig = "000" and data /= X"0000" ELSE -- digit 0 40 | "11111101" WHEN dig = "001" and data(15 downto 4) /= X"000" ELSE -- digit 1 41 | "11111011" WHEN dig = "010" and data(15 downto 8) /= X"00" ELSE -- digit 2 42 | "11110111" WHEN dig = "011" and data(15 downto 12) /= X"0" ELSE -- digit 3 43 | "11111111"; 44 | END Behavioral; 45 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/Modifications/pong_1.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {clk_in}]; 2 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_in}]; 3 | 4 | set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_hsync }]; #IO_L4P_T0_15 Sch=vga_hs 5 | set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 6 | 7 | set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 8 | set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 9 | set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[2] }]; 10 | set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[3] }]; 11 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 12 | set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 13 | set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 14 | set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[3] }]; 15 | set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 16 | set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 17 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 18 | set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[3] }]; 19 | 20 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA1 }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 21 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA2 }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 22 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ADC_SCLK }]; #IO_L18N_T2_A23_15 Sch=ja[4] 23 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ADC_CS }]; #IO_L20N_T3_A19_15 Sch=ja[1] 24 | 25 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L9P_T1_DQS_14 Sch=btnc 26 | 27 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 28 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 29 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 30 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 31 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 32 | 33 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[0]}] 34 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[1]}] 35 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[2]}] 36 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[3]}] 37 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[4]}] 38 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[5]}] 39 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[6]}] 40 | 41 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[7]}] 42 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[6]}] 43 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[5]}] 44 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[4]}] 45 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[3]}] 46 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[2]}] 47 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[1]}] 48 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[0]}] 49 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/ad1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-6/ad1.jpg -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/adc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-6/adc.png -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/adc_if.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY adc_if IS 6 | PORT ( 7 | SCK : IN STD_LOGIC; -- serial clock that goes to ADC 8 | SDATA1 : IN STD_LOGIC; -- serial data channel 1 9 | SDATA2 : IN STD_LOGIC; -- serial data channel 2 10 | CS : IN STD_LOGIC; -- chip select that initiates A/D conversion 11 | data_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- parallel 12-bit data ch1 12 | data_2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); -- parallel 12-bit data ch2 13 | END adc_if; 14 | 15 | ARCHITECTURE Behavioral OF adc_if IS 16 | SIGNAL pdata1, pdata2 : std_logic_vector (11 DOWNTO 0); -- 12-bit shift registers 17 | BEGIN 18 | -- this process waits for CS=0 and then clocks serial data from ADC into shift register 19 | -- MSBit first. After 16 SCK's, four leading zeros will have fallen out of the most significant 20 | -- end of the shift register and the register will contain the parallel 12-bit data 21 | adpr : PROCESS 22 | BEGIN 23 | WAIT UNTIL falling_edge (SCK); 24 | IF CS = '0' THEN 25 | pdata1 <= pdata1 (10 DOWNTO 0) & SDATA1; 26 | pdata2 <= pdata2 (10 DOWNTO 0) & SDATA2; 27 | END IF; 28 | END PROCESS; 29 | -- this process waits for rising edge of CS and then loads parallel data 30 | -- from shift register into appropriate output port 31 | sync : PROCESS 32 | BEGIN 33 | WAIT UNTIL rising_edge (CS); 34 | data_1 <= pdata1; 35 | data_2 <= pdata2; 36 | END PROCESS; 37 | END Behavioral; 38 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/knob.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-6/knob.jpg -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/pong.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {clk_in}]; 2 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_in}]; 3 | 4 | set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_hsync }]; #IO_L4P_T0_15 Sch=vga_hs 5 | set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 6 | 7 | set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 8 | set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 9 | set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[2] }] 10 | set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[3] }] 11 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 12 | set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 13 | set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 14 | set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[3] }] 15 | set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 16 | set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 17 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 18 | set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[3] }] 19 | 20 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA1 }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 21 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA2 }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 22 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ADC_SCLK }]; #IO_L18N_T2_A23_15 Sch=ja[4] 23 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ADC_CS }]; #IO_L20N_T3_A19_15 Sch=ja[1] 24 | 25 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L9P_T1_DQS_14 Sch=btnc 26 | -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/potentiometer.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/Lab-6/potentiometer.jpg -------------------------------------------------------------------------------- /Nexys-A7/Lab-6/vga_sync.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.STD_LOGIC_1164.ALL; 3 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | 5 | ENTITY vga_sync IS 6 | PORT ( 7 | pixel_clk : IN STD_LOGIC; 8 | red_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 9 | green_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 10 | blue_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 11 | red_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 12 | green_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 13 | blue_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); 14 | hsync : OUT STD_LOGIC; 15 | vsync : OUT STD_LOGIC; 16 | pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); 17 | pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) 18 | ); 19 | END vga_sync; 20 | 21 | ARCHITECTURE Behavioral OF vga_sync IS 22 | SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (10 DOWNTO 0); 23 | 24 | CONSTANT H : INTEGER := 800; 25 | CONSTANT V : INTEGER := 600; 26 | CONSTANT H_FP : INTEGER := 40; 27 | CONSTANT H_BP : INTEGER := 88; 28 | CONSTANT H_SYNC : INTEGER := 128; 29 | CONSTANT V_FP : INTEGER := 1; 30 | CONSTANT V_BP : INTEGER := 23; 31 | CONSTANT V_SYNC : INTEGER := 4; 32 | 33 | CONSTANT FREQ : INTEGER := 60; 34 | 35 | BEGIN 36 | sync_pr : PROCESS 37 | VARIABLE video_on : STD_LOGIC; 38 | BEGIN 39 | WAIT UNTIL rising_edge(pixel_clk); 40 | -- Generate Horizontal Timing Signals for Video Signal 41 | -- total horizontal line width = H + H_FP + H_SYNC + H_BP 42 | -- Reset h_cnt when at end of line 43 | IF (h_cnt >= H + H_FP + H_SYNC + H_BP - 1) THEN 44 | h_cnt <= (others => '0'); 45 | ELSE 46 | h_cnt <= h_cnt + 1; 47 | END IF; 48 | -- Pull down hsync after front porch 49 | IF (h_cnt >= H + H_FP) AND (h_cnt <= H + H_FP + H_SYNC) THEN 50 | hsync <= '0'; 51 | ELSE 52 | hsync <= '1'; 53 | END IF; 54 | 55 | IF (v_cnt >= V + V_FP + V_SYNC + V_BP - 1) AND (h_cnt = H + FREQ - 1) THEN 56 | v_cnt <= (others => '0'); 57 | ELSIF (h_cnt = H + FREQ - 1) THEN 58 | v_cnt <= v_cnt + 1; 59 | END IF; 60 | IF (v_cnt >= V + V_FP) AND (v_cnt <= V + V_FP + V_SYNC) THEN 61 | vsync <= '0'; 62 | ELSE 63 | vsync <= '1'; 64 | END IF; 65 | -- Generate Video Signals and Pixel Address 66 | IF (h_cnt < H) AND (v_cnt < V) THEN 67 | video_on := '1'; 68 | ELSE 69 | video_on := '0'; 70 | END IF; 71 | pixel_col <= h_cnt; 72 | pixel_row <= v_cnt; 73 | -- Register video to clock edge and suppress video during blanking and sync periods 74 | if video_on = '1' then 75 | red_out <= red_in; 76 | green_out <= green_in; 77 | blue_out <= blue_in; 78 | else 79 | red_out <= "0000"; 80 | green_out <= "0000"; 81 | blue_out <= "0000"; 82 | end if; 83 | END PROCESS; 84 | END Behavioral; 85 | -------------------------------------------------------------------------------- /Nexys-A7/install-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/install-1.png -------------------------------------------------------------------------------- /Nexys-A7/install-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/Nexys-A7/install-2.png -------------------------------------------------------------------------------- /TinyFPGA-BX/boot.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/TinyFPGA-BX/boot.gif -------------------------------------------------------------------------------- /TinyFPGA-BX/sos.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/TinyFPGA-BX/sos.gif -------------------------------------------------------------------------------- /TinyFPGA-BX/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | output LED, // User/boot LED next to power LED 5 | output USBPU // USB pull-up resistor 6 | ); 7 | // drive USB pull-up resistor to '0' to disable USB 8 | assign USBPU = 0; 9 | 10 | //////// 11 | // make a simple blink circuit 12 | //////// 13 | 14 | // keep track of time and location in blink_pattern 15 | reg [25:0] blink_counter; 16 | 17 | // pattern that will be flashed over the LED over time 18 | wire [31:0] blink_pattern = 32'b101010001110111011100010101; 19 | 20 | // increment the blink_counter every clock 21 | always @(posedge CLK) begin 22 | blink_counter <= blink_counter + 1; 23 | end 24 | 25 | // light up the LED according to the pattern 26 | assign LED = blink_pattern[blink_counter[25:21]]; 27 | endmodule 28 | -------------------------------------------------------------------------------- /Xilinx/genesys-zu-5ev/C.0/changelog.txt: -------------------------------------------------------------------------------- 1 | 1.1 Fixed PSU__DDRC__DDR4_ADDR_MAPPING appearing twice and with conflicting values that was causing a silent FSBL failure in the boot process. 2 | 1.0. Genesys ZU-ZU5EV initial board support for rev C. 3 | -------------------------------------------------------------------------------- /board_files/README.md: -------------------------------------------------------------------------------- 1 | # Vivado Board Files for NI Digilent FPGA Boards 2 | 3 | [Vivado Board files](https://github.com/Digilent/vivado-boards) and [Xilinx Design Constraints](https://github.com/Digilent/digilent-xdc) (XDC) files including 4 | * [Nexys A7 Artix-7 FPGA Trainer Board](https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/) 5 | * [Basys 3 Artix-7 FPGA Trainer Board](https://store.digilentinc.com/basys-3-artix-7-fpga-beginner-board-recommended-for-introductory-users/) 6 | * [Cmod A7 Breadboardable Artix-7 FPGA Module](https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/) 7 | -------------------------------------------------------------------------------- /circuit/README.md: -------------------------------------------------------------------------------- 1 | # Electronic Circuit 2 | ## YouTube Channels 3 | * [CircuitBread](https://www.youtube.com/@CircuitBread/) 4 | * [Phil's Lab](https://www.youtube.com/@PhilsLab) by [Philip Salmony](https://github.com/pms67) 5 | --- 6 | * [Circuits and Electronics](https://ocw.mit.edu/courses/6-002-circuits-and-electronics-spring-2007/) MIT OpenCourseWare (OCW) 7 | --- 8 | * [Electronic circuit](https://en.wikipedia.org/wiki/Electronic_circuit) 9 | * [Electrical network](https://en.wikipedia.org/wiki/Electrical_network) 10 | * [Network analysis (electrical circuits)](https://en.wikipedia.org/wiki/Network_analysis_(electrical_circuits)) 11 | * [Ohm's law](https://en.wikipedia.org/wiki/Ohm%27s_law) 1827 12 | * [Georg Ohm](https://en.wikipedia.org/wiki/Georg_Ohm) 1789—1854 13 | * [Kirchhoff's circuit laws](https://en.wikipedia.org/wiki/Kirchhoff%27s_circuit_laws) 1845 14 | * [Gustav Kirchhoff](https://en.wikipedia.org/wiki/Gustav_Kirchhoff) 1824—1887 15 | * [Thévenin's theorem](https://en.wikipedia.org/wiki/Th%C3%A9venin%27s_theorem) 1853 and 1883 16 | * [Hermann von Helmholtz](https://en.wikipedia.org/wiki/Hermann_von_Helmholtz) 1821—1894 17 | * [Léon Charles Thévenin](https://en.wikipedia.org/wiki/L%C3%A9on_Charles_Th%C3%A9venin) 1857—1926 18 | * [Norton's theorem](https://en.wikipedia.org/wiki/Norton%27s_theorem) 1926 19 | * [Hans Ferdinand Mayer](https://en.wikipedia.org/wiki/Hans_Ferdinand_Mayer) 1895—1980 20 | * [Edward Lawry Norton](https://en.wikipedia.org/wiki/Edward_Lawry_Norton) 1898—1983 21 | * [Alexander Graham Bell](https://en.wikipedia.org/wiki/Alexander_Graham_Bell) 1847—1922 22 | --- 23 | * [Wheatstone bridge](https://en.wikipedia.org/wiki/Wheatstone_bridge) 1833 and 1843 24 | * [Samuel Hunter Christie](https://en.wikipedia.org/wiki/Samuel_Hunter_Christie) 1784—1865 25 | * [Charles Wheatstone](https://en.wikipedia.org/wiki/Charles_Wheatstone) 1802—1875 26 | --- 27 | * [Differential amplifier](https://en.wikipedia.org/wiki/Differential_amplifier) 28 | * [Operational amplifier](https://en.wikipedia.org/wiki/Operational_amplifier) 29 | * [The Golden Rules of Op-Amps](https://www.circuitbread.com/ee-faq/what-are-the-golden-rules-of-op-amps) 30 | * [Operational amplifier applications](https://en.wikipedia.org/wiki/Operational_amplifier_applications) 31 | * [Karl D. Swartzel Jr.](https://en.wikipedia.org/wiki/Karl_D._Swartzel_Jr.) 1907—1998 32 | * [Negative-feedback amplifier](https://en.wikipedia.org/wiki/Negative-feedback_amplifier) 33 | * [Push–pull output](https://en.wikipedia.org/wiki/Push%E2%80%93pull_output) 34 | * [LM741](https://www.ti.com/lit/ds/symlink/lm741.pdf) 35 | * [LM6172](https://www.ti.com/lit/ds/symlink/lm6172.pdf) 36 | --- 37 | * [Electromagnetic field](https://en.wikipedia.org/wiki/Electromagnetic_field) 38 | * [Radio-frequency engineering](https://en.wikipedia.org/wiki/Radio-frequency_engineering) 39 | * [Radio propagation](https://en.wikipedia.org/wiki/Radio_propagation) 40 | * [Michael Faraday](https://en.wikipedia.org/wiki/Michael_Faraday) 1791—1867 41 | * [James Clerk Maxwell](https://en.wikipedia.org/wiki/James_Clerk_Maxwell) 1831—1879 42 | * [Guglielmo Marconi](https://en.wikipedia.org/wiki/Guglielmo_Marconi) 1874—1937 43 | --- 44 | * [Photonic integrated circuit](https://en.wikipedia.org/wiki/Photonic_integrated_circuit) 45 | * [Isaac Newton](https://en.wikipedia.org/wiki/Isaac_Newton) 1643—1727 46 | * [Albert Einstein](https://en.wikipedia.org/wiki/Albert_Einstein) 1879—1955 47 | * [Charles K. Kao](https://en.wikipedia.org/wiki/Charles_K._Kao) 1933—2018 48 | --- 49 | * [Through-hole technology](https://en.wikipedia.org/wiki/Through-hole_technology) 50 | * [Surface-mount technology](https://en.wikipedia.org/wiki/Surface-mount_technology) (SMT) 51 | * [Jabil](https://en.wikipedia.org/wiki/Jabil) 52 | -------------------------------------------------------------------------------- /code/README.md: -------------------------------------------------------------------------------- 1 | # Code 2 | * [Semiconductor intellectual property core](https://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core) 3 | * [VHDL repositories](https://github.com/search?q=VHDL) 4 | * [VHDL repository](https://github.com/fcayci/vhdl-digital-design) by Dr. [Furkan Çayci](https://tr.linkedin.com/in/fcayci) of [Gebze Technical University](https://en.wikipedia.org/wiki/Gebze_Technical_University) 5 | * [VHDL examples](http://www.csun.edu/edaasic/roosta/VHDL_Examples.pdf) by Prof. [Ramin Roosta](url) of [California State University, Northridge](https://en.wikipedia.org/wiki/California_State_University,_Northridge) (CSUN) 6 | * [VHDL examples](https://lauri.xn--vsandi-pxa.com/search.html#VHDL) by [Lauri Võsandi](https://lauri.xn--vsandi-pxa.com/) 7 | * [Verilog repositories](https://github.com/search?q=Verilog) 8 | * [Verilog for Beginners](https://esrd2014.blogspot.com/) 9 | * [SystemVerilog repositories](https://github.com/search?q=SystemVerilog) 10 | * [SystemVerilog design](https://www.accellera.org/images/resources/videos/systemverilog-design-tutorial-2015.pdf) by Stuart Sutherland 11 | * [SystemVerilog examples](https://github.com/JeffDeCola/my-systemverilog-examples) by Jeff DeCola 12 | * [SystemVerilog examples](https://www.asic-world.com/examples/systemverilog/index.html) by Deepak Kumar Tala 13 | * [SystemVerilog tutorial](https://www.chipverify.com/systemverilog/systemverilog-tutorial) 14 | * [SystemVerilog testbench examples](https://verificationguide.com/systemverilog-examples/systemverilog-testbench-examples/) 15 | * [OpenCores](https://en.wikipedia.org/wiki/OpenCores) 16 | * [opencores.org](https://opencores.org/) 17 | * [Free Range Factory IP Cores](https://github.com/fabriziotappero/ip-cores) 18 | * Arithmetic core 19 | * Prototype board 20 | * Communication controller 21 | * Coprocessor 22 | * [Crypto](https://en.wikipedia.org/wiki/Cryptography) core 23 | * [Digital signal processor](https://en.wikipedia.org/wiki/Digital_signal_processor) (DSP) core 24 | * [Error correction code](https://en.wikipedia.org/wiki/Error_correction_code) (ECC) core 25 | * Library 26 | * Memory core 27 | * Other 28 | * Processor 29 | * [System on a chip](https://en.wikipedia.org/wiki/System_on_a_chip) (SoC) 30 | * [System on module](https://en.wikipedia.org/wiki/System_on_module) (SOM) 31 | * System controller 32 | * Testing/verification 33 | * Video controller 34 | -------------------------------------------------------------------------------- /code/fullAdder.v: -------------------------------------------------------------------------------- 1 | // https://esrd2014.blogspot.com/p/full-adder.html 2 | `timescale 1ns / 1ps 3 | module fullAdder ( In1, 4 | In2, 5 | Cin, 6 | Sum, 7 | Cout 8 | ); 9 | input In1, 10 | In2, 11 | Cin; 12 | output Sum, 13 | Cout; 14 | 15 | assign Sum = (In1 ^ In2) ^ Cin; 16 | assign Cout = (In1 & In2) | (In2 & Cin) | (Cin & In1); 17 | endmodule 18 | -------------------------------------------------------------------------------- /code/fullAdder_tb.v: -------------------------------------------------------------------------------- 1 | // https://esrd2014.blogspot.com/p/full-adder.html 2 | `timescale 1ns / 1ps 3 | 4 | module fullAdder_tb; 5 | // Inputs 6 | reg In1; 7 | reg In2; 8 | reg Cin; 9 | 10 | // Outputs 11 | wire Sum; 12 | wire Cout; 13 | 14 | //Temporary looping variable 15 | reg [2:0] i = 3'd0; 16 | 17 | // Instantiate the Unit Under Test (UUT) 18 | fullAdder uut ( 19 | .In1(In1), 20 | .In2(In2), 21 | .Cin(Cin), 22 | .Sum(Sum), 23 | .Cout(Cout) 24 | ); 25 | initial begin 26 | // Initialize Inputs 27 | In1 = 1'b0; 28 | In2 = 1'b0; 29 | Cin = 1'b0; 30 | 31 | // Wait 100 ns for global reset to finish 32 | #100; 33 | 34 | // Add stimulus here 35 | for = 0; i < 8; i = i + 1'b1)begin 36 | {In1,In2,Cin} = {In1,In2,Cin} + 1'b1; 37 | #20; 38 | end 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /code/half_adder.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // File Downloaded from http://www.nandland.com 3 | /////////////////////////////////////////////////////////////////////////////// 4 | module half_adder 5 | ( 6 | i_bit1, 7 | i_bit2, 8 | o_sum, 9 | o_carry 10 | ); 11 | 12 | input i_bit1; 13 | input i_bit2; 14 | output o_sum; 15 | output o_carry; 16 | 17 | assign o_sum = i_bit1 ^ i_bit2; // bitwise xor 18 | assign o_carry = i_bit1 & i_bit2; // bitwise and 19 | 20 | endmodule // half_adder 21 | -------------------------------------------------------------------------------- /code/half_adder_tb.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // File Downloaded from http://www.nandland.com 3 | /////////////////////////////////////////////////////////////////////////////// 4 | `include "half_adder.v" 5 | 6 | module half_adder_tb; 7 | 8 | reg r_BIT1 = 0; 9 | reg r_BIT2 = 0; 10 | wire w_SUM; 11 | wire w_CARRY; 12 | 13 | half_adder half_adder_inst 14 | ( 15 | .i_bit1(r_BIT1), 16 | .i_bit2(r_BIT2), 17 | .o_sum(w_SUM), 18 | .o_carry(w_CARRY) 19 | ); 20 | 21 | initial 22 | begin 23 | r_BIT1 = 1'b0; 24 | r_BIT2 = 1'b0; 25 | #10; 26 | r_BIT1 = 1'b0; 27 | r_BIT2 = 1'b1; 28 | #10; 29 | r_BIT1 = 1'b1; 30 | r_BIT2 = 1'b0; 31 | #10; 32 | r_BIT1 = 1'b1; 33 | r_BIT2 = 1'b1; 34 | #10; 35 | end 36 | 37 | endmodule // half_adder_tb 38 | -------------------------------------------------------------------------------- /control/README.md: -------------------------------------------------------------------------------- 1 | # Control 2 | * [System](https://en.wikipedia.org/wiki/System) 3 | * [Control system](https://en.wikipedia.org/wiki/Control_system) 4 | * [Dynamical system](https://en.wikipedia.org/wiki/Dynamical_system) 5 | * [Control theory](https://en.wikipedia.org/wiki/Control_theory) 6 | * [Control engineering](https://en.wikipedia.org/wiki/Control_engineering) 7 | * [Guidance, navigation, and control](https://en.wikipedia.org/wiki/Guidance,_navigation,_and_control) (GNC) 8 | * [Bode plot](https://en.wikipedia.org/wiki/Bode_plot) 9 | * [Hendrik Wade Bode](https://en.wikipedia.org/wiki/Hendrik_Wade_Bode) 1905—1982 10 | * [Controllability](https://en.wikipedia.org/wiki/Controllability) 11 | * [Observability](https://en.wikipedia.org/wiki/Observability) 12 | * [Stability theory](https://en.wikipedia.org/wiki/Stability_theory) 13 | * [Aleksandr Lyapunov](https://en.wikipedia.org/wiki/Aleksandr_Lyapunov) 1857—1918 14 | --- 15 | * [Proportional myoelectric control](https://en.wikipedia.org/wiki/Proportional_myoelectric_control) 16 | -------------------------------------------------------------------------------- /free_range_vhdl_2013.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/free_range_vhdl_2013.pdf -------------------------------------------------------------------------------- /free_range_vhdl_2018.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/free_range_vhdl_2018.pdf -------------------------------------------------------------------------------- /free_range_vhdl_2019.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/free_range_vhdl_2019.pdf -------------------------------------------------------------------------------- /ghdl/adder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/ghdl/adder.png -------------------------------------------------------------------------------- /ghdl/adder.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Sep 16 09:48:06 2018 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $var reg 1 ! i0 $end 11 | $var reg 1 " i1 $end 12 | $var reg 1 # ci $end 13 | $var reg 1 $ s $end 14 | $var reg 1 % co $end 15 | $scope module adder_0 $end 16 | $var reg 1 & i0 $end 17 | $var reg 1 ' i1 $end 18 | $var reg 1 ( ci $end 19 | $var reg 1 ) s $end 20 | $var reg 1 * co $end 21 | $upscope $end 22 | $enddefinitions $end 23 | #0 24 | 0! 25 | 0" 26 | 0# 27 | 0$ 28 | 0% 29 | 0& 30 | 0' 31 | 0( 32 | 0) 33 | 0* 34 | #1000000 35 | 1# 36 | 1$ 37 | 1( 38 | 1) 39 | #2000000 40 | 1" 41 | 0# 42 | 1' 43 | 0( 44 | #3000000 45 | 1# 46 | 0$ 47 | 1% 48 | 1( 49 | 0) 50 | 1* 51 | #4000000 52 | 1! 53 | 0" 54 | 0# 55 | 1$ 56 | 0% 57 | 1& 58 | 0' 59 | 0( 60 | 1) 61 | 0* 62 | #5000000 63 | 1# 64 | 0$ 65 | 1% 66 | 1( 67 | 0) 68 | 1* 69 | #6000000 70 | 1" 71 | 0# 72 | 1' 73 | 0( 74 | #7000000 75 | 1# 76 | 1$ 77 | 1( 78 | 1) 79 | #8000000 80 | -------------------------------------------------------------------------------- /ghdl/adder.vhdl: -------------------------------------------------------------------------------- 1 | -- https://ghdl.readthedocs.io/en/stable/using/QuickStartGuide.html 2 | entity adder is 3 | -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder. 4 | -- `s` is the sum output, `co` is the carry-out. 5 | port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); 6 | end adder; 7 | 8 | architecture rtl of adder is 9 | begin 10 | -- This full-adder architecture contains two concurrent assignments. 11 | -- Compute the sum. 12 | s <= i0 xor i1 xor ci; 13 | -- Compute the carry. 14 | co <= (i0 and i1) or (i0 and ci) or (i1 and ci); 15 | end rtl; 16 | -------------------------------------------------------------------------------- /ghdl/adder_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- https://ghdl.readthedocs.io/en/stable/using/QuickStartGuide.html 2 | -- A testbench has no ports. 3 | entity adder_tb is 4 | end adder_tb; 5 | 6 | architecture behav of adder_tb is 7 | -- Declaration of the component that will be instantiated. 8 | component adder 9 | port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); 10 | end component; 11 | 12 | -- Specifies which entity is bound with the component. 13 | for adder_0: adder use entity work.adder; 14 | signal i0, i1, ci, s, co : bit; 15 | begin 16 | -- Component instantiation. 17 | adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, 18 | s => s, co => co); 19 | 20 | -- This process does the real job. 21 | process 22 | type pattern_type is record 23 | -- The inputs of the adder. 24 | i0, i1, ci : bit; 25 | -- The expected outputs of the adder. 26 | s, co : bit; 27 | end record; 28 | -- The patterns to apply. 29 | type pattern_array is array (natural range <>) of pattern_type; 30 | constant patterns : pattern_array := 31 | (('0', '0', '0', '0', '0'), 32 | ('0', '0', '1', '1', '0'), 33 | ('0', '1', '0', '1', '0'), 34 | ('0', '1', '1', '0', '1'), 35 | ('1', '0', '0', '1', '0'), 36 | ('1', '0', '1', '0', '1'), 37 | ('1', '1', '0', '0', '1'), 38 | ('1', '1', '1', '1', '1')); 39 | begin 40 | -- Check each pattern. 41 | for i in patterns'range loop 42 | -- Set the inputs. 43 | i0 <= patterns(i).i0; 44 | i1 <= patterns(i).i1; 45 | ci <= patterns(i).ci; 46 | -- Wait for the results. 47 | wait for 1 ns; 48 | -- Check the outputs. 49 | assert s = patterns(i).s 50 | report "bad sum value" severity error; 51 | assert co = patterns(i).co 52 | report "bad carry out value" severity error; 53 | end loop; 54 | assert false report "end of test" severity note; 55 | -- Wait forever; this will finish the simulation. 56 | wait; 57 | end process; 58 | end behav; 59 | -------------------------------------------------------------------------------- /ghdl/demux.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/ghdl/demux.png -------------------------------------------------------------------------------- /ghdl/demux.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Jun 23 17:10:09 2019 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $var reg 1 ! f $end 11 | $var reg 1 " s0 $end 12 | $var reg 1 # s1 $end 13 | $var reg 1 $ a $end 14 | $var reg 1 % b $end 15 | $var reg 1 & c $end 16 | $var reg 1 ' d $end 17 | $scope module uut $end 18 | $var reg 1 ( f $end 19 | $var reg 1 ) s0 $end 20 | $var reg 1 * s1 $end 21 | $var reg 1 + a $end 22 | $var reg 1 , b $end 23 | $var reg 1 - c $end 24 | $var reg 1 . d $end 25 | $upscope $end 26 | $enddefinitions $end 27 | #0 28 | 0! 29 | 0" 30 | 0# 31 | 0$ 32 | U% 33 | U& 34 | U' 35 | 0( 36 | 0) 37 | 0* 38 | 0+ 39 | U, 40 | U- 41 | U. 42 | #100000000 43 | 1! 44 | 1$ 45 | 1( 46 | 1+ 47 | #200000000 48 | 1" 49 | 1% 50 | 1) 51 | 1, 52 | #300000000 53 | 0" 54 | 1# 55 | 1& 56 | 0) 57 | 1* 58 | 1- 59 | #400000000 60 | 1" 61 | 1' 62 | 1) 63 | 1. 64 | #500000000 65 | -------------------------------------------------------------------------------- /ghdl/demux.vhdl: -------------------------------------------------------------------------------- 1 | -- https://allaboutfpga.com/vhdl-code-for-1-to-4-demux/ 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.all; 4 | 5 | entity demux is 6 | port( 7 | 8 | F : in STD_LOGIC; 9 | S0,S1: in STD_LOGIC; 10 | A,B,C,D: out STD_LOGIC 11 | ); 12 | end demux; 13 | 14 | architecture bhv of demux is 15 | begin 16 | process (F,S0,S1) is 17 | begin 18 | if (S0 ='0' and S1 = '0') then 19 | A <= F; 20 | elsif (S0 ='1' and S1 = '0') then 21 | B <= F; 22 | elsif (S0 ='0' and S1 = '1') then 23 | C <= F; 24 | else 25 | D <= F; 26 | end if; 27 | 28 | end process; 29 | end bhv; 30 | -------------------------------------------------------------------------------- /ghdl/demux_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- https://allaboutfpga.com/vhdl-code-for-1-to-4-demux/ 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.ALL; 4 | 5 | ENTITY demux_tb IS 6 | END demux_tb; 7 | 8 | ARCHITECTURE behavior OF demux_tb IS 9 | 10 | -- Component Declaration for the Unit Under Test (UUT) 11 | 12 | COMPONENT demux 13 | PORT( 14 | F : IN std_logic; 15 | S0 : IN std_logic; 16 | S1 : IN std_logic; 17 | A : OUT std_logic; 18 | B : OUT std_logic; 19 | C : OUT std_logic; 20 | D : OUT std_logic 21 | ); 22 | END COMPONENT; 23 | 24 | --Inputs 25 | signal F : std_logic := '0'; 26 | signal S0 : std_logic := '0'; 27 | signal S1 : std_logic := '0'; 28 | 29 | --Outputs 30 | signal A : std_logic; 31 | signal B : std_logic; 32 | signal C : std_logic; 33 | signal D : std_logic; 34 | -- No clocks detected in port list. Replace below with 35 | -- appropriate port name 36 | 37 | BEGIN 38 | 39 | -- Instantiate the Unit Under Test (UUT) 40 | uut: demux PORT MAP ( 41 | F => F, 42 | S0 => S0, 43 | S1 => S1, 44 | A => A, 45 | B => B, 46 | C => C, 47 | D => D 48 | ); 49 | 50 | -- Stimulus process 51 | stim_proc: process 52 | begin 53 | -- hold reset state for 100 ns. 54 | wait for 100 ns; 55 | 56 | F <= '1'; 57 | 58 | S0 <= '0'; S1 <= '0'; 59 | wait for 100 ns; 60 | 61 | S0 <= '1'; S1 <= '0'; 62 | wait for 100 ns; 63 | 64 | S0 <= '0'; S1 <= '1'; 65 | wait for 100 ns; 66 | 67 | S0 <= '1'; S1 <= '1'; 68 | wait for 100 ns; 69 | -- insert stimulus here 70 | 71 | wait; 72 | end process; 73 | 74 | END; 75 | -------------------------------------------------------------------------------- /ghdl/dff.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/ghdl/dff.png -------------------------------------------------------------------------------- /ghdl/dff.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Jun 23 11:28:57 2019 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $var reg 1 ! din $end 11 | $var reg 1 " clk $end 12 | $var reg 1 # rst $end 13 | $var reg 1 $ dout $end 14 | $scope module uut $end 15 | $var reg 1 % din $end 16 | $var reg 1 & clk $end 17 | $var reg 1 ' rst $end 18 | $var reg 1 ( dout $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | 0! 23 | 0" 24 | 1# 25 | 0$ 26 | 0% 27 | 0& 28 | 1' 29 | 0( 30 | #5000000 31 | 1" 32 | 1& 33 | #10000000 34 | 0" 35 | 0& 36 | #15000000 37 | 1" 38 | 1& 39 | #20000000 40 | 0" 41 | 0& 42 | #25000000 43 | 1" 44 | 1& 45 | #30000000 46 | 0" 47 | 0& 48 | #35000000 49 | 1" 50 | 1& 51 | #40000000 52 | 0" 53 | 0& 54 | #45000000 55 | 1" 56 | 1& 57 | #50000000 58 | 0" 59 | 0# 60 | 0& 61 | 0' 62 | #55000000 63 | 1" 64 | 1& 65 | #60000000 66 | 0" 67 | 0& 68 | #65000000 69 | 1" 70 | 1& 71 | #70000000 72 | 0" 73 | 0& 74 | #75000000 75 | 1" 76 | 1& 77 | #80000000 78 | 0" 79 | 0& 80 | #85000000 81 | 1" 82 | 1& 83 | #90000000 84 | 0" 85 | 0& 86 | #95000000 87 | 1" 88 | 1& 89 | #100000000 90 | 1! 91 | 0" 92 | 1% 93 | 0& 94 | #105000000 95 | 1" 96 | 1$ 97 | 1& 98 | 1( 99 | #110000000 100 | 0" 101 | 0& 102 | #115000000 103 | 1" 104 | 1& 105 | #120000000 106 | 0" 107 | 0& 108 | #125000000 109 | 1" 110 | 1& 111 | #130000000 112 | 0" 113 | 0& 114 | #135000000 115 | 1" 116 | 1& 117 | #140000000 118 | 0" 119 | 0& 120 | #145000000 121 | 1" 122 | 1& 123 | #150000000 124 | 0" 125 | 1# 126 | 0$ 127 | 0& 128 | 1' 129 | 0( 130 | #155000000 131 | 1" 132 | 1& 133 | #160000000 134 | 0" 135 | 0& 136 | #165000000 137 | 1" 138 | 1& 139 | #170000000 140 | 0" 141 | 0& 142 | #175000000 143 | 1" 144 | 1& 145 | #180000000 146 | 0" 147 | 0& 148 | #185000000 149 | 1" 150 | 1& 151 | #190000000 152 | 0" 153 | 0& 154 | #195000000 155 | 1" 156 | 1& 157 | #200000000 158 | 0" 159 | 0& 160 | #205000000 161 | 1" 162 | 1& 163 | #210000000 164 | -------------------------------------------------------------------------------- /ghdl/dff.vhdl: -------------------------------------------------------------------------------- 1 | -- https://electronicstopper.blogspot.com/2017/07/d-flip-flop-in-vhdl-with-testbench.html 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | 5 | entity DFF is 6 | port( din: in std_logic; 7 | clk: in std_logic; 8 | rst: in std_logic; 9 | dout: out std_logic); 10 | end DFF; 11 | 12 | architecture behavioral of DFF is 13 | begin 14 | process(rst,clk,din) 15 | begin 16 | if (rst='1') then 17 | dout<='0'; 18 | elsif(rising_edge(clk)) then 19 | dout<= din; 20 | end if; 21 | end process; 22 | 23 | end behavioral; 24 | -------------------------------------------------------------------------------- /ghdl/dff_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- https://electronicstopper.blogspot.com/2017/07/d-flip-flop-in-vhdl-with-testbench.html 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.ALL; 4 | 5 | ENTITY DFF_tb IS 6 | END DFF_tb; 7 | 8 | ARCHITECTURE behavior OF DFF_tb IS 9 | 10 | COMPONENT DFF 11 | PORT( 12 | din : IN std_logic; 13 | clk : IN std_logic; 14 | rst : IN std_logic; 15 | dout : OUT std_logic 16 | ); 17 | END COMPONENT; 18 | 19 | signal din : std_logic := '0'; 20 | signal clk : std_logic := '0'; 21 | signal rst : std_logic := '1'; 22 | signal dout : std_logic; 23 | 24 | constant clk_period : time := 10 ns; 25 | 26 | BEGIN 27 | 28 | uut: DFF PORT MAP ( 29 | din => din, 30 | clk => clk, 31 | rst => rst, 32 | dout => dout 33 | ); 34 | 35 | clk_process :process 36 | begin 37 | clk <= '0'; 38 | wait for clk_period/2; 39 | clk <= '1'; 40 | wait for clk_period/2; 41 | if NOW > 200 ns then 42 | wait; 43 | end if; 44 | end process; 45 | 46 | stim_proc: process 47 | begin 48 | 49 | rst <= '1'; 50 | wait for 50 ns; 51 | 52 | rst <= '0'; 53 | din <= '0'; 54 | wait for 50 ns; 55 | 56 | rst <= '0'; 57 | din <= '1'; 58 | wait for 50 ns; 59 | 60 | rst <= '1'; 61 | wait; 62 | 63 | end process; 64 | 65 | END; 66 | -------------------------------------------------------------------------------- /ghdl/ha.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/ghdl/ha.png -------------------------------------------------------------------------------- /ghdl/ha.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Sep 16 09:42:54 2018 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $var reg 1 ! a $end 11 | $var reg 1 " b $end 12 | $var reg 1 # s $end 13 | $var reg 1 $ c $end 14 | $scope module half_addr $end 15 | $var reg 1 % a $end 16 | $var reg 1 & b $end 17 | $var reg 1 ' s $end 18 | $var reg 1 ( c $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | X! 23 | X" 24 | X# 25 | X$ 26 | X% 27 | X& 28 | X' 29 | X( 30 | #1000000 31 | 0! 32 | 0" 33 | 0# 34 | 0$ 35 | 0% 36 | 0& 37 | 0' 38 | 0( 39 | #2000000 40 | 1" 41 | 1# 42 | 1& 43 | 1' 44 | #3000000 45 | 1! 46 | 0" 47 | 1% 48 | 0& 49 | #4000000 50 | 1" 51 | 0# 52 | 1$ 53 | 1& 54 | 0' 55 | 1( 56 | #5000000 57 | -------------------------------------------------------------------------------- /ghdl/ha.vhdl: -------------------------------------------------------------------------------- 1 | -- Binary half adder (HA) 2 | -- Author: Nerdy Dave 3 | -- Source: https://youtu.be/H2GyAIYwZbw 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | 7 | entity ha is 8 | port 9 | ( 10 | a: in std_ulogic; -- Input of the unresolved type 11 | b: in std_ulogic; -- https://vhdlwhiz.com/std_logic-vs-std_ulogic/ 12 | s: out std_ulogic; -- Output sum of a and b 13 | c: out std_ulogic -- Output carry 14 | ); 15 | end ha; 16 | 17 | architecture behave of ha is 18 | begin 19 | s <= a xor b; 20 | c <= a and b; 21 | end behave; 22 | -------------------------------------------------------------------------------- /ghdl/ha_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- Half Adder (HA) Test Bench (TB) 2 | -- Author: Nerdy Dave 3 | -- Source: https://youtu.be/H2GyAIYwZbw 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | 7 | entity ha_tb is 8 | end ha_tb; 9 | 10 | architecture test of ha_tb is 11 | component ha 12 | port 13 | ( 14 | a: in std_ulogic; 15 | b: in std_ulogic; 16 | s: out std_ulogic; -- Sum 17 | c: out std_ulogic -- Carry 18 | ); 19 | end component; 20 | 21 | signal a, b, s, c : std_ulogic; 22 | begin 23 | half_addr: ha port map (a => a, b => b, s => s, c => c); 24 | 25 | process begin 26 | 27 | a <= 'X'; 28 | b <= 'X'; 29 | wait for 1 ns; 30 | 31 | a <= '0'; 32 | b <= '0'; 33 | wait for 1 ns; 34 | 35 | a <= '0'; 36 | b <= '1'; 37 | wait for 1 ns; 38 | 39 | a <= '1'; 40 | b <= '0'; 41 | wait for 1 ns; 42 | 43 | a <= '1'; 44 | b <= '1'; 45 | wait for 1 ns; 46 | 47 | assert false report "Reached end of test"; 48 | wait; 49 | 50 | end process; 51 | 52 | end test; 53 | -------------------------------------------------------------------------------- /ghdl/hello.vhdl: -------------------------------------------------------------------------------- 1 | -- https://ghdl.readthedocs.io/en/stable/using/QuickStartGuide.html 2 | -- Hello world program 3 | use std.textio.all; -- Imports the standard textio package. 4 | 5 | -- Defines a design entity, without any ports. 6 | entity hello_world is 7 | end hello_world; 8 | 9 | architecture behaviour of hello_world is 10 | begin 11 | process 12 | variable l : line; 13 | begin 14 | write (l, String'("Hello world!")); 15 | writeline (output, l); 16 | wait; 17 | end process; 18 | end behaviour; 19 | -------------------------------------------------------------------------------- /ghdl/mux.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/ghdl/mux.png -------------------------------------------------------------------------------- /ghdl/mux.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Jun 23 16:31:19 2019 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $var reg 1 ! a $end 11 | $var reg 1 " b $end 12 | $var reg 1 # c $end 13 | $var reg 1 $ d $end 14 | $var reg 1 % s0 $end 15 | $var reg 1 & s1 $end 16 | $var reg 1 ' z $end 17 | $scope module uut $end 18 | $var reg 1 ( a $end 19 | $var reg 1 ) b $end 20 | $var reg 1 * c $end 21 | $var reg 1 + d $end 22 | $var reg 1 , s0 $end 23 | $var reg 1 - s1 $end 24 | $var reg 1 . z $end 25 | $upscope $end 26 | $enddefinitions $end 27 | #0 28 | 0! 29 | 0" 30 | 0# 31 | 0$ 32 | 0% 33 | 0& 34 | 0' 35 | 0( 36 | 0) 37 | 0* 38 | 0+ 39 | 0, 40 | 0- 41 | 0. 42 | #100000000 43 | 1! 44 | 1# 45 | 1' 46 | 1( 47 | 1* 48 | 1. 49 | #200000000 50 | 1% 51 | 0' 52 | 1, 53 | 0. 54 | #300000000 55 | 0% 56 | 1& 57 | 1' 58 | 0, 59 | 1- 60 | 1. 61 | #400000000 62 | 1% 63 | 0' 64 | 1, 65 | 0. 66 | #500000000 67 | -------------------------------------------------------------------------------- /ghdl/mux.vhdl: -------------------------------------------------------------------------------- 1 | -- https://allaboutfpga.com/vhdl-4-to-1-mux-multiplexer/ 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.all; 4 | 5 | entity mux is 6 | port( 7 | 8 | A,B,C,D : in STD_LOGIC; 9 | S0,S1: in STD_LOGIC; 10 | Z: out STD_LOGIC 11 | ); 12 | end mux; 13 | 14 | architecture bhv of mux is 15 | begin 16 | process (A,B,C,D,S0,S1) is 17 | begin 18 | if (S0 ='0' and S1 = '0') then 19 | Z <= A; 20 | elsif (S0 ='1' and S1 = '0') then 21 | Z <= B; 22 | elsif (S0 ='0' and S1 = '1') then 23 | Z <= C; 24 | else 25 | Z <= D; 26 | end if; 27 | 28 | end process; 29 | end bhv; 30 | -------------------------------------------------------------------------------- /ghdl/mux_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- https://allaboutfpga.com/vhdl-4-to-1-mux-multiplexer/ 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.ALL; 4 | 5 | ENTITY mux_tb IS 6 | END mux_tb; 7 | 8 | ARCHITECTURE behavior OF mux_tb IS 9 | 10 | -- Component Declaration for the Unit Under Test (UUT) 11 | 12 | COMPONENT mux 13 | PORT( 14 | A : IN std_logic; 15 | B : IN std_logic; 16 | C : IN std_logic; 17 | D : IN std_logic; 18 | S0 : IN std_logic; 19 | S1 : IN std_logic; 20 | Z : OUT std_logic 21 | ); 22 | END COMPONENT; 23 | 24 | --Inputs 25 | signal A : std_logic := '0'; 26 | signal B : std_logic := '0'; 27 | signal C : std_logic := '0'; 28 | signal D : std_logic := '0'; 29 | signal S0 : std_logic := '0'; 30 | signal S1 : std_logic := '0'; 31 | 32 | --Outputs 33 | signal Z : std_logic; 34 | 35 | BEGIN 36 | 37 | -- Instantiate the Unit Under Test (UUT) 38 | uut: mux PORT MAP ( 39 | A => A, 40 | B => B, 41 | C => C, 42 | D => D, 43 | S0 => S0, 44 | S1 => S1, 45 | Z => Z 46 | ); 47 | 48 | -- Stimulus process 49 | stim_proc: process 50 | begin 51 | -- hold reset state for 100 ns. 52 | wait for 100 ns; 53 | 54 | A <= '1'; 55 | B <= '0'; 56 | C <= '1'; 57 | D <= '0'; 58 | 59 | S0 <= '0'; S1 <= '0'; 60 | wait for 100 ns; 61 | 62 | S0 <= '1'; S1 <= '0'; 63 | wait for 100 ns; 64 | 65 | S0 <= '0'; S1 <= '1'; 66 | wait for 100 ns; 67 | 68 | S0 <= '1'; S1 <= '1'; 69 | wait for 100 ns; 70 | 71 | wait; 72 | 73 | end process; 74 | 75 | END; 76 | -------------------------------------------------------------------------------- /ghdl/my_sys.vhd: -------------------------------------------------------------------------------- 1 | ---------------------- FILE: my_sys.vhd ---------------------- 2 | -- library declaration 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | -- the ENTITY 7 | entity circuit1 is 8 | port (A,B,C : in std_logic; 9 | F,G : out std_logic); 10 | end circuit1; 11 | 12 | -- the ARCHITECTURE 13 | architecture circuit1_arc of circuit1 is 14 | signal sig_1 : std_logic; -- signal definition 15 | begin 16 | process (a,b,c) 17 | variable var_1 : integer; -- variable definition 18 | begin 19 | F <= not (A and B and C); -- signal assignment 20 | sig_1 <= A; -- another signal assignment 21 | var_1 := 34; -- variable assignment 22 | end process; 23 | 24 | G <= not (A and B); -- concurrent assignment 25 | end circuit1_arc; 26 | -------------------------------------------------------------------------------- /ghdl/sr_ff.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Tue Oct 12 06:14:59 2021 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $scope module standard $end 11 | $upscope $end 12 | $scope module std_logic_1164 $end 13 | $upscope $end 14 | $scope module std_logic_arith $end 15 | $upscope $end 16 | $scope module std_logic_unsigned $end 17 | $upscope $end 18 | $scope module sr_ff_tb $end 19 | $var reg 1 ! s $end 20 | $var reg 1 " r $end 21 | $var reg 1 # rst $end 22 | $var reg 1 $ clk $end 23 | $var reg 1 % q $end 24 | $var reg 1 & qb $end 25 | $scope module uut $end 26 | $var reg 1 ' s $end 27 | $var reg 1 ( r $end 28 | $var reg 1 ) rst $end 29 | $var reg 1 * clk $end 30 | $var reg 1 + q $end 31 | $var reg 1 , qb $end 32 | $upscope $end 33 | $upscope $end 34 | $enddefinitions $end 35 | #0 36 | 0! 37 | 0" 38 | 0# 39 | 0$ 40 | U% 41 | U& 42 | 0' 43 | 0( 44 | 0) 45 | 0* 46 | U+ 47 | U, 48 | #10000000 49 | 1$ 50 | 1* 51 | #20000000 52 | 1" 53 | 0$ 54 | 1( 55 | 0* 56 | #30000000 57 | 1$ 58 | 0% 59 | 1& 60 | 1* 61 | 0+ 62 | 1, 63 | #40000000 64 | 1! 65 | 0" 66 | 0$ 67 | 1' 68 | 0( 69 | 0* 70 | #50000000 71 | 1$ 72 | 1% 73 | 0& 74 | 1* 75 | 1+ 76 | 0, 77 | #60000000 78 | 1" 79 | 0$ 80 | 1( 81 | 0* 82 | #70000000 83 | 1$ 84 | Z% 85 | Z& 86 | 1* 87 | Z+ 88 | Z, 89 | #80000000 90 | 0! 91 | 0" 92 | 0$ 93 | 0' 94 | 0( 95 | 0* 96 | #90000000 97 | 1$ 98 | 1* 99 | #100000000 100 | 1" 101 | 0$ 102 | 1( 103 | 0* 104 | -------------------------------------------------------------------------------- /ghdl/sr_ff.vhdl: -------------------------------------------------------------------------------- 1 | -- https://technobyte.org/vhdl-code-flip-flops-behavioral/ 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.STD_LOGIC_ARITH.ALL; 5 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | entity SR_FLIPFLOP_SOURCE is 7 | Port ( S,R,RST,CLK : in STD_LOGIC; 8 | Q,Qb : out STD_LOGIC); 9 | end SR_FLIPFLOP_SOURCE; 10 | 11 | architecture Behavioral of SR_FLIPFLOP_SOURCE is 12 | 13 | begin 14 | 15 | process (S,R,RST,CLK) 16 | 17 | begin 18 | 19 | if (RST = '1') then 20 | Q <= '0'; 21 | elsif (RISING_EDGE(CLK))then 22 | if (S /= R) then 23 | Q <= S; 24 | Qb <= R; 25 | elsif (S = '1' AND R = '1') then 26 | Q <= 'Z'; 27 | Qb <= 'Z'; 28 | 29 | end if; 30 | end if; 31 | end process; 32 | end Behavioral; 33 | -------------------------------------------------------------------------------- /ghdl/sr_ff_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- https://technobyte.org/vhdl-code-flip-flops-behavioral/ 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.STD_LOGIC_ARITH.ALL; 5 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | 7 | entity SR_FF_tb is 8 | end entity; 9 | 10 | architecture tb of SR_FF_tb is 11 | 12 | component SR_FLIPFLOP_SOURCE is 13 | Port ( S,R,RST,CLK : in STD_LOGIC; 14 | Q,Qb : out STD_LOGIC); 15 | end component; 16 | 17 | signal S, R, RST, CLK, Q, Qb : STD_LOGIC; 18 | 19 | begin 20 | uut: SR_FLIPFLOP_SOURCE port map( 21 | S => S, 22 | R => R, 23 | RST => RST, 24 | CLK => CLK, 25 | Q => Q, 26 | Qb => Qb); 27 | 28 | Clock : process 29 | begin 30 | 31 | CLK <= '0'; 32 | wait for 10 ns; 33 | CLK <= '1'; 34 | wait for 10 ns; 35 | 36 | end process; 37 | 38 | Stim : process 39 | begin 40 | 41 | RST <= '0'; 42 | 43 | S <= '0'; 44 | R <= '0'; 45 | wait for 20 ns; 46 | 47 | S <= '0'; 48 | R <= '1'; 49 | wait for 20 ns; 50 | 51 | S <= '1'; 52 | R <= '0'; 53 | wait for 20 ns; 54 | 55 | S <= '1'; 56 | R <= '1'; 57 | wait for 20 ns; 58 | 59 | end process; 60 | end tb; 61 | -------------------------------------------------------------------------------- /ghdl/tff.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/ghdl/tff.png -------------------------------------------------------------------------------- /ghdl/tff.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Jun 23 12:24:08 2019 3 | $end 4 | $version 5 | GHDL v0 6 | $end 7 | $timescale 8 | 1 fs 9 | $end 10 | $var reg 1 ! din $end 11 | $var reg 1 " clk $end 12 | $var reg 1 # rst $end 13 | $var reg 1 $ dout $end 14 | $scope module uut $end 15 | $var reg 1 % din $end 16 | $var reg 1 & clk $end 17 | $var reg 1 ' rst $end 18 | $var reg 1 ( dout $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | 0! 23 | 0" 24 | 1# 25 | 0$ 26 | 0% 27 | 0& 28 | 1' 29 | 0( 30 | #5000000 31 | 1" 32 | 1& 33 | #10000000 34 | 0" 35 | 0& 36 | #15000000 37 | 1" 38 | 1& 39 | #20000000 40 | 0" 41 | 0& 42 | #25000000 43 | 1" 44 | 1& 45 | #30000000 46 | 0" 47 | 0& 48 | #35000000 49 | 1" 50 | 1& 51 | #40000000 52 | 0" 53 | 0& 54 | #45000000 55 | 1" 56 | 1& 57 | #50000000 58 | 0" 59 | 0# 60 | 0& 61 | 0' 62 | #55000000 63 | 1" 64 | 1$ 65 | 1& 66 | 1( 67 | #60000000 68 | 0" 69 | 0& 70 | #65000000 71 | 1" 72 | 1& 73 | #70000000 74 | 0" 75 | 0& 76 | #75000000 77 | 1" 78 | 1& 79 | #80000000 80 | 0" 81 | 0& 82 | #85000000 83 | 1" 84 | 1& 85 | #90000000 86 | 0" 87 | 0& 88 | #95000000 89 | 1" 90 | 1& 91 | #100000000 92 | 1! 93 | 0" 94 | 1% 95 | 0& 96 | #105000000 97 | 1" 98 | 0$ 99 | 1& 100 | 0( 101 | #110000000 102 | 0" 103 | 0& 104 | #115000000 105 | 1" 106 | 1& 107 | #120000000 108 | 0" 109 | 0& 110 | #125000000 111 | 1" 112 | 1& 113 | #130000000 114 | 0" 115 | 0& 116 | #135000000 117 | 1" 118 | 1& 119 | #140000000 120 | 0" 121 | 0& 122 | #145000000 123 | 1" 124 | 1& 125 | #150000000 126 | 0" 127 | 1# 128 | 0& 129 | 1' 130 | #155000000 131 | 1" 132 | 1& 133 | #160000000 134 | 0" 135 | 0& 136 | #165000000 137 | 1" 138 | 1& 139 | #170000000 140 | 0" 141 | 0& 142 | #175000000 143 | 1" 144 | 1& 145 | #180000000 146 | 0" 147 | 0& 148 | #185000000 149 | 1" 150 | 1& 151 | #190000000 152 | 0" 153 | 0& 154 | #195000000 155 | 1" 156 | 1& 157 | #200000000 158 | 0" 159 | 0& 160 | #205000000 161 | 1" 162 | 1& 163 | #210000000 164 | -------------------------------------------------------------------------------- /ghdl/tff.vhdl: -------------------------------------------------------------------------------- 1 | -- https://electronicstopper.blogspot.com/2017/07/t-flip-flop-in-vhdl-with-testbench.html 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | 5 | entity TFF is 6 | port( din: in std_logic; 7 | clk: in std_logic; 8 | rst: in std_logic; 9 | dout: out std_logic); 10 | end TFF; 11 | 12 | architecture behavioral of TFF is 13 | begin 14 | process(rst,clk,din) 15 | begin 16 | if (rst='1') then 17 | dout<='0'; 18 | elsif(rising_edge(clk)) then 19 | dout<=not din; 20 | end if; 21 | end process; 22 | 23 | end behavioral; 24 | -------------------------------------------------------------------------------- /ghdl/tff_tb.vhdl: -------------------------------------------------------------------------------- 1 | -- https://electronicstopper.blogspot.com/2017/07/t-flip-flop-in-vhdl-with-testbench.html 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.ALL; 4 | 5 | ENTITY TFF_tb IS 6 | END TFF_tb; 7 | 8 | ARCHITECTURE behavior OF TFF_tb IS 9 | 10 | COMPONENT TFF 11 | PORT( 12 | din : IN std_logic; 13 | clk : IN std_logic; 14 | rst : IN std_logic; 15 | dout : OUT std_logic 16 | ); 17 | END COMPONENT; 18 | 19 | signal din : std_logic := '0'; 20 | signal clk : std_logic := '0'; 21 | signal rst : std_logic := '0'; 22 | signal dout : std_logic; 23 | 24 | constant clk_period : time := 10 ns; 25 | 26 | BEGIN 27 | 28 | uut: TFF PORT MAP ( 29 | din => din, 30 | clk => clk, 31 | rst => rst, 32 | dout => dout 33 | ); 34 | 35 | clk_process :process 36 | begin 37 | clk <= '0'; 38 | wait for clk_period/2; 39 | clk <= '1'; 40 | wait for clk_period/2; 41 | if NOW > 200 ns then 42 | wait; 43 | end if; 44 | end process; 45 | 46 | stim_proc: process 47 | begin 48 | 49 | rst <= '1'; 50 | wait for 50 ns; 51 | 52 | rst <= '0'; 53 | din <= '0'; 54 | wait for 50 ns; 55 | 56 | rst <= '0'; 57 | din <= '1'; 58 | wait for 50 ns; 59 | 60 | rst <= '1'; 61 | wait; 62 | 63 | end process; 64 | 65 | END; 66 | -------------------------------------------------------------------------------- /power/README.md: -------------------------------------------------------------------------------- 1 | # Power 2 | * [Steinmetz's equation](https://en.wikipedia.org/wiki/Steinmetz%27s_equation) 3 | * [Charles Proteus Steinmetz](https://en.wikipedia.org/wiki/Charles_Proteus_Steinmetz) 1865—1923 4 | * [Charles P. Steinmetz Memorial Lecture](https://en.wikipedia.org/wiki/Charles_P._Steinmetz_Memorial_Lecture) 5 | * [IEEE Charles Proteus Steinmetz Award](https://en.wikipedia.org/wiki/IEEE_Charles_Proteus_Steinmetz_Award) 6 | * [List of battery sizes](https://en.wikipedia.org/wiki/List_of_battery_sizes) 7 | * [Inductive charging](https://en.wikipedia.org/wiki/Inductive_charging) 8 | ## Power Management 9 | * [Power management integrated circuit](https://en.wikipedia.org/wiki/Power_management_integrated_circuit) (PMIC) 10 | * [Power Management Unit](https://en.wikipedia.org/wiki/Power_Management_Unit) (PMU) 11 | * [Power system simulation](https://en.wikipedia.org/wiki/Power_system_simulation) 12 | * [Power-flow study](https://en.wikipedia.org/wiki/Power-flow_study) 13 | * [Linear decision rule](https://link.springer.com/referenceworkentry/10.1007/1-4020-0612-8_515) (LDR) 14 | * [Low-dropout regulator](https://en.wikipedia.org/wiki/Low-dropout_regulator) (LDO) 15 | * [Sleep mode](https://en.wikipedia.org/wiki/Sleep_mode) 16 | * [BatteryML](https://github.com/microsoft/BatteryML) 17 | ## Thermal Management 18 | * [Thermal management](https://en.wikipedia.org/wiki/Thermal_management_(electronics)) 19 | * [Thermodynamics](https://en.wikipedia.org/wiki/Thermodynamics) 20 | * [Laws of thermodynamics](https://en.wikipedia.org/wiki/Laws_of_thermodynamics) 21 | * [Table of thermodynamic equations](https://en.wikipedia.org/wiki/Table_of_thermodynamic_equations) 22 | * [Entropy](https://en.wikipedia.org/wiki/Entropy) 23 | * [Rudolf Clausius](https://en.wikipedia.org/wiki/Rudolf_Clausius) 1822—1888 24 | * [Enthalpy](https://en.wikipedia.org/wiki/Enthalpy) 25 | * [Specific heat capacity](https://en.wikipedia.org/wiki/Specific_heat_capacity) 26 | * [Table of specific heat capacities](https://en.wikipedia.org/wiki/Table_of_specific_heat_capacities) 27 | * [Liquid metal](https://en.wikipedia.org/wiki/Liquid_metal) 28 | * [Immersion cooling](https://en.wikipedia.org/wiki/Immersion_cooling) 29 | * [Dielectric](https://en.wikipedia.org/wiki/Dielectric) 30 | * [Liquid dielectric](https://en.wikipedia.org/wiki/Liquid_dielectric) 31 | * [Submer Technologies](https://wikitia.com/wiki/Submer_Technologies) 32 | * [Iceotope](https://www.iceotope.com/) 33 | ## Standards 34 | * [IEEE 1547](https://en.wikipedia.org/wiki/IEEE_1547) Standard for Interconnection and Interoperability of Distributed Energy Resources with Associated Electric Power Systems Interfaces 35 | * [Nuclear Power and Flexible Grid Solutions](https://ieee-pes.org/trending-tech/nuclear-power-and-flexible-grid-solutions/) 36 | -------------------------------------------------------------------------------- /smartsim/README.md: -------------------------------------------------------------------------------- 1 | # SmartSim 2 | * [SmartSim](https://smartsim.org.uk/) is a digital logic circuit design and simulation package for Windows and Linux 3 | including [Raspberry Pi OS](https://en.wikipedia.org/wiki/Raspberry_Pi_OS) 4 | * Maintainer: [Ashley Newson](https://github.com/ashleynewson) 5 | * [SmartSim example projects](https://smartsim.org.uk/index.php?page=examples) 6 | * 4-bit addition 7 | * [Flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)) collection 8 | * 8-bit divider 9 | * 8-bit division using [finite-state machine](https://en.wikipedia.org/wiki/Finite-state_machine) (FSM) 10 | * 16-bit [one-instruction set computer](https://en.wikipedia.org/wiki/One-instruction_set_computer) (OISC) 11 | -------------------------------------------------------------------------------- /smartsim/addition/4 bit addition.ssp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 4 Bit Addition 7 | 8 | half adder.ssc 9 | full adder.ssc 10 | 4 bit addition.ssc 11 | 12 | -------------------------------------------------------------------------------- /smartsim/addition/full adder.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Full Adder 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | -------------------------------------------------------------------------------- /smartsim/addition/half adder.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Half Adder 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | -------------------------------------------------------------------------------- /smartsim/division/2 to 1.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Multiplexer 2-1 7 | 2 to 1 multiplexer 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | -------------------------------------------------------------------------------- /smartsim/division/division.ssp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 8 Bit Division 7 | 8 | up count bit.ssc 9 | full adder.ssc 10 | 8 bit d flipflop array.ssc 11 | 2 to 1.ssc 12 | 3 bit up counter.ssc 13 | 8 bit addition using full adder.ssc 14 | 8 bit 2 to 1.ssc 15 | divider.ssc 16 | division.ssc 17 | 18 | -------------------------------------------------------------------------------- /smartsim/division/up count bit.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Toggle Carry 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | -------------------------------------------------------------------------------- /smartsim/division_b/8-bit divider circuit.ssp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 8 Bit Divider with FSM 7 | 8 | Delay (DLY).ssc 9 | D flip-flop with clear and preset (DFFCP).ssc 10 | Full-adder (FA).ssc 11 | 8-bit shift register (SHIFT8).ssc 12 | 8-bit select or clear (SELCLR8).ssc 13 | 8-bit register (REG8).ssc 14 | 8-bit synchronous up-counter with enable (CNTR8).ssc 15 | T flip-flop with preset (TFFP).ssc 16 | 8-bit adder (ADD8).ssc 17 | 3-bit down-counter with load (DCNT3L).ssc 18 | Divider FSM control logic (DIVFSM).ssc 19 | 8-bit divider (DIV8).ssc 20 | 8-bit divider test circuit.ssc 21 | 22 | -------------------------------------------------------------------------------- /smartsim/division_b/Delay (DLY).ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Delay (DLY) 7 | Delay (DLY) 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /smartsim/flipflops/flipflops.ssp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Flipflops 7 | 8 | gated d latch.ssc 9 | sr nor latch.ssc 10 | jk flipflop.ssc 11 | pe d flipflop.ssc 12 | flipflops.ssc 13 | 14 | -------------------------------------------------------------------------------- /smartsim/flipflops/sr nor latch.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | SR Latch 7 | Sets value to 1 when S is high, or 0 when R is high. 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | -------------------------------------------------------------------------------- /smartsim/sbn oisc/bidirectional controller.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Bidirectional Controller 7 | Controls input and output on a bidirectional wire. 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | -------------------------------------------------------------------------------- /smartsim/sbn oisc/delay 2.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Delay 2 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /smartsim/sbn oisc/half adder.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Half Adder 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | -------------------------------------------------------------------------------- /smartsim/sbn oisc/programs/count11.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/smartsim/sbn oisc/programs/count11.bin -------------------------------------------------------------------------------- /smartsim/sbn oisc/programs/fibonacci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kevinwlu/dsd/ef9755fc16d6e349e5f9c9f72fd9f04822fb90ff/smartsim/sbn oisc/programs/fibonacci.bin -------------------------------------------------------------------------------- /smartsim/sbn oisc/readme.txt: -------------------------------------------------------------------------------- 1 | To load and run one of the programs into the memory chip: 2 | 3 | Open the project normally. 4 | In the computer component (shown by default), select the adjust tool and click on the "MEM" component. 5 | Click on the "Browse" button in the "Read File" section. 6 | Find and select one of the "*.bin" files inside the "programs" folder. 7 | Close the properties window. 8 | 9 | Run the circuit. 10 | Set the clock toggle (lower left) to 1. 11 | Set the "Rst" toggle to 1, and set it back to 0 when the "Rdy" signal is 1. 12 | Set the "Exe" toggle to 1 to start the program's execution. 13 | 14 | Look inside the running processor to watch it work. 15 | -------------------------------------------------------------------------------- /smartsim/sbn oisc/sbn oisc.ssp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | Single Opcode Processor 7 | 8 | full adder.ssc 9 | 16 bit d flipflop array.ssc 10 | memory controller fsm.ssc 11 | bidirectional controller.ssc 12 | state selector bit.ssc 13 | 16 bit tristate.ssc 14 | half adder.ssc 15 | 16 bit 2 to 1.ssc 16 | delay 2.ssc 17 | 16 bit addition using full adder.ssc 18 | 16 bit bidirectional controller.ssc 19 | up set counter 16.ssc 20 | 16 state selector.ssc 21 | processor fsm.ssc 22 | memory controller.ssc 23 | processor.ssc 24 | computer.ssc 25 | 26 | -------------------------------------------------------------------------------- /smartsim/sbn oisc/state selector bit.ssc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | State Selector Bit 7 | A bit with activate and persist 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | -------------------------------------------------------------------------------- /standards/README.md: -------------------------------------------------------------------------------- 1 | # Standards 2 | * [Accellera](https://en.wikipedia.org/wiki/Accellera) 3 | * [Advanced Microcontroller Bus Architecture](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture) (AMBA) 4 | * [American National Standards Institute](https://en.wikipedia.org/wiki/American_National_Standards_Institute) (ANSI) 5 | * [ANSI Selected Standards](https://webstore.ansi.org/industry/selected-standards) 6 | * [ANSI Electronics Standards](https://webstore.ansi.org/industry/electronics) 7 | * [ANSI Semiconductor Standards](https://webstore.ansi.org/industry/semiconductors) 8 | * [Cache coherent interconnect for accelerators](https://en.wikipedia.org/wiki/Cache_coherent_interconnect_for_accelerators) (CCIX) 9 | * [Compute Express Link](https://en.wikipedia.org/wiki/Compute_Express_Link) (CXL) 10 | * [Coherent Accelerator Processor Interface](https://en.wikipedia.org/wiki/Coherent_Accelerator_Processor_Interface) (CAPI) 11 | * [Gen-Z](https://en.wikipedia.org/wiki/Gen-Z_(consortium)) 12 | * [IEEE Council on Electronic Design Automation](https://ieee-ceda.org/) (CEDA) 13 | * [IEEE Symposium-Workshop on Emerging AI/ML Trends](https://sweat.ieeebangalore.org/) (SWEAT) 14 | * [IEEE Design Automation Standards Committee](https://www.dasc.org/) (DASC) 15 | * [IEEE Global Semiconductors](https://semiconductors.ieee.org/) Ad Hoc of the IEEE Future Directions Committee 16 | * [Joint Electron Device Engineering Council](https://en.wikipedia.org/wiki/JEDEC) (JEDEC) Solid State Technology Association 17 | * [JEDEC memory standards](https://en.wikipedia.org/wiki/JEDEC_memory_standards) 18 | * [Joint Test Action Group](https://en.wikipedia.org/wiki/JTAG) (JTAG) 19 | * [Musical Instrument Digital Interface](https://en.wikipedia.org/wiki/MIDI) (MIDI) 20 | * [Mobile Industry Processor Interface](https://en.wikipedia.org/wiki/MIPI_Alliance) (MIPI) 21 | * [Moving Picture, Audio and Data Coding by Artificial Intelligence](https://mpai.community/) (MPAI) 22 | * [IEEE 3301-2022](https://standards.ieee.org/ieee/3301/11096/) Standard Adoption of Moving Picture, Audio and Data Coding by Artificial Intelligence (MPAI) Technical Specification Artificial Intelligence Framework (AIF) 1.1 23 | * [IEEE P3307](https://standards.ieee.org/ieee/3307/11503/) Adoption of Moving Picture, Audio and Data Coding by Artificial Intelligence (MPAI) Technical Specification Connected Autonomous Vehicle - Architecture (CAV) Version 1 24 | * [North American Charging Standard](https://en.wikipedia.org/wiki/North_American_Charging_Standard) (NACS) 25 | * [Opening the North American Charging Standard](https://www.tesla.com/blog/opening-north-american-charging-standard) by The Tesla Team, November 11, 2022 26 | * [SEMI](https://en.wikipedia.org/wiki/SEMI) 27 | * [Open Artwork System Interchange Standard](https://en.wikipedia.org/wiki/Open_Artwork_System_Interchange_Standard) (OASIS) replaced Graphic Design System [GDSII](https://en.wikipedia.org/wiki/GDSII) 28 | * [Semiconductor Industry Association](https://en.wikipedia.org/wiki/Semiconductor_Industry_Association) (SIA) 29 | * [Society of Motion Picture and Television Engineers](https://en.wikipedia.org/wiki/Society_of_Motion_Picture_and_Television_Engineers) (SMPTE) 30 | * [UL](https://en.wikipedia.org/wiki/UL_(safety_organization)) 31 | * [Video Electronics Standards Association](https://en.wikipedia.org/wiki/Video_Electronics_Standards_Association) (VESA) 32 | --------------------------------------------------------------------------------