├── combinational.v
├── control.v
├── decrypt.v
├── div_stage1.v
├── div_stage2.v
├── divider.v
├── ecc.v
├── encrypt_x.v
├── encrypt_y.v
├── mul_stage1.v
├── mul_stage2.v
├── multiplier.v
├── square.v
├── top_ecc.ucf
└── top_ecc.v


/combinational.v:
--------------------------------------------------------------------------------
  1 | module combinational(clk,reset,inst,
  2 | 	     c10,c11,c12,c13,c14,
  3 | 	     c20,c21,c22,c23,c24,
  4 |              c30,c31,c32,c33,c34,
  5 | 		 c0,c1,c2,c3,c4);
  6 | 
  7 | input clk;
  8 | input reset;
  9 | 
 10 | input [2:0] inst;
 11 | 
 12 | input [7:0] c10;
 13 | input [7:0] c11;
 14 | input [7:0] c12;
 15 | input [7:0] c13;
 16 | input [7:0] c14;
 17 | 
 18 | input [7:0] c20;
 19 | input [7:0] c21;
 20 | input [7:0] c22;
 21 | input [7:0] c23;
 22 | input [7:0] c24;
 23 | 
 24 | input [7:0] c30;
 25 | input [7:0] c31;
 26 | input [7:0] c32;
 27 | input [7:0] c33;
 28 | input [7:0] c34;
 29 | 
 30 | output [7:0] c0;
 31 | output [7:0] c1;
 32 | output [7:0] c2;
 33 | output [7:0] c3;
 34 | output [7:0] c4;
 35 | 
 36 | wire clk;
 37 | wire reset;
 38 | 
 39 | wire [2:0] inst;
 40 | 
 41 | wire [7:0] c10;
 42 | wire [7:0] c11;
 43 | wire [7:0] c12;
 44 | wire [7:0] c13;
 45 | wire [7:0] c14;
 46 | 
 47 | wire [7:0] c20;
 48 | wire [7:0] c21;
 49 | wire [7:0] c22;
 50 | wire [7:0] c23;
 51 | wire [7:0] c24;
 52 | 
 53 | wire [7:0] c30;
 54 | wire [7:0] c31;
 55 | wire [7:0] c32;
 56 | wire [7:0] c33;
 57 | wire [7:0] c34;
 58 | 
 59 | reg [7:0] c0;
 60 | reg [7:0] c1;
 61 | reg [7:0] c2;
 62 | reg [7:0] c3;
 63 | reg [7:0] c4;
 64 | 
 65 | always@(posedge clk)
 66 | 	begin
 67 | 	   if(reset == 1)
 68 | 		begin
 69 | 		     c0 <= 8'd0;
 70 | 		     c1 <= 8'd0;
 71 | 	             c2 <= 8'd0;
 72 | 		     c3 <= 8'd0;	   
 73 | 		     c4 <= 8'd0;
 74 | 		end
 75 | 	   else if(inst == 3'd1)
 76 | 		begin
 77 | 			c0 <= c10;
 78 |                         c1 <= c11;
 79 | 			c2 <= c12;
 80 | 			c3 <= c13;
 81 | 			c4 <= c14;	
 82 | 		end
 83 |          else if(inst == 3'd2)
 84 | 		begin
 85 | 			c0 <= c20;
 86 |                         c1 <= c21;
 87 | 			c2 <= c22;
 88 | 			c3 <= c23;
 89 | 			c4 <= c24;	
 90 | 		end	
 91 | 	  else if(inst == 3'd3)
 92 | 		begin
 93 | 			c0 <= c30;
 94 |                         c1 <= c31;
 95 | 			c2 <= c32;
 96 | 			c3 <= c33;
 97 | 			c4 <= c34;	
 98 | 		end
 99 | 	  else 
100 | 		begin
101 | 			c0 <= c0;
102 |           	        c1 <= c1;
103 | 			c2 <= c2;
104 | 			c3 <= c3;
105 | 			c4 <= c4;	
106 | 		end
107 | 	end
108 | endmodule
109 | 
110 | 
111 | 
112 | 
113 | 
114 | 
115 | 
116 | 
117 | 


--------------------------------------------------------------------------------
/control.v:
--------------------------------------------------------------------------------
  1 | module control(clk,reset,ctrl,
  2 | 	   data_in,data_out,
  3 | 	   x_in,y_in,
  4 | 	   x_out1,y_out1,
  5 | 	   x_out2,y_out2,
  6 |    	   s0,valid);
  7 | 
  8 | input clk;
  9 | input reset;
 10 | input [2:0] ctrl;
 11 | 
 12 | input [31:0] data_in;
 13 | input [7:0] x_in;
 14 | input [7:0] y_in;
 15 | input valid;
 16 | 
 17 | output [31:0] data_out;
 18 | output [7:0] x_out1;
 19 | output [7:0] x_out2;
 20 | output [7:0] y_out1;
 21 | output [7:0] y_out2;
 22 | output s0;
 23 | 
 24 | wire clk;
 25 | wire reset;
 26 | wire [2:0] ctrl;
 27 | wire [31:0] data_in;
 28 | wire [7:0] x_in;
 29 | wire [7:0] y_in;
 30 | 
 31 | reg [31:0] data_out;
 32 | reg [7:0] x_out1;
 33 | reg [7:0] x_out2;
 34 | reg [7:0] y_out1;
 35 | reg [7:0] y_out2;
 36 | reg s0;
 37 | 
 38 | reg [4:0] count;
 39 | reg [4:0] temp;
 40 | 
 41 | reg [7:0] data_in_x0;
 42 | reg [7:0] data_in_y0;
 43 | reg [7:0] data_in_x1;
 44 | reg [7:0] data_in_y1;
 45 | 
 46 | wire [7:0] data_out_x0;
 47 | wire [7:0] data_out_y0;
 48 | wire [7:0] data_out_x1;
 49 | wire [7:0] data_out_y1;
 50 | 
 51 | reg [7:0] data_in_de0;
 52 | wire [7:0] data_out_de0;
 53 | 
 54 | reg [7:0] data_in_de1;
 55 | wire [7:0] data_out_de1;
 56 | 
 57 | encrypt_x e1(clk,reset,data_in_x0,data_out_x0);
 58 | encrypt_y e2(clk,reset,data_in_y0,data_out_y0);
 59 | 
 60 | encrypt_x e3(clk,reset,data_in_x1,data_out_x1);
 61 | encrypt_y e4(clk,reset,data_in_y1,data_out_y1);
 62 | 
 63 | decrypt   e6(clk,reset,data_in_de0,data_out_de0);
 64 | decrypt   e7(clk,reset,data_in_de1,data_out_de1);
 65 | 
 66 | always@(posedge clk)
 67 | 	begin
 68 | 		if(reset)
 69 | 			count <= 0;
 70 | 		else if (count == 31)
 71 | 				count <= 31;
 72 | 			else 
 73 | 				count <= count + 1;
 74 | 	end
 75 | 
 76 | always@(posedge clk)
 77 | 	begin
 78 | 		if(reset == 1)
 79 | 			begin
 80 | 				data_out <= 0;
 81 | 				data_in_x0 <= 0;
 82 | 				data_in_x1 <= 0;
 83 | 				data_in_y0 <= 0;
 84 | 				data_in_y1 <= 0;
 85 | 				x_out1     <= 0;
 86 | 				x_out2     <= 0;
 87 | 				y_out1     <= 0;
 88 | 				y_out2     <= 0;
 89 | 				s0         <= 0;
 90 | 			end
 91 | 		   else if( count == 0)
 92 | 			begin
 93 | 				data_in_x0 <= data_in[7:0];	
 94 | 				data_in_y0 <= data_in[7:0];	
 95 | 				data_in_x1 <= data_in[15:8];	
 96 | 				data_in_y1 <= data_in[15:8];
 97 | 			end
 98 | 		   else if(count == 2)
 99 | 			begin
100 | 				x_out1     <= data_out_x0 ;
101 | 				y_out1     <= data_out_y0 ;
102 | 				x_out2     <= data_out_x1 ;
103 | 				y_out2     <= data_out_y1 ;
104 | 				data_in_x0 <= data_in[23:16];	
105 | 				data_in_y0 <= data_in[23:16];	
106 | 				data_in_x1 <= data_in[31:24];	
107 | 				data_in_y1 <= data_in[31:24];
108 | 				s0         <= 1;
109 | 			end
110 | 		   else if(count == 4)
111 | 			begin
112 | 				x_out1     <= data_out_x0 ;
113 | 				y_out1     <= data_out_y0 ;
114 | 				x_out2     <= data_out_x1 ;
115 | 				y_out2     <= data_out_y1 ;
116 | 				s0         <= 1;
117 | 			end
118 | 		  else if(valid == 1)
119 | 		  	begin
120 | 				data_in_de0 <= x_in;
121 | 				data_in_de1 <= y_in;
122 | 				temp        <= count;
123 | 			end
124 | 		  else if(count == temp + 2)
125 | 		  	begin	  
126 | 				data_out[7:0]  <= data_out_de0;
127 | 				data_out[15:8] <= data_out_de1;
128 | 			end
129 | 		  else if(count == temp + 1)
130 | 		  	begin
131 | 				data_in_de0 <= x_in;
132 | 				data_in_de1 <= y_in;
133 | 			end
134 | 		  else if(count == temp + 3)
135 | 		  	begin
136 | 				data_out[24:16]  <= data_out_de0;
137 | 				data_out[31:25]  <= data_out_de1;
138 | 			end
139 | 
140 | 		  else 
141 | 		  	begin
142 | 				s0 <= 0;
143 | 			end
144 | 
145 | 
146 | 	end
147 | 
148 | endmodule
149 | 
150 | 
151 | 
152 | 
153 | 
154 | 
155 | 
156 | 
157 | 
158 | 


--------------------------------------------------------------------------------
/decrypt.v:
--------------------------------------------------------------------------------
  1 | module decrypt(clk,reset,data_in,data_out);
  2 | input clk;
  3 | input reset;
  4 | input [7:0] data_in;
  5 | 
  6 | output [7:0] data_out;
  7 | 
  8 | wire clk;
  9 | wire reset;
 10 | wire [7:0] data_in;
 11 | 
 12 | reg [7:0] data_out;
 13 | 
 14 | reg [7:0] mem [0:255];
 15 | 
 16 | always@(posedge clk)
 17 |     begin
 18 |       if(reset == 1)
 19 |           begin
 20 |          mem[0] <= 0;
 21 |          mem[1] <= 0;
 22 |          mem[2] <= 1;
 23 |          mem[3] <= 2;
 24 |          mem[4] <= 3;
 25 |          mem[5] <= 4;
 26 |          mem[6] <= 5;
 27 |          mem[7] <= 6;
 28 |          mem[8] <= 7;
 29 |          mem[9] <= 8;
 30 |          mem[10] <= 9;
 31 |          mem[11] <= 10;
 32 |          mem[12] <= 11;
 33 |          mem[13] <= 12;
 34 |          mem[14] <= 13;
 35 |          mem[15] <= 14;
 36 |          mem[16] <= 15;
 37 |          mem[17] <= 16;
 38 |          mem[18] <= 17;
 39 |          mem[19] <= 18;
 40 |          mem[20] <= 19;
 41 |          mem[21] <= 20;
 42 |          mem[22] <= 21;
 43 |          mem[23] <= 22;
 44 |          mem[24] <= 23;
 45 |          mem[25] <= 24;
 46 |          mem[26] <= 25;
 47 |          mem[27] <= 26;
 48 |          mem[28] <= 27;
 49 |          mem[29] <= 28;
 50 |          mem[30] <= 29;
 51 |          mem[31] <= 30;
 52 |          mem[32] <= 31;
 53 |          mem[33] <= 32;
 54 |          mem[34] <= 33;
 55 |          mem[35] <= 34;
 56 |          mem[36] <= 35;
 57 |          mem[37] <= 36;
 58 |          mem[38] <= 37;
 59 |          mem[39] <= 38;
 60 |          mem[40] <= 39;
 61 |          mem[41] <= 40;
 62 |          mem[42] <= 41;
 63 |          mem[43] <= 42;
 64 |          mem[44] <= 43;
 65 |          mem[45] <= 44;
 66 |          mem[46] <= 45;
 67 |          mem[47] <= 46;
 68 |          mem[48] <= 47;
 69 |          mem[49] <= 48;
 70 |          mem[50] <= 49;
 71 |          mem[51] <= 50;
 72 |          mem[52] <= 51;
 73 |          mem[53] <= 52;
 74 |          mem[54] <= 53;
 75 |          mem[55] <= 54;
 76 |          mem[56] <= 55;
 77 |          mem[57] <= 56;
 78 |          mem[58] <= 57;
 79 |          mem[59] <= 58;
 80 |          mem[60] <= 59;
 81 |          mem[61] <= 60;
 82 |          mem[62] <= 61;
 83 |          mem[63] <= 62;
 84 |          mem[64] <= 63;
 85 |          mem[65] <= 64;
 86 |          mem[66] <= 65;
 87 |          mem[67] <= 66;
 88 |          mem[68] <= 67;
 89 |          mem[69] <= 68;
 90 |          mem[70] <= 69;
 91 |          mem[71] <= 70;
 92 |          mem[72] <= 71;
 93 |          mem[73] <= 72;
 94 |          mem[74] <= 73;
 95 |          mem[75] <= 74;
 96 |          mem[76] <= 75;
 97 |          mem[77] <= 76;
 98 |          mem[78] <= 77;
 99 |          mem[79] <= 78;
100 |          mem[80] <= 79;
101 |          mem[81] <= 80;
102 |          mem[82] <= 81;
103 |          mem[83] <= 82;
104 |          mem[84] <= 83;
105 |          mem[85] <= 84;
106 |          mem[86] <= 85;
107 |          mem[87] <= 86;
108 |          mem[88] <= 87;
109 |          mem[89] <= 88;
110 |          mem[90] <= 89;
111 |          mem[91] <= 90;
112 |          mem[92] <= 91;
113 |          mem[93] <= 92;
114 |          mem[94] <= 93;
115 |          mem[95] <= 94;
116 |          mem[96] <= 95;
117 |          mem[97] <= 96;
118 |          mem[98] <= 97;
119 |          mem[99] <= 98;
120 |          mem[100] <= 99;
121 |          mem[101] <= 100;
122 |          mem[102] <= 101;
123 |          mem[103] <= 102;
124 |          mem[104] <= 103;
125 |          mem[105] <= 104;
126 |          mem[106] <= 105;
127 |          mem[107] <= 106;
128 |          mem[108] <= 107;
129 |          mem[109] <= 108;
130 |          mem[110] <= 109;
131 |          mem[111] <= 110;
132 |          mem[112] <= 111;
133 |          mem[113] <= 112;
134 |          mem[114] <= 113;
135 |          mem[115] <= 114;
136 |          mem[116] <= 115;
137 |          mem[117] <= 116;
138 |          mem[118] <= 117;
139 |          mem[119] <= 118;
140 |          mem[120] <= 119;
141 |          mem[121] <= 120;
142 |          mem[122] <= 121;
143 |          mem[123] <= 122;
144 |          mem[124] <= 123;
145 |          mem[125] <= 124;
146 |          mem[126] <= 125;
147 |          mem[127] <= 126;
148 |          mem[128] <= 127;
149 |          mem[129] <= 128;
150 |          mem[130] <= 129;
151 |          mem[131] <= 130;
152 |          mem[132] <= 131;
153 |          mem[133] <= 132;
154 |          mem[134] <= 133;
155 |          mem[135] <= 134;
156 |          mem[136] <= 135;
157 |          mem[137] <= 136;
158 |          mem[138] <= 137;
159 |          mem[139] <= 138;
160 |          mem[140] <= 139;
161 |          mem[141] <= 140;
162 |          mem[142] <= 141;
163 |          mem[143] <= 142;
164 |          mem[144] <= 143;
165 |          mem[145] <= 144;
166 |          mem[146] <= 145;
167 |          mem[147] <= 146;
168 |          mem[148] <= 147;
169 |          mem[149] <= 148;
170 |          mem[150] <= 149;
171 |          mem[151] <= 150;
172 |          mem[152] <= 151;
173 |          mem[153] <= 152;
174 |          mem[154] <= 153;
175 |          mem[155] <= 154;
176 |          mem[156] <= 155;
177 |          mem[157] <= 156;
178 |          mem[158] <= 157;
179 |          mem[159] <= 158;
180 |          mem[160] <= 159;
181 |          mem[161] <= 160;
182 |          mem[162] <= 161;
183 |          mem[163] <= 162;
184 |          mem[164] <= 163;
185 |          mem[165] <= 164;
186 |          mem[166] <= 165;
187 |          mem[167] <= 166;
188 |          mem[168] <= 167;
189 |          mem[169] <= 168;
190 |          mem[170] <= 169;
191 |          mem[171] <= 170;
192 |          mem[172] <= 171;
193 |          mem[173] <= 172;
194 |          mem[174] <= 173;
195 |          mem[175] <= 174;
196 |          mem[176] <= 175;
197 |          mem[177] <= 176;
198 |          mem[178] <= 177;
199 |          mem[179] <= 178;
200 |          mem[180] <= 179;
201 |          mem[181] <= 180;
202 |          mem[182] <= 181;
203 |          mem[183] <= 182;
204 |          mem[184] <= 183;
205 |          mem[185] <= 184;
206 |          mem[186] <= 185;
207 |          mem[187] <= 186;
208 |          mem[188] <= 187;
209 |          mem[189] <= 188;
210 |          mem[190] <= 189;
211 |          mem[191] <= 190;
212 |          mem[192] <= 191;
213 |          mem[193] <= 192;
214 |          mem[194] <= 193;
215 |          mem[195] <= 194;
216 |          mem[196] <= 195;
217 |          mem[197] <= 196;
218 |          mem[198] <= 197;
219 |          mem[199] <= 198;
220 |          mem[200] <= 199;
221 |          mem[201] <= 200;
222 |          mem[202] <= 201;
223 |          mem[203] <= 202;
224 |          mem[204] <= 203;
225 |          mem[205] <= 204;
226 |          mem[206] <= 205;
227 |          mem[207] <= 206;
228 |          mem[208] <= 207;
229 |          mem[209] <= 208;
230 |          mem[210] <= 209;
231 |          mem[211] <= 210;
232 |          mem[212] <= 211;
233 |          mem[213] <= 212;
234 |          mem[214] <= 213;
235 |          mem[215] <= 214;
236 |          mem[216] <= 215;
237 |          mem[217] <= 216;
238 |          mem[218] <= 217;
239 |          mem[219] <= 218;
240 |          mem[220] <= 219;
241 |          mem[221] <= 220;
242 |          mem[222] <= 221;
243 |          mem[223] <= 222;
244 |          mem[224] <= 223;
245 |          mem[225] <= 224;
246 |          mem[226] <= 225;
247 |          mem[227] <= 226;
248 |          mem[228] <= 227;
249 |          mem[229] <= 228;
250 |          mem[230] <= 229;
251 |          mem[231] <= 230;
252 |          mem[232] <= 231;
253 |          mem[233] <= 232;
254 |          mem[234] <= 233;
255 |          mem[235] <= 234;
256 |          mem[236] <= 235;
257 |          mem[237] <= 236;
258 |          mem[238] <= 237;
259 |          mem[239] <= 238;
260 |          mem[240] <= 239;
261 |          mem[241] <= 240;
262 |          mem[242] <= 241;
263 |          mem[243] <= 242;
264 |          mem[244] <= 243;
265 |          mem[245] <= 244;
266 |          mem[246] <= 245;
267 |          mem[247] <= 246;
268 |          mem[248] <= 247;
269 |          mem[249] <= 248;
270 |          mem[250] <= 249;
271 |          mem[251] <= 250;
272 |          mem[252] <= 251;
273 |          mem[253] <= 252;
274 |          mem[254] <= 253;
275 |          mem[255] <= 254;
276 |          end
277 |           else
278 |             data_out <= mem[data_in];
279 | end
280 | endmodule
281 | 


--------------------------------------------------------------------------------
/div_stage1.v:
--------------------------------------------------------------------------------
 1 | module div_stage1(clk,reset,
 2 | 		  a0,a1,a2,a3,a4,
 3 | 		  b0,b1,b2,b3,b4,
 4 | 		  s0,s1,s2,s3,s4,s5,s6,s7,s8);
 5 | 
 6 | input clk;
 7 | input reset;
 8 | 
 9 | input [7:0] a0;
10 | input [7:0] a1;
11 | input [7:0] a2;
12 | input [7:0] a3;
13 | input [7:0] a4;
14 | 
15 | input [7:0] b0;
16 | input [7:0] b1;
17 | input [7:0] b2;
18 | input [7:0] b3;
19 | input [7:0] b4;
20 | 
21 | output [7:0] s0;
22 | output [7:0] s1;
23 | output [7:0] s2;
24 | output [7:0] s3;
25 | output [7:0] s4;
26 | output [7:0] s5;
27 | output [7:0] s6;
28 | output [7:0] s7;
29 | output [7:0] s8;
30 | 
31 | 
32 | wire clk;
33 | wire reset;
34 | 
35 | wire [7:0] a0;
36 | wire [7:0] a1;
37 | wire [7:0] a2;
38 | wire [7:0] a3;
39 | wire [7:0] a4;
40 | 
41 | wire [7:0] b0;
42 | wire [7:0] b1;
43 | wire [7:0] b2;
44 | wire [7:0] b3;
45 | wire [7:0] b4;
46 | 
47 | reg [7:0] s0;
48 | reg [7:0] s1;
49 | reg [7:0] s2;
50 | reg [7:0] s3;
51 | reg [7:0] s4;
52 | reg [7:0] s5;
53 | reg [7:0] s6;
54 | reg [7:0] s7;
55 | reg [7:0] s8;
56 | 
57 | always@(posedge clk)
58 | 	begin
59 | 		if(reset == 1)
60 | 			begin
61 | 			   s0 = 8'd0;
62 | 			   s1 = 8'd0;
63 | 			   s2 = 8'd0;
64 | 			   s3 = 8'd0;
65 | 			   s4 = 8'd0;
66 | 			   s5=  8'd0;
67 | 			   s6 = 8'd0;
68 | 			   s7 = 8'd0;
69 | 			   s8 = 8'd0;
70 | 			end
71 | 		else
72 | 			begin
73 | 				s0 = (a0 & b0);
74 | 				s1 = (a0 & b1) + (a1 & b0) ;
75 | 			        s2 = (a0 & b2) + (a1 & b1) + (a2 & b0);
76 | 				s3 = (a0 & b3) + (a1 & b2) + (a2 & b1) + (a3 & b0);
77 | 				s4 = (a0 & b4) + (a1 & b3) + (a2 & b2) + (a3 & b1) + (a4 & b0);
78 | 				s5 = (a1 & b4) + (a2 & b3) + (a3 & b2) + (a4 & b1);
79 | 				s6 = (a2 & b4) + (a3 & b3) + (a4 & b2);
80 | 				s7 = (a3 & b4) + (a4 & b3);
81 | 				s8 = (a4 & b4);
82 | 			end
83 | 	end
84 | 		 
85 | 
86 | endmodule
87 | 
88 | 
89 | 
90 | 
91 | 
92 | 
93 | 
94 | 
95 | 
96 | 


--------------------------------------------------------------------------------
/div_stage2.v:
--------------------------------------------------------------------------------
 1 | module div_stage2(clk,reset,
 2 | 		  s0,s1,s2,s3,s4,s5,s6,s7,s8,
 3 | 		  c0,c1,c2,c3,c4);
 4 | 
 5 | input clk;
 6 | input reset;
 7 | 
 8 | input [7:0] s0;
 9 | input [7:0] s1;
10 | input [7:0] s2;
11 | input [7:0] s3;
12 | input [7:0] s4;
13 | input [7:0] s5;
14 | input [7:0] s6;
15 | input [7:0] s7;
16 | input [7:0] s8;
17 | 
18 | output [7:0] c0;
19 | output [7:0] c1;
20 | output [7:0] c2;
21 | output [7:0] c3;
22 | output [7:0] c4;
23 | 
24 | wire clk;
25 | wire reset;
26 | 
27 | wire [7:0] s0;
28 | wire [7:0] s1;
29 | wire [7:0] s2;
30 | wire [7:0] s3;
31 | wire [7:0] s4;
32 | wire [7:0] s5;
33 | wire [7:0] s6;
34 | wire [7:0] s7;
35 | wire [7:0] s8;
36 | 
37 | reg [7:0] c0;
38 | reg [7:0] c1;
39 | reg [7:0] c2;
40 | reg [7:0] c3;
41 | reg [7:0] c4;
42 | 
43 | always@(posedge clk)
44 | 	begin
45 | 		if(reset == 1)
46 | 			begin
47 | 			   c0 = 8'd0;
48 | 			   c1 = 8'd0;
49 | 			   c2 = 8'd0;
50 | 			   c3 = 8'd0;
51 | 			   c4 = 8'd0;
52 | 			end
53 | 		else
54 | 			begin
55 | 		         c0 = s0 - s5 - s6;
56 | 			   c1 = s1 - s6;
57 | 			   c2 = s2 - s7 - s5 - s8;
58 | 			   c3 = s3 - s8 - s6;
59 | 			   c4 = s4 - s7;
60 | 			end
61 | 	end
62 | 		 
63 | 
64 | endmodule
65 | 
66 | 
67 | 
68 | 
69 | 
70 | 
71 | 
72 | 
73 | 
74 | 


--------------------------------------------------------------------------------
/divider.v:
--------------------------------------------------------------------------------
 1 | module divider(clk,reset,
 2 | 			a0,a1,a2,a3,a4,
 3 | 			b0,b1,b2,b3,b4,
 4 | 			c0,c1,c2,c3,c4);
 5 | 
 6 | input clk;
 7 | input reset;
 8 | 
 9 | input [7:0] a0;
10 | input [7:0] a1;
11 | input [7:0] a2;
12 | input [7:0] a3;
13 | input [7:0] a4;
14 | 
15 | input [7:0] b0;
16 | input [7:0] b1;
17 | input [7:0] b2;
18 | input [7:0] b3;
19 | input [7:0] b4;
20 | 
21 | output [7:0] c0;
22 | output [7:0] c1;
23 | output [7:0] c2;
24 | output [7:0] c3;
25 | output [7:0] c4;
26 | 
27 | wire clk;
28 | wire reset;
29 | 
30 | wire [7:0] a0;
31 | wire [7:0] a1;
32 | wire [7:0] a2;
33 | wire [7:0] a3;
34 | wire [7:0] a4;
35 | 
36 | wire [7:0] b0;
37 | wire [7:0] b1;
38 | wire [7:0] b2;
39 | wire [7:0] b3;
40 | wire [7:0] b4;
41 | 
42 | wire [7:0] c0;
43 | wire [7:0] c1;
44 | wire [7:0] c2;
45 | wire [7:0] c3;
46 | wire [7:0] c4;
47 | 
48 | wire [7:0] s0;
49 | wire [7:0] s1;
50 | wire [7:0] s2;
51 | wire [7:0] s3;
52 | wire [7:0] s4;
53 | wire [7:0] s5;
54 | wire [7:0] s6;
55 | wire [7:0] s7;
56 | wire [7:0] s8;
57 | 
58 | div_stage1 st1(clk,reset,a0,a1,a2,a3,a4,b0,b1,b2,b3,b4,s0,s1,s2,s3,s4,s5,s6,s7,s8);
59 | 
60 | div_stage2 st2(clk,reset,s0,s1,s2,s3,s4,s5,s6,s7,s8,c0,c1,c2,c3,c4);
61 | 
62 | endmodule
63 | 
64 | 
65 | 
66 | 
67 | 
68 | 
69 | 
70 | 
71 | 
72 | 


--------------------------------------------------------------------------------
/ecc.v:
--------------------------------------------------------------------------------
  1 | module ecc(clk,reset,inst,
  2 | 		  a0,a1,a2,a3,a4,
  3 | 		  b0,b1,b2,b3,b4,
  4 | 		  c0,c1,c2,c3,c4);
  5 | 
  6 | input clk;
  7 | input reset;
  8 | input [2:0] inst;
  9 | 
 10 | input [7:0] a0;
 11 | input [7:0] a1;
 12 | input [7:0] a2;
 13 | input [7:0] a3;
 14 | input [7:0] a4;
 15 | 
 16 | input [7:0] b0;
 17 | input [7:0] b1;
 18 | input [7:0] b2;
 19 | input [7:0] b3;
 20 | input [7:0] b4;
 21 | 
 22 | output [7:0] c0;
 23 | output [7:0] c1;
 24 | output [7:0] c2;
 25 | output [7:0] c3;
 26 | output [7:0] c4;
 27 | 
 28 | 
 29 | wire clk;
 30 | wire reset;
 31 | wire [2:0] inst;
 32 | 
 33 | wire [7:0] a0;
 34 | wire [7:0] a1;
 35 | wire [7:0] a2;
 36 | wire [7:0] a3;
 37 | wire [7:0] a4;
 38 | 
 39 | wire [7:0] b0;
 40 | wire [7:0] b1;
 41 | wire [7:0] b2;
 42 | wire [7:0] b3;
 43 | wire [7:0] b4;
 44 | 
 45 | wire [7:0] c0;
 46 | wire [7:0] c1;
 47 | wire [7:0] c2;
 48 | wire [7:0] c3;
 49 | wire [7:0] c4;
 50 | 
 51 | wire [7:0] c10;
 52 | wire [7:0] c11;
 53 | wire [7:0] c12;
 54 | wire [7:0] c13;
 55 | wire [7:0] c14;
 56 | 
 57 | wire [7:0] c20;
 58 | wire [7:0] c21;
 59 | wire [7:0] c22;
 60 | wire [7:0] c23;
 61 | wire [7:0] c24;
 62 | 
 63 | wire [7:0] c30;
 64 | wire [7:0] c31;
 65 | wire [7:0] c32;
 66 | wire [7:0] c33;
 67 | wire [7:0] c34;
 68 | 
 69 | multiplier e1(clk,reset,
 70 |               a0,a1,a2,a3,a4,
 71 |               b0,b1,b2,b3,b4,
 72 | 	      c10,c11,c12,c13,c14);
 73 | 
 74 | divider    e2(clk,reset,
 75 |               a0,a1,a2,a3,a4,
 76 |               b0,b1,b2,b3,b4,
 77 | 	      c20,c21,c22,c23,c24);
 78 | 
 79 | 
 80 | square     e3(clk,reset,
 81 |                a0,a1,a2,a3,a4,
 82 | 	       c30,c31,c32,c33,c34);
 83 | 
 84 | combinational e4(clk,reset,inst,
 85 | 	      c10,c11,c12,c13,c14,
 86 | 	      c20,c21,c22,c23,c24,
 87 | 	      c30,c31,c32,c33,c34,
 88 |               c0,c1,c2,c3,c4);
 89 | 
 90 | 
 91 | 
 92 | 
 93 | 
 94 | endmodule
 95 | 
 96 | 
 97 | 
 98 | 
 99 | 
100 | 
101 | 
102 | 
103 | 
104 | 


--------------------------------------------------------------------------------
/encrypt_x.v:
--------------------------------------------------------------------------------
  1 | module encrypt_x(clk,reset,data_in,data_out);
  2 | input clk;
  3 | input reset;
  4 | input [7:0] data_in;
  5 | 
  6 | output [7:0] data_out;
  7 | 
  8 | wire clk;
  9 | wire reset;
 10 | wire [7:0] data_in;
 11 | 
 12 | reg [7:0] data_out;
 13 | 
 14 | reg [7:0] mem [0:255];
 15 | 
 16 | always@(posedge clk)
 17 |   begin
 18 |     if(reset == 1)
 19 |       begin
 20 |       mem[3] <= 4;
 21 | 	    mem[4] <= 5;
 22 | 	    mem[6] <= 7;
 23 | 	    mem[7] <= 8;
 24 | 	    mem[10] <= 11;
 25 | 	    mem[11] <= 12;
 26 | 	    mem[12] <= 13;
 27 | 	    mem[14] <= 15;
 28 | 	    mem[15] <= 16;
 29 | 	    mem[16] <= 17;
 30 | 	    mem[18] <= 19;
 31 | 	    mem[19] <= 20;
 32 | 	    mem[21] <= 22;
 33 | 	    mem[22] <= 23;
 34 | 	    mem[23] <= 24;
 35 | 	    mem[26] <= 27;
 36 | 	    mem[27] <= 28;
 37 | 	    mem[29] <= 30;
 38 | 	    mem[30] <= 31;
 39 | 	    mem[33] <= 34;
 40 | 	    mem[34] <= 35;
 41 | 	    mem[35] <= 36;
 42 | 	    mem[37] <= 38;
 43 | 	    mem[38] <= 39;
 44 | 	    mem[39] <= 40;
 45 | 	    mem[41] <= 42;
 46 | 	    mem[42] <= 43;
 47 | 	    mem[44] <= 45;
 48 | 	    mem[45] <= 46;
 49 | 	    mem[46] <= 47;
 50 | 	    mem[49] <= 50;
 51 | 	    mem[50] <= 51;
 52 | 	    mem[52] <= 53;
 53 | 	    mem[53] <= 54;
 54 | 	    mem[56] <= 57;
 55 | 	    mem[57] <= 58;
 56 | 	    mem[58] <= 59;
 57 | 	    mem[60] <= 61;
 58 | 	    mem[61] <= 62;
 59 | 	    mem[62] <= 63;
 60 | 	    mem[64] <= 65;
 61 | 	    mem[65] <= 66;
 62 | 	    mem[67] <= 68;
 63 | 	    mem[68] <= 69;
 64 | 	    mem[69] <= 70;
 65 | 	    mem[72] <= 73;
 66 | 	    mem[73] <= 74;
 67 | 	    mem[75] <= 76;
 68 | 	    mem[76] <= 77;
 69 | 	    mem[79] <= 80;
 70 | 	    mem[80] <= 81;
 71 | 	    mem[81] <= 82;
 72 | 	    mem[83] <= 84;
 73 | 	    mem[84] <= 85;
 74 | 	    mem[85] <= 86;
 75 | 	    mem[87] <= 88;
 76 | 	    mem[88] <= 89;
 77 | 	    mem[90] <= 91;
 78 | 	    mem[91] <= 92;
 79 | 	    mem[92] <= 93;
 80 | 	    mem[95] <= 96;
 81 | 	    mem[96] <= 97;
 82 | 	    mem[98] <= 99;
 83 | 	    mem[99] <= 100;
 84 | 	    mem[102] <= 103;
 85 | 	    mem[103] <= 104;
 86 | 	    mem[104] <= 105;
 87 | 	    mem[106] <= 107;
 88 | 	    mem[107] <= 108;
 89 | 	    mem[108] <= 109;
 90 | 	    mem[110] <= 111;
 91 | 	    mem[111] <= 112;
 92 | 	    mem[113] <= 114;
 93 | 	    mem[114] <= 115;
 94 | 	    mem[115] <= 116;
 95 | 	    mem[118] <= 119;
 96 | 	    mem[119] <= 120;
 97 | 	    mem[121] <= 122;
 98 | 	    mem[122] <= 123;
 99 | 	    mem[125] <= 126;
100 | 	    mem[126] <= 127;
101 | 	    mem[127] <= 128;
102 | 	    mem[129] <= 130;
103 | 	    mem[130] <= 131;
104 | 	    mem[131] <= 132;
105 | 	    mem[133] <= 134;
106 | 	    mem[134] <= 135;
107 | 	    mem[136] <= 137;
108 | 	    mem[137] <= 138;
109 | 	    mem[138] <= 139;
110 | 	    mem[141] <= 142;
111 | 	    mem[142] <= 143;
112 | 	    mem[144] <= 145;
113 | 	    mem[145] <= 146;
114 | 	    mem[148] <= 149;
115 | 	    mem[149] <= 150;
116 | 	    mem[150] <= 151;
117 | 	    mem[152] <= 153;
118 | 	    mem[153] <= 154;
119 | 	    mem[154] <= 155;
120 | 	    mem[156] <= 157;
121 | 	    mem[157] <= 158;
122 | 	    mem[159] <= 160;
123 | 	    mem[160] <= 161;
124 | 	    mem[161] <= 162;
125 | 	    mem[164] <= 165;
126 | 	    mem[165] <= 166;
127 | 	    mem[167] <= 168;
128 | 	    mem[168] <= 169;
129 | 	    mem[171] <= 172;
130 | 	    mem[172] <= 173;
131 | 	    mem[173] <= 174;
132 | 	    mem[175] <= 176;
133 | 	    mem[176] <= 177;
134 | 	    mem[177] <= 178;
135 | 	    mem[179] <= 180;
136 | 	    mem[180] <= 181;
137 | 	    mem[182] <= 183;
138 | 	    mem[183] <= 184;
139 | 	    mem[184] <= 185;
140 | 	    mem[187] <= 188;
141 | 	    mem[188] <= 189;
142 | 	    mem[190] <= 191;
143 | 	    mem[191] <= 192;
144 | 	    mem[194] <= 195;
145 | 	    mem[195] <= 196;
146 | 	    mem[196] <= 197;
147 | 	    mem[198] <= 199;
148 | 	    mem[199] <= 200;
149 | 	    mem[200] <= 201;
150 | 	    mem[202] <= 203;
151 | 	    mem[203] <= 204;
152 | 	    mem[205] <= 206;
153 | 	    mem[206] <= 207;
154 | 	    mem[207] <= 208;
155 | 	    mem[210] <= 211;
156 | 	    mem[211] <= 212;
157 | 	    mem[213] <= 214;
158 | 	    mem[214] <= 215;
159 | 	    mem[217] <= 218;
160 | 	    mem[218] <= 219;
161 | 	    mem[219] <= 220;
162 | 	    mem[221] <= 222;
163 | 	    mem[222] <= 223;
164 | 	    mem[223] <= 224;
165 | 	    mem[225] <= 226;
166 | 	    mem[226] <= 227;
167 | 	    mem[228] <= 229;
168 | 	    mem[229] <= 230;
169 | 	    mem[230] <= 231;
170 | 	    mem[233] <= 234;
171 | 	    mem[234] <= 235;
172 | 	    mem[236] <= 237;
173 | 	    mem[237] <= 238;
174 | 	    mem[240] <= 241;
175 | 	    mem[241] <= 242;
176 | 	    mem[242] <= 243;
177 | 	    mem[244] <= 245;
178 | 	    mem[245] <= 246;
179 | 	    mem[246] <= 247;
180 | 	    mem[248] <= 249;
181 | 	    mem[249] <= 250;
182 | 	    mem[251] <= 252;
183 | 	    mem[252] <= 253;
184 | 	    mem[253] <= 254;
185 |       data_out <= 0;
186 |       end
187 |       else
188 |         data_out <= mem[data_in];
189 | 
190 | end
191 | 
192 | endmodule
193 |           
194 | 
195 | 


--------------------------------------------------------------------------------
/encrypt_y.v:
--------------------------------------------------------------------------------
  1 | module encrypt_y(clk,reset,data_in,data_out);
  2 | input clk;
  3 | input reset;
  4 | input [7:0] data_in;
  5 | 
  6 | output [7:0] data_out;
  7 | 
  8 | wire clk;
  9 | wire reset;
 10 | wire [7:0] data_in;
 11 | 
 12 | reg [7:0] data_out;
 13 | 
 14 | reg [7:0] mem [0:255];
 15 | 
 16 | always@(posedge clk)
 17 | begin
 18 |       if(reset == 1)
 19 |          begin
 20 |             mem[3] <= 8;
 21 |             mem[4] <= 3;
 22 |             mem[6] <= 8;
 23 |             mem[7] <= 5;
 24 |             mem[10] <= 6;
 25 |             mem[11] <= 8;
 26 |             mem[12] <= 7;
 27 |             mem[14] <= 11;
 28 |             mem[15] <= 6;
 29 |             mem[16] <= 1;
 30 |             mem[18] <= 6;
 31 |             mem[19] <= 7;
 32 |             mem[21] <= 2;
 33 |             mem[22] <= 2;
 34 |             mem[23] <= 2;
 35 |             mem[26] <= 8;
 36 |             mem[27] <= 3;
 37 |             mem[29] <= 8;
 38 |             mem[30] <= 5;
 39 |             mem[33] <= 6;
 40 |             mem[34] <= 8;
 41 |             mem[35] <= 7;
 42 |             mem[37] <= 11;
 43 |             mem[38] <= 6;
 44 |             mem[39] <= 1;
 45 |             mem[41] <= 6;
 46 |             mem[42] <= 7;
 47 |             mem[44] <= 2;
 48 |             mem[45] <= 2;
 49 |             mem[46] <= 2;
 50 |             mem[49] <= 8;
 51 |             mem[50] <= 3;
 52 |             mem[52] <= 8;
 53 |             mem[53] <= 5;
 54 |             mem[56] <= 6;
 55 |             mem[57] <= 8;
 56 |             mem[58] <= 7;
 57 |             mem[60] <= 11;
 58 |             mem[61] <= 6;
 59 |             mem[62] <= 1;
 60 |             mem[64] <= 6;
 61 |             mem[65] <= 7;
 62 |             mem[67] <= 2;
 63 |             mem[68] <= 2;
 64 |             mem[69] <= 2;
 65 |             mem[72] <= 8;
 66 |             mem[73] <= 3;
 67 |             mem[75] <= 8;
 68 |             mem[76] <= 5;
 69 |             mem[79] <= 6;
 70 |             mem[80] <= 8;
 71 |             mem[81] <= 7;
 72 |             mem[83] <= 11;
 73 |             mem[84] <= 6;
 74 |             mem[85] <= 1;
 75 |             mem[87] <= 6;
 76 |             mem[88] <= 7;
 77 |             mem[90] <= 2;
 78 |             mem[91] <= 2;
 79 |             mem[92] <= 2;
 80 |             mem[95] <= 8;
 81 |             mem[96] <= 3;
 82 |             mem[98] <= 8;
 83 |             mem[99] <= 5;
 84 |             mem[102] <= 6;
 85 |             mem[103] <= 8;
 86 |             mem[104] <= 7;
 87 |             mem[106] <= 11;
 88 |             mem[107] <= 6;
 89 |             mem[108] <= 1;
 90 |             mem[110] <= 6;
 91 |             mem[111] <= 7;
 92 |             mem[113] <= 2;
 93 |             mem[114] <= 2;
 94 |             mem[115] <= 2;
 95 |             mem[118] <= 8;
 96 |             mem[119] <= 3;
 97 |             mem[121] <= 8;
 98 |             mem[122] <= 5;
 99 |             mem[125] <= 6;
100 |             mem[126] <= 8;
101 |             mem[127] <= 7;
102 |             mem[129] <= 11;
103 |             mem[130] <= 6;
104 |             mem[131] <= 1;
105 |             mem[133] <= 6;
106 |             mem[134] <= 7;
107 |             mem[136] <= 2;
108 |             mem[137] <= 2;
109 |             mem[138] <= 2;
110 |             mem[141] <= 8;
111 |             mem[142] <= 3;
112 |             mem[144] <= 8;
113 |             mem[145] <= 5;
114 |             mem[148] <= 6;
115 |             mem[149] <= 8;
116 |             mem[150] <= 7;
117 |             mem[152] <= 11;
118 |             mem[153] <= 6;
119 |             mem[154] <= 1;
120 |             mem[156] <= 6;
121 |             mem[157] <= 7;
122 |             mem[159] <= 2;
123 |             mem[160] <= 2;
124 |             mem[161] <= 2;
125 |             mem[164] <= 8;
126 |             mem[165] <= 3;
127 |             mem[167] <= 8;
128 |             mem[168] <= 5;
129 |             mem[171] <= 6;
130 |             mem[172] <= 8;
131 |             mem[173] <= 7;
132 |             mem[175] <= 11;
133 |             mem[176] <= 6;
134 |             mem[177] <= 1;
135 |             mem[179] <= 6;
136 |             mem[180] <= 7;
137 |             mem[182] <= 2;
138 |             mem[183] <= 2;
139 |             mem[184] <= 2;
140 |             mem[187] <= 8;
141 |             mem[188] <= 3;
142 |             mem[190] <= 8;
143 |             mem[191] <= 5;
144 |             mem[194] <= 6;
145 |             mem[195] <= 8;
146 |             mem[196] <= 7;
147 |             mem[198] <= 11;
148 |             mem[199] <= 6;
149 |             mem[200] <= 1;
150 |             mem[202] <= 6;
151 |             mem[203] <= 7;
152 |             mem[205] <= 2;
153 |             mem[206] <= 2;
154 |             mem[207] <= 2;
155 |             mem[210] <= 8;
156 |             mem[211] <= 3;
157 |             mem[213] <= 8;
158 |             mem[214] <= 5;
159 |             mem[217] <= 6;
160 |             mem[218] <= 8;
161 |             mem[219] <= 7;
162 |             mem[221] <= 11;
163 |             mem[222] <= 6;
164 |             mem[223] <= 1;
165 |             mem[225] <= 6;
166 |             mem[226] <= 7;
167 |             mem[228] <= 2;
168 |             mem[229] <= 2;
169 |             mem[230] <= 2;
170 |             mem[233] <= 8;
171 |             mem[234] <= 3;
172 |             mem[236] <= 8;
173 |             mem[237] <= 5;
174 |             mem[240] <= 6;
175 |             mem[241] <= 8;
176 |             mem[242] <= 7;
177 |             mem[244] <= 11;
178 |             mem[245] <= 6;
179 |             mem[246] <= 1;
180 |             mem[248] <= 6;
181 |             mem[249] <= 7;
182 |             mem[251] <= 2;
183 |             mem[252] <= 2;
184 |             mem[253] <= 2;
185 |           end
186 | 
187 |           else
188 |               data_out <= mem[data_in];
189 | 
190 |   end
191 | 
192 | endmodule  
193 | 


--------------------------------------------------------------------------------
/mul_stage1.v:
--------------------------------------------------------------------------------
 1 | module mul_stage1(clk,reset,
 2 | 		  a0,a1,a2,a3,a4,
 3 | 		  b0,b1,b2,b3,b4,
 4 | 		  s0,s1,s2,s3,s4,s5,s6,s7,s8);
 5 | 
 6 | input clk;
 7 | input reset;
 8 | 
 9 | input [7:0] a0;
10 | input [7:0] a1;
11 | input [7:0] a2;
12 | input [7:0] a3;
13 | input [7:0] a4;
14 | 
15 | input [7:0] b0;
16 | input [7:0] b1;
17 | input [7:0] b2;
18 | input [7:0] b3;
19 | input [7:0] b4;
20 | 
21 | output [7:0] s0;
22 | output [7:0] s1;
23 | output [7:0] s2;
24 | output [7:0] s3;
25 | output [7:0] s4;
26 | output [7:0] s5;
27 | output [7:0] s6;
28 | output [7:0] s7;
29 | output [7:0] s8;
30 | 
31 | 
32 | wire clk;
33 | wire reset;
34 | 
35 | wire [7:0] a0;
36 | wire [7:0] a1;
37 | wire [7:0] a2;
38 | wire [7:0] a3;
39 | wire [7:0] a4;
40 | 
41 | wire [7:0] b0;
42 | wire [7:0] b1;
43 | wire [7:0] b2;
44 | wire [7:0] b3;
45 | wire [7:0] b4;
46 | 
47 | reg [7:0] s0;
48 | reg [7:0] s1;
49 | reg [7:0] s2;
50 | reg [7:0] s3;
51 | reg [7:0] s4;
52 | reg [7:0] s5;
53 | reg [7:0] s6;
54 | reg [7:0] s7;
55 | reg [7:0] s8;
56 | 
57 | always@(posedge clk)
58 | 	begin
59 | 		if(reset == 1)
60 | 			begin
61 | 			   s0 = 8'd0;
62 | 			   s1 = 8'd0;
63 | 			   s2 = 8'd0;
64 | 			   s3 = 8'd0;
65 | 			   s4 = 8'd0;
66 | 			   s5=  8'd0;
67 | 			   s6 = 8'd0;
68 | 			   s7 = 8'd0;
69 | 			   s8 = 8'd0;
70 | 			end
71 | 		else
72 | 			begin
73 | 				s0 = (a0 & b0);
74 | 				s1 = (a0 & b1) + (a1 & b0) ;
75 | 			      s2 = (a0 & b2) + (a1 & b1) + (a2 & b0);
76 | 				s3 = (a0 & b3) + (a1 & b2) + (a2 & b1) + (a3 & b0);
77 | 				s4 = (a0 & b4) + (a1 & b3) + (a2 & b2) + (a3 & b1) + (a4 & b0);
78 | 				s5 = (a1 & b4) + (a2 & b3) + (a3 & b2) + (a4 & b1);
79 | 				s6 = (a2 & b4) + (a3 & b3) + (a4 & b2);
80 | 				s7 = (a3 & b4) + (a4 & b3);
81 | 				s8 = (a4 & b4);
82 | 			end
83 | 	end
84 | 		 
85 | 
86 | endmodule
87 | 
88 | 
89 | 
90 | 
91 | 
92 | 
93 | 
94 | 
95 | 
96 | 


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/mul_stage2.v:
--------------------------------------------------------------------------------
 1 | module mul_stage2(clk,reset,
 2 | 		  s0,s1,s2,s3,s4,s5,s6,s7,s8,
 3 | 		  c0,c1,c2,c3,c4);
 4 | 
 5 | input clk;
 6 | input reset;
 7 | 
 8 | input [7:0] s0;
 9 | input [7:0] s1;
10 | input [7:0] s2;
11 | input [7:0] s3;
12 | input [7:0] s4;
13 | input [7:0] s5;
14 | input [7:0] s6;
15 | input [7:0] s7;
16 | input [7:0] s8;
17 | 
18 | output [7:0] c0;
19 | output [7:0] c1;
20 | output [7:0] c2;
21 | output [7:0] c3;
22 | output [7:0] c4;
23 | 
24 | wire clk;
25 | wire reset;
26 | 
27 | wire [7:0] s0;
28 | wire [7:0] s1;
29 | wire [7:0] s2;
30 | wire [7:0] s3;
31 | wire [7:0] s4;
32 | wire [7:0] s5;
33 | wire [7:0] s6;
34 | wire [7:0] s7;
35 | wire [7:0] s8;
36 | 
37 | reg [7:0] c0;
38 | reg [7:0] c1;
39 | reg [7:0] c2;
40 | reg [7:0] c3;
41 | reg [7:0] c4;
42 | 
43 | always@(posedge clk)
44 | 	begin
45 | 		if(reset == 1)
46 | 			begin
47 | 			   c0 = 8'd0;
48 | 			   c1 = 8'd0;
49 | 			   c2 = 8'd0;
50 | 			   c3 = 8'd0;
51 | 			   c4 = 8'd0;
52 | 			end
53 | 		else
54 | 			begin
55 | 		         c0 = s0 + s5 + s6;
56 | 			   c1 = s1 + s6;
57 | 			   c2 = s2 + s7 + s5 + s8;
58 | 			   c3 = s3 + s8 + s6;
59 | 			   c4 = s4 + s7;
60 | 			end
61 | 	end
62 | 		 
63 | 
64 | endmodule
65 | 
66 | 
67 | 
68 | 
69 | 
70 | 
71 | 
72 | 
73 | 
74 | 


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/multiplier.v:
--------------------------------------------------------------------------------
 1 | module multiplier(clk,reset,
 2 | 			a0,a1,a2,a3,a4,
 3 | 			b0,b1,b2,b3,b4,
 4 | 			c0,c1,c2,c3,c4);
 5 | 
 6 | input clk;
 7 | input reset;
 8 | 
 9 | input [7:0] a0;
10 | input [7:0] a1;
11 | input [7:0] a2;
12 | input [7:0] a3;
13 | input [7:0] a4;
14 | 
15 | input [7:0] b0;
16 | input [7:0] b1;
17 | input [7:0] b2;
18 | input [7:0] b3;
19 | input [7:0] b4;
20 | 
21 | output [7:0] c0;
22 | output [7:0] c1;
23 | output [7:0] c2;
24 | output [7:0] c3;
25 | output [7:0] c4;
26 | 
27 | wire clk;
28 | wire reset;
29 | 
30 | wire [7:0] a0;
31 | wire [7:0] a1;
32 | wire [7:0] a2;
33 | wire [7:0] a3;
34 | wire [7:0] a4;
35 | 
36 | wire [7:0] b0;
37 | wire [7:0] b1;
38 | wire [7:0] b2;
39 | wire [7:0] b3;
40 | wire [7:0] b4;
41 | 
42 | wire [7:0] c0;
43 | wire [7:0] c1;
44 | wire [7:0] c2;
45 | wire [7:0] c3;
46 | wire [7:0] c4;
47 | 
48 | wire [7:0] s0;
49 | wire [7:0] s1;
50 | wire [7:0] s2;
51 | wire [7:0] s3;
52 | wire [7:0] s4;
53 | wire [7:0] s5;
54 | wire [7:0] s6;
55 | wire [7:0] s7;
56 | wire [7:0] s8;
57 | 
58 | mul_stage1 st1(clk,reset,a0,a1,a2,a3,a4,b0,b1,b2,b3,b4,s0,s1,s2,s3,s4,s5,s6,s7,s8);
59 | 
60 | mul_stage2 st2(clk,reset,s0,s1,s2,s3,s4,s5,s6,s7,s8,c0,c1,c2,c3,c4);
61 | 
62 | endmodule
63 | 
64 | 
65 | 
66 | 
67 | 
68 | 
69 | 
70 | 
71 | 
72 | 


--------------------------------------------------------------------------------
/square.v:
--------------------------------------------------------------------------------
 1 | module square(clk,reset,
 2 | 	     a0,a1,a2,a3,a4,
 3 | 	     c0,c1,c2,c3,c4);
 4 | 
 5 | input clk;
 6 | input reset;
 7 | 
 8 | input [7:0] a0;
 9 | input [7:0] a1;
10 | input [7:0] a2;
11 | input [7:0] a3;
12 | input [7:0] a4;
13 | 
14 | 
15 | output [7:0] c0;
16 | output [7:0] c1;
17 | output [7:0] c2;
18 | output [7:0] c3;
19 | output [7:0] c4;
20 | 
21 | wire clk;
22 | wire reset;
23 | 
24 | wire [7:0] a0;
25 | wire [7:0] a1;
26 | wire [7:0] a2;
27 | wire [7:0] a3;
28 | wire [7:0] a4;
29 | 
30 | reg [7:0] c0;
31 | reg [7:0] c1;
32 | reg [7:0] c2;
33 | reg [7:0] c3;
34 | reg [7:0] c4;
35 | 
36 | 
37 | always@(posedge clk)
38 | 		begin
39 | 			if(reset == 1)
40 | 				begin
41 | 				   c0 <= 8'd0;
42 | 				   c1 <= 8'd0;
43 | 				   c2 <= 8'd0;
44 | 				   c3 <= 8'd0;
45 | 				   c4 <= 8'd0;
46 | 				end
47 | 		       else
48 | 				begin
49 | 				   c0 <= a0 + a4;
50 | 				   c1 <= a3;
51 | 				   c2 <= a1 + a4;
52 | 				   c3 <= a3 + a2;
53 | 				   c4 <= a2;
54 | 				end
55 | 	    end
56 | 
57 | endmodule
58 | 
59 | 
60 | 
61 | 
62 | 
63 | 
64 | 
65 | 
66 | 
67 | 


--------------------------------------------------------------------------------
/top_ecc.ucf:
--------------------------------------------------------------------------------
 1 | NET "clk" LOC = P57;
 2 | 
 3 | NET "reset" LOC = P29;
 4 | 
 5 | NET "data_out[7]" LOC = P7;
 6 | NET "data_out[6]" LOC = P8;
 7 | NET "data_out[5]" LOC = P10;
 8 | NET "data_out[4]" LOC = P11;
 9 | NET "data_out[3]" LOC = P12;
10 | NET "data_out[2]" LOC = P13;
11 | NET "data_out[1]" LOC = P15;
12 | NET "data_out[0]" LOC = P16;
13 | 
14 | NET "inst[2]" LOC = P18;
15 | NET "inst[1]" LOC = P19;
16 | NET "inst[0]" LOC = P20;
17 | NET "ctrl[2]" LOC = P21;
18 | NET "ctrl[1]" LOC = P23;
19 | NET "ctrl[0]" LOC = P24;
20 | NET "sel[1]" LOC = P27;
21 | NET "sel[0]" LOC = P28;
22 | 
23 | 
24 | 
25 | 


--------------------------------------------------------------------------------
/top_ecc.v:
--------------------------------------------------------------------------------
  1 | module top_ecc(clk,reset,inst,
  2 | 	   ctrl,sel,data_out);
  3 | 
  4 | 	   
  5 | 
  6 | input clk;
  7 | input reset;
  8 | input [2:0] inst;
  9 | input [2:0] ctrl;
 10 | input [1:0] sel;
 11 | 
 12 | output [7:0] data_out;
 13 | 
 14 | wire clk;
 15 | wire reset;
 16 | wire [2:0] inst;
 17 | wire [2:0] ctrl;
 18 | wire [1:0] sel;
 19 | wire [7:0] data_out;
 20 | wire [31:0] data_out1;
 21 | wire [31:0] data_in;
 22 | wire [7:0] a0;
 23 | wire [7:0] a1;
 24 | wire [7:0] a2;
 25 | wire [7:0] a3;
 26 | 
 27 | wire [7:0] b0;
 28 | wire [7:0] b1;
 29 | wire [7:0] b2;
 30 | wire [7:0] b3;
 31 | 
 32 | wire [7:0] c0;
 33 | wire [7:0] c1;
 34 | wire [7:0] c2;
 35 | wire [7:0] c3;
 36 | wire [7:0] c4;
 37 | 
 38 | reg [4:0] count;
 39 | reg [4:0] temp;
 40 | 
 41 | reg [7:0] a0_temp;
 42 | reg [7:0] a1_temp;
 43 | reg [7:0] a2_temp;
 44 | reg [7:0] a3_temp;
 45 | 
 46 | reg [7:0] b0_temp;
 47 | reg [7:0] b1_temp;
 48 | reg [7:0] b2_temp;
 49 | reg [7:0] b3_temp;
 50 | 
 51 | reg [7:0] x_in;
 52 | reg [7:0] y_in;
 53 | 
 54 | wire [7:0] x_out1;
 55 | wire [7:0] y_out1;
 56 | wire [7:0] x_out2;
 57 | wire [7:0] y_out2;
 58 | 
 59 | reg valid;
 60 | assign data_in = 32'h12345678;
 61 | assign a0 = a0_temp;
 62 | assign a1 = a1_temp;
 63 | assign a2 = a2_temp;
 64 | assign a3 = a3_temp;
 65 | 
 66 | assign b0 = b0_temp;
 67 | assign b1 = b1_temp;
 68 | assign b2 = b2_temp;
 69 | assign b3 = b3_temp;
 70 | 
 71 | control  ct1(clk,reset,ctrl,
 72 | 	   data_in,data_out1,
 73 | 	   x_in,y_in,
 74 | 	   x_out1,y_out1,
 75 | 	   x_out2,y_out2,
 76 |    	   s0,valid);
 77 | 
 78 | ecc      ct2(clk,reset,inst,
 79 |             a0,a1,a2,a3,8'd0,
 80 | 	    b0,b1,b2,b3,8'd0,
 81 | 	    c0,c1,c2,c3,c4);
 82 |  
 83 |  always@(posedge clk)
 84 | 	begin
 85 | 		if(reset)
 86 | 			count <= 0;
 87 | 		else if (count == 31)
 88 | 				count <= 31;
 89 | 			else 
 90 | 				count <= count + 1;
 91 | 	end   
 92 | 
 93 | always@(posedge clk)
 94 | begin
 95 | 	if(reset == 1)
 96 | 	begin
 97 | 		valid <= 0;
 98 | 		temp  <= 0;
 99 | 	end
100 | 	else if(s0 == 1 && temp == 0)
101 | 	begin
102 | 		a0_temp <= x_out1;
103 | 		b0_temp <= y_out1;
104 | 		a1_temp <= x_out2;
105 | 		b1_temp <= y_out2;
106 | 		temp    <= 1;
107 | 	end
108 | 	else if(s0 == 1 && temp == 1)
109 | 	begin
110 | 		a2_temp <= x_out1;
111 | 		b2_temp <= y_out1;
112 | 		a3_temp <= x_out2;
113 | 		b3_temp <= y_out2;
114 | 		temp    <= 0;
115 | 	end
116 | 	else if(count == 11 )
117 | 	begin
118 | 		valid <= 1;
119 | 		x_in  <= c0;
120 | 		y_in  <= c1;
121 | 	end
122 | 	else if(count == 12 )
123 | 	begin
124 | 		valid <= 1;
125 | 		x_in  <= c2;
126 | 		y_in  <= c3;
127 | 	end
128 | 	else
129 | 	begin
130 | 		valid <= 0;
131 | 	end
132 | end
133 | 
134 | assign data_out = ( sel == 2'b00 ) ? data_out1[7:0] :
135 | 			( sel == 2'b01 ) ? data_out1[15:8] :
136 | 			( sel == 2'b10 ) ? data_out1[23:16] :
137 | 			( sel == 2'b11 ) ? data_out1[31:24] : 8'd0;
138 | endmodule
139 | 
140 | 
141 | 
142 | 
143 | 
144 | 
145 | 
146 | 
147 | 
148 | 


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