├── INTEGRATION.md ├── LICENSE ├── README.md ├── dsketch ├── variant_1 │ └── dsketch.p4 └── variant_2 │ └── dsketch.p4 └── misc ├── cms └── cms.p4 ├── conquest └── conquest.p4 ├── fcm └── fcm.p4 └── precision ├── entries_better_32.p4inc └── precision.p4 /INTEGRATION.md: -------------------------------------------------------------------------------- 1 | # Integrating/ Using `dSketch` 2 | 3 | Here, we discuss the steps to integrate `dSketch` in to existing P4_16 programs for the Intel Tofino-based switches. 4 | We use the commodity programmable switch, `switch.p4` as the example in this case. The same applies for other programs. 5 | 6 | > Note: Due to confidentiality reasons, the program, `switch.p4` and it's derivatives are not publicly shared.. 7 | 8 | ## Overview 9 | We provide two functional equivalent variants of the `dSketch` module. One in in-line style while the other in match-action-table style. However, both of them have slight differences in terms of memory consumption with the latter requiring more memory to maintain the table entries. 10 | 11 | The `dSketch` module is wrapped in the form of a control block. It requires 5 parameters. 12 | ```c 13 | control DSketch ( 14 | inout switch_header_t hdr, 15 | in bit<8> ts, 16 | in bit<32> index, 17 | inout bit<32> flow_count, 18 | inout bit<9> egress_port 19 | ) 20 | { 21 | ... 22 | } 23 | ``` 24 | 25 | - `inout switch_header_t hdr` : headers used in the main program. 26 | - `in bit<8> ts` : sliced from the 48-bit timestamp. 27 | - `in bit<32> index` : output from hash functions. 28 | - `inout bit<32> flow_count` : metadata/ variable to store the flow count output from `dSketch` 29 | - `inout bit<9> egress_port` : egress port field for traffic manager 30 | 31 | ## Headers & Constants 32 | As we rely on (cloned) recirculated packets to update `dSketch` with the decayed counts, we require a special header to carry the necessary information (i.e., decayed counts). To ease the packet parsing process, we define a header formatted similarly as a VLAN which contains an ethernet type field to store the original ethernet type. 33 | 34 | Recirculated packets carrying the decay update header will be set with ethernet type `0xDECA`. 35 | The decay update header should be declared right after the ethernet header. 36 | 37 | ```c 38 | #define ETHERTYPE_DECAY_UPDATE 0xDECA 39 | 40 | header decay_update_h { 41 | bit<32> count_r0; 42 | bit<32> count_r1; 43 | bit<16> ether_type; 44 | } 45 | 46 | struct switch_header_t { 47 | ... 48 | ethernet_h ethernet; 49 | decay_update_h decay_update; 50 | ... 51 | } 52 | ``` 53 | 54 | ## Parsers 55 | To parse the (cloned and) recirculated packets, we look for the special ethernet type `0xDECA` when parsing the ethernet frame. This requires modifications to the existing parsers (see below). Then, we extract the information from the decay update header before continuing to parse the remaining headers as usual using the carried ethernet type in the header. 56 | 57 | ```c 58 | state parse_ethernet { 59 | pkt.extract(hdr.ethernet); 60 | transition select(hdr.ethernet.ether_type, ig_intr_md.ingress_port) { 61 | ... 62 | (ETHERTYPE_DECAY_UPDATE, _) : parse_decay_update; 63 | ... 64 | } 65 | } 66 | 67 | state parse_decay_update { 68 | pkt.extract(hdr.decay_update); 69 | transition select(hdr.decay_update.ether_type) { 70 | ... 71 | } 72 | } 73 | ``` 74 | 75 | ## Integrating `dSketch` 76 | To integrate `dSketch`, we include `dsketch.p4` into the main program. Then, we initialize an instance of `dSketch` in the Ingress control block before applying it in the `apply` block with the necessary parameters. 77 | This completes the integration. 78 | 79 | > Note: `dSketch` can only work in the Ingress control block. 80 | 81 | ```c 82 | #include "dsketch.p4" 83 | ... 84 | 85 | SwitchIngress(...) { 86 | ... 87 | DSketch() dsketch; 88 | ... 89 | 90 | apply { 91 | ... 92 | dsketch.apply( 93 | hdr, // switch headers 94 | ig_md.timestamp[40:33], // timestamp (from metadata) 95 | ig_md.hash[31:0], // hash (from metadata) 96 | ig_md.flow_count, // flow count (to write to metadata) 97 | ig_intr_md_for_tm.ucast_egress_port // egress port (for traffic manager) 98 | ); 99 | ... 100 | } 101 | } 102 | 103 | ``` 104 | 105 | ## Optimizations 106 | Instead of recirculating the original packet, in the paper, we recommend to clone the packet and then recirculate only the cloned packet to update the `dSketch` (which will subsequently then be dropped). 107 | 108 | To do this, you will need to replace the few lines of code in `dSketch` to set the `mirror_type` in place of setting the egress ports to the recirculation port. 109 | 110 | Then, you will need to specify the `mirror_type` used, as well as the ports belonging to the mirror `session` (in the following example, we use `mirror_type` 1 and `session` 123). 111 | ```c 112 | SwitchIngressDeparser (...) { 113 | apply { 114 | ... 115 | if(ig_dprsr_md.mirror_type == 1) { 116 | // session 123, where it points to the recirculation port 117 | mirror.emit< /*mirror header here*/ >(10w123, { /*mirror header fields*/ }); 118 | } 119 | ... 120 | } 121 | } 122 | ``` 123 | On top of that, you will have to manually invalidate the `decay_update` header in the *Egress control block* in order to restore the original packet structure before being forwarded out. 124 | 125 | > Note: There exists multiple ways to clone and recirculate, e.g., by defining custom mirror headers. 126 | By doing that, one does not need the `decay_update` header as long as the custom mirror headers can carry the information in `decay_update`. 127 | However, this is subjected to the number of `mirror_types` that are already in use. 128 | If fully utilized by other applications, then this method may not be feasible. 129 | More examples on mirroring can be found on Intel's Open-Tofino [repository](https://github.com/barefootnetworks/Open-Tofino). 130 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU AFFERO GENERAL PUBLIC LICENSE 2 | Version 3, 19 November 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU Affero General Public License is a free, copyleft license for 11 | software and other kinds of works, specifically designed to ensure 12 | cooperation with the community in the case of network server software. 13 | 14 | The licenses for most software and other practical works are designed 15 | to take away your freedom to share and change the works. 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It is safest 628 | to attach them to the start of each source file to most effectively 629 | state the exclusion of warranty; and each file should have at least 630 | the "copyright" line and a pointer to where the full notice is found. 631 | 632 | 633 | Copyright (C) 634 | 635 | This program is free software: you can redistribute it and/or modify 636 | it under the terms of the GNU Affero General Public License as published 637 | by the Free Software Foundation, either version 3 of the License, or 638 | (at your option) any later version. 639 | 640 | This program is distributed in the hope that it will be useful, 641 | but WITHOUT ANY WARRANTY; without even the implied warranty of 642 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 643 | GNU Affero General Public License for more details. 644 | 645 | You should have received a copy of the GNU Affero General Public License 646 | along with this program. If not, see . 647 | 648 | Also add information on how to contact you by electronic and paper mail. 649 | 650 | If your software can interact with users remotely through a computer 651 | network, you should also make sure that it provides a way for users to 652 | get its source. For example, if your program is a web application, its 653 | interface could display a "Source" link that leads users to an archive 654 | of the code. There are many ways you could offer source, and different 655 | solutions will be better for different programs; see section 13 for the 656 | specific requirements. 657 | 658 | You should also get your employer (if you work as a programmer) or school, 659 | if any, to sign a "copyright disclaimer" for the program, if necessary. 660 | For more information on this, and how to apply and follow the GNU AGPL, see 661 | . 662 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # dSketch 2 | 3 | This repository holds the implementation for the time-decaying in-network heavy-hitter detection algorithm, `dSketch`, proposed in the paper `Revisiting Heavy-Hitter Detection on Commodity Programmable Switches` accepted (and to be presented) at [IEEE NetSoft 2021](https://netsoft2021.ieee-netsoft.org/). 4 | 5 | You can find the paper [here](https://ieeexplore.ieee.org/document/9492531). 6 | 7 | ## Usage/ Integration 8 | Please see [INTEGRATION.md](INTEGRATION.md) for more detail. 9 | 10 | The implementation for `dSketch` can be found under the folder `dsketch/`. 11 | 12 | ## Miscellaneous 13 | The folder `misc/` holds the reference implementation for the other algorithms' evaluated in the paper. 14 | 15 | ## Citation 16 | 17 | If you find this work useful for your research, please cite: 18 | 19 | ``` 20 | @INPROCEEDINGS{9492531, 21 | author={Khooi, Xin Zhe and Csikor, Levente and Li, Jialin and Kang, Min Suk and Divakaran, Dinil Mon}, 22 | booktitle={2021 IEEE 7th International Conference on Network Softwarization (NetSoft)}, 23 | title={Revisiting Heavy-Hitter Detection on Commodity Programmable Switches}, 24 | year={2021}, 25 | volume={}, 26 | number={}, 27 | pages={79-87}, 28 | doi={10.1109/NetSoft51509.2021.9492531} 29 | } 30 | ``` 31 | 32 | ## Feedback/ Questions 33 | We welcome questions/ comments/ feedback. 34 | 35 | Please do not hesitate reach out the authors via email. 36 | 37 | ## License 38 | Copyright 2021 Xin Zhe Khooi, National University of Singapore. 39 | 40 | The project's source code are released here under the [GNU Affero General Public License v3](https://www.gnu.org/licenses/agpl-3.0.html). 41 | -------------------------------------------------------------------------------- /dsketch/variant_1/dsketch.p4: -------------------------------------------------------------------------------- 1 | /* 2 | dSketch: Time-Decaying Sketches 3 | 4 | Copyright (C) 2021 Xin Zhe Khooi, National University of Singapore 5 | 6 | This program is free software: you can redistribute it and/or modify 7 | it under the terms of the GNU Affero General Public License as published by 8 | the Free Software Foundation, either version 3 of the License, or 9 | (at your option) any later version. 10 | This program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU Affero General Public License for more details. 14 | You should have received a copy of the GNU Affero General Public License 15 | along with this program. If not, see . 16 | */ 17 | 18 | typedef bit<32> count_t; 19 | typedef bit<8> window_t; 20 | 21 | // Use packet length as the unit 22 | // #define INCREMENT ((bit<32>)hdr.ipv4.total_len) 23 | 24 | // Use packet counts as the unit 25 | #define INCREMENT 1 26 | #define SKETCH_CTR_PER_ROW 63356 27 | 28 | control DSketch ( 29 | inout switch_header_t hdr, 30 | in bit<8> ts, 31 | in bit<32> index, 32 | inout bit<32> flow_count, 33 | inout bit<9> egress_port 34 | ) 35 | { 36 | count_t count_r0 = 0; 37 | window_t diff_r0 = 0; 38 | count_t count_r1 = 0; 39 | window_t diff_r1 = 0; 40 | 41 | Register(SKETCH_CTR_PER_ROW) sketch0; 42 | Register(SKETCH_CTR_PER_ROW) window0; 43 | 44 | Register(SKETCH_CTR_PER_ROW) sketch1; 45 | Register(SKETCH_CTR_PER_ROW) window1; 46 | 47 | RegisterAction (sketch0) sketch0_count = { 48 | void apply(inout count_t val, out count_t rv) { 49 | val = val |+| INCREMENT; 50 | rv = val; 51 | } 52 | }; 53 | 54 | RegisterAction (sketch0) sketch0_decay = { 55 | void apply(inout count_t val, out count_t rv) { 56 | val = hdr.decay_update.count_r0; 57 | rv = val; 58 | } 59 | }; 60 | 61 | RegisterAction (window0) window0_update = { 62 | void apply(inout window_t val, out window_t rv) { 63 | val = ts; 64 | rv = 0; 65 | } 66 | }; 67 | 68 | RegisterAction (window0) window0_diff = { 69 | void apply(inout window_t val, out window_t rv) { 70 | rv = ts - val; 71 | } 72 | }; 73 | 74 | RegisterAction (sketch1) sketch1_count = { 75 | void apply(inout count_t val, out count_t rv) { 76 | val = val |+| INCREMENT; 77 | rv = val; 78 | } 79 | }; 80 | 81 | RegisterAction (sketch1) sketch1_decay = { 82 | void apply(inout count_t val, out count_t rv) { 83 | val = hdr.decay_update.count_r1; 84 | rv = val; 85 | } 86 | }; 87 | 88 | RegisterAction (window1) window1_update = { 89 | void apply(inout window_t val, out window_t rv) { 90 | val = ts; 91 | rv = 0; 92 | } 93 | }; 94 | 95 | RegisterAction (window1) window1_diff = { 96 | void apply(inout window_t val, out window_t rv) { 97 | rv = ts - val; 98 | } 99 | }; 100 | 101 | action update_sketch0() { 102 | count_r0 = sketch0_count.execute(index[31:16]); 103 | } 104 | 105 | action decay_sketch0() { 106 | count_r0 = sketch0_decay.execute(index[31:16]); 107 | } 108 | 109 | action update_sketch1() { 110 | count_r1 = sketch1_count.execute(index[15:0]); 111 | } 112 | 113 | action decay_sketch1() { 114 | count_r1 = sketch1_decay.execute(index[15:0]); 115 | } 116 | 117 | action diff_window0() { 118 | diff_r0 = window0_diff.execute(index[31:16]); 119 | } 120 | 121 | action update_window0() { 122 | diff_r0 = window0_update.execute(index[31:16]); 123 | } 124 | 125 | action diff_window1() { 126 | diff_r1 = window1_diff.execute(index[15:0]); 127 | } 128 | 129 | action update_window1() { 130 | diff_r1 = window1_update.execute(index[15:0]); 131 | } 132 | 133 | action zero0 (bit<9> recirc_port) { 134 | hdr.decay_update.setValid(); 135 | egress_port = recirc_port; 136 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 137 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 138 | hdr.decay_update.count_r0 = count_r0; 139 | } 140 | 141 | action shift0(bit<9> recirc_port) { 142 | hdr.decay_update.setValid(); 143 | egress_port = recirc_port; 144 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 145 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 146 | hdr.decay_update.count_r0 = count_r0 >> 1; 147 | } 148 | 149 | action zero1 (bit<9> recirc_port) { 150 | hdr.decay_update.setValid(); 151 | egress_port = recirc_port; 152 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 153 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 154 | hdr.decay_update.count_r1 = count_r1; 155 | } 156 | 157 | action shift1(bit<9> recirc_port) { 158 | hdr.decay_update.setValid(); 159 | egress_port = recirc_port; 160 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 161 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 162 | hdr.decay_update.count_r1 = count_r1 >> 1; 163 | } 164 | 165 | apply { 166 | if (!hdr.decay_update.isValid()) { 167 | update_sketch0(); 168 | update_sketch1(); 169 | diff_window0(); 170 | diff_window1(); 171 | } else { 172 | decay_sketch0(); 173 | decay_sketch1(); 174 | update_window0(); 175 | update_window1(); 176 | hdr.decay_update.setInvalid(); 177 | } 178 | 179 | flow_count = min(count_r1, count_r0); 180 | 181 | if (diff_r0 == 0) { 182 | NoAction(); 183 | } else if (diff_r0 == 1) { 184 | shift0(192); // specify your recirculation port 185 | } else { 186 | zero0(192); // specify your recirculation port 187 | } 188 | 189 | if (diff_r1 == 0) { 190 | NoAction(); 191 | } else if (diff_r1 == 1) { 192 | shift1(192); // specify your recirculation port 193 | } else { 194 | zero1(192); // specify your recirculation port 195 | } 196 | } 197 | } -------------------------------------------------------------------------------- /dsketch/variant_2/dsketch.p4: -------------------------------------------------------------------------------- 1 | /* 2 | dSketch: Time-Decaying Sketches 3 | 4 | Copyright (C) 2021 Xin Zhe Khooi, National University of Singapore 5 | 6 | This program is free software: you can redistribute it and/or modify 7 | it under the terms of the GNU Affero General Public License as published by 8 | the Free Software Foundation, either version 3 of the License, or 9 | (at your option) any later version. 10 | This program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU Affero General Public License for more details. 14 | You should have received a copy of the GNU Affero General Public License 15 | along with this program. If not, see . 16 | */ 17 | 18 | typedef bit<32> count_t; 19 | typedef bit<8> window_t; 20 | 21 | // Use packet length as the unit 22 | // #define INCREMENT ((bit<32>)hdr.ipv4.total_len) 23 | 24 | // Use packet counts as the unit 25 | #define INCREMENT 1 26 | #define SKETCH_CTR_PER_ROW 65536 27 | 28 | control DSketch ( 29 | inout switch_header_t hdr, 30 | in bit<8> ts, 31 | in bit<32> index, 32 | inout bit<32> flow_count, 33 | inout bit<9> egress_port 34 | ) 35 | { 36 | count_t count_r0 = 0; 37 | window_t diff_r0 = 0; 38 | count_t count_r1 = 0; 39 | window_t diff_r1 = 0; 40 | 41 | Register(SKETCH_CTR_PER_ROW) sketch0; 42 | Register(SKETCH_CTR_PER_ROW) window0; 43 | 44 | Register(SKETCH_CTR_PER_ROW) sketch1; 45 | Register(SKETCH_CTR_PER_ROW) window1; 46 | 47 | RegisterAction (sketch0) sketch0_count = { 48 | void apply(inout count_t val, out count_t rv) { 49 | val = val |+| INCREMENT; 50 | rv = val; 51 | } 52 | }; 53 | 54 | RegisterAction (sketch0) sketch0_decay = { 55 | void apply(inout count_t val, out count_t rv) { 56 | val = hdr.decay_update.count_r0; 57 | rv = val; 58 | } 59 | }; 60 | 61 | RegisterAction (window0) window0_update = { 62 | void apply(inout window_t val, out window_t rv) { 63 | val = ts; 64 | rv = 0; 65 | } 66 | }; 67 | 68 | RegisterAction (window0) window0_diff = { 69 | void apply(inout window_t val, out window_t rv) { 70 | rv = ts - val; 71 | } 72 | }; 73 | 74 | RegisterAction (sketch1) sketch1_count = { 75 | void apply(inout count_t val, out count_t rv) { 76 | val = val |+| INCREMENT; 77 | rv = val; 78 | } 79 | }; 80 | 81 | RegisterAction (sketch1) sketch1_decay = { 82 | void apply(inout count_t val, out count_t rv) { 83 | val = hdr.decay_update.count_r1; 84 | rv = val; 85 | } 86 | }; 87 | 88 | RegisterAction (window1) window1_update = { 89 | void apply(inout window_t val, out window_t rv) { 90 | val = ts; 91 | rv = 0; 92 | } 93 | }; 94 | 95 | RegisterAction (window1) window1_diff = { 96 | void apply(inout window_t val, out window_t rv) { 97 | rv = ts - val; 98 | } 99 | }; 100 | 101 | action update_sketch0() { 102 | count_r0 = sketch0_count.execute(index[31:16]); 103 | } 104 | 105 | action decay_sketch0() { 106 | hdr.decay_update.setInvalid(); 107 | count_r0 = sketch0_decay.execute(index[31:16]); 108 | } 109 | 110 | action update_sketch1() { 111 | count_r1 = sketch1_count.execute(index[15:0]); 112 | } 113 | 114 | action decay_sketch1() { 115 | hdr.decay_update.setInvalid(); 116 | count_r1 = sketch1_decay.execute(index[15:0]); 117 | } 118 | 119 | action diff_window0() { 120 | diff_r0 = window0_diff.execute(index[31:16]); 121 | } 122 | 123 | action update_window0() { 124 | diff_r0 = window0_update.execute(index[31:16]); 125 | } 126 | 127 | action diff_window1() { 128 | diff_r1 = window1_diff.execute(index[15:0]); 129 | } 130 | 131 | action update_window1() { 132 | diff_r1 = window1_update.execute(index[15:0]); 133 | } 134 | 135 | action zero0 (bit<9> recirc_port) { 136 | hdr.decay_update.setValid(); 137 | egress_port = recirc_port; 138 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 139 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 140 | hdr.decay_update.count_r0 = count_r0; 141 | } 142 | 143 | action shift0(bit<9> recirc_port) { 144 | hdr.decay_update.setValid(); 145 | egress_port = recirc_port; 146 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 147 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 148 | hdr.decay_update.count_r0 = count_r0 >> 1; 149 | } 150 | 151 | action zero1 (bit<9> recirc_port) { 152 | hdr.decay_update.setValid(); 153 | egress_port = recirc_port; 154 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 155 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 156 | hdr.decay_update.count_r1 = count_r1; 157 | } 158 | 159 | action shift1(bit<9> recirc_port) { 160 | hdr.decay_update.setValid(); 161 | egress_port = recirc_port; 162 | hdr.ethernet.ether_type = ETHERTYPE_DECAY_UPDATE; 163 | hdr.decay_update.ether_type = ETHERTYPE_IPV4; 164 | hdr.decay_update.count_r1 = count_r1 >> 1; 165 | } 166 | 167 | table sketch00 { 168 | key = { 169 | hdr.decay_update.isValid() : exact; 170 | } 171 | actions = { 172 | update_sketch0; 173 | decay_sketch0; 174 | } 175 | const entries = { 176 | false : update_sketch0(); 177 | true : decay_sketch0(); 178 | } 179 | } 180 | 181 | table sketch11 { 182 | key = { 183 | hdr.decay_update.isValid() : exact; 184 | } 185 | actions = { 186 | update_sketch1; 187 | decay_sketch1; 188 | } 189 | const entries = { 190 | false : update_sketch1(); 191 | true : decay_sketch1(); 192 | } 193 | } 194 | 195 | table window00 { 196 | key = { 197 | hdr.decay_update.isValid() : exact; 198 | } 199 | actions = { 200 | diff_window0; 201 | update_window0; 202 | } 203 | const entries = { 204 | false : diff_window0(); 205 | true : update_window0(); 206 | } 207 | } 208 | 209 | table window11 { 210 | key = { 211 | hdr.decay_update.isValid() : exact; 212 | } 213 | actions = { 214 | diff_window1; 215 | update_window1; 216 | } 217 | const entries = { 218 | false : diff_window1(); 219 | true : update_window1(); 220 | } 221 | } 222 | 223 | table decay0 { 224 | key = { 225 | diff_r0 : exact; 226 | } 227 | actions = { 228 | zero0; 229 | shift0; 230 | NoAction; 231 | } 232 | // specify your recirculation port 233 | // const entries = { 234 | // 0 : NoAction(); 235 | // 1 : shift0(192); 236 | // } 237 | // default_action = zero0(192); 238 | } 239 | 240 | table decay1 { 241 | key = { 242 | diff_r1 : exact; 243 | } 244 | actions = { 245 | zero1; 246 | shift1; 247 | NoAction; 248 | } 249 | // specify your recirculation port 250 | // const entries = { 251 | // 0 : NoAction(); 252 | // 1 : shift1(192); 253 | // } 254 | // default_action = zero1(192); 255 | } 256 | 257 | apply { 258 | sketch00.apply(); 259 | sketch11.apply(); 260 | window00.apply(); 261 | window11.apply(); 262 | flow_count = min(count_r1, count_r0); 263 | decay0.apply(); 264 | decay1.apply(); 265 | } 266 | } -------------------------------------------------------------------------------- /misc/cms/cms.p4: -------------------------------------------------------------------------------- 1 | /* -*- P4_16 -*- */ 2 | 3 | #include 4 | #include 5 | 6 | /************************************************************************* 7 | ************* C O N S T A N T S A N D T Y P E S ******************* 8 | **************************************************************************/ 9 | typedef bit<48> mac_addr_t; 10 | typedef bit<32> ipv4_addr_t; 11 | typedef bit<16> l4_port_t; 12 | 13 | typedef bit<16> ether_type_t; 14 | const ether_type_t ETHERTYPE_IPV4 = 16w0x0800; 15 | const ether_type_t ETHERTYPE_ARP = 16w0x0806; 16 | const ether_type_t ETHERTYPE_DECAY_UPDATE = 16w0x8888; 17 | 18 | typedef bit<8> ip_proto_t; 19 | const ip_proto_t IP_PROTO_ICMP = 1; 20 | const ip_proto_t IP_PROTO_TCP = 6; 21 | const ip_proto_t IP_PROTO_UDP = 17; 22 | 23 | typedef bit<32> count_t; 24 | 25 | const bit<3> HH_DIGEST = 0x03; 26 | struct hh_digest_t { 27 | ipv4_addr_t src_addr; 28 | ipv4_addr_t dst_addr; 29 | bit<8> protocol; 30 | l4_port_t src_port; 31 | l4_port_t dst_port; 32 | } 33 | 34 | /************************************************************************* 35 | *********************** H E A D E R S ********************************* 36 | *************************************************************************/ 37 | 38 | /* Define all the headers the program will recognize */ 39 | /* The actual sets of headers processed by each gress can differ */ 40 | 41 | /* Standard ethernet header */ 42 | header ethernet_h { 43 | mac_addr_t dst_addr; 44 | mac_addr_t src_addr; 45 | ether_type_t ether_type; 46 | } 47 | 48 | header ipv4_h { 49 | bit<4> version; 50 | bit<4> ihl; 51 | bit<8> diffserv; 52 | bit<16> total_len; 53 | bit<16> identification; 54 | bit<3> flags; 55 | bit<13> frag_offset; 56 | bit<8> ttl; 57 | ip_proto_t protocol; 58 | bit<16> hdr_checksum; 59 | ipv4_addr_t src_addr; 60 | ipv4_addr_t dst_addr; 61 | } 62 | 63 | header icmp_h { 64 | bit<8> type_; 65 | bit<8> code; 66 | bit<16> hdr_checksum; 67 | } 68 | 69 | header tcp_h { 70 | l4_port_t src_port; 71 | l4_port_t dst_port; 72 | bit<32> seq_no; 73 | bit<32> ack_no; 74 | bit<4> data_offset; 75 | bit<4> res; 76 | bit<8> flag; 77 | bit<16> window; 78 | bit<16> checksum; 79 | bit<16> urgent_ptr; 80 | } 81 | 82 | header udp_h { 83 | l4_port_t src_port; 84 | l4_port_t dst_port; 85 | bit<16> hdr_length; 86 | bit<16> checksum; 87 | } 88 | 89 | 90 | /************************************************************************* 91 | ************** I N G R E S S P R O C E S S I N G ******************* 92 | *************************************************************************/ 93 | 94 | /*********************** H E A D E R S ************************/ 95 | 96 | struct my_ingress_headers_t { 97 | ethernet_h ethernet; 98 | ipv4_h ipv4; 99 | tcp_h tcp; 100 | udp_h udp; 101 | } 102 | 103 | /****** G L O B A L I N G R E S S M E T A D A T A *********/ 104 | 105 | struct my_ingress_metadata_t { 106 | l4_port_t src_port; 107 | l4_port_t dst_port; 108 | } 109 | 110 | /*********************** P A R S E R **************************/ 111 | parser IngressParser(packet_in pkt, 112 | /* User */ 113 | out my_ingress_headers_t hdr, 114 | out my_ingress_metadata_t meta, 115 | /* Intrinsic */ 116 | out ingress_intrinsic_metadata_t ig_intr_md) 117 | { 118 | /* This is a mandatory state, required by Tofino Architecture */ 119 | state start { 120 | pkt.extract(ig_intr_md); 121 | pkt.advance(PORT_METADATA_SIZE); 122 | transition parse_ethernet; 123 | } 124 | 125 | state parse_ethernet { 126 | pkt.extract(hdr.ethernet); 127 | transition select(hdr.ethernet.ether_type) { 128 | ETHERTYPE_IPV4 : parse_ipv4; 129 | } 130 | } 131 | 132 | state parse_ipv4 { 133 | pkt.extract(hdr.ipv4); 134 | meta.src_port = 0; 135 | meta.dst_port = 0; 136 | transition select(hdr.ipv4.protocol) { 137 | IP_PROTO_TCP : parse_tcp; 138 | IP_PROTO_UDP : parse_udp; 139 | default : accept; 140 | } 141 | } 142 | 143 | state parse_tcp { 144 | pkt.extract(hdr.tcp); 145 | meta.src_port = hdr.tcp.src_port; 146 | meta.dst_port = hdr.tcp.dst_port; 147 | transition accept; 148 | } 149 | 150 | state parse_udp { 151 | pkt.extract(hdr.udp); 152 | meta.src_port = hdr.udp.src_port; 153 | meta.dst_port = hdr.udp.dst_port; 154 | transition accept; 155 | } 156 | } 157 | 158 | /***************** M A T C H - A C T I O N *********************/ 159 | 160 | control Ingress( 161 | /* User */ 162 | inout my_ingress_headers_t hdr, 163 | inout my_ingress_metadata_t meta, 164 | /* Intrinsic */ 165 | in ingress_intrinsic_metadata_t ig_intr_md, 166 | in ingress_intrinsic_metadata_from_parser_t ig_prsr_md, 167 | inout ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md, 168 | inout ingress_intrinsic_metadata_for_tm_t ig_tm_md) 169 | { 170 | bit<16> index0 = 0; 171 | bit<16> index1 = 0; 172 | count_t count_r0 = 0; 173 | count_t count_r1 = 0; 174 | 175 | count_t count0 = 0; 176 | count_t count1 = 0; 177 | bit<32> min_count = 0; 178 | 179 | Hash>(HashAlgorithm_t.CRC32) hash_index0; 180 | Hash>(HashAlgorithm_t.CRC16) hash_index1; 181 | 182 | Register(65536) sketch0; 183 | Register(65536) sketch1; 184 | 185 | RegisterAction (sketch0) sketch0_count = { 186 | void apply(inout count_t val, out count_t rv) { 187 | val = val |+| 1; 188 | rv = val; 189 | } 190 | }; 191 | 192 | RegisterAction (sketch1) sketch1_count = { 193 | void apply(inout count_t val, out count_t rv) { 194 | val = val |+| 1; 195 | rv = val; 196 | } 197 | }; 198 | 199 | action drop() { 200 | ig_dprsr_md.drop_ctl = 0x0; // drop packet 201 | exit; 202 | } 203 | 204 | action forward(PortId_t port) { 205 | ig_tm_md.ucast_egress_port = port; 206 | } 207 | 208 | table ipv4_forward { 209 | key = { 210 | ig_intr_md.ingress_port : exact; 211 | } 212 | actions = { 213 | forward; 214 | NoAction; 215 | } 216 | default_action = NoAction(); 217 | } 218 | 219 | action generate_digest() { 220 | ig_dprsr_md.digest_type = HH_DIGEST; 221 | } 222 | 223 | table threshold { 224 | key = { 225 | // TODO: this needs to be slightly readjusted 226 | min_count[19:0] : range; 227 | } 228 | actions = { 229 | generate_digest; 230 | NoAction; 231 | } 232 | default_action = NoAction(); 233 | size = 1; 234 | } 235 | 236 | apply { 237 | ipv4_forward.apply(); 238 | index0 = hash_index0.get( 239 | { 240 | hdr.ipv4.src_addr, 241 | hdr.ipv4.dst_addr, 242 | hdr.ipv4.protocol, 243 | meta.src_port, 244 | meta.dst_port 245 | } 246 | ); 247 | index1 = hash_index1.get( 248 | { 249 | hdr.ipv4.src_addr, 250 | hdr.ipv4.dst_addr, 251 | hdr.ipv4.protocol, 252 | meta.src_port, 253 | meta.dst_port 254 | } 255 | ); 256 | 257 | count0 = sketch0_count.execute(index0); 258 | count1 = sketch1_count.execute(index1); 259 | min_count = min(count0, count1); 260 | 261 | threshold.apply(); 262 | 263 | // we do not need egress processing for now 264 | ig_tm_md.bypass_egress = 1; 265 | } 266 | } 267 | 268 | /********************* D E P A R S E R ************************/ 269 | 270 | control IngressDeparser(packet_out pkt, 271 | /* User */ 272 | inout my_ingress_headers_t hdr, 273 | in my_ingress_metadata_t meta, 274 | /* Intrinsic */ 275 | in ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md) 276 | { 277 | Digest () hh_digest; 278 | 279 | apply { 280 | if(ig_dprsr_md.digest_type == HH_DIGEST) { 281 | hh_digest.pack({hdr.ipv4.src_addr, hdr.ipv4.dst_addr, hdr.ipv4.protocol, meta.src_port, meta.dst_port}); 282 | } 283 | 284 | pkt.emit(hdr); 285 | } 286 | } 287 | 288 | 289 | /************************************************************************* 290 | **************** E G R E S S P R O C E S S I N G ******************* 291 | *************************************************************************/ 292 | 293 | /*********************** H E A D E R S ************************/ 294 | 295 | struct my_egress_headers_t { 296 | } 297 | 298 | /******** G L O B A L E G R E S S M E T A D A T A *********/ 299 | 300 | struct my_egress_metadata_t { 301 | } 302 | 303 | /*********************** P A R S E R **************************/ 304 | 305 | parser EgressParser(packet_in pkt, 306 | /* User */ 307 | out my_egress_headers_t hdr, 308 | out my_egress_metadata_t meta, 309 | /* Intrinsic */ 310 | out egress_intrinsic_metadata_t eg_intr_md) 311 | { 312 | /* This is a mandatory state, required by Tofino Architecture */ 313 | state start { 314 | pkt.extract(eg_intr_md); 315 | transition accept; 316 | } 317 | } 318 | 319 | /***************** M A T C H - A C T I O N *********************/ 320 | 321 | control Egress( 322 | /* User */ 323 | inout my_egress_headers_t hdr, 324 | inout my_egress_metadata_t meta, 325 | /* Intrinsic */ 326 | in egress_intrinsic_metadata_t eg_intr_md, 327 | in egress_intrinsic_metadata_from_parser_t eg_prsr_md, 328 | inout egress_intrinsic_metadata_for_deparser_t eg_dprsr_md, 329 | inout egress_intrinsic_metadata_for_output_port_t eg_oport_md) 330 | { 331 | apply { 332 | } 333 | } 334 | 335 | /********************* D E P A R S E R ************************/ 336 | 337 | control EgressDeparser(packet_out pkt, 338 | /* User */ 339 | inout my_egress_headers_t hdr, 340 | in my_egress_metadata_t meta, 341 | /* Intrinsic */ 342 | in egress_intrinsic_metadata_for_deparser_t eg_dprsr_md) 343 | { 344 | apply { 345 | pkt.emit(hdr); 346 | } 347 | } 348 | 349 | 350 | /************ F I N A L P A C K A G E ******************************/ 351 | Pipeline( 352 | IngressParser(), 353 | Ingress(), 354 | IngressDeparser(), 355 | EgressParser(), 356 | Egress(), 357 | EgressDeparser() 358 | ) pipe; 359 | 360 | Switch(pipe) main; 361 | -------------------------------------------------------------------------------- /misc/conquest/conquest.p4: -------------------------------------------------------------------------------- 1 | // vim: syntax=P4 2 | /* 3 | ConQuest: Fine-Grained Queue Measurement in the Data Plane 4 | 5 | Copyright (C) 2020 Xiaoqi Chen, Princeton University 6 | xiaoqic [at] cs.princeton.edu / https://doi.org/10.1145/3359989.3365408 7 | 8 | This program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU Affero General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU Affero General Public License for more details. 16 | You should have received a copy of the GNU Affero General Public License 17 | along with this program. If not, see . 18 | */ 19 | 20 | /* 21 | Retrieved, and adapted from: https://github.com/Princeton-Cabernet/p4-projects 22 | 23 | Note: 24 | - cleaning is done on the corresponding sketch instance using the control plane whenever the epoch advances. 25 | */ 26 | 27 | #define SKETCH_INC ((bit<32>) hdr.ipv4.total_len) 28 | 29 | //== Preamble: constants, headers 30 | #include 31 | #include 32 | 33 | const bit<32> SKETCH_SIZE = 16384; 34 | typedef bit<14> hash_index_t; 35 | 36 | typedef bit<48> mac_addr_t; 37 | typedef bit<32> ipv4_addr_t; 38 | typedef bit<16> ether_type_t; 39 | const ether_type_t ETHERTYPE_IPV4 = 16w0x0800; 40 | const ether_type_t ETHERTYPE_VLAN = 16w0x0810; 41 | 42 | typedef bit<8> ip_proto_t; 43 | const ip_proto_t IP_PROTO_ICMP = 1; 44 | const ip_proto_t IP_PROTO_TCP = 6; 45 | const ip_proto_t IP_PROTO_UDP = 17; 46 | 47 | 48 | header ethernet_h { 49 | mac_addr_t dst_addr; 50 | mac_addr_t src_addr; 51 | bit<16> ether_type; 52 | } 53 | 54 | header ipv4_h { 55 | bit<4> version; 56 | bit<4> ihl; 57 | bit<6> diffserv; 58 | bit<2> ecn; 59 | bit<16> total_len; 60 | bit<16> identification; 61 | bit<3> flags; 62 | bit<13> frag_offset; 63 | bit<8> ttl; 64 | bit<8> protocol; 65 | bit<16> hdr_checksum; 66 | ipv4_addr_t src_addr; 67 | ipv4_addr_t dst_addr; 68 | } 69 | 70 | header tcp_h { 71 | bit<16> src_port; 72 | bit<16> dst_port; 73 | 74 | bit<32> seq_no; 75 | bit<32> ack_no; 76 | bit<4> data_offset; 77 | bit<4> res; 78 | bit<8> flags; 79 | bit<16> window; 80 | bit<16> checksum; 81 | bit<16> urgent_ptr; 82 | } 83 | 84 | header udp_h { 85 | bit<16> src_port; 86 | bit<16> dst_port; 87 | bit<16> hdr_lenght; 88 | bit<16> checksum; 89 | } 90 | 91 | struct header_t { 92 | ethernet_h ethernet; 93 | ipv4_h ipv4; 94 | tcp_h tcp; 95 | udp_h udp; 96 | } 97 | 98 | struct paired_32bit { 99 | bit<32> hi; 100 | bit<32> lo; 101 | } 102 | 103 | 104 | //== Metadata definition 105 | struct ig_metadata_t { 106 | bit<16> src_port; 107 | bit<16> dst_port; 108 | 109 | bit<2> snap_epoch; 110 | 111 | hash_index_t hashed_index_row_0; 112 | hash_index_t hashed_index_row_1; 113 | 114 | hash_index_t snap_0_row_0_index; 115 | bit<32> snap_0_row_0_read; 116 | hash_index_t snap_0_row_1_index; 117 | bit<32> snap_0_row_1_read; 118 | hash_index_t snap_1_row_0_index; 119 | bit<32> snap_1_row_0_read; 120 | hash_index_t snap_1_row_1_index; 121 | bit<32> snap_1_row_1_read; 122 | hash_index_t snap_2_row_0_index; 123 | bit<32> snap_2_row_0_read; 124 | hash_index_t snap_2_row_1_index; 125 | bit<32> snap_2_row_1_read; 126 | hash_index_t snap_3_row_0_index; 127 | bit<32> snap_3_row_0_read; 128 | hash_index_t snap_3_row_1_index; 129 | bit<32> snap_3_row_1_read; 130 | 131 | bit<32> snap_0_read_min_l0; 132 | bit<32> snap_1_read_min_l0; 133 | bit<32> snap_2_read_min_l0; 134 | bit<32> snap_3_read_min_l0; 135 | 136 | bit<32> snap_0_read_min_l1; 137 | bit<32> snap_2_read_min_l1; 138 | bit<32> snap_0_read_min_l2; 139 | 140 | bit<14> cyclic_index; 141 | } 142 | 143 | struct eg_metadata_t { 144 | 145 | } 146 | 147 | parser SwitchIngressParser( 148 | packet_in pkt, 149 | out header_t hdr, 150 | out ig_metadata_t ig_md, 151 | out ingress_intrinsic_metadata_t ig_intr_md) { 152 | 153 | state start { 154 | pkt.extract(ig_intr_md); 155 | pkt.advance(PORT_METADATA_SIZE); 156 | transition parse_ethernet; 157 | } 158 | 159 | state parse_ethernet { 160 | pkt.extract(hdr.ethernet); 161 | transition select(hdr.ethernet.ether_type) { 162 | ETHERTYPE_IPV4 : parse_ipv4; 163 | } 164 | } 165 | 166 | state parse_ipv4 { 167 | pkt.extract(hdr.ipv4); 168 | ig_md.src_port = 0; 169 | ig_md.dst_port = 0; 170 | transition select(hdr.ipv4.protocol) { 171 | IP_PROTO_TCP : parse_tcp; 172 | IP_PROTO_UDP : parse_udp; 173 | default : accept; 174 | } 175 | } 176 | 177 | state parse_tcp { 178 | pkt.extract(hdr.tcp); 179 | ig_md.src_port = hdr.tcp.src_port; 180 | ig_md.dst_port = hdr.tcp.dst_port; 181 | transition accept; 182 | } 183 | 184 | state parse_udp { 185 | pkt.extract(hdr.udp); 186 | ig_md.src_port = hdr.udp.src_port; 187 | ig_md.dst_port = hdr.udp.dst_port; 188 | transition accept; 189 | } 190 | } 191 | 192 | control SwitchIngressDeparser( 193 | packet_out pkt, 194 | inout header_t hdr, 195 | in ig_metadata_t ig_md, 196 | in ingress_intrinsic_metadata_for_deparser_t ig_intr_dprsr_md) { 197 | apply { 198 | pkt.emit(hdr); 199 | } 200 | } 201 | 202 | parser SwitchEgressParser( 203 | packet_in pkt, 204 | out header_t hdr, 205 | out eg_metadata_t eg_md, 206 | out egress_intrinsic_metadata_t eg_intr_md) { 207 | 208 | state start { 209 | pkt.extract(eg_intr_md); 210 | transition accept; 211 | } 212 | } 213 | 214 | control SwitchEgressDeparser( 215 | packet_out pkt, 216 | inout header_t hdr, 217 | in eg_metadata_t eg_md, 218 | in egress_intrinsic_metadata_for_deparser_t eg_intr_md_for_dprsr) { 219 | apply { 220 | pkt.emit(hdr); 221 | } 222 | } 223 | 224 | 225 | //== Control logic 226 | control SwitchIngress( 227 | inout header_t hdr, 228 | inout ig_metadata_t ig_md, 229 | in ingress_intrinsic_metadata_t ig_intr_md, 230 | in ingress_intrinsic_metadata_from_parser_t ig_intr_prsr_md, 231 | inout ingress_intrinsic_metadata_for_deparser_t ig_intr_dprsr_md, 232 | inout ingress_intrinsic_metadata_for_tm_t ig_intr_tm_md) { 233 | 234 | Hash>(HashAlgorithm_t.CRC32) hash_index; 235 | // Hash>(HashAlgorithm_t.CRC32) hash_0_TCP; 236 | // Hash>(HashAlgorithm_t.CRC32) hash_0_UDP; 237 | // Hash>(HashAlgorithm_t.CRC32) hash_0_Other; 238 | // Hash>(HashAlgorithm_t.CRC32) hash_1_TCP; 239 | // Hash>(HashAlgorithm_t.CRC32) hash_1_UDP; 240 | // Hash>(HashAlgorithm_t.CRC32) hash_1_Other; 241 | 242 | // action calc_hashed_index_TCP(){ 243 | // ig_md.hashed_index_row_0 = hash_0_TCP.get({ 244 | // 6w27, hdr.ipv4.src_addr, 245 | // 5w8, hdr.ipv4.dst_addr, 246 | // 4w8, hdr.tcp.src_port, 247 | // 6w6, hdr.tcp.dst_port 248 | // }); 249 | // ig_md.hashed_index_row_1 = hash_1_TCP.get({ 250 | // 4w2, hdr.ipv4.src_addr, 251 | // 4w13, hdr.ipv4.dst_addr, 252 | // 3w1, hdr.tcp.src_port, 253 | // 4w3, hdr.tcp.dst_port 254 | // }); 255 | // } 256 | // action calc_hashed_index_UDP(){ 257 | // ig_md.hashed_index_row_0 = hash_0_UDP.get({ 258 | // 5w20, hdr.ipv4.src_addr, 259 | // 4w2, hdr.ipv4.dst_addr, 260 | // 6w28, hdr.udp.src_port, 261 | // 5w19, hdr.udp.dst_port 262 | // }); 263 | // ig_md.hashed_index_row_1 = hash_1_UDP.get({ 264 | // 5w11, hdr.ipv4.src_addr, 265 | // 5w3, hdr.ipv4.dst_addr, 266 | // 3w2, hdr.udp.src_port, 267 | // 3w2, hdr.udp.dst_port 268 | // }); 269 | // } 270 | // action calc_hashed_index_Other(){ 271 | // ig_md.hashed_index_row_0 = hash_0_Other.get({ 272 | // 3w0, hdr.ipv4.src_addr, 273 | // 3w3, hdr.ipv4.dst_addr, 274 | // 4w2, hdr.ipv4.protocol 275 | // }); 276 | // ig_md.hashed_index_row_1 = hash_1_Other.get({ 277 | // 4w0, hdr.ipv4.src_addr, 278 | // 5w6, hdr.ipv4.dst_addr, 279 | // 3w7, hdr.ipv4.protocol 280 | // }); 281 | // } 282 | 283 | action prep_reads(){ 284 | ig_md.snap_0_row_0_read=0; 285 | ig_md.snap_0_row_1_read=0; 286 | ig_md.snap_1_row_0_read=0; 287 | ig_md.snap_1_row_1_read=0; 288 | ig_md.snap_2_row_0_read=0; 289 | ig_md.snap_2_row_1_read=0; 290 | ig_md.snap_3_row_0_read=0; 291 | ig_md.snap_3_row_1_read=0; 292 | } 293 | 294 | action drop() { 295 | ig_intr_dprsr_md.drop_ctl = 0x1; 296 | exit; 297 | } 298 | 299 | //== Prepare register access index options 300 | Register,_>(1) reg_cleaning_index; 301 | RegisterAction, _, bit<32>>(reg_cleaning_index) reg_cleaning_index_rw = { 302 | void apply(inout bit<32> val, out bit<32> rv) { 303 | rv = val; 304 | val = val + 1; 305 | } 306 | }; 307 | action calc_cyclic_index(){ 308 | ig_md.cyclic_index = (bit<14>) reg_cleaning_index_rw.execute(0); 309 | } 310 | 311 | // SNAPSHOT 0 312 | action snap_0_select_index_hash(){ 313 | // READ or WRITE 314 | ig_md.snap_0_row_0_index=ig_md.hashed_index_row_0; 315 | ig_md.snap_0_row_1_index=ig_md.hashed_index_row_1; 316 | } 317 | action snap_0_select_index_cyclic(){ 318 | // CLEAN 319 | ig_md.snap_0_row_0_index=ig_md.cyclic_index; 320 | ig_md.snap_0_row_1_index=ig_md.cyclic_index; 321 | } 322 | table tb_snap_0_select_index { 323 | key = { 324 | ig_md.snap_epoch: exact; 325 | } 326 | actions = { 327 | snap_0_select_index_hash; 328 | snap_0_select_index_cyclic; 329 | } 330 | // size = 2; 331 | default_action = snap_0_select_index_hash(); 332 | const entries = { 333 | 1 : snap_0_select_index_cyclic(); // CLEAN 334 | } 335 | } 336 | // SNAPSHOT 1 337 | action snap_1_select_index_hash(){ 338 | // READ or WRITE 339 | ig_md.snap_1_row_0_index=ig_md.hashed_index_row_0; 340 | ig_md.snap_1_row_1_index=ig_md.hashed_index_row_1; 341 | } 342 | action snap_1_select_index_cyclic(){ 343 | // CLEAN 344 | } 345 | table tb_snap_1_select_index { 346 | key = { 347 | ig_md.snap_epoch: exact; 348 | } 349 | actions = { 350 | snap_1_select_index_hash; 351 | snap_1_select_index_cyclic; 352 | } 353 | // size = 2; 354 | default_action = snap_1_select_index_hash(); 355 | const entries = { 356 | 2 : snap_1_select_index_cyclic(); // CLEAN 357 | } 358 | } 359 | // SNAPSHOT 2 360 | action snap_2_select_index_hash(){ 361 | // READ or WRITE 362 | ig_md.snap_2_row_0_index=ig_md.hashed_index_row_0; 363 | ig_md.snap_2_row_1_index=ig_md.hashed_index_row_1; 364 | } 365 | action snap_2_select_index_cyclic(){ 366 | // CLEAN 367 | ig_md.snap_2_row_0_index=ig_md.cyclic_index; 368 | ig_md.snap_2_row_1_index=ig_md.cyclic_index; 369 | } 370 | table tb_snap_2_select_index { 371 | key = { 372 | ig_md.snap_epoch: exact; 373 | } 374 | actions = { 375 | snap_2_select_index_hash; 376 | snap_2_select_index_cyclic; 377 | } 378 | size = 2; 379 | default_action = snap_2_select_index_hash(); 380 | const entries = { 381 | 3 : snap_2_select_index_cyclic(); // CLEAN 382 | } 383 | } 384 | // SNAPSHOT 3 385 | action snap_3_select_index_hash(){ 386 | // READ or WRITE 387 | ig_md.snap_3_row_0_index=ig_md.hashed_index_row_0; 388 | ig_md.snap_3_row_1_index=ig_md.hashed_index_row_1; 389 | } 390 | action snap_3_select_index_cyclic(){ 391 | // CLEAN 392 | ig_md.snap_3_row_0_index=ig_md.cyclic_index; 393 | ig_md.snap_3_row_1_index=ig_md.cyclic_index; 394 | } 395 | table tb_snap_3_select_index { 396 | key = { 397 | ig_md.snap_epoch: exact; 398 | } 399 | actions = { 400 | snap_3_select_index_hash; 401 | snap_3_select_index_cyclic; 402 | } 403 | // size = 2; 404 | default_action = snap_3_select_index_hash(); 405 | const entries = { 406 | 0 : snap_3_select_index_cyclic(); // CLEAN 407 | } 408 | } 409 | 410 | // SNAPSHOT 0 411 | Register,_>(SKETCH_SIZE) snap_0_row_0; 412 | RegisterAction, _, bit<32>> (snap_0_row_0) snap_0_row_0_read = { 413 | void apply(inout bit<32> val, out bit<32> rv) { 414 | rv = val; 415 | } 416 | }; 417 | action regexec_snap_0_row_0_read(){ 418 | ig_md.snap_0_row_0_read=snap_0_row_0_read.execute(ig_md.snap_0_row_0_index); 419 | } 420 | RegisterAction, _, bit<32>> (snap_0_row_0) snap_0_row_0_inc = { 421 | void apply(inout bit<32> val, out bit<32> rv) { 422 | val = val + SKETCH_INC; 423 | rv = val; 424 | } 425 | }; 426 | action regexec_snap_0_row_0_inc(){ 427 | ig_md.snap_0_row_0_read=snap_0_row_0_inc.execute(ig_md.snap_0_row_0_index); 428 | } 429 | RegisterAction, _, bit<32>> (snap_0_row_0) snap_0_row_0_clr = { 430 | void apply(inout bit<32> val, out bit<32> rv) { 431 | val = 0; 432 | rv = 0; 433 | } 434 | }; 435 | action regexec_snap_0_row_0_clr(){ 436 | snap_0_row_0_clr.execute(ig_md.snap_0_row_0_index); 437 | } 438 | table tb_snap_0_row_0_rr { 439 | key = { 440 | ig_md.snap_epoch: exact; 441 | } 442 | actions = { 443 | regexec_snap_0_row_0_read; 444 | regexec_snap_0_row_0_inc; 445 | regexec_snap_0_row_0_clr; 446 | // NoAction; 447 | } 448 | // default_action = NoAction(); 449 | //round-robin logic 450 | // const entries = { 451 | // 0 : regexec_snap_0_row_0_inc(); 452 | // 1 : regexec_snap_0_row_0_clr(); 453 | // 2 : regexec_snap_0_row_0_read(); 454 | // 3 : regexec_snap_0_row_0_read(); 455 | // } 456 | // size = 4; 457 | } 458 | Register,_>(SKETCH_SIZE) snap_0_row_1; 459 | RegisterAction, _, bit<32>> (snap_0_row_1) snap_0_row_1_read = { 460 | void apply(inout bit<32> val, out bit<32> rv) { 461 | rv = val; 462 | } 463 | }; 464 | action regexec_snap_0_row_1_read(){ 465 | ig_md.snap_0_row_1_read=snap_0_row_1_read.execute(ig_md.snap_0_row_1_index); 466 | } 467 | RegisterAction, _, bit<32>> (snap_0_row_1) snap_0_row_1_inc = { 468 | void apply(inout bit<32> val, out bit<32> rv) { 469 | val = val + SKETCH_INC; 470 | rv = val; 471 | } 472 | }; 473 | action regexec_snap_0_row_1_inc(){ 474 | ig_md.snap_0_row_1_read=snap_0_row_1_inc.execute(ig_md.snap_0_row_1_index); 475 | } 476 | RegisterAction, _, bit<32>> (snap_0_row_1) snap_0_row_1_clr = { 477 | void apply(inout bit<32> val, out bit<32> rv) { 478 | val = 0; 479 | rv = 0; 480 | } 481 | }; 482 | action regexec_snap_0_row_1_clr(){ 483 | snap_0_row_1_clr.execute(ig_md.snap_0_row_1_index); 484 | } 485 | table tb_snap_0_row_1_rr { 486 | key = { 487 | ig_md.snap_epoch: exact; 488 | } 489 | actions = { 490 | regexec_snap_0_row_1_read; 491 | regexec_snap_0_row_1_inc; 492 | regexec_snap_0_row_1_clr; 493 | // NoAction; 494 | } 495 | // default_action = NoAction(); 496 | //round-robin logic 497 | // const entries = { 498 | // 0 : regexec_snap_0_row_1_inc(); 499 | // 1 : regexec_snap_0_row_1_clr(); 500 | // 2 : regexec_snap_0_row_1_read(); 501 | // 3 : regexec_snap_0_row_1_read(); 502 | // } 503 | // size = 4; 504 | } 505 | 506 | // SNAPSHOT 1 507 | Register,_>(SKETCH_SIZE) snap_1_row_0; 508 | RegisterAction, _, bit<32>> (snap_1_row_0) snap_1_row_0_read = { 509 | void apply(inout bit<32> val, out bit<32> rv) { 510 | rv = val; 511 | } 512 | }; 513 | action regexec_snap_1_row_0_read(){ 514 | ig_md.snap_1_row_0_read=snap_1_row_0_read.execute(ig_md.snap_1_row_0_index); 515 | } 516 | RegisterAction, _, bit<32>> (snap_1_row_0) snap_1_row_0_inc = { 517 | void apply(inout bit<32> val, out bit<32> rv) { 518 | val = val + SKETCH_INC; 519 | rv = val; 520 | } 521 | }; 522 | action regexec_snap_1_row_0_inc(){ 523 | ig_md.snap_1_row_0_read=snap_1_row_0_inc.execute(ig_md.snap_1_row_0_index); 524 | } 525 | RegisterAction, _, bit<32>> (snap_1_row_0) snap_1_row_0_clr = { 526 | void apply(inout bit<32> val, out bit<32> rv) { 527 | val = 0; 528 | rv = 0; 529 | } 530 | }; 531 | action regexec_snap_1_row_0_clr(){ 532 | snap_1_row_0_clr.execute(ig_md.snap_1_row_0_index); 533 | } 534 | table tb_snap_1_row_0_rr { 535 | key = { 536 | ig_md.snap_epoch: exact; 537 | } 538 | actions = { 539 | regexec_snap_1_row_0_read; 540 | regexec_snap_1_row_0_inc; 541 | regexec_snap_1_row_0_clr; 542 | // NoAction; 543 | } 544 | // default_action = NoAction(); 545 | //round-robin logic 546 | // const entries = { 547 | // 0 : regexec_snap_1_row_0_read(); 548 | // 1 : regexec_snap_1_row_0_inc(); 549 | // 2 : regexec_snap_1_row_0_clr(); 550 | // 3 : regexec_snap_1_row_0_read(); 551 | // } 552 | // size = 4; 553 | } 554 | Register,_>(SKETCH_SIZE) snap_1_row_1; 555 | RegisterAction, _, bit<32>> (snap_1_row_1) snap_1_row_1_read = { 556 | void apply(inout bit<32> val, out bit<32> rv) { 557 | rv = val; 558 | } 559 | }; 560 | action regexec_snap_1_row_1_read(){ 561 | ig_md.snap_1_row_1_read=snap_1_row_1_read.execute(ig_md.snap_1_row_1_index); 562 | } 563 | RegisterAction, _, bit<32>> (snap_1_row_1) snap_1_row_1_inc = { 564 | void apply(inout bit<32> val, out bit<32> rv) { 565 | val = val + SKETCH_INC; 566 | rv = val; 567 | } 568 | }; 569 | action regexec_snap_1_row_1_inc(){ 570 | ig_md.snap_1_row_1_read=snap_1_row_1_inc.execute(ig_md.snap_1_row_1_index); 571 | } 572 | RegisterAction, _, bit<32>> (snap_1_row_1) snap_1_row_1_clr = { 573 | void apply(inout bit<32> val, out bit<32> rv) { 574 | val = 0; 575 | rv = 0; 576 | } 577 | }; 578 | action regexec_snap_1_row_1_clr(){ 579 | snap_1_row_1_clr.execute(ig_md.snap_1_row_1_index); 580 | } 581 | table tb_snap_1_row_1_rr { 582 | key = { 583 | ig_md.snap_epoch: exact; 584 | } 585 | actions = { 586 | regexec_snap_1_row_1_read; 587 | regexec_snap_1_row_1_inc; 588 | regexec_snap_1_row_1_clr; 589 | // NoAction; 590 | } 591 | // default_action = NoAction(); 592 | //round-robin logic 593 | // const entries = { 594 | // 0 : regexec_snap_1_row_1_read(); 595 | // 1 : regexec_snap_1_row_1_inc(); 596 | // 2 : regexec_snap_1_row_1_clr(); 597 | // 3 : regexec_snap_1_row_1_read(); 598 | // } 599 | // size = 4; 600 | } 601 | 602 | // SNAPSHOT 2 603 | Register,_>(SKETCH_SIZE) snap_2_row_0; 604 | RegisterAction, _, bit<32>> (snap_2_row_0) snap_2_row_0_read = { 605 | void apply(inout bit<32> val, out bit<32> rv) { 606 | rv = val; 607 | } 608 | }; 609 | action regexec_snap_2_row_0_read(){ 610 | ig_md.snap_2_row_0_read=snap_2_row_0_read.execute(ig_md.snap_2_row_0_index); 611 | } 612 | RegisterAction, _, bit<32>> (snap_2_row_0) snap_2_row_0_inc = { 613 | void apply(inout bit<32> val, out bit<32> rv) { 614 | val = val + SKETCH_INC; 615 | rv = val; 616 | } 617 | }; 618 | action regexec_snap_2_row_0_inc(){ 619 | ig_md.snap_2_row_0_read=snap_2_row_0_inc.execute(ig_md.snap_2_row_0_index); 620 | } 621 | RegisterAction, _, bit<32>> (snap_2_row_0) snap_2_row_0_clr = { 622 | void apply(inout bit<32> val, out bit<32> rv) { 623 | val = 0; 624 | rv = 0; 625 | } 626 | }; 627 | action regexec_snap_2_row_0_clr(){ 628 | snap_2_row_0_clr.execute(ig_md.snap_2_row_0_index); 629 | } 630 | table tb_snap_2_row_0_rr { 631 | key = { 632 | ig_md.snap_epoch: exact; 633 | } 634 | actions = { 635 | regexec_snap_2_row_0_read; 636 | regexec_snap_2_row_0_inc; 637 | regexec_snap_2_row_0_clr; 638 | // NoAction; 639 | } 640 | 641 | // default_action = NoAction(); 642 | //round-robin logic 643 | // const entries = { 644 | // 0 : regexec_snap_2_row_0_read(); 645 | // 1 : regexec_snap_2_row_0_read(); 646 | // 2 : regexec_snap_2_row_0_inc(); 647 | // 3 : regexec_snap_2_row_0_clr(); 648 | // } 649 | // size = 4; 650 | } 651 | Register,_>(SKETCH_SIZE) snap_2_row_1; 652 | RegisterAction, _, bit<32>> (snap_2_row_1) snap_2_row_1_read = { 653 | void apply(inout bit<32> val, out bit<32> rv) { 654 | rv = val; 655 | } 656 | }; 657 | action regexec_snap_2_row_1_read(){ 658 | ig_md.snap_2_row_1_read=snap_2_row_1_read.execute(ig_md.snap_2_row_1_index); 659 | } 660 | RegisterAction, _, bit<32>> (snap_2_row_1) snap_2_row_1_inc = { 661 | void apply(inout bit<32> val, out bit<32> rv) { 662 | val = val + SKETCH_INC; 663 | rv = val; 664 | } 665 | }; 666 | action regexec_snap_2_row_1_inc(){ 667 | ig_md.snap_2_row_1_read=snap_2_row_1_inc.execute(ig_md.snap_2_row_1_index); 668 | } 669 | RegisterAction, _, bit<32>> (snap_2_row_1) snap_2_row_1_clr = { 670 | void apply(inout bit<32> val, out bit<32> rv) { 671 | val = 0; 672 | rv = 0; 673 | } 674 | }; 675 | action regexec_snap_2_row_1_clr(){ 676 | snap_2_row_1_clr.execute(ig_md.snap_2_row_1_index); 677 | } 678 | table tb_snap_2_row_1_rr { 679 | key = { 680 | ig_md.snap_epoch: exact; 681 | } 682 | actions = { 683 | regexec_snap_2_row_1_read; 684 | regexec_snap_2_row_1_inc; 685 | regexec_snap_2_row_1_clr; 686 | // NoAction; 687 | } 688 | 689 | // default_action = NoAction(); 690 | //round-robin logic 691 | // const entries = { 692 | // 0 : regexec_snap_2_row_1_read(); 693 | // 1 : regexec_snap_2_row_1_read(); 694 | // 2 : regexec_snap_2_row_1_inc(); 695 | // 3 : regexec_snap_2_row_1_clr(); 696 | // } 697 | // size = 4; 698 | } 699 | 700 | // SNAPSHOT 3 701 | Register,_>(SKETCH_SIZE) snap_3_row_0; 702 | RegisterAction, _, bit<32>> (snap_3_row_0) snap_3_row_0_read = { 703 | void apply(inout bit<32> val, out bit<32> rv) { 704 | rv = val; 705 | } 706 | }; 707 | action regexec_snap_3_row_0_read(){ 708 | ig_md.snap_3_row_0_read=snap_3_row_0_read.execute(ig_md.snap_3_row_0_index); 709 | } 710 | RegisterAction, _, bit<32>> (snap_3_row_0) snap_3_row_0_inc = { 711 | void apply(inout bit<32> val, out bit<32> rv) { 712 | val = val + SKETCH_INC; 713 | rv = val; 714 | } 715 | }; 716 | action regexec_snap_3_row_0_inc(){ 717 | ig_md.snap_3_row_0_read=snap_3_row_0_inc.execute(ig_md.snap_3_row_0_index); 718 | } 719 | RegisterAction, _, bit<32>> (snap_3_row_0) snap_3_row_0_clr = { 720 | void apply(inout bit<32> val, out bit<32> rv) { 721 | val = 0; 722 | rv = 0; 723 | } 724 | }; 725 | action regexec_snap_3_row_0_clr(){ 726 | snap_3_row_0_clr.execute(ig_md.snap_3_row_0_index); 727 | } 728 | table tb_snap_3_row_0_rr { 729 | key = { 730 | ig_md.snap_epoch: exact; 731 | } 732 | actions = { 733 | regexec_snap_3_row_0_read; 734 | regexec_snap_3_row_0_inc; 735 | regexec_snap_3_row_0_clr; 736 | // NoAction; 737 | } 738 | 739 | // default_action = NoAction(); 740 | //round-robin logic 741 | // const entries = { 742 | // 0 : regexec_snap_3_row_0_clr(); 743 | // 1 : regexec_snap_3_row_0_read(); 744 | // 2 : regexec_snap_3_row_0_read(); 745 | // 3 : regexec_snap_3_row_0_inc(); 746 | // } 747 | // size = 4; 748 | } 749 | Register,_>(SKETCH_SIZE) snap_3_row_1; 750 | RegisterAction, _, bit<32>> (snap_3_row_1) snap_3_row_1_read = { 751 | void apply(inout bit<32> val, out bit<32> rv) { 752 | rv = val; 753 | } 754 | }; 755 | action regexec_snap_3_row_1_read(){ 756 | ig_md.snap_3_row_1_read=snap_3_row_1_read.execute(ig_md.snap_3_row_1_index); 757 | } 758 | RegisterAction, _, bit<32>> (snap_3_row_1) snap_3_row_1_inc = { 759 | void apply(inout bit<32> val, out bit<32> rv) { 760 | val = val + SKETCH_INC; 761 | rv = val; 762 | } 763 | }; 764 | action regexec_snap_3_row_1_inc(){ 765 | ig_md.snap_3_row_1_read=snap_3_row_1_inc.execute(ig_md.snap_3_row_1_index); 766 | } 767 | RegisterAction, _, bit<32>> (snap_3_row_1) snap_3_row_1_clr = { 768 | void apply(inout bit<32> val, out bit<32> rv) { 769 | val = 0; 770 | rv = 0; 771 | } 772 | }; 773 | action regexec_snap_3_row_1_clr(){ 774 | snap_3_row_1_clr.execute(ig_md.snap_3_row_1_index); 775 | } 776 | table tb_snap_3_row_1_rr { 777 | key = { 778 | ig_md.snap_epoch: exact; 779 | } 780 | actions = { 781 | regexec_snap_3_row_1_read; 782 | regexec_snap_3_row_1_inc; 783 | regexec_snap_3_row_1_clr; 784 | // NoAction; 785 | } 786 | 787 | // default_action = NoAction(); 788 | //round-robin logic 789 | // const entries = { 790 | // 0 : regexec_snap_3_row_1_clr(); 791 | // 1 : regexec_snap_3_row_1_read(); 792 | // 2 : regexec_snap_3_row_1_read(); 793 | // 3 : regexec_snap_3_row_1_inc(); 794 | // } 795 | // size = 4; 796 | } 797 | 798 | //== Folding sums, which can't be written inline 799 | action calc_sum_0_l0(){ 800 | ig_md.snap_0_read_min_l1 = 801 | ig_md.snap_0_read_min_l0 + ig_md.snap_1_read_min_l0; 802 | } 803 | action calc_sum_2_l0(){ 804 | ig_md.snap_2_read_min_l1 = 805 | ig_md.snap_2_read_min_l0 + ig_md.snap_3_read_min_l0; 806 | } 807 | 808 | action calc_sum_0_l1(){ 809 | ig_md.snap_0_read_min_l2 = 810 | ig_md.snap_0_read_min_l1 + ig_md.snap_2_read_min_l1; 811 | } 812 | 813 | table threshold { 814 | key = { 815 | ig_md.snap_0_read_min_l2[19:0] : range; //scale down to 20 bits 816 | } 817 | actions = { 818 | NoAction; 819 | drop; 820 | } 821 | default_action = NoAction(); 822 | size = 1; 823 | } 824 | 825 | apply { 826 | ig_md.snap_epoch = ig_intr_md.ingress_mac_tstamp[33:32]; 827 | prep_reads(); 828 | 829 | bit<32> index = hash_index.get( 830 | { 831 | hdr.ipv4.src_addr, 832 | hdr.ipv4.dst_addr, 833 | hdr.ipv4.protocol, 834 | ig_md.src_port, 835 | ig_md.dst_port 836 | } 837 | ); 838 | 839 | ig_md.hashed_index_row_0 = index[13:0]; 840 | ig_md.hashed_index_row_1 = index[21:8]; 841 | 842 | // if(hdr.ipv4.protocol==IP_PROTOCOLS_TCP){ 843 | // calc_hashed_index_TCP(); 844 | // }else if(hdr.ipv4.protocol==IP_PROTOCOLS_UDP){ 845 | // calc_hashed_index_UDP(); 846 | // }else{ 847 | // calc_hashed_index_Other(); 848 | // } 849 | 850 | // Select index for snapshots. Cyclic for cleaning, hashed for read/inc 851 | // @stage(1){ 852 | tb_snap_0_select_index.apply(); 853 | tb_snap_1_select_index.apply(); 854 | tb_snap_2_select_index.apply(); 855 | tb_snap_3_select_index.apply(); 856 | // } 857 | // Run the snapshots! Round-robin clean, inc, read 858 | tb_snap_0_row_0_rr.apply(); 859 | tb_snap_0_row_1_rr.apply(); 860 | tb_snap_1_row_0_rr.apply(); 861 | tb_snap_1_row_1_rr.apply(); 862 | tb_snap_2_row_0_rr.apply(); 863 | tb_snap_2_row_1_rr.apply(); 864 | tb_snap_3_row_0_rr.apply(); 865 | tb_snap_3_row_1_rr.apply(); 866 | 867 | // Calc min across rows (as in count-"min" sketch) 868 | ig_md.snap_0_read_min_l0=min(ig_md.snap_0_row_0_read,ig_md.snap_0_row_1_read); 869 | ig_md.snap_1_read_min_l0=min(ig_md.snap_1_row_0_read,ig_md.snap_1_row_1_read); 870 | ig_md.snap_2_read_min_l0=min(ig_md.snap_2_row_0_read,ig_md.snap_2_row_1_read); 871 | ig_md.snap_3_read_min_l0=min(ig_md.snap_3_row_0_read,ig_md.snap_3_row_1_read); 872 | 873 | // Sum all reads together, using log(CQ_H) layers. 874 | calc_sum_0_l0(); 875 | calc_sum_2_l0(); 876 | 877 | calc_sum_0_l1(); 878 | 879 | // Check whether it exceeds threshold 880 | threshold.apply(); 881 | } 882 | } 883 | 884 | control SwitchEgress( 885 | inout header_t hdr, 886 | inout eg_metadata_t eg_md, 887 | in egress_intrinsic_metadata_t eg_intr_md, 888 | in egress_intrinsic_metadata_from_parser_t eg_intr_md_from_prsr, 889 | inout egress_intrinsic_metadata_for_deparser_t ig_intr_dprs_md, 890 | inout egress_intrinsic_metadata_for_output_port_t eg_intr_oport_md) { 891 | 892 | apply { 893 | 894 | } 895 | } 896 | 897 | 898 | Pipeline(SwitchIngressParser(), 899 | SwitchIngress(), 900 | SwitchIngressDeparser(), 901 | SwitchEgressParser(), 902 | SwitchEgress(), 903 | SwitchEgressDeparser() 904 | ) pipe; 905 | 906 | Switch(pipe) main; -------------------------------------------------------------------------------- /misc/fcm/fcm.p4: -------------------------------------------------------------------------------- 1 | /* -*- P4_16 -*- */ 2 | /* 3 | Retrieved and adapted from: https://github.com/fcm-project/fcm_p4 4 | */ 5 | 6 | #include 7 | #include 8 | 9 | /************************************************************************* 10 | ************* C O N S T A N T S A N D T Y P E S ******************* 11 | **************************************************************************/ 12 | #define SKETCH_W1 0x40000 // 8 bits, width at layer 1, 2^18 = 262,144 13 | #define SKETCH_W2 0x8000 // 16 bits, width at layer 2, 2^15 = 32,768 14 | #define SKETCH_W3 0x1000 // 32 bits, width at layer 3, 2^12 = 4096 15 | 16 | #define ADD_LEVEL1 0x000000ff // 2^8 - 2 + 1 (property of SALU) 17 | #define ADD_LEVEL2 0x000100fd // (2^8 - 2) + (2^16 - 2) + 1 (property of SALU) 18 | 19 | typedef bit<48> mac_addr_t; 20 | typedef bit<32> ipv4_addr_t; 21 | typedef bit<16> l4_port_t; 22 | 23 | typedef bit<16> ether_type_t; 24 | const ether_type_t ETHERTYPE_IPV4 = 16w0x0800; 25 | const ether_type_t ETHERTYPE_ARP = 16w0x0806; 26 | const ether_type_t ETHERTYPE_DECAY_UPDATE = 16w0x8888; 27 | 28 | typedef bit<8> ip_proto_t; 29 | const ip_proto_t IP_PROTO_ICMP = 1; 30 | const ip_proto_t IP_PROTO_TCP = 6; 31 | const ip_proto_t IP_PROTO_UDP = 17; 32 | 33 | typedef bit<32> count_t; 34 | 35 | const bit<3> HH_DIGEST = 0x03; 36 | struct hh_digest_t { 37 | ipv4_addr_t src_addr; 38 | ipv4_addr_t dst_addr; 39 | bit<8> protocol; 40 | l4_port_t src_port; 41 | l4_port_t dst_port; 42 | } 43 | 44 | /************************************************************************* 45 | *********************** H E A D E R S ********************************* 46 | *************************************************************************/ 47 | 48 | /* Define all the headers the program will recognize */ 49 | /* The actual sets of headers processed by each gress can differ */ 50 | 51 | /* Standard ethernet header */ 52 | header ethernet_h { 53 | mac_addr_t dst_addr; 54 | mac_addr_t src_addr; 55 | ether_type_t ether_type; 56 | } 57 | 58 | header ipv4_h { 59 | bit<4> version; 60 | bit<4> ihl; 61 | bit<8> diffserv; 62 | bit<16> total_len; 63 | bit<16> identification; 64 | bit<3> flags; 65 | bit<13> frag_offset; 66 | bit<8> ttl; 67 | ip_proto_t protocol; 68 | bit<16> hdr_checksum; 69 | ipv4_addr_t src_addr; 70 | ipv4_addr_t dst_addr; 71 | } 72 | 73 | header icmp_h { 74 | bit<8> type_; 75 | bit<8> code; 76 | bit<16> hdr_checksum; 77 | } 78 | 79 | header tcp_h { 80 | l4_port_t src_port; 81 | l4_port_t dst_port; 82 | bit<32> seq_no; 83 | bit<32> ack_no; 84 | bit<4> data_offset; 85 | bit<4> res; 86 | bit<8> flag; 87 | bit<16> window; 88 | bit<16> checksum; 89 | bit<16> urgent_ptr; 90 | } 91 | 92 | header udp_h { 93 | l4_port_t src_port; 94 | l4_port_t dst_port; 95 | bit<16> hdr_length; 96 | bit<16> checksum; 97 | } 98 | 99 | 100 | /************************************************************************* 101 | ************** I N G R E S S P R O C E S S I N G ******************* 102 | *************************************************************************/ 103 | 104 | /*********************** H E A D E R S ************************/ 105 | 106 | struct my_ingress_headers_t { 107 | ethernet_h ethernet; 108 | ipv4_h ipv4; 109 | tcp_h tcp; 110 | udp_h udp; 111 | } 112 | 113 | /****** G L O B A L I N G R E S S M E T A D A T A *********/ 114 | struct fcm_metadata_t { 115 | bit<32> hash_meta_d1; 116 | bit<32> hash_meta_d2; 117 | 118 | 119 | bit<32> result_d1; 120 | bit<32> result_d2; 121 | bit<32> increment_occupied; 122 | } 123 | 124 | struct my_ingress_metadata_t { 125 | fcm_metadata_t fcm_mdata; 126 | l4_port_t src_port; 127 | l4_port_t dst_port; 128 | } 129 | 130 | /*********************** P A R S E R **************************/ 131 | parser IngressParser(packet_in pkt, 132 | /* User */ 133 | out my_ingress_headers_t hdr, 134 | out my_ingress_metadata_t meta, 135 | /* Intrinsic */ 136 | out ingress_intrinsic_metadata_t ig_intr_md) 137 | { 138 | /* This is a mandatory state, required by Tofino Architecture */ 139 | state start { 140 | pkt.extract(ig_intr_md); 141 | pkt.advance(PORT_METADATA_SIZE); 142 | 143 | // initialize metadata 144 | meta.fcm_mdata.result_d1 = 0; 145 | meta.fcm_mdata.result_d2 = 0; 146 | meta.fcm_mdata.increment_occupied = 0; 147 | 148 | transition parse_ethernet; 149 | } 150 | 151 | state parse_ethernet { 152 | pkt.extract(hdr.ethernet); 153 | transition select(hdr.ethernet.ether_type) { 154 | ETHERTYPE_IPV4 : parse_ipv4; 155 | } 156 | } 157 | 158 | state parse_ipv4 { 159 | pkt.extract(hdr.ipv4); 160 | meta.src_port = 0; 161 | meta.dst_port = 0; 162 | transition select(hdr.ipv4.protocol) { 163 | IP_PROTO_TCP : parse_tcp; 164 | IP_PROTO_UDP : parse_udp; 165 | default : accept; 166 | } 167 | } 168 | 169 | state parse_tcp { 170 | pkt.extract(hdr.tcp); 171 | meta.src_port = hdr.tcp.src_port; 172 | meta.dst_port = hdr.tcp.dst_port; 173 | transition accept; 174 | } 175 | 176 | state parse_udp { 177 | pkt.extract(hdr.udp); 178 | meta.src_port = hdr.udp.src_port; 179 | meta.dst_port = hdr.udp.dst_port; 180 | transition accept; 181 | } 182 | } 183 | 184 | /********************* D E P A R S E R ************************/ 185 | 186 | control IngressDeparser(packet_out pkt, 187 | /* User */ 188 | inout my_ingress_headers_t hdr, 189 | in my_ingress_metadata_t meta, 190 | /* Intrinsic */ 191 | in ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md) 192 | { 193 | Mirror() mirror; 194 | Digest () hh_digest; 195 | 196 | apply { 197 | if(ig_dprsr_md.mirror_type == 1) { 198 | // session 1, where it points to the recirculation port 199 | mirror.emit(10w1); 200 | } 201 | 202 | if(ig_dprsr_md.digest_type == HH_DIGEST) { 203 | hh_digest.pack({hdr.ipv4.src_addr, hdr.ipv4.dst_addr, hdr.ipv4.protocol, meta.src_port, meta.dst_port}); 204 | } 205 | 206 | pkt.emit(hdr); 207 | } 208 | } 209 | 210 | // --------------------------------------------------------------------------- 211 | // FCM logic control block 212 | // --------------------------------------------------------------------------- 213 | control FCMSketch ( 214 | inout my_ingress_headers_t hdr, 215 | inout my_ingress_metadata_t meta, 216 | out bit<19> num_occupied_reg, 217 | out bit<32> flow_size, 218 | out bit<32> cardinality) { 219 | 220 | bit<32> index = 0; 221 | bit<32> index0 = 0; 222 | bit<32> index1 = 0; 223 | 224 | // +++++++++++++++++++ 225 | // hashings & hash action 226 | // +++++++++++++++++++ 227 | 228 | // CRCPolynomial>(32w0x04C11DB7, // polynomial 229 | // true, // reversed 230 | // false, // use msb? 231 | // false, // extended? 232 | // 32w0xFFFFFFFF, // initial shift register value 233 | // 32w0xFFFFFFFF // result xor 234 | // ) CRC32; 235 | // Hash>(HashAlgorithm_t.CUSTOM, CRC32) hash_d1; 236 | 237 | Hash>(HashAlgorithm_t.CRC32) hash_d1; 238 | CRCPolynomial>(32w0x04C11DB7, 239 | false, 240 | false, 241 | false, 242 | 32w0xFFFFFFFF, 243 | 32w0x00000000 244 | ) CRC32_MPEG; 245 | Hash>(HashAlgorithm_t.CUSTOM, CRC32_MPEG) hash_d2; 246 | 247 | 248 | // +++++++++++++++++++ 249 | // registers 250 | // +++++++++++++++++++ 251 | 252 | Register, bit<18>>(SKETCH_W1) sketch_reg_l1_d1; 253 | Register, bit<15>>(SKETCH_W2) sketch_reg_l2_d1; 254 | Register, bit<12>>(SKETCH_W3) sketch_reg_l3_d1; 255 | 256 | Register, bit<18>>(SKETCH_W1) sketch_reg_l1_d2; 257 | Register, bit<15>>(SKETCH_W2) sketch_reg_l2_d2; 258 | Register, bit<12>>(SKETCH_W3) sketch_reg_l3_d2; 259 | 260 | // total number of empty registers for all trees 261 | Register, _>(1) reg_num_empty; 262 | 263 | // +++++++++++++++++++ 264 | // register actions 265 | // +++++++++++++++++++ 266 | 267 | // level 1, depth 1 268 | RegisterAction, bit<18>, bit<32>>(sketch_reg_l1_d1) increment_l1_d1 = { 269 | void apply(inout bit<8> value, out bit<32> result) { 270 | value = value |+| 1; 271 | result = (bit<32>)value; // return level 1 value (255 -> count 254) 272 | } 273 | }; 274 | // level 2, depth 1, only when level 1 output is 255 275 | RegisterAction, bit<15>, bit<32>>(sketch_reg_l2_d1) increment_l2_d1 = { 276 | void apply(inout bit<16> value, out bit<32> result) { 277 | result = (bit<32>)value + ADD_LEVEL1; // return level 1 + 2 278 | value = value |+| 1; 279 | } 280 | }; 281 | // level 3, depth 1, only when level 2 output is 65789 282 | RegisterAction, bit<12>, bit<32>>(sketch_reg_l3_d1) increment_l3_d1 = { 283 | void apply(inout bit<32> value, out bit<32> result) { 284 | result = value + ADD_LEVEL2; // return level 1 + 2 + 3 285 | value = value |+| 1; 286 | 287 | } 288 | }; 289 | 290 | // level 1, depth 2 291 | RegisterAction, bit<18>, bit<32>>(sketch_reg_l1_d2) increment_l1_d2 = { 292 | void apply(inout bit<8> value, out bit<32> result) { 293 | value = value |+| 1; 294 | result = (bit<32>)value; // return level 1 value (255 -> count 254) 295 | } 296 | }; 297 | // level 2, depth 2, only when level 1 output is 255 298 | RegisterAction, bit<15>, bit<32>>(sketch_reg_l2_d2) increment_l2_d2 = { 299 | void apply(inout bit<16> value, out bit<32> result) { 300 | result = (bit<32>)value + ADD_LEVEL1; // return level 1 + 2 301 | value = value |+| 1; 302 | } 303 | }; 304 | // level 3, depth 2, only when level 2 output is 65789 305 | RegisterAction, bit<12>, bit<32>>(sketch_reg_l3_d2) increment_l3_d2 = { 306 | void apply(inout bit<32> value, out bit<32> result) { 307 | result = value + ADD_LEVEL2; // return level 1 + 2 + 3 308 | value = value |+| 1; // increment assuming no 32-bit overflow 309 | 310 | } 311 | }; 312 | 313 | // increment number of empty register value for cardinality 314 | RegisterAction, _, bit<32>>(reg_num_empty) increment_occupied_reg = { 315 | void apply(inout bit<32> value, out bit<32> result) { 316 | result = value + meta.fcm_mdata.increment_occupied; 317 | value = value + meta.fcm_mdata.increment_occupied; 318 | } 319 | }; 320 | 321 | 322 | // +++++++++++++++++++ 323 | // actions 324 | // +++++++++++++++++++ 325 | 326 | // action for level 1, depth 1, you can re-define the flow key identification 327 | action fcm_action_l1_d1() { 328 | // meta.fcm_mdata.result_d1 = increment_l1_d1.execute(index0[17:0]); 329 | meta.fcm_mdata.result_d1 = increment_l1_d1.execute(index[17:0]); 330 | } 331 | // action for level 2, depth 1 332 | action fcm_action_l2_d1() { 333 | // meta.fcm_mdata.result_d1 = increment_l2_d1.execute(index0[17:3]); 334 | meta.fcm_mdata.result_d1 = increment_l2_d1.execute(index[17:3]); 335 | } 336 | // action for level 3, depth 1 337 | action fcm_action_l3_d1() { 338 | // meta.fcm_mdata.result_d1 = increment_l3_d1.execute(index0[17:6]); 339 | meta.fcm_mdata.result_d1 = increment_l3_d1.execute(index[17:6]); 340 | } 341 | 342 | // action for level 1, depth 2, you can re-define the flow key identification 343 | action fcm_action_l1_d2() { 344 | // meta.fcm_mdata.result_d2 = increment_l1_d2.execute(index1[17:0]); 345 | meta.fcm_mdata.result_d2 = increment_l1_d2.execute(index[23:6]); 346 | } 347 | // action for level 2, depth 2 348 | action fcm_action_l2_d2() { 349 | // meta.fcm_mdata.result_d2 = increment_l2_d2.execute(index1[17:3]); 350 | meta.fcm_mdata.result_d2 = increment_l2_d2.execute(index1[23:9]); 351 | } 352 | // action for level 3, depth 2 353 | action fcm_action_l3_d2() { 354 | // meta.fcm_mdata.result_d2 = increment_l3_d2.execute(index1[17:6]); 355 | meta.fcm_mdata.result_d2 = increment_l3_d2.execute(index1[23:12]); 356 | } 357 | 358 | 359 | // increment reg of occupied leaf number 360 | action fcm_action_increment_cardreg() { 361 | num_occupied_reg = (increment_occupied_reg.execute(0))[19:1]; 362 | } 363 | 364 | action fcm_action_check_occupied(bit<32> increment_val) { 365 | meta.fcm_mdata.increment_occupied = increment_val; 366 | } 367 | 368 | 369 | action fcm_action_set_cardinality(bit<32> card_match) { 370 | cardinality = card_match; 371 | } 372 | 373 | // +++++++++++++++++++ 374 | // tables 375 | // +++++++++++++++++++ 376 | 377 | // if level 1 is full, move to level 2. 378 | table tb_fcm_l1_to_l2_d1 { 379 | key = { 380 | meta.fcm_mdata.result_d1 : exact; 381 | } 382 | actions = { 383 | fcm_action_l2_d1; 384 | @defaultonly NoAction; 385 | } 386 | const default_action = NoAction(); 387 | const entries = { 388 | 32w255: fcm_action_l2_d1(); 389 | } 390 | size = 2; 391 | } 392 | 393 | // if level 2 is full, move to level 3. 394 | table tb_fcm_l2_to_l3_d1 { 395 | key = { 396 | meta.fcm_mdata.result_d1 : exact; 397 | } 398 | actions = { 399 | fcm_action_l3_d1; 400 | @defaultonly NoAction; 401 | } 402 | const default_action = NoAction(); 403 | const entries = { 404 | 32w65789: fcm_action_l3_d1(); 405 | } 406 | size = 2; 407 | } 408 | 409 | // if level 1 is full, move to level 2. 410 | table tb_fcm_l1_to_l2_d2 { 411 | key = { 412 | meta.fcm_mdata.result_d2 : exact; 413 | } 414 | actions = { 415 | fcm_action_l2_d2; 416 | @defaultonly NoAction; 417 | } 418 | const default_action = NoAction(); 419 | const entries = { 420 | 32w255: fcm_action_l2_d2(); 421 | } 422 | size = 2; 423 | } 424 | 425 | // if level 2 is full, move to level 3. 426 | table tb_fcm_l2_to_l3_d2 { 427 | key = { 428 | meta.fcm_mdata.result_d2 : exact; 429 | } 430 | actions = { 431 | fcm_action_l3_d2; 432 | @defaultonly NoAction; 433 | } 434 | const default_action = NoAction(); 435 | const entries = { 436 | 32w65789: fcm_action_l3_d2(); 437 | } 438 | size = 2; 439 | } 440 | 441 | // Update the number of occupied leaf nodes 442 | table tb_fcm_increment_occupied { 443 | key = { 444 | meta.fcm_mdata.result_d1 : ternary; 445 | meta.fcm_mdata.result_d2 : ternary; 446 | } 447 | actions = { 448 | fcm_action_check_occupied; 449 | } 450 | const default_action = fcm_action_check_occupied(0); 451 | const entries = { 452 | (32w1, 32w1) : fcm_action_check_occupied(2); 453 | (32w1, _) : fcm_action_check_occupied(1); 454 | (_, 32w1) : fcm_action_check_occupied(1); 455 | } 456 | size = 4; 457 | } 458 | 459 | 460 | // look up LC cardinality using number of empty counters at level 1 461 | // [30:12] : divide by 2 ("average" empty_reg number). 462 | // Each array size is 2 ** 19, so slice 19 bits 463 | table tb_fcm_cardinality { 464 | key = { 465 | num_occupied_reg : range; // 19 bits 466 | } 467 | actions = { 468 | fcm_action_set_cardinality; 469 | } 470 | const default_action = fcm_action_set_cardinality(0); 471 | size = 4096; 472 | } 473 | 474 | 475 | // +++++++++++++++++++ 476 | // apply 477 | // +++++++++++++++++++ 478 | apply { 479 | // index0 = hash_d1.get( 480 | // { 481 | // hdr.ipv4.src_addr, 482 | // hdr.ipv4.dst_addr, 483 | // hdr.ipv4.protocol, 484 | // meta.src_port, 485 | // meta.dst_port 486 | // } 487 | // ); 488 | // index1 = hash_d2.get( 489 | // { 490 | // hdr.ipv4.src_addr, 491 | // hdr.ipv4.dst_addr, 492 | // hdr.ipv4.protocol, 493 | // meta.src_port, 494 | // meta.dst_port 495 | // } 496 | // ); 497 | index = hash_d2.get( 498 | { 499 | hdr.ipv4.src_addr, 500 | hdr.ipv4.dst_addr, 501 | hdr.ipv4.protocol, 502 | meta.src_port, 503 | meta.dst_port 504 | } 505 | ); 506 | 507 | fcm_action_l1_d1(); // increment level 1, depth 1 508 | fcm_action_l1_d2(); // increment level 1, depth 2 509 | /* increment the number of occupied leaf nodes */ 510 | // tb_fcm_increment_occupied.apply(); 511 | // fcm_action_increment_cardreg(); 512 | // tb_fcm_cardinality.apply(); // calculate cardinality estimate 513 | tb_fcm_l1_to_l2_d1.apply(); // conditional increment level 2, depth 1 514 | tb_fcm_l1_to_l2_d2.apply(); // conditional increment level 2, depth 2 515 | tb_fcm_l2_to_l3_d1.apply(); // conditional increment level 3, depth 1 516 | tb_fcm_l2_to_l3_d2.apply(); // conditional increment level 3, depth 2 517 | 518 | /* Take minimum for final count-query. */ 519 | flow_size = meta.fcm_mdata.result_d1 > meta.fcm_mdata.result_d2 ? meta.fcm_mdata.result_d2 : meta.fcm_mdata.result_d1; 520 | } 521 | } 522 | 523 | 524 | /***************** M A T C H - A C T I O N *********************/ 525 | 526 | control Ingress( 527 | /* User */ 528 | inout my_ingress_headers_t hdr, 529 | inout my_ingress_metadata_t meta, 530 | /* Intrinsic */ 531 | in ingress_intrinsic_metadata_t ig_intr_md, 532 | in ingress_intrinsic_metadata_from_parser_t ig_prsr_md, 533 | inout ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md, 534 | inout ingress_intrinsic_metadata_for_tm_t ig_tm_md) 535 | { 536 | 537 | bit<19> num_occupied_reg = 0; // local variable for cardinality 538 | bit<32> flow_size = 0; // local variable for final query 539 | bit<32> cardinality = 0; // local variable for final query 540 | 541 | 542 | /*** temp ***/ 543 | // increment when packet comes in 544 | Register, _>(1, 0) num_pkt; 545 | RegisterAction, _, bit<32>>(num_pkt) increment_pkt = { 546 | void apply(inout bit<32> value, out bit<32> result) { 547 | value = value |+| 1; 548 | result = value; 549 | } 550 | }; 551 | 552 | action count_pkt() { 553 | increment_pkt.execute(0); 554 | } 555 | /*** temp ***/ 556 | 557 | action generate_digest() { 558 | ig_dprsr_md.digest_type = 0x03; 559 | } 560 | 561 | action drop() { 562 | ig_dprsr_md.drop_ctl = 0x0; // drop packet 563 | exit; 564 | } 565 | 566 | action forward(PortId_t port) { 567 | ig_tm_md.ucast_egress_port = port; 568 | } 569 | 570 | table ipv4_forward { 571 | key = { 572 | ig_intr_md.ingress_port : exact; 573 | } 574 | actions = { 575 | forward; 576 | NoAction; 577 | } 578 | default_action = NoAction(); 579 | } 580 | 581 | 582 | table threshold { 583 | key = { 584 | // TODO: this needs to be slightly readjusted 585 | flow_size[19:0] : range; 586 | } 587 | actions = { 588 | generate_digest; 589 | NoAction; 590 | } 591 | default_action = NoAction(); 592 | size = 1; 593 | } 594 | 595 | 596 | FCMSketch() fcmsketch; 597 | apply { 598 | // bit<19> num_occupied_reg; // local variable for cardinality 599 | // bit<32> flow_size; // local variable for final query 600 | // bit<32> cardinality; // local variable for final query 601 | 602 | // count_pkt(); // temp 603 | ipv4_forward.apply(); 604 | fcmsketch.apply(hdr, 605 | meta, 606 | num_occupied_reg, 607 | flow_size, 608 | cardinality); 609 | 610 | threshold.apply(); 611 | } 612 | } 613 | 614 | /************************************************************************* 615 | **************** E G R E S S P R O C E S S I N G ******************* 616 | *************************************************************************/ 617 | 618 | /*********************** H E A D E R S ************************/ 619 | 620 | struct my_egress_headers_t { 621 | } 622 | 623 | /******** G L O B A L E G R E S S M E T A D A T A *********/ 624 | 625 | struct my_egress_metadata_t { 626 | } 627 | 628 | /*********************** P A R S E R **************************/ 629 | 630 | parser EgressParser(packet_in pkt, 631 | /* User */ 632 | out my_egress_headers_t hdr, 633 | out my_egress_metadata_t meta, 634 | /* Intrinsic */ 635 | out egress_intrinsic_metadata_t eg_intr_md) 636 | { 637 | /* This is a mandatory state, required by Tofino Architecture */ 638 | state start { 639 | pkt.extract(eg_intr_md); 640 | transition accept; 641 | } 642 | } 643 | 644 | /***************** M A T C H - A C T I O N *********************/ 645 | 646 | control Egress( 647 | /* User */ 648 | inout my_egress_headers_t hdr, 649 | inout my_egress_metadata_t meta, 650 | /* Intrinsic */ 651 | in egress_intrinsic_metadata_t eg_intr_md, 652 | in egress_intrinsic_metadata_from_parser_t eg_prsr_md, 653 | inout egress_intrinsic_metadata_for_deparser_t eg_dprsr_md, 654 | inout egress_intrinsic_metadata_for_output_port_t eg_oport_md) 655 | { 656 | apply { 657 | } 658 | } 659 | 660 | /********************* D E P A R S E R ************************/ 661 | 662 | control EgressDeparser(packet_out pkt, 663 | /* User */ 664 | inout my_egress_headers_t hdr, 665 | in my_egress_metadata_t meta, 666 | /* Intrinsic */ 667 | in egress_intrinsic_metadata_for_deparser_t eg_dprsr_md) 668 | { 669 | apply { 670 | pkt.emit(hdr); 671 | } 672 | } 673 | 674 | 675 | Pipeline( 676 | IngressParser(), 677 | Ingress(), 678 | IngressDeparser(), 679 | EgressParser(), 680 | Egress(), 681 | EgressDeparser() 682 | ) pipe; 683 | 684 | Switch(pipe) main; 685 | 686 | 687 | -------------------------------------------------------------------------------- /misc/precision/entries_better_32.p4inc: -------------------------------------------------------------------------------- 1 | (32w0x0 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w4095 ) : clone_and_recirc_replace_entry(); 2 | (32w0x1 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w2047 ) : clone_and_recirc_replace_entry(); 3 | (32w0x2 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w1364 ) : clone_and_recirc_replace_entry(); 4 | (32w0x3 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w1023 ) : clone_and_recirc_replace_entry(); 5 | (32w0x4 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w818 ) : clone_and_recirc_replace_entry(); 6 | (32w0x5 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w681 ) : clone_and_recirc_replace_entry(); 7 | (32w0x6 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w584 ) : clone_and_recirc_replace_entry(); 8 | (32w0x7 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 9 | (32w0x8 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 10 | (32w0x9 &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 11 | (32w0xa &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 12 | (32w0xb &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 13 | (32w0xc &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 14 | (32w0xd &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 15 | (32w0xe &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 16 | (32w0xf &&& 32w0xffffffff, 32w0 &&& 32w0, 12w0..12w255 ) : clone_and_recirc_replace_entry(); 17 | (32w0x10 &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 18 | (32w0x12 &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 19 | (32w0x14 &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 20 | (32w0x16 &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 21 | (32w0x18 &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 22 | (32w0x1a &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 23 | (32w0x1c &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 24 | (32w0x1e &&& 32w0xfffffffe, 32w0 &&& 32w0x1, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 25 | (32w0x20 &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 26 | (32w0x24 &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 27 | (32w0x28 &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 28 | (32w0x2c &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 29 | (32w0x30 &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 30 | (32w0x34 &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 31 | (32w0x38 &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 32 | (32w0x3c &&& 32w0xfffffffc, 32w0 &&& 32w0x3, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 33 | (32w0x40 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 34 | (32w0x48 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 35 | (32w0x50 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 36 | (32w0x58 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 37 | (32w0x60 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 38 | (32w0x68 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 39 | (32w0x70 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 40 | (32w0x78 &&& 32w0xfffffff8, 32w0 &&& 32w0x7, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 41 | (32w0x80 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 42 | (32w0x90 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 43 | (32w0xa0 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 44 | (32w0xb0 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 45 | (32w0xc0 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 46 | (32w0xd0 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 47 | (32w0xe0 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 48 | (32w0xf0 &&& 32w0xfffffff0, 32w0 &&& 32w0xf, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 49 | (32w0x100 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 50 | (32w0x120 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 51 | (32w0x140 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 52 | (32w0x160 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 53 | (32w0x180 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 54 | (32w0x1a0 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 55 | (32w0x1c0 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 56 | (32w0x1e0 &&& 32w0xffffffe0, 32w0 &&& 32w0x1f, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 57 | (32w0x200 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 58 | (32w0x240 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 59 | (32w0x280 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 60 | (32w0x2c0 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 61 | (32w0x300 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 62 | (32w0x340 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 63 | (32w0x380 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 64 | (32w0x3c0 &&& 32w0xffffffc0, 32w0 &&& 32w0x3f, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 65 | (32w0x400 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 66 | (32w0x480 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 67 | (32w0x500 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 68 | (32w0x580 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 69 | (32w0x600 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 70 | (32w0x680 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 71 | (32w0x700 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 72 | (32w0x780 &&& 32w0xffffff80, 32w0 &&& 32w0x7f, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 73 | (32w0x800 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 74 | (32w0x900 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 75 | (32w0xa00 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 76 | (32w0xb00 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 77 | (32w0xc00 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 78 | (32w0xd00 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 79 | (32w0xe00 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 80 | (32w0xf00 &&& 32w0xffffff00, 32w0 &&& 32w0xff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 81 | (32w0x1000 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 82 | (32w0x1200 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 83 | (32w0x1400 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 84 | (32w0x1600 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 85 | (32w0x1800 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 86 | (32w0x1a00 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 87 | (32w0x1c00 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 88 | (32w0x1e00 &&& 32w0xfffffe00, 32w0 &&& 32w0x1ff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 89 | (32w0x2000 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 90 | (32w0x2400 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 91 | (32w0x2800 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 92 | (32w0x2c00 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 93 | (32w0x3000 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 94 | (32w0x3400 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 95 | (32w0x3800 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 96 | (32w0x3c00 &&& 32w0xfffffc00, 32w0 &&& 32w0x3ff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 97 | (32w0x4000 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 98 | (32w0x4800 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 99 | (32w0x5000 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 100 | (32w0x5800 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 101 | (32w0x6000 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 102 | (32w0x6800 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 103 | (32w0x7000 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 104 | (32w0x7800 &&& 32w0xfffff800, 32w0 &&& 32w0x7ff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 105 | (32w0x8000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 106 | (32w0x9000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 107 | (32w0xa000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 108 | (32w0xb000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 109 | (32w0xc000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 110 | (32w0xd000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 111 | (32w0xe000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 112 | (32w0xf000 &&& 32w0xfffff000, 32w0 &&& 32w0xfff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 113 | (32w0x10000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 114 | (32w0x12000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 115 | (32w0x14000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 116 | (32w0x16000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 117 | (32w0x18000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 118 | (32w0x1a000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 119 | (32w0x1c000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 120 | (32w0x1e000 &&& 32w0xffffe000, 32w0 &&& 32w0x1fff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 121 | (32w0x20000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 122 | (32w0x24000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 123 | (32w0x28000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 124 | (32w0x2c000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 125 | (32w0x30000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 126 | (32w0x34000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 127 | (32w0x38000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 128 | (32w0x3c000 &&& 32w0xffffc000, 32w0 &&& 32w0x3fff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 129 | (32w0x40000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 130 | (32w0x48000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 131 | (32w0x50000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 132 | (32w0x58000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 133 | (32w0x60000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 134 | (32w0x68000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 135 | (32w0x70000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 136 | (32w0x78000 &&& 32w0xffff8000, 32w0 &&& 32w0x7fff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 137 | (32w0x80000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 138 | (32w0x90000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 139 | (32w0xa0000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 140 | (32w0xb0000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 141 | (32w0xc0000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 142 | (32w0xd0000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 143 | (32w0xe0000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 144 | (32w0xf0000 &&& 32w0xffff0000, 32w0 &&& 32w0xffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 145 | (32w0x100000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 146 | (32w0x120000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 147 | (32w0x140000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 148 | (32w0x160000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 149 | (32w0x180000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 150 | (32w0x1a0000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 151 | (32w0x1c0000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 152 | (32w0x1e0000 &&& 32w0xfffe0000, 32w0 &&& 32w0x1ffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 153 | (32w0x200000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 154 | (32w0x240000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 155 | (32w0x280000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 156 | (32w0x2c0000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 157 | (32w0x300000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 158 | (32w0x340000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 159 | (32w0x380000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 160 | (32w0x3c0000 &&& 32w0xfffc0000, 32w0 &&& 32w0x3ffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 161 | (32w0x400000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 162 | (32w0x480000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 163 | (32w0x500000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 164 | (32w0x580000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 165 | (32w0x600000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 166 | (32w0x680000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 167 | (32w0x700000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 168 | (32w0x780000 &&& 32w0xfff80000, 32w0 &&& 32w0x7ffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 169 | (32w0x800000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 170 | (32w0x900000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 171 | (32w0xa00000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 172 | (32w0xb00000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 173 | (32w0xc00000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 174 | (32w0xd00000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 175 | (32w0xe00000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 176 | (32w0xf00000 &&& 32w0xfff00000, 32w0 &&& 32w0xfffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 177 | (32w0x1000000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 178 | (32w0x1200000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 179 | (32w0x1400000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 180 | (32w0x1600000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 181 | (32w0x1800000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 182 | (32w0x1a00000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 183 | (32w0x1c00000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 184 | (32w0x1e00000 &&& 32w0xffe00000, 32w0 &&& 32w0x1fffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 185 | (32w0x2000000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 186 | (32w0x2400000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 187 | (32w0x2800000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 188 | (32w0x2c00000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 189 | (32w0x3000000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 190 | (32w0x3400000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 191 | (32w0x3800000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 192 | (32w0x3c00000 &&& 32w0xffc00000, 32w0 &&& 32w0x3fffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 193 | (32w0x4000000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 194 | (32w0x4800000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 195 | (32w0x5000000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 196 | (32w0x5800000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 197 | (32w0x6000000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 198 | (32w0x6800000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 199 | (32w0x7000000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 200 | (32w0x7800000 &&& 32w0xff800000, 32w0 &&& 32w0x7fffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 201 | (32w0x8000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 202 | (32w0x9000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 203 | (32w0xa000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 204 | (32w0xb000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 205 | (32w0xc000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 206 | (32w0xd000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 207 | (32w0xe000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 208 | (32w0xf000000 &&& 32w0xff000000, 32w0 &&& 32w0xffffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 209 | (32w0x10000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 210 | (32w0x12000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 211 | (32w0x14000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 212 | (32w0x16000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 213 | (32w0x18000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 214 | (32w0x1a000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 215 | (32w0x1c000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 216 | (32w0x1e000000 &&& 32w0xfe000000, 32w0 &&& 32w0x1ffffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 217 | (32w0x20000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 218 | (32w0x24000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 219 | (32w0x28000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 220 | (32w0x2c000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 221 | (32w0x30000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 222 | (32w0x34000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 223 | (32w0x38000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 224 | (32w0x3c000000 &&& 32w0xfc000000, 32w0 &&& 32w0x3ffffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 225 | (32w0x40000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 226 | (32w0x48000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 227 | (32w0x50000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 228 | (32w0x58000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 229 | (32w0x60000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 230 | (32w0x68000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 231 | (32w0x70000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 232 | (32w0x78000000 &&& 32w0xf8000000, 32w0 &&& 32w0x7ffffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 233 | (32w0x80000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w511 ) : clone_and_recirc_replace_entry(); 234 | (32w0x90000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w454 ) : clone_and_recirc_replace_entry(); 235 | (32w0xa0000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w408 ) : clone_and_recirc_replace_entry(); 236 | (32w0xb0000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w371 ) : clone_and_recirc_replace_entry(); 237 | (32w0xc0000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w340 ) : clone_and_recirc_replace_entry(); 238 | (32w0xd0000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w314 ) : clone_and_recirc_replace_entry(); 239 | (32w0xe0000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w291 ) : clone_and_recirc_replace_entry(); 240 | (32w0xf0000000 &&& 32w0xf0000000, 32w0 &&& 32w0xfffffff, 12w0..12w272 ) : clone_and_recirc_replace_entry(); 241 | -------------------------------------------------------------------------------- /misc/precision/precision.p4: -------------------------------------------------------------------------------- 1 | /* 2 | PRECISION: A heavy-htter detection algorithm using Probabilistic Recirculation 3 | 4 | Copyright (C) 2019 Xiaoqi Chen, Princeton University 5 | xiaoqic [at] cs.princeton.edu 6 | 7 | This program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU Affero General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | This program is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | GNU Affero General Public License for more details. 15 | You should have received a copy of the GNU Affero General Public License 16 | along with this program. If not, see . 17 | */ 18 | 19 | /* 20 | Retrieved, and adapted from: https://github.com/Princeton-Cabernet/p4-projects 21 | */ 22 | 23 | 24 | #include 25 | #include 26 | //== Preamble: macro, header and parser definitions 27 | 28 | #define _OAT(act) table tb_## act { \ 29 | actions = {act;} \ 30 | default_action = act(); \ 31 | size = 1; \ 32 | } 33 | 34 | typedef bit<48> mac_addr_t; 35 | typedef bit<32> ipv4_addr_t; 36 | typedef bit<16> ether_type_t; 37 | const ether_type_t ETHERTYPE_IPV4 = 16w0x0800; 38 | const ether_type_t ETHERTYPE_VLAN = 16w0x0810; 39 | 40 | typedef bit<8> ip_protocol_t; 41 | const ip_protocol_t IP_PROTOCOLS_ICMP = 1; 42 | const ip_protocol_t IP_PROTOCOLS_TCP = 6; 43 | const ip_protocol_t IP_PROTOCOLS_UDP = 17; 44 | 45 | 46 | header ethernet_h { 47 | mac_addr_t dst_addr; 48 | mac_addr_t src_addr; 49 | bit<16> ether_type; 50 | } 51 | 52 | header vlan_h { 53 | bit<3> pri; 54 | bit<1> cfi; 55 | bit<12> vlan_id; 56 | bit<16> etherType; 57 | } 58 | 59 | header ipv4_h { 60 | bit<4> version; 61 | bit<4> ihl; 62 | bit<8> diffserv; 63 | bit<16> total_len; 64 | bit<16> identification; 65 | bit<3> flags; 66 | bit<13> frag_offset; 67 | bit<8> ttl; 68 | bit<8> protocol; 69 | bit<16> hdr_checksum; 70 | ipv4_addr_t src_addr; 71 | ipv4_addr_t dst_addr; 72 | } 73 | 74 | header tcp_h { 75 | bit<16> src_port; 76 | bit<16> dst_port; 77 | 78 | bit<32> seq_no; 79 | bit<32> ack_no; 80 | bit<4> data_offset; 81 | bit<4> res; 82 | bit<8> flags; 83 | bit<16> window; 84 | bit<16> checksum; 85 | bit<16> urgent_ptr; 86 | } 87 | 88 | header udp_h { 89 | bit<16> src_port; 90 | bit<16> dst_port; 91 | bit<16> hdr_lenght; 92 | bit<16> checksum; 93 | } 94 | 95 | struct header_t { 96 | ethernet_h ethernet; 97 | vlan_h vlan; 98 | ipv4_h ipv4; 99 | tcp_h tcp; 100 | udp_h udp; 101 | } 102 | 103 | header resubmit_data_64bit_t { 104 | //size is 64, same as port meta 105 | bit<8> min_stage; 106 | bit<8> data_1; 107 | bit<16> data_2; 108 | bit<32> _padding; 109 | } 110 | 111 | header resubmit_data_skimmed_t { 112 | bit<8> min_stage; 113 | bit<8> data_1; 114 | bit<16> data_2; 115 | } 116 | 117 | const bit<3> HH_DIGEST = 0x03; 118 | struct hh_digest_t { 119 | ipv4_addr_t src_addr; 120 | ipv4_addr_t dst_addr; 121 | bit<8> protocol; 122 | bit<16> src_port; 123 | bit<16> dst_port; 124 | } 125 | 126 | 127 | @pa_container_size("ingress","ig_md.flow_id_part_1",32) 128 | @pa_container_size("ingress","ig_md.flow_id_part_2",32) 129 | @pa_container_size("ingress","ig_md.flow_id_part_3",32) 130 | @pa_container_size("ingress","ig_md.flow_id_part_4",32) 131 | @pa_container_size("ingress","ig_md.resubmit_data_read.min_stage",8) 132 | @pa_container_size("ingress","ig_md.resubmit_data_write.min_stage",8) 133 | struct ig_metadata_t { 134 | resubmit_data_64bit_t resubmit_data_read; 135 | resubmit_data_skimmed_t resubmit_data_write; 136 | 137 | //128bit flowID 138 | bit<32> flow_id_part_1; 139 | bit<32> flow_id_part_2; 140 | bit<32> flow_id_part_3; 141 | bit<32> flow_id_part_4; 142 | 143 | //register index to access (hash of flow ID, with different hash functions) 144 | bit<14> stage_1_loc; 145 | bit<14> stage_2_loc; 146 | //hash seeds, different width 147 | bit<3> hash_seed_1; 148 | bit<5> hash_seed_2; 149 | 150 | //is flowID matched register entry? 151 | bit<8> fid_matched_1_1; 152 | bit<8> fid_matched_1_2; 153 | bit<8> fid_matched_1_3; 154 | bit<8> fid_matched_1_4; 155 | bit<8> fid_matched_2_1; 156 | bit<8> fid_matched_2_2; 157 | bit<8> fid_matched_2_3; 158 | bit<8> fid_matched_2_4; 159 | 160 | bool matched_at_stage_1; 161 | bool matched_at_stage_2; 162 | 163 | //if so, we need to carry current count, and remember c_min/min_stage 164 | bit<32> counter_read_1; 165 | bit<32> counter_read_2; 166 | //bit<32> counter_incr;//you have a match, this is incremented value 167 | bit<32> c_min; 168 | bit<32> diff; 169 | 170 | //need some entropy for random coin flips! 171 | bit<32> entropy_long; 172 | bit<12> entropy_short; 173 | 174 | bit<16> src_port; 175 | bit<16> dst_port; 176 | } 177 | struct eg_metadata_t { 178 | } 179 | 180 | struct paired_32bit { 181 | bit<32> lo; 182 | bit<32> hi; 183 | } 184 | 185 | parser TofinoIngressParser( 186 | packet_in pkt, 187 | inout ig_metadata_t ig_md, 188 | out ingress_intrinsic_metadata_t ig_intr_md) { 189 | state start { 190 | pkt.extract(ig_intr_md); 191 | transition select(ig_intr_md.resubmit_flag) { 192 | 1 : parse_resubmit; 193 | 0 : parse_port_metadata; 194 | } 195 | } 196 | 197 | state parse_resubmit { 198 | // Parse resubmitted packet here. 199 | //pkt.advance(64); 200 | pkt.extract(ig_md.resubmit_data_read); 201 | transition accept; 202 | } 203 | 204 | state parse_port_metadata { 205 | pkt.advance(64); //tofino 1 206 | transition accept; 207 | } 208 | } 209 | parser SwitchIngressParser( 210 | packet_in pkt, 211 | out header_t hdr, 212 | out ig_metadata_t ig_md, 213 | out ingress_intrinsic_metadata_t ig_intr_md) { 214 | 215 | TofinoIngressParser() tofino_parser; 216 | 217 | state start { 218 | tofino_parser.apply(pkt, ig_md, ig_intr_md); 219 | transition parse_ethernet; 220 | } 221 | 222 | state parse_ethernet { 223 | pkt.extract(hdr.ethernet); 224 | transition select (hdr.ethernet.ether_type) { 225 | ETHERTYPE_IPV4 : parse_ipv4; 226 | ETHERTYPE_VLAN: parse_vlan; 227 | default : reject; 228 | } 229 | } 230 | 231 | state parse_vlan { 232 | pkt.extract(hdr.vlan); 233 | transition select(hdr.vlan.etherType) { 234 | ETHERTYPE_IPV4: parse_ipv4; 235 | default: reject; 236 | } 237 | } 238 | 239 | state parse_ipv4 { 240 | pkt.extract(hdr.ipv4); 241 | ig_md.src_port = 0; 242 | ig_md.dst_port = 0; 243 | transition select(hdr.ipv4.protocol) { 244 | IP_PROTOCOLS_TCP : parse_tcp; 245 | IP_PROTOCOLS_UDP : parse_udp; 246 | default : accept; 247 | } 248 | } 249 | 250 | state parse_tcp { 251 | pkt.extract(hdr.tcp); 252 | ig_md.src_port = hdr.tcp.src_port; 253 | ig_md.dst_port = hdr.tcp.dst_port; 254 | transition accept; 255 | } 256 | 257 | state parse_udp { 258 | pkt.extract(hdr.udp); 259 | ig_md.src_port = hdr.udp.src_port; 260 | ig_md.dst_port = hdr.udp.dst_port; 261 | transition accept; 262 | } 263 | } 264 | 265 | control SwitchIngressDeparser( 266 | packet_out pkt, 267 | inout header_t hdr, 268 | in ig_metadata_t ig_md, 269 | in ingress_intrinsic_metadata_for_deparser_t ig_intr_dprsr_md) { 270 | 271 | Digest () hh_digest; 272 | Resubmit() resubmit; 273 | 274 | apply { 275 | 276 | if(ig_intr_dprsr_md.digest_type == HH_DIGEST) { 277 | hh_digest.pack({hdr.ipv4.src_addr, hdr.ipv4.dst_addr, hdr.ipv4.protocol, ig_md.src_port, ig_md.dst_port}); 278 | } 279 | 280 | if (ig_intr_dprsr_md.resubmit_type == 1) { 281 | resubmit.emit(ig_md.resubmit_data_write); 282 | } 283 | 284 | pkt.emit(hdr.ethernet); 285 | pkt.emit(hdr.vlan); 286 | pkt.emit(hdr.ipv4); 287 | pkt.emit(hdr.tcp); 288 | pkt.emit(hdr.udp); 289 | } 290 | } 291 | 292 | parser SwitchEgressParser( 293 | packet_in pkt, 294 | out header_t hdr, 295 | out eg_metadata_t eg_md, 296 | out egress_intrinsic_metadata_t eg_intr_md) { 297 | state start { 298 | pkt.extract(eg_intr_md); 299 | transition accept; 300 | } 301 | } 302 | 303 | control SwitchEgressDeparser( 304 | packet_out pkt, 305 | inout header_t hdr, 306 | in eg_metadata_t eg_md, 307 | in egress_intrinsic_metadata_for_deparser_t eg_intr_md_for_dprsr) { 308 | apply { 309 | } 310 | } 311 | 312 | 313 | // == Start of control logic 314 | control SwitchIngress( 315 | inout header_t hdr, 316 | inout ig_metadata_t ig_md, 317 | in ingress_intrinsic_metadata_t ig_intr_md, 318 | in ingress_intrinsic_metadata_from_parser_t ig_intr_prsr_md, 319 | inout ingress_intrinsic_metadata_for_deparser_t ig_intr_dprsr_md, 320 | inout ingress_intrinsic_metadata_for_tm_t ig_intr_tm_md) { 321 | 322 | // action drop() { 323 | // ig_intr_dprsr_md.drop_ctl = 0x1; // Drop packet. 324 | // } 325 | action nop() { 326 | } 327 | 328 | action route_to_64(){ 329 | //route to CPU NIC. on model, it is veth250 330 | ig_intr_tm_md.ucast_egress_port=64; 331 | } 332 | 333 | action drop() { 334 | ig_intr_dprsr_md.drop_ctl = 0x1; // drop packet 335 | exit; 336 | } 337 | 338 | action forward(PortId_t port) { 339 | ig_intr_tm_md.ucast_egress_port = port; 340 | } 341 | 342 | table ipv4_forward { 343 | key = { 344 | 345 | ig_intr_md.ingress_port : exact; 346 | } 347 | actions = { 348 | forward; 349 | NoAction; 350 | } 351 | default_action = NoAction(); 352 | } 353 | 354 | action generate_digest() { 355 | // ig_intr_dprsr_md.digest_type = HH_DIGEST; 356 | ig_intr_tm_md.ucast_egress_port = 320; 357 | } 358 | 359 | // == Calculate flow ID for the packet 360 | 361 | Hash>(HashAlgorithm_t.IDENTITY) copy32_1; 362 | Hash>(HashAlgorithm_t.IDENTITY) copy32_2; 363 | Hash>(HashAlgorithm_t.IDENTITY) copy32_3; 364 | Hash>(HashAlgorithm_t.IDENTITY) copy16_1; 365 | Hash>(HashAlgorithm_t.IDENTITY) copy16_2; 366 | Hash>(HashAlgorithm_t.IDENTITY) copy16_3; 367 | Hash>(HashAlgorithm_t.IDENTITY) copy16_4; 368 | 369 | action copy_flow_id_common_1_(){ 370 | ig_md.flow_id_part_1=hdr.ipv4.src_addr;//copy32_1.get({hdr.ipv4.src_addr}); 371 | } 372 | action copy_flow_id_common_2_(){ 373 | ig_md.flow_id_part_2=hdr.ipv4.dst_addr;//copy32_2.get({hdr.ipv4.dst_addr}); 374 | } 375 | action copy_flow_id_common_3_(){ 376 | //16+16bit ports 377 | //ig_md.flow_id_part_4[7:0]=hdr.ipv4.protocol; 378 | //ig_md.flow_id_part_4[8+12-1:8]=hdr.vlan.vlan_id; 379 | ig_md.flow_id_part_4=copy32_3.get({hdr.ipv4.protocol, hdr.vlan.vlan_id, 12w0});//12+8=20bit, remaining 12bit 380 | } 381 | action copy_flow_id_tcp(){ 382 | ig_md.flow_id_part_3[15:0]=hdr.tcp.src_port;//copy16_1.get({hdr.tcp.src_port}); 383 | ig_md.flow_id_part_3[31:16]=hdr.tcp.dst_port;//copy16_2.get({hdr.tcp.dst_port}); 384 | } 385 | action copy_flow_id_udp(){ 386 | ig_md.flow_id_part_3[15:0]=hdr.udp.src_port;//copy16_3.get({hdr.udp.src_port}); 387 | ig_md.flow_id_part_3[31:16]=hdr.udp.dst_port;//copy16_4.get({hdr.udp.dst_port}); 388 | } 389 | action copy_flow_id_unknown(){ 390 | ig_md.flow_id_part_3=0; 391 | } 392 | 393 | @stage(0) 394 | _OAT(copy_flow_id_common_1_) 395 | @stage(0) 396 | _OAT(copy_flow_id_common_2_) 397 | @stage(0) 398 | _OAT(copy_flow_id_common_3_) 399 | 400 | // == Calculate array indices for array access 401 | 402 | Hash>(HashAlgorithm_t.CRC16, CRCPolynomial>(16w0x8005,false,false,false,0,0)) hash1; 403 | Hash>(HashAlgorithm_t.CRC16, CRCPolynomial>(16w0x3D65,false,false,false,0,0)) hash2; 404 | //Hash>(HashAlgorithm_t.CRC32) hash3; 405 | //possible polynomials in standards: 406 | //0x8005,0x0589,0x3D65,0x1021,0x8BB7,0xA097 407 | 408 | action get_hashed_locations_1_(){ 409 | ig_md.stage_1_loc=(bit<14>) hash1.get({ 410 | ig_md.hash_seed_1, 411 | ig_md.flow_id_part_1, 412 | // 3w0, 413 | ig_md.flow_id_part_2, 414 | // 3w0, 415 | ig_md.flow_id_part_3, 416 | ig_md.flow_id_part_4 417 | }); 418 | } 419 | action get_hashed_locations_2_(){ 420 | ig_md.stage_2_loc=(bit<14>) hash2.get({ 421 | ig_md.hash_seed_2, 422 | ig_md.flow_id_part_1, 423 | // 2w0, 424 | ig_md.flow_id_part_2, 425 | // 2w0, 426 | ig_md.flow_id_part_3, 427 | // 1w0, 428 | ig_md.flow_id_part_4 429 | }); 430 | } 431 | 432 | 433 | @stage(1) 434 | _OAT(get_hashed_locations_1_) 435 | //this can be later... 436 | _OAT(get_hashed_locations_2_) 437 | 438 | action init_hash_seed(bit<3> v1, bit<5> v2, bit<7> v3){ 439 | ig_md.hash_seed_1=v1; 440 | ig_md.hash_seed_2=v2; 441 | } 442 | table tb_init_hash_seed { 443 | actions = { 444 | init_hash_seed; 445 | } 446 | default_action = init_hash_seed(3w2,5w17,7w71); 447 | } 448 | //enables re-seeding from control plane 449 | 450 | 451 | // == Register arrays for the stateful data structure 452 | 453 | Register,_>(32w16384) reg_flowid_1_1_R; 454 | Register,_>(32w16384) reg_flowid_1_2_R; 455 | Register,_>(32w16384) reg_flowid_1_3_R; 456 | Register,_>(32w16384) reg_flowid_1_4_R; 457 | Register,_>(32w16384) reg_counter_1_R; 458 | Register,_>(32w16384) reg_flowid_2_1_R; 459 | Register,_>(32w16384) reg_flowid_2_2_R; 460 | Register,_>(32w16384) reg_flowid_2_3_R; 461 | Register,_>(32w16384) reg_flowid_2_4_R; 462 | Register,_>(32w16384) reg_counter_2_R; 463 | 464 | 465 | // Define read/write actions for each flowID array 466 | #define RegAct_FlowID(st,pi) \ 467 | RegisterAction, _, bit<8>>(reg_flowid_## st ##_## pi ##_R) stage_## st ##_fid_match_## pi ##_RA= { \ 468 | void apply(inout bit<32> value, out bit<8> rv) { \ 469 | rv = 0; \ 470 | bit<32> in_value; \ 471 | in_value = value; \ 472 | if(in_value==ig_md.flow_id_part_## pi ){ \ 473 | rv = 1;} \ 474 | } \ 475 | }; \ 476 | \ 477 | RegisterAction, _, bit<8>>(reg_flowid_## st ##_## pi ##_R) stage_## st ##_fid_write_## pi ##_RA= { \ 478 | void apply(inout bit<32> value, out bit<8> rv) { \ 479 | rv = 0; \ 480 | bit<32> in_value; \ 481 | in_value = value; \ 482 | value=ig_md.flow_id_part_ ## pi; \ 483 | } \ 484 | }; \ 485 | action exec_stage_## st ##_fid_match_## pi ##_(){ ig_md.fid_matched_## st ##_## pi=stage_## st ##_fid_match_## pi ##_RA.execute(ig_md.stage_## st ##_loc);} \ 486 | action exec_stage_## st ##_fid_write_## pi ##_(){ stage_## st ##_fid_write_## pi ##_RA.execute(ig_md.stage_## st ##_loc);} \ 487 | //done 488 | 489 | RegAct_FlowID(1,1) 490 | RegAct_FlowID(1,2) 491 | RegAct_FlowID(1,3) 492 | RegAct_FlowID(1,4) 493 | RegAct_FlowID(2,1) 494 | RegAct_FlowID(2,2) 495 | RegAct_FlowID(2,3) 496 | RegAct_FlowID(2,4) 497 | 498 | @stage(2) 499 | _OAT(exec_stage_1_fid_match_1_) 500 | @stage(2) 501 | _OAT(exec_stage_1_fid_write_1_) 502 | @stage(2) 503 | _OAT(exec_stage_1_fid_match_2_) 504 | @stage(2) 505 | _OAT(exec_stage_1_fid_write_2_) 506 | @stage(3) 507 | _OAT(exec_stage_1_fid_match_3_) 508 | @stage(3) 509 | _OAT(exec_stage_1_fid_write_3_) 510 | @stage(3) 511 | _OAT(exec_stage_1_fid_match_4_) 512 | @stage(3) 513 | _OAT(exec_stage_1_fid_write_4_) 514 | 515 | 516 | @stage(4) 517 | _OAT(exec_stage_2_fid_match_1_) 518 | @stage(4) 519 | _OAT(exec_stage_2_fid_write_1_) 520 | @stage(4) 521 | _OAT(exec_stage_2_fid_match_2_) 522 | @stage(4) 523 | _OAT(exec_stage_2_fid_write_2_) 524 | @stage(5) 525 | _OAT(exec_stage_2_fid_match_3_) 526 | @stage(5) 527 | _OAT(exec_stage_2_fid_write_3_) 528 | @stage(5) 529 | _OAT(exec_stage_2_fid_match_4_) 530 | @stage(5) 531 | _OAT(exec_stage_2_fid_write_4_) 532 | 533 | 534 | action set_matched_at_stage_1_(){ 535 | ig_md.matched_at_stage_1=true; 536 | } 537 | action set_matched_at_stage_2_(){ 538 | ig_md.matched_at_stage_2=true; 539 | } 540 | 541 | @stage(6) 542 | _OAT(set_matched_at_stage_1_) 543 | 544 | @stage(6) 545 | _OAT(set_matched_at_stage_2_) 546 | 547 | // Define stateful actions for matching flow ID 548 | #define RegAct_Counter(st) \ 549 | RegisterAction, _, bit<32>>(reg_counter_## st ##_R) stage_## st ##_counter_read = { \ 550 | void apply(inout bit<32> value, out bit<32> rv) { \ 551 | rv = 0; \ 552 | bit<32> in_value; \ 553 | in_value = value; \ 554 | rv = value; \ 555 | } \ 556 | }; \ 557 | action exec_stage_## st ##_counter_read(){ ig_md.counter_read_## st =stage_## st ##_counter_read.execute(ig_md.stage_## st ##_loc);} \ 558 | RegisterAction, _, bit<32>>(reg_counter_## st ##_R) stage_## st ##_counter_incr = { \ 559 | void apply(inout bit<32> value, out bit<32> rv) { \ 560 | rv = 0; \ 561 | bit<32> in_value; \ 562 | in_value = value; \ 563 | value = in_value+1; \ 564 | rv = value; \ 565 | } \ 566 | }; \ 567 | action exec_stage_## st ##_counter_incr(){ ig_md.counter_read_## st =stage_## st ##_counter_incr.execute(ig_md.stage_## st ##_loc);} \ 568 | //done 569 | 570 | RegAct_Counter(1) 571 | RegAct_Counter(2) 572 | 573 | // @stage(7) 574 | _OAT(exec_stage_1_counter_read) 575 | _OAT(exec_stage_1_counter_incr) 576 | 577 | // @stage(7) 578 | _OAT(exec_stage_2_counter_read) 579 | _OAT(exec_stage_2_counter_incr) 580 | 581 | // == Randomization, for running Probabilistic Recirculation 582 | 583 | Random>() rng1; 584 | Random>() rng2; 585 | action get_randomness_1_(){ 586 | ig_md.entropy_long=rng1.get(); 587 | } 588 | action get_randomness_2_(){ 589 | ig_md.entropy_short=rng2.get(); 590 | } 591 | 592 | // @stage(8) 593 | _OAT(get_randomness_1_) 594 | // @stage(8) 595 | _OAT(get_randomness_2_) 596 | 597 | // Find out which stage has the minimum count. 598 | // We use a 32-bit register here for comparing two 32bit numbers 599 | Register,_>(32w32) dummy_reg1; 600 | Register,_>(32w32) dummy_reg2; 601 | RegisterAction, _, bit<32>>(dummy_reg1) get_min_stage = { 602 | void apply(inout bit<32> value, out bit<32> rv) { 603 | rv = 0; 604 | bit<32> in_value; 605 | in_value = value; 606 | if(ig_md.diff>0x7fffff){//negative 607 | value=1; 608 | } 609 | else{ 610 | value=2; 611 | } 612 | if((bool) 1) 613 | rv=value; 614 | } 615 | }; 616 | action exec_get_min_stage() { 617 | ig_md.resubmit_data_write.min_stage=(bit<8>) get_min_stage.execute(0); 618 | } 619 | // @stage(9) 620 | _OAT(exec_get_min_stage) 621 | 622 | action clear_resubmit_flag(){ 623 | ig_intr_dprsr_md.resubmit_type = 0; 624 | } 625 | action clone_and_recirc_replace_entry(){ 626 | //trigger resubmit 627 | ig_intr_dprsr_md.resubmit_type = 1; 628 | } 629 | 630 | // Approximate coin flip! See our paper for discussion of 1.125-approximation to coin flip probability. 631 | // Section IV.D @ https://doi.org/10.1109/TNET.2020.2982739 632 | // @stage(11) 633 | table better_approximation { 634 | // Goal: recirculate using probability 1/(2^x*T) nearest to 1/(carry_min+1), x between [1..63], T between [8..15] 635 | actions = { 636 | NoAction(); 637 | clone_and_recirc_replace_entry(); 638 | } 639 | key = { 640 | ig_md.c_min: ternary; 641 | ig_md.entropy_long: ternary; 642 | ig_md.entropy_short: range; 643 | } 644 | size = 512; 645 | default_action = NoAction(); 646 | const entries = { 647 | #include "entries_better_32.p4inc" 648 | } 649 | } 650 | 651 | bit<32> counter0 = 0; 652 | bit<32> counter1 = 0; 653 | table threshold0 { 654 | key = { 655 | ig_intr_md.resubmit_flag : ternary; 656 | ig_md.resubmit_data_read.min_stage : ternary; 657 | ig_md.matched_at_stage_1 : ternary; 658 | ig_md.counter_read_1[19:0] : range; 659 | } 660 | actions = { 661 | generate_digest; 662 | NoAction; 663 | } 664 | default_action = NoAction(); 665 | size = 1; 666 | } 667 | 668 | table threshold1 { 669 | key = { 670 | ig_intr_md.resubmit_flag : ternary; 671 | ig_md.resubmit_data_read.min_stage : ternary; 672 | ig_md.matched_at_stage_1 : ternary; 673 | ig_md.counter_read_2[19:0] : range; 674 | } 675 | actions = { 676 | generate_digest; 677 | NoAction; 678 | } 679 | default_action = NoAction(); 680 | size = 1; 681 | } 682 | 683 | #undef _OAT 684 | #define _OAT(act) tb_##act.apply() 685 | apply { 686 | //for debugging 687 | // route_to_64(); 688 | if(!hdr.ipv4.isValid()) { 689 | drop(); 690 | } 691 | 692 | ipv4_forward.apply(); 693 | 694 | // === Preprocessing === 695 | // Get flow ID 696 | _OAT(copy_flow_id_common_1_); 697 | _OAT(copy_flow_id_common_2_); 698 | _OAT(copy_flow_id_common_3_); 699 | 700 | if(hdr.tcp.isValid()){copy_flow_id_tcp();} 701 | else if(hdr.udp.isValid()){copy_flow_id_udp();} 702 | else {copy_flow_id_unknown();} 703 | 704 | // optional hash re-seeding 705 | // tb_init_hash_seed.apply(); 706 | 707 | // Get hashed locations based on flow ID 708 | _OAT(get_hashed_locations_1_); 709 | _OAT(get_hashed_locations_2_); 710 | 711 | 712 | // === Start of PRECISION stage counter logic === 713 | 714 | 715 | // For normal packets, for each stage, we match flow ID, then increment or compute carry_min 716 | // to simplify program logic, we ignore a special case, where both slots are the same flow ID. 717 | // For resubmitted packet, just do write FID + INCR at the right stage. 718 | 719 | bool is_resubmitted=(bool) ig_intr_md.resubmit_flag; 720 | bit<8> resubmitted_min_stage=ig_md.resubmit_data_read.min_stage; 721 | 722 | // = Stage 1 match = 723 | 724 | if(!is_resubmitted){ 725 | _OAT(exec_stage_1_fid_match_1_); 726 | }else if(is_resubmitted && resubmitted_min_stage==1){ 727 | _OAT(exec_stage_1_fid_write_1_); 728 | } 729 | if(!is_resubmitted){ 730 | _OAT(exec_stage_1_fid_match_2_); 731 | }else if(is_resubmitted && resubmitted_min_stage==1){ 732 | _OAT(exec_stage_1_fid_write_2_); 733 | } 734 | 735 | if(!is_resubmitted){ 736 | _OAT(exec_stage_1_fid_match_3_); 737 | }else if(is_resubmitted && resubmitted_min_stage==1){ 738 | _OAT(exec_stage_1_fid_write_3_); 739 | } 740 | if(!is_resubmitted){ 741 | _OAT(exec_stage_1_fid_match_4_); 742 | }else if(is_resubmitted && resubmitted_min_stage==1){ 743 | _OAT(exec_stage_1_fid_write_4_); 744 | } 745 | 746 | //have a boolean alias, for immediate use in gateway table controlling stage 2 fid match 747 | bool matched_at_stage_1=((ig_md.fid_matched_1_1!=0) && 748 | (ig_md.fid_matched_1_2!=0) && 749 | (ig_md.fid_matched_1_3!=0) && 750 | (ig_md.fid_matched_1_4!=0)); 751 | //also have a boolean phv value, for longer gateway matches 752 | if(matched_at_stage_1) 753 | { 754 | _OAT(set_matched_at_stage_1_); 755 | } 756 | 757 | // = Stage 1 incr = 758 | if(is_resubmitted && resubmitted_min_stage==1){ 759 | _OAT(exec_stage_1_counter_incr); 760 | }else if(ig_md.matched_at_stage_1){ 761 | _OAT(exec_stage_1_counter_incr); 762 | }else{ 763 | _OAT(exec_stage_1_counter_read); 764 | } 765 | 766 | threshold0.apply(); 767 | 768 | // = Stage 2 match = 769 | 770 | if(!is_resubmitted && !matched_at_stage_1){ 771 | _OAT(exec_stage_2_fid_match_1_); 772 | }else if(is_resubmitted && resubmitted_min_stage==2){ 773 | _OAT(exec_stage_2_fid_write_1_); 774 | } 775 | if(!is_resubmitted && !matched_at_stage_1){ 776 | _OAT(exec_stage_2_fid_match_2_); 777 | }else if(is_resubmitted && resubmitted_min_stage==2){ 778 | _OAT(exec_stage_2_fid_write_2_); 779 | } 780 | 781 | if(!is_resubmitted && !matched_at_stage_1){ 782 | _OAT(exec_stage_2_fid_match_3_); 783 | }else if(is_resubmitted && resubmitted_min_stage==2){ 784 | _OAT(exec_stage_2_fid_write_3_); 785 | } 786 | if(!is_resubmitted && !matched_at_stage_1){ 787 | _OAT(exec_stage_2_fid_match_4_); 788 | }else if(is_resubmitted && resubmitted_min_stage==2){ 789 | _OAT(exec_stage_2_fid_write_4_); 790 | } 791 | 792 | if((ig_md.fid_matched_2_1!=0) && 793 | (ig_md.fid_matched_2_2!=0) && 794 | (ig_md.fid_matched_2_3!=0) && 795 | (ig_md.fid_matched_2_4!=0)) 796 | { 797 | _OAT(set_matched_at_stage_2_); 798 | } 799 | 800 | // = Stage 2 incr = 801 | if(is_resubmitted && resubmitted_min_stage==2){ 802 | _OAT(exec_stage_2_counter_incr); 803 | }else if(ig_md.matched_at_stage_2){ 804 | _OAT(exec_stage_2_counter_incr); 805 | }else{ 806 | _OAT(exec_stage_2_counter_read); 807 | } 808 | 809 | threshold1.apply(); 810 | 811 | // Always compute min_stage and c_min, even it's not useful 812 | ig_md.diff= ig_md.counter_read_1 - ig_md.counter_read_2; 813 | ig_md.resubmit_data_write.setValid(); 814 | // _OAT(exec_get_min_stage); 815 | 816 | // ig_md.c_min=min(ig_md.counter_read_1, ig_md.counter_read_2); 817 | if(ig_md.resubmit_data_write.min_stage==1){ 818 | ig_md.c_min=ig_md.counter_read_1; 819 | }else if(ig_md.resubmit_data_write.min_stage==2){ 820 | ig_md.c_min=ig_md.counter_read_2; 821 | } 822 | 823 | // prepare entropy 824 | _OAT(get_randomness_1_); 825 | _OAT(get_randomness_2_); 826 | 827 | clear_resubmit_flag(); 828 | 829 | // === If none matched: choose your min stage, for recirculation (actually resubmit) === 830 | if(!is_resubmitted && !ig_md.matched_at_stage_1 && !ig_md.matched_at_stage_2){ 831 | //none matched 832 | //prepare for resubmit! 833 | better_approximation.apply(); 834 | } 835 | else if(is_resubmitted){ 836 | // finished second pipeline pass. route as normal. 837 | } 838 | else if(ig_md.matched_at_stage_1){ 839 | // matched with counter. 840 | }else if(ig_md.matched_at_stage_2){ 841 | // matched with counter. 842 | } 843 | 844 | 845 | 846 | if(ig_md.matched_at_stage_1){ 847 | hdr.ethernet.dst_addr=(bit<48>)ig_md.counter_read_1; 848 | }else if(ig_md.matched_at_stage_2){ 849 | hdr.ethernet.dst_addr=(bit<48>)ig_md.counter_read_2; 850 | }else{ 851 | hdr.ethernet.dst_addr=0; 852 | } 853 | } 854 | } 855 | 856 | control SwitchEgress( 857 | inout header_t hdr, 858 | inout eg_metadata_t eg_md, 859 | in egress_intrinsic_metadata_t eg_intr_md, 860 | in egress_intrinsic_metadata_from_parser_t eg_intr_md_from_prsr, 861 | inout egress_intrinsic_metadata_for_deparser_t ig_intr_dprs_md, 862 | inout egress_intrinsic_metadata_for_output_port_t eg_intr_oport_md) { 863 | apply { 864 | } 865 | } 866 | 867 | 868 | 869 | Pipeline(SwitchIngressParser(), 870 | SwitchIngress(), 871 | SwitchIngressDeparser(), 872 | SwitchEgressParser(), 873 | SwitchEgress(), 874 | SwitchEgressDeparser() 875 | ) pipe; 876 | 877 | Switch(pipe) main; 878 | 879 | --------------------------------------------------------------------------------