├── common ├── conf │ ├── utils.mk │ ├── subdirs.mk │ ├── demo.mk │ ├── simplelib.mk │ ├── programmer.mk │ ├── armgcc.mk │ ├── program.mk │ └── gcc.ld ├── Makefile ├── minilibc │ ├── Makefile │ ├── libc.h │ └── libc.c ├── cmsis │ ├── Makefile │ ├── README_bug.txt │ └── core_cm3_psoc5.h ├── hw │ ├── Makefile │ ├── lcd_hw.h │ ├── lcd.h │ ├── lcd_hd44780.h │ ├── lcd_printf.c │ └── lcd.c └── psoc │ ├── Makefile │ ├── psoc_support.c │ ├── cmsis_alt.c │ ├── psoc5.h │ ├── cmsis_alt.h │ ├── psoc_support.h │ ├── delay.s │ ├── delay_funcs.c │ └── psoc_regmacro.h ├── demo1 ├── main.c ├── systeminit.c ├── startup.c ├── README.txt ├── Makefile ├── gcc.ld └── startup_ARMCM3.S ├── demo2b ├── config.hex ├── startup.c ├── Makefile ├── README.txt ├── config.h ├── main.c ├── systeminit.c ├── app_config.c └── startup_ARMCM3.S ├── demo2a ├── startup.c ├── Makefile ├── README.txt ├── config.h ├── main.c ├── systeminit.c └── startup_ARMCM3.S ├── demo2c ├── startup.c ├── config.h ├── Makefile ├── config.conf ├── README.txt ├── main.c ├── systeminit.c ├── app_config.c └── startup_ARMCM3.S ├── demo2d ├── startup.c ├── README.txt ├── config.h ├── Makefile ├── config.conf ├── main.c ├── systeminit.c ├── app_config.c └── startup_ARMCM3.S ├── demo3a ├── startup.c ├── config.h ├── README.txt ├── Makefile ├── config.conf ├── main.c ├── systeminit.c ├── gcc_arm.ld.ORIG ├── app_config.c ├── gcc.ld └── startup_ARMCM3.S ├── demo3b ├── startup.c ├── config.h ├── README.txt ├── Makefile ├── config.conf ├── main.c ├── systeminit.c ├── app_config.c ├── gcc.ld └── startup_ARMCM3.c ├── Makefile ├── COPYING.txt └── README.md /common/conf/utils.mk: -------------------------------------------------------------------------------- 1 | CP = cp 2 | -------------------------------------------------------------------------------- /demo1/main.c: -------------------------------------------------------------------------------- 1 | void main(void) 2 | { 3 | 4 | // main shouldn't return 5 | for(;;) {} 6 | } 7 | -------------------------------------------------------------------------------- /demo2b/config.hex: -------------------------------------------------------------------------------- 1 | :200000000152004004010000060001060600000000000000007F7F00000000000000000037 2 | :00000001FF 3 | -------------------------------------------------------------------------------- /common/Makefile: -------------------------------------------------------------------------------- 1 | include conf/subdirs.mk 2 | 3 | SUBDIRS = hw minilibc psoc cmsis 4 | 5 | clean:: 6 | $(RM) libs/* 7 | -------------------------------------------------------------------------------- /demo1/systeminit.c: -------------------------------------------------------------------------------- 1 | void SystemInit(void) 2 | { 3 | // really need to configure PSoC clock here as a minimum 4 | } 5 | -------------------------------------------------------------------------------- /demo1/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /demo2a/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /demo2b/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /demo2c/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /demo2d/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /demo3a/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /demo3b/startup.c: -------------------------------------------------------------------------------- 1 | extern void main(void); 2 | 3 | void _start(void) 4 | { 5 | main(); 6 | for(;;) {} 7 | } 8 | -------------------------------------------------------------------------------- /common/minilibc/Makefile: -------------------------------------------------------------------------------- 1 | LIBNAME = libc.a 2 | INCS = -I . 3 | OBJS = libc.o 4 | INSTALL_DIR = ../libs 5 | 6 | include ../conf/simplelib.mk 7 | -------------------------------------------------------------------------------- /common/cmsis/Makefile: -------------------------------------------------------------------------------- 1 | LIBNAME = libcmsis.a 2 | INCS = -I . 3 | OBJS = core_cm3.o 4 | INSTALL_DIR = ../libs 5 | 6 | include ../conf/simplelib.mk 7 | -------------------------------------------------------------------------------- /common/hw/Makefile: -------------------------------------------------------------------------------- 1 | LIBNAME = libhw.a 2 | INCS = -I . -I ../psoc 3 | OBJS = lcd.o lcd_printf.o 4 | INSTALL_DIR = ../libs 5 | 6 | include ../conf/simplelib.mk 7 | -------------------------------------------------------------------------------- /common/psoc/Makefile: -------------------------------------------------------------------------------- 1 | LIBNAME = libpsoc.a 2 | INCS = -I . 3 | OBJS = delay.o delay_funcs.o psoc_support.o cmsis_alt.o 4 | INSTALL_DIR = ../libs 5 | 6 | include ../conf/simplelib.mk 7 | -------------------------------------------------------------------------------- /demo2b/Makefile: -------------------------------------------------------------------------------- 1 | #DEVICE_NAME = PSOC5LP-xxx 2 | CONFIG_HEX_PATH = config.hex 3 | 4 | OBJS = main.o startup_ARMCM3.o startup.o systeminit.o app_config.o 5 | 6 | include ../common/conf/demo.mk 7 | -------------------------------------------------------------------------------- /demo2a/Makefile: -------------------------------------------------------------------------------- 1 | OBJS = main.o startup_ARMCM3.o startup.o systeminit.o 2 | 3 | #PROG = prog 4 | #DEVICE_NAME = PSOC5LP-xxx 5 | #CONFIG_HEX_PATH = config.hex 6 | 7 | include ../common/conf/demo.mk 8 | -------------------------------------------------------------------------------- /common/conf/subdirs.mk: -------------------------------------------------------------------------------- 1 | SUBDIRS ?= 2 | 3 | .PHONY: all install clean 4 | 5 | all install clean:: 6 | @for dir in $(SUBDIRS); do \ 7 | echo Make $@ in subdir: $$dir; \ 8 | $(MAKE) -C $$dir $(DEFS) $@; \ 9 | done 10 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | FILEDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 2 | export PSOC_PROG_DIR = $(FILEDIR)/../PSOC_programmer 3 | 4 | include common/conf/subdirs.mk 5 | 6 | DEMOS = demo1 demo2a demo2b demo2c demo2d demo3a demo3b 7 | 8 | SUBDIRS = common $(DEMOS) 9 | -------------------------------------------------------------------------------- /common/psoc/psoc_support.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "psoc_regmacro.h" 5 | #include "psoc_registers.h" 6 | 7 | #include "psoc_support.h" 8 | 9 | 10 | void soft_reset(void) 11 | { 12 | REG_SET_8(REG_RESET_CR2, 0x01); 13 | } 14 | 15 | void halt(void) 16 | { 17 | __asm("BKPT 0x01"); 18 | } 19 | -------------------------------------------------------------------------------- /common/conf/demo.mk: -------------------------------------------------------------------------------- 1 | FILEDIR := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | #Requires following variables: 4 | # OBJS = 5 | PROG ?= demo 6 | 7 | include $(FILEDIR)program.mk 8 | 9 | DEVICE_NAME ?= PSOC5LP-xxx 10 | 11 | COMMON_INC_DIRS ?= hw psoc minilibc 12 | 13 | INCS += $(COMMON_INC_DIRS:%=-I$(FILEDIR)../%) 14 | LIBS += -L $(FILEDIR)../libs -lhw -lpsoc -lc 15 | 16 | -------------------------------------------------------------------------------- /common/psoc/cmsis_alt.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "psoc_support.h" 4 | 5 | 6 | // We need the included functionality. We don't need to follow the Cypress names 7 | // and given these funcs are omitted from CMSISv1.3 BUT added to later CMSIS 8 | // versions we might as well use the CMSIS function names. 9 | 10 | void disable_irq(void) 11 | { 12 | __asm("CPSID i"); 13 | } 14 | 15 | void enable_irq(void) 16 | { 17 | __asm("CPSIE i"); 18 | } 19 | -------------------------------------------------------------------------------- /common/conf/simplelib.mk: -------------------------------------------------------------------------------- 1 | FILEDIR := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | include $(FILEDIR)armgcc.mk 4 | include $(FILEDIR)utils.mk 5 | 6 | 7 | # Required vars: 8 | # LIBNAME = lblah.a 9 | # INCS = -I . -I ... 10 | # OBJS = ... 11 | # INSTALL_DIR = ... 12 | 13 | 14 | all: $(LIBNAME) install 15 | 16 | $(LIBNAME): $(OBJS) 17 | $(RM) $@ 18 | $(AR) -rs $@ $(OBJS) 19 | 20 | install: 21 | $(RM) $(INSTALL_DIR)/$(LIBNAME) 22 | $(CP) $(LIBNAME) $(INSTALL_DIR) 23 | 24 | clean:: 25 | $(RM) *.o $(LIBNAME) 26 | -------------------------------------------------------------------------------- /common/cmsis/README_bug.txt: -------------------------------------------------------------------------------- 1 | The CMSIS library code (1.3 and possibly 2.0) has a bug in it under at least the GCC compiler 2 | When compiling under GCC we get the assembler errors: 3 | 4 | Error: registers may not be the same -- `strexb r3,r2,[r3]' 5 | Error: registers may not be the same -- `strexh r3,r2,[r3]' 6 | 7 | It is illegal on this architecture to have the three strex registers identical. 8 | This has been fixed by using "=&r" rather than "=r". 9 | The & ensures the register is not the same as that of the source operands. 10 | 11 | -------------------------------------------------------------------------------- /common/conf/programmer.mk: -------------------------------------------------------------------------------- 1 | # Incoming Variables: 2 | # CONFIG_HEX_PATH (optional) 3 | 4 | UTILSPATH = $(PSOC_PROG_DIR) 5 | #UTILSPATH = ~/projects/PSoC/programmer 6 | 7 | MERGEHEX = $(UTILSPATH)/bin/mergehex -nm $(UTILSPATH)/config/nm.hex 8 | BURNCMD = $(UTILSPATH)/bin/prog -C $(UTILSPATH)/config -d $(DEVICE_NAME) program 9 | 10 | ifdef CONFIG_HEX_PATH 11 | CONFIG_HEX = -d $(CONFIG_HEX_PATH) 12 | endif 13 | 14 | %.hex: %.elf 15 | $(OBJCOPY) -O ihex $< $*_tmp.hex 16 | $(MERGEHEX) -c $*_tmp.hex $(CONFIG_HEX) -o $@ 17 | 18 | %.bin: %.elf 19 | $(OBJCOPY) -O binary $< $@ 20 | -------------------------------------------------------------------------------- /demo2a/README.txt: -------------------------------------------------------------------------------- 1 | Demo 2a - LCD and LED 2 | --------------------- 3 | This demo flashes LED2 at 0.5Hz and turns on LED1 whilst SW2 is pressed (P6_1) 4 | 5 | Key points: 6 | * Minimal system setup 7 | * No config.hex (ie no config data) 8 | * Busy wait to drive LED 9 | 10 | Code Dependencies: 11 | * Essentially no Cypress code 12 | * No CMSIS 13 | 14 | Hardware Setup: 15 | * Requires CYC8KIT-050 16 | 17 | * Set up the CYC8KIT-050 as folows 18 | - Two wires: 19 | P6_0 (connector P9) to LED1 (connecor P6) 20 | P6_6 (connector P9) to LED2 (connecor P6) 21 | - Connect 2 line LCD 22 | -------------------------------------------------------------------------------- /common/conf/armgcc.mk: -------------------------------------------------------------------------------- 1 | FILEDIR := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | ARCH=arm-none-eabi- 4 | 5 | CC=$(ARCH)gcc 6 | LD=$(ARCH)ld 7 | AS=$(ARCH)as 8 | AR=$(ARCH)ar 9 | CPP=$(ARCH)cpp 10 | RANLIB=$(ARCH)ranlib 11 | STRIP=$(ARCH)strip 12 | OBJCOPY=$(ARCH)objcopy 13 | OBJDUMP=$(ARCH)objdump 14 | NM=$(ARCH)nm 15 | 16 | # CDEFS= -D__STARTUP_CLEAR_BSS -nostdlib -nostartupfiles 17 | # CDEFS= -D__STARTUP_CLEAR_BSS 18 | CDEFS= 19 | ASDEFS= 20 | ARCHFLAGS = -mcpu=cortex-m3 -march=armv7-m -mthumb -mthumb-interwork 21 | CFLAGS = $(ARCHFLAGS) $(INCS) $(CDEFS) $(DEFS) 22 | ASFLAGS = $(ARCHFLAGS) $(INCS) $(ASDEFS) $(DEFS) 23 | LDSCRIPT ?= $(FILEDIR)gcc.ld 24 | -------------------------------------------------------------------------------- /common/conf/program.mk: -------------------------------------------------------------------------------- 1 | FILEDIR := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | include $(FILEDIR)armgcc.mk 4 | include $(FILEDIR)programmer.mk 5 | 6 | .PHONY: all map dump dis burn clean 7 | 8 | OUTPUTS = $(PROG).hex $(PROG)_tmp.hex $(PROG).elf $(PROG).bin 9 | 10 | all:: $(PROG).elf $(PROG).hex $(PROG).bin 11 | 12 | $(PROG).elf: $(OBJS) 13 | $(LD) -T $(LDSCRIPT) $(OBJS) $(LIBS) -o $@ 14 | 15 | map: $(OBJS) 16 | $(LD) -M -T $(LDSCRIPT) $(OBJS) $(LIBS) 17 | 18 | dump: $(PROG).elf 19 | $(OBJDUMP) -x $< 20 | #$(OBJDUMP) -sph $< 21 | 22 | dis: $(PROG).elf 23 | $(OBJDUMP) -d $< 24 | 25 | burn: $(PROG).hex 26 | $(BURNCMD) $< 27 | 28 | clean:: 29 | rm -f *.o $(OUTPUTS) 30 | -------------------------------------------------------------------------------- /demo1/README.txt: -------------------------------------------------------------------------------- 1 | Demo1 2 | ----- 3 | 4 | Read: http://dfusion.com.au/wiki/tiki-index.php?page=PSoC5+bare+metal 5 | 6 | Download an ARM GCC Cross compiler if you don't already have one. 7 | https://launchpad.net/gcc-arm-embedded/+download 8 | 9 | Put the cross compiler into your PATH - something like: 10 | PATH=~/software/arm-gnu-baremetal-compiler/gcc-arm-none-eabi-4_8-2014q2/bin:$PATH 11 | 12 | Run make to compile this app. 13 | 14 | Note (after all your effort) the app does absolutely nothing - it's an empty app to understand the compile and link process. 15 | 16 | Note this makefile is all-in one so you can see the workings and hack it simply. Later demos use the included makefile framework. 17 | 18 | -------------------------------------------------------------------------------- /demo1/Makefile: -------------------------------------------------------------------------------- 1 | PROG = demo 2 | 3 | all: $(PROG) 4 | 5 | ARCH=arm-none-eabi- 6 | 7 | CC=$(ARCH)gcc 8 | LD=$(ARCH)ld 9 | AS=$(ARCH)as 10 | AR=$(ARCH)ar 11 | RANLIB=$(ARCH)ranlib 12 | STRIP=$(ARCH)strip 13 | 14 | INCS = -I . 15 | # CDEFS= -D__STARTUP_CLEAR_BSS -nostdlib -nostartupfiles 16 | # CDEFS= -D__STARTUP_CLEAR_BSS 17 | CDEFS= 18 | ASDEFS= 19 | ARCHFLAGS = -mcpu=cortex-m3 -march=armv7-m -mthumb -mthumb-interwork 20 | CFLAGS = $(ARCHFLAGS) $(INCS) $(CDEFS) $(DEFS) 21 | ASFLAGS = $(ARCHFLAGS) $(INCS) $(ASDEFS) $(DEFS) 22 | LDSCRIPT = -T gcc.ld 23 | 24 | OBJS = main.o startup.o systeminit.o startup_ARMCM3.o 25 | 26 | $(PROG): $(OBJS) gcc.ld 27 | $(LD) $(LDSCRIPT) $(OBJS) -o $@ 28 | 29 | clean: 30 | $(RM) *.o $(PROG) 31 | -------------------------------------------------------------------------------- /demo2c/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | 5 | // CLOCK SETUP 6 | // =========== 7 | #define CONFIG_SYSTEM_CLOCK_MHZ 63 8 | #define CONFIG_SYSTEM_CLOCK_HZ (CONFIG_SYSTEM_CLOCK_MHZ * 1000000) 9 | 10 | // Next two must match 11 | #define CONFIG_IMO_FREQ_MHZ 3 12 | #define CONFIG_IMO_FREQ_ENUM FASTCLK_IMO__F_RANGE__3MHz 13 | 14 | #define CONFIG_FASTCLK_PLL_P CONFIG_SYSTEM_CLOCK_MHZ 15 | #define CONFIG_FASTCLK_PLL_Q 0x02 16 | 17 | 18 | // OTHER SETUP 19 | // =========== 20 | // Note: delay_cycles() assumes instruction cache enabled. Refer source. 21 | #define CONFIG_INSTRUCTION_CACHE_ENABLED 1 22 | #define CONFIG_NVIC_PRIORITY_GROUP NVIC_APPLN_INTR__PRIGROUP__3_5 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /demo2d/README.txt: -------------------------------------------------------------------------------- 1 | Demo 2d - LCD and LED 2 | --------------------- 3 | This demo flashes LED2 at 0.5Hz and turns on LED1 whilst SW2 is pressed (P6_1) 4 | 5 | Differences from demo 2c: 6 | * Uses CMSIS 7 | 8 | Key points: 9 | * Minimal system setup 10 | * Uses enhanced config format (see Demo 2c) 11 | * Busy wait to drive LED 12 | 13 | Code Dependencies: 14 | * Essentially no Cypress code 15 | * Use CMSIS v1.3 (provided with PSoC) for core functions 16 | 17 | Hardware Setup: 18 | * Requires CYC8KIT-050 19 | 20 | * Set up the CYC8KIT-050 as folows 21 | - Two wires: 22 | P6_0 (connector P9) to LED1 (connecor P6) 23 | P6_6 (connector P9) to LED2 (connecor P6) 24 | - Connect 2 line LCD 25 | 26 | -------------------------------------------------------------------------------- /demo2d/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | 5 | // CLOCK SETUP 6 | // =========== 7 | #define CONFIG_SYSTEM_CLOCK_MHZ 63 8 | #define CONFIG_SYSTEM_CLOCK_HZ (CONFIG_SYSTEM_CLOCK_MHZ * 1000000) 9 | 10 | // Next two must match 11 | #define CONFIG_IMO_FREQ_MHZ 3 12 | #define CONFIG_IMO_FREQ_ENUM FASTCLK_IMO__F_RANGE__3MHz 13 | 14 | #define CONFIG_FASTCLK_PLL_P CONFIG_SYSTEM_CLOCK_MHZ 15 | #define CONFIG_FASTCLK_PLL_Q 0x02 16 | 17 | 18 | // OTHER SETUP 19 | // =========== 20 | // Note: delay_cycles() assumes instruction cache enabled. Refer source. 21 | #define CONFIG_INSTRUCTION_CACHE_ENABLED 1 22 | #define CONFIG_NVIC_PRIORITY_GROUP NVIC_APPLN_INTR__PRIGROUP__3_5 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /demo3a/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | 5 | // CLOCK SETUP 6 | // =========== 7 | #define CONFIG_SYSTEM_CLOCK_MHZ 63 8 | #define CONFIG_SYSTEM_CLOCK_HZ (CONFIG_SYSTEM_CLOCK_MHZ * 1000000) 9 | 10 | // Next two must match 11 | #define CONFIG_IMO_FREQ_MHZ 3 12 | #define CONFIG_IMO_FREQ_ENUM FASTCLK_IMO__F_RANGE__3MHz 13 | 14 | #define CONFIG_FASTCLK_PLL_P CONFIG_SYSTEM_CLOCK_MHZ 15 | #define CONFIG_FASTCLK_PLL_Q 0x02 16 | 17 | 18 | // OTHER SETUP 19 | // =========== 20 | // Note: delay_cycles() assumes instruction cache enabled. Refer source. 21 | #define CONFIG_INSTRUCTION_CACHE_ENABLED 1 22 | #define CONFIG_NVIC_PRIORITY_GROUP NVIC_APPLN_INTR__PRIGROUP__3_5 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /demo3b/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | 5 | // CLOCK SETUP 6 | // =========== 7 | #define CONFIG_SYSTEM_CLOCK_MHZ 63 8 | #define CONFIG_SYSTEM_CLOCK_HZ (CONFIG_SYSTEM_CLOCK_MHZ * 1000000) 9 | 10 | // Next two must match 11 | #define CONFIG_IMO_FREQ_MHZ 3 12 | #define CONFIG_IMO_FREQ_ENUM FASTCLK_IMO__F_RANGE__3MHz 13 | 14 | #define CONFIG_FASTCLK_PLL_P CONFIG_SYSTEM_CLOCK_MHZ 15 | #define CONFIG_FASTCLK_PLL_Q 0x02 16 | 17 | 18 | // OTHER SETUP 19 | // =========== 20 | // Note: delay_cycles() assumes instruction cache enabled. Refer source. 21 | #define CONFIG_INSTRUCTION_CACHE_ENABLED 1 22 | #define CONFIG_NVIC_PRIORITY_GROUP NVIC_APPLN_INTR__PRIGROUP__3_5 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /demo2a/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | #include "psoc_registers.h" 5 | 6 | 7 | // CLOCK SETUP 8 | // =========== 9 | #define CONFIG_SYSTEM_CLOCK_MHZ 63 10 | #define CONFIG_SYSTEM_CLOCK_HZ (CONFIG_SYSTEM_CLOCK_MHZ * 1000000) 11 | 12 | // Next two must match 13 | #define CONFIG_IMO_FREQ_MHZ 3 14 | #define CONFIG_IMO_FREQ_ENUM FASTCLK_IMO__F_RANGE__3MHz 15 | 16 | #define CONFIG_FASTCLK_PLL_P CONFIG_SYSTEM_CLOCK_MHZ 17 | #define CONFIG_FASTCLK_PLL_Q 0x02 18 | 19 | 20 | // OTHER SETUP 21 | // =========== 22 | // Note: delay_cycles() assumes instruction cache enabled. Refer source. 23 | #define CONFIG_INSTRUCTION_CACHE_ENABLED 1 24 | 25 | #define CONFIG_NVIC_PRIORITY_GROUP NVIC_APPLN_INTR__PRIGROUP__3_5 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /COPYING.txt: -------------------------------------------------------------------------------- 1 | All is published under GPL with the exception of libini. 2 | libini is published under the New BSD license. See the libini directory. 3 | 4 | Copyright (C) 2014 Kim Lester 5 | http://www.dfusion.com.au/ 6 | 7 | This Program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | This Program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this Program. If not, see . 19 | -------------------------------------------------------------------------------- /demo3b/README.txt: -------------------------------------------------------------------------------- 1 | Demo 3b - LCD and LED 2 | --------------------- 3 | This demo flashes LED2 at 0.5Hz and turns on LED1 whilst SW2 is pressed (P6_1) 4 | 5 | Differences from demo 3a: 6 | * Replace startup_ARMCM3.S with startup_ARMCM3.c 7 | 8 | Key points: 9 | * Minimal system setup 10 | * Uses enhanced config format (see Demo 2c/d) 11 | * Full gcc.ld (from ARM but modified) 12 | * Full startup_ARMCM3.c (from ARM but modified) 13 | * Sets up SystemTick Event and Handler 14 | * System goes to sleep between System clock (ms) ticks 15 | 16 | Code Dependencies: 17 | * Essentially no Cypress code 18 | * Use CMSIS v1.3 (provided with PSoC) for core functions 19 | 20 | Hardware Setup: 21 | * Requires CYC8KIT-050 22 | 23 | * Set up the CYC8KIT-050 as folows 24 | - Two wires: 25 | P6_0 (connector P9) to LED1 (connecor P6) 26 | P6_6 (connector P9) to LED2 (connecor P6) 27 | - Connect 2 line LCD 28 | -------------------------------------------------------------------------------- /common/psoc/psoc5.h: -------------------------------------------------------------------------------- 1 | #ifndef _PSOC_H 2 | 3 | /* 4 | Copyright (C) 2014 Kim Lester 5 | http://www.dfusion.com.au/ 6 | 7 | This Program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | This Program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this Program. If not, see . 19 | */ 20 | 21 | #include "psoc_registers.h" 22 | #include "psoc_regmacro.h" 23 | #include "psoc_support.h" 24 | 25 | #define _PSOC_H 26 | #endif 27 | -------------------------------------------------------------------------------- /demo3a/README.txt: -------------------------------------------------------------------------------- 1 | Demo 3a - LCD and LED 2 | --------------------- 3 | This demo flashes LED2 at 0.5Hz and turns on LED1 whilst SW2 is pressed (P6_1) 4 | 5 | Differences from demo 2d: 6 | * Sets up SystemTick Event and Handler and sleeps between ticks 7 | * Full gcc.ld (from ARM but modified) 8 | * Full startup_ARMCM3.S (from ARM but modified) 9 | 10 | Key points: 11 | * Minimal system setup 12 | * Uses enhanced config format (see Demo 2c/d) 13 | * Full gcc.ld (from ARM but modified) 14 | * Full startup_ARMCM3.S (from ARM but modified) 15 | * Sets up SystemTick Event and Handler 16 | * System goes to sleep between System clock (ms) ticks 17 | 18 | Code Dependencies: 19 | * Essentially no Cypress code 20 | * Use CMSIS v1.3 (provided with PSoC) for core functions 21 | 22 | Hardware Setup: 23 | * Requires CYC8KIT-050 24 | 25 | * Set up the CYC8KIT-050 as folows 26 | - Two wires: 27 | P6_0 (connector P9) to LED1 (connecor P6) 28 | P6_6 (connector P9) to LED2 (connecor P6) 29 | - Connect 2 line LCD 30 | -------------------------------------------------------------------------------- /demo2c/Makefile: -------------------------------------------------------------------------------- 1 | #DEVICE_NAME = PSOC5LP-xxx 2 | CONFIG_HEX_PATH = config.hex 3 | 4 | CONFIG_SRC = config.conf 5 | OBJS = main.o startup_ARMCM3.o startup.o systeminit.o app_config.o 6 | 7 | # --- 8 | 9 | CONFIG_BIN = $(CONFIG_SRC:%.conf=%.bin) 10 | CONFIG_HEX = $(CONFIG_SRC:%.conf=%.hex) 11 | 12 | 13 | all:: $(CONFIG_HEX) 14 | 15 | clean:: 16 | $(RM) $(CONFIG_HEX) $(CONFIG_BIN) 17 | 18 | $(CONFIG_HEX): $(CONFIG_SRC) 19 | $(UTILSPATH)/bin/gen_config.py -i $< | $(UTILSPATH)/bin/freehex2other.py -f intelhex -o $@ 20 | 21 | # Testing 22 | 23 | # This is a host (eg X86) debug compile - uses printf etc 24 | # avoid creating an X86 .o version of app_config.o (rather than an ARM version) 25 | test_app_config: app_config.c 26 | gcc -D DEBUG app_config.c -o $@ 27 | 28 | $(CONFIG_BIN): $(CONFIG_SRC) 29 | $(UTILSPATH)/bin/gen_config.py -i $(CONFIG_SRC) | $(UTILSPATH)/bin/freehex2other.py -f binary -o $(CONFIG_BIN) 30 | 31 | test: test_app_config $(CONFIG_BIN) 32 | ./test_app_config $(CONFIG_BIN) 33 | 34 | clean:: 35 | $(RM) app_config 36 | 37 | include ../common/conf/demo.mk 38 | -------------------------------------------------------------------------------- /demo2d/Makefile: -------------------------------------------------------------------------------- 1 | #DEVICE_NAME = PSOC5LP-xxx 2 | CONFIG_HEX_PATH = config.hex 3 | CONFIG_SRC = config.conf 4 | OBJS = main.o startup_ARMCM3.o startup.o systeminit.o app_config.o 5 | 6 | COMMON_INC_DIRS = hw psoc minilibc cmsis 7 | 8 | LIBS += -lcmsis 9 | 10 | CONFIG_BIN = $(CONFIG_SRC:%.conf=%.bin) 11 | CONFIG_HEX = $(CONFIG_SRC:%.conf=%.hex) 12 | 13 | 14 | all:: $(CONFIG_HEX) 15 | 16 | clean:: 17 | $(RM) $(CONFIG_HEX) $(CONFIG_BIN) 18 | 19 | $(CONFIG_HEX): $(CONFIG_SRC) 20 | $(UTILSPATH)/bin/gen_config.py -i $< | $(UTILSPATH)/bin/freehex2other.py -f intelhex -o $@ 21 | 22 | # Testing 23 | 24 | # This is a host (eg X86) debug compile - uses printf etc 25 | # avoid creating an X86 .o version of app_config.o (rather than an ARM version) 26 | app_config: app_config.c 27 | gcc -D DEBUG app_config.c -o $@ 28 | 29 | $(CONFIG_BIN): $(CONFIG_SRC) 30 | $(UTILSPATH)/bin/gen_config.py -i $(CONFIG_SRC) | $(UTILSPATH)/bin/freehex2other.py -f binary -o $(CONFIG_BIN) 31 | 32 | test: test_app_config $(CONFIG_BIN) 33 | ./test_app_config $(CONFIG_BIN) 34 | 35 | clean:: 36 | $(RM) app_config 37 | 38 | include ../common/conf/demo.mk 39 | -------------------------------------------------------------------------------- /common/minilibc/libc.h: -------------------------------------------------------------------------------- 1 | #ifndef _LIBC_H 2 | #define _LIBC_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #include 23 | 24 | void *memset(void *addr, int value, size_t len); 25 | void *memcpy(void *__restrict__ dest, const void *__restrict__ src, size_t len); 26 | 27 | size_t strlen(const char *str); 28 | 29 | //void exit(int status); 30 | //void _exit(int status); 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /demo2b/README.txt: -------------------------------------------------------------------------------- 1 | Demo 2b - LCD and LED 2 | --------------------- 3 | This demo flashes LED2 at 0.5Hz and turns on LED1 whilst SW2 is pressed (P6_1) 4 | 5 | Differences from demo 2a: 6 | * Uses config data 7 | 8 | Key points: 9 | * Minimal system setup 10 | * Uses Cypress generated config.hex to replace some hardware configuration 11 | in main code compared to demo2a. 12 | * Busy wait to drive LED 13 | 14 | Code Dependencies: 15 | * Essentially no Cypress code 16 | * No CMSIS 17 | 18 | Hardware Setup: 19 | * Requires CYC8KIT-050 20 | 21 | * Set up the CYC8KIT-050 as folows 22 | - Two wires: 23 | P6_0 (connector P9) to LED1 (connecor P6) 24 | P6_6 (connector P9) to LED2 (connecor P6) 25 | - Connect 2 line LCD 26 | 27 | Notes 28 | ----- 29 | It is probable that the Port6 setup code in main.c could also have been added into the config.hex file 30 | However I do not have the Cypress window toolkit and the next demo (2c) presents an enhanced config solution. 31 | The config.hex used was borrowed from another published Cypress project which happen to set up an LCD. 32 | The config.hex file also sets a few other ports but they don't interfere with our use. 33 | -------------------------------------------------------------------------------- /demo3a/Makefile: -------------------------------------------------------------------------------- 1 | #DEVICE_NAME = PSOC5LP-xxx 2 | CONFIG_HEX_PATH = config.hex 3 | 4 | CONFIG_SRC = config.conf 5 | OBJS = main.o startup_ARMCM3.o startup.o systeminit.o app_config.o 6 | 7 | COMMON_INC_DIRS = hw psoc minilibc cmsis 8 | LIBS += -lcmsis 9 | 10 | #LDSCRIPT = $(FILEDIR)gcc.ld 11 | LDSCRIPT = gcc.ld 12 | 13 | # --- 14 | 15 | CONFIG_BIN = $(CONFIG_SRC:%.conf=%.bin) 16 | CONFIG_HEX = $(CONFIG_SRC:%.conf=%.hex) 17 | 18 | 19 | all:: $(CONFIG_HEX) 20 | 21 | clean:: 22 | $(RM) $(CONFIG_HEX) $(CONFIG_BIN) 23 | 24 | $(CONFIG_HEX): $(CONFIG_SRC) 25 | $(UTILSPATH)/bin/gen_config.py -i $< | $(UTILSPATH)/bin/freehex2other.py -f intelhex -o $@ 26 | 27 | # Testing 28 | 29 | # This is a host (eg X86) debug compile - uses printf etc 30 | # avoid creating an X86 .o version of app_config.o (rather than an ARM version) 31 | app_config: app_config.c 32 | gcc -D DEBUG app_config.c -o $@ 33 | 34 | $(CONFIG_BIN): $(CONFIG_SRC) 35 | $(UTILSPATH)/bin/gen_config.py -i $(CONFIG_SRC) | $(UTILSPATH)/bin/freehex2other.py -f binary -o $(CONFIG_BIN) 36 | 37 | test: test_app_config $(CONFIG_BIN) 38 | ./test_app_config $(CONFIG_BIN) 39 | 40 | clean:: 41 | $(RM) app_config 42 | 43 | include ../common/conf/demo.mk 44 | -------------------------------------------------------------------------------- /demo3b/Makefile: -------------------------------------------------------------------------------- 1 | #DEVICE_NAME = PSOC5LP-xxx 2 | CONFIG_HEX_PATH = config.hex 3 | 4 | CONFIG_SRC = config.conf 5 | OBJS = main.o startup_ARMCM3.o startup.o systeminit.o app_config.o 6 | 7 | COMMON_INC_DIRS = hw psoc minilibc cmsis 8 | LIBS += -lcmsis 9 | 10 | #LDSCRIPT = $(FILEDIR)gcc.ld 11 | LDSCRIPT = gcc.ld 12 | 13 | # --- 14 | 15 | CONFIG_BIN = $(CONFIG_SRC:%.conf=%.bin) 16 | CONFIG_HEX = $(CONFIG_SRC:%.conf=%.hex) 17 | 18 | 19 | all:: $(CONFIG_HEX) 20 | 21 | clean:: 22 | $(RM) $(CONFIG_HEX) $(CONFIG_BIN) 23 | 24 | $(CONFIG_HEX): $(CONFIG_SRC) 25 | $(UTILSPATH)/bin/gen_config.py -i $< | $(UTILSPATH)/bin/freehex2other.py -f intelhex -o $@ 26 | 27 | # Testing 28 | 29 | # This is a host (eg X86) debug compile - uses printf etc 30 | # avoid creating an X86 .o version of app_config.o (rather than an ARM version) 31 | app_config: app_config.c 32 | gcc -D DEBUG app_config.c -o $@ 33 | 34 | $(CONFIG_BIN): $(CONFIG_SRC) 35 | $(UTILSPATH)/bin/gen_config.py -i $(CONFIG_SRC) | $(UTILSPATH)/bin/freehex2other.py -f binary -o $(CONFIG_BIN) 36 | 37 | test: test_app_config $(CONFIG_BIN) 38 | ./test_app_config $(CONFIG_BIN) 39 | 40 | clean:: 41 | $(RM) app_config 42 | 43 | include ../common/conf/demo.mk 44 | -------------------------------------------------------------------------------- /common/psoc/cmsis_alt.h: -------------------------------------------------------------------------------- 1 | #ifndef _CMSIS_ALT_H 2 | #define _CMSIS_ALT_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #include 23 | #include 24 | 25 | 26 | // Create two functions that are compatible with CMSIS library 27 | // but don't clash with the it if header file is not sued. 28 | // These exist here because they are the only functions needed 29 | // for a simple setup that are also in the CMSIS library. 30 | 31 | #define __enable_irq enable_irq 32 | #define __disable_irq disable_irq 33 | 34 | void enable_irq(void); 35 | void disable_irq(void); 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /demo2c/config.conf: -------------------------------------------------------------------------------- 1 | #include "../common/psoc/psoc_registers.h" 2 | 3 | #label config_base_addr @ 0x48000000 4 | 5 | # Have to use local versions as include versions use macros/maths as we don't handle that 6 | #define _REG_PRT2_BASE 0x40005120 7 | #define _REG_PRT6_BASE 0x40005160 8 | #define _REG_UDB_CFG_B1_IMPLEMENTED_BASE 0x40011400 9 | #define _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 0x800 10 | #define _REG_UDB_CFG_DSI_0_9_SIZE 0xA00 11 | #define _REG_UDB_CFG_DSI12_BASE 0x40014C00 12 | #define _REG_UDB_CFG_DSI_12_13_SIZE 0x200 13 | 14 | # Zero 15 | # ---- 16 | # (Note these are power on defaults anyway and weren't done in demo2a) 17 | 18 | #_REG_PRT2_BASE: 0 * PRTx_REG_SIZE 19 | #_REG_PRT6_BASE: 0 * PRTx_REG_SIZE 20 | 21 | REG_UDB_CFG_B0_BASE: 0 * REG_UDB_CFG_Bi_SIZE 22 | _REG_UDB_CFG_B1_IMPLEMENTED_BASE: 0 * _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 23 | REG_UDB_CFG_DSI0_BASE: 0 * _REG_UDB_CFG_DSI_0_9_SIZE 24 | _REG_UDB_CFG_DSI12_BASE: 0 * _REG_UDB_CFG_DSI_12_13_SIZE 25 | 26 | REG_BCTL_BASE: 0 * 32 # 2 * 16 (only BCTL0,1 implemented, 0-3 possible) 27 | 28 | # Init ports 29 | # ----------- 30 | # STRONG (mode 6) DM in bits 3-1 (6 << 1 -> 0x0C) 31 | # PULLUP (mode 2) DM in bits 3-1 (2 << 1 -> 0x04) 32 | 33 | #REG_PRT2_PC0: 0x 0C 0C 0C 0C 0C 0C 0C # set pins 0-6 34 | REG_PRT2_PC0: 0x0C * 7 # set pins 0-6 35 | 36 | REG_PRT6_PC0: 0x0C 37 | REG_PRT6_PC1: 0x05 # 0x04 | 1 (data out set) 38 | REG_PRT6_PC6: 0x0C 39 | -------------------------------------------------------------------------------- /demo2d/config.conf: -------------------------------------------------------------------------------- 1 | #include "../common/psoc/psoc_registers.h" 2 | 3 | #label config_base_addr @ 0x48000000 4 | 5 | # Have to use local versions as include versions use macros/maths as we don't handle that 6 | #define _REG_PRT2_BASE 0x40005120 7 | #define _REG_PRT6_BASE 0x40005160 8 | #define _REG_UDB_CFG_B1_IMPLEMENTED_BASE 0x40011400 9 | #define _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 0x800 10 | #define _REG_UDB_CFG_DSI_0_9_SIZE 0xA00 11 | #define _REG_UDB_CFG_DSI12_BASE 0x40014C00 12 | #define _REG_UDB_CFG_DSI_12_13_SIZE 0x200 13 | 14 | # Zero 15 | # ---- 16 | # (Note these are power on defaults anyway and weren't done in demo2a) 17 | 18 | #_REG_PRT2_BASE: 0 * PRTx_REG_SIZE 19 | #_REG_PRT6_BASE: 0 * PRTx_REG_SIZE 20 | 21 | REG_UDB_CFG_B0_BASE: 0 * REG_UDB_CFG_Bi_SIZE 22 | _REG_UDB_CFG_B1_IMPLEMENTED_BASE: 0 * _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 23 | REG_UDB_CFG_DSI0_BASE: 0 * _REG_UDB_CFG_DSI_0_9_SIZE 24 | _REG_UDB_CFG_DSI12_BASE: 0 * _REG_UDB_CFG_DSI_12_13_SIZE 25 | 26 | REG_BCTL_BASE: 0 * 32 # 2 * 16 (only BCTL0,1 implemented, 0-3 possible) 27 | 28 | # Init ports 29 | # ----------- 30 | # STRONG (mode 6) DM in bits 3-1 (6 << 1 -> 0x0C) 31 | # PULLUP (mode 2) DM in bits 3-1 (2 << 1 -> 0x04) 32 | 33 | #REG_PRT2_PC0: 0x 0C 0C 0C 0C 0C 0C 0C # set pins 0-6 34 | REG_PRT2_PC0: 0x0C * 7 # set pins 0-6 35 | 36 | REG_PRT6_PC0: 0x0C 37 | REG_PRT6_PC1: 0x05 # 0x04 | 1 (data out set) 38 | REG_PRT6_PC6: 0x0C 39 | -------------------------------------------------------------------------------- /demo3a/config.conf: -------------------------------------------------------------------------------- 1 | #include "../common/psoc/psoc_registers.h" 2 | 3 | #label config_base_addr @ 0x48000000 4 | 5 | # Have to use local versions as include versions use macros/maths as we don't handle that 6 | #define _REG_PRT2_BASE 0x40005120 7 | #define _REG_PRT6_BASE 0x40005160 8 | #define _REG_UDB_CFG_B1_IMPLEMENTED_BASE 0x40011400 9 | #define _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 0x800 10 | #define _REG_UDB_CFG_DSI_0_9_SIZE 0xA00 11 | #define _REG_UDB_CFG_DSI12_BASE 0x40014C00 12 | #define _REG_UDB_CFG_DSI_12_13_SIZE 0x200 13 | 14 | # Zero 15 | # ---- 16 | # (Note these are power on defaults anyway and weren't done in demo2a) 17 | 18 | #_REG_PRT2_BASE: 0 * PRTx_REG_SIZE 19 | #_REG_PRT6_BASE: 0 * PRTx_REG_SIZE 20 | 21 | REG_UDB_CFG_B0_BASE: 0 * REG_UDB_CFG_Bi_SIZE 22 | _REG_UDB_CFG_B1_IMPLEMENTED_BASE: 0 * _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 23 | REG_UDB_CFG_DSI0_BASE: 0 * _REG_UDB_CFG_DSI_0_9_SIZE 24 | _REG_UDB_CFG_DSI12_BASE: 0 * _REG_UDB_CFG_DSI_12_13_SIZE 25 | 26 | REG_BCTL_BASE: 0 * 32 # 2 * 16 (only BCTL0,1 implemented, 0-3 possible) 27 | 28 | # Init ports 29 | # ----------- 30 | # STRONG (mode 6) DM in bits 3-1 (6 << 1 -> 0x0C) 31 | # PULLUP (mode 2) DM in bits 3-1 (2 << 1 -> 0x04) 32 | 33 | #REG_PRT2_PC0: 0x 0C 0C 0C 0C 0C 0C 0C # set pins 0-6 34 | REG_PRT2_PC0: 0x0C * 7 # set pins 0-6 35 | 36 | REG_PRT6_PC0: 0x0C 37 | REG_PRT6_PC1: 0x05 # 0x04 | 1 (data out set) 38 | REG_PRT6_PC6: 0x0C 39 | -------------------------------------------------------------------------------- /demo3b/config.conf: -------------------------------------------------------------------------------- 1 | #include "../common/psoc/psoc_registers.h" 2 | 3 | #label config_base_addr @ 0x48000000 4 | 5 | # Have to use local versions as include versions use macros/maths as we don't handle that 6 | #define _REG_PRT2_BASE 0x40005120 7 | #define _REG_PRT6_BASE 0x40005160 8 | #define _REG_UDB_CFG_B1_IMPLEMENTED_BASE 0x40011400 9 | #define _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 0x800 10 | #define _REG_UDB_CFG_DSI_0_9_SIZE 0xA00 11 | #define _REG_UDB_CFG_DSI12_BASE 0x40014C00 12 | #define _REG_UDB_CFG_DSI_12_13_SIZE 0x200 13 | 14 | # Zero 15 | # ---- 16 | # (Note these are power on defaults anyway and weren't done in demo2a) 17 | 18 | #_REG_PRT2_BASE: 0 * PRTx_REG_SIZE 19 | #_REG_PRT6_BASE: 0 * PRTx_REG_SIZE 20 | 21 | REG_UDB_CFG_B0_BASE: 0 * REG_UDB_CFG_Bi_SIZE 22 | _REG_UDB_CFG_B1_IMPLEMENTED_BASE: 0 * _REG_UDB_CFG_B1_IMPLEMENTED_SIZE 23 | REG_UDB_CFG_DSI0_BASE: 0 * _REG_UDB_CFG_DSI_0_9_SIZE 24 | _REG_UDB_CFG_DSI12_BASE: 0 * _REG_UDB_CFG_DSI_12_13_SIZE 25 | 26 | REG_BCTL_BASE: 0 * 32 # 2 * 16 (only BCTL0,1 implemented, 0-3 possible) 27 | 28 | # Init ports 29 | # ----------- 30 | # STRONG (mode 6) DM in bits 3-1 (6 << 1 -> 0x0C) 31 | # PULLUP (mode 2) DM in bits 3-1 (2 << 1 -> 0x04) 32 | 33 | #REG_PRT2_PC0: 0x 0C 0C 0C 0C 0C 0C 0C # set pins 0-6 34 | REG_PRT2_PC0: 0x0C * 7 # set pins 0-6 35 | 36 | REG_PRT6_PC0: 0x0C 37 | REG_PRT6_PC1: 0x05 # 0x04 | 1 (data out set) 38 | REG_PRT6_PC6: 0x0C 39 | -------------------------------------------------------------------------------- /demo1/gcc.ld: -------------------------------------------------------------------------------- 1 | /* This linker script does NOT support 2 | * - C++ 3 | * - exception handling 4 | * - debugging 5 | */ 6 | 7 | MEMORY 8 | { 9 | FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K */ 10 | RAM (rwx) : ORIGIN = 0x20000000 - (0x10000 / 2), LENGTH = 0x10000 /* 64K */ 11 | } 12 | 13 | __StackSize = 0x1000; 14 | __HeapSize = 0x1000; 15 | 16 | 17 | ENTRY(Reset_Handler) 18 | 19 | SECTIONS 20 | { 21 | .text : 22 | { 23 | . = ALIGN(4); 24 | *(.isr_vector) 25 | 26 | *(.text) 27 | 28 | /* 29 | *(.init) 30 | *(.fini) 31 | */ 32 | 33 | *(.rodata) 34 | 35 | . = ALIGN(4); 36 | __etext = .; 37 | 38 | } > FLASH 39 | 40 | 41 | .data : AT (__etext) 42 | { 43 | . = ALIGN(4); 44 | __data_start__ = .; 45 | *(.data) 46 | . = ALIGN(4); 47 | __data_end__ = .; 48 | 49 | } > RAM /* AT>FLASH */ 50 | 51 | .bss : 52 | { 53 | . = ALIGN(4); 54 | __bss_start__ = .; 55 | *(.bss) 56 | *(COMMON) 57 | . = ALIGN(4); 58 | __bss_end__ = .; 59 | } > RAM 60 | 61 | /* Set stack at top end of RAM */ 62 | 63 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 64 | __StackLimit = __StackTop - __StackSize; 65 | /* PROVIDE(__stack = __StackTop); */ 66 | 67 | __HeapStart = __bss_end__; /* use highest/last RAM section */ 68 | __HeapLimit = __HeapStart + __HeapSize; 69 | 70 | /* Check if data + heap + stack exceeds RAM limit */ 71 | ASSERT(__HeapLimit < __StackLimit, "Heap overlaps Stack") 72 | } 73 | -------------------------------------------------------------------------------- /demo2b/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | #include "psoc_registers.h" 5 | 6 | 7 | // CLOCK SETUP 8 | // =========== 9 | #define CONFIG_SYSTEM_CLOCK_MHZ 63 10 | #define CONFIG_SYSTEM_CLOCK_HZ (CONFIG_SYSTEM_CLOCK_MHZ * 1000000) 11 | 12 | // Next two must match 13 | #define CONFIG_IMO_FREQ_MHZ 3 14 | #define CONFIG_IMO_FREQ_ENUM FASTCLK_IMO__F_RANGE__3MHz 15 | 16 | #define CONFIG_FASTCLK_PLL_P CONFIG_SYSTEM_CLOCK_MHZ 17 | #define CONFIG_FASTCLK_PLL_Q 0x02 18 | 19 | 20 | // OTHER SETUP 21 | // =========== 22 | // Note: delay_cycles() assumes instruction cache enabled. Refer source. 23 | #define CONFIG_INSTRUCTION_CACHE_ENABLED 1 24 | 25 | #define CONFIG_NVIC_PRIORITY_GROUP NVIC_APPLN_INTR__PRIGROUP__3_5 26 | 27 | 28 | // CONFIG DATA SETUP 29 | // ================= 30 | 31 | #define CONFIG_ADDR_TABLE_ADDR 0x48000000 32 | #define CONFIG_ADDR_TABLE_NELTS 1 33 | 34 | #define CONFIG_DATA_TABLE_ADDR 0x48000004 35 | 36 | // Init by copy 0 (data from config.hex) 37 | #define CONFIG_INITCOPY_0_SRC_ADDR 0x48000008 38 | #define CONFIG_INITCOPY_0_DEST_ADDR (REG_PRT0_DR + 0) 39 | #define CONFIG_INITCOPY_0_LEN 10 40 | 41 | // Init by copy 1 (data from config.hex) 42 | #define CONFIG_INITCOPY_1_SRC_ADDR 0x48000014 43 | #define CONFIG_INITCOPY_1_DEST_ADDR (REG_PRT2_DR + 2) 44 | #define CONFIG_INITCOPY_1_LEN 8 45 | 46 | #if 0 47 | // Init by copy 2 48 | #define CONFIG_INITCOPY_2_SRC_ADDR REG_PM_ACT_CFG0 49 | #define CONFIG_INITCOPY_2_DEST_ADDR REG_PM_STBY_CFG0 50 | #define CONFIG_INITCOPY_2_LEN PM_CFG_NREGS 51 | #endif 52 | 53 | #endif 54 | -------------------------------------------------------------------------------- /common/hw/lcd_hw.h: -------------------------------------------------------------------------------- 1 | #ifndef _LCD_HW_H 2 | #define _LCD_HW_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #include "psoc_registers.h" 23 | 24 | #define LCD_PORT_DR_REG ((uint8_t *) REG_PRT2_DR) 25 | #define LCD_PORT_DM0_REG ((uint8_t *) REG_PRT2_DM0) 26 | #define LCD_PORT_DM1_REG ((uint8_t *) REG_PRT2_DM1) 27 | #define LCD_PORT_DM2_REG ((uint8_t *) REG_PRT2_DM2) 28 | #define LCD_PORT_PS_REG ((uint8_t *) REG_PRT2_PS) 29 | 30 | #define LCD_HIGH_Z_DM0 0xFF 31 | #define LCD_HIGH_Z_DM1 0x00 32 | #define LCD_HIGH_Z_DM2 0x00 33 | 34 | #define LCD_STRONG_DM0 0x00 35 | #define LCD_STRONG_DM1 0xFF 36 | #define LCD_STRONG_DM2 0xFF 37 | 38 | #define LCD_DATA_OFFSET 0 39 | #define LCD_DATA_MASK_4BIT (0x0F << LCD_DATA_OFFSET) 40 | #define LCD_E 0x10 41 | #define LCD_RS 0x20 42 | #define LCD_RW 0x40 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /common/psoc/psoc_support.h: -------------------------------------------------------------------------------- 1 | #ifndef _PSOC_SUPPORT_H 2 | #define _PSOC_SUPPORT_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #include 23 | #include 24 | 25 | 26 | #define PACKED __attribute__ ((packed)) 27 | 28 | 29 | #define Set_Pin_Drive_Mode(pin, mode) \ 30 | REG_SET_BITS_8((pin), PRT_PC__DRIVE_MODE_MASK, (mode)) 31 | #define Set_Pin(pin) REG_OR_8((pin), PRT_PC__DATA_OUT) 32 | #define Clear_Pin(pin) REG_CLEAR_BITS_8((pin), PRT_PC__DATA_OUT) 33 | 34 | #define Read_Pin_Raw(pin) (REG_8((pin)) & PRT_PC__PIN_STATE) 35 | #define Read_Pin(pin) (REG_8((pin)) & PRT_PC__PIN_STATE) >> PRT_PC__PIN_STATE_SBIT) 36 | 37 | 38 | void delay_cycles(uint32_t cycles); // defined in delay.s 39 | 40 | void halt(void); 41 | void soft_reset(void); 42 | 43 | uint32_t sysclock_ticks_per_ms(void); 44 | 45 | void delay_ms(uint32_t milliseconds); 46 | void delay_us(uint16_t microseconds); 47 | void set_delay_freq(uint32_t freq); 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /common/psoc/delay.s: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is closely based on CyBootAsmGnu.s v 3.20 3 | * Therefore the original license is included 4 | * 5 | ******************************************************************************** 6 | * Copyright 2010-2012, Cypress Semiconductor Corporation. All rights reserved. 7 | * You may use this file only in accordance with the license, terms, conditions, 8 | * disclaimers, and limitations in the end user license agreement accompanying 9 | * the software package with which this file was provided. 10 | *******************************************************************************/ 11 | 12 | .syntax unified 13 | .text 14 | .thumb 15 | 16 | 17 | /* void delay_cycles(uint32_t cycles) */ 18 | /* busy loop for the given number of cycles. The resolution is 4 cycles */ 19 | 20 | /* Note: Delay func assumes instruction cache is enabled. 21 | * If not actual delays are twice expected. 22 | */ 23 | 24 | 25 | .align 3 /* Align to 8 byte boundary (2^n) */ 26 | .global delay_cycles 27 | .func delay_cycles, delay_cycles 28 | .type delay_cycles, %function 29 | .thumb_func 30 | delay_cycles: /* cycles bytes */ 31 | ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ 32 | LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ 33 | BEQ delay_cycles_done /* 2 2 Skip if 0 */ 34 | NOP /* 1 2 Loop alignment padding */ 35 | delay_cycles_loop: 36 | SUBS r0, r0, #1 /* 1 2 */ 37 | MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ 38 | BNE delay_cycles_loop /* 2 2 */ 39 | delay_cycles_done: 40 | BX lr /* 3 2 */ 41 | .endfunc 42 | 43 | .end 44 | -------------------------------------------------------------------------------- /common/hw/lcd.h: -------------------------------------------------------------------------------- 1 | #ifndef _LCD_H 2 | #define _LCD_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #include 23 | #include 24 | 25 | // convenience function 26 | void LCD_write_string(uint8_t *str); 27 | void LCD_write_stringn(uint8_t *str, int n); 28 | void LCD_write_cmd(uint8_t data); 29 | void LCD_write_data(uint8_t data); 30 | void LCD_clear(void); 31 | void LCD_home(void); 32 | void LCD_display_on(bool enable); 33 | void LCD_cursor(bool cursor_en, bool blinking_en); 34 | void LCD_moveto(uint8_t x, uint8_t y); 35 | int LCD_printf(const char *fmt, ...); 36 | 37 | // Core interface 38 | 39 | //#define LCD_IO_4_BIT 0 40 | //#define LCD_IO_8_BIT 1 41 | #define LCD_FONT_5x8 0 42 | #define LCD_FONT_5x10 1 43 | void LCD_init_4bit(uint8_t lines, uint8_t font); 44 | 45 | #define LCD_CONTROL 0 46 | #define LCD_DATA 1 47 | void LCD_write_byte(uint8_t data, uint8_t type); 48 | void LCD_write_nibble(uint8_t nibble, uint8_t type); 49 | 50 | void LCD_port_read_mode(void); 51 | void LCD_port_write_mode(void); 52 | void LCD_wait_ready(void); 53 | uint8_t LCD_read_byte(void); 54 | 55 | #endif 56 | -------------------------------------------------------------------------------- /common/psoc/delay_funcs.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "psoc_support.h" 4 | 5 | 6 | static uint32_t Ticks_per_ms; 7 | static uint8_t Ticks_per_us; 8 | static uint32_t Delay_32k_ms_ticks; // specific delay of 32k ms in units of ticks 9 | 10 | 11 | // Note: Delay funcs assume instruction cache is enabled. 12 | // If not actual delays are twice expected. 13 | // If the bus clock frequency is a small non-integer number, the actual delay 14 | // can be up to twice as long as the nominal value. The actual delay cannot be 15 | // shorter than the nominal value. 16 | 17 | // ticks per ms will have better resolution/precision that ticks_per_us 18 | uint32_t sysclock_ticks_per_ms(void) 19 | { 20 | return Ticks_per_ms; 21 | } 22 | 23 | #if 0 24 | uint8_t sysclock_ticks_per_us(void) 25 | { 26 | return Ticks_per_us; 27 | } 28 | #endif 29 | 30 | void delay_ms(uint32_t milliseconds) 31 | { 32 | // NOTE: This function is essentially copied from Cypress published source 33 | 34 | // Loop prevents overflow. 35 | // At 100MHz, milliseconds * Ticks_per_ms overflows at about 42 seconds. 36 | 37 | while (milliseconds > 32768) 38 | { 39 | delay_cycles(Delay_32k_ms_ticks); 40 | milliseconds -= 32768; 41 | } 42 | 43 | delay_cycles(milliseconds * Ticks_per_ms); // remainder 44 | } 45 | 46 | 47 | void delay_us(uint16_t microseconds) 48 | { 49 | delay_cycles((uint32_t)microseconds * Ticks_per_us); 50 | } 51 | 52 | 53 | void set_delay_freq(uint32_t freq_hz) 54 | { 55 | // freq_hz: Frequency of bus clock in Hertz. 56 | // NOTE: This function is essentially copied from Cypress published source 57 | 58 | #if 0 59 | if (freq_hz == 0) freq_hz = DEFAULT_MASTER_CLOCK__HZ; 60 | #endif 61 | Ticks_per_us = (uint8_t)((freq_hz + 999999u) / 1000000u); // nearest M 62 | Ticks_per_ms = (freq_hz + 999u) / 1000u; // integer round to nearest K 63 | Delay_32k_ms_ticks = 32768 * Ticks_per_ms; 64 | } 65 | -------------------------------------------------------------------------------- /common/conf/gcc.ld: -------------------------------------------------------------------------------- 1 | /* This linker script does NOT support 2 | * - C++ 3 | * - exception handling 4 | * - debugging 5 | */ 6 | 7 | MEMORY 8 | { 9 | FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K */ 10 | RAM (rwx) : ORIGIN = 0x20000000 - (0x10000 / 2), LENGTH = 0x10000 /* 64K */ 11 | 12 | /* NOTE: RAM is split into two halves. They are on different buses internally. 13 | * BOTTOM is 'CODE' RAM and should contain: ISR table, ISR code and speed critical code 14 | * TOP is 'DATA' RAM and should contain stack, heap etc. 15 | * ** This split hasn't be done in this version. ** 16 | * Data can be put into 'CODE' and vice versa but there will be performance penalties 17 | * See TRM 1.3.5 and 1.3.6 18 | */ 19 | } 20 | 21 | 22 | __StackSize = 0x1000; 23 | __HeapSize = 0x1000; 24 | 25 | 26 | ENTRY(Reset_Handler) 27 | 28 | SECTIONS 29 | { 30 | .text : 31 | { 32 | . = ALIGN(4); 33 | *(.isr_vector) 34 | 35 | *(.text) 36 | 37 | /* 38 | *(.init) 39 | *(.fini) 40 | */ 41 | 42 | *(.rodata) 43 | 44 | . = ALIGN(4); 45 | __etext = .; 46 | 47 | } > FLASH 48 | 49 | 50 | .data : AT (__etext) 51 | { 52 | . = ALIGN(4); 53 | __data_start__ = .; 54 | *(.data) 55 | . = ALIGN(4); 56 | __data_end__ = .; 57 | 58 | } > RAM /* AT>FLASH */ 59 | 60 | .bss : 61 | { 62 | . = ALIGN(4); 63 | __bss_start__ = .; 64 | *(.bss) 65 | *(COMMON) 66 | . = ALIGN(4); 67 | __bss_end__ = .; 68 | } > RAM 69 | 70 | /* Set stack at top end of RAM */ 71 | 72 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 73 | __StackLimit = __StackTop - __StackSize; 74 | /* PROVIDE(__stack = __StackTop); */ 75 | 76 | __HeapStart = __bss_end__; /* use highest/last RAM section */ 77 | __HeapLimit = __HeapStart + __HeapSize; 78 | 79 | /* Check if data + heap + stack exceeds RAM limit */ 80 | ASSERT(__HeapLimit < __StackLimit, "Heap overlaps Stack") 81 | } 82 | -------------------------------------------------------------------------------- /demo2c/README.txt: -------------------------------------------------------------------------------- 1 | Demo 2c - LCD and LED 2 | --------------------- 3 | This demo flashes LED2 at 0.5Hz and turns on LED1 whilst SW2 is pressed (P6_1) 4 | 5 | Differences from demo 2b: 6 | * Enhanced data config format 7 | 8 | Key points: 9 | * Minimal system setup 10 | * Uses an enhanced (non-Cypress compatible) config format (see below) for config data. 11 | * Busy wait to drive LED 12 | 13 | Code Dependencies: 14 | * Essentially no Cypress code 15 | * No CMSIS 16 | 17 | Hardware Setup: 18 | * Requires CYC8KIT-050 19 | 20 | * Set up the CYC8KIT-050 as folows 21 | - Two wires: 22 | P6_0 (connector P9) to LED1 (connecor P6) 23 | P6_6 (connector P9) to LED2 (connecor P6) 24 | - Connect 2 line LCD 25 | 26 | 27 | Config Format 28 | ------------- 29 | This is documented in the PSOC_programmer git repo docs (also partly in the gen_config python source). 30 | It is modelled on the Cypress idea but extends the concept to allow more sophisticated config in data, reducing custom code. 31 | The configuration data source is a simple readable text file. This is "compiled" into binary data. 32 | A small library (single function) is provided to parse/process the data. 33 | 34 | In summary: 35 | config.conf is the source file. 36 | It can be "compiled" ultimately into one of three forms: 37 | - "freehex" 38 | - Intel hex 39 | - binary 40 | 41 | The native format is the newly invented "freehex" format. It started out as a dump format but was convenient to use 42 | as an intermediate file format because it supports #lines for metadata and comments, plus is (almost) human readable. 43 | * gen_config takes .conf files and produces freehex. 44 | * freehex2other takes freehex and produces plain ascii hex dumps, Intel hex records, or binary. 45 | 46 | Config Format Test/Demo 47 | ----------------------- 48 | On your host machine (ie x86) do: 49 | make test 50 | 51 | This will compile the app_config.c code for the _host_ environment and include debug statements. 52 | The test will run and dump out the actions it's performing, which can be mapped easily back to the .conf file. 53 | (It could also be used as the basis to decode binary config back into a usable .conf file). 54 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ##PSOC_compiler 2 | 3 | #####Summary 4 | Demos for writing and compiling bare metal programs for PSOC5 using open source tools. 5 | 6 | #####Purpose 7 | To demo ARM Cortex M3 low level development with specific reference to PSoC. 8 | To provide some open source support for the PSoC. 9 | 10 | #####Requirements 11 | * ARM GCC cross compiler 12 | * A Cypress CY8CKIT-050 dev kit (to actually run programs) 13 | 14 | #####See Also 15 | * https://github.com/kiml/PSOC_programmer.git 16 | * http://dfusion.com.au/wiki/ The ARM Embedded pages: 17 | - PSoC5 bare metal 18 | - PSoC5 programmer 19 | - GCC Linker 20 | 21 | #####Additional Uses 22 | * A simple general purpose embedded LCD printf library 23 | 24 | #####License 25 | * All code is released under GPL v3 except for any third party files which have their original license included. 26 | 27 | #####Raison d'Etre 28 | * Cypress put out a free but closed source MS Windows development environment. They do provide GCC but pretty much everything else is proprietary which is fine but: 29 | - I like the PSoC feature set (basically ARM CPU, mxied signal FPGA, decent analogue) 30 | - I wanted to learn more about internals of the ARM Cortex M3 chip used 31 | - I wanted to program the PSoC under Unix. 32 | 33 | Short version - the mountain was there so I climbed it :-) 34 | 35 | 36 | #####Getting Started 37 | To use the programmer, edit conf/programmer.mak and change the UTILSPATH to point to the directory that contains bin/ and config/ of the programmer git repo. 38 | 39 | #####Dirs 40 | 41 | * demo1 - A basic demo to get started with bare metal. It's more about showing the compiler/linker options and interacting with the peer programmer tools than making a working program. 42 | * demo2* - Hello World. This is a minimal working PSOC5LP program that flashes lights and outputs to the LCD 43 | demo2a - no config.hex, 'std' nm.hex, all config done in code. 44 | demo2b - Cypress compat config.hex, 'std' nm.hex, config done in mix code/data. Basically Cypress devkit model, but open source code. 45 | demo2c - My own app_data config format. Removes need for much custom register init config in code. 'std' nm.hex??. Config format is NOT Cypress compatible. 46 | demo2d - democ2c + cmsisv1.3 47 | 48 | * demo3 - Compiling a Cypress devkit app (partial) 49 | -------------------------------------------------------------------------------- /common/hw/lcd_hd44780.h: -------------------------------------------------------------------------------- 1 | #ifndef _LCD_HD44780_H 2 | #define _LCD_HD44780_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #define HD44780_DISPLAY_CLEAR 0x01 23 | #define HD44780_HOME 0x02 24 | #define HD44780_ENTRY_MODE 0x04 25 | // 0x02 = I/D, 0x01 = S 26 | #define HD44870_EM_CURS_DEC (0 << 1) 27 | #define HD44870_EM_CURS_INC (1 << 1) 28 | #define HD44870_EM_DISPLAY_FIXED (0 << 0) 29 | #define HD44870_EM_DISPLAY_SHIFT (1 << 0) 30 | 31 | #define HD44780_DISPLAY 0x08 32 | // 0x04 display, 0x02 cursor, 0x01 blink 33 | #define HD44870_D_DISP_OFF (0 << 2) 34 | #define HD44870_D_DISP_ON (1 << 2) 35 | #define HD44870_D_CURS_OFF (0 << 1) 36 | #define HD44870_D_CURS_ON (1 << 1) 37 | #define HD44870_D_BLINK_OFF (0 << 0) 38 | #define HD44870_D_BLINK_ON (1 << 0) 39 | 40 | #define HD44780_CURSOR 0x10 41 | // 0x08 S/C, 0x04 R/L 42 | #define HD44870_C_SHIFT_CURS (0 << 3) 43 | #define HD44870_C_SHIFT_DISP (1 << 3) 44 | #define HD44870_C_SHIFT_LEFT (0 << 2) 45 | #define HD44870_C_SHIFT_RIGHT (1 << 2) 46 | 47 | #define HD44780_FUNC 0x20 48 | // 0x10 8/4bit(DL), 0x08 N, 0x04 F 49 | #define HD44870_F_LINES_1 (0 << 3) 50 | #define HD44870_F_LINES_2 (1 << 3) 51 | #define HD44870_F_FONT_5x8 (0 << 2) 52 | #define HD44870_F_FONT_5x10 (1 << 2) 53 | 54 | #define HD44780_CGRAM_ADDR 0x40 55 | #define HD44780_DDRAM_ADDR 0x80 56 | 57 | #define HD44870_BF 0x80 58 | #define HD44870_AC_MASK 0x7F 59 | 60 | #endif 61 | -------------------------------------------------------------------------------- /common/cmsis/core_cm3_psoc5.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * File Name: core_cm3_psoc5.h 3 | * Version 3.20 4 | * 5 | * Description: 6 | * Provides important type information for the PSoC5. This includes types 7 | * necessary for core_cm3.h. 8 | * 9 | * Note: 10 | * Documentation of the API's in this file is located in the 11 | * System Reference Guide provided with PSoC Creator. 12 | * 13 | ******************************************************************************** 14 | * Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. 15 | * You may use this file only in accordance with the license, terms, conditions, 16 | * disclaimers, and limitations in the end user license agreement accompanying 17 | * the software package with which this file was provided. 18 | ********************************************************************************/ 19 | 20 | 21 | #if !defined(__CORE_CM3_PSOC5_H__) 22 | #define __CORE_CM3_PSOC5_H__ 23 | 24 | /** Interrupt Number Definition */ 25 | typedef enum IRQn 26 | { 27 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 28 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 29 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 30 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 31 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 32 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 33 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 34 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 35 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 36 | SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ 37 | /****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ 38 | /* Not relevant. All peripheral interrupts are defined by the user */ 39 | } IRQn_Type; 40 | 41 | #include 42 | 43 | #endif /* __CORE_CM3_PSOC5_H__ */ 44 | -------------------------------------------------------------------------------- /demo2b/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "psoc5.h" 4 | #include "libc.h" 5 | #include "lcd.h" 6 | 7 | 8 | void main(void) 9 | { 10 | 11 | #if 0 12 | // Config data in config.hex, implemented by app_config.c code 13 | 14 | Set_Pin_Drive_Mode(REG_PRT2_PC0, PRT_PC__DRIVE_MODE__STRONG); 15 | Set_Pin_Drive_Mode(REG_PRT2_PC1, PRT_PC__DRIVE_MODE__STRONG); 16 | Set_Pin_Drive_Mode(REG_PRT2_PC2, PRT_PC__DRIVE_MODE__STRONG); 17 | Set_Pin_Drive_Mode(REG_PRT2_PC3, PRT_PC__DRIVE_MODE__STRONG); 18 | Set_Pin_Drive_Mode(REG_PRT2_PC4, PRT_PC__DRIVE_MODE__STRONG); 19 | Set_Pin_Drive_Mode(REG_PRT2_PC5, PRT_PC__DRIVE_MODE__STRONG); 20 | Set_Pin_Drive_Mode(REG_PRT2_PC6, PRT_PC__DRIVE_MODE__STRONG); 21 | #endif 22 | 23 | LCD_init_4bit(2, LCD_FONT_5x10); 24 | LCD_moveto(0,0); 25 | LCD_write_string("Hello PSoC 2b"); 26 | 27 | LCD_moveto(0,1); 28 | LCD_write_data('X'); 29 | LCD_moveto(3,1); 30 | LCD_write_data('Y'); 31 | LCD_moveto(11,1); 32 | LCD_printf("ver %d", 1); 33 | 34 | 35 | // NOTE: The following pin() functions could also be moved to config.hex 36 | 37 | // LED: OUT: Port 6.0 Strong, initially OFF 38 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 39 | Set_Pin_Drive_Mode(REG_PRT6_PC0, PRT_PC__DRIVE_MODE__STRONG); 40 | Clear_Pin(REG_PRT6_PC0); 41 | 42 | // LED: OUT: Port 6.6 Strong, initially OFF 43 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 44 | Set_Pin_Drive_Mode(REG_PRT6_PC6, PRT_PC__DRIVE_MODE__STRONG); 45 | Clear_Pin(REG_PRT6_PC6); 46 | 47 | // Button: IN: Port 6.1 Pull Up 48 | // DM 2,1,0: Pullup: 0 1 0 (Data = 1 pullup 5K Vcc) [not 0 - hard 0V] 49 | Set_Pin_Drive_Mode(REG_PRT6_PC1, PRT_PC__DRIVE_MODE__RES_PULLUP); 50 | Set_Pin(REG_PRT6_PC1); 51 | 52 | 53 | bool led2 = false; 54 | uint32_t count = 0; 55 | 56 | // Note: This is a busy wait loop - ok for a demo but not for product code. 57 | while(1) 58 | { 59 | if (Read_Pin_Raw(REG_PRT6_PC1)) 60 | Clear_Pin(REG_PRT6_PC0); 61 | else 62 | Set_Pin(REG_PRT6_PC0); 63 | 64 | delay_ms(10); 65 | if (count++ % 100 == 0) // 10 * 100 = 1000 ms 66 | led2 = !led2; 67 | 68 | if (led2) 69 | Clear_Pin(REG_PRT6_PC6); 70 | else 71 | Set_Pin(REG_PRT6_PC6); 72 | }; 73 | 74 | // don't return 75 | } 76 | -------------------------------------------------------------------------------- /demo2c/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "psoc5.h" 4 | #include "libc.h" 5 | #include "lcd.h" 6 | 7 | 8 | void main(void) 9 | { 10 | 11 | #if 0 12 | // Config data in config.hex, implemented by app_config.c code 13 | 14 | Set_Pin_Drive_Mode(REG_PRT2_PC0, PRT_PC__DRIVE_MODE__STRONG); 15 | Set_Pin_Drive_Mode(REG_PRT2_PC1, PRT_PC__DRIVE_MODE__STRONG); 16 | Set_Pin_Drive_Mode(REG_PRT2_PC2, PRT_PC__DRIVE_MODE__STRONG); 17 | Set_Pin_Drive_Mode(REG_PRT2_PC3, PRT_PC__DRIVE_MODE__STRONG); 18 | Set_Pin_Drive_Mode(REG_PRT2_PC4, PRT_PC__DRIVE_MODE__STRONG); 19 | Set_Pin_Drive_Mode(REG_PRT2_PC5, PRT_PC__DRIVE_MODE__STRONG); 20 | Set_Pin_Drive_Mode(REG_PRT2_PC6, PRT_PC__DRIVE_MODE__STRONG); 21 | #endif 22 | 23 | LCD_init_4bit(2, LCD_FONT_5x10); 24 | LCD_moveto(0,0); 25 | LCD_write_string("Hello PSoC 2c"); 26 | 27 | LCD_moveto(0,1); 28 | LCD_write_data('X'); 29 | LCD_moveto(3,1); 30 | LCD_write_data('Y'); 31 | LCD_moveto(11,1); 32 | LCD_printf("ver %d", 1); 33 | 34 | 35 | #if 0 36 | // NOTE: The following pin() functions have been moved to config.hex 37 | 38 | // LED: OUT: Port 6.0 Strong, initially OFF 39 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 40 | Set_Pin_Drive_Mode(REG_PRT6_PC0, PRT_PC__DRIVE_MODE__STRONG); 41 | Clear_Pin(REG_PRT6_PC0); 42 | 43 | // LED: OUT: Port 6.6 Strong, initially OFF 44 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 45 | Set_Pin_Drive_Mode(REG_PRT6_PC6, PRT_PC__DRIVE_MODE__STRONG); 46 | Clear_Pin(REG_PRT6_PC6); 47 | 48 | // Button: IN: Port 6.1 Pull Up 49 | // DM 2,1,0: Pullup: 0 1 0 (Data = 1 pullup 5K Vcc) [not 0 - hard 0V] 50 | Set_Pin_Drive_Mode(REG_PRT6_PC1, PRT_PC__DRIVE_MODE__RES_PULLUP); 51 | Set_Pin(REG_PRT6_PC1); 52 | #endif 53 | 54 | 55 | bool led2 = false; 56 | uint32_t count = 0; 57 | 58 | // Note: This is a busy wait loop - ok for a demo but not for product code. 59 | while(1) 60 | { 61 | if (Read_Pin_Raw(REG_PRT6_PC1)) 62 | Clear_Pin(REG_PRT6_PC0); 63 | else 64 | Set_Pin(REG_PRT6_PC0); 65 | 66 | delay_ms(10); 67 | if (count++ % 100 == 0) // 10 * 100 = 1000 ms 68 | led2 = !led2; 69 | 70 | if (led2) 71 | Clear_Pin(REG_PRT6_PC6); 72 | else 73 | Set_Pin(REG_PRT6_PC6); 74 | }; 75 | 76 | // don't return 77 | } 78 | -------------------------------------------------------------------------------- /demo2d/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "psoc5.h" 4 | #include "libc.h" 5 | #include "lcd.h" 6 | 7 | 8 | void main(void) 9 | { 10 | 11 | #if 0 12 | // Config data in config.hex, implemented by app_config.c code 13 | 14 | Set_Pin_Drive_Mode(REG_PRT2_PC0, PRT_PC__DRIVE_MODE__STRONG); 15 | Set_Pin_Drive_Mode(REG_PRT2_PC1, PRT_PC__DRIVE_MODE__STRONG); 16 | Set_Pin_Drive_Mode(REG_PRT2_PC2, PRT_PC__DRIVE_MODE__STRONG); 17 | Set_Pin_Drive_Mode(REG_PRT2_PC3, PRT_PC__DRIVE_MODE__STRONG); 18 | Set_Pin_Drive_Mode(REG_PRT2_PC4, PRT_PC__DRIVE_MODE__STRONG); 19 | Set_Pin_Drive_Mode(REG_PRT2_PC5, PRT_PC__DRIVE_MODE__STRONG); 20 | Set_Pin_Drive_Mode(REG_PRT2_PC6, PRT_PC__DRIVE_MODE__STRONG); 21 | #endif 22 | 23 | LCD_init_4bit(2, LCD_FONT_5x10); 24 | LCD_moveto(0,0); 25 | LCD_write_string("Hello PSoC 2d"); 26 | 27 | LCD_moveto(0,1); 28 | LCD_write_data('X'); 29 | LCD_moveto(3,1); 30 | LCD_write_data('Y'); 31 | LCD_moveto(11,1); 32 | LCD_printf("ver %d", 1); 33 | 34 | 35 | #if 0 36 | // NOTE: The following pin() functions have been moved to config.hex 37 | 38 | // LED: OUT: Port 6.0 Strong, initially OFF 39 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 40 | Set_Pin_Drive_Mode(REG_PRT6_PC0, PRT_PC__DRIVE_MODE__STRONG); 41 | Clear_Pin(REG_PRT6_PC0); 42 | 43 | // LED: OUT: Port 6.6 Strong, initially OFF 44 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 45 | Set_Pin_Drive_Mode(REG_PRT6_PC6, PRT_PC__DRIVE_MODE__STRONG); 46 | Clear_Pin(REG_PRT6_PC6); 47 | 48 | // Button: IN: Port 6.1 Pull Up 49 | // DM 2,1,0: Pullup: 0 1 0 (Data = 1 pullup 5K Vcc) [not 0 - hard 0V] 50 | Set_Pin_Drive_Mode(REG_PRT6_PC1, PRT_PC__DRIVE_MODE__RES_PULLUP); 51 | Set_Pin(REG_PRT6_PC1); 52 | #endif 53 | 54 | 55 | bool led2 = false; 56 | uint32_t count = 0; 57 | 58 | // Note: This is a busy wait loop - ok for a demo but not for product code. 59 | while(1) 60 | { 61 | if (Read_Pin_Raw(REG_PRT6_PC1)) 62 | Clear_Pin(REG_PRT6_PC0); 63 | else 64 | Set_Pin(REG_PRT6_PC0); 65 | 66 | delay_ms(10); 67 | if (count++ % 100 == 0) // 10 * 100 = 1000 ms 68 | led2 = !led2; 69 | 70 | if (led2) 71 | Clear_Pin(REG_PRT6_PC6); 72 | else 73 | Set_Pin(REG_PRT6_PC6); 74 | }; 75 | 76 | // don't return 77 | } 78 | -------------------------------------------------------------------------------- /common/psoc/psoc_regmacro.h: -------------------------------------------------------------------------------- 1 | #ifndef _PSOC_REG_H 2 | #define _PSOC_REG_H 3 | 4 | /* 5 | Copyright (C) 2014 Kim Lester 6 | http://www.dfusion.com.au/ 7 | 8 | This Program is free software: you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation, either version 3 of the License, or 11 | (at your option) any later version. 12 | 13 | This Program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this Program. If not, see . 20 | */ 21 | 22 | #include 23 | 24 | typedef volatile uint8_t reg8; 25 | typedef volatile uint16_t reg16; 26 | typedef volatile uint32_t reg32; 27 | 28 | #define REG_8(addr) (*((reg8 *)(void *)(addr))) 29 | #define REG_16(addr) (*((reg16 *)(void *)(addr))) 30 | #define REG_32(addr) (*((reg32 *)(void *)(addr))) 31 | 32 | #define REG_CLEAR_BITS_8(addr, mask) \ 33 | ( REG_8(addr) = (REG_8(addr) & ~(mask)) ) 34 | 35 | #define REG_CLEAR_BITS_16(addr, mask) \ 36 | ( REG_16(addr) = (REG_16(addr) & ~(mask)) ) 37 | 38 | #define REG_CLEAR_BITS_32(addr, mask) \ 39 | ( REG_32(addr) = (REG_32(addr) & ~(mask)) ) 40 | 41 | 42 | #define REG_OR_8(addr, value) ( REG_8(addr) |= (uint8_t)(value)) 43 | #define REG_OR_16(addr, value) ( REG_16(addr) |= (uint16_t)(value)) 44 | #define REG_OR_32(addr, value) ( REG_32(addr) |= (uint32_t)(value)) 45 | 46 | 47 | #define REG_SET_8(addr, value) ( REG_8(addr) = (uint8_t)(value)) 48 | #define REG_SET_16(addr, value) ( REG_16(addr) = (uint16_t)(value)) 49 | #define REG_SET_32(addr, value) ( REG_32(addr) = (uint32_t)(value)) 50 | 51 | 52 | #define REG_SET_BITS_8(addr, mask, sbits) \ 53 | ( REG_8(addr) = ((REG_8(addr) & ~(mask)) | ((sbits) & (mask))) ) 54 | 55 | #define REG_SET_BITS_16(addr, mask, sbits) \ 56 | ( REG_16(addr) = ((REG_16(addr) & ~(mask)) | ((sbits) & (mask))) ) 57 | 58 | #define REG_SET_BITS_32(addr, mask, sbits) \ 59 | ( REG_32(addr) = ((REG_32(addr) & ~(mask)) | ((sbits) & (mask))) ) 60 | 61 | 62 | //#define PSOC_SET_REG_APINT(addr, value) (PSOC_SET_REG32((addr),(APINT_VECTKEY | (value)))) 63 | 64 | 65 | #endif 66 | -------------------------------------------------------------------------------- /common/minilibc/libc.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include 20 | #include 21 | //#include 22 | 23 | #include "libc.h" 24 | 25 | 26 | void *sbrk(int incr) 27 | { 28 | extern uint8_t __HeapStart; // Defined by the linker 29 | extern uint8_t __StackLimit; // Defined by the linker 30 | 31 | static uint8_t *heap_end = 0; 32 | 33 | if (heap_end == 0) 34 | { 35 | heap_end = &__HeapStart; 36 | } 37 | 38 | if (incr < 0) 39 | { 40 | return (void *) -1; 41 | } 42 | 43 | uint8_t *prev_heap_end = heap_end; 44 | 45 | if (heap_end + incr > &__StackLimit) 46 | { 47 | // Heap hit the stack 48 | // FIXME: Should set errno to ENOMEM 49 | return (void *) -1; 50 | } 51 | 52 | heap_end += incr; 53 | 54 | return (void *) prev_heap_end; 55 | } 56 | 57 | 58 | void *memset(void *addr, int value, size_t len) 59 | { 60 | int i; 61 | uint8_t *ap = (uint8_t *)addr; 62 | for (i=0; i 2 | 3 | #include "core_cm3_psoc5.h" 4 | #include "core_cm3.h" 5 | #include "psoc5.h" 6 | #include "libc.h" 7 | #include "lcd.h" 8 | 9 | 10 | extern uint32_t volatile msTicks; 11 | 12 | void WaitForTick(void) 13 | { 14 | uint32_t curTicks = msTicks; // Save Current SysTick Value 15 | while (msTicks == curTicks) 16 | { 17 | // Wait for next SysTick Interrupt 18 | __WFE(); // Power-Down until next Event/Interrupt 19 | } 20 | } 21 | 22 | void main(void) 23 | { 24 | 25 | #if 0 26 | // Config data in config.hex, implemented by app_config.c code 27 | 28 | Set_Pin_Drive_Mode(REG_PRT2_PC0, PRT_PC__DRIVE_MODE__STRONG); 29 | Set_Pin_Drive_Mode(REG_PRT2_PC1, PRT_PC__DRIVE_MODE__STRONG); 30 | Set_Pin_Drive_Mode(REG_PRT2_PC2, PRT_PC__DRIVE_MODE__STRONG); 31 | Set_Pin_Drive_Mode(REG_PRT2_PC3, PRT_PC__DRIVE_MODE__STRONG); 32 | Set_Pin_Drive_Mode(REG_PRT2_PC4, PRT_PC__DRIVE_MODE__STRONG); 33 | Set_Pin_Drive_Mode(REG_PRT2_PC5, PRT_PC__DRIVE_MODE__STRONG); 34 | Set_Pin_Drive_Mode(REG_PRT2_PC6, PRT_PC__DRIVE_MODE__STRONG); 35 | 36 | // LED: OUT: Port 6.0 Strong, initially OFF 37 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 38 | Set_Pin_Drive_Mode(REG_PRT6_PC0, PRT_PC__DRIVE_MODE__STRONG); 39 | Clear_Pin(REG_PRT6_PC0); 40 | 41 | // LED: OUT: Port 6.6 Strong, initially OFF 42 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 43 | Set_Pin_Drive_Mode(REG_PRT6_PC6, PRT_PC__DRIVE_MODE__STRONG); 44 | Clear_Pin(REG_PRT6_PC6); 45 | 46 | // Button: IN: Port 6.1 Pull Up 47 | // DM 2,1,0: Pullup: 0 1 0 (Data = 1 pullup 5K Vcc) [not 0 - hard 0V] 48 | Set_Pin_Drive_Mode(REG_PRT6_PC1, PRT_PC__DRIVE_MODE__RES_PULLUP); 49 | Set_Pin(REG_PRT6_PC1); 50 | #endif 51 | 52 | LCD_init_4bit(2, LCD_FONT_5x10); 53 | LCD_moveto(0,0); 54 | LCD_write_string("Hello PSoC 3a"); 55 | 56 | bool led2 = false; 57 | uint32_t count = 0; 58 | 59 | // Note: This is a busy wait loop - ok for a demo but not for product code. 60 | while(1) 61 | { 62 | if (Read_Pin_Raw(REG_PRT6_PC1)) 63 | Clear_Pin(REG_PRT6_PC0); 64 | else 65 | Set_Pin(REG_PRT6_PC0); 66 | 67 | #if 0 68 | // busy wait 69 | delay_ms(10); 70 | if (count++ % 100 == 0) // 10 * 100 = 1000 ms 71 | led2 = !led2; 72 | #else 73 | // system sleeps between ticks 74 | WaitForTick(); // note that this reduces button responsiveness to once per tick (ms) 75 | #endif 76 | count++; 77 | 78 | if (count % 1000 == 0) 79 | { 80 | led2 = !led2; 81 | LCD_moveto(0,1); 82 | LCD_printf("count %d", count/1000); 83 | } 84 | 85 | if (led2) 86 | Clear_Pin(REG_PRT6_PC6); 87 | else 88 | Set_Pin(REG_PRT6_PC6); 89 | }; 90 | 91 | // don't return 92 | } 93 | -------------------------------------------------------------------------------- /demo3b/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "core_cm3_psoc5.h" 4 | #include "core_cm3.h" 5 | #include "psoc5.h" 6 | #include "libc.h" 7 | #include "lcd.h" 8 | 9 | 10 | extern uint32_t volatile msTicks; 11 | 12 | void WaitForTick(void) 13 | { 14 | uint32_t curTicks = msTicks; // Save Current SysTick Value 15 | while (msTicks == curTicks) 16 | { 17 | // Wait for next SysTick Interrupt 18 | __WFE(); // Power-Down until next Event/Interrupt 19 | } 20 | } 21 | 22 | void main(void) 23 | { 24 | 25 | #if 0 26 | // Config data in config.hex, implemented by app_config.c code 27 | 28 | Set_Pin_Drive_Mode(REG_PRT2_PC0, PRT_PC__DRIVE_MODE__STRONG); 29 | Set_Pin_Drive_Mode(REG_PRT2_PC1, PRT_PC__DRIVE_MODE__STRONG); 30 | Set_Pin_Drive_Mode(REG_PRT2_PC2, PRT_PC__DRIVE_MODE__STRONG); 31 | Set_Pin_Drive_Mode(REG_PRT2_PC3, PRT_PC__DRIVE_MODE__STRONG); 32 | Set_Pin_Drive_Mode(REG_PRT2_PC4, PRT_PC__DRIVE_MODE__STRONG); 33 | Set_Pin_Drive_Mode(REG_PRT2_PC5, PRT_PC__DRIVE_MODE__STRONG); 34 | Set_Pin_Drive_Mode(REG_PRT2_PC6, PRT_PC__DRIVE_MODE__STRONG); 35 | 36 | // LED: OUT: Port 6.0 Strong, initially OFF 37 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 38 | Set_Pin_Drive_Mode(REG_PRT6_PC0, PRT_PC__DRIVE_MODE__STRONG); 39 | Clear_Pin(REG_PRT6_PC0); 40 | 41 | // LED: OUT: Port 6.6 Strong, initially OFF 42 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 43 | Set_Pin_Drive_Mode(REG_PRT6_PC6, PRT_PC__DRIVE_MODE__STRONG); 44 | Clear_Pin(REG_PRT6_PC6); 45 | 46 | // Button: IN: Port 6.1 Pull Up 47 | // DM 2,1,0: Pullup: 0 1 0 (Data = 1 pullup 5K Vcc) [not 0 - hard 0V] 48 | Set_Pin_Drive_Mode(REG_PRT6_PC1, PRT_PC__DRIVE_MODE__RES_PULLUP); 49 | Set_Pin(REG_PRT6_PC1); 50 | #endif 51 | 52 | LCD_init_4bit(2, LCD_FONT_5x10); 53 | LCD_moveto(0,0); 54 | LCD_write_string("Hello PSoC 3b"); 55 | 56 | bool led2 = false; 57 | uint32_t count = 0; 58 | 59 | // Note: This is a busy wait loop - ok for a demo but not for product code. 60 | while(1) 61 | { 62 | if (Read_Pin_Raw(REG_PRT6_PC1)) 63 | Clear_Pin(REG_PRT6_PC0); 64 | else 65 | Set_Pin(REG_PRT6_PC0); 66 | 67 | #if 0 68 | // busy wait 69 | delay_ms(10); 70 | if (count++ % 100 == 0) // 10 * 100 = 1000 ms 71 | led2 = !led2; 72 | #else 73 | // system sleeps between ticks 74 | WaitForTick(); // note that this reduces button responsiveness to once per tick (ms) 75 | #endif 76 | count++; 77 | 78 | if (count % 1000 == 0) 79 | { 80 | led2 = !led2; 81 | LCD_moveto(0,1); 82 | LCD_printf("count %d", count/1000); 83 | } 84 | 85 | if (led2) 86 | Clear_Pin(REG_PRT6_PC6); 87 | else 88 | Set_Pin(REG_PRT6_PC6); 89 | }; 90 | 91 | // don't return 92 | } 93 | -------------------------------------------------------------------------------- /demo2a/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include 20 | 21 | #include "psoc5.h" 22 | #include "libc.h" 23 | #include "lcd.h" 24 | 25 | 26 | void main(void) 27 | { 28 | 29 | // Manual config of LCD lines 30 | Set_Pin_Drive_Mode(REG_PRT2_PC0, PRT_PC__DRIVE_MODE__STRONG); 31 | Set_Pin_Drive_Mode(REG_PRT2_PC1, PRT_PC__DRIVE_MODE__STRONG); 32 | Set_Pin_Drive_Mode(REG_PRT2_PC2, PRT_PC__DRIVE_MODE__STRONG); 33 | Set_Pin_Drive_Mode(REG_PRT2_PC3, PRT_PC__DRIVE_MODE__STRONG); 34 | Set_Pin_Drive_Mode(REG_PRT2_PC4, PRT_PC__DRIVE_MODE__STRONG); 35 | Set_Pin_Drive_Mode(REG_PRT2_PC5, PRT_PC__DRIVE_MODE__STRONG); 36 | Set_Pin_Drive_Mode(REG_PRT2_PC6, PRT_PC__DRIVE_MODE__STRONG); 37 | 38 | LCD_init_4bit(2, LCD_FONT_5x10); 39 | LCD_moveto(0,0); 40 | LCD_write_string("Hello PSoC 2a"); 41 | 42 | LCD_moveto(0,1); 43 | LCD_write_data('X'); 44 | LCD_moveto(3,1); 45 | LCD_write_data('Y'); 46 | LCD_moveto(11,1); 47 | LCD_printf("ver %d", 1); 48 | 49 | 50 | // LED: OUT: Port 6.0 Strong, initially OFF 51 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 52 | Set_Pin_Drive_Mode(REG_PRT6_PC0, PRT_PC__DRIVE_MODE__STRONG); 53 | Clear_Pin(REG_PRT6_PC0); 54 | 55 | // LED: OUT: Port 6.6 Strong, initially OFF 56 | // DM 2,1,0: Strong: 1 1 0 (DATA = 1 ON, 0 OFF) 57 | Set_Pin_Drive_Mode(REG_PRT6_PC6, PRT_PC__DRIVE_MODE__STRONG); 58 | Clear_Pin(REG_PRT6_PC6); 59 | 60 | // Button: IN: Port 6.1 Pull Up 61 | // DM 2,1,0: Pullup: 0 1 0 (Data = 1 pullup 5K Vcc) [not 0 - hard 0V] 62 | Set_Pin_Drive_Mode(REG_PRT6_PC1, PRT_PC__DRIVE_MODE__RES_PULLUP); 63 | Set_Pin(REG_PRT6_PC1); 64 | 65 | 66 | bool led2 = false; 67 | uint32_t count = 0; 68 | 69 | // Note: This is a busy wait loop - ok for a demo but not for product code. 70 | while(1) 71 | { 72 | if (Read_Pin_Raw(REG_PRT6_PC1)) 73 | Clear_Pin(REG_PRT6_PC0); 74 | else 75 | Set_Pin(REG_PRT6_PC0); 76 | 77 | delay_ms(10); 78 | if (count++ % 100 == 0) // 10 * 100 = 1000 ms 79 | led2 = !led2; 80 | 81 | if (led2) 82 | Clear_Pin(REG_PRT6_PC6); 83 | else 84 | Set_Pin(REG_PRT6_PC6); 85 | }; 86 | 87 | // don't return 88 | } 89 | -------------------------------------------------------------------------------- /demo2a/systeminit.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "cmsis_alt.h" 20 | #include "psoc5.h" 21 | #include "config.h" 22 | 23 | 24 | static void clock_setup(void) 25 | { 26 | // Enable/initialise device clocks 27 | 28 | // Configure Internal Low freq Oscillator (ILO) 29 | // Enable 1KHz clock and route to central timewheel (sleep timer) and watchdog timer. 30 | // PSoC TRM Section 16.3 31 | REG_SET_8(REG_SLOWCLK_ILO_CR0, SLOWCLK_ILO__EN_1K); 32 | REG_SET_8(REG_CLKDIST_CR, CLKDIST__ILO_OUT__1K); 33 | 34 | // Configure Internal Main Oscillator (IMO) 35 | // No fast start, no high precision USB clock. (TRM 1.3.31) 36 | REG_SET_8(REG_FASTCLK_IMO_CR, CONFIG_IMO_FREQ_ENUM); 37 | // REG_SET_8(CYREG_IMO_TR1, REG_8(REG_FLSHID_CUST_TABLES_IMO_3MHZ)); 38 | 39 | // Configure PLL 40 | // freq_out = freq_in * (P/(Q+1)). 41 | // Eg: => freq_out ~ 63/3 * freq_in. So freq_out ~ 21 * 3MHz ~ 63MHz 42 | //REG_SET_16(REG_FASTCLK_PLL_P, 0x023F); // set P and Q counters (Q=0x02, P=0x3F) 43 | REG_SET_8(REG_FASTCLK_PLL_P, CONFIG_FASTCLK_PLL_P); 44 | REG_SET_8(REG_FASTCLK_PLL_Q, CONFIG_FASTCLK_PLL_Q); 45 | REG_SET_16(REG_FASTCLK_PLL_CFG0, 0x1051); // Set params and Enable PLL 46 | 47 | // Wait up to 250us for the PLL to lock 48 | reg8 pllLock = 0; 49 | reg32 timeout; 50 | // reg32* timeout_p = &timeout; // Is this to avoid a weird optimisation !? 51 | // for (timeout = 250 / 10; *timeout_p && (pllLock != 0x03u); timeout--) 52 | for (timeout = 250 / 10; timeout && (pllLock != 0x03u); timeout--) 53 | { 54 | pllLock = 0x03u & ((pllLock << 1) | ((REG_8(REG_FASTCLK_PLL_SR) & FASTCLK_PLL_SR__LOCKDET) >> 0)); 55 | delay_cycles(10 * CONFIG_SYSTEM_CLOCK_MHZ); /* Delay 10us based on 63MHz clock */ 56 | } 57 | 58 | // Configure Master, Bus Clocks 59 | // IMO (3MHz) -> PLL (*21 -> 63MHz) -> Master(System) Clock (/1) -> Bus Clock (/1) 60 | REG_SET_16(REG_CLKDIST_MSTR0, 0x0100); // sets MSTR1 source = 01 PLL, Divider = 1 61 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x07); // sets Divider = 8 (but resets to 1 below) 62 | //REG_SET_8(REG_CLKDIST_BCFG0, 0x00); // LSB Divider value 63 | //REG_SET_8(REG_CLKDIST_BCFG1, 0x00); // MSB Divider value 64 | REG_SET_8(REG_CLKDIST_BCFG2, (CLKDIST__SSS|CLKDIST__SYNC)); // sync bus to master 65 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x00); // divider value -1 : 0 == source / 1 66 | REG_SET_8(REG_CLKDIST_LD, CLKDIST_LD__SYNC_EN); // restart master clock dividers in phase !? 67 | 68 | // Specify clock ticks for delay library routines (not the hardware) 69 | set_delay_freq(CONFIG_SYSTEM_CLOCK_HZ); 70 | } 71 | 72 | 73 | void SystemInit(void) 74 | { 75 | // NVIC Setup 76 | REG_SET_32(REG_NVIC_APPLN_INTR, (NVIC_APPLN_INTR__VECTKEY__KEY | CONFIG_NVIC_PRIORITY_GROUP)); 77 | REG_OR_32(REG_NVIC_CFG_CONTROL, NVIC_CFG_CONTROL__STKALIGN); 78 | 79 | __disable_irq(); 80 | 81 | // Enable cache and set flash_cycles assuming max clock (50-67MHz) 82 | REG_SET_8(REG_CACHE_CC_CTL, ((CONFIG_INSTRUCTION_CACHE_ENABLED) ? 0x01 : 0x00)); 83 | 84 | clock_setup(); 85 | } 86 | -------------------------------------------------------------------------------- /demo2b/systeminit.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "cmsis_alt.h" 20 | #include "psoc5.h" 21 | #include "config.h" 22 | 23 | extern void app_config(void); 24 | 25 | static void clock_setup(void) 26 | { 27 | // Enable/initialise device clocks 28 | 29 | // Configure Internal Low freq Oscillator (ILO) 30 | // Enable 1KHz clock and route to central timewheel (sleep timer) and watchdog timer. 31 | // PSoC TRM Section 16.3 32 | REG_SET_8(REG_SLOWCLK_ILO_CR0, SLOWCLK_ILO__EN_1K); 33 | REG_SET_8(REG_CLKDIST_CR, CLKDIST__ILO_OUT__1K); 34 | 35 | // Configure Internal Main Oscillator (IMO) 36 | // No fast start, no high precision USB clock. (TRM 1.3.31) 37 | REG_SET_8(REG_FASTCLK_IMO_CR, CONFIG_IMO_FREQ_ENUM); 38 | // REG_SET_8(CYREG_IMO_TR1, REG_8(REG_FLSHID_CUST_TABLES_IMO_3MHZ)); 39 | 40 | // Configure PLL 41 | // freq_out = freq_in * (P/(Q+1)). 42 | // Eg: => freq_out ~ 63/3 * freq_in. So freq_out ~ 21 * 3MHz ~ 63MHz 43 | //REG_SET_16(REG_FASTCLK_PLL_P, 0x023F); // set P and Q counters (Q=0x02, P=0x3F) 44 | REG_SET_8(REG_FASTCLK_PLL_P, CONFIG_FASTCLK_PLL_P); 45 | REG_SET_8(REG_FASTCLK_PLL_Q, CONFIG_FASTCLK_PLL_Q); 46 | REG_SET_16(REG_FASTCLK_PLL_CFG0, 0x1051); // Set params and Enable PLL 47 | 48 | // Wait up to 250us for the PLL to lock 49 | reg8 pllLock = 0; 50 | reg32 timeout; 51 | // reg32* timeout_p = &timeout; // Is this to avoid a weird optimisation !? 52 | // for (timeout = 250 / 10; *timeout_p && (pllLock != 0x03u); timeout--) 53 | for (timeout = 250 / 10; timeout && (pllLock != 0x03u); timeout--) 54 | { 55 | pllLock = 0x03u & ((pllLock << 1) | ((REG_8(REG_FASTCLK_PLL_SR) & FASTCLK_PLL_SR__LOCKDET) >> 0)); 56 | delay_cycles(10 * CONFIG_SYSTEM_CLOCK_MHZ); /* Delay 10us based on 63MHz clock */ 57 | } 58 | 59 | // Configure Master, Bus Clocks 60 | // IMO (3MHz) -> PLL (*21 -> 63MHz) -> Master(System) Clock (/1) -> Bus Clock (/1) 61 | REG_SET_16(REG_CLKDIST_MSTR0, 0x0100); // sets MSTR1 source = 01 PLL, Divider = 1 62 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x07); // sets Divider = 8 (but resets to 1 below) 63 | //REG_SET_8(REG_CLKDIST_BCFG0, 0x00); // LSB Divider value 64 | //REG_SET_8(REG_CLKDIST_BCFG1, 0x00); // MSB Divider value 65 | REG_SET_8(REG_CLKDIST_BCFG2, (CLKDIST__SSS|CLKDIST__SYNC)); // sync bus to master 66 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x00); // divider value -1 : 0 == source / 1 67 | REG_SET_8(REG_CLKDIST_LD, CLKDIST_LD__SYNC_EN); // restart master clock dividers in phase !? 68 | 69 | // Specify clock ticks for delay library routines (not the hardware) 70 | set_delay_freq(CONFIG_SYSTEM_CLOCK_HZ); 71 | } 72 | 73 | 74 | void SystemInit(void) 75 | { 76 | // NVIC Setup 77 | REG_SET_32(REG_NVIC_APPLN_INTR, (NVIC_APPLN_INTR__VECTKEY__KEY | CONFIG_NVIC_PRIORITY_GROUP)); 78 | REG_OR_32(REG_NVIC_CFG_CONTROL, NVIC_CFG_CONTROL__STKALIGN); 79 | 80 | __disable_irq(); 81 | 82 | // Enable cache and set flash_cycles assuming max clock (50-67MHz) 83 | REG_SET_8(REG_CACHE_CC_CTL, ((CONFIG_INSTRUCTION_CACHE_ENABLED) ? 0x01 : 0x00)); 84 | 85 | clock_setup(); 86 | 87 | app_config(); 88 | } 89 | -------------------------------------------------------------------------------- /demo2c/systeminit.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "cmsis_alt.h" 20 | #include "psoc5.h" 21 | #include "config.h" 22 | 23 | extern void app_config(void); 24 | 25 | static void clock_setup(void) 26 | { 27 | // Enable/initialise device clocks 28 | 29 | // Configure Internal Low freq Oscillator (ILO) 30 | // Enable 1KHz clock and route to central timewheel (sleep timer) and watchdog timer. 31 | // PSoC TRM Section 16.3 32 | REG_SET_8(REG_SLOWCLK_ILO_CR0, SLOWCLK_ILO__EN_1K); 33 | REG_SET_8(REG_CLKDIST_CR, CLKDIST__ILO_OUT__1K); 34 | 35 | // Configure Internal Main Oscillator (IMO) 36 | // No fast start, no high precision USB clock. (TRM 1.3.31) 37 | REG_SET_8(REG_FASTCLK_IMO_CR, CONFIG_IMO_FREQ_ENUM); 38 | // REG_SET_8(CYREG_IMO_TR1, REG_8(REG_FLSHID_CUST_TABLES_IMO_3MHZ)); 39 | 40 | // Configure PLL 41 | // freq_out = freq_in * (P/(Q+1)). 42 | // Eg: => freq_out ~ 63/3 * freq_in. So freq_out ~ 21 * 3MHz ~ 63MHz 43 | //REG_SET_16(REG_FASTCLK_PLL_P, 0x023F); // set P and Q counters (Q=0x02, P=0x3F) 44 | REG_SET_8(REG_FASTCLK_PLL_P, CONFIG_FASTCLK_PLL_P); 45 | REG_SET_8(REG_FASTCLK_PLL_Q, CONFIG_FASTCLK_PLL_Q); 46 | REG_SET_16(REG_FASTCLK_PLL_CFG0, 0x1051); // Set params and Enable PLL 47 | 48 | // Wait up to 250us for the PLL to lock 49 | reg8 pllLock = 0; 50 | reg32 timeout; 51 | // reg32* timeout_p = &timeout; // Is this to avoid a weird optimisation !? 52 | // for (timeout = 250 / 10; *timeout_p && (pllLock != 0x03u); timeout--) 53 | for (timeout = 250 / 10; timeout && (pllLock != 0x03u); timeout--) 54 | { 55 | pllLock = 0x03u & ((pllLock << 1) | ((REG_8(REG_FASTCLK_PLL_SR) & FASTCLK_PLL_SR__LOCKDET) >> 0)); 56 | delay_cycles(10 * CONFIG_SYSTEM_CLOCK_MHZ); /* Delay 10us based on 63MHz clock */ 57 | } 58 | 59 | // Configure Master, Bus Clocks 60 | // IMO (3MHz) -> PLL (*21 -> 63MHz) -> Master(System) Clock (/1) -> Bus Clock (/1) 61 | REG_SET_16(REG_CLKDIST_MSTR0, 0x0100); // sets MSTR1 source = 01 PLL, Divider = 1 62 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x07); // sets Divider = 8 (but resets to 1 below) 63 | //REG_SET_8(REG_CLKDIST_BCFG0, 0x00); // LSB Divider value 64 | //REG_SET_8(REG_CLKDIST_BCFG1, 0x00); // MSB Divider value 65 | REG_SET_8(REG_CLKDIST_BCFG2, (CLKDIST__SSS|CLKDIST__SYNC)); // sync bus to master 66 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x00); // divider value -1 : 0 == source / 1 67 | REG_SET_8(REG_CLKDIST_LD, CLKDIST_LD__SYNC_EN); // restart master clock dividers in phase !? 68 | 69 | // Specify clock ticks for delay library routines (not the hardware) 70 | set_delay_freq(CONFIG_SYSTEM_CLOCK_HZ); 71 | } 72 | 73 | 74 | void SystemInit(void) 75 | { 76 | // NVIC Setup 77 | REG_SET_32(REG_NVIC_APPLN_INTR, (NVIC_APPLN_INTR__VECTKEY__KEY | CONFIG_NVIC_PRIORITY_GROUP)); 78 | REG_OR_32(REG_NVIC_CFG_CONTROL, NVIC_CFG_CONTROL__STKALIGN); 79 | 80 | __disable_irq(); 81 | 82 | // Enable cache and set flash_cycles assuming max clock (50-67MHz) 83 | REG_SET_8(REG_CACHE_CC_CTL, ((CONFIG_INSTRUCTION_CACHE_ENABLED) ? 0x01 : 0x00)); 84 | 85 | clock_setup(); 86 | 87 | app_config(); 88 | } 89 | -------------------------------------------------------------------------------- /demo2d/systeminit.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "core_cm3_psoc5.h" 20 | #include "core_cm3.h" 21 | #include "psoc5.h" 22 | #include "config.h" 23 | 24 | extern void app_config(void); 25 | 26 | static void clock_setup(void) 27 | { 28 | // Enable/initialise device clocks 29 | 30 | // Configure Internal Low freq Oscillator (ILO) 31 | // Enable 1KHz clock and route to central timewheel (sleep timer) and watchdog timer. 32 | // PSoC TRM Section 16.3 33 | REG_SET_8(REG_SLOWCLK_ILO_CR0, SLOWCLK_ILO__EN_1K); 34 | REG_SET_8(REG_CLKDIST_CR, CLKDIST__ILO_OUT__1K); 35 | 36 | // Configure Internal Main Oscillator (IMO) 37 | // No fast start, no high precision USB clock. (TRM 1.3.31) 38 | REG_SET_8(REG_FASTCLK_IMO_CR, CONFIG_IMO_FREQ_ENUM); 39 | // REG_SET_8(CYREG_IMO_TR1, REG_8(REG_FLSHID_CUST_TABLES_IMO_3MHZ)); 40 | 41 | // Configure PLL 42 | // freq_out = freq_in * (P/(Q+1)). 43 | // Eg: => freq_out ~ 63/3 * freq_in. So freq_out ~ 21 * 3MHz ~ 63MHz 44 | //REG_SET_16(REG_FASTCLK_PLL_P, 0x023F); // set P and Q counters (Q=0x02, P=0x3F) 45 | REG_SET_8(REG_FASTCLK_PLL_P, CONFIG_FASTCLK_PLL_P); 46 | REG_SET_8(REG_FASTCLK_PLL_Q, CONFIG_FASTCLK_PLL_Q); 47 | REG_SET_16(REG_FASTCLK_PLL_CFG0, 0x1051); // Set params and Enable PLL 48 | 49 | // Wait up to 250us for the PLL to lock 50 | reg8 pllLock = 0; 51 | reg32 timeout; 52 | // reg32* timeout_p = &timeout; // Is this to avoid a weird optimisation !? 53 | // for (timeout = 250 / 10; *timeout_p && (pllLock != 0x03u); timeout--) 54 | for (timeout = 250 / 10; timeout && (pllLock != 0x03u); timeout--) 55 | { 56 | pllLock = 0x03u & ((pllLock << 1) | ((REG_8(REG_FASTCLK_PLL_SR) & FASTCLK_PLL_SR__LOCKDET) >> 0)); 57 | delay_cycles(10 * CONFIG_SYSTEM_CLOCK_MHZ); /* Delay 10us based on 63MHz clock */ 58 | } 59 | 60 | // Configure Master, Bus Clocks 61 | // IMO (3MHz) -> PLL (*21 -> 63MHz) -> Master(System) Clock (/1) -> Bus Clock (/1) 62 | REG_SET_16(REG_CLKDIST_MSTR0, 0x0100); // sets MSTR1 source = 01 PLL, Divider = 1 63 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x07); // sets Divider = 8 (but resets to 1 below) 64 | //REG_SET_8(REG_CLKDIST_BCFG0, 0x00); // LSB Divider value 65 | //REG_SET_8(REG_CLKDIST_BCFG1, 0x00); // MSB Divider value 66 | REG_SET_8(REG_CLKDIST_BCFG2, (CLKDIST__SSS|CLKDIST__SYNC)); // sync bus to master 67 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x00); // divider value -1 : 0 == source / 1 68 | REG_SET_8(REG_CLKDIST_LD, CLKDIST_LD__SYNC_EN); // restart master clock dividers in phase !? 69 | 70 | // Specify clock ticks for delay library routines (not the hardware) 71 | set_delay_freq(CONFIG_SYSTEM_CLOCK_HZ); 72 | } 73 | 74 | 75 | void SystemInit(void) 76 | { 77 | // NVIC Setup 78 | // SCB->AIRCR = (NVIC_APPLN_INTR__VECTKEY__KEY | CONFIG_NVIC_PRIORITY_GROUP); 79 | //or 80 | NVIC_SetPriorityGrouping(4); // 4 is PRIGROUP__3_5 split 81 | 82 | // SCB->CCR |= NVIC_CFG_CONTROL__STKALIGN; 83 | // or 84 | SCB->CCR |= (1 << SCB_CCR_STKALIGN_Pos); 85 | 86 | __disable_irq(); 87 | 88 | // Enable cache and set flash_cycles assuming max clock (50-67MHz) 89 | REG_SET_8(REG_CACHE_CC_CTL, ((CONFIG_INSTRUCTION_CACHE_ENABLED) ? 0x01 : 0x00)); 90 | 91 | clock_setup(); 92 | 93 | app_config(); 94 | } 95 | -------------------------------------------------------------------------------- /common/hw/lcd_printf.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include 20 | #include 21 | 22 | 23 | // quick and dirty printf 24 | // note there is a stdarg-printf.c out there etc 25 | 26 | static int print_escape(const char **escape_code); 27 | static int int2string(int value, char *buf); 28 | 29 | 30 | int LCD_printf(const char *fmt, ...) 31 | { 32 | va_list ap; 33 | int count = 0; 34 | 35 | va_start(ap, fmt); 36 | 37 | while (*fmt) 38 | { 39 | switch(*fmt) 40 | { 41 | case '%': 42 | switch(*++fmt) 43 | { 44 | case 's': 45 | { 46 | char *s = va_arg(ap, char *); 47 | LCD_write_string(s); 48 | count += strlen(s); 49 | } 50 | break; 51 | 52 | case 'd': 53 | { 54 | char tmp[15]; 55 | int d = va_arg(ap, int); 56 | int len = int2string(d, tmp); 57 | LCD_write_stringn(tmp, len); 58 | count += len; 59 | } 60 | break; 61 | 62 | case 'c': 63 | LCD_write_data((int)va_arg(ap, int)); // char -> int 64 | count++; 65 | break; 66 | 67 | default: 68 | LCD_write_data(*fmt); 69 | count++; 70 | break; 71 | } 72 | 73 | //fmt++; 74 | //print_value(++fmt); 75 | break; 76 | 77 | case '\\': 78 | fmt++; 79 | count += print_escape(&fmt); 80 | break; 81 | 82 | default: // FIXME ok or return error ? 83 | LCD_write_data(*fmt); 84 | count++; 85 | break; 86 | } 87 | 88 | fmt++; 89 | } 90 | 91 | va_end(ap); 92 | 93 | return count; 94 | } 95 | 96 | 97 | int print_escape(const char **fmt) 98 | { 99 | switch(**fmt) 100 | { 101 | // case 'a': break; 102 | // case 'b': break; 103 | // case 'c': break; 104 | // case 'f': break; 105 | // case 'n': break; 106 | // case 'r': break; 107 | // case 't': break; 108 | // case 'v': break; 109 | case '\'': 110 | case '\\': 111 | LCD_write_data(**fmt); 112 | break; 113 | // default: 114 | // is_digit(); 115 | // break; 116 | } 117 | 118 | *fmt++; 119 | return 1; 120 | } 121 | 122 | 123 | int int2string(int value, char *buf) 124 | { 125 | int count = 0; 126 | char *bp = buf; 127 | if (value < 0) 128 | { 129 | *bp++ = '-'; 130 | value = -value; // won't handle max neg 131 | count++; 132 | } 133 | 134 | char tmp[15]; 135 | int i=0; 136 | while (value > 0) 137 | { 138 | tmp[i++] = value % 10; 139 | value /= 10; 140 | } 141 | count += i; 142 | 143 | while(i) 144 | { 145 | *bp++ = tmp[--i] + '0'; 146 | } 147 | *bp = 0; 148 | 149 | return count; 150 | } 151 | -------------------------------------------------------------------------------- /demo2b/app_config.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include 20 | 21 | #include "libc.h" 22 | #include "psoc5.h" 23 | #include "config.h" 24 | 25 | 26 | // Note: I believe most unaligned data accesses are supported on Cortex M3 (ARMv7-M cores). I think a register may have to be set as well (CP15 ?) 27 | 28 | typedef struct { 29 | void *address; 30 | uint16_t size; 31 | } PACKED cfg_memset_t; 32 | 33 | 34 | // Defines the layout and meaning of each entry in the cfg_memcpy_list used for initializing registers 35 | typedef struct { 36 | void *dest; 37 | const void *src; 38 | uint16_t size; 39 | } PACKED cfg_memcpy_t; 40 | 41 | 42 | typedef struct { 43 | uint8_t offset; 44 | uint8_t value; 45 | } PACKED cfg_data_t; 46 | 47 | 48 | // Contains the regions of memory that must be zeroed during configuration 49 | // Whilst we could zero all registers in a region the preference seems to 50 | // be to only zero those that aren't about to be configured, possibly to 51 | // better handle IO during some reset conditions (or it may be irrelevant in 52 | // which case we could simplify things here) 53 | 54 | static const cfg_memset_t cfg_memset_list [] = { 55 | /* address, size */ 56 | // PRTx: Don't reset ports 0, 2 (we config and use those later) 57 | {(void *)(REG_PRTx_BASE(1)), PRTx_REG_SIZE}, 58 | {(void *)(REG_PRTx_BASE(3)), 4 * PRTx_REG_SIZE}, // 3 - 6 59 | {(void *)(REG_PRTx_BASE(12)), PRTx_REG_SIZE}, 60 | {(void *)(REG_PRTx_BASE(15)), PRTx_REG_SIZE}, 61 | {(void *)(REG_UDB_CFG_B0_BASE), REG_UDB_CFG_Bi_SIZE}, 62 | {(void *)(REG_UDB_CFG_B1_IMPLEMENTED_BASE), REG_UDB_CFG_B1_IMPLEMENTED_SIZE}, 63 | {(void *)(REG_UDB_CFG_DSI_BASE), REG_UDB_CFG_DSI_SIZE}, // ignored gap in middle 64 | {(void *)(REG_BCTL_BASE), 2 * REG_BCTLi_SIZE}, 65 | }; 66 | 67 | 68 | static void cfg_zero_regions(void) 69 | { 70 | // Zero out critical memory blocks before beginning configuration 71 | 72 | uint8_t i; 73 | uint8_t len = sizeof(cfg_memset_list)/sizeof(*cfg_memset_list); 74 | 75 | for (i = 0; i < len; i++) 76 | { 77 | const cfg_memset_t *ms = &cfg_memset_list[i]; 78 | memset(ms->address, 0, ms->size); 79 | } 80 | } 81 | 82 | 83 | static void cfg_sparse_regions(void) 84 | { 85 | // For 32-bit little-endian architectures 86 | // Writes chip sparse configuration - index, value 87 | 88 | unsigned int i, j = 0; 89 | for (i = 0; i < CONFIG_ADDR_TABLE_NELTS; i++) 90 | { 91 | uint32_t baseAddr = ((const uint32_t *)CONFIG_ADDR_TABLE_ADDR)[i]; 92 | uint8_t count = baseAddr & 0xFFu; 93 | baseAddr &= 0xFFFFFF00u; 94 | while (count--) 95 | { 96 | const cfg_data_t *data_item = &((const cfg_data_t *)CONFIG_DATA_TABLE_ADDR)[j]; 97 | REG_SET_8((baseAddr + data_item->offset), data_item->value); 98 | j++; 99 | } 100 | } 101 | } 102 | 103 | 104 | static void cfg_copy_regions(void) 105 | { 106 | memcpy(((void *)CONFIG_INITCOPY_0_DEST_ADDR), (void *)(CONFIG_INITCOPY_0_SRC_ADDR), 107 | CONFIG_INITCOPY_0_LEN); 108 | 109 | memcpy(((void *)CONFIG_INITCOPY_1_DEST_ADDR), (void *)(CONFIG_INITCOPY_1_SRC_ADDR), 110 | CONFIG_INITCOPY_1_LEN); 111 | 112 | #if 0 113 | memcpy(((void *)CONFIG_INITCOPY_2_DEST_ADDR), (void *)(CONFIG_INITCOPY_2_SRC_ADDR), 114 | CONFIG_INITCOPY_2_LEN); 115 | #endif 116 | } 117 | 118 | 119 | void app_config(void) 120 | { 121 | cfg_zero_regions(); // must come first (in case of overlaps) 122 | cfg_sparse_regions(); 123 | cfg_copy_regions(); 124 | } 125 | -------------------------------------------------------------------------------- /demo3a/systeminit.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "core_cm3_psoc5.h" 20 | #include "core_cm3.h" 21 | #include "psoc5.h" 22 | #include "config.h" 23 | 24 | 25 | extern void app_config(void); 26 | 27 | static void clock_setup(void) 28 | { 29 | // Enable/initialise device clocks 30 | 31 | // Configure Internal Low freq Oscillator (ILO) 32 | // Enable 1KHz clock and route to central timewheel (sleep timer) and watchdog timer. 33 | // PSoC TRM Section 16.3 34 | REG_SET_8(REG_SLOWCLK_ILO_CR0, SLOWCLK_ILO__EN_1K); 35 | REG_SET_8(REG_CLKDIST_CR, CLKDIST__ILO_OUT__1K); 36 | 37 | // Configure Internal Main Oscillator (IMO) 38 | // No fast start, no high precision USB clock. (TRM 1.3.31) 39 | REG_SET_8(REG_FASTCLK_IMO_CR, CONFIG_IMO_FREQ_ENUM); 40 | // REG_SET_8(CYREG_IMO_TR1, REG_8(REG_FLSHID_CUST_TABLES_IMO_3MHZ)); 41 | 42 | // Configure PLL 43 | // freq_out = freq_in * (P/(Q+1)). 44 | // Eg: => freq_out ~ 63/3 * freq_in. So freq_out ~ 21 * 3MHz ~ 63MHz 45 | //REG_SET_16(REG_FASTCLK_PLL_P, 0x023F); // set P and Q counters (Q=0x02, P=0x3F) 46 | REG_SET_8(REG_FASTCLK_PLL_P, CONFIG_FASTCLK_PLL_P); 47 | REG_SET_8(REG_FASTCLK_PLL_Q, CONFIG_FASTCLK_PLL_Q); 48 | REG_SET_16(REG_FASTCLK_PLL_CFG0, 0x1051); // Set params and Enable PLL 49 | 50 | // Wait up to 250us for the PLL to lock 51 | reg8 pllLock = 0; 52 | reg32 timeout; 53 | // reg32* timeout_p = &timeout; // Is this to avoid a weird optimisation !? 54 | // for (timeout = 250 / 10; *timeout_p && (pllLock != 0x03u); timeout--) 55 | for (timeout = 250 / 10; timeout && (pllLock != 0x03u); timeout--) 56 | { 57 | pllLock = 0x03u & ((pllLock << 1) | ((REG_8(REG_FASTCLK_PLL_SR) & FASTCLK_PLL_SR__LOCKDET) >> 0)); 58 | delay_cycles(10 * CONFIG_SYSTEM_CLOCK_MHZ); /* Delay 10us based on 63MHz clock */ 59 | } 60 | 61 | // Configure Master, Bus Clocks 62 | // IMO (3MHz) -> PLL (*21 -> 63MHz) -> Master(System) Clock (/1) -> Bus Clock (/1) 63 | REG_SET_16(REG_CLKDIST_MSTR0, 0x0100); // sets MSTR1 source = 01 PLL, Divider = 1 64 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x07); // sets Divider = 8 (but resets to 1 below) 65 | //REG_SET_8(REG_CLKDIST_BCFG0, 0x00); // LSB Divider value 66 | //REG_SET_8(REG_CLKDIST_BCFG1, 0x00); // MSB Divider value 67 | REG_SET_8(REG_CLKDIST_BCFG2, (CLKDIST__SSS|CLKDIST__SYNC)); // sync bus to master 68 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x00); // divider value -1 : 0 == source / 1 69 | REG_SET_8(REG_CLKDIST_LD, CLKDIST_LD__SYNC_EN); // restart master clock dividers in phase !? 70 | 71 | // Specify clock ticks for delay library routines (not the hardware) 72 | set_delay_freq(CONFIG_SYSTEM_CLOCK_HZ); 73 | } 74 | 75 | 76 | void SystemInit(void) 77 | { 78 | // NVIC Setup 79 | NVIC_SetPriorityGrouping(4); // 4 is PRIGROUP__3_5 split 80 | SCB->CCR |= (1 << SCB_CCR_STKALIGN_Pos); 81 | 82 | clock_setup(); 83 | 84 | uint32_t ticks = sysclock_ticks_per_ms(); 85 | SysTick_Config(ticks); // so we have one software tick per 'ticks' hardware clock ticks 86 | 87 | // Enable cache and set flash_cycles assuming max clock (50-67MHz) 88 | REG_SET_8(REG_CACHE_CC_CTL, ((CONFIG_INSTRUCTION_CACHE_ENABLED) ? 0x01 : 0x00)); 89 | 90 | app_config(); 91 | 92 | __enable_irq(); // start clock ticking 93 | } 94 | 95 | 96 | uint32_t volatile msTicks; // Counter for millisecond Interval 97 | 98 | void SysTick_Handler(void) 99 | // SysTick Interrupt Handler. Overrides weak reference in startup_ARMCM3.S 100 | // Note this currently executes in ROM. We could move code to RAM for better performance 101 | { 102 | msTicks++; 103 | } 104 | 105 | -------------------------------------------------------------------------------- /demo3b/systeminit.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "core_cm3_psoc5.h" 20 | #include "core_cm3.h" 21 | #include "psoc5.h" 22 | #include "config.h" 23 | 24 | 25 | extern void app_config(void); 26 | 27 | static void clock_setup(void) 28 | { 29 | // Enable/initialise device clocks 30 | 31 | // Configure Internal Low freq Oscillator (ILO) 32 | // Enable 1KHz clock and route to central timewheel (sleep timer) and watchdog timer. 33 | // PSoC TRM Section 16.3 34 | REG_SET_8(REG_SLOWCLK_ILO_CR0, SLOWCLK_ILO__EN_1K); 35 | REG_SET_8(REG_CLKDIST_CR, CLKDIST__ILO_OUT__1K); 36 | 37 | // Configure Internal Main Oscillator (IMO) 38 | // No fast start, no high precision USB clock. (TRM 1.3.31) 39 | REG_SET_8(REG_FASTCLK_IMO_CR, CONFIG_IMO_FREQ_ENUM); 40 | // REG_SET_8(CYREG_IMO_TR1, REG_8(REG_FLSHID_CUST_TABLES_IMO_3MHZ)); 41 | 42 | // Configure PLL 43 | // freq_out = freq_in * (P/(Q+1)). 44 | // Eg: => freq_out ~ 63/3 * freq_in. So freq_out ~ 21 * 3MHz ~ 63MHz 45 | //REG_SET_16(REG_FASTCLK_PLL_P, 0x023F); // set P and Q counters (Q=0x02, P=0x3F) 46 | REG_SET_8(REG_FASTCLK_PLL_P, CONFIG_FASTCLK_PLL_P); 47 | REG_SET_8(REG_FASTCLK_PLL_Q, CONFIG_FASTCLK_PLL_Q); 48 | REG_SET_16(REG_FASTCLK_PLL_CFG0, 0x1051); // Set params and Enable PLL 49 | 50 | // Wait up to 250us for the PLL to lock 51 | reg8 pllLock = 0; 52 | reg32 timeout; 53 | // reg32* timeout_p = &timeout; // Is this to avoid a weird optimisation !? 54 | // for (timeout = 250 / 10; *timeout_p && (pllLock != 0x03u); timeout--) 55 | for (timeout = 250 / 10; timeout && (pllLock != 0x03u); timeout--) 56 | { 57 | pllLock = 0x03u & ((pllLock << 1) | ((REG_8(REG_FASTCLK_PLL_SR) & FASTCLK_PLL_SR__LOCKDET) >> 0)); 58 | delay_cycles(10 * CONFIG_SYSTEM_CLOCK_MHZ); /* Delay 10us based on 63MHz clock */ 59 | } 60 | 61 | // Configure Master, Bus Clocks 62 | // IMO (3MHz) -> PLL (*21 -> 63MHz) -> Master(System) Clock (/1) -> Bus Clock (/1) 63 | REG_SET_16(REG_CLKDIST_MSTR0, 0x0100); // sets MSTR1 source = 01 PLL, Divider = 1 64 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x07); // sets Divider = 8 (but resets to 1 below) 65 | //REG_SET_8(REG_CLKDIST_BCFG0, 0x00); // LSB Divider value 66 | //REG_SET_8(REG_CLKDIST_BCFG1, 0x00); // MSB Divider value 67 | REG_SET_8(REG_CLKDIST_BCFG2, (CLKDIST__SSS|CLKDIST__SYNC)); // sync bus to master 68 | //REG_SET_8(REG_CLKDIST_MSTR0, 0x00); // divider value -1 : 0 == source / 1 69 | REG_SET_8(REG_CLKDIST_LD, CLKDIST_LD__SYNC_EN); // restart master clock dividers in phase !? 70 | 71 | // Specify clock ticks for delay library routines (not the hardware) 72 | set_delay_freq(CONFIG_SYSTEM_CLOCK_HZ); 73 | } 74 | 75 | 76 | void SystemInit(void) 77 | { 78 | // NVIC Setup 79 | NVIC_SetPriorityGrouping(4); // 4 is PRIGROUP__3_5 split 80 | SCB->CCR |= (1 << SCB_CCR_STKALIGN_Pos); 81 | 82 | clock_setup(); 83 | 84 | uint32_t ticks = sysclock_ticks_per_ms(); 85 | SysTick_Config(ticks); // so we have one software tick per 'ticks' hardware clock ticks 86 | 87 | // Enable cache and set flash_cycles assuming max clock (50-67MHz) 88 | REG_SET_8(REG_CACHE_CC_CTL, ((CONFIG_INSTRUCTION_CACHE_ENABLED) ? 0x01 : 0x00)); 89 | 90 | app_config(); 91 | 92 | __enable_irq(); // start clock ticking 93 | } 94 | 95 | 96 | uint32_t volatile msTicks; // Counter for millisecond Interval 97 | 98 | void SysTick_Handler(void) 99 | // SysTick Interrupt Handler. Overrides weak reference in startup_ARMCM3.S 100 | // Note this currently executes in ROM. We could move code to RAM for better performance 101 | { 102 | msTicks++; 103 | } 104 | 105 | -------------------------------------------------------------------------------- /demo3a/gcc_arm.ld.ORIG: -------------------------------------------------------------------------------- 1 | /* Linker script to configure memory regions. */ 2 | MEMORY 3 | { 4 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */ 5 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */ 6 | } 7 | 8 | /* Library configurations */ 9 | GROUP(libgcc.a libc.a libm.a libnosys.a) 10 | 11 | /* Linker script to place sections and symbol values. Should be used together 12 | * with other linker script that defines memory regions FLASH and RAM. 13 | * It references following symbols, which must be defined in code: 14 | * Reset_Handler : Entry of reset handler 15 | * 16 | * It defines following symbols, which code can use without definition: 17 | * __exidx_start 18 | * __exidx_end 19 | * __copy_table_start__ 20 | * __copy_table_end__ 21 | * __zero_table_start__ 22 | * __zero_table_end__ 23 | * __etext 24 | * __data_start__ 25 | * __preinit_array_start 26 | * __preinit_array_end 27 | * __init_array_start 28 | * __init_array_end 29 | * __fini_array_start 30 | * __fini_array_end 31 | * __data_end__ 32 | * __bss_start__ 33 | * __bss_end__ 34 | * __end__ 35 | * end 36 | * __HeapLimit 37 | * __StackLimit 38 | * __StackTop 39 | * __stack 40 | * __Vectors_End 41 | * __Vectors_Size 42 | */ 43 | ENTRY(Reset_Handler) 44 | 45 | SECTIONS 46 | { 47 | .text : 48 | { 49 | KEEP(*(.vectors)) 50 | __Vectors_End = .; 51 | __Vectors_Size = __Vectors_End - __Vectors; 52 | __end__ = .; 53 | 54 | *(.text*) 55 | 56 | KEEP(*(.init)) 57 | KEEP(*(.fini)) 58 | 59 | /* .ctors */ 60 | *crtbegin.o(.ctors) 61 | *crtbegin?.o(.ctors) 62 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 63 | *(SORT(.ctors.*)) 64 | *(.ctors) 65 | 66 | /* .dtors */ 67 | *crtbegin.o(.dtors) 68 | *crtbegin?.o(.dtors) 69 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 70 | *(SORT(.dtors.*)) 71 | *(.dtors) 72 | 73 | *(.rodata*) 74 | 75 | KEEP(*(.eh_frame*)) 76 | } > FLASH 77 | 78 | .ARM.extab : 79 | { 80 | *(.ARM.extab* .gnu.linkonce.armextab.*) 81 | } > FLASH 82 | 83 | __exidx_start = .; 84 | .ARM.exidx : 85 | { 86 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 87 | } > FLASH 88 | __exidx_end = .; 89 | 90 | /* To copy multiple ROM to RAM sections, 91 | * uncomment .copy.table section and, 92 | * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ 93 | /* 94 | .copy.table : 95 | { 96 | . = ALIGN(4); 97 | __copy_table_start__ = .; 98 | LONG (__etext) 99 | LONG (__data_start__) 100 | LONG (__data_end__ - __data_start__) 101 | LONG (__etext2) 102 | LONG (__data2_start__) 103 | LONG (__data2_end__ - __data2_start__) 104 | __copy_table_end__ = .; 105 | } > FLASH 106 | */ 107 | 108 | /* To clear multiple BSS sections, 109 | * uncomment .zero.table section and, 110 | * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ 111 | /* 112 | .zero.table : 113 | { 114 | . = ALIGN(4); 115 | __zero_table_start__ = .; 116 | LONG (__bss_start__) 117 | LONG (__bss_end__ - __bss_start__) 118 | LONG (__bss2_start__) 119 | LONG (__bss2_end__ - __bss2_start__) 120 | __zero_table_end__ = .; 121 | } > FLASH 122 | */ 123 | 124 | __etext = .; 125 | 126 | .data : AT (__etext) 127 | { 128 | __data_start__ = .; 129 | *(vtable) 130 | *(.data*) 131 | 132 | . = ALIGN(4); 133 | /* preinit data */ 134 | PROVIDE_HIDDEN (__preinit_array_start = .); 135 | KEEP(*(.preinit_array)) 136 | PROVIDE_HIDDEN (__preinit_array_end = .); 137 | 138 | . = ALIGN(4); 139 | /* init data */ 140 | PROVIDE_HIDDEN (__init_array_start = .); 141 | KEEP(*(SORT(.init_array.*))) 142 | KEEP(*(.init_array)) 143 | PROVIDE_HIDDEN (__init_array_end = .); 144 | 145 | 146 | . = ALIGN(4); 147 | /* finit data */ 148 | PROVIDE_HIDDEN (__fini_array_start = .); 149 | KEEP(*(SORT(.fini_array.*))) 150 | KEEP(*(.fini_array)) 151 | PROVIDE_HIDDEN (__fini_array_end = .); 152 | 153 | KEEP(*(.jcr*)) 154 | . = ALIGN(4); 155 | /* All data end */ 156 | __data_end__ = .; 157 | 158 | } > RAM 159 | 160 | .bss : 161 | { 162 | . = ALIGN(4); 163 | __bss_start__ = .; 164 | *(.bss*) 165 | *(COMMON) 166 | . = ALIGN(4); 167 | __bss_end__ = .; 168 | } > RAM 169 | 170 | .heap (COPY): 171 | { 172 | __HeapBase = .; 173 | __end__ = .; 174 | end = __end__; 175 | KEEP(*(.heap*)) 176 | __HeapLimit = .; 177 | } > RAM 178 | 179 | /* .stack_dummy section doesn't contains any symbols. It is only 180 | * used for linker to calculate size of stack sections, and assign 181 | * values to stack symbols later */ 182 | .stack_dummy (COPY): 183 | { 184 | KEEP(*(.stack*)) 185 | } > RAM 186 | 187 | /* Set stack top to end of RAM, and stack limit move down by 188 | * size of stack_dummy section */ 189 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 190 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 191 | PROVIDE(__stack = __StackTop); 192 | 193 | /* Check if data + heap + stack exceeds RAM limit */ 194 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 195 | } 196 | -------------------------------------------------------------------------------- /demo2c/app_config.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include 20 | #include "libc.h" 21 | 22 | 23 | #if DEBUG 24 | #include 25 | #include 26 | #include 27 | #include 28 | #endif 29 | 30 | 31 | // Config Table Types 32 | #define CFG_TT_END 0 33 | #define CFG_TT_CF 1 34 | #define CFG_TT_OV 2 35 | #define CFG_TT_DA 3 36 | #define CFG_TT_AC 4 37 | 38 | #define config_base_addr ((const uint8_t *)0x48000000) 39 | 40 | static void cfg_set_regions(const uint8_t *cfg_base_addr) 41 | { 42 | // Note: count is [cc]cc + 1. Zero is not allowed except in END case. 43 | 44 | // table: [ ttcc aaaa aaaa ]* 0000 0000 45 | // tt = type, cc = value|00 46 | // element: tt == 1: constant fill subtable 47 | // ccvv # cccc 48 | // element: tt == 2: offset value subtable 49 | // [ oovv ]+(cc) 50 | // element: tt == 3: data array subtable 51 | // [ vv ]+(cc) 52 | // element: tt == 4: address copy subtable 53 | // ssss ssss 54 | 55 | //uint32_t *tablebase = &config_base_addr[0]; 56 | // WARNING for compactness 32 bit addresses are NOT aligned on relevant memory boundaries. 57 | // easiest way to manage data is 8 bit chunks. (unless I pad case 3 for cc == 1) 58 | 59 | const uint8_t *tbl = cfg_base_addr; 60 | while(1) 61 | { 62 | uint8_t table_type = tbl[0]; 63 | uint32_t count = tbl[1] + 1; // Note + 1. uint32_t to handle count=63336. 64 | 65 | #if DEBUG 66 | printf("Table Type: %d\n", table_type); 67 | #endif 68 | if (table_type == CFG_TT_END) break; 69 | 70 | uint32_t addr = (tbl[5] << 24) | (tbl[4] << 16) | (tbl[3] << 8) | tbl[2]; 71 | uint8_t *ap = (uint8_t *)(intptr_t)addr; 72 | 73 | tbl += 6; 74 | 75 | if (table_type == CFG_TT_CF) 76 | { 77 | // constant fill: ccvv 78 | uint8_t count_hi = tbl[0]; 79 | uint8_t value = tbl[1]; 80 | count += (count_hi << 8); 81 | #if DEBUG 82 | printf(" CF: %p = 0x%02x * %d\n", ap, value, count); 83 | #else 84 | memset(ap, value, count); 85 | #endif 86 | tbl += 2; 87 | } 88 | else if (table_type == CFG_TT_OV) 89 | { 90 | // offset value: [ oovv ]+(count) 91 | uint8_t i; 92 | for(i=0; i. 17 | */ 18 | 19 | #include 20 | #include "libc.h" 21 | 22 | 23 | #if DEBUG 24 | #include 25 | #include 26 | #include 27 | #include 28 | #endif 29 | 30 | 31 | // Config Table Types 32 | #define CFG_TT_END 0 33 | #define CFG_TT_CF 1 34 | #define CFG_TT_OV 2 35 | #define CFG_TT_DA 3 36 | #define CFG_TT_AC 4 37 | 38 | #define config_base_addr ((const uint8_t *)0x48000000) 39 | 40 | static void cfg_set_regions(const uint8_t *cfg_base_addr) 41 | { 42 | // Note: count is [cc]cc + 1. Zero is not allowed except in END case. 43 | 44 | // table: [ ttcc aaaa aaaa ]* 0000 0000 45 | // tt = type, cc = value|00 46 | // element: tt == 1: constant fill subtable 47 | // ccvv # cccc 48 | // element: tt == 2: offset value subtable 49 | // [ oovv ]+(cc) 50 | // element: tt == 3: data array subtable 51 | // [ vv ]+(cc) 52 | // element: tt == 4: address copy subtable 53 | // ssss ssss 54 | 55 | //uint32_t *tablebase = &config_base_addr[0]; 56 | // WARNING for compactness 32 bit addresses are NOT aligned on relevant memory boundaries. 57 | // easiest way to manage data is 8 bit chunks. (unless I pad case 3 for cc == 1) 58 | 59 | const uint8_t *tbl = cfg_base_addr; 60 | while(1) 61 | { 62 | uint8_t table_type = tbl[0]; 63 | uint32_t count = tbl[1] + 1; // Note + 1. uint32_t to handle count=63336. 64 | 65 | #if DEBUG 66 | printf("Table Type: %d\n", table_type); 67 | #endif 68 | if (table_type == CFG_TT_END) break; 69 | 70 | uint32_t addr = (tbl[5] << 24) | (tbl[4] << 16) | (tbl[3] << 8) | tbl[2]; 71 | uint8_t *ap = (uint8_t *)(intptr_t)addr; 72 | 73 | tbl += 6; 74 | 75 | if (table_type == CFG_TT_CF) 76 | { 77 | // constant fill: ccvv 78 | uint8_t count_hi = tbl[0]; 79 | uint8_t value = tbl[1]; 80 | count += (count_hi << 8); 81 | #if DEBUG 82 | printf(" CF: %p = 0x%02x * %d\n", ap, value, count); 83 | #else 84 | memset(ap, value, count); 85 | #endif 86 | tbl += 2; 87 | } 88 | else if (table_type == CFG_TT_OV) 89 | { 90 | // offset value: [ oovv ]+(count) 91 | uint8_t i; 92 | for(i=0; i. 17 | */ 18 | 19 | #include 20 | #include "libc.h" 21 | 22 | 23 | #if DEBUG 24 | #include 25 | #include 26 | #include 27 | #include 28 | #endif 29 | 30 | 31 | // Config Table Types 32 | #define CFG_TT_END 0 33 | #define CFG_TT_CF 1 34 | #define CFG_TT_OV 2 35 | #define CFG_TT_DA 3 36 | #define CFG_TT_AC 4 37 | 38 | #define config_base_addr ((const uint8_t *)0x48000000) 39 | 40 | static void cfg_set_regions(const uint8_t *cfg_base_addr) 41 | { 42 | // Note: count is [cc]cc + 1. Zero is not allowed except in END case. 43 | 44 | // table: [ ttcc aaaa aaaa ]* 0000 0000 45 | // tt = type, cc = value|00 46 | // element: tt == 1: constant fill subtable 47 | // ccvv # cccc 48 | // element: tt == 2: offset value subtable 49 | // [ oovv ]+(cc) 50 | // element: tt == 3: data array subtable 51 | // [ vv ]+(cc) 52 | // element: tt == 4: address copy subtable 53 | // ssss ssss 54 | 55 | //uint32_t *tablebase = &config_base_addr[0]; 56 | // WARNING for compactness 32 bit addresses are NOT aligned on relevant memory boundaries. 57 | // easiest way to manage data is 8 bit chunks. (unless I pad case 3 for cc == 1) 58 | 59 | const uint8_t *tbl = cfg_base_addr; 60 | while(1) 61 | { 62 | uint8_t table_type = tbl[0]; 63 | uint32_t count = tbl[1] + 1; // Note + 1. uint32_t to handle count=63336. 64 | 65 | #if DEBUG 66 | printf("Table Type: %d\n", table_type); 67 | #endif 68 | if (table_type == CFG_TT_END) break; 69 | 70 | uint32_t addr = (tbl[5] << 24) | (tbl[4] << 16) | (tbl[3] << 8) | tbl[2]; 71 | uint8_t *ap = (uint8_t *)(intptr_t)addr; 72 | 73 | tbl += 6; 74 | 75 | if (table_type == CFG_TT_CF) 76 | { 77 | // constant fill: ccvv 78 | uint8_t count_hi = tbl[0]; 79 | uint8_t value = tbl[1]; 80 | count += (count_hi << 8); 81 | #if DEBUG 82 | printf(" CF: %p = 0x%02x * %d\n", ap, value, count); 83 | #else 84 | memset(ap, value, count); 85 | #endif 86 | tbl += 2; 87 | } 88 | else if (table_type == CFG_TT_OV) 89 | { 90 | // offset value: [ oovv ]+(count) 91 | uint8_t i; 92 | for(i=0; i. 17 | */ 18 | 19 | #include 20 | #include "libc.h" 21 | 22 | 23 | #if DEBUG 24 | #include 25 | #include 26 | #include 27 | #include 28 | #endif 29 | 30 | 31 | // Config Table Types 32 | #define CFG_TT_END 0 33 | #define CFG_TT_CF 1 34 | #define CFG_TT_OV 2 35 | #define CFG_TT_DA 3 36 | #define CFG_TT_AC 4 37 | 38 | #define config_base_addr ((const uint8_t *)0x48000000) 39 | 40 | static void cfg_set_regions(const uint8_t *cfg_base_addr) 41 | { 42 | // Note: count is [cc]cc + 1. Zero is not allowed except in END case. 43 | 44 | // table: [ ttcc aaaa aaaa ]* 0000 0000 45 | // tt = type, cc = value|00 46 | // element: tt == 1: constant fill subtable 47 | // ccvv # cccc 48 | // element: tt == 2: offset value subtable 49 | // [ oovv ]+(cc) 50 | // element: tt == 3: data array subtable 51 | // [ vv ]+(cc) 52 | // element: tt == 4: address copy subtable 53 | // ssss ssss 54 | 55 | //uint32_t *tablebase = &config_base_addr[0]; 56 | // WARNING for compactness 32 bit addresses are NOT aligned on relevant memory boundaries. 57 | // easiest way to manage data is 8 bit chunks. (unless I pad case 3 for cc == 1) 58 | 59 | const uint8_t *tbl = cfg_base_addr; 60 | while(1) 61 | { 62 | uint8_t table_type = tbl[0]; 63 | uint32_t count = tbl[1] + 1; // Note + 1. uint32_t to handle count=63336. 64 | 65 | #if DEBUG 66 | printf("Table Type: %d\n", table_type); 67 | #endif 68 | if (table_type == CFG_TT_END) break; 69 | 70 | uint32_t addr = (tbl[5] << 24) | (tbl[4] << 16) | (tbl[3] << 8) | tbl[2]; 71 | uint8_t *ap = (uint8_t *)(intptr_t)addr; 72 | 73 | tbl += 6; 74 | 75 | if (table_type == CFG_TT_CF) 76 | { 77 | // constant fill: ccvv 78 | uint8_t count_hi = tbl[0]; 79 | uint8_t value = tbl[1]; 80 | count += (count_hi << 8); 81 | #if DEBUG 82 | printf(" CF: %p = 0x%02x * %d\n", ap, value, count); 83 | #else 84 | memset(ap, value, count); 85 | #endif 86 | tbl += 2; 87 | } 88 | else if (table_type == CFG_TT_OV) 89 | { 90 | // offset value: [ oovv ]+(count) 91 | uint8_t i; 92 | for(i=0; i FLASH 85 | 86 | .ARM.extab : 87 | { 88 | *(.ARM.extab* .gnu.linkonce.armextab.*) 89 | } > FLASH 90 | 91 | __exidx_start = .; 92 | .ARM.exidx : 93 | { 94 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 95 | } > FLASH 96 | __exidx_end = .; 97 | 98 | /* To copy multiple ROM to RAM sections, 99 | * uncomment .copy.table section and, 100 | * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ 101 | /* 102 | .copy.table : 103 | { 104 | . = ALIGN(4); 105 | __copy_table_start__ = .; 106 | LONG (__etext) 107 | LONG (__data_start__) 108 | LONG (__data_end__ - __data_start__) 109 | LONG (__etext2) 110 | LONG (__data2_start__) 111 | LONG (__data2_end__ - __data2_start__) 112 | __copy_table_end__ = .; 113 | } > FLASH 114 | */ 115 | 116 | /* To clear multiple BSS sections, 117 | * uncomment .zero.table section and, 118 | * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ 119 | /* 120 | .zero.table : 121 | { 122 | . = ALIGN(4); 123 | __zero_table_start__ = .; 124 | LONG (__bss_start__) 125 | LONG (__bss_end__ - __bss_start__) 126 | LONG (__bss2_start__) 127 | LONG (__bss2_end__ - __bss2_start__) 128 | __zero_table_end__ = .; 129 | } > FLASH 130 | */ 131 | 132 | __etext = .; 133 | 134 | .data : AT (__etext) 135 | { 136 | __data_start__ = .; 137 | /* 138 | We probably don't actually need this 139 | . = ALIGN(0x100); 140 | *(.vectors_ram) 141 | 142 | . = ALIGN(4); 143 | */ 144 | *(vtable) 145 | *(.data*) 146 | 147 | . = ALIGN(4); 148 | /* preinit data */ 149 | PROVIDE_HIDDEN (__preinit_array_start = .); 150 | KEEP(*(.preinit_array)) 151 | PROVIDE_HIDDEN (__preinit_array_end = .); 152 | 153 | . = ALIGN(4); 154 | /* init data */ 155 | PROVIDE_HIDDEN (__init_array_start = .); 156 | KEEP(*(SORT(.init_array.*))) 157 | KEEP(*(.init_array)) 158 | PROVIDE_HIDDEN (__init_array_end = .); 159 | 160 | 161 | . = ALIGN(4); 162 | /* finit data */ 163 | PROVIDE_HIDDEN (__fini_array_start = .); 164 | KEEP(*(SORT(.fini_array.*))) 165 | KEEP(*(.fini_array)) 166 | PROVIDE_HIDDEN (__fini_array_end = .); 167 | 168 | KEEP(*(.jcr*)) 169 | . = ALIGN(4); 170 | /* All data end */ 171 | __data_end__ = .; 172 | 173 | } > RAM 174 | 175 | .bss : 176 | { 177 | . = ALIGN(4); 178 | __bss_start__ = .; 179 | *(.bss*) 180 | *(COMMON) 181 | . = ALIGN(4); 182 | __bss_end__ = .; 183 | } > RAM 184 | 185 | .heap (COPY): 186 | { 187 | __HeapBase = .; 188 | __end__ = .; 189 | end = __end__; 190 | KEEP(*(.heap*)) 191 | __HeapLimit = .; 192 | } > RAM 193 | 194 | /* .stack_dummy section doesn't contains any symbols. It is only 195 | * used for linker to calculate size of stack sections, and assign 196 | * values to stack symbols later */ 197 | .stack_dummy (COPY): 198 | { 199 | KEEP(*(.stack*)) 200 | } > RAM 201 | 202 | __HeapStart = __HeapBase; /* minilibc uses __HeapStart */ 203 | 204 | /* Set stack top to end of RAM, and stack limit move down by 205 | * size of stack_dummy section */ 206 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 207 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 208 | PROVIDE(__stack = __StackTop); 209 | 210 | /* Check if data + heap + stack exceeds RAM limit */ 211 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 212 | } 213 | -------------------------------------------------------------------------------- /demo3b/gcc.ld: -------------------------------------------------------------------------------- 1 | /* Linker script to configure memory regions. */ 2 | MEMORY 3 | { 4 | FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K */ 5 | RAM (rwx) : ORIGIN = 0x20000000 - (0x10000 / 2), LENGTH = 0x10000 /* 64K */ 6 | 7 | /* NOTE: RAM is split into two halves. They are on different buses internally. 8 | * BOTTOM is 'CODE' RAM and should contain: ISR table, ISR code and speed critical code 9 | * TOP is 'DATA' RAM and should contain stack, heap etc. 10 | * ** This split hasn't be done in this version. ** 11 | * Data can be put into 'CODE' and vice versa but there will be performance penalties 12 | * See TRM 1.3.5 and 1.3.6 13 | */ 14 | } 15 | 16 | /* Library configurations */ 17 | /* GROUP(libgcc.a libc.a libm.a libnosys.a) */ 18 | 19 | /* Linker script to place sections and symbol values. Should be used together 20 | * with other linker script that defines memory regions FLASH and RAM. 21 | * It references following symbols, which must be defined in code: 22 | * Reset_Handler : Entry of reset handler 23 | * 24 | * It defines following symbols, which code can use without definition: 25 | * __exidx_start 26 | * __exidx_end 27 | * __copy_table_start__ 28 | * __copy_table_end__ 29 | * __zero_table_start__ 30 | * __zero_table_end__ 31 | * __etext 32 | * __data_start__ 33 | * __preinit_array_start 34 | * __preinit_array_end 35 | * __init_array_start 36 | * __init_array_end 37 | * __fini_array_start 38 | * __fini_array_end 39 | * __data_end__ 40 | * __bss_start__ 41 | * __bss_end__ 42 | * __end__ 43 | * end 44 | * __HeapLimit 45 | * __StackLimit 46 | * __StackTop 47 | * __stack 48 | * __Vectors_End 49 | * __Vectors_Size 50 | */ 51 | ENTRY(Reset_Handler) 52 | 53 | SECTIONS 54 | { 55 | .text : 56 | { 57 | KEEP(*(.vectors)) 58 | __Vectors_End = .; 59 | __Vectors_Size = __Vectors_End - __Vectors; 60 | __end__ = .; 61 | 62 | *(.text*) 63 | 64 | KEEP(*(.init)) 65 | KEEP(*(.fini)) 66 | 67 | /* .ctors */ 68 | *crtbegin.o(.ctors) 69 | *crtbegin?.o(.ctors) 70 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 71 | *(SORT(.ctors.*)) 72 | *(.ctors) 73 | 74 | /* .dtors */ 75 | *crtbegin.o(.dtors) 76 | *crtbegin?.o(.dtors) 77 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 78 | *(SORT(.dtors.*)) 79 | *(.dtors) 80 | 81 | *(.rodata*) 82 | 83 | KEEP(*(.eh_frame*)) 84 | } > FLASH 85 | 86 | .ARM.extab : 87 | { 88 | *(.ARM.extab* .gnu.linkonce.armextab.*) 89 | } > FLASH 90 | 91 | __exidx_start = .; 92 | .ARM.exidx : 93 | { 94 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 95 | } > FLASH 96 | __exidx_end = .; 97 | 98 | /* To copy multiple ROM to RAM sections, 99 | * uncomment .copy.table section and, 100 | * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ 101 | /* 102 | .copy.table : 103 | { 104 | . = ALIGN(4); 105 | __copy_table_start__ = .; 106 | LONG (__etext) 107 | LONG (__data_start__) 108 | LONG (__data_end__ - __data_start__) 109 | LONG (__etext2) 110 | LONG (__data2_start__) 111 | LONG (__data2_end__ - __data2_start__) 112 | __copy_table_end__ = .; 113 | } > FLASH 114 | */ 115 | 116 | /* To clear multiple BSS sections, 117 | * uncomment .zero.table section and, 118 | * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ 119 | /* 120 | .zero.table : 121 | { 122 | . = ALIGN(4); 123 | __zero_table_start__ = .; 124 | LONG (__bss_start__) 125 | LONG (__bss_end__ - __bss_start__) 126 | LONG (__bss2_start__) 127 | LONG (__bss2_end__ - __bss2_start__) 128 | __zero_table_end__ = .; 129 | } > FLASH 130 | */ 131 | 132 | __etext = .; 133 | 134 | .data : AT (__etext) 135 | { 136 | __data_start__ = .; 137 | /* 138 | We probably don't actually need this 139 | . = ALIGN(0x100); 140 | *(.vectors_ram) 141 | 142 | . = ALIGN(4); 143 | */ 144 | *(vtable) 145 | *(.data*) 146 | 147 | . = ALIGN(4); 148 | /* preinit data */ 149 | PROVIDE_HIDDEN (__preinit_array_start = .); 150 | KEEP(*(.preinit_array)) 151 | PROVIDE_HIDDEN (__preinit_array_end = .); 152 | 153 | . = ALIGN(4); 154 | /* init data */ 155 | PROVIDE_HIDDEN (__init_array_start = .); 156 | KEEP(*(SORT(.init_array.*))) 157 | KEEP(*(.init_array)) 158 | PROVIDE_HIDDEN (__init_array_end = .); 159 | 160 | 161 | . = ALIGN(4); 162 | /* finit data */ 163 | PROVIDE_HIDDEN (__fini_array_start = .); 164 | KEEP(*(SORT(.fini_array.*))) 165 | KEEP(*(.fini_array)) 166 | PROVIDE_HIDDEN (__fini_array_end = .); 167 | 168 | KEEP(*(.jcr*)) 169 | . = ALIGN(4); 170 | /* All data end */ 171 | __data_end__ = .; 172 | 173 | } > RAM 174 | 175 | .bss : 176 | { 177 | . = ALIGN(4); 178 | __bss_start__ = .; 179 | *(.bss*) 180 | *(COMMON) 181 | . = ALIGN(4); 182 | __bss_end__ = .; 183 | } > RAM 184 | 185 | .heap (COPY): 186 | { 187 | __HeapBase = .; 188 | __end__ = .; 189 | end = __end__; 190 | KEEP(*(.heap*)) 191 | __HeapLimit = .; 192 | } > RAM 193 | 194 | /* .stack_dummy section doesn't contains any symbols. It is only 195 | * used for linker to calculate size of stack sections, and assign 196 | * values to stack symbols later */ 197 | .stack_dummy (COPY): 198 | { 199 | KEEP(*(.stack*)) 200 | } > RAM 201 | 202 | __HeapStart = __HeapBase; /* minilibc uses __HeapStart */ 203 | 204 | /* Set stack top to end of RAM, and stack limit move down by 205 | * size of stack_dummy section */ 206 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 207 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 208 | PROVIDE(__stack = __StackTop); 209 | 210 | /* Check if data + heap + stack exceeds RAM limit */ 211 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 212 | } 213 | -------------------------------------------------------------------------------- /common/hw/lcd.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2014 Kim Lester 3 | http://www.dfusion.com.au/ 4 | 5 | This Program is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | This Program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with this Program. If not, see . 17 | */ 18 | 19 | #include "lcd.h" 20 | #include "lcd_hd44780.h" 21 | #include "lcd_hw.h" 22 | 23 | 24 | // Convenience functions 25 | 26 | // Used by LCD_moveto() 27 | // Notes: 28 | // Assumes each row is contiguous from start address. Not all are. 29 | // Last two in particular depend on variant. Eg see http://www.8052.com/tutlcd2.php 30 | static uint8_t LCD_row_table[] = {0x00, 0x40, 0x00, 0x00}; // last two not set 31 | 32 | 33 | void LCD_write_string(uint8_t *str) 34 | { 35 | uint8_t *bp = str; 36 | 37 | while(*bp) 38 | { 39 | LCD_write_byte(*bp++, LCD_DATA); 40 | } 41 | } 42 | 43 | 44 | void LCD_write_stringn(uint8_t *str, int n) 45 | { 46 | uint8_t *bp = str; 47 | 48 | while(n--) 49 | { 50 | LCD_write_byte(*bp++, LCD_DATA); 51 | } 52 | } 53 | 54 | 55 | void LCD_write_cmd(uint8_t data) 56 | { 57 | LCD_write_byte(data, LCD_CONTROL); 58 | } 59 | 60 | 61 | void LCD_write_data(uint8_t data) 62 | { 63 | LCD_write_byte(data, LCD_DATA); 64 | } 65 | 66 | 67 | void LCD_clear(void) 68 | { 69 | LCD_write_byte(HD44780_DISPLAY_CLEAR, LCD_CONTROL); 70 | } 71 | 72 | 73 | void LCD_home(void) 74 | { 75 | LCD_write_byte(HD44780_HOME, LCD_CONTROL); 76 | } 77 | 78 | 79 | void LCD_display_on(bool enable) 80 | { 81 | uint8_t data = HD44780_DISPLAY; 82 | data |= (enable ? HD44870_D_DISP_ON : HD44870_D_DISP_OFF); 83 | 84 | LCD_write_byte(data, LCD_CONTROL); 85 | } 86 | 87 | 88 | void LCD_cursor(bool cursor_en, bool blinking_en) 89 | { 90 | // Note: forces display on too (since we need to set D to something) 91 | uint8_t data = HD44780_DISPLAY; 92 | data |= HD44870_D_DISP_ON; 93 | data |= (cursor_en ? HD44870_D_CURS_ON : HD44870_D_CURS_OFF); 94 | data |= (blinking_en ? HD44870_D_BLINK_ON : HD44870_D_BLINK_OFF); 95 | 96 | LCD_write_byte(data, LCD_CONTROL); 97 | } 98 | 99 | 100 | void LCD_moveto(uint8_t x, uint8_t y) 101 | { 102 | // Note: not bounds checking x,y 103 | if (y > 3) return; // better to do nothing 104 | 105 | LCD_write_byte(HD44780_DDRAM_ADDR | (LCD_row_table[y] + x), LCD_CONTROL); 106 | } 107 | 108 | 109 | 110 | // Core interface 111 | 112 | void LCD_write_byte(uint8_t data, uint8_t type) 113 | { 114 | // type: 0 control, 1: data 115 | // Assume E == 0 116 | 117 | LCD_write_nibble((data >> 4), type); // write hi first 118 | LCD_write_nibble((data & 0x0F), type); // write lo 119 | } 120 | 121 | 122 | void LCD_init_4bit(uint8_t lines, uint8_t font) 123 | { 124 | // Note: Only supports 1,2 line displays 125 | // font: LCD_FONT_* (Note: Many displays can't do 5x10) 126 | 127 | // At reset: 128 | // Config: 8 bit, 1 line, 5x8 font 129 | // Display clear, Display off, Cursor off, Blinking off 130 | // Entry mode: Inc, No shift 131 | 132 | // At end of this func we just turn display on 133 | 134 | LCD_port_write_mode(); 135 | 136 | #if 1 137 | // This for re-init (note BF can't be checked hence fixed timings) 138 | delay_ms(100); // some say >= 40ms some say 100ms 139 | LCD_write_nibble(0x3, LCD_CONTROL); // 8 bit mode - just one nibble 140 | delay_ms(5); // >= 4.1ms 141 | LCD_write_nibble(0x3, LCD_CONTROL); // 8 bit mode - just one nibble 142 | delay_us(1); // >= 100us 143 | 144 | LCD_write_nibble(0x3, LCD_CONTROL); // 8 bit mode - just one nibble 145 | delay_us(1); // >= 100us assumed 146 | #endif 147 | LCD_write_nibble(0x2, LCD_CONTROL); // 4 bit mode - just one nibble 148 | //delay_us(1); // >= 100us assumed 149 | 150 | uint8_t data = HD44780_FUNC; 151 | data |= (lines ? HD44870_F_LINES_2 : HD44870_F_LINES_1); 152 | data |= (font == LCD_FONT_5x10 ? HD44870_F_FONT_5x10 : HD44870_F_FONT_5x8); 153 | LCD_write_byte(data, LCD_CONTROL); // lines and font 154 | 155 | LCD_clear(); // Without clearing display contents remain over soft resets 156 | LCD_display_on(true); 157 | } 158 | 159 | 160 | void LCD_wait_ready(void) 161 | { 162 | // wait until Busy Flag (BF) is 0 163 | // We have to change port pin directions for read 164 | 165 | LCD_port_read_mode(); 166 | 167 | uint8_t data = 0; 168 | 169 | #if 0 170 | delay_ms(2); // worst case (most are 40us) 171 | #else 172 | // wait until Busy Flag is 0 173 | while ((data = LCD_read_byte()) & HD44870_BF) 174 | ; 175 | #endif 176 | 177 | LCD_port_write_mode(); 178 | } 179 | 180 | 181 | // HAL 182 | // Assumes 4 bit mode, all IO lines in on one port, data bits contiguous. This can be changed manually 183 | 184 | void LCD_write_nibble(uint8_t nibble, uint8_t type) 185 | { 186 | // type: LCD_CONTROL:0, LCD_DATA:1 187 | // Assume E == 0 188 | 189 | LCD_wait_ready(); 190 | 191 | // RW=0: write, RS = 0: control / 1: Data 192 | *LCD_PORT_DR_REG = (*LCD_PORT_DR_REG & ~(LCD_RW | LCD_RS) | (type ? LCD_RS : 0)); 193 | 194 | // Addr (RS, R/nW to E) setup time 40ns min. These instructions are enough !? 195 | *LCD_PORT_DR_REG = ((*LCD_PORT_DR_REG & ~LCD_DATA_MASK_4BIT) | ((nibble & 0x0F) << LCD_DATA_OFFSET)); // Set data 196 | 197 | *LCD_PORT_DR_REG |= LCD_E; // E=1, set data 198 | 199 | delay_us(1); // PWeh = 230ns 200 | 201 | *LCD_PORT_DR_REG &= ~LCD_E; // E = 0 202 | } 203 | 204 | 205 | uint8_t LCD_read_byte(void) 206 | { 207 | // Assumes port I/O direction has been set to read first 208 | uint8_t data = 0; 209 | 210 | *LCD_PORT_DR_REG = (*LCD_PORT_DR_REG & ~LCD_RS) | LCD_RW; // RS=0: control, R/nW = 1: read 211 | 212 | // Addr (RS, R/nW to E) setup time 40ns min. Need a short delay 213 | delay_us(0); 214 | 215 | // Min E period tcycE = 500ns 216 | 217 | *LCD_PORT_DR_REG |= LCD_E; // E = 1 218 | delay_us(1); // 230ns PWeh 219 | data = (*LCD_PORT_PS_REG << 4); // read upper 4 bits 220 | *LCD_PORT_DR_REG &= ~LCD_E; // E = 0 221 | 222 | delay_us(0); 223 | 224 | *LCD_PORT_DR_REG |= LCD_E; // E = 1 225 | delay_us(1); // 230ns PWeh 226 | data |= *LCD_PORT_PS_REG; 227 | *LCD_PORT_DR_REG &= ~LCD_E; // E = 0 228 | 229 | return data; 230 | } 231 | 232 | 233 | void LCD_port_read_mode(void) 234 | { 235 | *LCD_PORT_DM0_REG = (*LCD_PORT_DM0_REG & ~LCD_DATA_MASK_4BIT) 236 | | (LCD_HIGH_Z_DM0 & LCD_DATA_MASK_4BIT); 237 | *LCD_PORT_DM1_REG = (*LCD_PORT_DM1_REG & ~LCD_DATA_MASK_4BIT) 238 | | (LCD_HIGH_Z_DM1 & LCD_DATA_MASK_4BIT); 239 | *LCD_PORT_DM2_REG = (*LCD_PORT_DM2_REG & ~LCD_DATA_MASK_4BIT) 240 | | (LCD_HIGH_Z_DM2 & LCD_DATA_MASK_4BIT); 241 | } 242 | 243 | 244 | void LCD_port_write_mode(void) 245 | { 246 | *LCD_PORT_DR_REG = 0; // E = 0 etc 247 | 248 | *LCD_PORT_DM0_REG = (*LCD_PORT_DM0_REG & ~LCD_DATA_MASK_4BIT) 249 | | (LCD_STRONG_DM0 & LCD_DATA_MASK_4BIT); 250 | *LCD_PORT_DM1_REG = (*LCD_PORT_DM1_REG & ~LCD_DATA_MASK_4BIT) 251 | | (LCD_STRONG_DM1 & LCD_DATA_MASK_4BIT); 252 | *LCD_PORT_DM2_REG = (*LCD_PORT_DM2_REG & ~LCD_DATA_MASK_4BIT) 253 | | (LCD_STRONG_DM2 & LCD_DATA_MASK_4BIT); 254 | } 255 | -------------------------------------------------------------------------------- /demo1/startup_ARMCM3.S: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.S 2 | * Purpose: startup file for Cortex-M3 devices. Should use with 3 | * GCC for ARM Embedded Processors 4 | * Orig Version: V2.0 5 | * Orig Date: 16 August 2013 6 | * Copyright (c) 2011 - 2013 ARM LIMITED 7 | * 8 | * Modified: (for PSoC 5) KRL, Datafusion, 2014 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | .syntax unified 35 | .arch armv7-m 36 | 37 | .section .isr_vector 38 | .align 2 39 | .globl __isr_vector 40 | __isr_vector: 41 | .long __StackTop /* Top of Stack */ 42 | .long Reset_Handler /* Reset Handler */ 43 | .long NMI_Handler /* NMI Handler */ 44 | .long HardFault_Handler /* Hard Fault Handler */ 45 | .long MemManage_Handler /* MPU Fault Handler */ 46 | .long BusFault_Handler /* Bus Fault Handler */ 47 | .long UsageFault_Handler /* Usage Fault Handler */ 48 | .long 0 /* Reserved */ 49 | .long 0 /* Reserved */ 50 | .long 0 /* Reserved */ 51 | .long 0 /* Reserved */ 52 | .long SVC_Handler /* SVCall Handler */ 53 | .long DebugMon_Handler /* Debug Monitor Handler */ 54 | .long 0 /* Reserved */ 55 | .long PendSV_Handler /* PendSV Handler */ 56 | .long SysTick_Handler /* SysTick Handler */ 57 | 58 | /* 32 IRQs */ 59 | .long Default_IRQ_Handler /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 60 | .long Default_IRQ_Handler /* 1: Cache / phub_to_0[1] / usb_int[1] */ 61 | .long 0 /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 62 | .long Default_IRQ_Handler /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 63 | .long Default_IRQ_Handler /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 64 | .long Default_IRQ_Handler /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 65 | .long Default_IRQ_Handler /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 66 | .long Default_IRQ_Handler /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 67 | .long Default_IRQ_Handler /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 68 | .long Default_IRQ_Handler /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 69 | .long Default_IRQ_Handler /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 70 | .long Default_IRQ_Handler /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 71 | .long Default_IRQ_Handler /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 72 | .long Default_IRQ_Handler /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 73 | .long Default_IRQ_Handler /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 74 | .long Default_IRQ_Handler /* 15: I2C / phub_to_0[15] / usb_int[15] */ 75 | .long 0 /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 76 | .long 0 /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 77 | .long 0 /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 78 | .long 0 /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 79 | .long 0 /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 80 | .long Default_IRQ_Handler /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 81 | .long Default_IRQ_Handler /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 82 | .long Default_IRQ_Handler /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 83 | .long Default_IRQ_Handler /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 84 | .long Default_IRQ_Handler /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 85 | .long 0 /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 86 | .long 0 /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 87 | .long Default_IRQ_Handler /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 88 | .long Default_IRQ_Handler /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 89 | .long Default_IRQ_Handler /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 90 | .long Default_IRQ_Handler /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 91 | 92 | .size __isr_vector, . - __isr_vector 93 | 94 | .text 95 | .thumb 96 | .thumb_func 97 | .align 2 98 | .globl Reset_Handler 99 | .type Reset_Handler, %function 100 | Reset_Handler: 101 | 102 | /* Firstly it copies data from read only memory to RAM. 103 | * 104 | * The ranges of copy from/to are specified by following symbols 105 | * __etext: LMA of start of the section to copy from. Usually end of text 106 | * __data_start__: VMA of start of the section to copy to 107 | * __data_end__: VMA of end of the section to copy to 108 | * 109 | * All addresses must be aligned to 4 bytes boundary. 110 | */ 111 | ldr r1, =__etext 112 | ldr r2, =__data_start__ 113 | ldr r3, =__data_end__ 114 | 115 | .L_loop1: 116 | cmp r2, r3 117 | ittt lt 118 | ldrlt r0, [r1], #4 119 | strlt r0, [r2], #4 120 | blt .L_loop1 121 | 122 | 123 | /* This part of work usually is done in C library startup code. Otherwise, 124 | * define this macro to enable it in this startup. 125 | * 126 | * The BSS section is specified by following symbols 127 | * __bss_start__: start of the BSS section. 128 | * __bss_end__: end of the BSS section. 129 | * 130 | * Both addresses must be aligned to 4 bytes boundary. 131 | */ 132 | ldr r1, =__bss_start__ 133 | ldr r2, =__bss_end__ 134 | 135 | movs r0, 0 136 | .L_loop3: 137 | cmp r1, r2 138 | itt lt 139 | strlt r0, [r1], #4 140 | blt .L_loop3 141 | 142 | bl SystemInit 143 | 144 | bl _start 145 | 146 | .pool 147 | .size Reset_Handler, . - Reset_Handler 148 | 149 | .align 1 150 | .thumb_func 151 | .weak Default_Handler 152 | .type Default_Handler, %function 153 | Default_Handler: 154 | b . 155 | .size Default_Handler, . - Default_Handler 156 | 157 | /* Macro to define default handlers as dead loops with weak linking */ 158 | .macro def_irq_handler handler_name 159 | .weak \handler_name 160 | .set \handler_name, Default_Handler 161 | .endm 162 | 163 | def_irq_handler NMI_Handler 164 | def_irq_handler HardFault_Handler 165 | def_irq_handler MemManage_Handler 166 | def_irq_handler BusFault_Handler 167 | def_irq_handler UsageFault_Handler 168 | def_irq_handler SVC_Handler 169 | def_irq_handler DebugMon_Handler 170 | def_irq_handler PendSV_Handler 171 | def_irq_handler SysTick_Handler 172 | def_irq_handler Default_IRQ_Handler 173 | 174 | .end 175 | -------------------------------------------------------------------------------- /demo2a/startup_ARMCM3.S: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.S 2 | * Purpose: startup file for Cortex-M3 devices. Should use with 3 | * GCC for ARM Embedded Processors 4 | * Orig Version: V2.0 5 | * Orig Date: 16 August 2013 6 | * Copyright (c) 2011 - 2013 ARM LIMITED 7 | * 8 | * Modified: (for PSoC 5) KRL, Datafusion, 2014 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | .syntax unified 35 | .arch armv7-m 36 | 37 | .section .isr_vector 38 | .align 2 39 | .globl __isr_vector 40 | __isr_vector: 41 | .long __StackTop /* Top of Stack */ 42 | .long Reset_Handler /* Reset Handler */ 43 | .long NMI_Handler /* NMI Handler */ 44 | .long HardFault_Handler /* Hard Fault Handler */ 45 | .long MemManage_Handler /* MPU Fault Handler */ 46 | .long BusFault_Handler /* Bus Fault Handler */ 47 | .long UsageFault_Handler /* Usage Fault Handler */ 48 | .long 0 /* Reserved */ 49 | .long 0 /* Reserved */ 50 | .long 0 /* Reserved */ 51 | .long 0 /* Reserved */ 52 | .long SVC_Handler /* SVCall Handler */ 53 | .long DebugMon_Handler /* Debug Monitor Handler */ 54 | .long 0 /* Reserved */ 55 | .long PendSV_Handler /* PendSV Handler */ 56 | .long SysTick_Handler /* SysTick Handler */ 57 | 58 | /* 32 IRQs */ 59 | .long Default_IRQ_Handler /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 60 | .long Default_IRQ_Handler /* 1: Cache / phub_to_0[1] / usb_int[1] */ 61 | .long 0 /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 62 | .long Default_IRQ_Handler /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 63 | .long Default_IRQ_Handler /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 64 | .long Default_IRQ_Handler /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 65 | .long Default_IRQ_Handler /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 66 | .long Default_IRQ_Handler /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 67 | .long Default_IRQ_Handler /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 68 | .long Default_IRQ_Handler /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 69 | .long Default_IRQ_Handler /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 70 | .long Default_IRQ_Handler /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 71 | .long Default_IRQ_Handler /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 72 | .long Default_IRQ_Handler /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 73 | .long Default_IRQ_Handler /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 74 | .long Default_IRQ_Handler /* 15: I2C / phub_to_0[15] / usb_int[15] */ 75 | .long 0 /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 76 | .long 0 /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 77 | .long 0 /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 78 | .long 0 /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 79 | .long 0 /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 80 | .long Default_IRQ_Handler /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 81 | .long Default_IRQ_Handler /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 82 | .long Default_IRQ_Handler /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 83 | .long Default_IRQ_Handler /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 84 | .long Default_IRQ_Handler /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 85 | .long 0 /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 86 | .long 0 /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 87 | .long Default_IRQ_Handler /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 88 | .long Default_IRQ_Handler /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 89 | .long Default_IRQ_Handler /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 90 | .long Default_IRQ_Handler /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 91 | 92 | .size __isr_vector, . - __isr_vector 93 | 94 | .text 95 | .thumb 96 | .thumb_func 97 | .align 2 98 | .globl Reset_Handler 99 | .type Reset_Handler, %function 100 | Reset_Handler: 101 | 102 | /* Firstly it copies data from read only memory to RAM. 103 | * 104 | * The ranges of copy from/to are specified by following symbols 105 | * __etext: LMA of start of the section to copy from. Usually end of text 106 | * __data_start__: VMA of start of the section to copy to 107 | * __data_end__: VMA of end of the section to copy to 108 | * 109 | * All addresses must be aligned to 4 bytes boundary. 110 | */ 111 | ldr r1, =__etext 112 | ldr r2, =__data_start__ 113 | ldr r3, =__data_end__ 114 | 115 | .L_loop1: 116 | cmp r2, r3 117 | ittt lt 118 | ldrlt r0, [r1], #4 119 | strlt r0, [r2], #4 120 | blt .L_loop1 121 | 122 | 123 | /* This part of work usually is done in C library startup code. Otherwise, 124 | * define this macro to enable it in this startup. 125 | * 126 | * The BSS section is specified by following symbols 127 | * __bss_start__: start of the BSS section. 128 | * __bss_end__: end of the BSS section. 129 | * 130 | * Both addresses must be aligned to 4 bytes boundary. 131 | */ 132 | ldr r1, =__bss_start__ 133 | ldr r2, =__bss_end__ 134 | 135 | movs r0, 0 136 | .L_loop3: 137 | cmp r1, r2 138 | itt lt 139 | strlt r0, [r1], #4 140 | blt .L_loop3 141 | 142 | bl SystemInit 143 | 144 | bl _start 145 | 146 | .pool 147 | .size Reset_Handler, . - Reset_Handler 148 | 149 | .align 1 150 | .thumb_func 151 | .weak Default_Handler 152 | .type Default_Handler, %function 153 | Default_Handler: 154 | b . 155 | .size Default_Handler, . - Default_Handler 156 | 157 | /* Macro to define default handlers as dead loops with weak linking */ 158 | .macro def_irq_handler handler_name 159 | .weak \handler_name 160 | .set \handler_name, Default_Handler 161 | .endm 162 | 163 | def_irq_handler NMI_Handler 164 | def_irq_handler HardFault_Handler 165 | def_irq_handler MemManage_Handler 166 | def_irq_handler BusFault_Handler 167 | def_irq_handler UsageFault_Handler 168 | def_irq_handler SVC_Handler 169 | def_irq_handler DebugMon_Handler 170 | def_irq_handler PendSV_Handler 171 | def_irq_handler SysTick_Handler 172 | def_irq_handler Default_IRQ_Handler 173 | 174 | .end 175 | -------------------------------------------------------------------------------- /demo2b/startup_ARMCM3.S: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.S 2 | * Purpose: startup file for Cortex-M3 devices. Should use with 3 | * GCC for ARM Embedded Processors 4 | * Orig Version: V2.0 5 | * Orig Date: 16 August 2013 6 | * Copyright (c) 2011 - 2013 ARM LIMITED 7 | * 8 | * Modified: (for PSoC 5) KRL, Datafusion, 2014 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | .syntax unified 35 | .arch armv7-m 36 | 37 | .section .isr_vector 38 | .align 2 39 | .globl __isr_vector 40 | __isr_vector: 41 | .long __StackTop /* Top of Stack */ 42 | .long Reset_Handler /* Reset Handler */ 43 | .long NMI_Handler /* NMI Handler */ 44 | .long HardFault_Handler /* Hard Fault Handler */ 45 | .long MemManage_Handler /* MPU Fault Handler */ 46 | .long BusFault_Handler /* Bus Fault Handler */ 47 | .long UsageFault_Handler /* Usage Fault Handler */ 48 | .long 0 /* Reserved */ 49 | .long 0 /* Reserved */ 50 | .long 0 /* Reserved */ 51 | .long 0 /* Reserved */ 52 | .long SVC_Handler /* SVCall Handler */ 53 | .long DebugMon_Handler /* Debug Monitor Handler */ 54 | .long 0 /* Reserved */ 55 | .long PendSV_Handler /* PendSV Handler */ 56 | .long SysTick_Handler /* SysTick Handler */ 57 | 58 | /* 32 IRQs */ 59 | .long Default_IRQ_Handler /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 60 | .long Default_IRQ_Handler /* 1: Cache / phub_to_0[1] / usb_int[1] */ 61 | .long 0 /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 62 | .long Default_IRQ_Handler /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 63 | .long Default_IRQ_Handler /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 64 | .long Default_IRQ_Handler /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 65 | .long Default_IRQ_Handler /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 66 | .long Default_IRQ_Handler /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 67 | .long Default_IRQ_Handler /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 68 | .long Default_IRQ_Handler /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 69 | .long Default_IRQ_Handler /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 70 | .long Default_IRQ_Handler /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 71 | .long Default_IRQ_Handler /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 72 | .long Default_IRQ_Handler /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 73 | .long Default_IRQ_Handler /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 74 | .long Default_IRQ_Handler /* 15: I2C / phub_to_0[15] / usb_int[15] */ 75 | .long 0 /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 76 | .long 0 /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 77 | .long 0 /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 78 | .long 0 /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 79 | .long 0 /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 80 | .long Default_IRQ_Handler /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 81 | .long Default_IRQ_Handler /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 82 | .long Default_IRQ_Handler /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 83 | .long Default_IRQ_Handler /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 84 | .long Default_IRQ_Handler /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 85 | .long 0 /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 86 | .long 0 /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 87 | .long Default_IRQ_Handler /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 88 | .long Default_IRQ_Handler /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 89 | .long Default_IRQ_Handler /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 90 | .long Default_IRQ_Handler /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 91 | 92 | .size __isr_vector, . - __isr_vector 93 | 94 | .text 95 | .thumb 96 | .thumb_func 97 | .align 2 98 | .globl Reset_Handler 99 | .type Reset_Handler, %function 100 | Reset_Handler: 101 | 102 | /* Firstly it copies data from read only memory to RAM. 103 | * 104 | * The ranges of copy from/to are specified by following symbols 105 | * __etext: LMA of start of the section to copy from. Usually end of text 106 | * __data_start__: VMA of start of the section to copy to 107 | * __data_end__: VMA of end of the section to copy to 108 | * 109 | * All addresses must be aligned to 4 bytes boundary. 110 | */ 111 | ldr r1, =__etext 112 | ldr r2, =__data_start__ 113 | ldr r3, =__data_end__ 114 | 115 | .L_loop1: 116 | cmp r2, r3 117 | ittt lt 118 | ldrlt r0, [r1], #4 119 | strlt r0, [r2], #4 120 | blt .L_loop1 121 | 122 | 123 | /* This part of work usually is done in C library startup code. Otherwise, 124 | * define this macro to enable it in this startup. 125 | * 126 | * The BSS section is specified by following symbols 127 | * __bss_start__: start of the BSS section. 128 | * __bss_end__: end of the BSS section. 129 | * 130 | * Both addresses must be aligned to 4 bytes boundary. 131 | */ 132 | ldr r1, =__bss_start__ 133 | ldr r2, =__bss_end__ 134 | 135 | movs r0, 0 136 | .L_loop3: 137 | cmp r1, r2 138 | itt lt 139 | strlt r0, [r1], #4 140 | blt .L_loop3 141 | 142 | bl SystemInit 143 | 144 | bl _start 145 | 146 | .pool 147 | .size Reset_Handler, . - Reset_Handler 148 | 149 | .align 1 150 | .thumb_func 151 | .weak Default_Handler 152 | .type Default_Handler, %function 153 | Default_Handler: 154 | b . 155 | .size Default_Handler, . - Default_Handler 156 | 157 | /* Macro to define default handlers as dead loops with weak linking */ 158 | .macro def_irq_handler handler_name 159 | .weak \handler_name 160 | .set \handler_name, Default_Handler 161 | .endm 162 | 163 | def_irq_handler NMI_Handler 164 | def_irq_handler HardFault_Handler 165 | def_irq_handler MemManage_Handler 166 | def_irq_handler BusFault_Handler 167 | def_irq_handler UsageFault_Handler 168 | def_irq_handler SVC_Handler 169 | def_irq_handler DebugMon_Handler 170 | def_irq_handler PendSV_Handler 171 | def_irq_handler SysTick_Handler 172 | def_irq_handler Default_IRQ_Handler 173 | 174 | .end 175 | -------------------------------------------------------------------------------- /demo2c/startup_ARMCM3.S: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.S 2 | * Purpose: startup file for Cortex-M3 devices. Should use with 3 | * GCC for ARM Embedded Processors 4 | * Orig Version: V2.0 5 | * Orig Date: 16 August 2013 6 | * Copyright (c) 2011 - 2013 ARM LIMITED 7 | * 8 | * Modified: (for PSoC 5) KRL, Datafusion, 2014 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | .syntax unified 35 | .arch armv7-m 36 | 37 | .section .isr_vector 38 | .align 2 39 | .globl __isr_vector 40 | __isr_vector: 41 | .long __StackTop /* Top of Stack */ 42 | .long Reset_Handler /* Reset Handler */ 43 | .long NMI_Handler /* NMI Handler */ 44 | .long HardFault_Handler /* Hard Fault Handler */ 45 | .long MemManage_Handler /* MPU Fault Handler */ 46 | .long BusFault_Handler /* Bus Fault Handler */ 47 | .long UsageFault_Handler /* Usage Fault Handler */ 48 | .long 0 /* Reserved */ 49 | .long 0 /* Reserved */ 50 | .long 0 /* Reserved */ 51 | .long 0 /* Reserved */ 52 | .long SVC_Handler /* SVCall Handler */ 53 | .long DebugMon_Handler /* Debug Monitor Handler */ 54 | .long 0 /* Reserved */ 55 | .long PendSV_Handler /* PendSV Handler */ 56 | .long SysTick_Handler /* SysTick Handler */ 57 | 58 | /* 32 IRQs */ 59 | .long Default_IRQ_Handler /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 60 | .long Default_IRQ_Handler /* 1: Cache / phub_to_0[1] / usb_int[1] */ 61 | .long 0 /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 62 | .long Default_IRQ_Handler /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 63 | .long Default_IRQ_Handler /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 64 | .long Default_IRQ_Handler /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 65 | .long Default_IRQ_Handler /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 66 | .long Default_IRQ_Handler /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 67 | .long Default_IRQ_Handler /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 68 | .long Default_IRQ_Handler /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 69 | .long Default_IRQ_Handler /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 70 | .long Default_IRQ_Handler /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 71 | .long Default_IRQ_Handler /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 72 | .long Default_IRQ_Handler /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 73 | .long Default_IRQ_Handler /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 74 | .long Default_IRQ_Handler /* 15: I2C / phub_to_0[15] / usb_int[15] */ 75 | .long 0 /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 76 | .long 0 /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 77 | .long 0 /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 78 | .long 0 /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 79 | .long 0 /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 80 | .long Default_IRQ_Handler /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 81 | .long Default_IRQ_Handler /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 82 | .long Default_IRQ_Handler /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 83 | .long Default_IRQ_Handler /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 84 | .long Default_IRQ_Handler /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 85 | .long 0 /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 86 | .long 0 /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 87 | .long Default_IRQ_Handler /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 88 | .long Default_IRQ_Handler /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 89 | .long Default_IRQ_Handler /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 90 | .long Default_IRQ_Handler /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 91 | 92 | .size __isr_vector, . - __isr_vector 93 | 94 | .text 95 | .thumb 96 | .thumb_func 97 | .align 2 98 | .globl Reset_Handler 99 | .type Reset_Handler, %function 100 | Reset_Handler: 101 | 102 | /* Firstly it copies data from read only memory to RAM. 103 | * 104 | * The ranges of copy from/to are specified by following symbols 105 | * __etext: LMA of start of the section to copy from. Usually end of text 106 | * __data_start__: VMA of start of the section to copy to 107 | * __data_end__: VMA of end of the section to copy to 108 | * 109 | * All addresses must be aligned to 4 bytes boundary. 110 | */ 111 | ldr r1, =__etext 112 | ldr r2, =__data_start__ 113 | ldr r3, =__data_end__ 114 | 115 | .L_loop1: 116 | cmp r2, r3 117 | ittt lt 118 | ldrlt r0, [r1], #4 119 | strlt r0, [r2], #4 120 | blt .L_loop1 121 | 122 | 123 | /* This part of work usually is done in C library startup code. Otherwise, 124 | * define this macro to enable it in this startup. 125 | * 126 | * The BSS section is specified by following symbols 127 | * __bss_start__: start of the BSS section. 128 | * __bss_end__: end of the BSS section. 129 | * 130 | * Both addresses must be aligned to 4 bytes boundary. 131 | */ 132 | ldr r1, =__bss_start__ 133 | ldr r2, =__bss_end__ 134 | 135 | movs r0, 0 136 | .L_loop3: 137 | cmp r1, r2 138 | itt lt 139 | strlt r0, [r1], #4 140 | blt .L_loop3 141 | 142 | bl SystemInit 143 | 144 | bl _start 145 | 146 | .pool 147 | .size Reset_Handler, . - Reset_Handler 148 | 149 | .align 1 150 | .thumb_func 151 | .weak Default_Handler 152 | .type Default_Handler, %function 153 | Default_Handler: 154 | b . 155 | .size Default_Handler, . - Default_Handler 156 | 157 | /* Macro to define default handlers as dead loops with weak linking */ 158 | .macro def_irq_handler handler_name 159 | .weak \handler_name 160 | .set \handler_name, Default_Handler 161 | .endm 162 | 163 | def_irq_handler NMI_Handler 164 | def_irq_handler HardFault_Handler 165 | def_irq_handler MemManage_Handler 166 | def_irq_handler BusFault_Handler 167 | def_irq_handler UsageFault_Handler 168 | def_irq_handler SVC_Handler 169 | def_irq_handler DebugMon_Handler 170 | def_irq_handler PendSV_Handler 171 | def_irq_handler SysTick_Handler 172 | def_irq_handler Default_IRQ_Handler 173 | 174 | .end 175 | -------------------------------------------------------------------------------- /demo2d/startup_ARMCM3.S: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.S 2 | * Purpose: startup file for Cortex-M3 devices. Should use with 3 | * GCC for ARM Embedded Processors 4 | * Orig Version: V2.0 5 | * Orig Date: 16 August 2013 6 | * Copyright (c) 2011 - 2013 ARM LIMITED 7 | * 8 | * Modified: (for PSoC 5) KRL, Datafusion, 2014 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | .syntax unified 35 | .arch armv7-m 36 | 37 | .section .isr_vector 38 | .align 2 39 | .globl __isr_vector 40 | __isr_vector: 41 | .long __StackTop /* Top of Stack */ 42 | .long Reset_Handler /* Reset Handler */ 43 | .long NMI_Handler /* NMI Handler */ 44 | .long HardFault_Handler /* Hard Fault Handler */ 45 | .long MemManage_Handler /* MPU Fault Handler */ 46 | .long BusFault_Handler /* Bus Fault Handler */ 47 | .long UsageFault_Handler /* Usage Fault Handler */ 48 | .long 0 /* Reserved */ 49 | .long 0 /* Reserved */ 50 | .long 0 /* Reserved */ 51 | .long 0 /* Reserved */ 52 | .long SVC_Handler /* SVCall Handler */ 53 | .long DebugMon_Handler /* Debug Monitor Handler */ 54 | .long 0 /* Reserved */ 55 | .long PendSV_Handler /* PendSV Handler */ 56 | .long SysTick_Handler /* SysTick Handler */ 57 | 58 | /* 32 IRQs */ 59 | .long Default_IRQ_Handler /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 60 | .long Default_IRQ_Handler /* 1: Cache / phub_to_0[1] / usb_int[1] */ 61 | .long 0 /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 62 | .long Default_IRQ_Handler /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 63 | .long Default_IRQ_Handler /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 64 | .long Default_IRQ_Handler /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 65 | .long Default_IRQ_Handler /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 66 | .long Default_IRQ_Handler /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 67 | .long Default_IRQ_Handler /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 68 | .long Default_IRQ_Handler /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 69 | .long Default_IRQ_Handler /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 70 | .long Default_IRQ_Handler /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 71 | .long Default_IRQ_Handler /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 72 | .long Default_IRQ_Handler /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 73 | .long Default_IRQ_Handler /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 74 | .long Default_IRQ_Handler /* 15: I2C / phub_to_0[15] / usb_int[15] */ 75 | .long 0 /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 76 | .long 0 /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 77 | .long 0 /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 78 | .long 0 /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 79 | .long 0 /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 80 | .long Default_IRQ_Handler /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 81 | .long Default_IRQ_Handler /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 82 | .long Default_IRQ_Handler /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 83 | .long Default_IRQ_Handler /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 84 | .long Default_IRQ_Handler /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 85 | .long 0 /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 86 | .long 0 /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 87 | .long Default_IRQ_Handler /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 88 | .long Default_IRQ_Handler /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 89 | .long Default_IRQ_Handler /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 90 | .long Default_IRQ_Handler /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 91 | 92 | .size __isr_vector, . - __isr_vector 93 | 94 | .text 95 | .thumb 96 | .thumb_func 97 | .align 2 98 | .globl Reset_Handler 99 | .type Reset_Handler, %function 100 | Reset_Handler: 101 | 102 | /* Firstly it copies data from read only memory to RAM. 103 | * 104 | * The ranges of copy from/to are specified by following symbols 105 | * __etext: LMA of start of the section to copy from. Usually end of text 106 | * __data_start__: VMA of start of the section to copy to 107 | * __data_end__: VMA of end of the section to copy to 108 | * 109 | * All addresses must be aligned to 4 bytes boundary. 110 | */ 111 | ldr r1, =__etext 112 | ldr r2, =__data_start__ 113 | ldr r3, =__data_end__ 114 | 115 | .L_loop1: 116 | cmp r2, r3 117 | ittt lt 118 | ldrlt r0, [r1], #4 119 | strlt r0, [r2], #4 120 | blt .L_loop1 121 | 122 | 123 | /* This part of work usually is done in C library startup code. Otherwise, 124 | * define this macro to enable it in this startup. 125 | * 126 | * The BSS section is specified by following symbols 127 | * __bss_start__: start of the BSS section. 128 | * __bss_end__: end of the BSS section. 129 | * 130 | * Both addresses must be aligned to 4 bytes boundary. 131 | */ 132 | ldr r1, =__bss_start__ 133 | ldr r2, =__bss_end__ 134 | 135 | movs r0, 0 136 | .L_loop3: 137 | cmp r1, r2 138 | itt lt 139 | strlt r0, [r1], #4 140 | blt .L_loop3 141 | 142 | bl SystemInit 143 | 144 | bl _start 145 | 146 | .pool 147 | .size Reset_Handler, . - Reset_Handler 148 | 149 | .align 1 150 | .thumb_func 151 | .weak Default_Handler 152 | .type Default_Handler, %function 153 | Default_Handler: 154 | b . 155 | .size Default_Handler, . - Default_Handler 156 | 157 | /* Macro to define default handlers as dead loops with weak linking */ 158 | .macro def_irq_handler handler_name 159 | .weak \handler_name 160 | .set \handler_name, Default_Handler 161 | .endm 162 | 163 | def_irq_handler NMI_Handler 164 | def_irq_handler HardFault_Handler 165 | def_irq_handler MemManage_Handler 166 | def_irq_handler BusFault_Handler 167 | def_irq_handler UsageFault_Handler 168 | def_irq_handler SVC_Handler 169 | def_irq_handler DebugMon_Handler 170 | def_irq_handler PendSV_Handler 171 | def_irq_handler SysTick_Handler 172 | def_irq_handler Default_IRQ_Handler 173 | 174 | .end 175 | -------------------------------------------------------------------------------- /demo3a/startup_ARMCM3.S: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.S 2 | * Purpose: startup file for Cortex-M3 devices. Should use with 3 | * GCC for ARM Embedded Processors 4 | * Version: V2.01 5 | * Date: 12 June 2014 6 | * 7 | */ 8 | /* Copyright (c) 2011 - 2014 ARM LIMITED 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | 35 | 36 | .syntax unified 37 | .arch armv7-m 38 | 39 | .section .stack 40 | .align 3 41 | #ifdef __STACK_SIZE 42 | .equ Stack_Size, __STACK_SIZE 43 | #else 44 | .equ Stack_Size, 0x00000400 45 | #endif 46 | .globl __StackTop 47 | .globl __StackLimit 48 | __StackLimit: 49 | .space Stack_Size 50 | .size __StackLimit, . - __StackLimit 51 | __StackTop: 52 | .size __StackTop, . - __StackTop 53 | 54 | .section .heap 55 | .align 3 56 | #ifdef __HEAP_SIZE 57 | .equ Heap_Size, __HEAP_SIZE 58 | #else 59 | .equ Heap_Size, 0x00000C00 60 | #endif 61 | .globl __HeapBase 62 | .globl __HeapLimit 63 | __HeapBase: 64 | .if Heap_Size 65 | .space Heap_Size 66 | .endif 67 | .size __HeapBase, . - __HeapBase 68 | __HeapLimit: 69 | .size __HeapLimit, . - __HeapLimit 70 | 71 | .section .vectors 72 | .align 2 73 | .globl __Vectors 74 | __Vectors: 75 | .long __StackTop /* Top of Stack */ 76 | .long Reset_Handler /* Reset Handler */ 77 | .long NMI_Handler /* NMI Handler */ 78 | .long HardFault_Handler /* Hard Fault Handler */ 79 | .long MemManage_Handler /* MPU Fault Handler */ 80 | .long BusFault_Handler /* Bus Fault Handler */ 81 | .long UsageFault_Handler /* Usage Fault Handler */ 82 | .long 0 /* Reserved */ 83 | .long 0 /* Reserved */ 84 | .long 0 /* Reserved */ 85 | .long 0 /* Reserved */ 86 | .long SVC_Handler /* SVCall Handler */ 87 | .long DebugMon_Handler /* Debug Monitor Handler */ 88 | .long 0 /* Reserved */ 89 | .long PendSV_Handler /* PendSV Handler */ 90 | .long SysTick_Handler /* SysTick Handler */ 91 | 92 | /* 32 IRQs - PSoC specific */ 93 | .long Default_IRQ_Handler /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 94 | .long Default_IRQ_Handler /* 1: Cache / phub_to_0[1] / usb_int[1] */ 95 | .long 0 /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 96 | .long Default_IRQ_Handler /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 97 | .long Default_IRQ_Handler /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 98 | .long Default_IRQ_Handler /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 99 | .long Default_IRQ_Handler /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 100 | .long Default_IRQ_Handler /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 101 | .long Default_IRQ_Handler /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 102 | .long Default_IRQ_Handler /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 103 | .long Default_IRQ_Handler /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 104 | .long Default_IRQ_Handler /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 105 | .long Default_IRQ_Handler /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 106 | .long Default_IRQ_Handler /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 107 | .long Default_IRQ_Handler /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 108 | .long Default_IRQ_Handler /* 15: I2C / phub_to_0[15] / usb_int[15] */ 109 | .long 0 /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 110 | .long 0 /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 111 | .long 0 /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 112 | .long 0 /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 113 | .long 0 /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 114 | .long Default_IRQ_Handler /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 115 | .long Default_IRQ_Handler /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 116 | .long Default_IRQ_Handler /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 117 | .long Default_IRQ_Handler /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 118 | .long Default_IRQ_Handler /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 119 | .long 0 /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 120 | .long 0 /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 121 | .long Default_IRQ_Handler /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 122 | .long Default_IRQ_Handler /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 123 | .long Default_IRQ_Handler /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 124 | .long Default_IRQ_Handler /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 125 | 126 | .size __Vectors, . - __Vectors 127 | 128 | .text 129 | .thumb 130 | .thumb_func 131 | .align 2 132 | .globl Reset_Handler 133 | .type Reset_Handler, %function 134 | Reset_Handler: 135 | /* Firstly it copies data from read only memory to RAM. There are two schemes 136 | * to copy. One can copy more than one sections. Another can only copy 137 | * one section. The former scheme needs more instructions and read-only 138 | * data to implement than the latter. 139 | * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 140 | 141 | #ifdef __STARTUP_COPY_MULTIPLE 142 | /* Multiple sections scheme. 143 | * 144 | * Between symbol address __copy_table_start__ and __copy_table_end__, 145 | * there are array of triplets, each of which specify: 146 | * offset 0: LMA of start of a section to copy from 147 | * offset 4: VMA of start of a section to copy to 148 | * offset 8: size of the section to copy. Must be multiply of 4 149 | * 150 | * All addresses must be aligned to 4 bytes boundary. 151 | */ 152 | ldr r4, =__copy_table_start__ 153 | ldr r5, =__copy_table_end__ 154 | 155 | .L_loop0: 156 | cmp r4, r5 157 | bge .L_loop0_done 158 | ldr r1, [r4] 159 | ldr r2, [r4, #4] 160 | ldr r3, [r4, #8] 161 | 162 | .L_loop0_0: 163 | subs r3, #4 164 | ittt ge 165 | ldrge r0, [r1, r3] 166 | strge r0, [r2, r3] 167 | bge .L_loop0_0 168 | 169 | adds r4, #12 170 | b .L_loop0 171 | 172 | .L_loop0_done: 173 | #else 174 | /* Single section scheme. 175 | * 176 | * The ranges of copy from/to are specified by following symbols 177 | * __etext: LMA of start of the section to copy from. Usually end of text 178 | * __data_start__: VMA of start of the section to copy to 179 | * __data_end__: VMA of end of the section to copy to 180 | * 181 | * All addresses must be aligned to 4 bytes boundary. 182 | */ 183 | ldr r1, =__etext 184 | ldr r2, =__data_start__ 185 | ldr r3, =__data_end__ 186 | 187 | .L_loop1: 188 | cmp r2, r3 189 | ittt lt 190 | ldrlt r0, [r1], #4 191 | strlt r0, [r2], #4 192 | blt .L_loop1 193 | #endif /*__STARTUP_COPY_MULTIPLE */ 194 | 195 | /* This part of work usually is done in C library startup code. Otherwise, 196 | * define this macro to enable it in this startup. 197 | * 198 | * There are two schemes too. One can clear multiple BSS sections. Another 199 | * can only clear one section. The former is more size expensive than the 200 | * latter. 201 | * 202 | * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 203 | * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. 204 | */ 205 | #ifdef __STARTUP_CLEAR_BSS_MULTIPLE 206 | /* Multiple sections scheme. 207 | * 208 | * Between symbol address __copy_table_start__ and __copy_table_end__, 209 | * there are array of tuples specifying: 210 | * offset 0: Start of a BSS section 211 | * offset 4: Size of this BSS section. Must be multiply of 4 212 | */ 213 | ldr r3, =__zero_table_start__ 214 | ldr r4, =__zero_table_end__ 215 | 216 | .L_loop2: 217 | cmp r3, r4 218 | bge .L_loop2_done 219 | ldr r1, [r3] 220 | ldr r2, [r3, #4] 221 | movs r0, 0 222 | 223 | .L_loop2_0: 224 | subs r2, #4 225 | itt ge 226 | strge r0, [r1, r2] 227 | bge .L_loop2_0 228 | 229 | adds r3, #8 230 | b .L_loop2 231 | .L_loop2_done: 232 | #elif defined (__STARTUP_CLEAR_BSS) 233 | /* Single BSS section scheme. 234 | * 235 | * The BSS section is specified by following symbols 236 | * __bss_start__: start of the BSS section. 237 | * __bss_end__: end of the BSS section. 238 | * 239 | * Both addresses must be aligned to 4 bytes boundary. 240 | */ 241 | ldr r1, =__bss_start__ 242 | ldr r2, =__bss_end__ 243 | 244 | movs r0, 0 245 | .L_loop3: 246 | cmp r1, r2 247 | itt lt 248 | strlt r0, [r1], #4 249 | blt .L_loop3 250 | #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 251 | 252 | #ifndef __NO_SYSTEM_INIT 253 | bl SystemInit 254 | #endif 255 | 256 | #ifndef __START 257 | #define __START _start 258 | #endif 259 | bl __START 260 | 261 | .pool 262 | .size Reset_Handler, . - Reset_Handler 263 | 264 | .align 1 265 | .thumb_func 266 | .weak Default_Handler 267 | .type Default_Handler, %function 268 | Default_Handler: 269 | b . 270 | .size Default_Handler, . - Default_Handler 271 | 272 | /* Macro to define default handlers. Default handler 273 | * will be weak symbol and just dead loops. They can be 274 | * overwritten by other handlers */ 275 | .macro def_irq_handler handler_name 276 | .weak \handler_name 277 | .set \handler_name, Default_Handler 278 | .endm 279 | 280 | def_irq_handler NMI_Handler 281 | def_irq_handler HardFault_Handler 282 | def_irq_handler MemManage_Handler 283 | def_irq_handler BusFault_Handler 284 | def_irq_handler UsageFault_Handler 285 | def_irq_handler SVC_Handler 286 | def_irq_handler DebugMon_Handler 287 | def_irq_handler PendSV_Handler 288 | def_irq_handler SysTick_Handler 289 | 290 | def_irq_handler Default_IRQ_Handler 291 | 292 | .end 293 | -------------------------------------------------------------------------------- /demo3b/startup_ARMCM3.c: -------------------------------------------------------------------------------- 1 | /* File: startup_ARMCM3.c 2 | * Purpose: startup file for Cortex-M3 devices. 3 | * Should be used with GCC 'GNU Tools ARM Embedded' 4 | * Version: V1.01 5 | * Date: 12 June 2014 6 | * 7 | */ 8 | /* Copyright (c) 2011 - 2014 ARM LIMITED 9 | 10 | All rights reserved. 11 | Redistribution and use in source and binary forms, with or without 12 | modification, are permitted provided that the following conditions are met: 13 | - Redistributions of source code must retain the above copyright 14 | notice, this list of conditions and the following disclaimer. 15 | - Redistributions in binary form must reproduce the above copyright 16 | notice, this list of conditions and the following disclaimer in the 17 | documentation and/or other materials provided with the distribution. 18 | - Neither the name of ARM nor the names of its contributors may be used 19 | to endorse or promote products derived from this software without 20 | specific prior written permission. 21 | * 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 | POSSIBILITY OF SUCH DAMAGE. 33 | ---------------------------------------------------------------------------*/ 34 | 35 | #include 36 | 37 | 38 | /*---------------------------------------------------------------------------- 39 | Linker generated Symbols 40 | *----------------------------------------------------------------------------*/ 41 | extern uint32_t __etext; 42 | extern uint32_t __data_start__; 43 | extern uint32_t __data_end__; 44 | extern uint32_t __copy_table_start__; 45 | extern uint32_t __copy_table_end__; 46 | extern uint32_t __zero_table_start__; 47 | extern uint32_t __zero_table_end__; 48 | extern uint32_t __bss_start__; 49 | extern uint32_t __bss_end__; 50 | extern uint32_t __StackTop; 51 | 52 | /*---------------------------------------------------------------------------- 53 | Exception / Interrupt Handler Function Prototype 54 | *----------------------------------------------------------------------------*/ 55 | typedef void( *pFunc )( void ); 56 | 57 | 58 | /*---------------------------------------------------------------------------- 59 | External References 60 | *----------------------------------------------------------------------------*/ 61 | #ifndef __START 62 | extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ 63 | #else 64 | extern int __START(void) __attribute__((noreturn)); /* main entry point */ 65 | #endif 66 | 67 | #ifndef __NO_SYSTEM_INIT 68 | extern void SystemInit (void); /* CMSIS System Initialization */ 69 | #endif 70 | 71 | 72 | /*---------------------------------------------------------------------------- 73 | Internal References 74 | *----------------------------------------------------------------------------*/ 75 | void Default_Handler(void); /* Default empty handler */ 76 | void Reset_Handler(void); /* Reset Handler */ 77 | 78 | 79 | /*---------------------------------------------------------------------------- 80 | User Initial Stack & Heap 81 | *----------------------------------------------------------------------------*/ 82 | #ifndef __STACK_SIZE 83 | #define __STACK_SIZE 0x00000400 84 | #endif 85 | static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); 86 | 87 | #ifndef __HEAP_SIZE 88 | #define __HEAP_SIZE 0x00000C00 89 | #endif 90 | #if __HEAP_SIZE > 0 91 | static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); 92 | #endif 93 | 94 | 95 | /*---------------------------------------------------------------------------- 96 | Exception / Interrupt Handler 97 | *----------------------------------------------------------------------------*/ 98 | 99 | #define WEAK(name) __attribute__ ((weak, alias(name))) 100 | #define WEAK_DEFAULT_HANDLER WEAK("Default_Handler") 101 | 102 | /* Cortex-M3 Processor Exceptions */ 103 | void NMI_Handler (void) WEAK_DEFAULT_HANDLER; 104 | void HardFault_Handler (void) WEAK_DEFAULT_HANDLER; 105 | void MemManage_Handler (void) WEAK_DEFAULT_HANDLER; 106 | void BusFault_Handler (void) WEAK_DEFAULT_HANDLER; 107 | void UsageFault_Handler (void) WEAK_DEFAULT_HANDLER; 108 | void SVC_Handler (void) WEAK_DEFAULT_HANDLER; 109 | void DebugMon_Handler (void) WEAK_DEFAULT_HANDLER; 110 | void PendSV_Handler (void) WEAK_DEFAULT_HANDLER; 111 | void SysTick_Handler (void) WEAK_DEFAULT_HANDLER; 112 | 113 | void Default_IRQ_Handler (void) WEAK_DEFAULT_HANDLER; 114 | 115 | 116 | 117 | /*---------------------------------------------------------------------------- 118 | Exception / Interrupt Vector table 119 | *----------------------------------------------------------------------------*/ 120 | const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { 121 | /* Cortex-M3 Exceptions Handler */ 122 | (pFunc)&__StackTop, /* Initial Stack Pointer */ 123 | Reset_Handler, /* Reset Handler */ 124 | NMI_Handler, /* NMI Handler */ 125 | HardFault_Handler, /* Hard Fault Handler */ 126 | MemManage_Handler, /* MPU Fault Handler */ 127 | BusFault_Handler, /* Bus Fault Handler */ 128 | UsageFault_Handler, /* Usage Fault Handler */ 129 | 0, /* Reserved */ 130 | 0, /* Reserved */ 131 | 0, /* Reserved */ 132 | 0, /* Reserved */ 133 | SVC_Handler, /* SVCall Handler */ 134 | DebugMon_Handler, /* Debug Monitor Handler */ 135 | 0, /* Reserved */ 136 | PendSV_Handler, /* PendSV Handler */ 137 | SysTick_Handler, /* SysTick Handler */ 138 | 139 | /* 32 IRQs - PSoC specific */ 140 | Default_IRQ_Handler, /* 0: Low V. Detect / phub_to_0[0] / usb_int[0] */ 141 | Default_IRQ_Handler, /* 1: Cache / phub_to_0[1] / usb_int[1] */ 142 | 0, /* 2: Reserved / phub_to_0[2] / usb_int[2] */ 143 | Default_IRQ_Handler, /* 3: Pwr Mgr / phub_to_0[3] / usb_int[3] */ 144 | Default_IRQ_Handler, /* 4: PICU[0] / phub_to_0[4] / usb_int[4] */ 145 | Default_IRQ_Handler, /* 5: PICU[1] / phub_to_0[5] / usb_int[5] */ 146 | Default_IRQ_Handler, /* 6: PICU[2] / phub_to_0[6] / usb_int[6] */ 147 | Default_IRQ_Handler, /* 7: PICU[3] / phub_to_0[7] / usb_int[7] */ 148 | Default_IRQ_Handler, /* 8: PICU[4] / phub_to_0[8] / usb_int[8] */ 149 | Default_IRQ_Handler, /* 9: PICU[5] / phub_to_0[9] / usb_int[9] */ 150 | Default_IRQ_Handler, /* 10: PICU[6] / phub_to_0[10] / usb_int[10] */ 151 | Default_IRQ_Handler, /* 11: PICU[12] / phub_to_0[11] / usb_int[11] */ 152 | Default_IRQ_Handler, /* 12: PICU[15] / phub_to_0[12] / usb_int[12] */ 153 | Default_IRQ_Handler, /* 13: Comparators / phub_to_0[13] / usb_int[13] */ 154 | Default_IRQ_Handler, /* 14: Sw. Caps / phub_to_0[14] / usb_int[14] */ 155 | Default_IRQ_Handler, /* 15: I2C / phub_to_0[15] / usb_int[15] */ 156 | 0, /* 16: Reserved / phub_to_1[0] / usb_int[16] */ 157 | 0, /* 17: Reserved / phub_to_1[1] / usb_int[17] */ 158 | 0, /* 18: Reserved / phub_to_1[2] / usb_int[18] */ 159 | 0, /* 19: Reserved / phub_to_1[3] / usb_int[19] */ 160 | 0, /* 20: Reserved / phub_to_1[4] / usb_int[20] */ 161 | Default_IRQ_Handler, /* 21: USB SOF Int / phub_to_1[5] / usb_int[21] */ 162 | Default_IRQ_Handler, /* 22: USB Arb Int / phub_to_1[6] / usb_int[22] */ 163 | Default_IRQ_Handler, /* 23: USB Bus Int / phub_to_1[7] / usb_int[23] */ 164 | Default_IRQ_Handler, /* 24: USB EP0 / phub_to_1[8] / usb_int[24] */ 165 | Default_IRQ_Handler, /* 25: USB EP Data / phub_to_1[9] / usb_int[25] */ 166 | 0, /* 26: Reserved / phub_to_1[10] / usb_int[26] */ 167 | 0, /* 27: Reserved / phub_to_1[11] / usb_int[27] */ 168 | Default_IRQ_Handler, /* 28: DFB Int / phub_to_1[12] / usb_int[28] */ 169 | Default_IRQ_Handler, /* 29: Decimator Int / phub_to_1[13] / usb_int[29] */ 170 | Default_IRQ_Handler, /* 30: phub_err_int / phub_to_1[14] / usb_int[30] */ 171 | Default_IRQ_Handler, /* 31: eeprom_fault_int / phub_to_1[15] / usb_int[31] */ 172 | }; 173 | 174 | 175 | /*---------------------------------------------------------------------------- 176 | Reset Handler called on controller reset 177 | *----------------------------------------------------------------------------*/ 178 | void Reset_Handler(void) { 179 | uint32_t *pSrc, *pDest; 180 | uint32_t *pTable __attribute__((unused)); 181 | 182 | /* Firstly it copies data from read only memory to RAM. There are two schemes 183 | * to copy. One can copy more than one sections. Another can only copy 184 | * one section. The former scheme needs more instructions and read-only 185 | * data to implement than the latter. 186 | * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 187 | 188 | #ifdef __STARTUP_COPY_MULTIPLE 189 | /* Multiple sections scheme. 190 | * 191 | * Between symbol address __copy_table_start__ and __copy_table_end__, 192 | * there are array of triplets, each of which specify: 193 | * offset 0: LMA of start of a section to copy from 194 | * offset 4: VMA of start of a section to copy to 195 | * offset 8: size of the section to copy. Must be multiply of 4 196 | * 197 | * All addresses must be aligned to 4 bytes boundary. 198 | */ 199 | pTable = &__copy_table_start__; 200 | 201 | for (; pTable < &__copy_table_end__; pTable = pTable + 3) { 202 | pSrc = (uint32_t*)*(pTable + 0); 203 | pDest = (uint32_t*)*(pTable + 1); 204 | for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { 205 | *pDest++ = *pSrc++; 206 | } 207 | } 208 | #else 209 | /* Single section scheme. 210 | * 211 | * The ranges of copy from/to are specified by following symbols 212 | * __etext: LMA of start of the section to copy from. Usually end of text 213 | * __data_start__: VMA of start of the section to copy to 214 | * __data_end__: VMA of end of the section to copy to 215 | * 216 | * All addresses must be aligned to 4 bytes boundary. 217 | */ 218 | pSrc = &__etext; 219 | pDest = &__data_start__; 220 | 221 | for ( ; pDest < &__data_end__ ; ) { 222 | *pDest++ = *pSrc++; 223 | } 224 | #endif /*__STARTUP_COPY_MULTIPLE */ 225 | 226 | /* This part of work usually is done in C library startup code. Otherwise, 227 | * define this macro to enable it in this startup. 228 | * 229 | * There are two schemes too. One can clear multiple BSS sections. Another 230 | * can only clear one section. The former is more size expensive than the 231 | * latter. 232 | * 233 | * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 234 | * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. 235 | */ 236 | #ifdef __STARTUP_CLEAR_BSS_MULTIPLE 237 | /* Multiple sections scheme. 238 | * 239 | * Between symbol address __copy_table_start__ and __copy_table_end__, 240 | * there are array of tuples specifying: 241 | * offset 0: Start of a BSS section 242 | * offset 4: Size of this BSS section. Must be multiply of 4 243 | */ 244 | pTable = &__zero_table_start__; 245 | 246 | for (; pTable < &__zero_table_end__; pTable = pTable + 2) { 247 | pDest = (uint32_t*)*(pTable + 0); 248 | for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { 249 | *pDest++ = 0; 250 | } 251 | } 252 | #elif defined (__STARTUP_CLEAR_BSS) 253 | /* Single BSS section scheme. 254 | * 255 | * The BSS section is specified by following symbols 256 | * __bss_start__: start of the BSS section. 257 | * __bss_end__: end of the BSS section. 258 | * 259 | * Both addresses must be aligned to 4 bytes boundary. 260 | */ 261 | pDest = &__bss_start__; 262 | 263 | for ( ; pDest < &__bss_end__ ; ) { 264 | *pDest++ = 0ul; 265 | } 266 | #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 267 | 268 | #ifndef __NO_SYSTEM_INIT 269 | SystemInit(); 270 | #endif 271 | 272 | #ifndef __START 273 | #define __START _start 274 | #endif 275 | __START(); 276 | 277 | } 278 | 279 | 280 | /*---------------------------------------------------------------------------- 281 | Default Handler for Exceptions / Interrupts 282 | *----------------------------------------------------------------------------*/ 283 | void Default_Handler(void) { 284 | 285 | while(1); 286 | } 287 | --------------------------------------------------------------------------------