├── .gitignore ├── Kconfig ├── Makefile ├── README.md ├── rtl8xxxu.h ├── rtl8xxxu_8188e.c ├── rtl8xxxu_8188f.c ├── rtl8xxxu_8192c.c ├── rtl8xxxu_8192e.c ├── rtl8xxxu_8710b.c ├── rtl8xxxu_8723a.c ├── rtl8xxxu_8723b.c ├── rtl8xxxu_core.c └── rtl8xxxu_regs.h /.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.cmd 3 | *.0 4 | modules.order 5 | Module.symvers 6 | -------------------------------------------------------------------------------- /Kconfig: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: GPL-2.0-only 2 | # 3 | # RTL8XXXU Wireless LAN device configuration 4 | # 5 | config RTL8XXXU 6 | tristate "Realtek 802.11n USB wireless chips support" 7 | depends on MAC80211 && USB 8 | depends on LEDS_CLASS 9 | help 10 | This is an alternative driver for various Realtek RTL8XXX 11 | parts written to utilize the Linux mac80211 stack. 12 | The driver is known to work with a number of RTL8723AU, 13 | RL8188CU, RTL8188RU, RTL8191CU, RTL8192CU, RTL8723BU, RTL8192EU, 14 | RTL8188FU, RTL8188EU, and RTL8710BU (aka RTL8188GU) devices. 15 | 16 | This driver is under development and has a limited feature 17 | set. In particular it does not yet support 40MHz channels 18 | and power management. However it should have a smaller 19 | memory footprint than the vendor drivers and benefits 20 | from the in kernel mac80211 stack. 21 | 22 | It can coexist with drivers from drivers/staging/rtl8723au, 23 | drivers/staging/rtl8192u, and drivers/net/wireless/rtlwifi, 24 | but you will need to control which module you wish to load. 25 | 26 | To compile this driver as a module, choose M here: the module will 27 | be called rtl8xxxu. If unsure, say N. 28 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: GPL-2.0-only 2 | obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o 3 | 4 | rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \ 5 | rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8188f.o \ 6 | rtl8xxxu_8188e.o rtl8xxxu_8710b.o 7 | 8 | 9 | KVER := $(shell uname -r) 10 | KSRC := /lib/modules/$(KVER)/build 11 | MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/realtek/ 12 | 13 | all: modules 14 | 15 | modules: 16 | $(MAKE) -C $(KSRC) M=$(shell pwd) modules 17 | 18 | MODULE_NAME = rtl8xxxu 19 | 20 | install: modules 21 | #gzip -f $(MODULE_NAME).ko 22 | sudo cp -f $(MODULE_NAME).ko $(MODDESTDIR) 23 | sudo /sbin/depmod -a ${KVER} 24 | sudo modprobe $(MODULE_NAME) 25 | sudo rmmod $(MODULE_NAME) 26 | sudo modprobe $(MODULE_NAME) 27 | 28 | uninstall: 29 | sudo rm -f $(MODDESTDIR)/$(MODULE_NAME).ko 30 | sudo /sbin/depmod -a ${KVER} 31 | 32 | .PHONY: modules clean 33 | 34 | clean: 35 | rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order 36 | rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~ 37 | rm -fr .tmp_versions 38 | 39 | rm: 40 | sudo rmmod $(MODULE_NAME) 41 | 42 | probe: 43 | sudo modprobe $(MODULE_NAME) 44 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | ## Realtek RTL8XXXU 3 | 4 | This driver currently supports these chipsets: 5 | REALTEK RTL 8188e(us), 8188f 8192e 8192c 8723a and 8723b 6 | 7 | 8 | [![kali](https://img.shields.io/badge/kali-supported-blue.svg)](https://www.kali.org) 9 | [![NetHunter](https://img.shields.io/badge/nethunter-supported-blue.svg)](https://nethunter.com) 10 | [![aircrack-ng](https://img.shields.io/badge/aircrack--ng-supported-blue.svg)](https://github.com/aircrack-ng/aircrack-ng) 11 | [![wifite2](https://img.shields.io/badge/wifite2-supported-blue.svg)](https://github.com/kimocoder/wifite2) 12 |
13 | [![GitHub issues](https://img.shields.io/github/issues/kimocoder/realtek_wifi.svg)](https://github.com/kimocoder/realtek_wifi/issues) 14 | [![GitHub forks](https://img.shields.io/github/forks/kimocoder/realtek_wifi.svg)](https://github.com/kimocoder/realtek_wifi/network) 15 | [![GitHub stars](https://img.shields.io/github/stars/kimocoder/realtek_wifi.svg)](https://github.com/kimocoder/realtek_wifi/stargazers) 16 | [![GitHub license](https://img.shields.io/github/license/aircrack-ng/rtl8812au.svg)](https://github.com/aircrack-ng/rtl8812au/blob/master/LICENSE) 17 | [![GitHub version](https://raster.shields.io/badge/version-BETA-lightgrey.svg)](#) 18 | 19 | 20 | ### What's new!? 21 | ```sh 22 | This is a new "base", put together from kernel mainline and upstream wireless-drivers-next. 23 | Since last "base" I used last time, the stack has gotten both 8188EU(s) and 8188F(x) support. 24 | 25 | And it has been targetted on a lot of fresh kernel includes to move things to much. 26 | 27 | That's why I put together a standalone "Makefile" for buillding kernel modult too, 28 | in case it's hard to backport a bunch, for some time. Your choice. 29 | 30 | 31 | Will keep the driver as clean/easy this time, Module name will be "rtl8xxxu" (original) 32 | 33 | 34 | 35 | 36 | 37 | Cheers! 38 | 39 | 40 | -------------------------------------------------------------------------------- /rtl8xxxu.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * Copyright (c) 2014 - 2017 Jes Sorensen 4 | * 5 | * Register definitions taken from original Realtek rtl8723au driver 6 | */ 7 | 8 | #include 9 | 10 | #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 | #define RTL8XXXU_DEBUG_REG_READ 0x02 12 | #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 | #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 | #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 | #define RTL8XXXU_DEBUG_TX 0x20 16 | #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 | #define RTL8XXXU_DEBUG_RX 0x80 18 | #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 | #define RTL8XXXU_DEBUG_USB 0x200 20 | #define RTL8XXXU_DEBUG_KEY 0x400 21 | #define RTL8XXXU_DEBUG_H2C 0x800 22 | #define RTL8XXXU_DEBUG_ACTION 0x1000 23 | #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 | #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 | 26 | #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 | #define RTL8XXXU_MAX_REG_POLL 500 28 | #define USB_INTR_CONTENT_LENGTH 56 29 | 30 | #define RTL8XXXU_OUT_ENDPOINTS 6 31 | 32 | #define REALTEK_USB_READ 0xc0 33 | #define REALTEK_USB_WRITE 0x40 34 | #define REALTEK_USB_CMD_REQ 0x05 35 | #define REALTEK_USB_CMD_IDX 0x00 36 | 37 | #define TX_TOTAL_PAGE_NUM 0xf8 38 | #define TX_TOTAL_PAGE_NUM_8188F 0xf7 39 | #define TX_TOTAL_PAGE_NUM_8188E 0xa9 40 | #define TX_TOTAL_PAGE_NUM_8192E 0xf3 41 | #define TX_TOTAL_PAGE_NUM_8723B 0xf7 42 | /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 43 | #define TX_PAGE_NUM_PUBQ 0xe7 44 | #define TX_PAGE_NUM_HI_PQ 0x0c 45 | #define TX_PAGE_NUM_LO_PQ 0x02 46 | #define TX_PAGE_NUM_NORM_PQ 0x02 47 | 48 | #define TX_PAGE_NUM_PUBQ_8188F 0xe5 49 | #define TX_PAGE_NUM_HI_PQ_8188F 0x0c 50 | #define TX_PAGE_NUM_LO_PQ_8188F 0x02 51 | #define TX_PAGE_NUM_NORM_PQ_8188F 0x02 52 | 53 | #define TX_PAGE_NUM_PUBQ_8188E 0x47 54 | #define TX_PAGE_NUM_HI_PQ_8188E 0x29 55 | #define TX_PAGE_NUM_LO_PQ_8188E 0x1c 56 | #define TX_PAGE_NUM_NORM_PQ_8188E 0x1c 57 | 58 | #define TX_PAGE_NUM_PUBQ_8192E 0xe7 59 | #define TX_PAGE_NUM_HI_PQ_8192E 0x08 60 | #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 61 | #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 62 | 63 | #define TX_PAGE_NUM_PUBQ_8723B 0xe7 64 | #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 65 | #define TX_PAGE_NUM_LO_PQ_8723B 0x02 66 | #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 67 | 68 | #define RTL_FW_PAGE_SIZE 4096 69 | #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 70 | 71 | #define RTL8723A_CHANNEL_GROUPS 3 72 | #define RTL8723A_MAX_RF_PATHS 2 73 | #define RTL8723B_CHANNEL_GROUPS 6 74 | #define RTL8723B_TX_COUNT 4 75 | #define RTL8723B_MAX_RF_PATHS 4 76 | #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 77 | #define RF6052_MAX_TX_PWR 0x3f 78 | 79 | #define EFUSE_MAP_LEN 512 80 | #define EFUSE_MAX_SECTION_8723A 64 81 | #define EFUSE_REAL_CONTENT_LEN_8723A 512 82 | #define EFUSE_BT_MAP_LEN_8723A 1024 83 | #define EFUSE_MAX_WORD_UNIT 4 84 | 85 | enum rtl8xxxu_rtl_chip { 86 | RTL8192S = 0x81920, 87 | RTL8191S = 0x81910, 88 | RTL8192C = 0x8192c, 89 | RTL8191C = 0x8191c, 90 | RTL8188C = 0x8188c, 91 | RTL8188R = 0x81889, 92 | RTL8192D = 0x8192d, 93 | RTL8723A = 0x8723a, 94 | RTL8188E = 0x8188e, 95 | RTL8812 = 0x88120, 96 | RTL8821 = 0x88210, 97 | RTL8192E = 0x8192e, 98 | RTL8191E = 0x8191e, 99 | RTL8723B = 0x8723b, 100 | RTL8814A = 0x8814a, 101 | RTL8881A = 0x8881a, 102 | RTL8821B = 0x8821b, 103 | RTL8822B = 0x8822b, 104 | RTL8703B = 0x8703b, 105 | RTL8195A = 0x8195a, 106 | RTL8188F = 0x8188f, 107 | RTL8710B = 0x8710b, 108 | }; 109 | 110 | enum rtl8xxxu_rx_type { 111 | RX_TYPE_DATA_PKT = 0, 112 | RX_TYPE_C2H = 1, 113 | RX_TYPE_ERROR = -1 114 | }; 115 | 116 | struct rtl8xxxu_rxdesc16 { 117 | #ifdef __LITTLE_ENDIAN 118 | u32 pktlen:14; 119 | u32 crc32:1; 120 | u32 icverr:1; 121 | u32 drvinfo_sz:4; 122 | u32 security:3; 123 | u32 qos:1; 124 | u32 shift:2; 125 | u32 phy_stats:1; 126 | u32 swdec:1; 127 | u32 ls:1; 128 | u32 fs:1; 129 | u32 eor:1; 130 | u32 own:1; 131 | 132 | u32 macid:5; 133 | u32 tid:4; 134 | u32 hwrsvd:4; 135 | u32 amsdu:1; 136 | u32 paggr:1; 137 | u32 faggr:1; 138 | u32 a1fit:4; 139 | u32 a2fit:4; 140 | u32 pam:1; 141 | u32 pwr:1; 142 | u32 md:1; 143 | u32 mf:1; 144 | u32 type:2; 145 | u32 mc:1; 146 | u32 bc:1; 147 | 148 | u32 seq:12; 149 | u32 frag:4; 150 | u32 pkt_cnt:8; 151 | u32 reserved:6; 152 | u32 nextind:1; 153 | u32 reserved0:1; 154 | 155 | u32 rxmcs:6; 156 | u32 rxht:1; 157 | u32 gf:1; 158 | u32 splcp:1; 159 | u32 bw:1; 160 | u32 htc:1; 161 | u32 eosp:1; 162 | u32 bssidfit:2; 163 | u32 rpt_sel:2; /* 8188e */ 164 | u32 reserved1:14; 165 | u32 unicastwake:1; 166 | u32 magicwake:1; 167 | 168 | u32 pattern0match:1; 169 | u32 pattern1match:1; 170 | u32 pattern2match:1; 171 | u32 pattern3match:1; 172 | u32 pattern4match:1; 173 | u32 pattern5match:1; 174 | u32 pattern6match:1; 175 | u32 pattern7match:1; 176 | u32 pattern8match:1; 177 | u32 pattern9match:1; 178 | u32 patternamatch:1; 179 | u32 patternbmatch:1; 180 | u32 patterncmatch:1; 181 | u32 reserved2:19; 182 | #else 183 | u32 own:1; 184 | u32 eor:1; 185 | u32 fs:1; 186 | u32 ls:1; 187 | u32 swdec:1; 188 | u32 phy_stats:1; 189 | u32 shift:2; 190 | u32 qos:1; 191 | u32 security:3; 192 | u32 drvinfo_sz:4; 193 | u32 icverr:1; 194 | u32 crc32:1; 195 | u32 pktlen:14; 196 | 197 | u32 bc:1; 198 | u32 mc:1; 199 | u32 type:2; 200 | u32 mf:1; 201 | u32 md:1; 202 | u32 pwr:1; 203 | u32 pam:1; 204 | u32 a2fit:4; 205 | u32 a1fit:4; 206 | u32 faggr:1; 207 | u32 paggr:1; 208 | u32 amsdu:1; 209 | u32 hwrsvd:4; 210 | u32 tid:4; 211 | u32 macid:5; 212 | 213 | u32 reserved0:1; 214 | u32 nextind:1; 215 | u32 reserved:6; 216 | u32 pkt_cnt:8; 217 | u32 frag:4; 218 | u32 seq:12; 219 | 220 | u32 magicwake:1; 221 | u32 unicastwake:1; 222 | u32 reserved1:14; 223 | u32 rpt_sel:2; /* 8188e */ 224 | u32 bssidfit:2; 225 | u32 eosp:1; 226 | u32 htc:1; 227 | u32 bw:1; 228 | u32 splcp:1; 229 | u32 gf:1; 230 | u32 rxht:1; 231 | u32 rxmcs:6; 232 | 233 | u32 reserved2:19; 234 | u32 patterncmatch:1; 235 | u32 patternbmatch:1; 236 | u32 patternamatch:1; 237 | u32 pattern9match:1; 238 | u32 pattern8match:1; 239 | u32 pattern7match:1; 240 | u32 pattern6match:1; 241 | u32 pattern5match:1; 242 | u32 pattern4match:1; 243 | u32 pattern3match:1; 244 | u32 pattern2match:1; 245 | u32 pattern1match:1; 246 | u32 pattern0match:1; 247 | #endif 248 | u32 tsfl; 249 | #if 0 250 | u32 bassn:12; 251 | u32 bavld:1; 252 | u32 reserved3:19; 253 | #endif 254 | }; 255 | 256 | struct rtl8xxxu_rxdesc24 { 257 | #ifdef __LITTLE_ENDIAN 258 | u32 pktlen:14; 259 | u32 crc32:1; 260 | u32 icverr:1; 261 | u32 drvinfo_sz:4; 262 | u32 security:3; 263 | u32 qos:1; 264 | u32 shift:2; 265 | u32 phy_stats:1; 266 | u32 swdec:1; 267 | u32 ls:1; 268 | u32 fs:1; 269 | u32 eor:1; 270 | u32 own:1; 271 | 272 | u32 macid:7; 273 | u32 dummy1_0:1; 274 | u32 tid:4; 275 | u32 dummy1_1:1; 276 | u32 amsdu:1; 277 | u32 rxid_match:1; 278 | u32 paggr:1; 279 | u32 a1fit:4; /* 16 */ 280 | u32 chkerr:1; 281 | u32 ipver:1; 282 | u32 tcpudp:1; 283 | u32 chkvld:1; 284 | u32 pam:1; 285 | u32 pwr:1; 286 | u32 more_data:1; 287 | u32 more_frag:1; 288 | u32 type:2; 289 | u32 mc:1; 290 | u32 bc:1; 291 | 292 | u32 seq:12; 293 | u32 frag:4; 294 | u32 rx_is_qos:1; /* 16 */ 295 | u32 dummy2_0:1; 296 | u32 wlanhd_iv_len:6; 297 | u32 dummy2_1:4; 298 | u32 rpt_sel:1; 299 | u32 dummy2_2:3; 300 | 301 | u32 rxmcs:7; 302 | u32 dummy3_0:3; 303 | u32 htc:1; 304 | u32 eosp:1; 305 | u32 bssidfit:2; 306 | u32 dummy3_1:2; 307 | u32 usb_agg_pktnum:8; /* 16 */ 308 | u32 dummy3_2:5; 309 | u32 pattern_match:1; 310 | u32 unicast_match:1; 311 | u32 magic_match:1; 312 | 313 | u32 splcp:1; 314 | u32 ldcp:1; 315 | u32 stbc:1; 316 | u32 dummy4_0:1; 317 | u32 bw:2; 318 | u32 dummy4_1:26; 319 | #else 320 | u32 own:1; 321 | u32 eor:1; 322 | u32 fs:1; 323 | u32 ls:1; 324 | u32 swdec:1; 325 | u32 phy_stats:1; 326 | u32 shift:2; 327 | u32 qos:1; 328 | u32 security:3; 329 | u32 drvinfo_sz:4; 330 | u32 icverr:1; 331 | u32 crc32:1; 332 | u32 pktlen:14; 333 | 334 | u32 bc:1; 335 | u32 mc:1; 336 | u32 type:2; 337 | u32 mf:1; 338 | u32 md:1; 339 | u32 pwr:1; 340 | u32 pam:1; 341 | u32 a2fit:4; 342 | u32 a1fit:4; 343 | u32 faggr:1; 344 | u32 paggr:1; 345 | u32 amsdu:1; 346 | u32 hwrsvd:4; 347 | u32 tid:4; 348 | u32 macid:5; 349 | 350 | u32 dummy2_2:3; 351 | u32 rpt_sel:1; 352 | u32 dummy2_1:4; 353 | u32 wlanhd_iv_len:6; 354 | u32 dummy2_0:1; 355 | u32 rx_is_qos:1; 356 | u32 frag:4; /* 16 */ 357 | u32 seq:12; 358 | 359 | u32 magic_match:1; 360 | u32 unicast_match:1; 361 | u32 pattern_match:1; 362 | u32 dummy3_2:5; 363 | u32 usb_agg_pktnum:8; 364 | u32 dummy3_1:2; /* 16 */ 365 | u32 bssidfit:2; 366 | u32 eosp:1; 367 | u32 htc:1; 368 | u32 dummy3_0:3; 369 | u32 rxmcs:7; 370 | 371 | u32 dumm4_1:26; 372 | u32 bw:2; 373 | u32 dummy4_0:1; 374 | u32 stbc:1; 375 | u32 ldcp:1; 376 | u32 splcp:1; 377 | #endif 378 | u32 tsfl; 379 | }; 380 | 381 | struct rtl8xxxu_txdesc32 { 382 | __le16 pkt_size; 383 | u8 pkt_offset; 384 | u8 txdw0; 385 | __le32 txdw1; 386 | __le32 txdw2; 387 | __le32 txdw3; 388 | __le32 txdw4; 389 | __le32 txdw5; 390 | __le32 txdw6; 391 | __le16 csum; 392 | __le16 txdw7; 393 | }; 394 | 395 | struct rtl8xxxu_txdesc40 { 396 | __le16 pkt_size; 397 | u8 pkt_offset; 398 | u8 txdw0; 399 | __le32 txdw1; 400 | __le32 txdw2; 401 | __le32 txdw3; 402 | __le32 txdw4; 403 | __le32 txdw5; 404 | __le32 txdw6; 405 | __le16 csum; 406 | __le16 txdw7; 407 | __le32 txdw8; 408 | __le32 txdw9; 409 | }; 410 | 411 | /* CCK Rates, TxHT = 0 */ 412 | #define DESC_RATE_1M 0x00 413 | #define DESC_RATE_2M 0x01 414 | #define DESC_RATE_5_5M 0x02 415 | #define DESC_RATE_11M 0x03 416 | 417 | /* OFDM Rates, TxHT = 0 */ 418 | #define DESC_RATE_6M 0x04 419 | #define DESC_RATE_9M 0x05 420 | #define DESC_RATE_12M 0x06 421 | #define DESC_RATE_18M 0x07 422 | #define DESC_RATE_24M 0x08 423 | #define DESC_RATE_36M 0x09 424 | #define DESC_RATE_48M 0x0a 425 | #define DESC_RATE_54M 0x0b 426 | 427 | /* MCS Rates, TxHT = 1 */ 428 | #define DESC_RATE_MCS0 0x0c 429 | #define DESC_RATE_MCS1 0x0d 430 | #define DESC_RATE_MCS2 0x0e 431 | #define DESC_RATE_MCS3 0x0f 432 | #define DESC_RATE_MCS4 0x10 433 | #define DESC_RATE_MCS5 0x11 434 | #define DESC_RATE_MCS6 0x12 435 | #define DESC_RATE_MCS7 0x13 436 | #define DESC_RATE_MCS8 0x14 437 | #define DESC_RATE_MCS9 0x15 438 | #define DESC_RATE_MCS10 0x16 439 | #define DESC_RATE_MCS11 0x17 440 | #define DESC_RATE_MCS12 0x18 441 | #define DESC_RATE_MCS13 0x19 442 | #define DESC_RATE_MCS14 0x1a 443 | #define DESC_RATE_MCS15 0x1b 444 | #define DESC_RATE_MCS15_SG 0x1c 445 | #define DESC_RATE_MCS32 0x20 446 | 447 | #define TXDESC_OFFSET_SZ 0 448 | #define TXDESC_OFFSET_SHT 16 449 | #if 0 450 | #define TXDESC_BMC BIT(24) 451 | #define TXDESC_LSG BIT(26) 452 | #define TXDESC_FSG BIT(27) 453 | #define TXDESC_OWN BIT(31) 454 | #else 455 | #define TXDESC_BROADMULTICAST BIT(0) 456 | #define TXDESC_HTC BIT(1) 457 | #define TXDESC_LAST_SEGMENT BIT(2) 458 | #define TXDESC_FIRST_SEGMENT BIT(3) 459 | #define TXDESC_LINIP BIT(4) 460 | #define TXDESC_NO_ACM BIT(5) 461 | #define TXDESC_GF BIT(6) 462 | #define TXDESC_OWN BIT(7) 463 | #endif 464 | 465 | /* Word 1 */ 466 | /* 467 | * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 468 | * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 469 | */ 470 | #define TXDESC_PKT_OFFSET_SZ 0 471 | #define TXDESC32_AGG_ENABLE BIT(5) 472 | #define TXDESC32_AGG_BREAK BIT(6) 473 | #define TXDESC40_MACID_SHIFT 0 474 | #define TXDESC40_MACID_MASK 0x00f0 475 | #define TXDESC_QUEUE_SHIFT 8 476 | #define TXDESC_QUEUE_MASK 0x1f00 477 | #define TXDESC_QUEUE_BK 0x2 478 | #define TXDESC_QUEUE_BE 0x0 479 | #define TXDESC_QUEUE_VI 0x5 480 | #define TXDESC_QUEUE_VO 0x7 481 | #define TXDESC_QUEUE_BEACON 0x10 482 | #define TXDESC_QUEUE_HIGH 0x11 483 | #define TXDESC_QUEUE_MGNT 0x12 484 | #define TXDESC_QUEUE_CMD 0x13 485 | #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 486 | #define TXDESC40_RDG_NAV_EXT BIT(13) 487 | #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 488 | #define TXDESC40_PIFS BIT(15) 489 | 490 | #define DESC_RATE_ID_SHIFT 16 491 | #define DESC_RATE_ID_MASK 0xf 492 | #define TXDESC_NAVUSEHDR BIT(20) 493 | #define TXDESC_SEC_RC4 0x00400000 494 | #define TXDESC_SEC_AES 0x00c00000 495 | #define TXDESC_PKT_OFFSET_SHIFT 26 496 | #define TXDESC_AGG_EN BIT(29) 497 | #define TXDESC_HWPC BIT(31) 498 | 499 | /* Word 2 */ 500 | #define TXDESC40_PAID_SHIFT 0 501 | #define TXDESC40_PAID_MASK 0x1ff 502 | #define TXDESC40_CCA_RTS_SHIFT 10 503 | #define TXDESC40_CCA_RTS_MASK 0xc00 504 | #define TXDESC40_AGG_ENABLE BIT(12) 505 | #define TXDESC40_RDG_ENABLE BIT(13) 506 | #define TXDESC40_AGG_BREAK BIT(16) 507 | #define TXDESC40_MORE_FRAG BIT(17) 508 | #define TXDESC40_RAW BIT(18) 509 | #define TXDESC32_ACK_REPORT BIT(19) 510 | #define TXDESC40_SPE_RPT BIT(19) 511 | #define TXDESC_AMPDU_DENSITY_SHIFT 20 512 | #define TXDESC40_BT_INT BIT(23) 513 | #define TXDESC40_GID_SHIFT 24 514 | #define TXDESC_ANTENNA_SELECT_A BIT(24) 515 | #define TXDESC_ANTENNA_SELECT_B BIT(25) 516 | 517 | /* Word 3 */ 518 | #define TXDESC40_USE_DRIVER_RATE BIT(8) 519 | #define TXDESC40_CTS_SELF_ENABLE BIT(11) 520 | #define TXDESC40_RTS_CTS_ENABLE BIT(12) 521 | #define TXDESC40_HW_RTS_ENABLE BIT(13) 522 | #define TXDESC32_SEQ_SHIFT 16 523 | #define TXDESC32_SEQ_MASK 0x0fff0000 524 | 525 | /* Word 4 */ 526 | #define TXDESC32_RTS_RATE_SHIFT 0 527 | #define TXDESC32_RTS_RATE_MASK 0x3f 528 | #define TXDESC32_QOS BIT(6) 529 | #define TXDESC32_HW_SEQ_ENABLE BIT(7) 530 | #define TXDESC32_USE_DRIVER_RATE BIT(8) 531 | #define TXDESC_DISABLE_DATA_FB BIT(10) 532 | #define TXDESC32_CTS_SELF_ENABLE BIT(11) 533 | #define TXDESC32_RTS_CTS_ENABLE BIT(12) 534 | #define TXDESC32_HW_RTS_ENABLE BIT(13) 535 | #define TXDESC32_PT_STAGE_MASK GENMASK(17, 15) 536 | #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 537 | #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 538 | #define TXDESC32_SHORT_PREAMBLE BIT(24) 539 | #define TXDESC_DATA_BW BIT(25) 540 | #define TXDESC_RTS_DATA_BW BIT(27) 541 | #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 542 | #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 543 | #define TXDESC40_DATA_RATE_FB_SHIFT 8 544 | #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 545 | #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 546 | #define TXDESC40_RETRY_LIMIT_SHIFT 18 547 | #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 548 | #define TXDESC40_RTS_RATE_SHIFT 24 549 | #define TXDESC40_RTS_RATE_MASK 0x3f000000 550 | 551 | /* Word 5 */ 552 | #define TXDESC40_SHORT_PREAMBLE BIT(4) 553 | #define TXDESC32_SHORT_GI BIT(6) 554 | #define TXDESC_CCX_TAG BIT(7) 555 | #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 556 | #define TXDESC32_RETRY_LIMIT_SHIFT 18 557 | #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 558 | 559 | /* Word 6 */ 560 | #define TXDESC_MAX_AGG_SHIFT 11 561 | #define TXDESC_USB_TX_AGG_SHIT 24 562 | 563 | /* Word 7 */ 564 | #define TXDESC_ANTENNA_SELECT_C BIT(29) 565 | 566 | /* Word 8 */ 567 | #define TXDESC40_HW_SEQ_ENABLE BIT(15) 568 | 569 | /* Word 9 */ 570 | #define TXDESC40_SEQ_SHIFT 12 571 | #define TXDESC40_SEQ_MASK 0x00fff000 572 | 573 | struct phy_rx_agc_info { 574 | #ifdef __LITTLE_ENDIAN 575 | u8 gain:7, trsw:1; 576 | #else 577 | u8 trsw:1, gain:7; 578 | #endif 579 | }; 580 | 581 | #define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5) 582 | #define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0) 583 | 584 | struct rtl8723au_phy_stats { 585 | struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 586 | u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 587 | u8 cck_sig_qual_ofdm_pwdb_all; 588 | u8 cck_agc_rpt_ofdm_cfosho_a; 589 | u8 cck_rpt_b_ofdm_cfosho_b; 590 | u8 reserved_1; 591 | u8 noise_power_db_msb; 592 | s8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 593 | u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 594 | s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 595 | u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 596 | u8 noise_power_db_lsb; 597 | u8 reserved_2[3]; 598 | u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 599 | u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 600 | s8 sig_evm; 601 | u8 reserved_3; 602 | 603 | #ifdef __LITTLE_ENDIAN 604 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 605 | u8 sgi_en:1; 606 | u8 rxsc:2; 607 | u8 idle_long:1; 608 | u8 r_ant_train_en:1; 609 | u8 antenna_select_b:1; 610 | u8 antenna_select:1; 611 | #else /* _BIG_ENDIAN_ */ 612 | u8 antenna_select:1; 613 | u8 antenna_select_b:1; 614 | u8 r_ant_train_en:1; 615 | u8 idle_long:1; 616 | u8 rxsc:2; 617 | u8 sgi_en:1; 618 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 619 | #endif 620 | }; 621 | 622 | struct jaguar2_phy_stats_type0 { 623 | /* DW0 */ 624 | u8 page_num; 625 | u8 pwdb; 626 | #ifdef __LITTLE_ENDIAN 627 | u8 gain: 6; 628 | u8 rsvd_0: 1; 629 | u8 trsw: 1; 630 | #else 631 | u8 trsw: 1; 632 | u8 rsvd_0: 1; 633 | u8 gain: 6; 634 | #endif 635 | u8 rsvd_1; 636 | 637 | /* DW1 */ 638 | u8 rsvd_2; 639 | #ifdef __LITTLE_ENDIAN 640 | u8 rxsc: 4; 641 | u8 agc_table: 4; 642 | #else 643 | u8 agc_table: 4; 644 | u8 rxsc: 4; 645 | #endif 646 | u8 channel; 647 | u8 band; 648 | 649 | /* DW2 */ 650 | u16 length; 651 | #ifdef __LITTLE_ENDIAN 652 | u8 antidx_a: 3; 653 | u8 antidx_b: 3; 654 | u8 rsvd_3: 2; 655 | u8 antidx_c: 3; 656 | u8 antidx_d: 3; 657 | u8 rsvd_4:2; 658 | #else 659 | u8 rsvd_3: 2; 660 | u8 antidx_b: 3; 661 | u8 antidx_a: 3; 662 | u8 rsvd_4:2; 663 | u8 antidx_d: 3; 664 | u8 antidx_c: 3; 665 | #endif 666 | 667 | /* DW3 */ 668 | u8 signal_quality; 669 | #ifdef __LITTLE_ENDIAN 670 | u8 vga:5; 671 | u8 lna_l:3; 672 | u8 bb_power:6; 673 | u8 rsvd_9:1; 674 | u8 lna_h:1; 675 | #else 676 | u8 lna_l:3; 677 | u8 vga:5; 678 | u8 lna_h:1; 679 | u8 rsvd_9:1; 680 | u8 bb_power:6; 681 | #endif 682 | u8 rsvd_5; 683 | 684 | /* DW4 */ 685 | u32 rsvd_6; 686 | 687 | /* DW5 */ 688 | u32 rsvd_7; 689 | 690 | /* DW6 */ 691 | u32 rsvd_8; 692 | } __packed; 693 | 694 | struct jaguar2_phy_stats_type1 { 695 | /* DW0 and DW1 */ 696 | u8 page_num; 697 | u8 pwdb[4]; 698 | #ifdef __LITTLE_ENDIAN 699 | u8 l_rxsc: 4; 700 | u8 ht_rxsc: 4; 701 | #else 702 | u8 ht_rxsc: 4; 703 | u8 l_rxsc: 4; 704 | #endif 705 | u8 channel; 706 | #ifdef __LITTLE_ENDIAN 707 | u8 band: 2; 708 | u8 rsvd_0: 1; 709 | u8 hw_antsw_occu: 1; 710 | u8 gnt_bt: 1; 711 | u8 ldpc: 1; 712 | u8 stbc: 1; 713 | u8 beamformed: 1; 714 | #else 715 | u8 beamformed: 1; 716 | u8 stbc: 1; 717 | u8 ldpc: 1; 718 | u8 gnt_bt: 1; 719 | u8 hw_antsw_occu: 1; 720 | u8 rsvd_0: 1; 721 | u8 band: 2; 722 | #endif 723 | 724 | /* DW2 */ 725 | u16 lsig_length; 726 | #ifdef __LITTLE_ENDIAN 727 | u8 antidx_a: 3; 728 | u8 antidx_b: 3; 729 | u8 rsvd_1: 2; 730 | u8 antidx_c: 3; 731 | u8 antidx_d: 3; 732 | u8 rsvd_2: 2; 733 | #else 734 | u8 rsvd_1: 2; 735 | u8 antidx_b: 3; 736 | u8 antidx_a: 3; 737 | u8 rsvd_2: 2; 738 | u8 antidx_d: 3; 739 | u8 antidx_c: 3; 740 | #endif 741 | 742 | /* DW3 */ 743 | u8 paid; 744 | #ifdef __LITTLE_ENDIAN 745 | u8 paid_msb: 1; 746 | u8 gid: 6; 747 | u8 rsvd_3: 1; 748 | #else 749 | u8 rsvd_3: 1; 750 | u8 gid: 6; 751 | u8 paid_msb: 1; 752 | #endif 753 | u8 intf_pos; 754 | #ifdef __LITTLE_ENDIAN 755 | u8 intf_pos_msb: 1; 756 | u8 rsvd_4: 2; 757 | u8 nb_intf_flag: 1; 758 | u8 rf_mode: 2; 759 | u8 rsvd_5: 2; 760 | #else 761 | u8 rsvd_5: 2; 762 | u8 rf_mode: 2; 763 | u8 nb_intf_flag: 1; 764 | u8 rsvd_4: 2; 765 | u8 intf_pos_msb: 1; 766 | #endif 767 | 768 | /* DW4 */ 769 | s8 rxevm[4]; /* s(8,1) */ 770 | 771 | /* DW5 */ 772 | s8 cfo_tail[4]; /* s(8,7) */ 773 | 774 | /* DW6 */ 775 | s8 rxsnr[4]; /* s(8,1) */ 776 | } __packed; 777 | 778 | struct jaguar2_phy_stats_type2 { 779 | /* DW0 ane DW1 */ 780 | u8 page_num; 781 | u8 pwdb[4]; 782 | #ifdef __LITTLE_ENDIAN 783 | u8 l_rxsc: 4; 784 | u8 ht_rxsc: 4; 785 | #else 786 | u8 ht_rxsc: 4; 787 | u8 l_rxsc: 4; 788 | #endif 789 | u8 channel; 790 | #ifdef __LITTLE_ENDIAN 791 | u8 band: 2; 792 | u8 rsvd_0: 1; 793 | u8 hw_antsw_occu: 1; 794 | u8 gnt_bt: 1; 795 | u8 ldpc: 1; 796 | u8 stbc: 1; 797 | u8 beamformed: 1; 798 | #else 799 | u8 beamformed: 1; 800 | u8 stbc: 1; 801 | u8 ldpc: 1; 802 | u8 gnt_bt: 1; 803 | u8 hw_antsw_occu: 1; 804 | u8 rsvd_0: 1; 805 | u8 band: 2; 806 | #endif 807 | 808 | /* DW2 */ 809 | #ifdef __LITTLE_ENDIAN 810 | u8 shift_l_map: 6; 811 | u8 rsvd_1: 2; 812 | #else 813 | u8 rsvd_1: 2; 814 | u8 shift_l_map: 6; 815 | #endif 816 | u8 cnt_pw2cca; 817 | #ifdef __LITTLE_ENDIAN 818 | u8 agc_table_a: 4; 819 | u8 agc_table_b: 4; 820 | u8 agc_table_c: 4; 821 | u8 agc_table_d: 4; 822 | #else 823 | u8 agc_table_b: 4; 824 | u8 agc_table_a: 4; 825 | u8 agc_table_d: 4; 826 | u8 agc_table_c: 4; 827 | #endif 828 | 829 | /* DW3 ~ DW6*/ 830 | u8 cnt_cca2agc_rdy; 831 | #ifdef __LITTLE_ENDIAN 832 | u8 gain_a: 6; 833 | u8 rsvd_2: 1; 834 | u8 trsw_a: 1; 835 | u8 gain_b: 6; 836 | u8 rsvd_3: 1; 837 | u8 trsw_b: 1; 838 | u8 gain_c: 6; 839 | u8 rsvd_4: 1; 840 | u8 trsw_c: 1; 841 | u8 gain_d: 6; 842 | u8 rsvd_5: 1; 843 | u8 trsw_d: 1; 844 | u8 aagc_step_a: 2; 845 | u8 aagc_step_b: 2; 846 | u8 aagc_step_c: 2; 847 | u8 aagc_step_d: 2; 848 | #else 849 | u8 trsw_a: 1; 850 | u8 rsvd_2: 1; 851 | u8 gain_a: 6; 852 | u8 trsw_b: 1; 853 | u8 rsvd_3: 1; 854 | u8 gain_b: 6; 855 | u8 trsw_c: 1; 856 | u8 rsvd_4: 1; 857 | u8 gain_c: 6; 858 | u8 trsw_d: 1; 859 | u8 rsvd_5: 1; 860 | u8 gain_d: 6; 861 | u8 aagc_step_d: 2; 862 | u8 aagc_step_c: 2; 863 | u8 aagc_step_b: 2; 864 | u8 aagc_step_a: 2; 865 | #endif 866 | u8 ht_aagc_gain[4]; 867 | u8 dagc_gain[4]; 868 | #ifdef __LITTLE_ENDIAN 869 | u8 counter: 6; 870 | u8 rsvd_6: 2; 871 | u8 syn_count: 5; 872 | u8 rsvd_7:3; 873 | #else 874 | u8 rsvd_6: 2; 875 | u8 counter: 6; 876 | u8 rsvd_7:3; 877 | u8 syn_count: 5; 878 | #endif 879 | } __packed; 880 | 881 | /* 882 | * Regs to backup 883 | */ 884 | #define RTL8XXXU_ADDA_REGS 16 885 | #define RTL8XXXU_MAC_REGS 4 886 | #define RTL8XXXU_BB_REGS 9 887 | 888 | struct rtl8xxxu_firmware_header { 889 | __le16 signature; /* 92C0: test chip; 92C, 890 | 88C0: test chip; 891 | 88C1: MP A-cut; 892 | 92C1: MP A-cut */ 893 | u8 category; /* AP/NIC and USB/PCI */ 894 | u8 function; 895 | 896 | __le16 major_version; /* FW Version */ 897 | u8 minor_version; /* FW Subversion, default 0x00 */ 898 | u8 reserved1; 899 | 900 | u8 month; /* Release time Month field */ 901 | u8 date; /* Release time Date field */ 902 | u8 hour; /* Release time Hour field */ 903 | u8 minute; /* Release time Minute field */ 904 | 905 | __le16 ramcodesize; /* Size of RAM code */ 906 | u16 reserved2; 907 | 908 | __le32 svn_idx; /* SVN entry index */ 909 | u32 reserved3; 910 | 911 | u32 reserved4; 912 | u32 reserved5; 913 | 914 | u8 data[]; 915 | }; 916 | 917 | /* 918 | * 8723au/8192cu/8188ru required base power index offset tables. 919 | */ 920 | struct rtl8xxxu_power_base { 921 | u32 reg_0e00; 922 | u32 reg_0e04; 923 | u32 reg_0e08; 924 | u32 reg_086c; 925 | 926 | u32 reg_0e10; 927 | u32 reg_0e14; 928 | u32 reg_0e18; 929 | u32 reg_0e1c; 930 | 931 | u32 reg_0830; 932 | u32 reg_0834; 933 | u32 reg_0838; 934 | u32 reg_086c_2; 935 | 936 | u32 reg_083c; 937 | u32 reg_0848; 938 | u32 reg_084c; 939 | u32 reg_0868; 940 | }; 941 | 942 | /* 943 | * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 944 | */ 945 | struct rtl8723au_idx { 946 | #ifdef __LITTLE_ENDIAN 947 | int a:4; 948 | int b:4; 949 | #else 950 | int b:4; 951 | int a:4; 952 | #endif 953 | } __attribute__((packed)); 954 | 955 | struct rtl8723au_efuse { 956 | __le16 rtl_id; 957 | u8 res0[0xe]; 958 | u8 cck_tx_power_index_A[3]; /* 0x10 */ 959 | u8 cck_tx_power_index_B[3]; 960 | u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 961 | u8 ht40_1s_tx_power_index_B[3]; 962 | /* 963 | * The following entries are half-bytes split as: 964 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 965 | */ 966 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; 967 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 968 | struct rtl8723au_idx ht40_max_power_offset[3]; 969 | struct rtl8723au_idx ht20_max_power_offset[3]; 970 | u8 channel_plan; /* 0x28 */ 971 | u8 tssi_a; 972 | u8 thermal_meter; 973 | u8 rf_regulatory; 974 | u8 rf_option_2; 975 | u8 rf_option_3; 976 | u8 rf_option_4; 977 | u8 res7; 978 | u8 version /* 0x30 */; 979 | u8 customer_id_major; 980 | u8 customer_id_minor; 981 | u8 xtal_k; 982 | u8 chipset; /* 0x34 */ 983 | u8 res8[0x82]; 984 | u8 vid; /* 0xb7 */ 985 | u8 res9; 986 | u8 pid; /* 0xb9 */ 987 | u8 res10[0x0c]; 988 | u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 989 | u8 res11[2]; 990 | u8 vendor_name[7]; 991 | u8 res12[2]; 992 | u8 device_name[0x29]; /* 0xd7 */ 993 | }; 994 | 995 | struct rtl8192cu_efuse { 996 | __le16 rtl_id; 997 | __le16 hpon; 998 | u8 res0[2]; 999 | __le16 clk; 1000 | __le16 testr; 1001 | __le16 vid; 1002 | __le16 did; 1003 | __le16 svid; 1004 | __le16 smid; /* 0x10 */ 1005 | u8 res1[4]; 1006 | u8 mac_addr[ETH_ALEN]; /* 0x16 */ 1007 | u8 res2[2]; 1008 | u8 vendor_name[7]; 1009 | u8 res3[3]; 1010 | u8 device_name[0x14]; /* 0x28 */ 1011 | u8 res4[0x1e]; /* 0x3c */ 1012 | u8 cck_tx_power_index_A[3]; /* 0x5a */ 1013 | u8 cck_tx_power_index_B[3]; 1014 | u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 1015 | u8 ht40_1s_tx_power_index_B[3]; 1016 | /* 1017 | * The following entries are half-bytes split as: 1018 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1019 | */ 1020 | struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 1021 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 1022 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 1023 | struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 1024 | struct rtl8723au_idx ht20_max_power_offset[3]; 1025 | u8 channel_plan; /* 0x75 */ 1026 | u8 tssi_a; 1027 | u8 tssi_b; 1028 | u8 thermal_meter; /* xtal_k */ /* 0x78 */ 1029 | u8 rf_regulatory; 1030 | u8 rf_option_2; 1031 | u8 rf_option_3; 1032 | u8 rf_option_4; 1033 | u8 res5[1]; /* 0x7d */ 1034 | u8 version; 1035 | u8 customer_id; 1036 | }; 1037 | 1038 | struct rtl8723bu_pwr_idx { 1039 | #ifdef __LITTLE_ENDIAN 1040 | int ht20:4; 1041 | int ht40:4; 1042 | int ofdm:4; 1043 | int cck:4; 1044 | #else 1045 | int cck:4; 1046 | int ofdm:4; 1047 | int ht40:4; 1048 | int ht20:4; 1049 | #endif 1050 | } __attribute__((packed)); 1051 | 1052 | struct rtl8723bu_efuse_tx_power { 1053 | u8 cck_base[6]; 1054 | u8 ht40_base[5]; 1055 | struct rtl8723au_idx ht20_ofdm_1s_diff; 1056 | struct rtl8723bu_pwr_idx pwr_diff[3]; 1057 | u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1058 | }; 1059 | 1060 | struct rtl8723bu_efuse { 1061 | __le16 rtl_id; 1062 | u8 res0[0x0e]; 1063 | struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1064 | struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1065 | struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 1066 | struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 1067 | u8 channel_plan; /* 0xb8 */ 1068 | u8 xtal_k; 1069 | u8 thermal_meter; 1070 | u8 iqk_lck; 1071 | u8 pa_type; /* 0xbc */ 1072 | u8 lna_type_2g; /* 0xbd */ 1073 | u8 res2[3]; 1074 | u8 rf_board_option; 1075 | u8 rf_feature_option; 1076 | u8 rf_bt_setting; 1077 | u8 eeprom_version; 1078 | u8 eeprom_customer_id; 1079 | u8 res3[2]; 1080 | u8 tx_pwr_calibrate_rate; 1081 | u8 rf_antenna_option; /* 0xc9 */ 1082 | u8 rfe_option; 1083 | u8 res4[9]; 1084 | u8 usb_optional_function; 1085 | u8 res5[0x1e]; 1086 | u8 res6[2]; 1087 | u8 serial[0x0b]; /* 0xf5 */ 1088 | u8 vid; /* 0x100 */ 1089 | u8 res7; 1090 | u8 pid; 1091 | u8 res8[4]; 1092 | u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1093 | u8 res9[2]; 1094 | u8 vendor_name[0x07]; 1095 | u8 res10[2]; 1096 | u8 device_name[0x14]; 1097 | u8 res11[0xcf]; 1098 | u8 package_type; /* 0x1fb */ 1099 | u8 res12[0x4]; 1100 | }; 1101 | 1102 | struct rtl8192eu_efuse_tx_power { 1103 | u8 cck_base[6]; 1104 | u8 ht40_base[5]; 1105 | struct rtl8723au_idx ht20_ofdm_1s_diff; 1106 | struct rtl8723bu_pwr_idx pwr_diff[3]; 1107 | u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1108 | }; 1109 | 1110 | struct rtl8192eu_efuse { 1111 | __le16 rtl_id; 1112 | u8 res0[0x0e]; 1113 | struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1114 | struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1115 | u8 res2[0x54]; 1116 | u8 channel_plan; /* 0xb8 */ 1117 | u8 xtal_k; 1118 | u8 thermal_meter; 1119 | u8 iqk_lck; 1120 | u8 pa_type; /* 0xbc */ 1121 | u8 lna_type_2g; /* 0xbd */ 1122 | u8 res3[1]; 1123 | u8 lna_type_5g; /* 0xbf */ 1124 | u8 res4[1]; 1125 | u8 rf_board_option; 1126 | u8 rf_feature_option; 1127 | u8 rf_bt_setting; 1128 | u8 eeprom_version; 1129 | u8 eeprom_customer_id; 1130 | u8 res5[3]; 1131 | u8 rf_antenna_option; /* 0xc9 */ 1132 | u8 res6[6]; 1133 | u8 vid; /* 0xd0 */ 1134 | u8 res7[1]; 1135 | u8 pid; /* 0xd2 */ 1136 | u8 res8[1]; 1137 | u8 usb_optional_function; 1138 | u8 res9[2]; 1139 | u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1140 | u8 device_info[80]; 1141 | u8 res11[3]; 1142 | u8 unknown[0x0d]; /* 0x130 */ 1143 | u8 res12[0xc3]; 1144 | }; 1145 | 1146 | struct rtl8188fu_efuse_tx_power { 1147 | u8 cck_base[6]; 1148 | u8 ht40_base[5]; 1149 | /* a: ofdm; b: ht20 */ 1150 | struct rtl8723au_idx ht20_ofdm_1s_diff; 1151 | }; 1152 | 1153 | struct rtl8188fu_efuse { 1154 | __le16 rtl_id; 1155 | u8 res0[0x0e]; 1156 | struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1157 | u8 res1[0x9c]; /* 0x1c */ 1158 | u8 channel_plan; /* 0xb8 */ 1159 | u8 xtal_k; 1160 | u8 thermal_meter; 1161 | u8 iqk_lck; 1162 | u8 res2[5]; 1163 | u8 rf_board_option; 1164 | u8 rf_feature_option; 1165 | u8 rf_bt_setting; 1166 | u8 eeprom_version; 1167 | u8 eeprom_customer_id; 1168 | u8 res3[2]; 1169 | u8 kfree_thermal_k_on; 1170 | u8 rf_antenna_option; /* 0xc9 */ 1171 | u8 rfe_option; 1172 | u8 country_code; 1173 | u8 res4[4]; 1174 | u8 vid; /* 0xd0 */ 1175 | u8 res5[1]; 1176 | u8 pid; /* 0xd2 */ 1177 | u8 res6[1]; 1178 | u8 usb_optional_function; 1179 | u8 res7[2]; 1180 | u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1181 | u8 res8[2]; 1182 | u8 vendor_name[7]; 1183 | u8 res9[2]; 1184 | u8 device_name[7]; /* 0xe8 */ 1185 | u8 res10[0x41]; 1186 | u8 unknown[0x0d]; /* 0x130 */ 1187 | u8 res11[0xc3]; 1188 | }; 1189 | 1190 | struct rtl8188eu_efuse { 1191 | __le16 rtl_id; 1192 | u8 res0[0x0e]; 1193 | struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1194 | u8 res1[0x7e]; /* 0x3a */ 1195 | u8 channel_plan; /* 0xb8 */ 1196 | u8 xtal_k; 1197 | u8 thermal_meter; 1198 | u8 iqk_lck; 1199 | u8 res2[5]; 1200 | u8 rf_board_option; 1201 | u8 rf_feature_option; 1202 | u8 rf_bt_setting; 1203 | u8 eeprom_version; 1204 | u8 eeprom_customer_id; 1205 | u8 res3[3]; 1206 | u8 rf_antenna_option; /* 0xc9 */ 1207 | u8 res4[6]; 1208 | u8 vid; /* 0xd0 */ 1209 | u8 res5[1]; 1210 | u8 pid; /* 0xd2 */ 1211 | u8 res6[1]; 1212 | u8 usb_optional_function; 1213 | u8 res7[2]; 1214 | u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1215 | u8 res8[2]; 1216 | u8 vendor_name[7]; 1217 | u8 res9[2]; 1218 | u8 device_name[0x0b]; /* 0xe8 */ 1219 | u8 res10[2]; 1220 | u8 serial[0x0b]; /* 0xf5 */ 1221 | u8 res11[0x30]; 1222 | u8 unknown[0x0d]; /* 0x130 */ 1223 | u8 res12[0xc3]; 1224 | } __packed; 1225 | 1226 | struct rtl8710bu_efuse { 1227 | __le16 rtl_id; 1228 | u8 res0[0x1e]; 1229 | struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x20 */ 1230 | u8 res1[0x9c]; /* 0x2c */ 1231 | u8 channel_plan; /* 0xc8 */ 1232 | u8 xtal_k; /* 0xc9 */ 1233 | u8 thermal_meter; /* 0xca */ 1234 | u8 res2[0x4f]; 1235 | u8 mac_addr[ETH_ALEN]; /* 0x11a */ 1236 | u8 res3[0x11]; 1237 | u8 rf_board_option; /* 0x131 */ 1238 | u8 res4[2]; 1239 | u8 eeprom_version; /* 0x134 */ 1240 | u8 eeprom_customer_id; /* 0x135 */ 1241 | u8 res5[5]; 1242 | u8 country_code; /* 0x13b */ 1243 | u8 res6[0x84]; 1244 | u8 vid[2]; /* 0x1c0 */ 1245 | u8 pid[2]; /* 0x1c2 */ 1246 | u8 res7[0x3c]; 1247 | } __packed; 1248 | 1249 | struct rtl8xxxu_reg8val { 1250 | u16 reg; 1251 | u8 val; 1252 | }; 1253 | 1254 | struct rtl8xxxu_reg32val { 1255 | u16 reg; 1256 | u32 val; 1257 | }; 1258 | 1259 | struct rtl8xxxu_rfregval { 1260 | u8 reg; 1261 | u32 val; 1262 | }; 1263 | 1264 | enum rtl8xxxu_rfpath { 1265 | RF_A = 0, 1266 | RF_B = 1, 1267 | }; 1268 | 1269 | struct rtl8xxxu_rfregs { 1270 | u16 hssiparm1; 1271 | u16 hssiparm2; 1272 | u16 lssiparm; 1273 | u16 hspiread; 1274 | u16 lssiread; 1275 | u16 rf_sw_ctrl; 1276 | }; 1277 | 1278 | #define H2C_MAX_MBOX 4 1279 | #define H2C_EXT BIT(7) 1280 | #define H2C_JOIN_BSS_DISCONNECT 0 1281 | #define H2C_JOIN_BSS_CONNECT 1 1282 | 1283 | #define H2C_MACID_ROLE_STA 1 1284 | #define H2C_MACID_ROLE_AP 2 1285 | 1286 | /* 1287 | * H2C (firmware) commands differ between the older generation chips 1288 | * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 1289 | * 8192[de]u, 8192eu, and 8812. 1290 | */ 1291 | enum h2c_cmd_8723a { 1292 | H2C_SET_POWER_MODE = 1, 1293 | H2C_JOIN_BSS_REPORT = 2, 1294 | H2C_SET_RSSI = 5, 1295 | H2C_SET_RATE_MASK = (6 | H2C_EXT), 1296 | }; 1297 | 1298 | enum h2c_cmd_8723b { 1299 | /* 1300 | * Common Class: 000 1301 | */ 1302 | H2C_8723B_RSVD_PAGE = 0x00, 1303 | H2C_8723B_MEDIA_STATUS_RPT = 0x01, 1304 | H2C_8723B_SCAN_ENABLE = 0x02, 1305 | H2C_8723B_KEEP_ALIVE = 0x03, 1306 | H2C_8723B_DISCON_DECISION = 0x04, 1307 | H2C_8723B_PSD_OFFLOAD = 0x05, 1308 | H2C_8723B_AP_OFFLOAD = 0x08, 1309 | H2C_8723B_BCN_RSVDPAGE = 0x09, 1310 | H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 1311 | H2C_8723B_FCS_RSVDPAGE = 0x10, 1312 | H2C_8723B_FCS_INFO = 0x11, 1313 | H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 1314 | 1315 | /* 1316 | * PoweSave Class: 001 1317 | */ 1318 | H2C_8723B_SET_PWR_MODE = 0x20, 1319 | H2C_8723B_PS_TUNING_PARA = 0x21, 1320 | H2C_8723B_PS_TUNING_PARA2 = 0x22, 1321 | H2C_8723B_P2P_LPS_PARAM = 0x23, 1322 | H2C_8723B_P2P_PS_OFFLOAD = 0x24, 1323 | H2C_8723B_PS_SCAN_ENABLE = 0x25, 1324 | H2C_8723B_SAP_PS_ = 0x26, 1325 | H2C_8723B_INACTIVE_PS_ = 0x27, 1326 | H2C_8723B_FWLPS_IN_IPS_ = 0x28, 1327 | 1328 | /* 1329 | * Dynamic Mechanism Class: 010 1330 | */ 1331 | H2C_8723B_MACID_CFG_RAID = 0x40, 1332 | H2C_8723B_TXBF = 0x41, 1333 | H2C_8723B_RSSI_SETTING = 0x42, 1334 | H2C_8723B_AP_REQ_TXRPT = 0x43, 1335 | H2C_8723B_INIT_RATE_COLLECT = 0x44, 1336 | 1337 | /* 1338 | * BT Class: 011 1339 | */ 1340 | H2C_8723B_B_TYPE_TDMA = 0x60, 1341 | H2C_8723B_BT_INFO = 0x61, 1342 | H2C_8723B_FORCE_BT_TXPWR = 0x62, 1343 | H2C_8723B_BT_IGNORE_WLANACT = 0x63, 1344 | H2C_8723B_DAC_SWING_VALUE = 0x64, 1345 | H2C_8723B_ANT_SEL_RSV = 0x65, 1346 | H2C_8723B_WL_OPMODE = 0x66, 1347 | H2C_8723B_BT_MP_OPER = 0x67, 1348 | H2C_8723B_BT_CONTROL = 0x68, 1349 | H2C_8723B_BT_WIFI_CTRL = 0x69, 1350 | H2C_8723B_BT_FW_PATCH = 0x6a, 1351 | H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 1352 | H2C_8723B_BT_GRANT = 0x6e, 1353 | 1354 | /* 1355 | * WOWLAN Class: 100 1356 | */ 1357 | H2C_8723B_WOWLAN = 0x80, 1358 | H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 1359 | H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 1360 | H2C_8723B_AOAC_RSVD_PAGE = 0x83, 1361 | H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 1362 | H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 1363 | H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 1364 | H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 1365 | 1366 | H2C_8723B_RESET_TSF = 0xC0, 1367 | }; 1368 | 1369 | 1370 | struct h2c_cmd { 1371 | union { 1372 | struct { 1373 | u8 cmd; 1374 | u8 data[7]; 1375 | } __packed cmd; 1376 | struct { 1377 | __le32 data; 1378 | __le16 ext; 1379 | } __packed raw; 1380 | struct { 1381 | __le32 data; 1382 | __le32 ext; 1383 | } __packed raw_wide; 1384 | struct { 1385 | u8 cmd; 1386 | u8 data; 1387 | } __packed joinbss; 1388 | struct { 1389 | u8 cmd; 1390 | __le16 mask_hi; 1391 | u8 arg; 1392 | __le16 mask_lo; 1393 | } __packed ramask; 1394 | struct { 1395 | u8 cmd; 1396 | u8 parm; 1397 | u8 macid; 1398 | u8 macid_end; 1399 | } __packed media_status_rpt; 1400 | struct { 1401 | u8 cmd; 1402 | u8 macid; 1403 | /* 1404 | * [0:4] - RAID 1405 | * [7] - SGI 1406 | */ 1407 | u8 data1; 1408 | /* 1409 | * [0:1] - Bandwidth 1410 | * [3] - No Update 1411 | * [4:5] - VHT enable 1412 | * [6] - DISPT 1413 | * [7] - DISRA 1414 | */ 1415 | u8 data2; 1416 | u8 ramask0; 1417 | u8 ramask1; 1418 | u8 ramask2; 1419 | u8 ramask3; 1420 | } __packed b_macid_cfg; 1421 | struct { 1422 | u8 cmd; 1423 | u8 data1; 1424 | u8 data2; 1425 | u8 data3; 1426 | u8 data4; 1427 | u8 data5; 1428 | } __packed b_type_dma; 1429 | struct { 1430 | u8 cmd; 1431 | u8 data; 1432 | } __packed bt_info; 1433 | struct { 1434 | u8 cmd; 1435 | u8 operreq; 1436 | u8 opcode; 1437 | u8 data; 1438 | u8 addr; 1439 | } __packed bt_mp_oper; 1440 | struct { 1441 | u8 cmd; 1442 | u8 data; 1443 | } __packed bt_wlan_calibration; 1444 | struct { 1445 | u8 cmd; 1446 | u8 data; 1447 | } __packed ignore_wlan; 1448 | struct { 1449 | u8 cmd; 1450 | u8 ant_inverse; 1451 | u8 int_switch_type; 1452 | } __packed ant_sel_rsv; 1453 | struct { 1454 | u8 cmd; 1455 | u8 data; 1456 | } __packed bt_grant; 1457 | struct { 1458 | u8 cmd; 1459 | u8 macid; 1460 | u8 unknown0; 1461 | u8 rssi; 1462 | /* 1463 | * [0] - is_rx 1464 | * [1] - stbc_en 1465 | * [2] - noisy_decision 1466 | * [6] - bf_en 1467 | */ 1468 | u8 data; 1469 | /* 1470 | * [0:6] - ra_th_offset 1471 | * [7] - ra_offset_direction 1472 | */ 1473 | u8 ra_th_offset; 1474 | u8 unknown1; 1475 | u8 unknown2; 1476 | } __packed rssi_report; 1477 | }; 1478 | }; 1479 | 1480 | enum c2h_evt_8723b { 1481 | C2H_8723B_DEBUG = 0, 1482 | C2H_8723B_TSF = 1, 1483 | C2H_8723B_AP_RPT_RSP = 2, 1484 | C2H_8723B_CCX_TX_RPT = 3, 1485 | C2H_8723B_BT_RSSI = 4, 1486 | C2H_8723B_BT_OP_MODE = 5, 1487 | C2H_8723B_EXT_RA_RPT = 6, 1488 | C2H_8723B_BT_INFO = 9, 1489 | C2H_8723B_HW_INFO_EXCH = 0x0a, 1490 | C2H_8723B_BT_MP_INFO = 0x0b, 1491 | C2H_8723B_RA_REPORT = 0x0c, 1492 | C2H_8723B_FW_DEBUG = 0xff, 1493 | }; 1494 | 1495 | enum bt_info_src_8723b { 1496 | BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1497 | BT_INFO_SRC_8723B_BT_RSP = 0x1, 1498 | BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1499 | }; 1500 | 1501 | enum bt_mp_oper_opcode_8723b { 1502 | BT_MP_OP_GET_BT_VERSION = 0x00, 1503 | BT_MP_OP_RESET = 0x01, 1504 | BT_MP_OP_TEST_CTRL = 0x02, 1505 | BT_MP_OP_SET_BT_MODE = 0x03, 1506 | BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1507 | BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1508 | BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1509 | BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1510 | BT_MP_OP_SET_PKT_HEADER = 0x08, 1511 | BT_MP_OP_SET_WHITENCOEFF = 0x09, 1512 | BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1513 | BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1514 | BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1515 | BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1516 | BT_MP_OP_GET_BT_STATUS = 0x0e, 1517 | BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1518 | BT_MP_OP_GET_BD_ADDR_H = 0x10, 1519 | BT_MP_OP_READ_REG = 0x11, 1520 | BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1521 | BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1522 | BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1523 | BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1524 | BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1525 | BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1526 | BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1527 | BT_MP_OP_GET_RSSI = 0x19, 1528 | BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1529 | BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1530 | BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1531 | BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1532 | BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1533 | BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1534 | BT_MP_OP_GET_AFH_MAP_H = 0x20, 1535 | BT_MP_OP_GET_AFH_STATUS = 0x21, 1536 | BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1537 | BT_MP_OP_SET_THERMAL_METER = 0x23, 1538 | BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1539 | }; 1540 | 1541 | enum rtl8xxxu_bw_mode { 1542 | RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1543 | RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1544 | RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1545 | RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1546 | RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1547 | RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1548 | }; 1549 | 1550 | struct rtl8723bu_c2h { 1551 | u8 id; 1552 | u8 seq; 1553 | union { 1554 | struct { 1555 | u8 payload[0]; 1556 | } __packed raw; 1557 | struct { 1558 | u8 ext_id; 1559 | u8 status:4; 1560 | u8 retlen:4; 1561 | u8 opcode_ver:4; 1562 | u8 req_num:4; 1563 | u8 payload[2]; 1564 | } __packed bt_mp_info; 1565 | struct { 1566 | u8 response_source:4; 1567 | u8 dummy0_0:4; 1568 | 1569 | u8 bt_info; 1570 | 1571 | u8 retry_count:4; 1572 | u8 dummy2_0:1; 1573 | u8 bt_page:1; 1574 | u8 tx_rx_mask:1; 1575 | u8 dummy2_2:1; 1576 | 1577 | u8 rssi; 1578 | 1579 | u8 basic_rate:1; 1580 | u8 bt_has_reset:1; 1581 | u8 dummy4_1:1; 1582 | u8 ignore_wlan:1; 1583 | u8 auto_report:1; 1584 | u8 dummy4_2:3; 1585 | 1586 | u8 a4; 1587 | u8 a5; 1588 | } __packed bt_info; 1589 | struct { 1590 | u8 rate:7; 1591 | u8 sgi:1; 1592 | u8 macid; 1593 | u8 ldpc:1; 1594 | u8 txbf:1; 1595 | u8 noisy_state:1; 1596 | u8 dummy2_0:5; 1597 | u8 dummy3_0; 1598 | u8 dummy4_0; 1599 | u8 dummy5_0; 1600 | u8 bw; 1601 | } __packed ra_report; 1602 | }; 1603 | } __packed; 1604 | 1605 | struct rtl8xxxu_fileops; 1606 | 1607 | /*mlme related.*/ 1608 | enum wireless_mode { 1609 | WIRELESS_MODE_UNKNOWN = 0, 1610 | /* Sub-Element */ 1611 | WIRELESS_MODE_B = BIT(0), 1612 | WIRELESS_MODE_G = BIT(1), 1613 | WIRELESS_MODE_A = BIT(2), 1614 | WIRELESS_MODE_N_24G = BIT(3), 1615 | WIRELESS_MODE_N_5G = BIT(4), 1616 | WIRELESS_AUTO = BIT(5), 1617 | WIRELESS_MODE_AC = BIT(6), 1618 | WIRELESS_MODE_MAX = 0x7F, 1619 | }; 1620 | 1621 | /* from rtlwifi/wifi.h */ 1622 | enum ratr_table_mode_new { 1623 | RATEID_IDX_BGN_40M_2SS = 0, 1624 | RATEID_IDX_BGN_40M_1SS = 1, 1625 | RATEID_IDX_BGN_20M_2SS_BN = 2, 1626 | RATEID_IDX_BGN_20M_1SS_BN = 3, 1627 | RATEID_IDX_GN_N2SS = 4, 1628 | RATEID_IDX_GN_N1SS = 5, 1629 | RATEID_IDX_BG = 6, 1630 | RATEID_IDX_G = 7, 1631 | RATEID_IDX_B = 8, 1632 | RATEID_IDX_VHT_2SS = 9, 1633 | RATEID_IDX_VHT_1SS = 10, 1634 | RATEID_IDX_MIX1 = 11, 1635 | RATEID_IDX_MIX2 = 12, 1636 | RATEID_IDX_VHT_3SS = 13, 1637 | RATEID_IDX_BGN_3SS = 14, 1638 | }; 1639 | 1640 | #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1641 | #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1642 | #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1643 | #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1644 | #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1645 | #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1646 | #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1647 | #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1648 | 1649 | enum _BT_8723B_1ANT_STATUS { 1650 | BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1651 | BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1652 | BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1653 | BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1654 | BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1655 | BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1656 | BT_8723B_1ANT_STATUS_MAX 1657 | }; 1658 | 1659 | struct rtl8xxxu_btcoex { 1660 | u8 bt_status; 1661 | bool bt_busy; 1662 | bool has_sco; 1663 | bool has_a2dp; 1664 | bool has_hid; 1665 | bool has_pan; 1666 | bool hid_only; 1667 | bool a2dp_only; 1668 | bool c2h_bt_inquiry; 1669 | }; 1670 | 1671 | #define RTL8XXXU_RATR_STA_INIT 0 1672 | #define RTL8XXXU_RATR_STA_HIGH 1 1673 | #define RTL8XXXU_RATR_STA_MID 2 1674 | #define RTL8XXXU_RATR_STA_LOW 3 1675 | 1676 | #define RTL8XXXU_NOISE_FLOOR_MIN -100 1677 | #define RTL8XXXU_SNR_THRESH_HIGH 50 1678 | #define RTL8XXXU_SNR_THRESH_LOW 20 1679 | 1680 | struct rtl8xxxu_ra_report { 1681 | struct rate_info txrate; 1682 | u32 bit_rate; 1683 | u8 desc_rate; 1684 | }; 1685 | 1686 | struct rtl8xxxu_ra_info { 1687 | u8 rate_id; 1688 | u32 rate_mask; 1689 | u32 ra_use_rate; 1690 | u8 rate_sgi; 1691 | u8 rssi_sta_ra; /* Percentage */ 1692 | u8 pre_rssi_sta_ra; 1693 | u8 sgi_enable; 1694 | u8 decision_rate; 1695 | u8 pre_rate; 1696 | u8 highest_rate; 1697 | u8 lowest_rate; 1698 | u32 nsc_up; 1699 | u32 nsc_down; 1700 | u32 total; 1701 | u16 retry[5]; 1702 | u16 drop; 1703 | u16 rpt_time; 1704 | u16 pre_min_rpt_time; 1705 | u8 dynamic_tx_rpt_timing_counter; 1706 | u8 ra_waiting_counter; 1707 | u8 ra_pending_counter; 1708 | u8 ra_drop_after_down; 1709 | u8 pt_try_state; /* 0 trying state, 1 for decision state */ 1710 | u8 pt_stage; /* 0~6 */ 1711 | u8 pt_stop_count; /* Stop PT counter */ 1712 | u8 pt_pre_rate; /* if rate change do PT */ 1713 | u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 1714 | u8 pt_mode_ss; /* decide which rate should do PT */ 1715 | u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 1716 | u8 pt_smooth_factor; 1717 | }; 1718 | 1719 | #define CFO_TH_XTAL_HIGH 20 /* kHz */ 1720 | #define CFO_TH_XTAL_LOW 10 /* kHz */ 1721 | #define CFO_TH_ATC 80 /* kHz */ 1722 | 1723 | struct rtl8xxxu_cfo_tracking { 1724 | bool adjust; 1725 | bool atc_status; 1726 | int cfo_tail[2]; 1727 | u8 crystal_cap; 1728 | u32 packet_count; 1729 | u32 packet_count_pre; 1730 | }; 1731 | 1732 | #define RTL8XXXU_HW_LED_CONTROL 2 1733 | #define RTL8XXXU_MAX_MAC_ID_NUM 128 1734 | #define RTL8XXXU_BC_MC_MACID 0 1735 | 1736 | struct rtl8xxxu_priv { 1737 | struct ieee80211_hw *hw; 1738 | struct usb_device *udev; 1739 | struct rtl8xxxu_fileops *fops; 1740 | 1741 | spinlock_t tx_urb_lock; 1742 | struct list_head tx_urb_free_list; 1743 | int tx_urb_free_count; 1744 | bool tx_stopped; 1745 | 1746 | spinlock_t rx_urb_lock; 1747 | struct list_head rx_urb_pending_list; 1748 | int rx_urb_pending_count; 1749 | bool shutdown; 1750 | struct work_struct rx_urb_wq; 1751 | 1752 | bool beacon_enabled; 1753 | 1754 | u8 mac_addr[ETH_ALEN]; 1755 | char chip_name[8]; 1756 | char chip_vendor[8]; 1757 | u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1758 | u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1759 | u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1760 | u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1761 | /* 1762 | * The following entries are half-bytes split as: 1763 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1764 | */ 1765 | struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1766 | RTL8723A_CHANNEL_GROUPS]; 1767 | struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1768 | struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1769 | struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1770 | struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1771 | /* 1772 | * Newer generation chips only keep power diffs per TX count, 1773 | * not per channel group. 1774 | */ 1775 | struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1776 | struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1777 | struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1778 | struct rtl8xxxu_power_base *power_base; 1779 | u8 package_type; 1780 | u32 chip_cut:4; 1781 | u32 rom_rev:4; 1782 | u32 is_multi_func:1; 1783 | u32 has_wifi:1; 1784 | u32 has_bluetooth:1; 1785 | u32 enable_bluetooth:1; 1786 | u32 has_gps:1; 1787 | u32 hi_pa:1; 1788 | u32 vendor_umc:1; 1789 | u32 vendor_smic:1; 1790 | u32 has_polarity_ctrl:1; 1791 | u32 has_eeprom:1; 1792 | u32 boot_eeprom:1; 1793 | u32 usb_interrupts:1; 1794 | u32 ep_tx_high_queue:1; 1795 | u32 ep_tx_normal_queue:1; 1796 | u32 ep_tx_low_queue:1; 1797 | u32 rx_buf_aggregation:1; 1798 | u32 cck_agc_report_type:1; 1799 | u32 cck_new_agc:1; 1800 | u8 default_crystal_cap; 1801 | unsigned int pipe_interrupt; 1802 | unsigned int pipe_in; 1803 | unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1804 | u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1805 | u8 ep_tx_count; 1806 | u8 rf_paths; 1807 | u8 rx_paths; 1808 | u8 tx_paths; 1809 | u32 rege94; 1810 | u32 rege9c; 1811 | u32 regeb4; 1812 | u32 regebc; 1813 | int next_mbox; 1814 | int nr_out_eps; 1815 | 1816 | struct mutex h2c_mutex; 1817 | /* Protect the indirect register accesses of RTL8710BU. */ 1818 | struct mutex syson_indirect_access_mutex; 1819 | 1820 | struct usb_anchor rx_anchor; 1821 | struct usb_anchor tx_anchor; 1822 | struct usb_anchor int_anchor; 1823 | struct rtl8xxxu_firmware_header *fw_data; 1824 | size_t fw_size; 1825 | struct mutex usb_buf_mutex; 1826 | union { 1827 | __le32 val32; 1828 | __le16 val16; 1829 | u8 val8; 1830 | } usb_buf; 1831 | union { 1832 | u8 raw[EFUSE_MAP_LEN]; 1833 | struct rtl8723au_efuse efuse8723; 1834 | struct rtl8723bu_efuse efuse8723bu; 1835 | struct rtl8192cu_efuse efuse8192; 1836 | struct rtl8192eu_efuse efuse8192eu; 1837 | struct rtl8188fu_efuse efuse8188fu; 1838 | struct rtl8188eu_efuse efuse8188eu; 1839 | struct rtl8710bu_efuse efuse8710bu; 1840 | } efuse_wifi; 1841 | u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1842 | u32 mac_backup[RTL8XXXU_MAC_REGS]; 1843 | u32 bb_backup[RTL8XXXU_BB_REGS]; 1844 | u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1845 | enum rtl8xxxu_rtl_chip rtl_chip; 1846 | u8 pi_enabled:1; 1847 | u8 no_pape:1; 1848 | u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1849 | u8 rssi_level; 1850 | DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS); 1851 | DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS); 1852 | /* 1853 | * Only one virtual interface permitted because only STA mode 1854 | * is supported and no iface_combinations are provided. 1855 | */ 1856 | struct ieee80211_vif *vif; 1857 | struct delayed_work ra_watchdog; 1858 | struct work_struct c2hcmd_work; 1859 | struct sk_buff_head c2hcmd_queue; 1860 | struct work_struct update_beacon_work; 1861 | struct rtl8xxxu_btcoex bt_coex; 1862 | struct rtl8xxxu_ra_report ra_report; 1863 | struct rtl8xxxu_cfo_tracking cfo_tracking; 1864 | struct rtl8xxxu_ra_info ra_info; 1865 | 1866 | bool led_registered; 1867 | char led_name[32]; 1868 | struct led_classdev led_cdev; 1869 | DECLARE_BITMAP(mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 1870 | }; 1871 | 1872 | struct rtl8xxxu_sta_info { 1873 | struct ieee80211_sta *sta; 1874 | struct ieee80211_vif *vif; 1875 | 1876 | u8 macid; 1877 | }; 1878 | 1879 | struct rtl8xxxu_rx_urb { 1880 | struct urb urb; 1881 | struct ieee80211_hw *hw; 1882 | struct list_head list; 1883 | }; 1884 | 1885 | struct rtl8xxxu_tx_urb { 1886 | struct urb urb; 1887 | struct ieee80211_hw *hw; 1888 | struct list_head list; 1889 | }; 1890 | 1891 | struct rtl8xxxu_fileops { 1892 | int (*identify_chip) (struct rtl8xxxu_priv *priv); 1893 | int (*read_efuse) (struct rtl8xxxu_priv *priv); 1894 | int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1895 | int (*load_firmware) (struct rtl8xxxu_priv *priv); 1896 | int (*power_on) (struct rtl8xxxu_priv *priv); 1897 | void (*power_off) (struct rtl8xxxu_priv *priv); 1898 | void (*reset_8051) (struct rtl8xxxu_priv *priv); 1899 | int (*llt_init) (struct rtl8xxxu_priv *priv); 1900 | void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1901 | int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1902 | void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1903 | void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); 1904 | void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1905 | void (*config_channel) (struct ieee80211_hw *hw); 1906 | int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1907 | void (*parse_phystats) (struct rtl8xxxu_priv *priv, 1908 | struct ieee80211_rx_status *rx_status, 1909 | struct rtl8723au_phy_stats *phy_stats, 1910 | u32 rxmcs, struct ieee80211_hdr *hdr, 1911 | bool crc_icv_err); 1912 | void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1913 | void (*init_statistics) (struct rtl8xxxu_priv *priv); 1914 | void (*init_burst) (struct rtl8xxxu_priv *priv); 1915 | void (*enable_rf) (struct rtl8xxxu_priv *priv); 1916 | void (*disable_rf) (struct rtl8xxxu_priv *priv); 1917 | void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1918 | void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1919 | bool ht40); 1920 | void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1921 | u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 1922 | u8 macid); 1923 | void (*report_connect) (struct rtl8xxxu_priv *priv, 1924 | u8 macid, u8 role, bool connect); 1925 | void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1926 | void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1927 | struct ieee80211_tx_info *tx_info, 1928 | struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1929 | bool short_preamble, bool ampdu_enable, 1930 | u32 rts_rate, u8 macid); 1931 | void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap); 1932 | s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 1933 | int (*led_classdev_brightness_set) (struct led_classdev *led_cdev, 1934 | enum led_brightness brightness); 1935 | int writeN_block_size; 1936 | int rx_agg_buf_size; 1937 | char tx_desc_size; 1938 | char rx_desc_size; 1939 | u8 has_s0s1:1; 1940 | u8 has_tx_report:1; 1941 | u8 gen2_thermal_meter:1; 1942 | u8 needs_full_init:1; 1943 | u8 init_reg_rxfltmap:1; 1944 | u8 init_reg_pkt_life_time:1; 1945 | u8 init_reg_hmtfr:1; 1946 | u8 ampdu_max_time; 1947 | u8 ustime_tsf_edca; 1948 | u8 supports_ap:1; 1949 | u16 max_sta_num; 1950 | u32 adda_1t_init; 1951 | u32 adda_1t_path_on; 1952 | u32 adda_2t_path_on_a; 1953 | u32 adda_2t_path_on_b; 1954 | u16 trxff_boundary; 1955 | u8 pbp_rx; 1956 | u8 pbp_tx; 1957 | const struct rtl8xxxu_reg8val *mactable; 1958 | u8 total_page_num; 1959 | u8 page_num_hi; 1960 | u8 page_num_lo; 1961 | u8 page_num_norm; 1962 | u8 last_llt_entry; 1963 | }; 1964 | 1965 | extern int rtl8xxxu_debug; 1966 | 1967 | extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 1968 | extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 1969 | u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 1970 | u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 1971 | u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 1972 | int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 1973 | int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 1974 | int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 1975 | int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 1976 | int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 1977 | int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 1978 | int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 1979 | int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 1980 | int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 1981 | int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 1982 | u32 mask, u32 val); 1983 | 1984 | u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 1985 | enum rtl8xxxu_rfpath path, u8 reg); 1986 | int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 1987 | enum rtl8xxxu_rfpath path, u8 reg, u32 data); 1988 | int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 1989 | enum rtl8xxxu_rfpath path, u8 reg, 1990 | u32 mask, u32 val); 1991 | void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1992 | u32 *backup, int count); 1993 | void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1994 | u32 *backup, int count); 1995 | void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 1996 | const u32 *reg, u32 *backup); 1997 | void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 1998 | const u32 *reg, u32 *backup); 1999 | void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2000 | bool path_a_on); 2001 | void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 2002 | const u32 *regs, u32 *backup); 2003 | void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2004 | int result[][8], int candidate, bool tx_only); 2005 | void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2006 | int result[][8], int candidate, bool tx_only); 2007 | int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2008 | const struct rtl8xxxu_rfregval *table, 2009 | enum rtl8xxxu_rfpath path); 2010 | int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2011 | const struct rtl8xxxu_reg32val *array); 2012 | int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); 2013 | void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 2014 | void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 2015 | void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); 2016 | void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); 2017 | void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); 2018 | int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); 2019 | int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); 2020 | int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv); 2021 | void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 2022 | int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 2023 | void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 2024 | void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2025 | void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2026 | int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 2027 | int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 2028 | struct h2c_cmd *h2c, int len); 2029 | int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 2030 | void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 2031 | int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 2032 | void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 2033 | void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 2034 | void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 2035 | int channel, bool ht40); 2036 | void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, 2037 | int channel, bool ht40); 2038 | void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 2039 | void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 2040 | void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 2041 | void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 2042 | void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 2043 | u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2044 | void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 2045 | u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2046 | void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 2047 | u8 macid, u8 role, bool connect); 2048 | void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 2049 | u8 macid, u8 role, bool connect); 2050 | void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2051 | void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2052 | void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 2053 | void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 2054 | void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 2055 | void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 2056 | void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); 2057 | int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2058 | int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2059 | void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2060 | struct ieee80211_rx_status *rx_status, 2061 | struct rtl8723au_phy_stats *phy_stats, 2062 | u32 rxmcs, struct ieee80211_hdr *hdr, 2063 | bool crc_icv_err); 2064 | void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2065 | struct ieee80211_rx_status *rx_status, 2066 | struct rtl8723au_phy_stats *phy_stats, 2067 | u32 rxmcs, struct ieee80211_hdr *hdr, 2068 | bool crc_icv_err); 2069 | int rtl8xxxu_gen2_channel_to_group(int channel); 2070 | bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2071 | int result[][8], int c1, int c2); 2072 | bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2073 | int result[][8], int c1, int c2); 2074 | void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2075 | struct ieee80211_tx_info *tx_info, 2076 | struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 2077 | bool short_preamble, bool ampdu_enable, 2078 | u32 rts_rate, u8 macid); 2079 | void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2080 | struct ieee80211_tx_info *tx_info, 2081 | struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2082 | bool short_preamble, bool ampdu_enable, 2083 | u32 rts_rate, u8 macid); 2084 | void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2085 | struct ieee80211_tx_info *tx_info, 2086 | struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2087 | bool short_preamble, bool ampdu_enable, 2088 | u32 rts_rate, u8 macid); 2089 | void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 2090 | u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 2091 | void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); 2092 | void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2093 | void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2094 | s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 2095 | void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 2096 | u8 rate, u8 sgi, u8 bw); 2097 | void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); 2098 | void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2099 | 2100 | extern struct rtl8xxxu_fileops rtl8710bu_fops; 2101 | extern struct rtl8xxxu_fileops rtl8188fu_fops; 2102 | extern struct rtl8xxxu_fileops rtl8188eu_fops; 2103 | extern struct rtl8xxxu_fileops rtl8192cu_fops; 2104 | extern struct rtl8xxxu_fileops rtl8192eu_fops; 2105 | extern struct rtl8xxxu_fileops rtl8723au_fops; 2106 | extern struct rtl8xxxu_fileops rtl8723bu_fops; 2107 | -------------------------------------------------------------------------------- /rtl8xxxu_8188f.c: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0-only 2 | /* 3 | * RTL8XXXU mac80211 USB driver - 8188f specific subdriver 4 | * 5 | * Copyright (c) 2022 Bitterblue Smith 6 | * 7 | * Portions copied from existing rtl8xxxu code: 8 | * Copyright (c) 2014 - 2017 Jes Sorensen 9 | * 10 | * Portions, notably calibration code: 11 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 12 | */ 13 | 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include "rtl8xxxu.h" 31 | #include "rtl8xxxu_regs.h" 32 | 33 | static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { 34 | {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, 35 | {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, 36 | {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, 37 | {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, 38 | {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, 39 | {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, 40 | {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, 41 | {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, 42 | {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, 43 | {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, 44 | {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, 45 | {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, 46 | {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, 47 | {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, 48 | {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, 49 | {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, 50 | {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, 51 | {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, 52 | {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, 53 | {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, 54 | {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, 55 | {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, 56 | {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, 57 | {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, 58 | {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, 59 | {0x70B, 0x87}, 60 | {0xffff, 0xff}, 61 | }; 62 | 63 | static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { 64 | {0x800, 0x80045700}, {0x804, 0x00000001}, 65 | {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, 66 | {0x810, 0x10001331}, {0x814, 0x020C3D10}, 67 | {0x818, 0x00200385}, {0x81C, 0x00000000}, 68 | {0x820, 0x01000100}, {0x824, 0x00390204}, 69 | {0x828, 0x00000000}, {0x82C, 0x00000000}, 70 | {0x830, 0x00000000}, {0x834, 0x00000000}, 71 | {0x838, 0x00000000}, {0x83C, 0x00000000}, 72 | {0x840, 0x00010000}, {0x844, 0x00000000}, 73 | {0x848, 0x00000000}, {0x84C, 0x00000000}, 74 | {0x850, 0x00030000}, {0x854, 0x00000000}, 75 | {0x858, 0x569A569A}, {0x85C, 0x569A569A}, 76 | {0x860, 0x00000130}, {0x864, 0x00000000}, 77 | {0x868, 0x00000000}, {0x86C, 0x27272700}, 78 | {0x870, 0x00000000}, {0x874, 0x25004000}, 79 | {0x878, 0x00000808}, {0x87C, 0x004F0201}, 80 | {0x880, 0xB0000B1E}, {0x884, 0x00000007}, 81 | {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, 82 | {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, 83 | {0x898, 0x40302010}, {0x89C, 0x00706050}, 84 | {0x900, 0x00000000}, {0x904, 0x00000023}, 85 | {0x908, 0x00000000}, {0x90C, 0x81121111}, 86 | {0x910, 0x00000002}, {0x914, 0x00000201}, 87 | {0x948, 0x99000000}, {0x94C, 0x00000010}, 88 | {0x950, 0x20003000}, {0x954, 0x4A880000}, 89 | {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, 90 | {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, 91 | {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, 92 | {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, 93 | {0xA14, 0x1114D028}, {0xA18, 0x00881117}, 94 | {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, 95 | {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, 96 | {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, 97 | {0xA74, 0x00000007}, {0xA78, 0x00000900}, 98 | {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, 99 | {0xA84, 0x00120000}, {0xA88, 0x040C0000}, 100 | {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, 101 | {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, 102 | {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, 103 | {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, 104 | {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, 105 | {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, 106 | {0xC14, 0x40000100}, {0xC18, 0x08800000}, 107 | {0xC1C, 0x40000100}, {0xC20, 0x00000000}, 108 | {0xC24, 0x00000000}, {0xC28, 0x00000000}, 109 | {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, 110 | {0xC34, 0x31000040}, {0xC38, 0x21688080}, 111 | {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, 112 | {0xC44, 0x00010036}, {0xC48, 0xEC020107}, 113 | {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, 114 | {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, 115 | {0xC5C, 0x00250492}, {0xC60, 0x00000000}, 116 | {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, 117 | {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, 118 | {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, 119 | {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, 120 | {0xC84, 0x11F60000}, 121 | {0xC88, 0x40000100}, {0xC8C, 0x20200000}, 122 | {0xC90, 0x00091521}, {0xC94, 0x00000000}, 123 | {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, 124 | {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, 125 | {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, 126 | {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, 127 | {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, 128 | {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, 129 | {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, 130 | {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, 131 | {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, 132 | {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, 133 | {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, 134 | {0xD00, 0x04030740}, {0xD04, 0x40020401}, 135 | {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, 136 | {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, 137 | {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, 138 | {0xD30, 0x00000000}, {0xD34, 0x80608000}, 139 | {0xD38, 0x98000000}, {0xD3C, 0x40127353}, 140 | {0xD40, 0x00000000}, {0xD44, 0x00000000}, 141 | {0xD48, 0x00000000}, {0xD4C, 0x00000000}, 142 | {0xD50, 0x6437140A}, {0xD54, 0x00000000}, 143 | {0xD58, 0x00000282}, {0xD5C, 0x30032064}, 144 | {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, 145 | {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, 146 | {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, 147 | {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, 148 | {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, 149 | {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, 150 | {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, 151 | {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, 152 | {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, 153 | {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, 154 | {0xE44, 0x01004800}, {0xE48, 0xFB000000}, 155 | {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, 156 | {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, 157 | {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, 158 | {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, 159 | {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, 160 | {0xE74, 0x02000010}, {0xE78, 0x02000010}, 161 | {0xE7C, 0x02000010}, {0xE80, 0x02000010}, 162 | {0xE84, 0x01C00010}, {0xE88, 0x02000010}, 163 | {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, 164 | {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, 165 | {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, 166 | {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, 167 | {0xF4C, 0x00000000}, {0xF00, 0x00000300}, 168 | {0xffff, 0xffffffff}, 169 | }; 170 | 171 | static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { 172 | {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, 173 | {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, 174 | {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, 175 | {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, 176 | {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, 177 | {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, 178 | {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, 179 | {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, 180 | {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, 181 | {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, 182 | {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, 183 | {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, 184 | {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, 185 | {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, 186 | {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, 187 | {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, 188 | {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, 189 | {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, 190 | {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, 191 | {0xC78, 0x65260001}, {0xC78, 0x64270001}, 192 | {0xC78, 0x63280001}, {0xC78, 0x62290001}, 193 | {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, 194 | {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, 195 | {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, 196 | {0xC78, 0x21300001}, {0xC78, 0x20310001}, 197 | {0xC78, 0x05320001}, {0xC78, 0x04330001}, 198 | {0xC78, 0x03340001}, {0xC78, 0x02350001}, 199 | {0xC78, 0x01360001}, {0xC78, 0x00370001}, 200 | {0xC78, 0x00380001}, {0xC78, 0x00390001}, 201 | {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, 202 | {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, 203 | {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, 204 | {0xC50, 0x69553422}, {0xC50, 0x69553420}, 205 | {0xffff, 0xffffffff} 206 | }; 207 | 208 | static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { 209 | {0x00, 0x00030000}, {0x08, 0x00008400}, 210 | {0x18, 0x00000407}, {0x19, 0x00000012}, 211 | {0x1B, 0x00001C6C}, 212 | {0x1E, 0x00080009}, {0x1F, 0x00000880}, 213 | {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 214 | {0x42, 0x000060C0}, {0x57, 0x000D0000}, 215 | {0x58, 0x000C0160}, {0x67, 0x00001552}, 216 | {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 217 | {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 218 | {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 219 | {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 220 | {0xB8, 0x00010200}, {0xB9, 0x00080001}, 221 | {0xBA, 0x00040001}, {0xBB, 0x00000400}, 222 | {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 223 | {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 224 | {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 225 | {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 226 | {0xC9, 0x00000000}, {0xCA, 0x00080000}, 227 | {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 228 | {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, 229 | {0x53, 0x00000103}, {0x56, 0x000517F0}, 230 | {0x35, 0x00000099}, {0x35, 0x00000199}, 231 | {0x35, 0x00000299}, {0x36, 0x00000064}, 232 | {0x36, 0x00008064}, {0x36, 0x00010064}, 233 | {0x36, 0x00018064}, {0x18, 0x00000C07}, 234 | {0x5A, 0x00048000}, {0x19, 0x000739D0}, 235 | {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, 236 | {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, 237 | {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, 238 | {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, 239 | {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, 240 | {0x34, 0x00000C48}, 241 | {0x00, 0x00030159}, {0x84, 0x00048000}, 242 | {0x86, 0x0000002A}, {0x87, 0x00000025}, 243 | {0x8E, 0x00065540}, {0x8F, 0x00088000}, 244 | {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 245 | {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 246 | {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 247 | {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 248 | {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 249 | {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 250 | {0x3B, 0x00040700}, {0x3B, 0x00030600}, 251 | {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 252 | {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 253 | {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 254 | {0x3B, 0x00010400}, {0xEF, 0x00000000}, 255 | {0xEF, 0x00080000}, {0x30, 0x00010000}, 256 | {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 257 | {0xEF, 0x00000000}, {0x00, 0x00010159}, 258 | {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 259 | {0xFE, 0x00000000}, {0x1F, 0x00080003}, 260 | {0xFE, 0x00000000}, {0xFE, 0x00000000}, 261 | {0x1E, 0x00000001}, {0x1F, 0x00080000}, 262 | {0x00, 0x00033D95}, 263 | {0xff, 0xffffffff} 264 | }; 265 | 266 | static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { 267 | {0x00, 0x00030000}, {0x08, 0x00008400}, 268 | {0x18, 0x00000407}, {0x19, 0x00000012}, 269 | {0x1B, 0x00001C6C}, 270 | {0x1E, 0x00080009}, {0x1F, 0x00000880}, 271 | {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 272 | {0x42, 0x000060C0}, {0x57, 0x000D0000}, 273 | {0x58, 0x000C0160}, {0x67, 0x00001552}, 274 | {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 275 | {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 276 | {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 277 | {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 278 | {0xB8, 0x00010200}, {0xB9, 0x00080001}, 279 | {0xBA, 0x00040001}, {0xBB, 0x00000400}, 280 | {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 281 | {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 282 | {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 283 | {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 284 | {0xC9, 0x00000000}, {0xCA, 0x00080000}, 285 | {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 286 | {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, 287 | {0x53, 0x00000141}, {0x56, 0x000517F0}, 288 | {0x35, 0x00000090}, {0x35, 0x00000190}, 289 | {0x35, 0x00000290}, {0x36, 0x00001064}, 290 | {0x36, 0x00009064}, {0x36, 0x00011064}, 291 | {0x36, 0x00019064}, {0x18, 0x00000C07}, 292 | {0x5A, 0x00048000}, {0x19, 0x000739D0}, 293 | {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, 294 | {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, 295 | {0x34, 0x00006CED}, {0x34, 0x00005CD2}, 296 | {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, 297 | {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, 298 | {0x34, 0x00000C49}, 299 | {0x00, 0x00030159}, {0x84, 0x00048000}, 300 | {0x86, 0x0000002A}, {0x87, 0x00000025}, 301 | {0x8E, 0x00065540}, {0x8F, 0x00088000}, 302 | {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 303 | {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 304 | {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 305 | {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 306 | {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 307 | {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 308 | {0x3B, 0x00040700}, {0x3B, 0x00030600}, 309 | {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 310 | {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 311 | {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 312 | {0x3B, 0x00010400}, {0xEF, 0x00000000}, 313 | {0xEF, 0x00080000}, {0x30, 0x00010000}, 314 | {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 315 | {0xEF, 0x00000000}, {0x00, 0x00010159}, 316 | {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 317 | {0xFE, 0x00000000}, {0x1F, 0x00080003}, 318 | {0xFE, 0x00000000}, {0xFE, 0x00000000}, 319 | {0x1E, 0x00000001}, {0x1F, 0x00080000}, 320 | {0x00, 0x00033D95}, 321 | {0xff, 0xffffffff} 322 | }; 323 | 324 | static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv) 325 | { 326 | struct device *dev = &priv->udev->dev; 327 | u32 sys_cfg, vendor; 328 | int ret = 0; 329 | 330 | strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); 331 | priv->rtl_chip = RTL8188F; 332 | priv->rf_paths = 1; 333 | priv->rx_paths = 1; 334 | priv->tx_paths = 1; 335 | priv->has_wifi = 1; 336 | 337 | sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 338 | priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 339 | if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 340 | dev_info(dev, "Unsupported test chip\n"); 341 | ret = -ENOTSUPP; 342 | goto out; 343 | } 344 | 345 | vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; 346 | rtl8xxxu_identify_vendor_2bits(priv, vendor); 347 | 348 | ret = rtl8xxxu_config_endpoints_no_sie(priv); 349 | 350 | out: 351 | return ret; 352 | } 353 | 354 | static void rtl8188f_channel_to_group(int channel, int *group, int *cck_group) 355 | { 356 | if (channel < 3) 357 | *group = 0; 358 | else if (channel < 6) 359 | *group = 1; 360 | else if (channel < 9) 361 | *group = 2; 362 | else if (channel < 12) 363 | *group = 3; 364 | else 365 | *group = 4; 366 | 367 | if (channel == 14) 368 | *cck_group = 5; 369 | else 370 | *cck_group = *group; 371 | } 372 | 373 | void 374 | rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 375 | { 376 | u32 val32, ofdm, mcs; 377 | u8 cck, ofdmbase, mcsbase; 378 | int group, cck_group; 379 | 380 | rtl8188f_channel_to_group(channel, &group, &cck_group); 381 | 382 | cck = priv->cck_tx_power_index_A[cck_group]; 383 | 384 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 385 | val32 &= 0xffff00ff; 386 | val32 |= (cck << 8); 387 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 388 | 389 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 390 | val32 &= 0xff; 391 | val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 392 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 393 | 394 | ofdmbase = priv->ht40_1s_tx_power_index_A[group]; 395 | ofdmbase += priv->ofdm_tx_power_diff[0].a; 396 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 397 | 398 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 399 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 400 | 401 | mcsbase = priv->ht40_1s_tx_power_index_A[group]; 402 | if (ht40) 403 | /* This diff is always 0 - not used in 8188FU. */ 404 | mcsbase += priv->ht40_tx_power_diff[0].a; 405 | else 406 | mcsbase += priv->ht20_tx_power_diff[0].a; 407 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 408 | 409 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 410 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 411 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); 412 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); 413 | } 414 | 415 | /* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ 416 | static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) 417 | { 418 | static const u32 frequencies[14 + 1] = { 419 | [5] = 0xFCCD, 420 | [6] = 0xFC4D, 421 | [7] = 0xFFCD, 422 | [8] = 0xFF4D, 423 | [11] = 0xFDCD, 424 | [13] = 0xFCCD, 425 | [14] = 0xFF9A 426 | }; 427 | 428 | static const u32 reg_d40[14 + 1] = { 429 | [5] = 0x06000000, 430 | [6] = 0x00000600, 431 | [13] = 0x06000000 432 | }; 433 | 434 | static const u32 reg_d44[14 + 1] = { 435 | [11] = 0x04000000 436 | }; 437 | 438 | static const u32 reg_d4c[14 + 1] = { 439 | [7] = 0x06000000, 440 | [8] = 0x00000380, 441 | [14] = 0x00180000 442 | }; 443 | 444 | const u8 threshold = 0x16; 445 | bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = 0, sw_ctrl_s1 = 0; 446 | u32 val32, initial_gain, reg948; 447 | 448 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 449 | val32 |= GENMASK(28, 24); 450 | rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 451 | 452 | /* enable notch filter */ 453 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 454 | val32 |= BIT(9); 455 | rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 456 | 457 | if (channel <= 14 && frequencies[channel] > 0) { 458 | reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 459 | hw_ctrl = reg948 & BIT(6); 460 | sw_ctrl = !hw_ctrl; 461 | 462 | if (hw_ctrl) { 463 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 464 | val32 &= GENMASK(5, 3); 465 | hw_ctrl_s1 = val32 == BIT(3); 466 | } else if (sw_ctrl) { 467 | sw_ctrl_s1 = !(reg948 & BIT(9)); 468 | } 469 | 470 | if (hw_ctrl_s1 || sw_ctrl_s1) { 471 | initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 472 | 473 | /* Disable CCK block */ 474 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 475 | val32 &= ~FPGA_RF_MODE_CCK; 476 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 477 | 478 | val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; 479 | val32 |= 0x30; 480 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 481 | 482 | /* disable 3-wire */ 483 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 484 | 485 | /* Setup PSD */ 486 | rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 487 | 488 | /* Start PSD */ 489 | rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); 490 | 491 | msleep(30); 492 | 493 | do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; 494 | 495 | /* turn off PSD */ 496 | rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 497 | 498 | /* enable 3-wire */ 499 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); 500 | 501 | /* Enable CCK block */ 502 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 503 | val32 |= FPGA_RF_MODE_CCK; 504 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 505 | 506 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); 507 | 508 | if (do_notch) { 509 | rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); 510 | rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); 511 | rtl8xxxu_write32(priv, 0xd48, 0x0); 512 | rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); 513 | 514 | /* enable CSI mask */ 515 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 516 | val32 |= BIT(28); 517 | rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 518 | 519 | return; 520 | } 521 | } 522 | } 523 | 524 | /* disable CSI mask function */ 525 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 526 | val32 &= ~BIT(28); 527 | rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 528 | } 529 | 530 | static void rtl8188fu_config_channel(struct ieee80211_hw *hw) 531 | { 532 | struct rtl8xxxu_priv *priv = hw->priv; 533 | u32 val32; 534 | u8 channel, subchannel; 535 | bool sec_ch_above; 536 | 537 | channel = (u8)hw->conf.chandef.chan->hw_value; 538 | 539 | /* Set channel */ 540 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 541 | val32 &= ~MODE_AG_CHANNEL_MASK; 542 | val32 |= channel; 543 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 544 | 545 | /* Spur calibration */ 546 | rtl8188f_spur_calibration(priv, channel); 547 | 548 | /* Set bandwidth mode */ 549 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 550 | val32 &= ~FPGA_RF_MODE; 551 | val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 552 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 553 | 554 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 555 | val32 &= ~FPGA_RF_MODE; 556 | val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 557 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 558 | 559 | /* RXADC CLK */ 560 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 561 | val32 |= GENMASK(10, 8); 562 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 563 | 564 | /* TXDAC CLK */ 565 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 566 | val32 |= BIT(14) | BIT(12); 567 | val32 &= ~BIT(13); 568 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 569 | 570 | /* small BW */ 571 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 572 | val32 &= ~GENMASK(31, 30); 573 | rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 574 | 575 | /* adc buffer clk */ 576 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 577 | val32 &= ~BIT(29); 578 | val32 |= BIT(28); 579 | rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 580 | 581 | /* adc buffer clk */ 582 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); 583 | val32 &= ~BIT(29); 584 | val32 |= BIT(28); 585 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); 586 | 587 | val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 588 | val32 &= ~BIT(19); 589 | rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 590 | 591 | val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 592 | val32 &= ~GENMASK(23, 20); 593 | val32 |= BIT(21); 594 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 595 | hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 596 | val32 |= BIT(20); 597 | else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 598 | val32 |= BIT(22); 599 | rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 600 | 601 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { 602 | if (hw->conf.chandef.center_freq1 > 603 | hw->conf.chandef.chan->center_freq) { 604 | sec_ch_above = 1; 605 | channel += 2; 606 | } else { 607 | sec_ch_above = 0; 608 | channel -= 2; 609 | } 610 | 611 | /* Set Control channel to upper or lower. */ 612 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 613 | val32 &= ~CCK0_SIDEBAND; 614 | if (!sec_ch_above) 615 | val32 |= CCK0_SIDEBAND; 616 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 617 | 618 | val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); 619 | val32 &= ~GENMASK(3, 0); 620 | if (sec_ch_above) 621 | subchannel = 2; 622 | else 623 | subchannel = 1; 624 | val32 |= subchannel; 625 | rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); 626 | 627 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 628 | val32 &= ~RSR_RSC_BANDWIDTH_40M; 629 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 630 | } 631 | 632 | /* RF TRX_BW */ 633 | val32 = channel; 634 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 635 | hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 636 | val32 |= MODE_AG_BW_20MHZ_8723B; 637 | else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 638 | val32 |= MODE_AG_BW_40MHZ_8723B; 639 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 640 | 641 | /* FILTER BW&RC Corner (ACPR) */ 642 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 643 | hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 644 | val32 = 0x00065; 645 | else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 646 | val32 = 0x00025; 647 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); 648 | 649 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 650 | hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 651 | val32 = 0x0; 652 | else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 653 | val32 = 0x01000; 654 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); 655 | 656 | /* RC Corner */ 657 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00140); 658 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); 659 | } 660 | 661 | static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) 662 | { 663 | u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; 664 | u32 agg_rx, val32; 665 | 666 | /* TX aggregation */ 667 | val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); 668 | val32 &= ~(0xf << 4); 669 | val32 |= usb_tx_agg_desc_num << 4; 670 | rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); 671 | rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); 672 | 673 | /* RX aggregation */ 674 | agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 675 | agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 676 | 677 | agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 678 | agg_rx &= ~RXDMA_USB_AGG_ENABLE; 679 | agg_rx &= ~0xFF0F; /* reset agg size and timeout */ 680 | 681 | rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 682 | rxdma_mode &= ~BIT(1); 683 | 684 | rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 685 | rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 686 | rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); 687 | } 688 | 689 | static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) 690 | { 691 | u32 val32; 692 | 693 | /* Time duration for NHM unit: 4us, 0xc350=200ms */ 694 | rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); 695 | rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); 696 | rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); 697 | rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); 698 | 699 | /* TH8 */ 700 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 701 | val32 |= 0xff; 702 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 703 | 704 | /* Enable CCK */ 705 | val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); 706 | val32 &= ~(BIT(8) | BIT(9) | BIT(10)); 707 | val32 |= BIT(8); 708 | rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); 709 | 710 | /* Max power amongst all RX antennas */ 711 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); 712 | val32 |= BIT(7); 713 | rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); 714 | } 715 | 716 | static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) 717 | { 718 | struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; 719 | 720 | if (efuse->rtl_id != cpu_to_le16(0x8129)) 721 | return -EINVAL; 722 | 723 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); 724 | 725 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 726 | sizeof(efuse->tx_power_index_A.cck_base)); 727 | 728 | memcpy(priv->ht40_1s_tx_power_index_A, 729 | efuse->tx_power_index_A.ht40_base, 730 | sizeof(efuse->tx_power_index_A.ht40_base)); 731 | 732 | priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; 733 | priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 734 | 735 | priv->default_crystal_cap = efuse->xtal_k & 0x3f; 736 | 737 | return 0; 738 | } 739 | 740 | static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) 741 | { 742 | const char *fw_name; 743 | int ret; 744 | 745 | fw_name = "rtlwifi/rtl8188fufw.bin"; 746 | 747 | ret = rtl8xxxu_load_firmware(priv, fw_name); 748 | 749 | return ret; 750 | } 751 | 752 | static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) 753 | { 754 | u8 val8; 755 | u16 val16; 756 | 757 | /* Enable BB and RF */ 758 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 759 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 760 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 761 | 762 | /* 763 | * Per vendor driver, run power sequence before init of RF 764 | */ 765 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 766 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 767 | 768 | usleep_range(10, 20); 769 | 770 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); 771 | 772 | val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; 773 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 774 | 775 | rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); 776 | rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); 777 | } 778 | 779 | static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) 780 | { 781 | int ret; 782 | 783 | if (priv->chip_cut == 1) 784 | ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); 785 | else 786 | ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); 787 | 788 | return ret; 789 | } 790 | 791 | void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 792 | { 793 | u32 val32; 794 | u32 rf_amode, lstf; 795 | int i; 796 | 797 | /* Check continuous TX and Packet TX */ 798 | lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 799 | 800 | if (lstf & OFDM_LSTF_MASK) { 801 | /* Disable all continuous TX */ 802 | val32 = lstf & ~OFDM_LSTF_MASK; 803 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 804 | } else { 805 | /* Deal with Packet TX case */ 806 | /* block all queues */ 807 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 808 | } 809 | 810 | /* Read original RF mode Path A */ 811 | rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 812 | 813 | /* Start LC calibration */ 814 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); 815 | 816 | for (i = 0; i < 100; i++) { 817 | if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) 818 | break; 819 | msleep(10); 820 | } 821 | 822 | if (i == 100) 823 | dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); 824 | 825 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); 826 | 827 | /* Restore original parameters */ 828 | if (lstf & OFDM_LSTF_MASK) 829 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 830 | else /* Deal with Packet TX case */ 831 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 832 | } 833 | 834 | static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) 835 | { 836 | u32 reg_eac, reg_e94, reg_e9c, val32; 837 | int result = 0; 838 | 839 | /* 840 | * Leave IQK mode 841 | */ 842 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 843 | val32 &= 0x000000ff; 844 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 845 | 846 | /* 847 | * Enable path A PA in TX IQK mode 848 | */ 849 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 850 | val32 |= 0x80000; 851 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 852 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); 853 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 854 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); 855 | 856 | /* PA,PAD gain adjust */ 857 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); 858 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a); 859 | 860 | /* enter IQK mode */ 861 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 862 | val32 &= 0x000000ff; 863 | val32 |= 0x80800000; 864 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 865 | 866 | /* path-A IQK setting */ 867 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 868 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 869 | 870 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); 871 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 872 | 873 | /* LO calibration setting */ 874 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 875 | 876 | /* One shot, path A LOK & IQK */ 877 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 878 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 879 | 880 | mdelay(25); 881 | 882 | /* 883 | * Leave IQK mode 884 | */ 885 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 886 | val32 &= 0x000000ff; 887 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 888 | 889 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 890 | 891 | /* save LOK result */ 892 | *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); 893 | 894 | /* Check failed */ 895 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 896 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 897 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 898 | 899 | if (!(reg_eac & BIT(28)) && 900 | ((reg_e94 & 0x03ff0000) != 0x01420000) && 901 | ((reg_e9c & 0x03ff0000) != 0x00420000)) 902 | result |= 0x01; 903 | 904 | return result; 905 | } 906 | 907 | static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) 908 | { 909 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 910 | int result = 0; 911 | 912 | /* 913 | * Leave IQK mode 914 | */ 915 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 916 | val32 &= 0x000000ff; 917 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 918 | 919 | /* 920 | * Enable path A PA in TX IQK mode 921 | */ 922 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 923 | val32 |= 0x80000; 924 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 925 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 926 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 927 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); 928 | 929 | /* PA,PAD gain adjust */ 930 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); 931 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a); 932 | 933 | /* 934 | * Enter IQK mode 935 | */ 936 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 937 | val32 &= 0x000000ff; 938 | val32 |= 0x80800000; 939 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 940 | 941 | /* 942 | * Tx IQK setting 943 | */ 944 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 945 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 946 | 947 | /* path-A IQK setting */ 948 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); 949 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); 950 | 951 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); 952 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 953 | 954 | /* LO calibration setting */ 955 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 956 | 957 | /* One shot, path A LOK & IQK */ 958 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 959 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 960 | 961 | mdelay(25); 962 | 963 | /* 964 | * Leave IQK mode 965 | */ 966 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 967 | val32 &= 0x000000ff; 968 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 969 | 970 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 971 | 972 | /* Check failed */ 973 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 974 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 975 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 976 | 977 | if (!(reg_eac & BIT(28)) && 978 | ((reg_e94 & 0x03ff0000) != 0x01420000) && 979 | ((reg_e9c & 0x03ff0000) != 0x00420000)) 980 | result |= 0x01; 981 | else /* If TX not OK, ignore RX */ 982 | goto out; 983 | 984 | val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | 985 | ((reg_e9c & 0x3ff0000) >> 16); 986 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); 987 | 988 | /* 989 | * Modify RX IQK mode table 990 | */ 991 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 992 | val32 &= 0x000000ff; 993 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 994 | 995 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 996 | val32 |= 0x80000; 997 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 998 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 999 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 1000 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); 1001 | 1002 | /* 1003 | * PA, PAD setting 1004 | */ 1005 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); 1006 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); 1007 | 1008 | /* 1009 | * Enter IQK mode 1010 | */ 1011 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1012 | val32 &= 0x000000ff; 1013 | val32 |= 0x80800000; 1014 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1015 | 1016 | /* 1017 | * RX IQK setting 1018 | */ 1019 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1020 | 1021 | /* path-A IQK setting */ 1022 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); 1023 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); 1024 | 1025 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); 1026 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); 1027 | 1028 | /* LO calibration setting */ 1029 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 1030 | 1031 | /* One shot, path A LOK & IQK */ 1032 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 1033 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 1034 | 1035 | mdelay(25); 1036 | 1037 | /* 1038 | * Leave IQK mode 1039 | */ 1040 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1041 | val32 &= 0x000000ff; 1042 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1043 | 1044 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 1045 | 1046 | /* reload LOK value */ 1047 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); 1048 | 1049 | /* Check failed */ 1050 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1051 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 1052 | 1053 | if (!(reg_eac & BIT(27)) && 1054 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && 1055 | ((reg_eac & 0x03ff0000) != 0x00360000)) 1056 | result |= 0x02; 1057 | 1058 | out: 1059 | return result; 1060 | } 1061 | 1062 | static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 1063 | int result[][8], int t) 1064 | { 1065 | struct device *dev = &priv->udev->dev; 1066 | u32 i, val32, rx_initial_gain, lok_result; 1067 | u32 path_sel_bb, path_sel_rf; 1068 | int path_a_ok; 1069 | int retry = 2; 1070 | static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 1071 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 1072 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 1073 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 1074 | REG_TX_OFDM_BBON, REG_TX_TO_RX, 1075 | REG_TX_TO_TX, REG_RX_CCK, 1076 | REG_RX_OFDM, REG_RX_WAIT_RIFS, 1077 | REG_RX_TO_RX, REG_STANDBY, 1078 | REG_SLEEP, REG_PMPD_ANAEN 1079 | }; 1080 | static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 1081 | REG_TXPAUSE, REG_BEACON_CTRL, 1082 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 1083 | }; 1084 | static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 1085 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 1086 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 1087 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 1088 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 1089 | }; 1090 | 1091 | /* 1092 | * Note: IQ calibration must be performed after loading 1093 | * PHY_REG.txt , and radio_a, radio_b.txt 1094 | */ 1095 | 1096 | rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1097 | 1098 | if (t == 0) { 1099 | /* Save ADDA parameters, turn Path A ADDA on */ 1100 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 1101 | RTL8XXXU_ADDA_REGS); 1102 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1103 | rtl8xxxu_save_regs(priv, iqk_bb_regs, 1104 | priv->bb_backup, RTL8XXXU_BB_REGS); 1105 | } 1106 | 1107 | rtl8xxxu_path_adda_on(priv, adda_regs, true); 1108 | 1109 | if (t == 0) { 1110 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 1111 | priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); 1112 | } 1113 | 1114 | /* save RF path */ 1115 | path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1116 | path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1117 | 1118 | /* BB setting */ 1119 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 1120 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 1121 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); 1122 | 1123 | /* MAC settings */ 1124 | val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); 1125 | val32 |= 0x00ff0000; 1126 | rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); 1127 | 1128 | /* IQ calibration setting */ 1129 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1130 | val32 &= 0xff; 1131 | val32 |= 0x80800000; 1132 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1133 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1134 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1135 | 1136 | for (i = 0; i < retry; i++) { 1137 | path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); 1138 | if (path_a_ok == 0x01) { 1139 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1140 | val32 &= 0xff; 1141 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1142 | 1143 | val32 = rtl8xxxu_read32(priv, 1144 | REG_TX_POWER_BEFORE_IQK_A); 1145 | result[t][0] = (val32 >> 16) & 0x3ff; 1146 | 1147 | val32 = rtl8xxxu_read32(priv, 1148 | REG_TX_POWER_AFTER_IQK_A); 1149 | result[t][1] = (val32 >> 16) & 0x3ff; 1150 | break; 1151 | } 1152 | } 1153 | 1154 | for (i = 0; i < retry; i++) { 1155 | path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); 1156 | if (path_a_ok == 0x03) { 1157 | val32 = rtl8xxxu_read32(priv, 1158 | REG_RX_POWER_BEFORE_IQK_A_2); 1159 | result[t][2] = (val32 >> 16) & 0x3ff; 1160 | 1161 | val32 = rtl8xxxu_read32(priv, 1162 | REG_RX_POWER_AFTER_IQK_A_2); 1163 | result[t][3] = (val32 >> 16) & 0x3ff; 1164 | break; 1165 | } 1166 | } 1167 | 1168 | if (!path_a_ok) 1169 | dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 1170 | 1171 | /* Back to BB mode, load original value */ 1172 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1173 | val32 &= 0xff; 1174 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1175 | 1176 | if (t == 0) 1177 | return; 1178 | 1179 | if (!priv->pi_enabled) { 1180 | /* 1181 | * Switch back BB to SI mode after finishing 1182 | * IQ Calibration 1183 | */ 1184 | val32 = 0x01000000; 1185 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 1186 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 1187 | } 1188 | 1189 | /* Reload ADDA power saving parameters */ 1190 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1191 | RTL8XXXU_ADDA_REGS); 1192 | 1193 | /* Reload MAC parameters */ 1194 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1195 | 1196 | /* Reload BB parameters */ 1197 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1198 | priv->bb_backup, RTL8XXXU_BB_REGS); 1199 | 1200 | /* Reload RF path */ 1201 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1202 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1203 | 1204 | /* Restore RX initial gain */ 1205 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1206 | val32 &= 0xffffff00; 1207 | val32 |= 0x50; 1208 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1209 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1210 | val32 &= 0xffffff00; 1211 | val32 |= rx_initial_gain & 0xff; 1212 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1213 | 1214 | /* Load 0xe30 IQC default value */ 1215 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1216 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1217 | } 1218 | 1219 | static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1220 | { 1221 | struct device *dev = &priv->udev->dev; 1222 | int result[4][8]; /* last is final result */ 1223 | int i, candidate; 1224 | bool path_a_ok; 1225 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1226 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1227 | s32 reg_tmp = 0; 1228 | bool simu; 1229 | u32 path_sel_bb, path_sel_rf; 1230 | 1231 | /* Save RF path */ 1232 | path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1233 | path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1234 | 1235 | memset(result, 0, sizeof(result)); 1236 | candidate = -1; 1237 | 1238 | path_a_ok = false; 1239 | 1240 | for (i = 0; i < 3; i++) { 1241 | rtl8188fu_phy_iqcalibrate(priv, result, i); 1242 | 1243 | if (i == 1) { 1244 | simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); 1245 | if (simu) { 1246 | candidate = 0; 1247 | break; 1248 | } 1249 | } 1250 | 1251 | if (i == 2) { 1252 | simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); 1253 | if (simu) { 1254 | candidate = 0; 1255 | break; 1256 | } 1257 | 1258 | simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); 1259 | if (simu) { 1260 | candidate = 1; 1261 | } else { 1262 | for (i = 0; i < 8; i++) 1263 | reg_tmp += result[3][i]; 1264 | 1265 | if (reg_tmp) 1266 | candidate = 3; 1267 | else 1268 | candidate = -1; 1269 | } 1270 | } 1271 | } 1272 | 1273 | for (i = 0; i < 4; i++) { 1274 | reg_e94 = result[i][0]; 1275 | reg_e9c = result[i][1]; 1276 | reg_ea4 = result[i][2]; 1277 | reg_eac = result[i][3]; 1278 | reg_eb4 = result[i][4]; 1279 | reg_ebc = result[i][5]; 1280 | reg_ec4 = result[i][6]; 1281 | reg_ecc = result[i][7]; 1282 | } 1283 | 1284 | if (candidate >= 0) { 1285 | reg_e94 = result[candidate][0]; 1286 | priv->rege94 = reg_e94; 1287 | reg_e9c = result[candidate][1]; 1288 | priv->rege9c = reg_e9c; 1289 | reg_ea4 = result[candidate][2]; 1290 | reg_eac = result[candidate][3]; 1291 | reg_eb4 = result[candidate][4]; 1292 | priv->regeb4 = reg_eb4; 1293 | reg_ebc = result[candidate][5]; 1294 | priv->regebc = reg_ebc; 1295 | reg_ec4 = result[candidate][6]; 1296 | reg_ecc = result[candidate][7]; 1297 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1298 | dev_dbg(dev, 1299 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1300 | __func__, reg_e94, reg_e9c, 1301 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1302 | path_a_ok = true; 1303 | } else { 1304 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1305 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1306 | } 1307 | 1308 | if (reg_e94 && candidate >= 0) 1309 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1310 | candidate, (reg_ea4 == 0)); 1311 | 1312 | rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1313 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1314 | 1315 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1316 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1317 | } 1318 | 1319 | static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) 1320 | { 1321 | u16 val8; 1322 | 1323 | /* 0x04[12:11] = 2b'01enable WL suspend */ 1324 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1325 | val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1326 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1327 | 1328 | /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1329 | val8 = rtl8xxxu_read8(priv, 0xc4); 1330 | val8 &= ~BIT(4); 1331 | rtl8xxxu_write8(priv, 0xc4, val8); 1332 | } 1333 | 1334 | static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) 1335 | { 1336 | u8 val8; 1337 | u32 val32; 1338 | int count, ret = 0; 1339 | 1340 | /* Disable SW LPS */ 1341 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1342 | val8 &= ~(APS_FSMCO_SW_LPS >> 8); 1343 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1344 | 1345 | /* wait till 0x04[17] = 1 power ready */ 1346 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1347 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1348 | if (val32 & BIT(17)) 1349 | break; 1350 | 1351 | udelay(10); 1352 | } 1353 | 1354 | if (!count) { 1355 | ret = -EBUSY; 1356 | goto exit; 1357 | } 1358 | 1359 | /* Disable HWPDN */ 1360 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1361 | val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); 1362 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1363 | 1364 | /* Disable WL suspend */ 1365 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1366 | val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); 1367 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1368 | 1369 | /* set, then poll until 0 */ 1370 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1371 | val8 |= APS_FSMCO_MAC_ENABLE >> 8; 1372 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1373 | 1374 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1375 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1376 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1377 | ret = 0; 1378 | break; 1379 | } 1380 | udelay(10); 1381 | } 1382 | 1383 | if (!count) { 1384 | ret = -EBUSY; 1385 | goto exit; 1386 | } 1387 | 1388 | /* 0x27<=35 to reduce RF noise */ 1389 | val8 = rtl8xxxu_write8(priv, 0x27, 0x35); 1390 | exit: 1391 | return ret; 1392 | } 1393 | 1394 | static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) 1395 | { 1396 | u8 val8; 1397 | u32 val32; 1398 | int count, ret = 0; 1399 | 1400 | /* Turn off RF */ 1401 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1402 | 1403 | /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ 1404 | val8 = rtl8xxxu_read8(priv, 0x4e); 1405 | val8 &= ~BIT(7); 1406 | rtl8xxxu_write8(priv, 0x4e, val8); 1407 | 1408 | /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ 1409 | rtl8xxxu_write8(priv, 0x27, 0x34); 1410 | 1411 | /* 0x04[9] = 1 turn off MAC by HW state machine */ 1412 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1413 | val8 |= APS_FSMCO_MAC_OFF >> 8; 1414 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1415 | 1416 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1417 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1418 | if ((val32 & APS_FSMCO_MAC_OFF) == 0) { 1419 | ret = 0; 1420 | break; 1421 | } 1422 | udelay(10); 1423 | } 1424 | 1425 | if (!count) { 1426 | ret = -EBUSY; 1427 | goto exit; 1428 | } 1429 | 1430 | exit: 1431 | return ret; 1432 | } 1433 | 1434 | static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1435 | { 1436 | u8 val8; 1437 | 1438 | /* 0x04[12:11] = 2b'01 enable WL suspend */ 1439 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1440 | val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1441 | val8 |= APS_FSMCO_HW_SUSPEND >> 8; 1442 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1443 | 1444 | /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1445 | val8 = rtl8xxxu_read8(priv, 0xc4); 1446 | val8 |= BIT(4); 1447 | rtl8xxxu_write8(priv, 0xc4, val8); 1448 | 1449 | return 0; 1450 | } 1451 | 1452 | static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) 1453 | { 1454 | struct device *dev = &priv->udev->dev; 1455 | u8 val8; 1456 | u16 val16; 1457 | u32 val32; 1458 | int retry, retval; 1459 | 1460 | /* set RPWM IMR */ 1461 | val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); 1462 | val8 |= IMR0_CPWM >> 8; 1463 | rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); 1464 | 1465 | /* Tx Pause */ 1466 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1467 | 1468 | retry = 100; 1469 | retval = -EBUSY; 1470 | 1471 | /* 1472 | * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. 1473 | */ 1474 | do { 1475 | val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1476 | if (!val32) { 1477 | retval = 0; 1478 | break; 1479 | } 1480 | } while (retry--); 1481 | 1482 | if (!retry) { 1483 | dev_warn(dev, "Failed to flush TX queue\n"); 1484 | retval = -EBUSY; 1485 | goto out; 1486 | } 1487 | 1488 | /* Disable CCK and OFDM, clock gated */ 1489 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1490 | val8 &= ~SYS_FUNC_BBRSTB; 1491 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1492 | 1493 | udelay(2); 1494 | 1495 | /* Whole BB is reset */ 1496 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1497 | val8 &= ~SYS_FUNC_BB_GLB_RSTN; 1498 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1499 | 1500 | /* Reset MAC TRX */ 1501 | val16 = rtl8xxxu_read16(priv, REG_CR); 1502 | val16 |= 0x3f; 1503 | val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); 1504 | rtl8xxxu_write16(priv, REG_CR, val16); 1505 | 1506 | /* Respond TxOK to scheduler */ 1507 | val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 1508 | val8 |= DUAL_TSF_TX_OK; 1509 | rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 1510 | 1511 | out: 1512 | return retval; 1513 | } 1514 | 1515 | static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) 1516 | { 1517 | u16 val16; 1518 | int ret; 1519 | 1520 | rtl8188f_disabled_to_emu(priv); 1521 | 1522 | ret = rtl8188f_emu_to_active(priv); 1523 | if (ret) 1524 | goto exit; 1525 | 1526 | rtl8xxxu_write8(priv, REG_CR, 0); 1527 | 1528 | val16 = rtl8xxxu_read16(priv, REG_CR); 1529 | 1530 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1531 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1532 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1533 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1534 | rtl8xxxu_write16(priv, REG_CR, val16); 1535 | 1536 | exit: 1537 | return ret; 1538 | } 1539 | 1540 | static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) 1541 | { 1542 | u8 val8; 1543 | u16 val16; 1544 | 1545 | rtl8xxxu_flush_fifo(priv); 1546 | 1547 | val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); 1548 | val16 &= ~BIT(12); 1549 | rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); 1550 | 1551 | rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); 1552 | rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); 1553 | 1554 | /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ 1555 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1556 | val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1557 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1558 | 1559 | /* Turn off RF */ 1560 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 1561 | 1562 | /* Reset Firmware if running in RAM */ 1563 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1564 | rtl8xxxu_firmware_self_reset(priv); 1565 | 1566 | rtl8188fu_active_to_lps(priv); 1567 | 1568 | /* Reset MCU */ 1569 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1570 | val16 &= ~SYS_FUNC_CPU_ENABLE; 1571 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1572 | 1573 | /* Reset MCU ready status */ 1574 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1575 | 1576 | rtl8188fu_active_to_emu(priv); 1577 | rtl8188fu_emu_to_disabled(priv); 1578 | } 1579 | 1580 | #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee 1581 | #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f 1582 | 1583 | static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) 1584 | { 1585 | u32 val32; 1586 | u8 pg_pwrtrim = 0xff, val8; 1587 | s8 bb_gain; 1588 | 1589 | /* Somehow this is not found in the efuse we read earlier. */ 1590 | rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); 1591 | 1592 | if (pg_pwrtrim != 0xff) { 1593 | bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; 1594 | 1595 | if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) 1596 | bb_gain = 0; 1597 | else if (bb_gain & 1) 1598 | bb_gain = bb_gain >> 1; 1599 | else 1600 | bb_gain = -(bb_gain >> 1); 1601 | 1602 | val8 = abs(bb_gain); 1603 | if (bb_gain > 0) 1604 | val8 |= BIT(5); 1605 | 1606 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); 1607 | val32 &= ~0xfc000; 1608 | val32 |= val8 << 14; 1609 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); 1610 | } 1611 | 1612 | rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 1613 | 1614 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1615 | val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 1616 | val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; 1617 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1618 | 1619 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1620 | } 1621 | 1622 | static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) 1623 | { 1624 | u32 val32; 1625 | 1626 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1627 | val32 &= ~OFDM_RF_PATH_TX_MASK; 1628 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1629 | 1630 | /* Power down RF module */ 1631 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1632 | } 1633 | 1634 | static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) 1635 | { 1636 | u16 val16; 1637 | u32 val32; 1638 | 1639 | val16 = rtl8xxxu_read16(priv, REG_CR); 1640 | val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); 1641 | rtl8xxxu_write16(priv, REG_CR, val16); 1642 | 1643 | val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 1644 | val32 |= TXDMA_OFFSET_DROP_DATA_EN; 1645 | rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 1646 | } 1647 | 1648 | #define XTAL1 GENMASK(22, 17) 1649 | #define XTAL0 GENMASK(16, 11) 1650 | 1651 | void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) 1652 | { 1653 | struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 1654 | u32 val32; 1655 | 1656 | if (crystal_cap == cfo->crystal_cap) 1657 | return; 1658 | 1659 | val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 1660 | 1661 | dev_dbg(&priv->udev->dev, 1662 | "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", 1663 | __func__, 1664 | cfo->crystal_cap, 1665 | FIELD_GET(XTAL1, val32), 1666 | FIELD_GET(XTAL0, val32), 1667 | crystal_cap); 1668 | 1669 | val32 &= ~(XTAL1 | XTAL0); 1670 | val32 |= FIELD_PREP(XTAL1, crystal_cap) | 1671 | FIELD_PREP(XTAL0, crystal_cap); 1672 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 1673 | 1674 | cfo->crystal_cap = crystal_cap; 1675 | } 1676 | 1677 | static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) 1678 | { 1679 | u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 1680 | s8 rx_pwr_all = 0x00; 1681 | u8 vga_idx, lna_idx; 1682 | 1683 | lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); 1684 | vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); 1685 | 1686 | switch (lna_idx) { 1687 | case 7: 1688 | if (vga_idx <= 27) 1689 | rx_pwr_all = -100 + 2 * (27 - vga_idx); 1690 | else 1691 | rx_pwr_all = -100; 1692 | break; 1693 | case 5: 1694 | rx_pwr_all = -74 + 2 * (21 - vga_idx); 1695 | break; 1696 | case 3: 1697 | rx_pwr_all = -60 + 2 * (20 - vga_idx); 1698 | break; 1699 | case 1: 1700 | rx_pwr_all = -44 + 2 * (19 - vga_idx); 1701 | break; 1702 | default: 1703 | break; 1704 | } 1705 | 1706 | return rx_pwr_all; 1707 | } 1708 | 1709 | struct rtl8xxxu_fileops rtl8188fu_fops = { 1710 | .identify_chip = rtl8188fu_identify_chip, 1711 | .parse_efuse = rtl8188fu_parse_efuse, 1712 | .load_firmware = rtl8188fu_load_firmware, 1713 | .power_on = rtl8188fu_power_on, 1714 | .power_off = rtl8188fu_power_off, 1715 | .read_efuse = rtl8xxxu_read_efuse, 1716 | .reset_8051 = rtl8xxxu_reset_8051, 1717 | .llt_init = rtl8xxxu_auto_llt_table, 1718 | .init_phy_bb = rtl8188fu_init_phy_bb, 1719 | .init_phy_rf = rtl8188fu_init_phy_rf, 1720 | .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, 1721 | .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, 1722 | .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, 1723 | .config_channel = rtl8188fu_config_channel, 1724 | .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1725 | .parse_phystats = rtl8723au_rx_parse_phystats, 1726 | .init_aggregation = rtl8188fu_init_aggregation, 1727 | .init_statistics = rtl8188fu_init_statistics, 1728 | .init_burst = rtl8xxxu_init_burst, 1729 | .enable_rf = rtl8188f_enable_rf, 1730 | .disable_rf = rtl8188f_disable_rf, 1731 | .usb_quirks = rtl8188f_usb_quirks, 1732 | .set_tx_power = rtl8188f_set_tx_power, 1733 | .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1734 | .report_connect = rtl8xxxu_gen2_report_connect, 1735 | .report_rssi = rtl8xxxu_gen2_report_rssi, 1736 | .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1737 | .set_crystal_cap = rtl8188f_set_crystal_cap, 1738 | .cck_rssi = rtl8188f_cck_rssi, 1739 | .writeN_block_size = 128, 1740 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1741 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1742 | .has_s0s1 = 1, 1743 | .has_tx_report = 1, 1744 | .gen2_thermal_meter = 1, 1745 | .needs_full_init = 1, 1746 | .init_reg_rxfltmap = 1, 1747 | .init_reg_pkt_life_time = 1, 1748 | .init_reg_hmtfr = 1, 1749 | .ampdu_max_time = 0x70, 1750 | .ustime_tsf_edca = 0x28, 1751 | .supports_ap = 1, 1752 | .max_sta_num = 16, 1753 | .adda_1t_init = 0x03c00014, 1754 | .adda_1t_path_on = 0x03c00014, 1755 | .trxff_boundary = 0x3f7f, 1756 | .pbp_rx = PBP_PAGE_SIZE_256, 1757 | .pbp_tx = PBP_PAGE_SIZE_256, 1758 | .mactable = rtl8188f_mac_init_table, 1759 | .total_page_num = TX_TOTAL_PAGE_NUM_8188F, 1760 | .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, 1761 | .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, 1762 | .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, 1763 | }; 1764 | -------------------------------------------------------------------------------- /rtl8xxxu_8192c.c: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0-only 2 | /* 3 | * RTL8XXXU mac80211 USB driver - 8188c/8188r/8192c specific subdriver 4 | * 5 | * Copyright (c) 2014 - 2017 Jes Sorensen 6 | * 7 | * Portions, notably calibration code: 8 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 | * 10 | * This driver was written as a replacement for the vendor provided 11 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 | * their programming interface, I have started adding support for 13 | * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 | */ 15 | 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include "rtl8xxxu.h" 33 | #include "rtl8xxxu_regs.h" 34 | 35 | static struct rtl8xxxu_power_base rtl8192c_power_base = { 36 | .reg_0e00 = 0x07090c0c, 37 | .reg_0e04 = 0x01020405, 38 | .reg_0e08 = 0x00000000, 39 | .reg_086c = 0x00000000, 40 | 41 | .reg_0e10 = 0x0b0c0c0e, 42 | .reg_0e14 = 0x01030506, 43 | .reg_0e18 = 0x0b0c0d0e, 44 | .reg_0e1c = 0x01030509, 45 | 46 | .reg_0830 = 0x07090c0c, 47 | .reg_0834 = 0x01020405, 48 | .reg_0838 = 0x00000000, 49 | .reg_086c_2 = 0x00000000, 50 | 51 | .reg_083c = 0x0b0c0d0e, 52 | .reg_0848 = 0x01030509, 53 | .reg_084c = 0x0b0c0d0e, 54 | .reg_0868 = 0x01030509, 55 | }; 56 | 57 | static struct rtl8xxxu_power_base rtl8188r_power_base = { 58 | .reg_0e00 = 0x06080808, 59 | .reg_0e04 = 0x00040406, 60 | .reg_0e08 = 0x00000000, 61 | .reg_086c = 0x00000000, 62 | 63 | .reg_0e10 = 0x04060608, 64 | .reg_0e14 = 0x00020204, 65 | .reg_0e18 = 0x04060608, 66 | .reg_0e1c = 0x00020204, 67 | 68 | .reg_0830 = 0x06080808, 69 | .reg_0834 = 0x00040406, 70 | .reg_0838 = 0x00000000, 71 | .reg_086c_2 = 0x00000000, 72 | 73 | .reg_083c = 0x04060608, 74 | .reg_0848 = 0x00020204, 75 | .reg_084c = 0x04060608, 76 | .reg_0868 = 0x00020204, 77 | }; 78 | 79 | static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { 80 | {0x00, 0x00030159}, {0x01, 0x00031284}, 81 | {0x02, 0x00098000}, {0x03, 0x00018c63}, 82 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, 83 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, 84 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, 85 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 86 | {0x19, 0x00000000}, {0x1a, 0x00010255}, 87 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 88 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, 89 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, 90 | {0x21, 0x0006c000}, {0x22, 0x00000000}, 91 | {0x23, 0x00001558}, {0x24, 0x00000060}, 92 | {0x25, 0x00000483}, {0x26, 0x0004f000}, 93 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, 94 | {0x29, 0x00004783}, {0x2a, 0x00000001}, 95 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, 96 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, 97 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, 98 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 99 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 100 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 101 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, 102 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 103 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 104 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 105 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, 106 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 107 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 108 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 109 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, 110 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 111 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 112 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 113 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 114 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 115 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 116 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 117 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 118 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 119 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 120 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 121 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 122 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 123 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 124 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 125 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 126 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 127 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, 128 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, 129 | {0x10, 0x00000000}, {0x11, 0x00000000}, 130 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, 131 | {0x10, 0x0009000f}, {0x11, 0x00023100}, 132 | {0x12, 0x00032000}, {0x12, 0x00071000}, 133 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, 134 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, 135 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 136 | {0x13, 0x00018493}, {0x13, 0x0001429b}, 137 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, 138 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, 139 | {0x13, 0x00000020}, {0x14, 0x0001944c}, 140 | {0x14, 0x00059444}, {0x14, 0x0009944c}, 141 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, 142 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, 143 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, 144 | {0x16, 0x000a0330}, {0x16, 0x00060330}, 145 | {0x16, 0x00020330}, {0x00, 0x00010159}, 146 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, 147 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, 148 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, 149 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, 150 | {0x00, 0x00030159}, 151 | {0xff, 0xffffffff} 152 | }; 153 | 154 | static const struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { 155 | {0x00, 0x00030159}, {0x01, 0x00031284}, 156 | {0x02, 0x00098000}, {0x03, 0x00018c63}, 157 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, 158 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, 159 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, 160 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 161 | {0x12, 0x00032000}, {0x12, 0x00071000}, 162 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, 163 | {0x13, 0x000287af}, {0x13, 0x000244b7}, 164 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 165 | {0x13, 0x00018493}, {0x13, 0x00014297}, 166 | {0x13, 0x00010295}, {0x13, 0x0000c298}, 167 | {0x13, 0x0000819c}, {0x13, 0x000040a8}, 168 | {0x13, 0x0000001c}, {0x14, 0x0001944c}, 169 | {0x14, 0x00059444}, {0x14, 0x0009944c}, 170 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, 171 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, 172 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, 173 | {0x16, 0x000a0330}, {0x16, 0x00060330}, 174 | {0x16, 0x00020330}, 175 | {0xff, 0xffffffff} 176 | }; 177 | 178 | static const struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { 179 | {0x00, 0x00030159}, {0x01, 0x00031284}, 180 | {0x02, 0x00098000}, {0x03, 0x00018c63}, 181 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, 182 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, 183 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, 184 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 185 | {0x19, 0x00000000}, {0x1a, 0x00010255}, 186 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 187 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, 188 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, 189 | {0x21, 0x0006c000}, {0x22, 0x00000000}, 190 | {0x23, 0x00001558}, {0x24, 0x00000060}, 191 | {0x25, 0x00000483}, {0x26, 0x0004f000}, 192 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, 193 | {0x29, 0x00004783}, {0x2a, 0x00000001}, 194 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, 195 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, 196 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, 197 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 198 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 199 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 200 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, 201 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 202 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 203 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 204 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, 205 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 206 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 207 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 208 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, 209 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 210 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 211 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 212 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 213 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 214 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 215 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 216 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 217 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 218 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 219 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 220 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 221 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 222 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 223 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 224 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 225 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 226 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, 227 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, 228 | {0x10, 0x00000000}, {0x11, 0x00000000}, 229 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, 230 | {0x10, 0x0009000f}, {0x11, 0x00023100}, 231 | {0x12, 0x00032000}, {0x12, 0x00071000}, 232 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, 233 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, 234 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 235 | {0x13, 0x00018493}, {0x13, 0x0001429b}, 236 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, 237 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, 238 | {0x13, 0x00000020}, {0x14, 0x0001944c}, 239 | {0x14, 0x00059444}, {0x14, 0x0009944c}, 240 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, 241 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, 242 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, 243 | {0x16, 0x000a0330}, {0x16, 0x00060330}, 244 | {0x16, 0x00020330}, {0x00, 0x00010159}, 245 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, 246 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, 247 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, 248 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, 249 | {0x00, 0x00030159}, 250 | {0xff, 0xffffffff} 251 | }; 252 | 253 | static const struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { 254 | {0x00, 0x00030159}, {0x01, 0x00031284}, 255 | {0x02, 0x00098000}, {0x03, 0x00018c63}, 256 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, 257 | {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, 258 | {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, 259 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 260 | {0x19, 0x00000000}, {0x1a, 0x00000255}, 261 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 262 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, 263 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, 264 | {0x21, 0x0006c000}, {0x22, 0x0000083c}, 265 | {0x23, 0x00001558}, {0x24, 0x00000060}, 266 | {0x25, 0x00000483}, {0x26, 0x0004f000}, 267 | {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, 268 | {0x29, 0x00004783}, {0x2a, 0x00000001}, 269 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, 270 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, 271 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, 272 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 273 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 274 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 275 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, 276 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 277 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 278 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 279 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, 280 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 281 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 282 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 283 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, 284 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 285 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 286 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 287 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 288 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 289 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 290 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 291 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 292 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 293 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 294 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 295 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 296 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 297 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 298 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 299 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 300 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 301 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, 302 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, 303 | {0x10, 0x00000000}, {0x11, 0x00000000}, 304 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, 305 | {0x10, 0x0009000f}, {0x11, 0x00023100}, 306 | {0x12, 0x000d8000}, {0x12, 0x00090000}, 307 | {0x12, 0x00051000}, {0x12, 0x00012000}, 308 | {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, 309 | {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, 310 | {0x13, 0x000183a4}, {0x13, 0x00014398}, 311 | {0x13, 0x000101a4}, {0x13, 0x0000c198}, 312 | {0x13, 0x000080a4}, {0x13, 0x00004098}, 313 | {0x13, 0x00000000}, {0x14, 0x0001944c}, 314 | {0x14, 0x00059444}, {0x14, 0x0009944c}, 315 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, 316 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, 317 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, 318 | {0x16, 0x000a0330}, {0x16, 0x00060330}, 319 | {0x16, 0x00020330}, {0x00, 0x00010159}, 320 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, 321 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, 322 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, 323 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, 324 | {0x00, 0x00030159}, 325 | {0xff, 0xffffffff} 326 | }; 327 | 328 | static int rtl8192cu_identify_chip(struct rtl8xxxu_priv *priv) 329 | { 330 | struct device *dev = &priv->udev->dev; 331 | u32 val32, bonding, sys_cfg, vendor; 332 | int ret = 0; 333 | 334 | sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 335 | priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 336 | if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 337 | dev_info(dev, "Unsupported test chip\n"); 338 | ret = -ENOTSUPP; 339 | goto out; 340 | } 341 | 342 | if (sys_cfg & SYS_CFG_TYPE_ID) { 343 | bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); 344 | bonding &= HPON_FSM_BONDING_MASK; 345 | if (bonding == HPON_FSM_BONDING_1T2R) { 346 | strscpy(priv->chip_name, "8191CU", sizeof(priv->chip_name)); 347 | priv->tx_paths = 1; 348 | priv->usb_interrupts = 1; 349 | priv->rtl_chip = RTL8191C; 350 | } else { 351 | strscpy(priv->chip_name, "8192CU", sizeof(priv->chip_name)); 352 | priv->tx_paths = 2; 353 | priv->usb_interrupts = 0; 354 | priv->rtl_chip = RTL8192C; 355 | } 356 | priv->rf_paths = 2; 357 | priv->rx_paths = 2; 358 | } else { 359 | strscpy(priv->chip_name, "8188CU", sizeof(priv->chip_name)); 360 | priv->rf_paths = 1; 361 | priv->rx_paths = 1; 362 | priv->tx_paths = 1; 363 | priv->rtl_chip = RTL8188C; 364 | priv->usb_interrupts = 0; 365 | } 366 | priv->has_wifi = 1; 367 | 368 | vendor = sys_cfg & SYS_CFG_VENDOR_ID; 369 | rtl8xxxu_identify_vendor_1bit(priv, vendor); 370 | 371 | val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 372 | priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 373 | 374 | rtl8xxxu_config_endpoints_sie(priv); 375 | 376 | /* 377 | * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 378 | */ 379 | if (!priv->ep_tx_count) 380 | ret = rtl8xxxu_config_endpoints_no_sie(priv); 381 | 382 | out: 383 | return ret; 384 | } 385 | 386 | static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) 387 | { 388 | const char *fw_name; 389 | int ret; 390 | 391 | if (!priv->vendor_umc) 392 | fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; 393 | else if (priv->chip_cut || priv->rtl_chip == RTL8192C) 394 | fw_name = "rtlwifi/rtl8192cufw_B.bin"; 395 | else 396 | fw_name = "rtlwifi/rtl8192cufw_A.bin"; 397 | 398 | ret = rtl8xxxu_load_firmware(priv, fw_name); 399 | 400 | return ret; 401 | } 402 | 403 | static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) 404 | { 405 | struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192; 406 | 407 | if (efuse->rtl_id != cpu_to_le16(0x8129)) 408 | return -EINVAL; 409 | 410 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); 411 | 412 | memcpy(priv->cck_tx_power_index_A, 413 | efuse->cck_tx_power_index_A, 414 | sizeof(efuse->cck_tx_power_index_A)); 415 | memcpy(priv->cck_tx_power_index_B, 416 | efuse->cck_tx_power_index_B, 417 | sizeof(efuse->cck_tx_power_index_B)); 418 | 419 | memcpy(priv->ht40_1s_tx_power_index_A, 420 | efuse->ht40_1s_tx_power_index_A, 421 | sizeof(efuse->ht40_1s_tx_power_index_A)); 422 | memcpy(priv->ht40_1s_tx_power_index_B, 423 | efuse->ht40_1s_tx_power_index_B, 424 | sizeof(efuse->ht40_1s_tx_power_index_B)); 425 | memcpy(priv->ht40_2s_tx_power_index_diff, 426 | efuse->ht40_2s_tx_power_index_diff, 427 | sizeof(efuse->ht40_2s_tx_power_index_diff)); 428 | 429 | memcpy(priv->ht20_tx_power_index_diff, 430 | efuse->ht20_tx_power_index_diff, 431 | sizeof(efuse->ht20_tx_power_index_diff)); 432 | memcpy(priv->ofdm_tx_power_index_diff, 433 | efuse->ofdm_tx_power_index_diff, 434 | sizeof(efuse->ofdm_tx_power_index_diff)); 435 | 436 | memcpy(priv->ht40_max_power_offset, 437 | efuse->ht40_max_power_offset, 438 | sizeof(efuse->ht40_max_power_offset)); 439 | memcpy(priv->ht20_max_power_offset, 440 | efuse->ht20_max_power_offset, 441 | sizeof(efuse->ht20_max_power_offset)); 442 | 443 | priv->power_base = &rtl8192c_power_base; 444 | 445 | if (efuse->rf_regulatory & 0x20) { 446 | strscpy(priv->chip_name, "8188RU", sizeof(priv->chip_name)); 447 | priv->rtl_chip = RTL8188R; 448 | priv->hi_pa = 1; 449 | priv->no_pape = 1; 450 | priv->power_base = &rtl8188r_power_base; 451 | } 452 | 453 | return 0; 454 | } 455 | 456 | static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv) 457 | { 458 | const struct rtl8xxxu_rfregval *rftable; 459 | int ret; 460 | 461 | if (priv->rtl_chip == RTL8188R) { 462 | rftable = rtl8188ru_radioa_1t_highpa_table; 463 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); 464 | } else if (priv->rf_paths == 1) { 465 | rftable = rtl8192cu_radioa_1t_init_table; 466 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); 467 | } else { 468 | rftable = rtl8192cu_radioa_2t_init_table; 469 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); 470 | if (ret) 471 | goto exit; 472 | rftable = rtl8192cu_radiob_2t_init_table; 473 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); 474 | } 475 | 476 | exit: 477 | return ret; 478 | } 479 | 480 | static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) 481 | { 482 | u8 val8; 483 | u16 val16; 484 | u32 val32; 485 | int i; 486 | 487 | for (i = 100; i; i--) { 488 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); 489 | if (val8 & APS_FSMCO_PFM_ALDN) 490 | break; 491 | } 492 | 493 | if (!i) { 494 | pr_info("%s: Poll failed\n", __func__); 495 | return -ENODEV; 496 | } 497 | 498 | /* 499 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register 500 | */ 501 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); 502 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); 503 | udelay(100); 504 | 505 | val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); 506 | if (!(val8 & LDOV12D_ENABLE)) { 507 | pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); 508 | val8 |= LDOV12D_ENABLE; 509 | rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); 510 | 511 | udelay(100); 512 | 513 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 514 | val8 &= ~SYS_ISO_MD2PP; 515 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 516 | } 517 | 518 | /* 519 | * Auto enable WLAN 520 | */ 521 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 522 | val16 |= APS_FSMCO_MAC_ENABLE; 523 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 524 | 525 | for (i = 1000; i; i--) { 526 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 527 | if (!(val16 & APS_FSMCO_MAC_ENABLE)) 528 | break; 529 | } 530 | if (!i) { 531 | pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); 532 | return -EBUSY; 533 | } 534 | 535 | /* 536 | * Enable radio, GPIO, LED 537 | */ 538 | val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | 539 | APS_FSMCO_PFM_ALDN; 540 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 541 | 542 | /* 543 | * Release RF digital isolation 544 | */ 545 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 546 | val16 &= ~SYS_ISO_DIOR; 547 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 548 | 549 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); 550 | val8 &= ~APSD_CTRL_OFF; 551 | rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); 552 | for (i = 200; i; i--) { 553 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); 554 | if (!(val8 & APSD_CTRL_OFF_STATUS)) 555 | break; 556 | } 557 | 558 | if (!i) { 559 | pr_info("%s: APSD_CTRL poll failed\n", __func__); 560 | return -EBUSY; 561 | } 562 | 563 | /* 564 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block 565 | */ 566 | val16 = rtl8xxxu_read16(priv, REG_CR); 567 | val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 568 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | 569 | CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; 570 | rtl8xxxu_write16(priv, REG_CR, val16); 571 | 572 | rtl8xxxu_write8(priv, 0xfe10, 0x19); 573 | 574 | /* 575 | * Workaround for 8188RU LNA power leakage problem. 576 | */ 577 | if (priv->rtl_chip == RTL8188R) { 578 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 579 | val32 &= ~BIT(1); 580 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 581 | } 582 | return 0; 583 | } 584 | 585 | struct rtl8xxxu_fileops rtl8192cu_fops = { 586 | .identify_chip = rtl8192cu_identify_chip, 587 | .parse_efuse = rtl8192cu_parse_efuse, 588 | .load_firmware = rtl8192cu_load_firmware, 589 | .power_on = rtl8192cu_power_on, 590 | .power_off = rtl8xxxu_power_off, 591 | .read_efuse = rtl8xxxu_read_efuse, 592 | .reset_8051 = rtl8xxxu_reset_8051, 593 | .llt_init = rtl8xxxu_init_llt_table, 594 | .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, 595 | .init_phy_rf = rtl8192cu_init_phy_rf, 596 | .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 597 | .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, 598 | .config_channel = rtl8xxxu_gen1_config_channel, 599 | .parse_rx_desc = rtl8xxxu_parse_rxdesc16, 600 | .parse_phystats = rtl8723au_rx_parse_phystats, 601 | .init_aggregation = rtl8xxxu_gen1_init_aggregation, 602 | .enable_rf = rtl8xxxu_gen1_enable_rf, 603 | .disable_rf = rtl8xxxu_gen1_disable_rf, 604 | .usb_quirks = rtl8xxxu_gen1_usb_quirks, 605 | .set_tx_power = rtl8xxxu_gen1_set_tx_power, 606 | .update_rate_mask = rtl8xxxu_update_rate_mask, 607 | .report_connect = rtl8xxxu_gen1_report_connect, 608 | .report_rssi = rtl8xxxu_gen1_report_rssi, 609 | .fill_txdesc = rtl8xxxu_fill_txdesc_v1, 610 | .cck_rssi = rtl8723a_cck_rssi, 611 | .writeN_block_size = 128, 612 | .rx_agg_buf_size = 16000, 613 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), 614 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), 615 | .adda_1t_init = 0x0b1b25a0, 616 | .adda_1t_path_on = 0x0bdb25a0, 617 | .adda_2t_path_on_a = 0x04db25a4, 618 | .adda_2t_path_on_b = 0x0b1b25a4, 619 | .trxff_boundary = 0x27ff, 620 | .pbp_rx = PBP_PAGE_SIZE_128, 621 | .pbp_tx = PBP_PAGE_SIZE_128, 622 | .mactable = rtl8xxxu_gen1_mac_init_table, 623 | .total_page_num = TX_TOTAL_PAGE_NUM, 624 | .page_num_hi = TX_PAGE_NUM_HI_PQ, 625 | .page_num_lo = TX_PAGE_NUM_LO_PQ, 626 | .page_num_norm = TX_PAGE_NUM_NORM_PQ, 627 | }; 628 | -------------------------------------------------------------------------------- /rtl8xxxu_8723a.c: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0-only 2 | /* 3 | * RTL8XXXU mac80211 USB driver - 8723a specific subdriver 4 | * 5 | * Copyright (c) 2014 - 2017 Jes Sorensen 6 | * 7 | * Portions, notably calibration code: 8 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 | * 10 | * This driver was written as a replacement for the vendor provided 11 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 | * their programming interface, I have started adding support for 13 | * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 | */ 15 | 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include "rtl8xxxu.h" 33 | #include "rtl8xxxu_regs.h" 34 | 35 | static struct rtl8xxxu_power_base rtl8723a_power_base = { 36 | .reg_0e00 = 0x0a0c0c0c, 37 | .reg_0e04 = 0x02040608, 38 | .reg_0e08 = 0x00000000, 39 | .reg_086c = 0x00000000, 40 | 41 | .reg_0e10 = 0x0a0c0d0e, 42 | .reg_0e14 = 0x02040608, 43 | .reg_0e18 = 0x0a0c0d0e, 44 | .reg_0e1c = 0x02040608, 45 | 46 | .reg_0830 = 0x0a0c0c0c, 47 | .reg_0834 = 0x02040608, 48 | .reg_0838 = 0x00000000, 49 | .reg_086c_2 = 0x00000000, 50 | 51 | .reg_083c = 0x0a0c0d0e, 52 | .reg_0848 = 0x02040608, 53 | .reg_084c = 0x0a0c0d0e, 54 | .reg_0868 = 0x02040608, 55 | }; 56 | 57 | static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { 58 | {0x00, 0x00030159}, {0x01, 0x00031284}, 59 | {0x02, 0x00098000}, {0x03, 0x00039c63}, 60 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, 61 | {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, 62 | {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, 63 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 64 | {0x19, 0x00000000}, {0x1a, 0x00030355}, 65 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 66 | {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, 67 | {0x1f, 0x00000000}, {0x20, 0x0000b614}, 68 | {0x21, 0x0006c000}, {0x22, 0x00000000}, 69 | {0x23, 0x00001558}, {0x24, 0x00000060}, 70 | {0x25, 0x00000483}, {0x26, 0x0004f000}, 71 | {0x27, 0x000ec7d9}, {0x28, 0x00057730}, 72 | {0x29, 0x00004783}, {0x2a, 0x00000001}, 73 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, 74 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, 75 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, 76 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 77 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 78 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 79 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, 80 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 81 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 82 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 83 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, 84 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 85 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 86 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 87 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, 88 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 89 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 90 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 91 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 92 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 93 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 94 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 95 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 96 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 97 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 98 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 99 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 100 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 101 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 102 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 103 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 104 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 105 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, 106 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, 107 | {0x10, 0x00000000}, {0x11, 0x00000000}, 108 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, 109 | {0x10, 0x0009000f}, {0x11, 0x00023100}, 110 | {0x12, 0x00032000}, {0x12, 0x00071000}, 111 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, 112 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, 113 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 114 | {0x13, 0x00018493}, {0x13, 0x0001429b}, 115 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, 116 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, 117 | {0x13, 0x00000020}, {0x14, 0x0001944c}, 118 | {0x14, 0x00059444}, {0x14, 0x0009944c}, 119 | {0x14, 0x000d9444}, {0x15, 0x0000f474}, 120 | {0x15, 0x0004f477}, {0x15, 0x0008f455}, 121 | {0x15, 0x000cf455}, {0x16, 0x00000339}, 122 | {0x16, 0x00040339}, {0x16, 0x00080339}, 123 | {0x16, 0x000c0366}, {0x00, 0x00010159}, 124 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, 125 | {0xfe, 0x00000000}, {0x1f, 0x00000003}, 126 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, 127 | {0x1e, 0x00000247}, {0x1f, 0x00000000}, 128 | {0x00, 0x00030159}, 129 | {0xff, 0xffffffff} 130 | }; 131 | 132 | static int rtl8723au_identify_chip(struct rtl8xxxu_priv *priv) 133 | { 134 | struct device *dev = &priv->udev->dev; 135 | u32 val32, sys_cfg, vendor; 136 | int ret = 0; 137 | 138 | sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 139 | priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 140 | if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 141 | dev_info(dev, "Unsupported test chip\n"); 142 | ret = -ENOTSUPP; 143 | goto out; 144 | } 145 | 146 | strscpy(priv->chip_name, "8723AU", sizeof(priv->chip_name)); 147 | priv->usb_interrupts = 1; 148 | priv->rtl_chip = RTL8723A; 149 | 150 | priv->rf_paths = 1; 151 | priv->rx_paths = 1; 152 | priv->tx_paths = 1; 153 | 154 | val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 155 | if (val32 & MULTI_WIFI_FUNC_EN) 156 | priv->has_wifi = 1; 157 | if (val32 & MULTI_BT_FUNC_EN) 158 | priv->has_bluetooth = 1; 159 | if (val32 & MULTI_GPS_FUNC_EN) 160 | priv->has_gps = 1; 161 | priv->is_multi_func = 1; 162 | 163 | vendor = sys_cfg & SYS_CFG_VENDOR_ID; 164 | rtl8xxxu_identify_vendor_1bit(priv, vendor); 165 | 166 | val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 167 | priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 168 | 169 | rtl8xxxu_config_endpoints_sie(priv); 170 | 171 | /* 172 | * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 173 | */ 174 | if (!priv->ep_tx_count) 175 | ret = rtl8xxxu_config_endpoints_no_sie(priv); 176 | 177 | out: 178 | return ret; 179 | } 180 | 181 | static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) 182 | { 183 | struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723; 184 | 185 | if (efuse->rtl_id != cpu_to_le16(0x8129)) 186 | return -EINVAL; 187 | 188 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); 189 | 190 | memcpy(priv->cck_tx_power_index_A, 191 | efuse->cck_tx_power_index_A, 192 | sizeof(efuse->cck_tx_power_index_A)); 193 | memcpy(priv->cck_tx_power_index_B, 194 | efuse->cck_tx_power_index_B, 195 | sizeof(efuse->cck_tx_power_index_B)); 196 | 197 | memcpy(priv->ht40_1s_tx_power_index_A, 198 | efuse->ht40_1s_tx_power_index_A, 199 | sizeof(efuse->ht40_1s_tx_power_index_A)); 200 | memcpy(priv->ht40_1s_tx_power_index_B, 201 | efuse->ht40_1s_tx_power_index_B, 202 | sizeof(efuse->ht40_1s_tx_power_index_B)); 203 | 204 | memcpy(priv->ht20_tx_power_index_diff, 205 | efuse->ht20_tx_power_index_diff, 206 | sizeof(efuse->ht20_tx_power_index_diff)); 207 | memcpy(priv->ofdm_tx_power_index_diff, 208 | efuse->ofdm_tx_power_index_diff, 209 | sizeof(efuse->ofdm_tx_power_index_diff)); 210 | 211 | memcpy(priv->ht40_max_power_offset, 212 | efuse->ht40_max_power_offset, 213 | sizeof(efuse->ht40_max_power_offset)); 214 | memcpy(priv->ht20_max_power_offset, 215 | efuse->ht20_max_power_offset, 216 | sizeof(efuse->ht20_max_power_offset)); 217 | 218 | if (priv->efuse_wifi.efuse8723.version >= 0x01) 219 | priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; 220 | else 221 | priv->fops->set_crystal_cap = NULL; 222 | 223 | priv->power_base = &rtl8723a_power_base; 224 | 225 | return 0; 226 | } 227 | 228 | static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) 229 | { 230 | const char *fw_name; 231 | int ret; 232 | 233 | switch (priv->chip_cut) { 234 | case 0: 235 | fw_name = "rtlwifi/rtl8723aufw_A.bin"; 236 | break; 237 | case 1: 238 | if (priv->enable_bluetooth) 239 | fw_name = "rtlwifi/rtl8723aufw_B.bin"; 240 | else 241 | fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; 242 | 243 | break; 244 | default: 245 | return -EINVAL; 246 | } 247 | 248 | ret = rtl8xxxu_load_firmware(priv, fw_name); 249 | return ret; 250 | } 251 | 252 | static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv) 253 | { 254 | int ret; 255 | 256 | ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A); 257 | 258 | /* Reduce 80M spur */ 259 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); 260 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); 261 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); 262 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); 263 | 264 | return ret; 265 | } 266 | 267 | static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv) 268 | { 269 | u8 val8; 270 | u32 val32; 271 | int count, ret = 0; 272 | 273 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ 274 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 275 | val8 |= LDOA15_ENABLE; 276 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 277 | 278 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ 279 | val8 = rtl8xxxu_read8(priv, 0x0067); 280 | val8 &= ~BIT(4); 281 | rtl8xxxu_write8(priv, 0x0067, val8); 282 | 283 | mdelay(1); 284 | 285 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ 286 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 287 | val8 &= ~SYS_ISO_ANALOG_IPS; 288 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 289 | 290 | /* disable SW LPS 0x04[10]= 0 */ 291 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 292 | val8 &= ~BIT(2); 293 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 294 | 295 | /* wait till 0x04[17] = 1 power ready*/ 296 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 297 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 298 | if (val32 & BIT(17)) 299 | break; 300 | 301 | udelay(10); 302 | } 303 | 304 | if (!count) { 305 | ret = -EBUSY; 306 | goto exit; 307 | } 308 | 309 | /* We should be able to optimize the following three entries into one */ 310 | 311 | /* release WLON reset 0x04[16]= 1*/ 312 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); 313 | val8 |= BIT(0); 314 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); 315 | 316 | /* disable HWPDN 0x04[15]= 0*/ 317 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 318 | val8 &= ~BIT(7); 319 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 320 | 321 | /* disable WL suspend*/ 322 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 323 | val8 &= ~(BIT(3) | BIT(4)); 324 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 325 | 326 | /* set, then poll until 0 */ 327 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 328 | val32 |= APS_FSMCO_MAC_ENABLE; 329 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 330 | 331 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 332 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 333 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 334 | ret = 0; 335 | break; 336 | } 337 | udelay(10); 338 | } 339 | 340 | if (!count) { 341 | ret = -EBUSY; 342 | goto exit; 343 | } 344 | 345 | /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ 346 | /* 347 | * Note: Vendor driver actually clears this bit, despite the 348 | * documentation claims it's being set! 349 | */ 350 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 351 | val8 |= LEDCFG2_DPDT_SELECT; 352 | val8 &= ~LEDCFG2_DPDT_SELECT; 353 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 354 | 355 | exit: 356 | return ret; 357 | } 358 | 359 | static int rtl8723au_power_on(struct rtl8xxxu_priv *priv) 360 | { 361 | u8 val8; 362 | u16 val16; 363 | u32 val32; 364 | int ret; 365 | 366 | /* 367 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register 368 | */ 369 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); 370 | 371 | rtl8xxxu_disabled_to_emu(priv); 372 | 373 | ret = rtl8723a_emu_to_active(priv); 374 | if (ret) 375 | goto exit; 376 | 377 | /* 378 | * 0x0004[19] = 1, reset 8051 379 | */ 380 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); 381 | val8 |= BIT(3); 382 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); 383 | 384 | /* 385 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block 386 | * Set CR bit10 to enable 32k calibration. 387 | */ 388 | val16 = rtl8xxxu_read16(priv, REG_CR); 389 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 390 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 391 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 392 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | 393 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 394 | rtl8xxxu_write16(priv, REG_CR, val16); 395 | 396 | /* For EFuse PG */ 397 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 398 | val32 &= ~(BIT(28) | BIT(29) | BIT(30)); 399 | val32 |= (0x06 << 28); 400 | rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); 401 | exit: 402 | return ret; 403 | } 404 | 405 | #define XTAL1 GENMASK(23, 18) 406 | #define XTAL0 GENMASK(17, 12) 407 | 408 | void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) 409 | { 410 | struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 411 | u32 val32; 412 | 413 | if (crystal_cap == cfo->crystal_cap) 414 | return; 415 | 416 | val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); 417 | 418 | dev_dbg(&priv->udev->dev, 419 | "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", 420 | __func__, 421 | cfo->crystal_cap, 422 | FIELD_GET(XTAL1, val32), 423 | FIELD_GET(XTAL0, val32), 424 | crystal_cap); 425 | 426 | val32 &= ~(XTAL1 | XTAL0); 427 | val32 |= FIELD_PREP(XTAL1, crystal_cap) | 428 | FIELD_PREP(XTAL0, crystal_cap); 429 | rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); 430 | 431 | cfo->crystal_cap = crystal_cap; 432 | } 433 | 434 | s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) 435 | { 436 | u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 437 | s8 rx_pwr_all = 0x00; 438 | 439 | switch (cck_agc_rpt & 0xc0) { 440 | case 0xc0: 441 | rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); 442 | break; 443 | case 0x80: 444 | rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); 445 | break; 446 | case 0x40: 447 | rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); 448 | break; 449 | case 0x00: 450 | rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); 451 | break; 452 | } 453 | 454 | return rx_pwr_all; 455 | } 456 | 457 | static int rtl8723au_led_brightness_set(struct led_classdev *led_cdev, 458 | enum led_brightness brightness) 459 | { 460 | struct rtl8xxxu_priv *priv = container_of(led_cdev, 461 | struct rtl8xxxu_priv, 462 | led_cdev); 463 | u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); 464 | 465 | if (brightness == LED_OFF) { 466 | ledcfg &= ~LEDCFG2_HW_LED_CONTROL; 467 | ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; 468 | } else if (brightness == LED_ON) { 469 | ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); 470 | ledcfg |= LEDCFG2_SW_LED_CONTROL; 471 | } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { 472 | ledcfg &= ~LEDCFG2_SW_LED_DISABLE; 473 | ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; 474 | } 475 | 476 | rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); 477 | 478 | return 0; 479 | } 480 | 481 | struct rtl8xxxu_fileops rtl8723au_fops = { 482 | .identify_chip = rtl8723au_identify_chip, 483 | .parse_efuse = rtl8723au_parse_efuse, 484 | .load_firmware = rtl8723au_load_firmware, 485 | .power_on = rtl8723au_power_on, 486 | .power_off = rtl8xxxu_power_off, 487 | .read_efuse = rtl8xxxu_read_efuse, 488 | .reset_8051 = rtl8xxxu_reset_8051, 489 | .llt_init = rtl8xxxu_init_llt_table, 490 | .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, 491 | .init_phy_rf = rtl8723au_init_phy_rf, 492 | .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 493 | .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, 494 | .config_channel = rtl8xxxu_gen1_config_channel, 495 | .parse_rx_desc = rtl8xxxu_parse_rxdesc16, 496 | .parse_phystats = rtl8723au_rx_parse_phystats, 497 | .init_aggregation = rtl8xxxu_gen1_init_aggregation, 498 | .enable_rf = rtl8xxxu_gen1_enable_rf, 499 | .disable_rf = rtl8xxxu_gen1_disable_rf, 500 | .usb_quirks = rtl8xxxu_gen1_usb_quirks, 501 | .set_tx_power = rtl8xxxu_gen1_set_tx_power, 502 | .update_rate_mask = rtl8xxxu_update_rate_mask, 503 | .report_connect = rtl8xxxu_gen1_report_connect, 504 | .report_rssi = rtl8xxxu_gen1_report_rssi, 505 | .fill_txdesc = rtl8xxxu_fill_txdesc_v1, 506 | .set_crystal_cap = rtl8723a_set_crystal_cap, 507 | .cck_rssi = rtl8723a_cck_rssi, 508 | .led_classdev_brightness_set = rtl8723au_led_brightness_set, 509 | .writeN_block_size = 1024, 510 | .rx_agg_buf_size = 16000, 511 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), 512 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), 513 | .adda_1t_init = 0x0b1b25a0, 514 | .adda_1t_path_on = 0x0bdb25a0, 515 | .adda_2t_path_on_a = 0x04db25a4, 516 | .adda_2t_path_on_b = 0x0b1b25a4, 517 | .trxff_boundary = 0x27ff, 518 | .pbp_rx = PBP_PAGE_SIZE_128, 519 | .pbp_tx = PBP_PAGE_SIZE_128, 520 | .mactable = rtl8xxxu_gen1_mac_init_table, 521 | .total_page_num = TX_TOTAL_PAGE_NUM, 522 | .page_num_hi = TX_PAGE_NUM_HI_PQ, 523 | .page_num_lo = TX_PAGE_NUM_LO_PQ, 524 | .page_num_norm = TX_PAGE_NUM_NORM_PQ, 525 | }; 526 | -------------------------------------------------------------------------------- /rtl8xxxu_regs.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * Copyright (c) 2014 - 2017 Jes Sorensen 4 | * 5 | * Register definitions taken from original Realtek rtl8723au driver 6 | */ 7 | 8 | /* 0x0000 ~ 0x00FF System Configuration */ 9 | #define REG_SYS_ISO_CTRL 0x0000 10 | #define SYS_ISO_MD2PP BIT(0) 11 | #define SYS_ISO_ANALOG_IPS BIT(5) 12 | #define SYS_ISO_DIOR BIT(9) 13 | #define SYS_ISO_PWC_EV25V BIT(14) 14 | #define SYS_ISO_PWC_EV12V BIT(15) 15 | 16 | #define REG_SYS_FUNC 0x0002 17 | #define SYS_FUNC_BBRSTB BIT(0) 18 | #define SYS_FUNC_BB_GLB_RSTN BIT(1) 19 | #define SYS_FUNC_USBA BIT(2) 20 | #define SYS_FUNC_UPLL BIT(3) 21 | #define SYS_FUNC_USBD BIT(4) 22 | #define SYS_FUNC_DIO_PCIE BIT(5) 23 | #define SYS_FUNC_PCIEA BIT(6) 24 | #define SYS_FUNC_PPLL BIT(7) 25 | #define SYS_FUNC_PCIED BIT(8) 26 | #define SYS_FUNC_DIOE BIT(9) 27 | #define SYS_FUNC_CPU_ENABLE BIT(10) 28 | #define SYS_FUNC_DCORE BIT(11) 29 | #define SYS_FUNC_ELDR BIT(12) 30 | #define SYS_FUNC_DIO_RF BIT(13) 31 | #define SYS_FUNC_HWPDN BIT(14) 32 | #define SYS_FUNC_MREGEN BIT(15) 33 | 34 | #define REG_APS_FSMCO 0x0004 35 | #define APS_FSMCO_PFM_ALDN BIT(1) 36 | #define APS_FSMCO_PFM_WOWL BIT(3) 37 | #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 38 | #define APS_FSMCO_MAC_ENABLE BIT(8) 39 | #define APS_FSMCO_MAC_OFF BIT(9) 40 | #define APS_FSMCO_SW_LPS BIT(10) 41 | #define APS_FSMCO_HW_SUSPEND BIT(11) 42 | #define APS_FSMCO_PCIE BIT(12) 43 | #define APS_FSMCO_HW_POWERDOWN BIT(15) 44 | #define APS_FSMCO_WLON_RESET BIT(16) 45 | 46 | #define REG_SYS_CLKR 0x0008 47 | #define SYS_CLK_ANAD16V_ENABLE BIT(0) 48 | #define SYS_CLK_ANA8M BIT(1) 49 | #define SYS_CLK_MACSLP BIT(4) 50 | #define SYS_CLK_LOADER_ENABLE BIT(5) 51 | #define SYS_CLK_80M_SSC_DISABLE BIT(7) 52 | #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 53 | #define SYS_CLK_PHY_SSC_RSTB BIT(9) 54 | #define SYS_CLK_SEC_CLK_ENABLE BIT(10) 55 | #define SYS_CLK_MAC_CLK_ENABLE BIT(11) 56 | #define SYS_CLK_ENABLE BIT(12) 57 | #define SYS_CLK_RING_CLK_ENABLE BIT(13) 58 | 59 | #define REG_9346CR 0x000a 60 | #define EEPROM_BOOT BIT(4) 61 | #define EEPROM_ENABLE BIT(5) 62 | 63 | #define REG_EE_VPD 0x000c 64 | #define REG_AFE_MISC 0x0010 65 | #define AFE_MISC_WL_XTAL_CTRL BIT(6) 66 | 67 | #define REG_SPS0_CTRL 0x0011 68 | #define REG_SPS_OCP_CFG 0x0018 69 | #define REG_8192E_LDOV12_CTRL 0x0014 70 | #define REG_RSV_CTRL 0x001c 71 | #define RSV_CTRL_WLOCK_1C BIT(5) 72 | #define RSV_CTRL_DIS_PRST BIT(6) 73 | 74 | #define REG_RF_CTRL 0x001f 75 | #define RF_ENABLE BIT(0) 76 | #define RF_RSTB BIT(1) 77 | #define RF_SDMRSTB BIT(2) 78 | 79 | #define REG_LDOA15_CTRL 0x0020 80 | #define LDOA15_ENABLE BIT(0) 81 | #define LDOA15_STANDBY BIT(1) 82 | #define LDOA15_OBUF BIT(2) 83 | #define LDOA15_REG_VOS BIT(3) 84 | #define LDOA15_VOADJ_SHIFT 4 85 | 86 | #define REG_LDOV12D_CTRL 0x0021 87 | #define LDOV12D_ENABLE BIT(0) 88 | #define LDOV12D_STANDBY BIT(1) 89 | #define LDOV12D_VADJ_SHIFT 4 90 | 91 | #define REG_LDOHCI12_CTRL 0x0022 92 | 93 | #define REG_LPLDO_CTRL 0x0023 94 | #define LPLDO_HSM BIT(2) 95 | #define LPLDO_LSM_DIS BIT(3) 96 | 97 | #define REG_AFE_XTAL_CTRL 0x0024 98 | #define AFE_XTAL_ENABLE BIT(0) 99 | #define AFE_XTAL_B_SELECT BIT(1) 100 | #define AFE_XTAL_GATE_USB BIT(8) 101 | #define AFE_XTAL_GATE_AFE BIT(11) 102 | #define AFE_XTAL_RF_GATE BIT(14) 103 | #define AFE_XTAL_GATE_DIG BIT(17) 104 | #define AFE_XTAL_BT_GATE BIT(20) 105 | 106 | /* 107 | * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu 108 | */ 109 | #define REG_AFE_PLL_CTRL 0x0028 110 | #define AFE_PLL_ENABLE BIT(0) 111 | #define AFE_PLL_320_ENABLE BIT(1) 112 | #define APE_PLL_FREF_SELECT BIT(2) 113 | #define AFE_PLL_EDGE_SELECT BIT(3) 114 | #define AFE_PLL_WDOGB BIT(4) 115 | #define AFE_PLL_LPF_ENABLE BIT(5) 116 | 117 | #define REG_MAC_PHY_CTRL 0x002c 118 | 119 | #define REG_EFUSE_CTRL 0x0030 120 | #define REG_EFUSE_TEST 0x0034 121 | #define EFUSE_TRPT BIT(7) 122 | /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 123 | #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 124 | #define EFUSE_LDOE25_ENABLE BIT(31) 125 | #define EFUSE_SELECT_MASK 0x0300 126 | #define EFUSE_WIFI_SELECT 0x0000 127 | #define EFUSE_BT0_SELECT 0x0100 128 | #define EFUSE_BT1_SELECT 0x0200 129 | #define EFUSE_BT2_SELECT 0x0300 130 | 131 | #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 132 | #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 133 | 134 | #define REG_PWR_DATA 0x0038 135 | #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) 136 | 137 | #define REG_CAL_TIMER 0x003c 138 | #define REG_ACLK_MON 0x003e 139 | #define REG_GPIO_MUXCFG 0x0040 140 | #define GPIO_MUXCFG_IO_SEL_ENBT BIT(5) 141 | #define REG_GPIO_IO_SEL 0x0042 142 | #define REG_MAC_PINMUX_CFG 0x0043 143 | #define REG_GPIO_PIN_CTRL 0x0044 144 | #define REG_GPIO_INTM 0x0048 145 | #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) 146 | 147 | #define REG_LEDCFG0 0x004c 148 | #define LEDCFG0_DPDT_SELECT BIT(23) 149 | #define REG_LEDCFG1 0x004d 150 | #define LEDCFG1_HW_LED_CONTROL BIT(1) 151 | #define LEDCFG1_LED_DISABLE BIT(7) 152 | #define REG_LEDCFG2 0x004e 153 | #define LEDCFG2_HW_LED_CONTROL BIT(1) 154 | #define LEDCFG2_HW_LED_ENABLE BIT(5) 155 | #define LEDCFG2_SW_LED_DISABLE BIT(3) 156 | #define LEDCFG2_SW_LED_CONTROL BIT(5) 157 | #define LEDCFG2_DPDT_SELECT BIT(7) 158 | #define REG_LEDCFG3 0x004f 159 | #define REG_LEDCFG REG_LEDCFG2 160 | #define REG_FSIMR 0x0050 161 | #define REG_FSISR 0x0054 162 | #define REG_HSIMR 0x0058 163 | #define REG_HSISR 0x005c 164 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 165 | #define REG_GPIO_PIN_CTRL_2 0x0060 166 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 167 | #define REG_GPIO_IO_SEL_2 0x0062 168 | #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) 169 | #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) 170 | 171 | /* RTL8723B */ 172 | #define REG_PAD_CTRL1 0x0064 173 | #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) 174 | 175 | /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 176 | #define REG_MULTI_FUNC_CTRL 0x0068 177 | 178 | #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 179 | powerdown source */ 180 | #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 181 | control */ 182 | #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 183 | 184 | #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 185 | powerdown source */ 186 | #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 187 | powerdown source */ 188 | #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 189 | control */ 190 | #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 191 | #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 192 | RF HW powerdown source */ 193 | #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 194 | powerdown source */ 195 | #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 196 | control */ 197 | #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 198 | 199 | #define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ 200 | #define REG_LDO_SW_CTRL 0x007c /* 8192eu */ 201 | 202 | #define REG_MCU_FW_DL 0x0080 203 | #define MCU_FW_DL_ENABLE BIT(0) 204 | #define MCU_FW_DL_READY BIT(1) 205 | #define MCU_FW_DL_CSUM_REPORT BIT(2) 206 | #define MCU_MAC_INIT_READY BIT(3) 207 | #define MCU_BB_INIT_READY BIT(4) 208 | #define MCU_RF_INIT_READY BIT(5) 209 | #define MCU_WINT_INIT_READY BIT(6) 210 | #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 211 | #define MCU_CP_RESET BIT(23) 212 | 213 | #define REG_HMBOX_EXT_0 0x0088 214 | #define REG_HMBOX_EXT_1 0x008a 215 | #define REG_HMBOX_EXT_2 0x008c 216 | #define REG_HMBOX_EXT_3 0x008e 217 | 218 | /* Interrupt registers for 8192e/8723bu/8812 */ 219 | #define REG_HIMR0 0x00b0 220 | #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit 221 | of the packet is set */ 222 | #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ 223 | #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ 224 | #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ 225 | #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ 226 | #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ 227 | #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle 228 | indication interrupt */ 229 | #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ 230 | #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ 231 | #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & 232 | HSISR is true) */ 233 | #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt 234 | Extension for Win7 */ 235 | #define IMR0_ATIMEND BIT(12) /* CTWidnow End or 236 | ATIM Window End */ 237 | #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator 238 | (HISR1 & HIMR1 is true) */ 239 | #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT 240 | Status, Write 1 to clear */ 241 | #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT 242 | Status, Write 1 to clear */ 243 | #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT 244 | Status, Write 1 to clear */ 245 | #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ 246 | #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ 247 | #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ 248 | #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ 249 | #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ 250 | #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ 251 | #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ 252 | #define IMR0_ROK BIT(0) /* Receive DMA OK */ 253 | #define REG_HISR0 0x00b4 254 | #define REG_HIMR1 0x00b8 255 | #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ 256 | #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ 257 | #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ 258 | #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ 259 | #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ 260 | #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ 261 | #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ 262 | #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ 263 | #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ 264 | #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ 265 | #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ 266 | #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ 267 | #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ 268 | #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ 269 | #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension 270 | for Win7 */ 271 | #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, 272 | write 1 to clear */ 273 | #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, 274 | write 1 to clear */ 275 | #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ 276 | #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ 277 | #define REG_HISR1 0x00bc 278 | 279 | /* Host suspend counter on FPGA platform */ 280 | #define REG_HOST_SUSP_CNT 0x00bc 281 | /* Efuse access protection for RTL8723 */ 282 | #define REG_EFUSE_ACCESS 0x00cf 283 | #define REG_BIST_SCAN 0x00d0 284 | #define REG_BIST_RPT 0x00d4 285 | #define REG_BIST_ROM_RPT 0x00d8 286 | #define REG_USB_SIE_INTF 0x00e0 287 | #define REG_PCIE_MIO_INTF 0x00e4 288 | #define REG_PCIE_MIO_INTD 0x00e8 289 | #define REG_HPON_FSM 0x00ec 290 | #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 291 | #define HPON_FSM_BONDING_1T2R BIT(22) 292 | #define REG_SYS_CFG 0x00f0 293 | #define SYS_CFG_XCLK_VLD BIT(0) 294 | #define SYS_CFG_ACLK_VLD BIT(1) 295 | #define SYS_CFG_UCLK_VLD BIT(2) 296 | #define SYS_CFG_PCLK_VLD BIT(3) 297 | #define SYS_CFG_PCIRSTB BIT(4) 298 | #define SYS_CFG_V15_VLD BIT(5) 299 | #define SYS_CFG_TRP_B15V_EN BIT(7) 300 | #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ 301 | #define SYS_CFG_SIC_IDLE BIT(8) 302 | #define SYS_CFG_BD_MAC2 BIT(9) 303 | #define SYS_CFG_BD_MAC1 BIT(10) 304 | #define SYS_CFG_IC_MACPHY_MODE BIT(11) 305 | #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 306 | #define SYS_CFG_BT_FUNC BIT(16) 307 | #define SYS_CFG_VENDOR_ID BIT(19) 308 | #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) 309 | #define SYS_CFG_VENDOR_ID_TSMC 0 310 | #define SYS_CFG_VENDOR_ID_SMIC BIT(18) 311 | #define SYS_CFG_VENDOR_ID_UMC BIT(19) 312 | #define SYS_CFG_PAD_HWPD_IDN BIT(22) 313 | #define SYS_CFG_TRP_VAUX_EN BIT(23) 314 | #define SYS_CFG_TRP_BT_EN BIT(24) 315 | #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ 316 | #define SYS_CFG_BD_PKG_SEL BIT(25) 317 | #define SYS_CFG_BD_HCI_SEL BIT(26) 318 | #define SYS_CFG_TYPE_ID BIT(27) 319 | #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 320 | 1:Test(RLE); 0:MP(RL) */ 321 | #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 322 | 0:Switching regulator mode*/ 323 | #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 324 | 325 | #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 326 | #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 327 | #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 328 | #define GPIO_HCI_SEL (BIT(4) | BIT(5)) 329 | #define GPIO_PKG_SEL_HCI BIT(6) 330 | #define GPIO_FEN_GPS BIT(7) 331 | #define GPIO_FEN_BT BIT(8) 332 | #define GPIO_FEN_WL BIT(9) 333 | #define GPIO_FEN_PCI BIT(10) 334 | #define GPIO_FEN_USB BIT(11) 335 | #define GPIO_BTRF_HWPDN_N BIT(12) 336 | #define GPIO_WLRF_HWPDN_N BIT(13) 337 | #define GPIO_PDN_BT_N BIT(14) 338 | #define GPIO_PDN_GPS_N BIT(15) 339 | #define GPIO_BT_CTL_HWPDN BIT(16) 340 | #define GPIO_GPS_CTL_HWPDN BIT(17) 341 | #define GPIO_PPHY_SUSB BIT(20) 342 | #define GPIO_UPHY_SUSB BIT(21) 343 | #define GPIO_PCI_SUSEN BIT(22) 344 | #define GPIO_USB_SUSEN BIT(23) 345 | #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 346 | 347 | #define REG_SYS_CFG2 0x00fc /* 8192eu */ 348 | 349 | /* 0x0100 ~ 0x01FF MACTOP General Configuration */ 350 | #define REG_CR 0x0100 351 | #define CR_HCI_TXDMA_ENABLE BIT(0) 352 | #define CR_HCI_RXDMA_ENABLE BIT(1) 353 | #define CR_TXDMA_ENABLE BIT(2) 354 | #define CR_RXDMA_ENABLE BIT(3) 355 | #define CR_PROTOCOL_ENABLE BIT(4) 356 | #define CR_SCHEDULE_ENABLE BIT(5) 357 | #define CR_MAC_TX_ENABLE BIT(6) 358 | #define CR_MAC_RX_ENABLE BIT(7) 359 | #define CR_SW_BEACON_ENABLE BIT(8) 360 | #define CR_SECURITY_ENABLE BIT(9) 361 | #define CR_CALTIMER_ENABLE BIT(10) 362 | 363 | /* Media Status Register */ 364 | #define REG_MSR 0x0102 365 | #define MSR_LINKTYPE_MASK 0x3 366 | #define MSR_LINKTYPE_NONE 0x0 367 | #define MSR_LINKTYPE_ADHOC 0x1 368 | #define MSR_LINKTYPE_STATION 0x2 369 | #define MSR_LINKTYPE_AP 0x3 370 | 371 | #define REG_PBP 0x0104 372 | #define PBP_PAGE_SIZE_RX_SHIFT 0 373 | #define PBP_PAGE_SIZE_TX_SHIFT 4 374 | #define PBP_PAGE_SIZE_64 0x0 375 | #define PBP_PAGE_SIZE_128 0x1 376 | #define PBP_PAGE_SIZE_256 0x2 377 | #define PBP_PAGE_SIZE_512 0x3 378 | #define PBP_PAGE_SIZE_1024 0x4 379 | 380 | /* 8188eu IOL magic */ 381 | #define REG_PKT_BUF_ACCESS_CTRL 0x0106 382 | #define PKT_BUF_ACCESS_CTRL_TX 0x69 383 | #define PKT_BUF_ACCESS_CTRL_RX 0xa5 384 | 385 | #define REG_TRXDMA_CTRL 0x010c 386 | #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) 387 | #define TRXDMA_CTRL_VOQ_SHIFT 4 388 | #define TRXDMA_CTRL_VIQ_SHIFT 6 389 | #define TRXDMA_CTRL_BEQ_SHIFT 8 390 | #define TRXDMA_CTRL_BKQ_SHIFT 10 391 | #define TRXDMA_CTRL_MGQ_SHIFT 12 392 | #define TRXDMA_CTRL_HIQ_SHIFT 14 393 | #define TRXDMA_QUEUE_LOW 1 394 | #define TRXDMA_QUEUE_NORMAL 2 395 | #define TRXDMA_QUEUE_HIGH 3 396 | 397 | #define REG_TRXFF_BNDY 0x0114 398 | #define REG_TRXFF_STATUS 0x0118 399 | #define REG_RXFF_PTR 0x011c 400 | #define REG_HIMR 0x0120 401 | #define REG_HISR 0x0124 402 | #define REG_HIMRE 0x0128 403 | #define REG_HISRE 0x012c 404 | #define REG_CPWM 0x012f 405 | #define REG_FWIMR 0x0130 406 | #define REG_FWISR 0x0134 407 | #define REG_FTIMR 0x0138 408 | #define REG_PKTBUF_DBG_CTRL 0x0140 409 | #define REG_PKTBUF_DBG_DATA_L 0x0144 410 | #define REG_PKTBUF_DBG_DATA_H 0x0148 411 | 412 | #define REG_TC0_CTRL 0x0150 413 | #define REG_TC1_CTRL 0x0154 414 | #define REG_TC2_CTRL 0x0158 415 | #define REG_TC3_CTRL 0x015c 416 | #define REG_TC4_CTRL 0x0160 417 | #define REG_TCUNIT_BASE 0x0164 418 | #define REG_MBIST_START 0x0174 419 | #define REG_MBIST_DONE 0x0178 420 | #define REG_MBIST_FAIL 0x017c 421 | /* 8188EU */ 422 | #define REG_32K_CTRL 0x0194 423 | #define REG_C2HEVT_MSG_NORMAL 0x01a0 424 | /* 8192EU/8723BU/8812 */ 425 | #define REG_C2HEVT_CMD_ID_8723B 0x01ae 426 | #define REG_C2HEVT_CLEAR 0x01af 427 | #define REG_C2HEVT_MSG_TEST 0x01b8 428 | #define REG_MCUTST_1 0x01c0 429 | #define REG_FMTHR 0x01c8 430 | #define REG_HMTFR 0x01cc 431 | #define REG_HMBOX_0 0x01d0 432 | #define REG_HMBOX_1 0x01d4 433 | #define REG_HMBOX_2 0x01d8 434 | #define REG_HMBOX_3 0x01dc 435 | 436 | #define REG_LLT_INIT 0x01e0 437 | #define LLT_OP_INACTIVE 0x0 438 | #define LLT_OP_WRITE (0x1 << 30) 439 | #define LLT_OP_READ (0x2 << 30) 440 | #define LLT_OP_MASK (0x3 << 30) 441 | 442 | #define REG_BB_ACCEESS_CTRL 0x01e8 443 | #define REG_BB_ACCESS_DATA 0x01ec 444 | 445 | #define REG_HMBOX_EXT0_8723B 0x01f0 446 | #define REG_HMBOX_EXT1_8723B 0x01f4 447 | #define REG_HMBOX_EXT2_8723B 0x01f8 448 | #define REG_HMBOX_EXT3_8723B 0x01fc 449 | 450 | /* 0x0200 ~ 0x027F TXDMA Configuration */ 451 | #define REG_RQPN 0x0200 452 | #define RQPN_HI_PQ_SHIFT 0 453 | #define RQPN_LO_PQ_SHIFT 8 454 | #define RQPN_PUB_PQ_SHIFT 16 455 | #define RQPN_LOAD BIT(31) 456 | 457 | #define REG_FIFOPAGE 0x0204 458 | #define REG_TDECTRL 0x0208 459 | #define BIT_BCN_VALID BIT(16) 460 | 461 | #define REG_DWBCN0_CTRL_8188F REG_TDECTRL 462 | 463 | #define REG_TXDMA_OFFSET_CHK 0x020c 464 | #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) 465 | #define REG_TXDMA_STATUS 0x0210 466 | #define REG_RQPN_NPQ 0x0214 467 | #define RQPN_NPQ_SHIFT 0 468 | #define RQPN_EPQ_SHIFT 16 469 | 470 | #define REG_AUTO_LLT 0x0224 471 | #define AUTO_LLT_INIT_LLT BIT(16) 472 | 473 | #define REG_DWBCN1_CTRL_8723B 0x0228 474 | #define BIT_SW_BCN_SEL BIT(20) 475 | 476 | /* 0x0280 ~ 0x02FF RXDMA Configuration */ 477 | #define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits 478 | 8-14: USB DMA timeout 479 | 15 : Aggregation enable 480 | Only seems to be used 481 | on 8723bu/8192eu */ 482 | #define RXDMA_USB_AGG_ENABLE BIT(31) 483 | #define REG_RXPKT_NUM 0x0284 484 | #define RXPKT_NUM_RXDMA_IDLE BIT(17) 485 | #define RXPKT_NUM_RW_RELEASE_EN BIT(18) 486 | #define REG_RXDMA_STATUS 0x0288 487 | 488 | /* Presumably only found on newer chips such as 8723bu */ 489 | #define REG_RX_DMA_CTRL_8723B 0x0286 490 | #define REG_RXDMA_PRO_8723B 0x0290 491 | #define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */ 492 | #define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */ 493 | #define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */ 494 | 495 | #define REG_EARLY_MODE_CONTROL_8710B 0x02bc 496 | 497 | #define REG_RF_BB_CMD_ADDR 0x02c0 498 | #define REG_RF_BB_CMD_DATA 0x02c4 499 | 500 | /* spec version 11 */ 501 | /* 0x0400 ~ 0x047F Protocol Configuration */ 502 | /* 8192c, 8192d */ 503 | #define REG_VOQ_INFO 0x0400 504 | #define REG_VIQ_INFO 0x0404 505 | #define REG_BEQ_INFO 0x0408 506 | #define REG_BKQ_INFO 0x040c 507 | /* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ 508 | #define REG_Q0_INFO 0x400 509 | #define REG_Q1_INFO 0x404 510 | #define REG_Q2_INFO 0x408 511 | #define REG_Q3_INFO 0x40c 512 | 513 | #define REG_MGQ_INFO 0x0410 514 | #define REG_HGQ_INFO 0x0414 515 | #define REG_BCNQ_INFO 0x0418 516 | 517 | #define REG_CPU_MGQ_INFORMATION 0x041c 518 | #define REG_FWHW_TXQ_CTRL 0x0420 519 | #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 520 | #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 521 | #define EN_BCNQ_DL BIT(22) 522 | 523 | #define REG_HWSEQ_CTRL 0x0423 524 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 525 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 526 | #define REG_LIFETIME_EN 0x0426 527 | #define REG_MULTI_BCNQ_OFFSET 0x0427 528 | 529 | #define REG_SPEC_SIFS 0x0428 530 | #define SPEC_SIFS_CCK_MASK 0x00ff 531 | #define SPEC_SIFS_CCK_SHIFT 0 532 | #define SPEC_SIFS_OFDM_MASK 0xff00 533 | #define SPEC_SIFS_OFDM_SHIFT 8 534 | 535 | #define REG_RETRY_LIMIT 0x042a 536 | #define RETRY_LIMIT_LONG_SHIFT 0 537 | #define RETRY_LIMIT_LONG_MASK 0x003f 538 | #define RETRY_LIMIT_SHORT_SHIFT 8 539 | #define RETRY_LIMIT_SHORT_MASK 0x3f00 540 | 541 | #define REG_DARFRC 0x0430 542 | #define REG_RARFRC 0x0438 543 | #define REG_RESPONSE_RATE_SET 0x0440 544 | #define RESPONSE_RATE_BITMAP_ALL 0xfffff 545 | #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 546 | #define RESPONSE_RATE_RRSR_INIT_2G 0x15f 547 | #define RESPONSE_RATE_RRSR_INIT_5G 0x150 548 | #define RSR_1M BIT(0) 549 | #define RSR_2M BIT(1) 550 | #define RSR_5_5M BIT(2) 551 | #define RSR_11M BIT(3) 552 | #define RSR_6M BIT(4) 553 | #define RSR_9M BIT(5) 554 | #define RSR_12M BIT(6) 555 | #define RSR_18M BIT(7) 556 | #define RSR_24M BIT(8) 557 | #define RSR_36M BIT(9) 558 | #define RSR_48M BIT(10) 559 | #define RSR_54M BIT(11) 560 | #define RSR_MCS0 BIT(12) 561 | #define RSR_MCS1 BIT(13) 562 | #define RSR_MCS2 BIT(14) 563 | #define RSR_MCS3 BIT(15) 564 | #define RSR_MCS4 BIT(16) 565 | #define RSR_MCS5 BIT(17) 566 | #define RSR_MCS6 BIT(18) 567 | #define RSR_MCS7 BIT(19) 568 | #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 569 | #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 570 | #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 571 | RSR_RSC_LOWER_SUB_CHANNEL) 572 | #define RSR_ACK_SHORT_PREAMBLE BIT(23) 573 | 574 | #define REG_ARFR0 0x0444 575 | #define REG_ARFR1 0x0448 576 | #define REG_ARFR2 0x044c 577 | #define REG_ARFR3 0x0450 578 | #define REG_CCK_CHECK 0x0454 579 | #define BIT_BCN_PORT_SEL BIT(5) 580 | #define REG_AMPDU_MAX_TIME_8723B 0x0456 581 | #define REG_AGGLEN_LMT 0x0458 582 | #define REG_AMPDU_MIN_SPACE 0x045c 583 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 584 | #define REG_FAST_EDCA_CTRL 0x0460 585 | #define REG_RD_RESP_PKT_TH 0x0463 586 | #define REG_INIRTS_RATE_SEL 0x0480 587 | /* 8723bu */ 588 | #define REG_DATA_SUBCHANNEL 0x0483 589 | /* 8723au */ 590 | #define REG_INIDATA_RATE_SEL 0x0484 591 | /* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ 592 | #define REG_MACID_SLEEP_3_8732B 0x0484 593 | #define REG_MACID_SLEEP_1_8732B 0x0488 594 | 595 | #define REG_POWER_STATUS 0x04a4 596 | #define REG_POWER_STAGE1 0x04b4 597 | #define REG_POWER_STAGE2 0x04b8 598 | #define REG_AMPDU_BURST_MODE_8723B 0x04bc 599 | #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 600 | #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 601 | #define REG_STBC_SETTING 0x04c4 602 | #define REG_QUEUE_CTRL 0x04c6 603 | #define REG_HT_SINGLE_AMPDU_8723B 0x04c7 604 | #define HT_SINGLE_AMPDU_ENABLE BIT(7) 605 | #define REG_PROT_MODE_CTRL 0x04c8 606 | #define REG_MAX_AGGR_NUM 0x04ca 607 | #define REG_RTS_MAX_AGGR_NUM 0x04cb 608 | #define REG_BAR_MODE_CTRL 0x04cc 609 | #define REG_RA_TRY_RATE_AGG_LMT 0x04cf 610 | /* MACID_DROP for 8723a */ 611 | #define REG_MACID_DROP_8732A 0x04d0 612 | /* EARLY_MODE_CONTROL 8188e */ 613 | #define REG_EARLY_MODE_CONTROL_8188E 0x04d0 614 | /* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ 615 | #define REG_MACID_SLEEP_2_8732B 0x04d0 616 | #define REG_MACID_SLEEP 0x04d4 617 | #define REG_NQOS_SEQ 0x04dc 618 | #define REG_QOS_SEQ 0x04de 619 | #define REG_NEED_CPU_HANDLE 0x04e0 620 | #define REG_PKT_LOSE_RPT 0x04e1 621 | #define REG_PTCL_ERR_STATUS 0x04e2 622 | #define REG_TX_REPORT_CTRL 0x04ec 623 | #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) 624 | 625 | #define REG_TX_REPORT_TIME 0x04f0 626 | #define REG_DUMMY 0x04fc 627 | 628 | /* 0x0500 ~ 0x05FF EDCA Configuration */ 629 | #define REG_EDCA_VO_PARAM 0x0500 630 | #define REG_EDCA_VI_PARAM 0x0504 631 | #define REG_EDCA_BE_PARAM 0x0508 632 | #define REG_EDCA_BK_PARAM 0x050c 633 | #define EDCA_PARAM_ECW_MIN_SHIFT 8 634 | #define EDCA_PARAM_ECW_MAX_SHIFT 12 635 | #define EDCA_PARAM_TXOP_SHIFT 16 636 | #define REG_BEACON_TCFG 0x0510 637 | #define REG_PIFS 0x0512 638 | #define REG_RDG_PIFS 0x0513 639 | #define REG_SIFS_CCK 0x0514 640 | #define REG_SIFS_OFDM 0x0516 641 | #define REG_TSFTR_SYN_OFFSET 0x0518 642 | #define REG_AGGR_BREAK_TIME 0x051a 643 | #define REG_SLOT 0x051b 644 | #define REG_TX_PTCL_CTRL 0x0520 645 | #define REG_TXPAUSE 0x0522 646 | #define REG_DIS_TXREQ_CLR 0x0523 647 | #define REG_RD_CTRL 0x0524 648 | #define REG_TBTT_PROHIBIT 0x0540 649 | #define REG_RD_NAV_NXT 0x0544 650 | #define REG_NAV_PROT_LEN 0x0546 651 | 652 | #define REG_BEACON_CTRL 0x0550 653 | #define REG_BEACON_CTRL_1 0x0551 654 | #define BEACON_ATIM BIT(0) 655 | #define BEACON_CTRL_MBSSID BIT(1) 656 | #define BEACON_CTRL_TX_BEACON_RPT BIT(2) 657 | #define BEACON_FUNCTION_ENABLE BIT(3) 658 | #define BEACON_DISABLE_TSF_UPDATE BIT(4) 659 | 660 | #define REG_MBID_NUM 0x0552 661 | #define REG_DUAL_TSF_RST 0x0553 662 | #define DUAL_TSF_RESET_TSF0 BIT(0) 663 | #define DUAL_TSF_RESET_TSF1 BIT(1) 664 | #define DUAL_TSF_RESET_P2P BIT(4) 665 | #define DUAL_TSF_TX_OK BIT(5) 666 | 667 | /* The same as REG_MBSSID_BCN_SPACE */ 668 | #define REG_BCN_INTERVAL 0x0554 669 | #define REG_MBSSID_BCN_SPACE 0x0554 670 | 671 | #define REG_DRIVER_EARLY_INT 0x0558 672 | #define DRIVER_EARLY_INT_TIME 5 673 | 674 | #define REG_BEACON_DMA_TIME 0x0559 675 | #define BEACON_DMA_ATIME_INT_TIME 2 676 | 677 | #define REG_ATIMWND 0x055a 678 | #define REG_USTIME_TSF_8723B 0x055c 679 | #define REG_BCN_MAX_ERR 0x055d 680 | #define REG_RXTSF_OFFSET_CCK 0x055e 681 | #define REG_RXTSF_OFFSET_OFDM 0x055f 682 | #define REG_TSFTR 0x0560 683 | #define REG_TSFTR1 0x0568 684 | #define REG_INIT_TSFTR 0x0564 685 | #define REG_ATIMWND_1 0x0570 686 | #define REG_PSTIMER 0x0580 687 | #define REG_TIMER0 0x0584 688 | #define REG_TIMER1 0x0588 689 | #define REG_ACM_HW_CTRL 0x05c0 690 | #define ACM_HW_CTRL_BK BIT(0) 691 | #define ACM_HW_CTRL_BE BIT(1) 692 | #define ACM_HW_CTRL_VI BIT(2) 693 | #define ACM_HW_CTRL_VO BIT(3) 694 | #define REG_ACM_RST_CTRL 0x05c1 695 | #define REG_ACMAVG 0x05c2 696 | #define REG_VO_ADMTIME 0x05c4 697 | #define REG_VI_ADMTIME 0x05c6 698 | #define REG_BE_ADMTIME 0x05c8 699 | #define REG_EDCA_RANDOM_GEN 0x05cc 700 | #define REG_SCH_TXCMD 0x05d0 701 | 702 | /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 703 | #define REG_SCH_TX_CMD 0x05f8 704 | #define REG_FW_RESET_TSF_CNT_1 0x05fc 705 | #define REG_FW_RESET_TSF_CNT_0 0x05fd 706 | #define REG_FW_BCN_DIS_CNT 0x05fe 707 | 708 | /* 0x0600 ~ 0x07FF WMAC Configuration */ 709 | #define REG_APSD_CTRL 0x0600 710 | #define APSD_CTRL_OFF BIT(6) 711 | #define APSD_CTRL_OFF_STATUS BIT(7) 712 | #define REG_BW_OPMODE 0x0603 713 | #define BW_OPMODE_20MHZ BIT(2) 714 | #define BW_OPMODE_5G BIT(1) 715 | #define BW_OPMODE_11J BIT(0) 716 | 717 | #define REG_TCR 0x0604 718 | 719 | /* Receive Configuration Register */ 720 | #define REG_RCR 0x0608 721 | #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 722 | #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 723 | #define RCR_ACCEPT_MCAST BIT(2) 724 | #define RCR_ACCEPT_BCAST BIT(3) 725 | #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 726 | packet */ 727 | #define RCR_ACCEPT_PM BIT(5) /* Accept power management 728 | packet */ 729 | #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 730 | #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 731 | (Rx beacon, probe rsp) */ 732 | #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 733 | #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 734 | #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use 735 | REG_RXFLTMAP2 */ 736 | #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use 737 | REG_RXFLTMAP1 */ 738 | #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use 739 | REG_RXFLTMAP0 */ 740 | #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 741 | #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet 742 | interrupt */ 743 | #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet 744 | interrupt */ 745 | #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ 746 | #define RCR_MFBEN BIT(22) 747 | #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection 748 | function. Search KEYCAM for 749 | each rx packet to check if 750 | LSIGEN bit is set. */ 751 | #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 752 | #define RCR_FORCE_ACK BIT(26) 753 | #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 754 | #define RCR_APPEND_PHYSTAT BIT(28) 755 | #define RCR_APPEND_ICV BIT(29) 756 | #define RCR_APPEND_MIC BIT(30) 757 | #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 758 | 759 | #define REG_RX_PKT_LIMIT 0x060c 760 | #define REG_RX_DLK_TIME 0x060d 761 | #define REG_RX_DRVINFO_SZ 0x060f 762 | 763 | #define REG_MACID 0x0610 764 | #define REG_BSSID 0x0618 765 | #define REG_MAR 0x0620 766 | #define REG_MBIDCAMCFG 0x0628 767 | 768 | #define REG_USTIME_EDCA 0x0638 769 | #define REG_MAC_SPEC_SIFS 0x063a 770 | 771 | /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 772 | /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 773 | #define REG_R2T_SIFS 0x063c 774 | /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 775 | #define REG_T2T_SIFS 0x063e 776 | #define REG_ACKTO 0x0640 777 | #define REG_CTS2TO 0x0641 778 | #define REG_EIFS 0x0642 779 | 780 | /* WMA, BA, CCX */ 781 | #define REG_NAV_CTRL 0x0650 782 | /* In units of 128us */ 783 | #define REG_NAV_UPPER 0x0652 784 | #define NAV_UPPER_UNIT 128 785 | 786 | #define REG_BACAMCMD 0x0654 787 | #define REG_BACAMCONTENT 0x0658 788 | #define REG_LBDLY 0x0660 789 | #define REG_FWDLY 0x0661 790 | #define REG_RXERR_RPT 0x0664 791 | #define REG_WMAC_TRXPTCL_CTL 0x0668 792 | #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) 793 | #define WMAC_TRXPTCL_CTL_BW_20 0 794 | #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) 795 | #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) 796 | 797 | /* Security */ 798 | #define REG_CAM_CMD 0x0670 799 | #define CAM_CMD_POLLING BIT(31) 800 | #define CAM_CMD_WRITE BIT(16) 801 | #define CAM_CMD_KEY_SHIFT 3 802 | #define REG_CAM_WRITE 0x0674 803 | #define CAM_WRITE_VALID BIT(15) 804 | #define REG_CAM_READ 0x0678 805 | #define REG_CAM_DEBUG 0x067c 806 | #define REG_SECURITY_CFG 0x0680 807 | #define SEC_CFG_TX_USE_DEFKEY BIT(0) 808 | #define SEC_CFG_RX_USE_DEFKEY BIT(1) 809 | #define SEC_CFG_TX_SEC_ENABLE BIT(2) 810 | #define SEC_CFG_RX_SEC_ENABLE BIT(3) 811 | #define SEC_CFG_SKBYA2 BIT(4) 812 | #define SEC_CFG_NO_SKMC BIT(5) 813 | #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 814 | #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 815 | 816 | /* Power */ 817 | #define REG_WOW_CTRL 0x0690 818 | #define REG_PSSTATUS 0x0691 819 | #define REG_PS_RX_INFO 0x0692 820 | #define REG_LPNAV_CTRL 0x0694 821 | #define REG_WKFMCAM_CMD 0x0698 822 | #define REG_WKFMCAM_RWD 0x069c 823 | 824 | /* 825 | * RX Filters: each bit corresponds to the numerical value of the subtype. 826 | * If it is set the subtype frame type is passed. The filter is only used when 827 | * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit 828 | * in the RCR are low. 829 | * 830 | * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set 831 | * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. 832 | */ 833 | #define REG_RXFLTMAP0 0x06a0 /* Management frames */ 834 | #define REG_RXFLTMAP1 0x06a2 /* Control frames */ 835 | #define REG_RXFLTMAP2 0x06a4 /* Data frames */ 836 | 837 | #define REG_BCN_PSR_RPT 0x06a8 838 | #define REG_CALB32K_CTRL 0x06ac 839 | #define REG_PKT_MON_CTRL 0x06b4 840 | #define REG_BT_COEX_TABLE1 0x06c0 841 | #define REG_BT_COEX_TABLE2 0x06c4 842 | #define REG_BT_COEX_TABLE3 0x06c8 843 | #define REG_BT_COEX_TABLE4 0x06cc 844 | #define REG_WMAC_RESP_TXINFO 0x06d8 845 | 846 | #define REG_MACID1 0x0700 847 | #define REG_BSSID1 0x0708 848 | 849 | /* 850 | * This seems to be 8723bu specific 851 | */ 852 | #define REG_BT_CONTROL_8723BU 0x0764 853 | #define BT_CONTROL_BT_GRANT BIT(12) 854 | 855 | #define REG_PORT_CONTROL_8710B 0x076d 856 | #define REG_WLAN_ACT_CONTROL_8723B 0x076e 857 | 858 | #define REG_FPGA0_RF_MODE 0x0800 859 | #define FPGA_RF_MODE BIT(0) 860 | #define FPGA_RF_MODE_JAPAN BIT(1) 861 | #define FPGA_RF_MODE_CCK BIT(24) 862 | #define FPGA_RF_MODE_OFDM BIT(25) 863 | 864 | #define REG_FPGA0_TX_INFO 0x0804 865 | #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) 866 | #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) 867 | #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) 868 | #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) 869 | #define REG_FPGA0_PSD_FUNC 0x0808 870 | #define REG_FPGA0_TX_GAIN 0x080c 871 | #define REG_FPGA0_RF_TIMING1 0x0810 872 | #define REG_FPGA0_RF_TIMING2 0x0814 873 | #define REG_FPGA0_POWER_SAVE 0x0818 874 | #define FPGA0_PS_LOWER_CHANNEL BIT(26) 875 | #define FPGA0_PS_UPPER_CHANNEL BIT(27) 876 | 877 | #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 878 | #define FPGA0_HSSI_PARM1_PI BIT(8) 879 | #define REG_FPGA0_XA_HSSI_PARM2 0x0824 880 | #define REG_FPGA0_XB_HSSI_PARM1 0x0828 881 | #define REG_FPGA0_XB_HSSI_PARM2 0x082c 882 | #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 883 | #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 884 | #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 885 | #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 886 | #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 887 | #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 888 | 889 | #define REG_TX_AGC_B_RATE18_06 0x0830 890 | #define REG_TX_AGC_B_RATE54_24 0x0834 891 | #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 892 | #define REG_TX_AGC_B_MCS03_MCS00 0x083c 893 | 894 | #define REG_FPGA0_XA_LSSI_PARM 0x0840 895 | #define REG_FPGA0_XB_LSSI_PARM 0x0844 896 | #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 897 | #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 898 | #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 899 | 900 | #define REG_TX_AGC_B_MCS07_MCS04 0x0848 901 | #define REG_TX_AGC_B_MCS11_MCS08 0x084c 902 | 903 | #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 904 | 905 | #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 906 | #define REG_FPGA0_XB_RF_INT_OE 0x0864 907 | #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 908 | #define FPGA0_INT_OE_ANTENNA_A BIT(8) 909 | #define FPGA0_INT_OE_ANTENNA_B BIT(9) 910 | #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 911 | FPGA0_INT_OE_ANTENNA_B) 912 | 913 | #define REG_TX_AGC_B_MCS15_MCS12 0x0868 914 | #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 915 | 916 | #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 917 | #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 918 | #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 919 | #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 920 | #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 921 | #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 922 | #define FPGA0_RF_3WIRE_DATA BIT(0) 923 | #define FPGA0_RF_3WIRE_CLOC BIT(1) 924 | #define FPGA0_RF_3WIRE_LOAD BIT(2) 925 | #define FPGA0_RF_3WIRE_RW BIT(3) 926 | #define FPGA0_RF_3WIRE_MASK 0xf 927 | #define FPGA0_RF_RFENV BIT(4) 928 | #define FPGA0_RF_TRSW BIT(5) /* Useless now */ 929 | #define FPGA0_RF_TRSWB BIT(6) 930 | #define FPGA0_RF_ANTSW BIT(8) 931 | #define FPGA0_RF_ANTSWB BIT(9) 932 | #define FPGA0_RF_PAPE BIT(10) 933 | #define FPGA0_RF_PAPE5G BIT(11) 934 | #define FPGA0_RF_BD_CTRL_SHIFT 16 935 | 936 | #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 937 | #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 938 | #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 939 | #define REG_FPGA0_XCD_RF_PARM 0x087c 940 | #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 941 | #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 942 | #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 943 | #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 944 | #define FPGA0_RF_PARM_CLK_GATE BIT(31) 945 | 946 | #define REG_FPGA0_ANALOG1 0x0880 947 | #define REG_FPGA0_ANALOG2 0x0884 948 | #define FPGA0_ANALOG2_20MHZ BIT(10) 949 | #define REG_FPGA0_ANALOG3 0x0888 950 | #define REG_FPGA0_ANALOG4 0x088c 951 | 952 | #define REG_NHM_TH9_TH10_8723B 0x0890 953 | #define REG_NHM_TIMER_8723B 0x0894 954 | #define REG_NHM_TH3_TO_TH0_8723B 0x0898 955 | #define REG_NHM_TH7_TO_TH4_8723B 0x089c 956 | 957 | #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 958 | #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 959 | #define REG_FPGA0_PSD_REPORT 0x08b4 960 | #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 961 | #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 962 | 963 | #define REG_FPGA1_RF_MODE 0x0900 964 | 965 | #define REG_FPGA1_TX_INFO 0x090c 966 | #define FPGA1_TX_ANT_MASK 0x0000000f 967 | #define FPGA1_TX_ANT_L_MASK 0x000000f0 968 | #define FPGA1_TX_ANT_NON_HT_MASK 0x00000f00 969 | #define FPGA1_TX_ANT_HT1_MASK 0x0000f000 970 | #define FPGA1_TX_ANT_HT2_MASK 0x000f0000 971 | #define FPGA1_TX_ANT_HT_S1_MASK 0x00f00000 972 | #define FPGA1_TX_ANT_NON_HT_S1_MASK 0x0f000000 973 | #define FPGA1_TX_OFDM_TXSC_MASK 0x30000000 974 | 975 | #define REG_ANT_MAPPING1 0x0914 976 | #define REG_DPDT_CTRL 0x092c /* 8723BU */ 977 | #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ 978 | #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ 979 | #define REG_RFE_BUFFER 0x0944 /* 8723BU */ 980 | #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ 981 | #define REG_OFDM_RX_DFIR 0x954 982 | 983 | #define REG_CCK0_SYSTEM 0x0a00 984 | #define CCK0_SIDEBAND BIT(4) 985 | 986 | #define REG_CCK0_AFE_SETTING 0x0a04 987 | #define CCK0_AFE_RX_MASK 0x0f000000 988 | #define CCK0_AFE_TX_MASK 0xf0000000 989 | #define CCK0_AFE_RX_ANT_A 0 990 | #define CCK0_AFE_RX_ANT_B BIT(26) 991 | #define CCK0_AFE_RX_ANT_C BIT(27) 992 | #define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27)) 993 | #define CCK0_AFE_RX_ANT_OPTION_A 0 994 | #define CCK0_AFE_RX_ANT_OPTION_B BIT(24) 995 | #define CCK0_AFE_RX_ANT_OPTION_C BIT(25) 996 | #define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25)) 997 | #define CCK0_AFE_TX_ANT_A BIT(31) 998 | #define CCK0_AFE_TX_ANT_B BIT(30) 999 | 1000 | #define REG_CCK_ANTDIV_PARA2 0x0a04 1001 | #define REG_BB_POWER_SAVE4 0x0a74 1002 | 1003 | /* 8188eu */ 1004 | #define REG_LNA_SWITCH 0x0b2c 1005 | #define LNA_SWITCH_DISABLE_CSCG BIT(22) 1006 | #define LNA_SWITCH_OUTPUT_CG BIT(31) 1007 | 1008 | #define REG_CCK_PD_THRESH 0x0a0a 1009 | #define CCK_PD_TYPE1_LV0_TH 0x40 1010 | #define CCK_PD_TYPE1_LV1_TH 0x83 1011 | #define CCK_PD_TYPE1_LV2_TH 0xcd 1012 | #define CCK_PD_TYPE1_LV3_TH 0xdd 1013 | #define CCK_PD_TYPE1_LV4_TH 0xed 1014 | 1015 | #define REG_CCK0_TX_FILTER1 0x0a20 1016 | #define REG_CCK0_TX_FILTER2 0x0a24 1017 | #define REG_CCK0_DEBUG_PORT 0x0a28 /* debug port and Tx filter3 */ 1018 | #define REG_AGC_RPT 0xa80 1019 | #define AGC_RPT_CCK BIT(7) 1020 | #define REG_CCK0_TX_FILTER3 0x0aac 1021 | 1022 | #define REG_CONFIG_ANT_A 0x0b68 1023 | #define REG_CONFIG_ANT_B 0x0b6c 1024 | 1025 | #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 1026 | #define OFDM_RF_PATH_RX_MASK 0x0f 1027 | #define OFDM_RF_PATH_RX_A BIT(0) 1028 | #define OFDM_RF_PATH_RX_B BIT(1) 1029 | #define OFDM_RF_PATH_RX_C BIT(2) 1030 | #define OFDM_RF_PATH_RX_D BIT(3) 1031 | #define OFDM_RF_PATH_TX_MASK 0xf0 1032 | #define OFDM_RF_PATH_TX_A BIT(4) 1033 | #define OFDM_RF_PATH_TX_B BIT(5) 1034 | #define OFDM_RF_PATH_TX_C BIT(6) 1035 | #define OFDM_RF_PATH_TX_D BIT(7) 1036 | 1037 | #define REG_OFDM0_TR_MUX_PAR 0x0c08 1038 | 1039 | #define REG_OFDM0_FA_RSTC 0x0c0c 1040 | 1041 | #define REG_OFDM0_XA_RX_AFE 0x0c10 1042 | #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 1043 | #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 1044 | 1045 | #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 1046 | 1047 | #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 1048 | #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) 1049 | 1050 | #define REG_OFDM0_XA_AGC_CORE1 0x0c50 1051 | #define REG_OFDM0_XA_AGC_CORE2 0x0c54 1052 | #define REG_OFDM0_XB_AGC_CORE1 0x0c58 1053 | #define REG_OFDM0_XB_AGC_CORE2 0x0c5c 1054 | #define REG_OFDM0_XC_AGC_CORE1 0x0c60 1055 | #define REG_OFDM0_XC_AGC_CORE2 0x0c64 1056 | #define REG_OFDM0_XD_AGC_CORE1 0x0c68 1057 | #define REG_OFDM0_XD_AGC_CORE2 0x0c6c 1058 | #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 1059 | 1060 | #define REG_OFDM0_AGC_PARM1 0x0c70 1061 | 1062 | #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 1063 | 1064 | #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 1065 | #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 1066 | #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 1067 | #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 1068 | 1069 | #define REG_OFDM0_XC_TX_AFE 0x0c94 1070 | #define REG_OFDM0_XD_TX_AFE 0x0c9c 1071 | 1072 | #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 1073 | 1074 | /* 8188eu */ 1075 | #define REG_ANTDIV_PARA1 0x0ca4 1076 | 1077 | /* 8723bu */ 1078 | #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 1079 | 1080 | #define REG_OFDM1_LSTF 0x0d00 1081 | #define OFDM_LSTF_PRIME_CH_LOW BIT(10) 1082 | #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 1083 | #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 1084 | OFDM_LSTF_PRIME_CH_HIGH) 1085 | #define OFDM_LSTF_CONTINUE_TX BIT(28) 1086 | #define OFDM_LSTF_SINGLE_CARRIER BIT(29) 1087 | #define OFDM_LSTF_SINGLE_TONE BIT(30) 1088 | #define OFDM_LSTF_MASK 0x70000000 1089 | 1090 | #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 1091 | #define REG_OFDM1_CFO_TRACKING 0x0d2c 1092 | #define CFO_TRACKING_ATC_STATUS BIT(11) 1093 | #define REG_OFDM1_CSI_FIX_MASK1 0x0d40 1094 | #define REG_OFDM1_CSI_FIX_MASK2 0x0d44 1095 | 1096 | #define REG_TX_AGC_A_RATE18_06 0x0e00 1097 | #define REG_TX_AGC_A_RATE54_24 0x0e04 1098 | #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 1099 | #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 1100 | #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 1101 | #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 1102 | #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 1103 | 1104 | #define REG_FPGA0_IQK 0x0e28 1105 | 1106 | #define REG_TX_IQK_TONE_A 0x0e30 1107 | #define REG_RX_IQK_TONE_A 0x0e34 1108 | #define REG_TX_IQK_PI_A 0x0e38 1109 | #define REG_RX_IQK_PI_A 0x0e3c 1110 | 1111 | #define REG_TX_IQK 0x0e40 1112 | #define REG_RX_IQK 0x0e44 1113 | #define REG_IQK_AGC_PTS 0x0e48 1114 | #define REG_IQK_AGC_RSP 0x0e4c 1115 | #define REG_TX_IQK_TONE_B 0x0e50 1116 | #define REG_RX_IQK_TONE_B 0x0e54 1117 | #define REG_TX_IQK_PI_B 0x0e58 1118 | #define REG_RX_IQK_PI_B 0x0e5c 1119 | #define REG_IQK_AGC_CONT 0x0e60 1120 | 1121 | #define REG_BLUETOOTH 0x0e6c 1122 | #define REG_RX_WAIT_CCA 0x0e70 1123 | #define REG_TX_CCK_RFON 0x0e74 1124 | #define REG_TX_CCK_BBON 0x0e78 1125 | #define REG_TX_OFDM_RFON 0x0e7c 1126 | #define REG_TX_OFDM_BBON 0x0e80 1127 | #define REG_TX_TO_RX 0x0e84 1128 | #define REG_TX_TO_TX 0x0e88 1129 | #define REG_RX_CCK 0x0e8c 1130 | 1131 | #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 1132 | #define REG_TX_POWER_AFTER_IQK_A 0x0e9c 1133 | 1134 | #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 1135 | #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 1136 | #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 1137 | #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 1138 | 1139 | #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 1140 | #define REG_TX_POWER_AFTER_IQK_B 0x0ebc 1141 | 1142 | #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 1143 | #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 1144 | #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 1145 | #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 1146 | 1147 | #define REG_RX_OFDM 0x0ed0 1148 | #define REG_RX_WAIT_RIFS 0x0ed4 1149 | #define REG_RX_TO_RX 0x0ed8 1150 | #define REG_STANDBY 0x0edc 1151 | #define REG_SLEEP 0x0ee0 1152 | #define REG_PMPD_ANAEN 0x0eec 1153 | 1154 | #define REG_FW_START_ADDRESS 0x1000 1155 | 1156 | #define REG_USB_INFO 0xfe17 1157 | #define REG_USB_HIMR 0xfe38 1158 | #define USB_HIMR_TIMEOUT2 BIT(31) 1159 | #define USB_HIMR_TIMEOUT1 BIT(30) 1160 | #define USB_HIMR_PSTIMEOUT BIT(29) 1161 | #define USB_HIMR_GTINT4 BIT(28) 1162 | #define USB_HIMR_GTINT3 BIT(27) 1163 | #define USB_HIMR_TXBCNERR BIT(26) 1164 | #define USB_HIMR_TXBCNOK BIT(25) 1165 | #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 1166 | #define USB_HIMR_BCNDMAINT3 BIT(23) 1167 | #define USB_HIMR_BCNDMAINT2 BIT(22) 1168 | #define USB_HIMR_BCNDMAINT1 BIT(21) 1169 | #define USB_HIMR_BCNDMAINT0 BIT(20) 1170 | #define USB_HIMR_BCNDOK3 BIT(19) 1171 | #define USB_HIMR_BCNDOK2 BIT(18) 1172 | #define USB_HIMR_BCNDOK1 BIT(17) 1173 | #define USB_HIMR_BCNDOK0 BIT(16) 1174 | #define USB_HIMR_HSISR_IND BIT(15) 1175 | #define USB_HIMR_BCNDMAINT_E BIT(14) 1176 | /* RSVD BIT(13) */ 1177 | #define USB_HIMR_CTW_END BIT(12) 1178 | /* RSVD BIT(11) */ 1179 | #define USB_HIMR_C2HCMD BIT(10) 1180 | #define USB_HIMR_CPWM2 BIT(9) 1181 | #define USB_HIMR_CPWM BIT(8) 1182 | #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 1183 | Interrupt */ 1184 | #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 1185 | Interrupt */ 1186 | #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 1187 | #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 1188 | #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 1189 | #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 1190 | #define USB_HIMR_RDU BIT(1) /* Receive Descriptor 1191 | Unavailable */ 1192 | #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 1193 | 1194 | #define REG_USB_ACCESS_TIMEOUT 0xfe4c 1195 | 1196 | #define REG_USB_SPECIAL_OPTION 0xfe55 1197 | #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ 1198 | #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to 1199 | deliver interrupt packet. 1200 | 0: Use int, 1: use bulk */ 1201 | #define REG_USB_HRPWM 0xfe58 1202 | #define REG_USB_DMA_AGG_TO 0xfe5b 1203 | #define REG_USB_AGG_TIMEOUT 0xfe5c 1204 | #define REG_USB_AGG_THRESH 0xfe5d 1205 | 1206 | #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 1207 | #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 1208 | #define REG_NORMAL_SIE_OPTIONAL 0xfe64 1209 | #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 1210 | #define REG_NORMAL_SIE_EP_TX 0xfe66 1211 | #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 1212 | #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 1213 | #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 1214 | 1215 | #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 1216 | #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 1217 | #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 1218 | #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 1219 | #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 1220 | 1221 | /* 1222 | * 8710B register addresses between 0x00 and 0xff must have 0x8000 1223 | * added to them. We take care of that in the rtl8xxxu_read{8,16,32} 1224 | * and rtl8xxxu_write{8,16,32} functions. 1225 | */ 1226 | #define REG_SYS_FUNC_8710B 0x0004 1227 | #define REG_AFE_CTRL_8710B 0x0050 1228 | #define REG_WL_RF_PSS_8710B 0x005c 1229 | #define REG_EFUSE_INDIRECT_CTRL_8710B 0x006c 1230 | #define NORMAL_REG_READ_OFFSET 0x83000000 1231 | #define NORMAL_REG_WRITE_OFFSET 0x84000000 1232 | #define EFUSE_READ_OFFSET 0x85000000 1233 | #define EFUSE_WRITE_OFFSET 0x86000000 1234 | #define REG_HIMR0_8710B 0x0080 1235 | #define REG_HISR0_8710B 0x0084 1236 | /* 1237 | * 8710B uses this instead of REG_MCU_FW_DL, but at least bits 1238 | * 0-7 have the same meaning. 1239 | */ 1240 | #define REG_8051FW_CTRL_V1_8710B 0x0090 1241 | #define REG_USB_HOST_INDIRECT_DATA_8710B 0x009c 1242 | #define REG_WL_STATUS_8710B 0x00f0 1243 | #define REG_USB_HOST_INDIRECT_ADDR_8710B 0x00f8 1244 | 1245 | /* 1246 | * 8710B registers which must be accessed through rtl8710b_read_syson_reg 1247 | * and rtl8710b_write_syson_reg. 1248 | */ 1249 | #define SYSON_REG_BASE_ADDR_8710B 0x40000000 1250 | #define REG_SYS_XTAL_CTRL0_8710B 0x060 1251 | #define REG_SYS_EEPROM_CTRL0_8710B 0x0e0 1252 | #define REG_SYS_SYSTEM_CFG0_8710B 0x1f0 1253 | #define REG_SYS_SYSTEM_CFG1_8710B 0x1f4 1254 | #define REG_SYS_SYSTEM_CFG2_8710B 0x1f8 1255 | 1256 | /* RF6052 registers */ 1257 | #define RF6052_REG_AC 0x00 1258 | #define RF6052_REG_IQADJ_G1 0x01 1259 | #define RF6052_REG_IQADJ_G2 0x02 1260 | #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 1261 | #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 1262 | #define RF6052_REG_POW_TRSW 0x05 1263 | #define RF6052_REG_GAIN_RX 0x06 1264 | #define RF6052_REG_GAIN_TX 0x07 1265 | #define RF6052_REG_TXM_IDAC 0x08 1266 | #define RF6052_REG_IPA_G 0x09 1267 | #define RF6052_REG_TXBIAS_G 0x0a 1268 | #define RF6052_REG_TXPA_AG 0x0b 1269 | #define RF6052_REG_IPA_A 0x0c 1270 | #define RF6052_REG_TXBIAS_A 0x0d 1271 | #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 1272 | #define RF6052_REG_BS_IQGEN 0x0f 1273 | #define RF6052_REG_MODE1 0x10 1274 | #define RF6052_REG_MODE2 0x11 1275 | #define RF6052_REG_RX_AGC_HP 0x12 1276 | #define RF6052_REG_TX_AGC 0x13 1277 | #define RF6052_REG_BIAS 0x14 1278 | #define RF6052_REG_IPA 0x15 1279 | #define RF6052_REG_TXBIAS 0x16 1280 | #define RF6052_REG_POW_ABILITY 0x17 1281 | #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 1282 | #define MODE_AG_CHANNEL_MASK 0x3ff 1283 | #define MODE_AG_CHANNEL_20MHZ BIT(10) 1284 | #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) 1285 | #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) 1286 | #define MODE_AG_BW_40MHZ_8723B BIT(10) 1287 | #define MODE_AG_BW_80MHZ_8723B 0 1288 | 1289 | #define RF6052_REG_TOP 0x19 1290 | #define RF6052_REG_RX_G1 0x1a 1291 | #define RF6052_REG_RX_G2 0x1b 1292 | #define RF6052_REG_RX_BB2 0x1c 1293 | #define RF6052_REG_RX_BB1 0x1d 1294 | #define RF6052_REG_RCK1 0x1e 1295 | #define RF6052_REG_RCK2 0x1f 1296 | #define RF6052_REG_TX_G1 0x20 1297 | #define RF6052_REG_TX_G2 0x21 1298 | #define RF6052_REG_TX_G3 0x22 1299 | #define RF6052_REG_TX_BB1 0x23 1300 | #define RF6052_REG_T_METER 0x24 1301 | #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 1302 | #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 1303 | #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 1304 | #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 1305 | #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 1306 | #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 1307 | #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 1308 | #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 1309 | 1310 | #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 1311 | 1312 | #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 1313 | #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 1314 | #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 1315 | 1316 | /* 1317 | * NextGen regs: 8723BU 1318 | */ 1319 | #define RF6052_REG_T_METER_8723B 0x42 1320 | #define RF6052_REG_UNKNOWN_43 0x43 1321 | #define RF6052_REG_UNKNOWN_55 0x55 1322 | #define RF6052_REG_UNKNOWN_56 0x56 1323 | #define RF6052_REG_RXG_MIX_SWBW 0x87 1324 | #define RF6052_REG_S0S1 0xb0 1325 | #define RF6052_REG_UNKNOWN_DF 0xdf 1326 | #define RF6052_REG_UNKNOWN_ED 0xed 1327 | #define RF6052_REG_WE_LUT 0xef 1328 | --------------------------------------------------------------------------------