├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── sim └── Makefile ├── src ├── rtl │ ├── 32saif.tar.gz │ ├── MatrixInputQueue │ │ ├── GrayCounter.v │ │ ├── MatrixInput.v │ │ ├── MatrixInput_sram.v │ │ ├── aFifo.v │ │ ├── aFifo_256x8.v │ │ ├── mux_DRAMorlocal.v │ │ ├── saed32sram.v │ │ ├── test_afifo.v │ │ └── test_afifo_sram.v │ ├── MultiplyAccumulateCell.v │ ├── MultiplyAccumulateMatrix.v │ ├── ShiftRegister.v │ ├── SystolicDataSetupCol.v │ ├── SystolicDataSetupRow.v │ ├── Top.sv │ ├── TopTest.sv │ ├── XdataSetup.v │ ├── fsdb │ │ └── features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv_1.fsdb │ ├── novas.fsdb │ ├── tb_Top.v │ ├── test.sig │ ├── test.svh │ ├── top.v │ └── untar.README ├── tests │ ├── Makefile │ ├── MultiplyAccumulateCell_tb.py │ ├── tb_SystolicDataSetup.v │ ├── tb_SystolicDataSetupCol.v │ └── verilog │ │ ├── run │ │ ├── tb_ShiftRegister │ │ ├── INCA_libs │ │ │ ├── .history.lock │ │ │ ├── history │ │ │ ├── irun.lnx8664.15.22.nc │ │ │ │ ├── .nclib.lock │ │ │ │ ├── .ncrun.lock │ │ │ │ ├── .ncv.lock │ │ │ │ ├── .timestamp.ts │ │ │ │ ├── OVMHOME │ │ │ │ ├── UVMHOME │ │ │ │ ├── bind.lst.lnx8664 │ │ │ │ ├── cds.lib │ │ │ │ ├── cdsrun.lib │ │ │ │ ├── files.ts │ │ │ │ ├── hdl.var │ │ │ │ ├── hdlrun.var │ │ │ │ ├── ncelab.args │ │ │ │ ├── ncelab.env │ │ │ │ ├── ncelab.hrd │ │ │ │ ├── ncsim.args │ │ │ │ ├── ncsim.env │ │ │ │ ├── ncsim_restart.args │ │ │ │ ├── ncsim_restart.env │ │ │ │ ├── ncverilog.args │ │ │ │ ├── ncvlog.args │ │ │ │ ├── ncvlog.env │ │ │ │ ├── ncvlog.files │ │ │ │ ├── ncvlog.hrd │ │ │ │ ├── scv-asramkum01.csg.apple.com_11846_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_11846_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_12119_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_12119_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_4362_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_4362_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_7225_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_7225_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_8359_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_8359_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_8830_cdsrun.lib │ │ │ │ └── scv-asramkum01.csg.apple.com_8830_hdlrun.var │ │ │ ├── snap.nc │ │ │ │ ├── .nclib.lock │ │ │ │ ├── .ncrun.lock │ │ │ │ ├── .ncv.lock │ │ │ │ ├── .timestamp.ts │ │ │ │ ├── OVMHOME │ │ │ │ ├── UVMHOME │ │ │ │ ├── bind.lst.lnx8664 │ │ │ │ ├── cds.lib │ │ │ │ ├── cdsrun.lib │ │ │ │ ├── files.ts │ │ │ │ ├── hdl.var │ │ │ │ ├── hdlrun.var │ │ │ │ ├── ncelab.args │ │ │ │ ├── ncelab.env │ │ │ │ ├── ncelab.hrd │ │ │ │ ├── ncsim.args │ │ │ │ ├── ncsim.env │ │ │ │ ├── ncsim_restart.args │ │ │ │ ├── ncsim_restart.env │ │ │ │ ├── ncverilog.args │ │ │ │ ├── ncvlog.args │ │ │ │ ├── ncvlog.env │ │ │ │ ├── ncvlog.files │ │ │ │ ├── ncvlog.hrd │ │ │ │ ├── scv-asramkum01.csg.apple.com_11846_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_11846_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_12119_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_12119_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_4362_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_4362_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_7225_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_7225_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_8359_cdsrun.lib │ │ │ │ ├── scv-asramkum01.csg.apple.com_8359_hdlrun.var │ │ │ │ ├── scv-asramkum01.csg.apple.com_8830_cdsrun.lib │ │ │ │ └── scv-asramkum01.csg.apple.com_8830_hdlrun.var │ │ │ └── worklib │ │ │ │ ├── .cdsvmod │ │ │ │ ├── .inca.db.061.lnx8664 │ │ │ │ ├── cdsinfo.tag │ │ │ │ └── inca.lnx8664.061.pak │ │ ├── ShiftRegister.vcd │ │ ├── include.f │ │ ├── ncverilog.history │ │ ├── sx_saved.sx │ │ ├── tb_ShiftRegister.v │ │ └── tb_ShiftRegister.v~ │ │ ├── tb_SystolicDataSetup.v~ │ │ ├── tb_SystolicDataSetup │ │ ├── include.f │ │ └── tb_SystolicDataSetup.v │ │ ├── tb_SystolicDataSetupCol │ │ ├── include.colf │ │ └── tb_SystolicDataSetupCol.v │ │ └── tb_XdataSetup │ │ ├── INCA_libs │ │ ├── .history.lock │ │ ├── history │ │ ├── irun.lnx8664.15.22.nc │ │ │ ├── .nclib.lock │ │ │ ├── .ncrun.lock │ │ │ ├── .ncv.lock │ │ │ ├── .timestamp.ts │ │ │ ├── OVMHOME │ │ │ ├── UVMHOME │ │ │ ├── bind.lst.lnx8664 │ │ │ ├── cds.lib │ │ │ ├── cdsrun.lib │ │ │ ├── files.ts │ │ │ ├── hdl.var │ │ │ ├── hdlrun.var │ │ │ ├── ncelab.args │ │ │ ├── ncelab.env │ │ │ ├── ncelab.hrd │ │ │ ├── ncsim.args │ │ │ ├── ncsim.env │ │ │ ├── ncsim_restart.args │ │ │ ├── ncsim_restart.env │ │ │ ├── ncverilog.args │ │ │ ├── ncvlog.args │ │ │ ├── ncvlog.env │ │ │ ├── ncvlog.files │ │ │ ├── ncvlog.hrd │ │ │ ├── scv-asramkum01.csg.apple.com_5315_cdsrun.lib │ │ │ └── scv-asramkum01.csg.apple.com_5315_hdlrun.var │ │ ├── snap.nc │ │ │ ├── .nclib.lock │ │ │ ├── .ncrun.lock │ │ │ ├── .ncv.lock │ │ │ ├── .timestamp.ts │ │ │ ├── OVMHOME │ │ │ ├── UVMHOME │ │ │ ├── bind.lst.lnx8664 │ │ │ ├── cds.lib │ │ │ ├── cdsrun.lib │ │ │ ├── files.ts │ │ │ ├── hdl.var │ │ │ ├── hdlrun.var │ │ │ ├── ncelab.args │ │ │ ├── ncelab.env │ │ │ ├── ncelab.hrd │ │ │ ├── ncsim.args │ │ │ ├── ncsim.env │ │ │ ├── ncsim_restart.args │ │ │ ├── ncsim_restart.env │ │ │ ├── ncverilog.args │ │ │ ├── ncvlog.args │ │ │ ├── ncvlog.env │ │ │ ├── ncvlog.files │ │ │ ├── ncvlog.hrd │ │ │ ├── scv-asramkum01.csg.apple.com_5315_cdsrun.lib │ │ │ └── scv-asramkum01.csg.apple.com_5315_hdlrun.var │ │ └── worklib │ │ │ ├── .cdsvmod │ │ │ ├── .inca.db.061.lnx8664 │ │ │ ├── cdsinfo.tag │ │ │ └── inca.lnx8664.061.pak │ │ ├── include.f │ │ └── ncverilog.history └── tf │ ├── collect_model_data.py │ ├── keras_profiling.py │ └── test_quantization.py └── syn ├── scripts ├── common │ ├── common_setup.tcl │ ├── dont_use.tcl │ ├── rtl.tcl │ └── saed32.tcl └── dc │ ├── dc.tcl │ ├── dc_setup.tcl │ ├── dc_setup_filenames.tcl │ ├── dc_top.tcl │ └── snpsll_hpdu_synth.tcl └── sdc └── SystolicArray.sdc /.gitignore: -------------------------------------------------------------------------------- 1 | # Byte-compiled / optimized / DLL files 2 | __pycache__/ 3 | *.py[cod] 4 | *$py.class 5 | 6 | # C extensions 7 | *.so 8 | 9 | # Distribution / packaging 10 | .Python 11 | env/ 12 | build/ 13 | develop-eggs/ 14 | dist/ 15 | downloads/ 16 | eggs/ 17 | .eggs/ 18 | lib/ 19 | lib64/ 20 | parts/ 21 | sdist/ 22 | var/ 23 | *.egg-info/ 24 | .installed.cfg 25 | *.egg 26 | 27 | # PyInstaller 28 | # Usually these files are written by a python script from a template 29 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 30 | *.manifest 31 | *.spec 32 | 33 | # Installer logs 34 | pip-log.txt 35 | pip-delete-this-directory.txt 36 | 37 | # Unit test / coverage reports 38 | htmlcov/ 39 | .tox/ 40 | .coverage 41 | .coverage.* 42 | .cache 43 | nosetests.xml 44 | coverage.xml 45 | *,cover 46 | .hypothesis/ 47 | 48 | # Translations 49 | *.mo 50 | *.pot 51 | 52 | # Django stuff: 53 | *.log 54 | local_settings.py 55 | 56 | # Flask stuff: 57 | instance/ 58 | .webassets-cache 59 | 60 | # Scrapy stuff: 61 | .scrapy 62 | 63 | # Sphinx documentation 64 | docs/_build/ 65 | 66 | # PyBuilder 67 | target/ 68 | 69 | # IPython Notebook 70 | .ipynb_checkpoints 71 | 72 | # pyenv 73 | .python-version 74 | 75 | # celery beat schedule file 76 | celerybeat-schedule 77 | 78 | # dotenv 79 | .env 80 | 81 | # virtualenv 82 | venv/ 83 | ENV/ 84 | 85 | # Spyder project settings 86 | .spyderproject 87 | 88 | # Rope project settings 89 | .ropeproject 90 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "cocotb"] 2 | path = cocotb 3 | url = https://github.com/potentialventures/cocotb 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Kevin K. 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Convolutional Neural Network (CNN) acclerator in Verilog 2 | --- 3 | 4 | Authors: Kevin Kiningham, Michael Graczyk, Athul Ramkumar 5 | 6 | Setup 7 | --- 8 | 9 | First, clone the respository (use --recursive to clone & initialize all 10 | submodules) 11 | 12 | ```bash 13 | git clone --recursive git@github.com:kkiningh/cs231n-project.git 14 | ``` 15 | 16 | TODO 17 | -------------------------------------------------------------------------------- /sim/Makefile: -------------------------------------------------------------------------------- 1 | RTL_DIR := ../src/rtl 2 | RTL_TB := $(RTL_DIR)/TopTest.sv 3 | RTL_SRC := $(RTL_DIR)/Top.sv 4 | 5 | ### Naming setup 6 | TOP ?= Top 7 | TB ?= $(basename $(basename $(notdir $(RTL_TB)))) 8 | 9 | ### Setup for VCS 10 | # Need to add linker flags if they're not already set 11 | VCS ?= vcs -full64 -LDFLAGS -Wl,--no-as-needed 12 | VCS_OPTIONS += -debug_access+all 13 | VCS_OPTIONS += -q -notice 14 | VCS_OPTIONS += -j8 15 | VCS_OPTIONS += -sverilog 16 | 17 | VCS := $(strip $(VCS)) 18 | VCS_OPTIONS := $(strip $(VCS_OPTIONS)) 19 | 20 | ### Acutal build rules 21 | build/$(TOP).$(TB).simv: $(RTL_TB) $(RTL_SRC) 22 | @mkdir -p $(dir $@) 23 | $(VCS) $(VCS_OPTIONS) \ 24 | -o $@ $^ \ 25 | -Mdir=$@-csrc \ 26 | -top $(TOP) 27 | 28 | build/$(TOP).$(TB).vcd: build/$(TOP).$(TB).simv 29 | @mkdir -p $(dir $@) 30 | $^ +vpdfile+$@ -k $@-ucli.key 31 | 32 | .PHONY: clean 33 | clean: 34 | rm -r build 35 | -------------------------------------------------------------------------------- /src/rtl/32saif.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/rtl/32saif.tar.gz -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/GrayCounter.v: -------------------------------------------------------------------------------- 1 | //========================================== 2 | // Function : Code Gray counter. 3 | // Coder : Alex Claros F. 4 | // Date : 15/May/2005. 5 | //======================================= 6 | 7 | `timescale 1ns/1ps 8 | 9 | module GrayCounter 10 | #(parameter COUNTER_WIDTH = 4) 11 | 12 | (output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output. 13 | 14 | input wire Enable_in, //Count enable. 15 | input wire Clear_in, //Count reset. 16 | 17 | input wire Clk); 18 | 19 | /////////Internal connections & variables/////// 20 | reg [COUNTER_WIDTH-1:0] BinaryCount; 21 | 22 | /////////Code/////////////////////// 23 | 24 | always @ (posedge Clk) 25 | if (Clear_in) begin 26 | BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with 27 | GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'. 28 | end 29 | else if (Enable_in) begin 30 | BinaryCount <= BinaryCount + 1; 31 | GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1], 32 | BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]}; 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/MatrixInput.v: -------------------------------------------------------------------------------- 1 | module MatrixInput #(parameter DEPTH = 256, ADDRESS_WIDTH =8, WIDTH = 8) ( Data_in, Data_out, valid, CLK, WEN, REN, RESET, Full_out, Empty_out); 2 | 3 | input wire [WIDTH-1:0] Data_in [DEPTH-1:0]; 4 | output wire [WIDTH-1:0] Data_out [DEPTH-1:0]; 5 | output wire [DEPTH-1:0] Full_out; 6 | output wire [DEPTH-1:0] Empty_out; 7 | input wire valid; 8 | input wire CLK; 9 | input wire REN; 10 | input wire WEN; 11 | input wire RESET; 12 | 13 | reg [DEPTH-1:0] valid_reg; 14 | 15 | always @(posedge CLK) begin 16 | valid_reg [DEPTH-1:0] <= {valid,valid_reg[DEPTH-1:1]}; 17 | end 18 | 19 | 20 | genvar i; 21 | 22 | generate 23 | for (i=DEPTH-1; i >=0; i=i-1) begin : ROWFIFO 24 | if (i==DEPTH-1) begin : check 25 | aFifo #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U 26 | (.Data_out(Data_out[i]), 27 | .Empty_out(Empty_out[i]), 28 | .ReadEn_in(valid), 29 | .RClk(CLK), 30 | .Data_in(Data_in[i]), 31 | .Full_out(Full_out[i]), 32 | .WriteEn_in(WEN), 33 | .WClk(CLK), 34 | .Clear_in(RESET)); 35 | end else begin : NonZero 36 | aFifo #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U 37 | (.Data_out(Data_out[i]), 38 | .Empty_out(Empty_out[i]), 39 | .ReadEn_in(valid_reg[i+1]), 40 | .RClk(CLK), 41 | .Data_in(Data_in[i]), 42 | .Full_out(Full_out[i]), 43 | .WriteEn_in(WEN), 44 | .WClk(CLK), 45 | .Clear_in(RESET)); 46 | end 47 | end 48 | endgenerate 49 | 50 | 51 | /*AUTOPERL 52 | for ($e=7; $e>=0; $e--) { 53 | $t = $e; 54 | if ($e==7) { 55 | print "aFifo #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U$e\n"; 56 | print "\t(.Data_out(Data_out[$e]),"; 57 | print ".Empty_out(),"; 58 | print ".ReadEn_in(REN & valid),\n"; 59 | print "\t.RClk(CLK),"; 60 | print ".Data_in(Data_in[$e]),"; 61 | print ".Full_out(),\n"; 62 | print "\t.WriteEn_in(WEN),"; 63 | print ".WClk(CLK),"; 64 | print ".Clear_in(RESET));\n"; 65 | print "\n"; 66 | } else { 67 | print "aFifo #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U$e\n"; 68 | print "\t(.Data_out(Data_out[$e]),"; 69 | print ".Empty_out(),"; 70 | print ".ReadEn_in(REN & valid_reg[$t]),\n"; 71 | print "\t.RClk(CLK),"; 72 | print ".Data_in(Data_in[$e]),"; 73 | print ".Full_out(),\n"; 74 | print "\t.WriteEn_in(WEN),"; 75 | print ".WClk(CLK),"; 76 | print ".Clear_in(RESET));\n"; 77 | print "\n"; 78 | } 79 | } 80 | */ 81 | 82 | endmodule 83 | 84 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/MatrixInput_sram.v: -------------------------------------------------------------------------------- 1 | module MatrixInput_sram #(parameter DEPTH = 256, ADDRESS_WIDTH =8, WIDTH = 8) ( Data_in, Data_out, valid, CLK, WEN, REN, RESET, Full_out, Empty_out); 2 | 3 | input wire [WIDTH-1:0] Data_in [DEPTH-1:0]; 4 | output wire [WIDTH-1:0] Data_out [DEPTH-1:0]; 5 | output wire [DEPTH-1:0] Full_out; 6 | output wire [DEPTH-1:0] Empty_out; 7 | input wire valid; 8 | input wire CLK; 9 | input wire REN; 10 | input wire WEN; 11 | input wire RESET; 12 | 13 | reg [DEPTH-1:0] valid_reg; 14 | 15 | always @(posedge CLK) begin 16 | valid_reg [DEPTH-1:0] <= {valid,valid_reg[DEPTH-1:1]}; 17 | end 18 | 19 | 20 | genvar i; 21 | 22 | generate 23 | for (i=DEPTH-1; i >=0; i=i-1) begin : ROWFIFO 24 | if (i==DEPTH-1) begin : check 25 | aFifo_256x8 #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U 26 | (.Data_out(Data_out[i]), 27 | .Empty_out(Empty_out[i]), 28 | .ReadEn_in(valid), 29 | .RClk(CLK), 30 | .Data_in(Data_in[i]), 31 | .Full_out(Full_out[i]), 32 | .WriteEn_in(WEN), 33 | .WClk(CLK), 34 | .Clear_in(RESET)); 35 | end else begin : NonZero 36 | aFifo_256x8 #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U 37 | (.Data_out(Data_out[i]), 38 | .Empty_out(Empty_out[i]), 39 | .ReadEn_in(valid_reg[i+1]), 40 | .RClk(CLK), 41 | .Data_in(Data_in[i]), 42 | .Full_out(Full_out[i]), 43 | .WriteEn_in(WEN), 44 | .WClk(CLK), 45 | .Clear_in(RESET)); 46 | end 47 | end 48 | endgenerate 49 | 50 | 51 | /*AUTOPERL 52 | for ($e=7; $e>=0; $e--) { 53 | $t = $e; 54 | if ($e==7) { 55 | print "aFifo #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U$e\n"; 56 | print "\t(.Data_out(Data_out[$e]),"; 57 | print ".Empty_out(),"; 58 | print ".ReadEn_in(REN & valid),\n"; 59 | print "\t.RClk(CLK),"; 60 | print ".Data_in(Data_in[$e]),"; 61 | print ".Full_out(),\n"; 62 | print "\t.WriteEn_in(WEN),"; 63 | print ".WClk(CLK),"; 64 | print ".Clear_in(RESET));\n"; 65 | print "\n"; 66 | } else { 67 | print "aFifo #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) U$e\n"; 68 | print "\t(.Data_out(Data_out[$e]),"; 69 | print ".Empty_out(),"; 70 | print ".ReadEn_in(REN & valid_reg[$t]),\n"; 71 | print "\t.RClk(CLK),"; 72 | print ".Data_in(Data_in[$e]),"; 73 | print ".Full_out(),\n"; 74 | print "\t.WriteEn_in(WEN),"; 75 | print ".WClk(CLK),"; 76 | print ".Clear_in(RESET));\n"; 77 | print "\n"; 78 | } 79 | } 80 | */ 81 | 82 | endmodule 83 | 84 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/aFifo.v: -------------------------------------------------------------------------------- 1 | //========================================== 2 | // Function : Asynchronous FIFO (w/ 2 asynchronous clocks). 3 | // Coder : Alex Claros F. 4 | // Date : 15/May/2005. 5 | // Notes : This implementation is based on the article 6 | // 'Asynchronous FIFO in Virtex-II FPGAs' 7 | // writen by Peter Alfke. This TechXclusive 8 | // article can be downloaded from the 9 | // Xilinx website. It has some minor modifications. 10 | //========================================= 11 | 12 | `timescale 1ns/1ps 13 | 14 | module aFifo 15 | #(parameter DATA_WIDTH = 8, 16 | ADDRESS_WIDTH = 8, 17 | FIFO_DEPTH = (1 << ADDRESS_WIDTH)) 18 | //Reading port 19 | (output reg [DATA_WIDTH-1:0] Data_out, 20 | output reg Empty_out, 21 | input wire ReadEn_in, 22 | input wire RClk, 23 | //Writing port. 24 | input wire [DATA_WIDTH-1:0] Data_in, 25 | output reg Full_out, 26 | input wire WriteEn_in, 27 | input wire WClk, 28 | 29 | input wire Clear_in); 30 | 31 | /////Internal connections & variables////// 32 | reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0]; 33 | wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead; 34 | wire EqualAddresses; 35 | wire NextWriteAddressEn, NextReadAddressEn; 36 | wire Set_Status, Rst_Status; 37 | reg Status; 38 | wire PresetFull, PresetEmpty; 39 | 40 | //////////////Code/////////////// 41 | //Data ports logic: 42 | //(Uses a dual-port RAM). 43 | //'Data_out' logic: 44 | always @ (posedge RClk) 45 | if (ReadEn_in & !Empty_out) 46 | Data_out <= Mem[pNextWordToRead]; 47 | 48 | //'Data_in' logic: 49 | always @ (posedge WClk) 50 | if (WriteEn_in & !Full_out) 51 | Mem[pNextWordToWrite] <= Data_in; 52 | 53 | //Fifo addresses support logic: 54 | //'Next Addresses' enable logic: 55 | assign NextWriteAddressEn = WriteEn_in & ~Full_out; 56 | assign NextReadAddressEn = ReadEn_in & ~Empty_out; 57 | 58 | //Addreses (Gray counters) logic: 59 | GrayCounter #(ADDRESS_WIDTH) GrayCounter_pWr 60 | (.GrayCount_out(pNextWordToWrite), 61 | 62 | .Enable_in(NextWriteAddressEn), 63 | .Clear_in(Clear_in), 64 | 65 | .Clk(WClk) 66 | ); 67 | 68 | GrayCounter #(ADDRESS_WIDTH) GrayCounter_pRd 69 | (.GrayCount_out(pNextWordToRead), 70 | .Enable_in(NextReadAddressEn), 71 | .Clear_in(Clear_in), 72 | .Clk(RClk) 73 | ); 74 | 75 | 76 | //'EqualAddresses' logic: 77 | assign EqualAddresses = (pNextWordToWrite == pNextWordToRead); 78 | 79 | //'Quadrant selectors' logic: 80 | assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) & 81 | (pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]); 82 | 83 | assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) & 84 | (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]); 85 | 86 | //'Status' latch logic: 87 | always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset. 88 | if (Rst_Status | Clear_in) 89 | Status = 0; //Going 'Empty'. 90 | else if (Set_Status) 91 | Status = 1; //Going 'Full'. 92 | 93 | //'Full_out' logic for the writing port: 94 | assign PresetFull = Status & EqualAddresses; //'Full' Fifo. 95 | 96 | always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset. 97 | if (PresetFull) 98 | Full_out <= 1; 99 | else 100 | Full_out <= 0; 101 | 102 | //'Empty_out' logic for the reading port: 103 | assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo. 104 | 105 | always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset. 106 | if (PresetEmpty) 107 | Empty_out <= 1; 108 | else 109 | Empty_out <= 0; 110 | 111 | endmodule 112 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/aFifo_256x8.v: -------------------------------------------------------------------------------- 1 | //========================================== 2 | // Function : Asynchronous FIFO (w/ 2 asynchronous clocks). 3 | // Coder : Alex Claros F. 4 | // Date : 15/May/2005. 5 | // Notes : This implementation is based on the article 6 | // 'Asynchronous FIFO in Virtex-II FPGAs' 7 | // writen by Peter Alfke. This TechXclusive 8 | // article can be downloaded from the 9 | // Xilinx website. It has some minor modifications. 10 | //========================================= 11 | 12 | `timescale 1ns/1ps 13 | 14 | module aFifo_256x8 15 | #(parameter DATA_WIDTH = 8, 16 | ADDRESS_WIDTH = 8, 17 | FIFO_DEPTH = (1 << ADDRESS_WIDTH)) 18 | //Reading port 19 | (output reg [DATA_WIDTH-1:0] Data_out, 20 | output reg Empty_out, 21 | input wire ReadEn_in, 22 | input wire RClk, 23 | //Writing port. 24 | input wire [DATA_WIDTH-1:0] Data_in, 25 | output reg Full_out, 26 | input wire WriteEn_in, 27 | input wire WClk, 28 | 29 | input wire Clear_in); 30 | 31 | /////Internal connections & variables////// 32 | reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0]; 33 | wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead; 34 | wire EqualAddresses; 35 | wire NextWriteAddressEn, NextReadAddressEn; 36 | wire Set_Status, Rst_Status; 37 | reg Status; 38 | wire PresetFull, PresetEmpty; 39 | 40 | //////////////Code/////////////// 41 | //Data ports logic: 42 | //(Uses a dual-port RAM). 43 | //'Data_out' logic: 44 | /* Begin Comment 45 | always @ (posedge RClk) 46 | if (ReadEn_in & !Empty_out) 47 | Data_out <= Mem[pNextWordToRead]; 48 | 49 | //'Data_in' logic: 50 | always @ (posedge WClk) 51 | if (WriteEn_in & !Full_out) 52 | Mem[pNextWordToWrite] <= Data_in; 53 | End Comment */ 54 | 55 | // Synopsys SRAM memory usage A1: ReadPort , A2 : WritePort 56 | wire [DATA_WIDTH-1:0] temp; 57 | wire [DATA_WIDTH-1:0] Lsb_Data_out; 58 | wire [DATA_WIDTH-1:0] Msb_Data_out; 59 | wire read_LsbEn , read_MsbEn, write_MsbEn, write_Lsben; 60 | 61 | assign read_LsbEn = ~pNextWordToRead[7]; 62 | assign read_MsbEn = pNextWordToRead[7]; 63 | assign write_LsbEn = ~pNextWordToWrite[7]; 64 | assign write_MsbEn = pNextWordToWrite[7]; 65 | 66 | assign Data_out = (read_LsbEn ? Lsb_Data_out : Msb_Data_out); 67 | 68 | SRAM2RW128x8 INST_LSB_SRAM2RW128x8 (.A1(pNextWordToRead[6:0]), 69 | .A2(pNextWordToWrite[6:0]), 70 | .CE1(RClk & read_LsbEn), 71 | .CE2(WClk & write_LsbEn), 72 | .WEB1(ReadEn_in), 73 | .WEB2(~WriteEn_in), 74 | .OEB1(1'b0), 75 | .OEB2(1'b1), 76 | .CSB1(~ReadEn_in), 77 | .CSB2(~WriteEn_in), 78 | .I1(8'h00), 79 | .I2(Data_in), 80 | .O1(Lsb_Data_out), 81 | .O2(temp)); 82 | 83 | SRAM2RW128x8 INST_MSB_SRAM2RW128x8 (.A1(pNextWordToRead[6:0]), 84 | .A2(pNextWordToWrite[6:0]), 85 | .CE1(RClk & read_MsbEn), 86 | .CE2(WClk & write_MsbEn), 87 | .WEB1(ReadEn_in), 88 | .WEB2(~WriteEn_in), 89 | .OEB1(1'b1), 90 | .OEB2(1'b0), 91 | .CSB1(~ReadEn_in), 92 | .CSB2(~WriteEn_in), 93 | .I1(8'h00), 94 | .I2(Data_in), 95 | .O1(Msb_Data_out), 96 | .O2(temp)); 97 | 98 | 99 | //Fifo addresses support logic: 100 | //'Next Addresses' enable logic: 101 | assign NextWriteAddressEn = WriteEn_in & ~Full_out; 102 | assign NextReadAddressEn = ReadEn_in & ~Empty_out; 103 | 104 | //Addreses (Gray counters) logic: 105 | GrayCounter #(ADDRESS_WIDTH) GrayCounter_pWr 106 | (.GrayCount_out(pNextWordToWrite), 107 | 108 | .Enable_in(NextWriteAddressEn), 109 | .Clear_in(Clear_in), 110 | 111 | .Clk(WClk) 112 | ); 113 | 114 | GrayCounter #(ADDRESS_WIDTH) GrayCounter_pRd 115 | (.GrayCount_out(pNextWordToRead), 116 | .Enable_in(NextReadAddressEn), 117 | .Clear_in(Clear_in), 118 | .Clk(RClk) 119 | ); 120 | 121 | 122 | //'EqualAddresses' logic: 123 | assign EqualAddresses = (pNextWordToWrite == pNextWordToRead); 124 | 125 | //'Quadrant selectors' logic: 126 | assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) & 127 | (pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]); 128 | 129 | assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) & 130 | (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]); 131 | 132 | //'Status' latch logic: 133 | always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset. 134 | if (Rst_Status | Clear_in) 135 | Status = 0; //Going 'Empty'. 136 | else if (Set_Status) 137 | Status = 1; //Going 'Full'. 138 | 139 | //'Full_out' logic for the writing port: 140 | assign PresetFull = Status & EqualAddresses; //'Full' Fifo. 141 | 142 | always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset. 143 | if (PresetFull) 144 | Full_out <= 1; 145 | else 146 | Full_out <= 0; 147 | 148 | //'Empty_out' logic for the reading port: 149 | assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo. 150 | 151 | always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset. 152 | if (PresetEmpty) 153 | Empty_out <= 1; 154 | else 155 | Empty_out <= 0; 156 | 157 | endmodule 158 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/mux_DRAMorlocal.v: -------------------------------------------------------------------------------- 1 | module mux_DRAMorLocal #(parameter DEPTH=8,WIDTH=8) ( data_in_dram, data_in_local, data_from_DRAM, data_out) ; 2 | 3 | input wire [WIDTH-1:0] data_in_dram [DEPTH-1:0]; 4 | input wire [WIDTH-1:0] data_in_local [DEPTH-1:0]; 5 | input wire data_from_DRAM; 6 | output wire [WIDTH-1:0] data_out [DEPTH-1:0]; 7 | 8 | assign data_out = ( data_from_DRAM ? data_in_dram : data_in_local) ; 9 | 10 | endmodule 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/saed32sram.v: -------------------------------------------------------------------------------- 1 | /********************************************************************* 2 | * SAED_EDK90nm_SRAM : SRAM2RW128x8 Verilog description * 3 | * --------------------------------------------------------------- * 4 | * Filename : SRAM2RW128x8.v * 5 | * SRAM name : SRAM2RW128x8 * 6 | * Word width : 8 bits * 7 | * Word number : 128 * 8 | * Adress width : 7 bits * 9 | **********************************************************************/ 10 | 11 | `timescale 1ns/100fs 12 | 13 | `define numAddr 7 14 | `define numWords 128 15 | `define wordLength 8 16 | 17 | 18 | 19 | module SRAM2RW128x8 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2); 20 | 21 | input CE1; 22 | input CE2; 23 | input WEB1; 24 | input WEB2; 25 | input OEB1; 26 | input OEB2; 27 | input CSB1; 28 | input CSB2; 29 | 30 | input [`numAddr-1:0] A1; 31 | input [`numAddr-1:0] A2; 32 | input [`wordLength-1:0] I1; 33 | input [`wordLength-1:0] I2; 34 | output [`wordLength-1:0] O1; 35 | output [`wordLength-1:0] O2; 36 | 37 | /*reg [`wordLength-1:0] memory[`numWords-1:0];*/ 38 | /*reg [`wordLength-1:0] data_out1;*/ 39 | /*reg [`wordLength-1:0] data_out2;*/ 40 | wire [`wordLength-1:0] O1; 41 | wire [`wordLength-1:0] O2; 42 | 43 | wire RE1; 44 | wire RE2; 45 | wire WE1; 46 | wire WE2; 47 | 48 | SRAM2RW128x8_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]); 49 | SRAM2RW128x8_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]); 50 | SRAM2RW128x8_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]); 51 | SRAM2RW128x8_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]); 52 | SRAM2RW128x8_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]); 53 | SRAM2RW128x8_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]); 54 | SRAM2RW128x8_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]); 55 | SRAM2RW128x8_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]); 56 | 57 | 58 | endmodule 59 | 60 | 61 | module SRAM2RW128x8_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i, A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i); 62 | 63 | input CSB1_i, CSB2_i; 64 | input OEB1_i, OEB2_i; 65 | input CE1_i, CE2_i; 66 | input WEB1_i, WEB2_i; 67 | 68 | input [`numAddr-1:0] A1_i, A2_i; 69 | input [0:0] I1_i, I2_i; 70 | 71 | output [0:0] O1_i, O2_i; 72 | 73 | reg [0:0] O1_i, O2_i; 74 | reg [0:0] memory[`numWords-1:0]; 75 | reg [0:0] data_out1, data_out2; 76 | 77 | 78 | and u1 (RE1, ~CSB1_i, WEB1_i); 79 | and u2 (WE1, ~CSB1_i, ~WEB1_i); 80 | and u3 (RE2, ~CSB2_i, WEB2_i); 81 | and u4 (WE2, ~CSB2_i, ~WEB2_i); 82 | 83 | //Primary ports 84 | 85 | always @ (posedge CE1_i) 86 | if (RE1) 87 | data_out1 = memory[A1_i]; 88 | always @ (posedge CE1_i) 89 | if (WE1) 90 | memory[A1_i] = I1_i; 91 | 92 | 93 | always @ (data_out1 or OEB1_i) 94 | if (!OEB1_i) 95 | O1_i = data_out1; 96 | else 97 | O1_i = 1'bz; 98 | 99 | //Dual ports 100 | always @ (posedge CE2_i) 101 | if (RE2) 102 | data_out2 = memory[A2_i]; 103 | always @ (posedge CE2_i) 104 | if (WE2) 105 | memory[A2_i] = I2_i; 106 | 107 | always @ (data_out2 or OEB2_i) 108 | if (!OEB2_i) 109 | O2_i = data_out2; 110 | else 111 | O2_i = 1'bz; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /src/rtl/MatrixInputQueue/test_afifo.v: -------------------------------------------------------------------------------- 1 | // 2 | `timescale 1ns/1ps 3 | 4 | module test_afifo 5 | (); 6 | 7 | parameter DEPTH = 8, ADDRESS_WIDTH = 3, WIDTH=8; 8 | parameter clk_period = 2; 9 | parameter half_period = 1; 10 | 11 | reg CLK; 12 | reg REN; 13 | reg WEN; 14 | reg RESET; 15 | reg valid; 16 | reg [WIDTH-1:0] Data_in [DEPTH-1:0]; 17 | wire [WIDTH-1:0] Data_out [DEPTH-1:0]; 18 | wire [DEPTH-1:0] Full_out; 19 | wire [DEPTH-1:0] Empty_out; 20 | 21 | 22 | MatrixInput #(.DEPTH(DEPTH),.ADDRESS_WIDTH(ADDRESS_WIDTH),.WIDTH(WIDTH)) DUT ( 23 | .CLK(CLK),.valid(valid),.REN(REN),.WEN(WEN),.RESET(RESET), 24 | .Data_in(Data_in),.Data_out(Data_out),.Full_out(Full_out),.Empty_out(Empty_out)); 25 | 26 | always begin 27 | #half_period 28 | CLK = ~CLK; 29 | end 30 | 31 | initial begin 32 | RESET = 1'b1; 33 | valid = 1'b0; 34 | REN = 1'b0; 35 | WEN = 1'b0; 36 | CLK = 1'b0; 37 | $dumpfile("test.vcd") ; 38 | $dumpvars; 39 | 40 | #20 RESET=1'b0; 41 | #clk_period 42 | for (integer i=0;i (i+MATRIX_SIZE-1)) begin 29 | data_out[j][i]=8'h00; 30 | $display("value of data_out[%d][%d] is 0 : 2",j,i); 31 | end 32 | else begin 33 | data_out[j][i] = data_in[i+j][i]; 34 | $display ("value of data_out[%d][%d] is data_in[%d][%d]",j,i,i+j,j ); 35 | end 36 | end 37 | end 38 | $display ("End Iteration"); 39 | $display("\n"); 40 | end 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /src/rtl/SystolicDataSetupRow.v: -------------------------------------------------------------------------------- 1 | module SystolicDataSetupRow #( 2 | parameter DATA_BITS = 8, 3 | parameter MATRIX_SIZE = 256, 4 | parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1 5 | ) ( 6 | input clock, 7 | input reset, 8 | 9 | input [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:MATRIX_SIZE-1], 10 | output [DATA_BITS-1:0] data_out[0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1] 11 | ); 12 | 13 | integer i; 14 | integer j; 15 | always @ (posedge clock or posedge reset) begin 16 | if (reset) begin 17 | for( i = 0; i < MATRIX_SIZE; i++ ) 18 | for (j=0;j< OUTPUT_SIZE;j++) 19 | data_out[i][j] = 8'h00; 20 | end else begin 21 | $display ("New Iteration"); 22 | for( i = 0; i < MATRIX_SIZE; i++ ) begin 23 | for( j = 0; j < OUTPUT_SIZE; j++ ) begin 24 | if (j (i+MATRIX_SIZE-1)) begin 29 | data_out[i][j]=8'h00; 30 | $display("value of data_out[%d][%d] is 0 : 2",i,j); 31 | end 32 | else begin 33 | data_out[i][j] = data_in[i][i+j]; 34 | $display ("value of data_out[%d][%d] is data_in[%d][%d]",i,j,i,i+j ); 35 | end 36 | end 37 | end 38 | $display ("End Iteration"); 39 | $display("\n"); 40 | end 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /src/rtl/Top.sv: -------------------------------------------------------------------------------- 1 | module Mac #( 2 | parameter D_BITS = 8, 3 | parameter W_BITS = 8, 4 | parameter A_BITS = 16 5 | ) ( 6 | input clock, 7 | input reset, 8 | 9 | input set_w, 10 | input stall, 11 | 12 | input [A_BITS-1:0] a_in, 13 | input [D_BITS-1:0] d_in, 14 | 15 | output reg [A_BITS-1:0] a_out, 16 | output reg [D_BITS-1:0] d_out 17 | ); 18 | reg [W_BITS-1:0] w; 19 | always @(posedge clock) begin 20 | if (reset) begin 21 | w <= {W_BITS{1'b0}}; 22 | a_out <= {A_BITS{1'b0}}; 23 | d_out <= {D_BITS{1'b0}}; 24 | end else if (!stall) begin 25 | if (set_w) begin 26 | w <= a_in; 27 | a_out <= a_in; 28 | end else begin 29 | a_out <= d_in * w + a_in; 30 | d_out <= d_in; 31 | end 32 | end 33 | end 34 | endmodule 35 | 36 | module SystolicArray #( 37 | parameter WIDTH = 4, 38 | parameter HEIGHT = 4, 39 | parameter D_BITS = 1, 40 | parameter W_BITS = 1, 41 | parameter A_BITS = 16 42 | ) ( 43 | input clock, 44 | input reset, 45 | 46 | input set_w, 47 | input stall, 48 | 49 | input [D_BITS-1:0] d_in [0:HEIGHT-1], 50 | input [W_BITS-1:0] w_in [0:WIDTH-1], 51 | 52 | output [A_BITS-1:0] a_out [0:WIDTH-1] 53 | ); 54 | genvar i, j; 55 | generate for (i = 0; i < HEIGHT; i = i + 1) begin : Row 56 | for (j = 0; j < WIDTH; j = j + 1) begin : Column 57 | wire [A_BITS-1:0] a_in_row, a_out_row; 58 | wire [D_BITS-1:0] d_in_col, d_out_col; 59 | 60 | // Special case first row 61 | if (i == 0) begin : RowEdge 62 | assign a_in_row = set_w ? w_in[i] : {A_BITS{1'b0}}; 63 | end else begin : RowNonEdge 64 | assign a_in_row = Row[i-1].Column[j].a_out_row; 65 | end 66 | 67 | // Special case first row 68 | if (j == 0) begin 69 | assign d_in_col = d_in[i]; 70 | end else begin 71 | assign d_in_col = Row[i].Column[j-1].d_out_col; 72 | end 73 | 74 | Mac #(.D_BITS(D_BITS), .W_BITS(W_BITS), .A_BITS(A_BITS)) mac ( 75 | .clock(clock), 76 | .reset(reset), 77 | .set_w(set_w), 78 | .stall(stall), 79 | 80 | .a_in(a_in_row), 81 | .d_in(d_in_col), 82 | .a_out(a_out_row), 83 | .d_out(d_out_col) 84 | ); 85 | end 86 | end endgenerate 87 | 88 | generate for (j = 0; j < WIDTH; j = j + 1) begin : ColumnOut 89 | assign a_out[j] = Row[HEIGHT-1].Column[j].a_out_row; 90 | end endgenerate 91 | endmodule 92 | 93 | module AccumulateQueue #( 94 | parameter A_BITS = 32, 95 | parameter FIFO_LENGTH = 8, 96 | 97 | /* Number of bits needed to index into the queue */ 98 | parameter INDEX_BITS = $clog2(FIFO_LENGTH) 99 | ) ( 100 | input clock, 101 | input reset, 102 | 103 | input stall, 104 | 105 | input [A_BITS-1:0] a_in, 106 | 107 | output [A_BITS-1:0] a_out 108 | ); 109 | /* 110 | The accumulation queue stores the results of the systolic array and adds 111 | it to previous partial products. 112 | 113 | In particular, on each cycle we read the previous partial product from 114 | the end of the fifo and add the value emitted from systolic array. 115 | Then, on the next cycle we write the value to the front of the queue. 116 | 117 | The way this is actually implemented is that we have two SRAMs - odd and 118 | even. When the index is even, we write last cycle's partial product to the 119 | even queue, and read the next partial product from the odd queue. 120 | 121 | This is reversed when the index is odd. 122 | */ 123 | reg [A_BITS-1:0] fifo_e [0:(FIFO_LENGTH/2)-1]; 124 | reg [A_BITS-1:0] fifo_o [0:(FIFO_LENGTH/2)-1]; 125 | reg [A_BITS-1:0] head; 126 | reg [INDEX_BITS-1:0] index; 127 | 128 | /* Set the fifo to zero on reset */ 129 | integer i; 130 | always @(posedge clock) begin 131 | if (reset) begin 132 | for (i = 0; i < FIFO_LENGTH; i = i + 1) begin 133 | fifo_e[i] <= {A_BITS{1'b0}}; 134 | fifo_o[i] <= {A_BITS{1'b0}}; 135 | end 136 | 137 | head <= {A_BITS{1'b0}}; 138 | index <= {INDEX_BITS{1'b0}}; 139 | end 140 | end 141 | 142 | /* The next index is just the current index + 1 */ 143 | wire [INDEX_BITS-1:0] index_next = index + 1; 144 | 145 | /* The fifo index is just the top INDEX_BITS-1 bits */ 146 | wire [INDEX_BITS-2:0] fifo_index = index[INDEX_BITS-1:1]; 147 | wire [INDEX_BITS-2:0] fifo_index_next = index_next[INDEX_BITS-1:1]; 148 | 149 | /* Index is odd if the last bit is 1 */ 150 | wire odd = index[0]; 151 | 152 | always @(posedge clock) begin 153 | if (!reset && !stall) begin 154 | if (odd) begin 155 | /* If odd, write to the odd queue... */ 156 | fifo_o[fifo_index] <= head + a_in; 157 | 158 | /* ...and read from the even queue */ 159 | head <= fifo_e[fifo_index_next]; 160 | end else begin 161 | /* If even, write to the even queue... */ 162 | fifo_e[fifo_index] <= head + a_in; 163 | 164 | /* ...and read from the odd queue */ 165 | head <= fifo_o[fifo_index_next]; 166 | end 167 | 168 | index <= index_next; 169 | end 170 | end 171 | 172 | /* Output is just the head of the queue */ 173 | assign a_out = head; 174 | endmodule 175 | -------------------------------------------------------------------------------- /src/rtl/TopTest.sv: -------------------------------------------------------------------------------- 1 | module Top; 2 | reg clock = 1'b0; 3 | reg reset = 1'b1; 4 | 5 | /* Toggle clock every 10 steps */ 6 | always #10 clock <= ~clock; 7 | 8 | /* DUT */ 9 | localparam A_BITS = 32; 10 | localparam FIFO_LENGTH = 8; 11 | reg stall = 1'b1; 12 | reg [A_BITS-1:0] a_in = {A_BITS{1'b0}}; 13 | wire [A_BITS-1:0] a_out; 14 | AccumulateQueue #( 15 | .A_BITS(A_BITS), 16 | .FIFO_LENGTH(FIFO_LENGTH) 17 | ) dut ( 18 | .clock(clock), 19 | .reset(reset), 20 | 21 | .stall(stall), 22 | .a_in(a_in), 23 | .a_out(a_out) 24 | ); 25 | 26 | /* Actual test program */ 27 | integer i; 28 | initial begin 29 | $vcdpluson; 30 | $display("Simulation begining"); 31 | 32 | /* Release reset after 10 cycles */ 33 | #100 reset <= 1'b0; 34 | $display("Reset released"); 35 | 36 | stall <= 0; 37 | 38 | for (i = 0; i < FIFO_LENGTH; i = i + 1) begin 39 | $display("Sending %d", i); 40 | a_in <= i; 41 | #10; 42 | $display("fifo_e %p, fifo_o %p, head %d, index %d", 43 | dut.fifo_e, dut.fifo_o, dut.head, dut.index); 44 | end 45 | 46 | // Stop sending 47 | a_in <= '0; 48 | 49 | for (i = 0; i < FIFO_LENGTH; i = i + 1) begin 50 | $display("Got %d", a_out); 51 | #10; 52 | end 53 | 54 | $finish; 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /src/rtl/XdataSetup.v: -------------------------------------------------------------------------------- 1 | module XdataSetup #( 2 | parameter DATA_BITS = 8, 3 | parameter MATRIX_SIZE = 256, 4 | parameter PAD_SIZE = 2*MATRIX_SIZE-1 5 | ) ( 6 | input clock, 7 | input reset, 8 | input [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:MATRIX_SIZE-1], 9 | input shift, 10 | input load, 11 | output [DATA_BITS-1:0] data_out [0:MATRIX_SIZE-1] 12 | ); 13 | 14 | 15 | wire [DATA_BITS-1:0] sys_data_out[0:MATRIX_SIZE-1][0:PAD_SIZE-1]; 16 | 17 | SystolicDataSetupRow #( 18 | .DATA_BITS(DATA_BITS), 19 | .MATRIX_SIZE(MATRIX_SIZE), 20 | .OUTPUT_SIZE(PAD_SIZE) 21 | ) XSetup ( 22 | .clock(clock), 23 | .reset(reset), 24 | .data_in(data_in), 25 | .data_out(sys_data_out) 26 | ); 27 | 28 | ShiftRegister #( 29 | .DATA_BITS(DATA_BITS), 30 | .MATRIX_SIZE(MATRIX_SIZE), 31 | .OUTPUT_SIZE(PAD_SIZE) 32 | ) XshiftReg ( 33 | .clock(clock), 34 | .reset(reset), 35 | .load(load), 36 | .shift(shift), 37 | .data_in(sys_data_out), 38 | .data_out(data_out) 39 | ); 40 | 41 | endmodule 42 | 43 | -------------------------------------------------------------------------------- /src/rtl/fsdb/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv_1.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/rtl/fsdb/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv_1.fsdb -------------------------------------------------------------------------------- /src/rtl/novas.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/rtl/novas.fsdb -------------------------------------------------------------------------------- /src/rtl/tb_Top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | `include "test.svh" 3 | 4 | module tb_Top (); 5 | 6 | parameter WIDTH = 8, DEPTH = 32 , DEPTH2 = 2*DEPTH; 7 | parameter clk_period = 2; 8 | parameter half_period = 1; 9 | //parameter SIZE = 3 ; 10 | `define SIZE = DEPTH 11 | /*integer [7:0] A [2:0][2:0]; 12 | integer [7:0] B [2:0][2:0]; 13 | 14 | integer [7:0] C [2:0][2:0];*/ 15 | 16 | byte unsigned A[DEPTH-1:0][DEPTH-1:0]; 17 | byte unsigned B[DEPTH-1:0][DEPTH-1:0]; 18 | byte unsigned C[DEPTH-1:0][DEPTH-1:0]; 19 | 20 | reg CLK; 21 | reg RESET; 22 | reg RESET_sram; 23 | reg [WIDTH-1:0] data_in_dram [DEPTH-1:0]; 24 | reg DRAM; 25 | reg valid; 26 | reg WEN; 27 | reg REN; 28 | reg REN_q; 29 | wire [DEPTH-1:0] Full_out; 30 | wire [DEPTH-1:0] Empty_out; 31 | reg [WIDTH-1:0] w_in [0:DEPTH-1]; 32 | reg stall; 33 | reg set_w; 34 | reg [WIDTH-1:0] temp ; 35 | 36 | `TB_ARG_STR(weights, "values.raw/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv/1/lhs_169_256.trunc"); 37 | `TB_ARG_STR(inputval, "values.raw/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv/1/rhs_256_48.trunc"); 38 | `TB_ARG_INT(mode, "0"); 39 | 40 | Top #(.DEPTH(DEPTH),.ADDRESS_WIDTH(5), .WIDTH(WIDTH))ITop (.CLK(CLK), .RESET_sram(RESET_sram),.RESET(RESET),.data_in_dram(data_in_dram),.DRAM(DRAM),.valid(valid),.REN(REN),.WEN(WEN),.Full_out(Full_out),.Empty_out(Empty_out),.w_in(w_in),.stall(stall),.set_w(set_w),.REN_q(REN_q)); 41 | 42 | always begin 43 | #half_period 44 | CLK = ~CLK; 45 | end 46 | 47 | initial begin 48 | CLK=0; 49 | RESET = 0; 50 | RESET_sram=0; 51 | DRAM=1; 52 | valid =0; 53 | REN =0; 54 | REN_q =0; 55 | WEN=0; 56 | stall=0; 57 | set_w=0; 58 | for(integer j=0;j=0;i--,j++) begin 171 | @(posedge CLK) begin 172 | set_w <= 1'b1; 173 | WEN <= 1'b1; 174 | for(integer k=0,l=DEPTH;k=0;i--,j++) begin 220 | @(posedge CLK) begin 221 | set_w <= 1'b1; 222 | //WEN <= 1'b1; 223 | for(integer k=0,l=DEPTH-1;k=0;i--,j++) begin 244 | @(posedge CLK) begin 245 | //set_w <= 1'b1; 246 | WEN <= 1'b1; 247 | for(integer k=0,l=DEPTH-1;k _level) begin \ 17 | $display({_type, ": [%t]: %s"}, $time, $sformatf _msg); \ 18 | end while(0) 19 | 20 | `define DEBUG(_msg) `LOG(_msg, "DEBUG", 3) 21 | `define INFO(_msg) `LOG(_msg, "INFO ", 2) 22 | `define WARN(_msg) `LOG(_msg, "WARN ", 1) 23 | `define ERROR(_msg) `LOG(_msg, "ERROR", 0) 24 | 25 | `ifndef NO_VPD 26 | `define SETUP_VPD(_levels, _scope) \ 27 | initial begin \ 28 | if ($test$plusargs("vcdpluson")) begin \ 29 | $vcdplusmemon; \ 30 | $vcdplusdeltacycleon; \ 31 | $vcdpluson(_levels, _scope); \ 32 | end \ 33 | end 34 | `else 35 | `define SETUP_VPD(_levels, _scope) 36 | `endif 37 | 38 | `define CLOCK_GEN(_clock_variable, _half_period) \ 39 | reg _clock_variable; \ 40 | initial begin \ 41 | _clock_variable = 0; \ 42 | forever begin \ 43 | #_half_period _clock_variable = !_clock_variable; \ 44 | end \ 45 | end 46 | 47 | `define WAIT_CYCLES(_cycles, _clock) \ 48 | do begin repeat (_cycles) @(posedge _clock) begin end end while(0) 49 | 50 | `endif 51 | -------------------------------------------------------------------------------- /src/rtl/untar.README: -------------------------------------------------------------------------------- 1 | tar -zxvf : To Extract 2 | -------------------------------------------------------------------------------- /src/tests/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL := MultiplyAccumulateCell 2 | MODULE := $(TOPLEVEL)_tb 3 | 4 | PWD=$(shell pwd) 5 | COCOTB=$(PWD)/../../cocotb 6 | RTL=$(PWD)/../rtl 7 | 8 | # List of Verilog source files 9 | VERILOG_SOURCES = \ 10 | $(RTL)/$(TOPLEVEL).v \ 11 | # $(RTL)/MultiplyAccumulateCell.v 12 | 13 | # Use VCS as the simulator 14 | SIM ?= VCS 15 | COMPILE_ARGS = -LDFLAGS -Wl,--no-as-needed 16 | 17 | include $(COCOTB)/makefiles/Makefile.inc 18 | include $(COCOTB)/makefiles/Makefile.sim 19 | -------------------------------------------------------------------------------- /src/tests/MultiplyAccumulateCell_tb.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | 3 | from cocotb.result import TestFailure 4 | from cocotb.clock import Clock 5 | from cocotb.triggers import RisingEdge, FallingEdge, ClockCycles, ReadOnly 6 | from cocotb.result import TestFailure 7 | 8 | class MultipyAccumulateCellTB(object): 9 | def __init__(self, dut): 10 | self.dut = dut 11 | self.weight = None 12 | 13 | @cocotb.coroutine 14 | def set_weight(self, weight): 15 | self.dut._log.debug("Setting weight to %d" % (weight,)) 16 | self.dut.weight_in = weight 17 | self.dut.weight_set = 1 18 | self.weight = weight 19 | yield RisingEdge(self.dut.clock) 20 | self.dut.weight_in = 0 21 | self.dut.weight_set = 0 22 | 23 | @cocotb.coroutine 24 | def multiply(self, data, accumulator=0): 25 | # Check that we've set a weight 26 | if self.weight == None: 27 | raise TestFailure( 28 | "No weight set in tb yet!") 29 | 30 | # Perform the MAC operation 31 | self.dut.data_in = data 32 | self.dut.accumulator_in = accumulator 33 | self.dut.mac_stall_in = 0 34 | yield RisingEdge(self.dut.clock) 35 | 36 | # Get the result and compare 37 | yield ReadOnly() 38 | acc_out = self.dut.accumulator_out 39 | data_out = self.dut.data_out 40 | 41 | acc_cor = data * self.weight + accumulator 42 | if acc_out != acc_cor: 43 | raise TestFailure( 44 | "Result was %d instead of %d" % (acc_out, acc_cor)) 45 | 46 | if data_out != data: 47 | raise TestFailure( 48 | "Data out was %d instead of %d" % (data_out, data)) 49 | 50 | @cocotb.coroutine 51 | def reset(self, cycles=1): 52 | self.dut._log.debug("Resetting DUT") 53 | self.dut.weight_in = 0 54 | self.dut.weight_set = 0 55 | self.dut.data_in = 0 56 | self.dut.accumulator_in = 0 57 | self.dut.mac_stall_in = 0 58 | self.dut.reset = 1 59 | yield ClockCycles(self.dut.clock, cycles) 60 | self.dut.reset = 0 61 | self.dut._log.debug("Out of reset") 62 | 63 | @cocotb.coroutine 64 | def wait(self, cycles=1): 65 | yield ClockCycles(self.dut.clock, cycles) 66 | 67 | @cocotb.test() 68 | def mac_test(dut): 69 | log = cocotb.logging.getLogger("cocotb.test") 70 | 71 | # Start clock on seperate execution thread 72 | cocotb.fork(Clock(dut.clock, 100).start()) 73 | 74 | # Create the testbench 75 | tb = MultipyAccumulateCellTB(dut) 76 | 77 | # Toggle reset before the actual test 78 | yield tb.reset(2) 79 | 80 | # Set the inputs and outputs 81 | yield tb.set_weight(10) 82 | yield tb.multiply(5) 83 | yield tb.wait(3) 84 | -------------------------------------------------------------------------------- /src/tests/tb_SystolicDataSetup.v: -------------------------------------------------------------------------------- 1 | module tb_SystolicDataSetupRow #( 2 | parameter DATA_BITS = 8, 3 | parameter MATRIX_SIZE = 8, 4 | parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1 5 | ) (); 6 | 7 | reg clock; 8 | reg reset; 9 | 10 | integer count; 11 | reg [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:MATRIX_SIZE-1]; 12 | wire [DATA_BITS-1:0] data_out [0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1]; 13 | 14 | SystolicDataSetupRow #( 15 | .DATA_BITS(DATA_BITS), 16 | .MATRIX_SIZE(MATRIX_SIZE), 17 | .OUTPUT_SIZE(OUTPUT_SIZE) 18 | ) DUT ( 19 | 20 | .clock(clock), 21 | .reset(reset), 22 | .data_in(data_in), 23 | .data_out(data_out) 24 | ); 25 | 26 | 27 | initial begin 28 | clock = 1'b0; 29 | reset = 1'b0; 30 | $dumpfile("Systolic.vcd") ; 31 | $dumpvars; 32 | end 33 | 34 | always begin 35 | #5 clock = ~clock; 36 | #5 clock = ~clock; 37 | end 38 | 39 | initial begin 40 | 41 | #10 reset = 1'b1; 42 | #20 reset = 1'b0; 43 | 44 | #30 45 | for (integer i=0;i worklib ) 6 | define ELAB_SNAPSHOT 7 | define SNAPSHOT worklib.tb_ShiftRegister:v 8 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | define ELAB_SNAPSHOT 87 | define SNAPSHOT worklib.tb_ShiftRegister:v 88 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncelab.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -noshowtop 10 | -LICQUEUE 11 | -ACCESS 12 | +r 13 | -MESSAGES 14 | -XLMODE 15 | ./INCA_libs/irun.lnx8664.15.22.nc 16 | -RUNMODE 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 21 | -WORK 22 | worklib 23 | -HASXLMODE 24 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncelab.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncelab.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -ACCESS 6 | +r 7 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncsim.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494907269 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncsim.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncsim_restart.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494907269 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -XLNAME 28 | ./INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_12119 29 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncsim_restart.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncverilog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -f 10 | include.f 11 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -XLMODE 6 | ./INCA_libs/irun.lnx8664.15.22.nc 7 | -RUNMODE 8 | -sv 9 | ./tb_ShiftRegister.v 10 | ../../../rtl/ShiftRegister.v 11 | -CDSLIB 12 | ./INCA_libs/irun.lnx8664.15.22.nc/cdsrun.lib 13 | -HDLVAR 14 | ./INCA_libs/irun.lnx8664.15.22.nc/hdlrun.var 15 | -MESSAGES 16 | -UPDATE 17 | -XLLIBSTORE 18 | ./INCA_libs/irun.lnx8664.15.22.nc/xllibs 19 | -ALLOWUNBOUND 20 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.files: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/tb_ShiftRegister.v 6 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 7 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -sv 6 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_11846_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_11846_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_12119_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_12119_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_4362_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_4362_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_7225_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_7225_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_8359_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_8359_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_8830_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_8830_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.nclib.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.nclib.lock -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.ncrun.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.ncrun.lock -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.ncv.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.ncv.lock -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/.timestamp.ts: -------------------------------------------------------------------------------- 1 | 1494907263 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/tb_ShiftRegister.v 2 | 1494906173 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/OVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/UVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/bind.lst.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/bind.lst.lnx8664 -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/cds.lib: -------------------------------------------------------------------------------- 1 | include ./cdsrun.lib 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/files.ts: -------------------------------------------------------------------------------- 1 | 1494906173 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 2 | 1494907263 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/tb_ShiftRegister.v 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/hdl.var: -------------------------------------------------------------------------------- 1 | define NCSIMRC ( /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/ncsimrc, ~/.ncsimrc ) 2 | include ./hdlrun.var 3 | define SNAPSHOT worklib.tb_ShiftRegister:v 4 | DEFINE RUNMODEDEFAULT 1 5 | DEFINE LIB_MAP ( + => worklib ) 6 | define ELAB_SNAPSHOT 7 | define SNAPSHOT worklib.tb_ShiftRegister:v 8 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | define ELAB_SNAPSHOT 87 | define SNAPSHOT worklib.tb_ShiftRegister:v 88 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncelab.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -noshowtop 10 | -LICQUEUE 11 | -ACCESS 12 | +r 13 | -MESSAGES 14 | -XLMODE 15 | ./INCA_libs/irun.lnx8664.15.22.nc 16 | -RUNMODE 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 21 | -WORK 22 | worklib 23 | -HASXLMODE 24 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncelab.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncelab.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -ACCESS 6 | +r 7 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncsim.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494907269 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncsim.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncsim_restart.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494907269 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -XLNAME 28 | ./INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_12119 29 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncsim_restart.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncverilog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -f 10 | include.f 11 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncvlog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -XLMODE 6 | ./INCA_libs/irun.lnx8664.15.22.nc 7 | -RUNMODE 8 | -sv 9 | ./tb_ShiftRegister.v 10 | ../../../rtl/ShiftRegister.v 11 | -CDSLIB 12 | ./INCA_libs/irun.lnx8664.15.22.nc/cdsrun.lib 13 | -HDLVAR 14 | ./INCA_libs/irun.lnx8664.15.22.nc/hdlrun.var 15 | -MESSAGES 16 | -UPDATE 17 | -XLLIBSTORE 18 | ./INCA_libs/irun.lnx8664.15.22.nc/xllibs 19 | -ALLOWUNBOUND 20 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncvlog.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncvlog.files: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/tb_ShiftRegister.v 6 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 7 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/ncvlog.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -sv 6 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_11846_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_11846_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_12119_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_12119_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_4362_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_4362_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_7225_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_7225_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_8359_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_8359_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_8830_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_8830_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/worklib/.cdsvmod: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_ShiftRegister/INCA_libs/worklib/.cdsvmod -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/worklib/.inca.db.061.lnx8664: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/worklib/cdsinfo.tag: -------------------------------------------------------------------------------- 1 | CDSLIBRARY 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/INCA_libs/worklib/inca.lnx8664.061.pak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_ShiftRegister/INCA_libs/worklib/inca.lnx8664.061.pak -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/include.f: -------------------------------------------------------------------------------- 1 | ./tb_ShiftRegister.v 2 | ../../../rtl/ShiftRegister.v 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/ncverilog.history: -------------------------------------------------------------------------------- 1 | s1(15May2017:20:13:40): ncverilog +nclicq +sv +nc64bit +access+r ../../../rtl/ShiftRegister.v 2 | s2(15May2017:20:14:05): ncverilog +nclicq +sv +nc64bit +access+r ../../../rtl/ShiftRegister.v 3 | s3(15May2017:20:14:20): ncverilog +nclicq +sv +nc64bit +access+r ../../../rtl/ShiftRegister.v 4 | s4(15May2017:20:15:48): ncverilog +nclicq +sv +nc64bit +access+r ../../../rtl/ShiftRegister.v 5 | s5(15May2017:20:30:02): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 6 | s6(15May2017:20:31:10): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 7 | s7(15May2017:20:33:22): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 8 | s8(15May2017:20:33:41): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 9 | s9(15May2017:20:40:46): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 10 | s10(15May2017:20:44:20): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 11 | s11(15May2017:20:59:39): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 12 | s12(15May2017:21:01:10): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 13 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/sx_saved.sx: -------------------------------------------------------------------------------- 1 | ### Custom WaveView session file (version L-2016.06 build May 19, ) ### 2 | ### saved at 22:47:22 on Mon May 15 2017 ### 3 | wdf 0 "/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_ShiftRegister/ShiftRegister.vcd" load=used 4 | scalar list 5 | waveview_begin 1 stack offset=0 name_b=288 mntr_b=358 name_width=273 xcur=2.7e-07 mcur=3.85e-07 vc=cur-pnl "name=waveview 1" 6 | panel_begin digital pidx=0 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 radix=bin 7 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/clock" disp=show 8 | panel_end 9 | panel_begin digital pidx=1 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 radix=bin 10 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/reset" disp=show 11 | panel_end 12 | panel_begin digital pidx=2 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 radix=bin 13 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/load" disp=show 14 | panel_end 15 | panel_begin digital pidx=3 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 vecname=data_out[7-0] radix=hex bus_head=true 16 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][0]" disp=show 17 | line src=wdf lidx=1 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][1]" disp=show 18 | line src=wdf lidx=2 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][2]" disp=show 19 | line src=wdf lidx=3 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][3]" disp=show 20 | line src=wdf lidx=4 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][4]" disp=show 21 | line src=wdf lidx=5 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][5]" disp=show 22 | line src=wdf lidx=6 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][6]" disp=show 23 | line src=wdf lidx=7 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[7][7]" disp=show 24 | line src=wdf lidx=8 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][0]" disp=show 25 | line src=wdf lidx=9 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][1]" disp=show 26 | line src=wdf lidx=10 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][2]" disp=show 27 | line src=wdf lidx=11 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][3]" disp=show 28 | line src=wdf lidx=12 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][4]" disp=show 29 | line src=wdf lidx=13 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][5]" disp=show 30 | line src=wdf lidx=14 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][6]" disp=show 31 | line src=wdf lidx=15 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[6][7]" disp=show 32 | line src=wdf lidx=16 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][0]" disp=show 33 | line src=wdf lidx=17 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][1]" disp=show 34 | line src=wdf lidx=18 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][2]" disp=show 35 | line src=wdf lidx=19 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][3]" disp=show 36 | line src=wdf lidx=20 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][4]" disp=show 37 | line src=wdf lidx=21 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][5]" disp=show 38 | line src=wdf lidx=22 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][6]" disp=show 39 | line src=wdf lidx=23 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[5][7]" disp=show 40 | line src=wdf lidx=24 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][0]" disp=show 41 | line src=wdf lidx=25 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][1]" disp=show 42 | line src=wdf lidx=26 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][2]" disp=show 43 | line src=wdf lidx=27 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][3]" disp=show 44 | line src=wdf lidx=28 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][4]" disp=show 45 | line src=wdf lidx=29 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][5]" disp=show 46 | line src=wdf lidx=30 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][6]" disp=show 47 | line src=wdf lidx=31 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[4][7]" disp=show 48 | line src=wdf lidx=32 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][0]" disp=show 49 | line src=wdf lidx=33 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][1]" disp=show 50 | line src=wdf lidx=34 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][2]" disp=show 51 | line src=wdf lidx=35 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][3]" disp=show 52 | line src=wdf lidx=36 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][4]" disp=show 53 | line src=wdf lidx=37 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][5]" disp=show 54 | line src=wdf lidx=38 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][6]" disp=show 55 | line src=wdf lidx=39 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[3][7]" disp=show 56 | line src=wdf lidx=40 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][0]" disp=show 57 | line src=wdf lidx=41 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][1]" disp=show 58 | line src=wdf lidx=42 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][2]" disp=show 59 | line src=wdf lidx=43 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][3]" disp=show 60 | line src=wdf lidx=44 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][4]" disp=show 61 | line src=wdf lidx=45 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][5]" disp=show 62 | line src=wdf lidx=46 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][6]" disp=show 63 | line src=wdf lidx=47 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[2][7]" disp=show 64 | line src=wdf lidx=48 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][0]" disp=show 65 | line src=wdf lidx=49 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][1]" disp=show 66 | line src=wdf lidx=50 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][2]" disp=show 67 | line src=wdf lidx=51 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][3]" disp=show 68 | line src=wdf lidx=52 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][4]" disp=show 69 | line src=wdf lidx=53 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][5]" disp=show 70 | line src=wdf lidx=54 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][6]" disp=show 71 | line src=wdf lidx=55 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[1][7]" disp=show 72 | line src=wdf lidx=56 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][0]" disp=show 73 | line src=wdf lidx=57 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][1]" disp=show 74 | line src=wdf lidx=58 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][2]" disp=show 75 | line src=wdf lidx=59 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][3]" disp=show 76 | line src=wdf lidx=60 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][4]" disp=show 77 | line src=wdf lidx=61 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][5]" disp=show 78 | line src=wdf lidx=62 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][6]" disp=show 79 | line src=wdf lidx=63 fidx=0 "delim=/" sigtype=20 "name=tb_ShiftRegister/data_out[0][7]" disp=show 80 | panel_end 81 | panel_begin digital pidx=4 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 vecname=data_in[7][9][7:0] radix=dec 82 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/DUT/data_in[7][9][7:0]" disp=show 83 | panel_end 84 | panel_begin digital pidx=5 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 vecname=mem[7][9][7:0] radix=hex 85 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/DUT/mem[7][9][7:0]" disp=show 86 | panel_end 87 | panel_begin digital pidx=6 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 vecname=data_in[7][9][7:0] radix=hex 88 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/data_in[7][9][7:0]" disp=show 89 | panel_end 90 | panel_begin digital pidx=7 spath=name+file marker=on xlabel=sec xmin=3.74711226476314e-07 xmax=6.02569759896171e-07 radix=bin 91 | line src=wdf lidx=0 fidx=0 "delim=/" sigtype=9 "name=tb_ShiftRegister/shift" disp=show 92 | panel_end 93 | waveview_end 94 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_ShiftRegister/tb_ShiftRegister.v: -------------------------------------------------------------------------------- 1 | module tb_ShiftRegister #( 2 | parameter DATA_BITS = 8, 3 | parameter MATRIX_SIZE = 8, 4 | parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1 5 | ) (); 6 | 7 | reg clock; 8 | reg reset; 9 | reg load; 10 | reg shift; 11 | reg [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1]; 12 | wire [DATA_BITS-1:0] data_out [0:MATRIX_SIZE-1]; 13 | 14 | ShiftRegister #( 15 | .DATA_BITS(DATA_BITS), 16 | .MATRIX_SIZE(MATRIX_SIZE), 17 | .OUTPUT_SIZE(OUTPUT_SIZE) 18 | ) DUT ( 19 | .clock(clock), 20 | .reset(reset), 21 | .load(load), 22 | .shift(shift), 23 | .data_in(data_in), 24 | .data_out(data_out) 25 | ); 26 | 27 | integer count; 28 | initial begin 29 | clock = 1'b0; 30 | reset = 1'b0; 31 | load = 1'b0; 32 | shift = 1'b0; 33 | $dumpfile("ShiftRegister.vcd") ; 34 | $dumpvars; 35 | end 36 | 37 | always begin 38 | #5 clock = ~clock; 39 | #5 clock = ~clock; 40 | end 41 | 42 | always @(data_out) begin 43 | $display("data_out[0] at %0t",data_out[0],$time); 44 | $display("data_out[7] at %0t",data_out[7],$time); 45 | end 46 | 47 | initial begin 48 | 49 | #10 reset = 1'b1; 50 | #20 reset = 1'b0; 51 | 52 | #200 53 | 54 | #10 load = 1'b1; 55 | #30 56 | count=0; 57 | for (integer i=0;i worklib ) 6 | define ELAB_SNAPSHOT 7 | define SNAPSHOT worklib.XdataSetup:v 8 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncelab.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -noshowtop 10 | -LICQUEUE 11 | -ACCESS 12 | +r 13 | -MESSAGES 14 | -XLMODE 15 | ./INCA_libs/irun.lnx8664.15.22.nc 16 | -RUNMODE 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 21 | -WORK 22 | worklib 23 | -HASXLMODE 24 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncelab.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncelab.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -ACCESS 6 | +r 7 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncsim.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494916726 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncsim.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncsim_restart.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494916726 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -XLNAME 28 | ./INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_5315 29 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncsim_restart.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncverilog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -f 10 | include.f 11 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -XLMODE 6 | ./INCA_libs/irun.lnx8664.15.22.nc 7 | -RUNMODE 8 | -sv 9 | ../../../rtl/SystolicDataSetupRow.v 10 | ../../../rtl/XdataSetup.v 11 | ../../../rtl/ShiftRegister.v 12 | -CDSLIB 13 | ./INCA_libs/irun.lnx8664.15.22.nc/cdsrun.lib 14 | -HDLVAR 15 | ./INCA_libs/irun.lnx8664.15.22.nc/hdlrun.var 16 | -MESSAGES 17 | -UPDATE 18 | -XLLIBSTORE 19 | ./INCA_libs/irun.lnx8664.15.22.nc/xllibs 20 | -ALLOWUNBOUND 21 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.files: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/SystolicDataSetupRow.v 6 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/XdataSetup.v 7 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 8 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/ncvlog.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -sv 6 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_5315_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_5315_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.nclib.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.nclib.lock -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.ncrun.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.ncrun.lock -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.ncv.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.ncv.lock -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/.timestamp.ts: -------------------------------------------------------------------------------- 1 | 1494829761 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/SystolicDataSetupRow.v 2 | 1494916657 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/XdataSetup.v 3 | 1494906173 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 4 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/OVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/UVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/bind.lst.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/bind.lst.lnx8664 -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/cds.lib: -------------------------------------------------------------------------------- 1 | include ./cdsrun.lib 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/files.ts: -------------------------------------------------------------------------------- 1 | 1494829761 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/SystolicDataSetupRow.v 2 | 1494916657 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/XdataSetup.v 3 | 1494906173 /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 4 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/hdl.var: -------------------------------------------------------------------------------- 1 | define NCSIMRC ( /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/ncsimrc, ~/.ncsimrc ) 2 | include ./hdlrun.var 3 | define SNAPSHOT worklib.XdataSetup:v 4 | DEFINE RUNMODEDEFAULT 1 5 | DEFINE LIB_MAP ( + => worklib ) 6 | define ELAB_SNAPSHOT 7 | define SNAPSHOT worklib.XdataSetup:v 8 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncelab.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -noshowtop 10 | -LICQUEUE 11 | -ACCESS 12 | +r 13 | -MESSAGES 14 | -XLMODE 15 | ./INCA_libs/irun.lnx8664.15.22.nc 16 | -RUNMODE 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 21 | -WORK 22 | worklib 23 | -HASXLMODE 24 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncelab.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncelab.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -ACCESS 6 | +r 7 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncsim.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494916726 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncsim.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncsim_restart.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -LICQUEUE 10 | -MESSAGES 11 | +EMGRLOG 12 | ncverilog.log 13 | -XLSTIME 14 | 1494916726 15 | -XLKEEP 16 | -XLMODE 17 | ./INCA_libs/irun.lnx8664.15.22.nc 18 | -RUNMODE 19 | -CDSLIB 20 | ./INCA_libs/irun.lnx8664.15.22.nc/cds.lib 21 | -HDLVAR 22 | ./INCA_libs/irun.lnx8664.15.22.nc/hdl.var 23 | -XLNAME 24 | ncverilog 25 | -XLVERSION 26 | "TOOL: ncverilog 15.22-s016" 27 | -XLNAME 28 | ./INCA_libs/irun.lnx8664.15.22.nc/scv-asramkum01.csg.apple.com_5315 29 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncsim_restart.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncverilog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | +nclicq 6 | +sv 7 | +nc64bit 8 | +access+r 9 | -f 10 | include.f 11 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncvlog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -XLMODE 6 | ./INCA_libs/irun.lnx8664.15.22.nc 7 | -RUNMODE 8 | -sv 9 | ../../../rtl/SystolicDataSetupRow.v 10 | ../../../rtl/XdataSetup.v 11 | ../../../rtl/ShiftRegister.v 12 | -CDSLIB 13 | ./INCA_libs/irun.lnx8664.15.22.nc/cdsrun.lib 14 | -HDLVAR 15 | ./INCA_libs/irun.lnx8664.15.22.nc/hdlrun.var 16 | -MESSAGES 17 | -UPDATE 18 | -XLLIBSTORE 19 | ./INCA_libs/irun.lnx8664.15.22.nc/xllibs 20 | -ALLOWUNBOUND 21 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncvlog.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: ncverilog 4 | # Do not modify this file 5 | # 6 | #<< : <#3 ncverilog:/site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/tests/verilog/tb_XdataSetup/INCA_libs/irun.lnx8664.15.22.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.22.nc>#> 7 | setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.22.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncvlog.files: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/SystolicDataSetupRow.v 6 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/XdataSetup.v 7 | /site/scv/org-seg-projects-osprey-scv-new-users-asramkum-safe1/CS231n/Project/cs231n-project/src/rtl/ShiftRegister.v 8 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/ncvlog.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: ncverilog 3 | // Do not modify this file 4 | // 5 | -sv 6 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_5315_cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /org/seg/tools/eda/cadence/incisive/15.22.016/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/snap.nc/scv-asramkum01.csg.apple.com_5315_hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | DEF => verilog\ 62 | ) 63 | define VIEW_MAP ( $VIEW_MAP, * => verilog) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | ) 86 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/worklib/.cdsvmod: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_XdataSetup/INCA_libs/worklib/.cdsvmod -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/worklib/.inca.db.061.lnx8664: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/worklib/cdsinfo.tag: -------------------------------------------------------------------------------- 1 | CDSLIBRARY 2 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/INCA_libs/worklib/inca.lnx8664.061.pak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kkiningh/cs231n-project/5f227e51f2c341b6a3157151aa8246a032966f16/src/tests/verilog/tb_XdataSetup/INCA_libs/worklib/inca.lnx8664.061.pak -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/include.f: -------------------------------------------------------------------------------- 1 | ../../../rtl/SystolicDataSetupRow.v 2 | ../../../rtl/XdataSetup.v 3 | ../../../rtl/ShiftRegister.v 4 | -------------------------------------------------------------------------------- /src/tests/verilog/tb_XdataSetup/ncverilog.history: -------------------------------------------------------------------------------- 1 | s1(15May2017:23:37:13): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 2 | s2(15May2017:23:37:41): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 3 | s3(15May2017:23:38:46): ncverilog +nclicq +sv +nc64bit +access+r -f include.f 4 | -------------------------------------------------------------------------------- /src/tf/collect_model_data.py: -------------------------------------------------------------------------------- 1 | import keras 2 | import time 3 | import numpy as np 4 | from keras import backend as K 5 | from keras.applications.inception_v3 import InceptionV3 6 | from keras.applications.vgg16 import VGG16 7 | from keras.applications.resnet50 import ResNet50 8 | from keras.layers.normalization import BatchNormalization 9 | 10 | from keras_profiling import keras_profiling_hack 11 | 12 | def benchmark_model(model): 13 | for layer in model.layers: 14 | layer.trainable = False 15 | model.compile(optimizer="sgd", loss="mse") 16 | 17 | batch_size = 64 18 | batch_shape = (batch_size,) + model.input_shape[1:] 19 | batch = np.random.randn(*batch_shape) 20 | 21 | print("Benchmarking") 22 | # Run once to make sure the GPU is ready. 23 | model.predict_on_batch(batch) 24 | 25 | N = 25 26 | start = time.time() 27 | for _ in range(N): 28 | model.predict_on_batch(batch) 29 | end = time.time() 30 | 31 | print( 32 | "Ran {} frames in {}s, at {} fps".format(N * batch_size, end - start, N * batch_size / (end - start))) 33 | 34 | def show_model_data(): 35 | K.set_image_data_format("channels_last") 36 | # K.set_image_data_format("channels_first") 37 | #keras_profiling_hack() 38 | inception = InceptionV3() 39 | inception.summary() 40 | 41 | vgg16 = VGG16() 42 | vgg16.summary() 43 | 44 | resnet = ResNet50() 45 | resnet.summary() 46 | 47 | print("Inception V3") 48 | benchmark_model(inception) 49 | 50 | print("VGG16") 51 | benchmark_model(vgg16) 52 | 53 | print("ResNet50") 54 | benchmark_model(resnet) 55 | 56 | 57 | if __name__ == "__main__": 58 | show_model_data() 59 | -------------------------------------------------------------------------------- /src/tf/keras_profiling.py: -------------------------------------------------------------------------------- 1 | import os 2 | import time 3 | from tempfile import mkdtemp 4 | 5 | import keras 6 | from keras import backend as K 7 | import tensorflow as tf 8 | from tensorflow.python.client import timeline 9 | 10 | class ProfiledSession(tf.Session): 11 | def __init__(self, *args, **kwargs): 12 | super(ProfiledSession, self).__init__(*args, **kwargs) 13 | self._num = 0 14 | self._timeline_dir = None 15 | 16 | def run(self, *args, **kwargs): 17 | if "options" not in kwargs: 18 | kwargs["options"] = tf.RunOptions(trace_level=tf.RunOptions.FULL_TRACE) 19 | 20 | assert "run_metadata" not in kwargs, "Profiling would overwrite existing metadata" 21 | run_metadata = tf.RunMetadata() 22 | kwargs["run_metadata"] = run_metadata 23 | 24 | before = time.time() 25 | result = super(ProfiledSession, self).run(*args, **kwargs) 26 | after = time.time() 27 | 28 | print("Run took {}s".format(after - before)) 29 | 30 | # Create the Timeline object, and write it to a json 31 | tl = timeline.Timeline(run_metadata.step_stats) 32 | ctf = tl.generate_chrome_trace_format() 33 | 34 | if self._timeline_dir is None: 35 | self._timeline_dir = mkdtemp() 36 | 37 | timeline_path = os.path.join(self._timeline_dir, "timeline_{}.json".format(self._num)) 38 | self._num += 1 39 | with open(timeline_path, 'w') as f: 40 | f.write(ctf) 41 | print("Wrote timeline to {}".format(timeline_path)) 42 | 43 | return result 44 | 45 | 46 | def keras_profiling_hack(): 47 | """Call this method before loading or building a Keras model to profile its usage. 48 | 49 | Outputs can be viewed with chrome://tracing. 50 | """ 51 | curr_session = K.get_session() 52 | new_session = ProfiledSession(config=curr_session._config) 53 | curr_session.close() 54 | K.set_session(new_session) 55 | keras.backend.tensorflow_backend._initialize_variables() 56 | -------------------------------------------------------------------------------- /src/tf/test_quantization.py: -------------------------------------------------------------------------------- 1 | import numpy as np 2 | 3 | def to_8(M_real, scale, offset): 4 | result = (M_real / scale - offset).round() 5 | result[result < 0] = 0 6 | result[result > 255] = 255 7 | return result.astype(np.uint8) 8 | 9 | def gemm8_32(l, r): 10 | assert l.dtype == np.uint8 11 | assert r.dtype == np.uint8 12 | return np.dot(l.astype(np.uint32), r.astype(np.uint32)) 13 | 14 | def example(): 15 | lhs_real = np.array([ 16 | [-0.1, 0.4], 17 | [0.1, 0.2], 18 | ]) 19 | lhs_scale = 1. / 128 20 | lhs_offset = -128 21 | 22 | rhs_real = np.array([ 23 | [30.], 24 | [5.], 25 | ]) 26 | rhs_scale = 1. 27 | rhs_offset = 5 28 | 29 | result_scale = 1. 30 | result_offset = 0. 31 | 32 | lhs8 = to_8(lhs_real, lhs_scale, lhs_offset) 33 | rhs8 = to_8(rhs_real, rhs_scale, rhs_offset) 34 | print("As 8bit: {}, {}".format(lhs8, rhs8)) 35 | 36 | P = np.ones(lhs8.shape, dtype=np.uint32) 37 | Q = np.ones(rhs8.shape, dtype=np.uint32) 38 | 39 | lhs_offset_16 = np.int8(lhs_offset) 40 | rhs_offset_16 = np.int8(rhs_offset) 41 | 42 | terms = ( 43 | gemm8_32(lhs8, rhs8), 44 | lhs_offset_16 * np.dot(P, rhs8), 45 | np.dot(lhs8, Q * rhs_offset_16), 46 | lhs_offset_16 * (rhs_offset_16 * np.dot(P, Q))) 47 | print("Terms: {}".format(" + ".join(map(str, terms)))) 48 | 49 | sum_terms = sum(terms) 50 | print("Sum of terms: {}".format(sum_terms)) 51 | 52 | result_real = (lhs_scale * rhs_scale) * sum_terms 53 | print("(Q result, FP result): {}\n{}".format(result_real, np.dot(lhs_real, rhs_real))) 54 | 55 | result = result_offset + (lhs_scale * rhs_scale / result_scale) * sum_terms 56 | print("Final result: {}".format(result)) 57 | 58 | example() 59 | -------------------------------------------------------------------------------- /syn/scripts/common/common_setup.tcl: -------------------------------------------------------------------------------- 1 | puts "Setting up common variables\n" 2 | 3 | # Name of the top-level design 4 | set DESIGN_NAME "SystolicArray" 5 | 6 | # Absolute path prefix for design data. 7 | set DESIGN_REF_DATA_PATH "" 8 | 9 | # List of hierarchical block design names "DesignA DesignB" 10 | set HIERARCHICAL_DESIGNS "" 11 | 12 | # List of hierarchical block cell instance names "u_DesignA u_DesignB" 13 | set HIERARCHICAL_CELLS "" 14 | 15 | # Setup the technology library files 16 | source -echo -verbose "scripts/common/saed32.tcl" 17 | 18 | # Setup the RTL files 19 | source -echo -verbose "scripts/common/rtl.tcl" 20 | -------------------------------------------------------------------------------- /syn/scripts/common/dont_use.tcl: -------------------------------------------------------------------------------- 1 | remove_attribute [get_lib_cells */*ISO*] dont_use 2 | remove_attribute [get_lib_cells */*ISO*] dont_touch 3 | remove_attribute [get_lib_cells */*HEAD*] dont_touch 4 | remove_attribute [get_lib_cells */*HEAD*] dont_use 5 | remove_attribute [get_lib_cells */*LS*] dont_touch 6 | remove_attribute [get_lib_cells */*LS*] dont_use 7 | remove_attribute [get_lib_cells */*AO*] dont_touch 8 | remove_attribute [get_lib_cells */*AO*] dont_use 9 | remove_attribute -quiet [get_lib_cells */* -filter {is_a_test_cell == true}] dont_use 10 | set_attribute [get_lib_cells */RSDFFARX*_HVT*] dont_use true 11 | set_attribute [get_lib_cells */RSDFFARX*_HVT*] dont_touch true 12 | -------------------------------------------------------------------------------- /syn/scripts/common/rtl.tcl: -------------------------------------------------------------------------------- 1 | # Note: When autoread is used ${RTL_SOURCE_FILES} can include a list of 2 | # both directories and files. 3 | 4 | set RTL_SOURCE_FILES "../src/rtl/Top.sv" 5 | -------------------------------------------------------------------------------- /syn/scripts/common/saed32.tcl: -------------------------------------------------------------------------------- 1 | puts "Using Synopsys EDK Gate Libraries (6M, 32nm)" 2 | 3 | # Set the SAED EDK32 path 4 | if {[info exists ::env(SAED32_EDK_PATH)]} { 5 | set SAED32_EDK_PATH $::env(SAED32_EDK_PATH) 6 | } else { 7 | set SAED32_EDK_PATH "/afs/ir.stanford.edu/class/ee/synopsys/physical/SAED32_EDK" 8 | puts "Warning: Path to SAED32 EDK was not specified in environment." 9 | puts " Defaulting to ${SAED32_EDK_PATH}" 10 | } 11 | 12 | # This script uses Tcl arrays to describe technology constants. 13 | # Standard library cells are keyed on process corner and voltage. 14 | # Note that not all corners are compatible with all voltages (see table below). 15 | # 16 | # Variable | Description | Values 17 | # -- 18 | # $transistor | Transistor n+p process corner | ss | tt | ff 19 | # $voltage | Primary voltage | 0p70v | 0p78v | 0p85v 20 | # | 0p75v | 0p85v | 0p95v 21 | # | 0p95v | 1p05v | 1p16v 22 | # 23 | # Additionally, you can also key on threshold voltage (low, regular, or high) 24 | # and tempurature. 25 | # 26 | # Variable | Description | Values 27 | # -- 28 | # $threshold | Transistor threshold | lvt, rvt, hvt 29 | # $temperature | Operating temperature | 125c, 25c, n40c 30 | 31 | set slow_corner_pvt ss_0p70v_125c 32 | set typical_corner_pvt tt_0p85v_25c 33 | set fast_corner_pvt ff_1p16v_n40c 34 | 35 | # Set the path of the cell libraries 36 | set DESIGN_REF_PATH ${SAED32_EDK_PATH} 37 | set DESIGN_REF_TECH_PATH ${SAED32_EDK_PATH}/tech 38 | 39 | # Setup some helper variables that map to the set of libraries we want to use 40 | set hvt_libs " \ 41 | saed32hvt_tt0p78v125c.db \ 42 | saed32hvt_tt0p85v125c.db \ 43 | saed32hvt_tt1p05v125c.db \ 44 | saed32hvt_ulvl_tt0p78v125c_i0p78v.db \ 45 | saed32hvt_ulvl_tt0p85v125c_i0p85v.db \ 46 | saed32hvt_ulvl_tt1p05v125c_i0p78v.db \ 47 | saed32hvt_dlvl_tt0p78v125c_i0p78v.db \ 48 | saed32hvt_dlvl_tt0p85v125c_i0p85v.db \ 49 | saed32hvt_pg_tt0p78v125c.db \ 50 | saed32hvt_pg_tt0p85v125c.db \ 51 | saed32hvt_pg_tt1p05v125c.db \ 52 | " 53 | 54 | set rvt_libs " \ 55 | saed32rvt_tt0p78v125c.db \ 56 | saed32rvt_tt0p85v125c.db \ 57 | saed32rvt_tt1p05v125c.db \ 58 | saed32rvt_ulvl_tt0p78v125c_i0p78v.db \ 59 | saed32rvt_ulvl_tt0p85v125c_i0p85v.db \ 60 | saed32rvt_ulvl_tt1p05v125c_i0p78v.db \ 61 | saed32rvt_dlvl_tt0p78v125c_i0p78v.db \ 62 | saed32rvt_dlvl_tt0p85v125c_i0p85v.db \ 63 | saed32rvt_pg_tt0p78v125c.db \ 64 | saed32rvt_pg_tt0p85v125c.db \ 65 | saed32rvt_pg_tt1p05v125c.db \ 66 | " 67 | 68 | set lvt_libs " \ 69 | saed32lvt_tt0p78v125c.db \ 70 | saed32lvt_tt0p85v125c.db \ 71 | saed32lvt_tt1p05v125c.db 72 | saed32lvt_ulvl_tt0p78v125c_i0p78v.db \ 73 | saed32lvt_ulvl_tt0p85v125c_i0p85v.db \ 74 | saed32lvt_ulvl_tt1p05v125c_i0p78v.db \ 75 | saed32lvt_dlvl_tt0p78v125c_i0p78v.db \ 76 | saed32lvt_dlvl_tt0p85v125c_i0p85v.db \ 77 | saed32lvt_pg_tt0p78v125c.db \ 78 | saed32lvt_pg_tt0p85v125c.db \ 79 | saed32lvt_pg_tt1p05v125c.db \ 80 | " 81 | 82 | set mem_libs " \ 83 | saed32sram_tt1p05v125c.db 84 | " 85 | 86 | set ADDITIONAL_SEARCH_PATH " \ 87 | ${DESIGN_REF_PATH}/lib/stdcell_rvt/db_nldm \ 88 | ${DESIGN_REF_PATH}/lib/stdcell_hvt/db_nldm \ 89 | ${DESIGN_REF_PATH}/lib/stdcell_lvt/db_nldm \ 90 | ${DESIGN_REF_PATH}/lib/io_std/db_nldm/ \ 91 | ${DESIGN_REF_PATH}/lib/sram/db_nldm/ \ 92 | " 93 | 94 | # Target technology logical libraries 95 | set TARGET_LIBRARY_FILES "$hvt_libs $rvt_libs $lvt_libs" 96 | 97 | # Extra link logical libraries (e.g. libraries that can be referenced but are 98 | # not targeted) that are not included in TARGET_LIBRARY_FILES 99 | set ADDITIONAL_LINK_LIB_FILES "$mem_libs" 100 | 101 | # List of max-min library paris "max1 min1 max2 min2 ..." 102 | set MIN_LIBRARY_FILES " \ 103 | saed32rvt_ff1p16v125c.db \ 104 | saed32rvt_ff1p16vn40c.db \ 105 | saed32lvt_ff1p16v125c.db \ 106 | saed32lvt_ff1p16vn40c.db \ 107 | saed32hvt_ff1p16v125c.db \ 108 | saed32hvt_ff1p16vn40c.db \ 109 | saed32rvt_pg_ff1p16v125c.db \ 110 | saed32rvt_pg_ff1p16vn40c.db \ 111 | saed32lvt_pg_ff1p16v125c.db \ 112 | saed32lvt_pg_ff1p16vn40c.db \ 113 | saed32hvt_pg_ff1p16v125c.db \ 114 | saed32hvt_pg_ff1p16vn40c.db \ 115 | saed32sram_ff1p16v125c.db \ 116 | saed32sram_ff1p16vn40c.db \ 117 | saed32sram_ss0p95v125c.db \ 118 | saed32sram_tt1p05v25c.db \ 119 | saed32io_wb_ff1p16v125c_2p75v.db \ 120 | saed32io_wb_ff1p16vn40c_2p75v.db" 121 | 122 | # Milkyway reference libraries (Include IC Compiler ILMs here) 123 | set MW_REFERENCE_LIB_DIRS " \ 124 | ${DESIGN_REF_PATH}/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m \ 125 | ${DESIGN_REF_PATH}/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m \ 126 | ${DESIGN_REF_PATH}/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m \ 127 | ${DESIGN_REF_PATH}/lib/sram/milkyway/SRAM32NM \ 128 | ${DESIGN_REF_PATH}/lib/io_std/milkyway/saed32_io_wb \ 129 | " 130 | 131 | # Reference Control File to define the MW reference libraries 132 | set MW_REFERENCE_CONTROL_FILE "" 133 | 134 | # Milkyway technology file 135 | set TECH_FILE "${DESIGN_REF_TECH_PATH}/milkyway/saed32nm_1p9m_mw.tf" 136 | 137 | # Mapping file for TLUplus 138 | set MAP_FILE "${DESIGN_REF_TECH_PATH}/star_rcxt/saed32nm_tf_itf_tluplus.map" 139 | 140 | # Max conditions 141 | set TLUPLUS_MAX_FILE "${DESIGN_REF_TECH_PATH}/star_rcxt/saed32nm_1p9m_Cmax.tluplus" 142 | 143 | # Min conditions 144 | set TLUPLUS_MIN_FILE "${DESIGN_REF_TECH_PATH}/star_rcxt/saed32nm_1p9m_Cmin.tluplus" 145 | 146 | # Name of power/ground ports/nets 147 | set MW_POWER_NET "VDD" 148 | set MW_POWER_PORT "VDD" 149 | set MW_GROUND_NET "VSS" 150 | set MW_GROUND_PORT "VSS" 151 | 152 | # Max/Min layers for routing 153 | set MIN_ROUTING_LAYER "M2" 154 | set MAX_ROUTING_LAYER "M8" 155 | 156 | #### Don't Use File 157 | # Tcl file to prevent Synopsys from considering irrelevent or unneeded library 158 | # components. 159 | set LIBRARY_DONT_USE_FILE "" 160 | set LIBRARY_DONT_USE_PRE_COMPILE_LIST "" 161 | set LIBRARY_DONT_USE_PRE_INCR_COMPILE_LIST "" 162 | 163 | ########################################################################################## 164 | # Multi-Voltage Common Variables 165 | # 166 | # Define the following MV common variables for the RM scripts for multi-voltage flows. 167 | # Use as few or as many of the following definitions as needed by your design. 168 | ########################################################################################## 169 | 170 | set PD1 "" ;# Name of power domain/voltage area 1 171 | set PD1_CELLS "" ;# Instances to include in power domain/voltage area 1 172 | set VA1_COORDINATES {} ;# Coordinates for voltage area 1 173 | set MW_POWER_NET1 "VDD1" ;# Power net for voltage area 1 174 | set MW_POWER_PORT1 "VDD" ;# Power port for voltage area 1 175 | 176 | set PD2 "" ;# Name of power domain/voltage area 2 177 | set PD2_CELLS "" ;# Instances to include in power domain/voltage area 2 178 | set VA2_COORDINATES {} ;# Coordinates for voltage area 2 179 | set MW_POWER_NET2 "VDD2" ;# Power net for voltage area 2 180 | set MW_POWER_PORT2 "VDD" ;# Power port for voltage area 2 181 | 182 | set PD3 "" ;# Name of power domain/voltage area 3 183 | set PD3_CELLS "" ;# Instances to include in power domain/voltage area 3 184 | set VA3_COORDINATES {} ;# Coordinates for voltage area 3 185 | set MW_POWER_NET3 "VDD3" ;# Power net for voltage area 3 186 | set MW_POWER_PORT3 "VDD" ;# Power port for voltage area 3 187 | 188 | set PD4 "" ;# Name of power domain/voltage area 4 189 | set PD4_CELLS "" ;# Instances to include in power domain/voltage area 4 190 | set VA4_COORDINATES {} ;# Coordinates for voltage area 4 191 | set MW_POWER_NET4 "VDD4" ;# Power net for voltage area 4 192 | set MW_POWER_PORT4 "VDD" ;# Power port for voltage area 4 193 | 194 | puts "Finished loading Synopsys EDK" 195 | -------------------------------------------------------------------------------- /syn/scripts/dc/dc_setup.tcl: -------------------------------------------------------------------------------- 1 | source -echo -verbose "scripts/common/common_setup.tcl" 2 | source -echo -verbose "scripts/dc/dc_setup_filenames.tcl" 3 | 4 | puts "Running DC Setup\n" 5 | 6 | ########################################################################################## 7 | # Hierarchical Flow Blocks 8 | # 9 | # If you are performing a hierarchical flow, define the hierarchical designs here. 10 | # List the reference names of the hierarchical blocks. Cell instance names will 11 | # be automatically derived from the design names provided. 12 | # 13 | # Note: These designs are expected to be unique. There should not be multiple 14 | # instantiations of physical hierarchical blocks. 15 | # 16 | ########################################################################################## 17 | 18 | # Each of the hierarchical designs specified in ${HIERARCHICAL_DESIGNS} in the 19 | # common_setup.tcl file should be added to only one of the lists below: 20 | 21 | # List of Design Compiler hierarchical design names (.ddc will be read) 22 | set DDC_HIER_DESIGNS "" 23 | 24 | # List of Design Compiler block abstraction hierarchical designs (.ddc will be 25 | # read) without transparent interface optimization 26 | set DC_BLOCK_ABSTRACTION_DESIGNS "" 27 | 28 | # List of Design Compiler block abstraction hierarchical designs 29 | # with transparent interface optimization 30 | set DC_BLOCK_ABSTRACTION_DESIGNS_TIO "" 31 | 32 | # List of IC Compiler block abstraction hierarchical design names (Milkyway will be read) 33 | set ICC_BLOCK_ABSTRACTION_DESIGNS "" 34 | 35 | ################################################################################# 36 | # Setup Variables 37 | # 38 | # Portions of dc_setup.tcl may be used by other tools so program name checks 39 | # are performed where necessary. 40 | ################################################################################# 41 | 42 | if {$synopsys_program_name != "mvrc" && 43 | $synopsys_program_name != "vsi" && 44 | $synopsys_program_name != "vcst"} { 45 | 46 | # The following setting removes new variable info messages from the end of the log file 47 | set_app_var sh_new_variable_message false 48 | } 49 | 50 | if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell"} { 51 | #### 52 | # Design Compiler and DC Explorer Setup Variables 53 | #### 54 | 55 | # Use the set_host_options command to enable multicore optimization to improve runtime. 56 | set_host_options -max_cores 8 57 | 58 | # Change alib_library_analysis_path to point to a central cache of analyzed libraries 59 | # to save runtime and disk space. The following setting only reflects the 60 | # default value and should be changed to a central location for best results. 61 | set_app_var alib_library_analysis_path . 62 | 63 | # In cases where RTL has VHDL generate loops or SystemVerilog structs, switching 64 | # activity annotation from SAIF may be rejected, the following variable setting 65 | # improves SAIF annotation, by making sure that synthesis object names follow same 66 | # naming convention as used by RTL simulation. 67 | set_app_var hdlin_enable_upf_compatible_naming true 68 | 69 | # By default the tool will create supply set handles. If your UPF has domain dependent 70 | # supply nets, please uncomment the following line: 71 | # set_app_var upf_create_implicit_supply_sets false 72 | 73 | # Add any additional Design Compiler variables needed here 74 | 75 | ################################################################################# 76 | # DC Explorer Specific Setup Variables 77 | ################################################################################# 78 | 79 | if {[shell_is_in_exploration_mode]} { 80 | # Uncomment the following setting to use top-level signal ports instead of a 81 | # isolation power controller. 82 | # set_app_var upf_auto_iso_enable_source top_level_port 83 | 84 | # Uncomment the following setting to allow DC Explorer to perform optimization with 85 | # physical design data. 86 | # set_app_var de_enable_physical_flow true 87 | 88 | # Add any additional DC Explorer variables needed here 89 | } 90 | } 91 | 92 | # Type of optimization to perform 93 | set OPTIMIZATION_FLOW "hplp" 94 | 95 | # Location of design and analysis files from output of Design Compiler 96 | set REPORTS_DIR "dc/work/reports" 97 | set RESULTS_DIR "dc/work/results" 98 | 99 | file mkdir ${REPORTS_DIR} 100 | file mkdir ${RESULTS_DIR} 101 | 102 | ################################################################################# 103 | # Search Path Setup 104 | # 105 | # Set up the search path to find the libraries and design files. 106 | ################################################################################# 107 | set_app_var search_path ". ${ADDITIONAL_SEARCH_PATH} $search_path" 108 | 109 | # For a hierarchical flow, add the following directory to the search path to 110 | # find the floorplan, voltage area definitions, and SDC budgets from IC Compiler. 111 | # Note: The floorplan files from IC Compiler are named ${DESIGN_NAME}.DCT.def and 112 | # ${DESIGN_NAME}.DCT.fp. You should choose your floorplan file and name it 113 | # to ${DESIGN_NAME}.def or ${DESIGN_NAME}.fp for Design Compiler. 114 | lappend search_path ./icc/work/DC 115 | 116 | # For a hierarchical flow, add the block-level results directories to the 117 | # search path to find the block-level design files. 118 | set HIER_DESIGNS "\ 119 | ${DDC_HIER_DESIGNS} \ 120 | ${DC_BLOCK_ABSTRACTION_DESIGNS} \ 121 | ${DC_BLOCK_ABSTRACTION_DESIGNS_TIO} \ 122 | " 123 | 124 | foreach design $HIER_DESIGNS { 125 | lappend search_path "../${design}/dc/work/results" 126 | } 127 | 128 | # For a hierarchical UPF flow, add the results directory to the search path for 129 | # Formality to find the output UPF files. 130 | lappend search_path ${RESULTS_DIR} 131 | 132 | ################################################################################# 133 | # Library Setup 134 | # 135 | # This section is designed to work with the settings from common_setup.tcl 136 | # without any additional modification. 137 | ################################################################################# 138 | 139 | if {$synopsys_program_name != "mvrc" && 140 | $synopsys_program_name != "vsi" && 141 | $synopsys_program_name != "vcst"} { 142 | 143 | # Milkyway variable settings 144 | 145 | # Make sure to define the Milkyway library variable 146 | # mw_design_library, it is needed by write_milkyway command 147 | 148 | set mw_reference_library ${MW_REFERENCE_LIB_DIRS} 149 | set mw_design_library ${RESULTS_DIR}/${DCRM_MW_LIBRARY_NAME} 150 | 151 | set mw_site_name_mapping { {CORE unit} {Core unit} {core unit} } 152 | } 153 | 154 | if {$synopsys_program_name == "mvrc"} { 155 | set_app_var link_library "$TARGET_LIBRARY_FILES $ADDITIONAL_LINK_LIB_FILES" 156 | } 157 | 158 | if {$synopsys_program_name == "vsi" || $synopsys_program_name == "vcst"} { 159 | set_app_var link_library "$TARGET_LIBRARY_FILES $ADDITIONAL_LINK_LIB_FILES" 160 | } 161 | 162 | if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell"} { 163 | # The target_library is the set of cells we want the tools to emit after 164 | # synthesis (e.g that our RTL gets "mapped to". This should be the gates 165 | # that can actually be physically manufactured in our process. 166 | set_app_var target_library ${TARGET_LIBRARY_FILES} 167 | 168 | # The synthetic_library is the name of the Designware libraries to use. 169 | # 170 | # Designware libraries are special, highly optimized implementations of 171 | # common operations (e.g *, +, registers, etc) that the Synopsys tool 172 | # can map to during optimization passes. 173 | set_app_var synthetic_library "dw_foundation.sldb" 174 | 175 | # The link_library tells the Synopsys tools where to look for the definitions 176 | # of module instances. 177 | # 178 | # The "*" at the begining tells the tools to first look in memory (ie. in the 179 | # previously analyzed Verilog files). 180 | set_app_var link_library \ 181 | "* $target_library $ADDITIONAL_LINK_LIB_FILES $synthetic_library" 182 | 183 | # Setup min libraries if they exist 184 | foreach {max_library min_library} $MIN_LIBRARY_FILES { 185 | set_min_library $max_library -min_version $min_library 186 | } 187 | 188 | # Set the variable to use Verilog libraries for Test Design Rule Checking 189 | # (See dc.tcl for details) 190 | # set_app_var test_simulation_library 191 | 192 | if {[shell_is_in_topographical_mode]} { 193 | # If we want extended support for 4095 layers, uncomment the following line 194 | # before creating the Milkyway library. 195 | # Note that this is permanent and cannot be reverted. 196 | # extend_mw_layers 197 | 198 | # Only create new Milyway design library if it doesn't exist 199 | if {![file isdirectory $mw_design_library]} { 200 | create_mw_lib \ 201 | -technology $TECH_FILE \ 202 | -mw_reference_library $mw_reference_library \ 203 | $mw_design_library 204 | } else { 205 | # If it does exist, make sure it's consistant with reference library 206 | set_mw_lib_reference $mw_design_library \ 207 | -mw_reference_library $mw_reference_library 208 | } 209 | 210 | open_mw_lib $mw_design_library 211 | 212 | set_check_library_options -upf 213 | check_library > ${REPORTS_DIR}/${DCRM_CHECK_LIBRARY_REPORT} 214 | 215 | set_tlu_plus_files \ 216 | -max_tluplus $TLUPLUS_MAX_FILE \ 217 | -min_tluplus $TLUPLUS_MIN_FILE \ 218 | -tech2itf_map $MAP_FILE 219 | 220 | check_tlu_plus_files 221 | } 222 | 223 | #### 224 | # Library modifications (apply after libraries are loaded 225 | #### 226 | if {[file exists [which ${LIBRARY_DONT_USE_FILE}]]} { 227 | source -echo -verbose ${LIBRARY_DONT_USE_FILE} 228 | } else { 229 | puts "Library Don't Use file not found: ${LIBRARY_DONT_USE_FILE}" 230 | } 231 | 232 | # Tcl file for Synopsys Logic Library don't use list 233 | set LIBRARY_DONT_USE_PRE_COMPILE_LIST "scripts/dc/snpsll_hpdu_synth.tcl" 234 | } 235 | 236 | puts "End DC Setup" 237 | -------------------------------------------------------------------------------- /syn/scripts/dc/dc_setup_filenames.tcl: -------------------------------------------------------------------------------- 1 | ################################################################################# 2 | # General Flow Files 3 | ################################################################################# 4 | 5 | ########################## 6 | # Milkyway Library Names # 7 | ########################## 8 | 9 | set DCRM_MW_LIBRARY_NAME ${DESIGN_NAME}_LIB 10 | set DCRM_FINAL_MW_CEL_NAME ${DESIGN_NAME}_DCT 11 | 12 | ############### 13 | # Input Files # 14 | ############### 15 | 16 | set DCRM_SDC_INPUT_FILE ${DESIGN_NAME}.sdc 17 | set DCRM_CONSTRAINTS_INPUT_FILE ${DESIGN_NAME}.constraints.tcl 18 | 19 | ########### 20 | # Reports # 21 | ########### 22 | 23 | set DCRM_CHECK_LIBRARY_REPORT ${DESIGN_NAME}.check_library.rpt 24 | 25 | set DCRM_CONSISTENCY_CHECK_ENV_FILE ${DESIGN_NAME}.compile_ultra.env 26 | set DCRM_CHECK_DESIGN_REPORT ${DESIGN_NAME}.check_design.rpt 27 | set DCRM_ANALYZE_DATAPATH_EXTRACTION_REPORT ${DESIGN_NAME}.analyze_datapath_extraction.rpt 28 | 29 | set DCRM_FINAL_QOR_REPORT ${DESIGN_NAME}.mapped.qor.rpt 30 | set DCRM_FINAL_TIMING_REPORT ${DESIGN_NAME}.mapped.timing.rpt 31 | set DCRM_FINAL_AREA_REPORT ${DESIGN_NAME}.mapped.area.rpt 32 | set DCRM_FINAL_POWER_REPORT ${DESIGN_NAME}.mapped.power.rpt 33 | set DCRM_FINAL_CLOCK_GATING_REPORT ${DESIGN_NAME}.mapped.clock_gating.rpt 34 | set DCRM_FINAL_SELF_GATING_REPORT ${DESIGN_NAME}.mapped.self_gating.rpt 35 | set DCRM_THRESHOLD_VOLTAGE_GROUP_REPORT ${DESIGN_NAME}.mapped.threshold.voltage.group.rpt 36 | set DCRM_INSTANTIATE_CLOCK_GATES_REPORT ${DESIGN_NAME}.instatiate_clock_gates.rpt 37 | set DCRM_FINAL_DESIGNWARE_AREA_REPORT ${DESIGN_NAME}.mapped.designware_area.rpt 38 | set DCRM_FINAL_RESOURCES_REPORT ${DESIGN_NAME}.mapped.final_resources.rpt 39 | 40 | set DCRM_MULTIBIT_CREATE_REGISTER_BANK_FILE ${DESIGN_NAME}.register_bank.rpt 41 | set DCRM_MULTIBIT_CREATE_REGISTER_BANK_REPORT ${DESIGN_NAME}.register_bank_report_file.rpt 42 | set DCRM_MULTIBIT_COMPONENTS_REPORT ${DESIGN_NAME}.multibit.components.rpt 43 | set DCRM_MULTIBIT_BANKING_REPORT ${DESIGN_NAME}.multibit.banking.rpt 44 | 45 | 46 | set DCRM_FINAL_INTERFACE_TIMING_REPORT ${DESIGN_NAME}.mapped.interface_timing.rpt 47 | 48 | ################ 49 | # Output Files # 50 | ################ 51 | 52 | set DCRM_AUTOREAD_RTL_SCRIPT ${DESIGN_NAME}.autoread_rtl.tcl 53 | set DCRM_ELABORATED_DESIGN_DDC_OUTPUT_FILE ${DESIGN_NAME}.elab.ddc 54 | set DCRM_COMPILE_ULTRA_DDC_OUTPUT_FILE ${DESIGN_NAME}.compile_ultra.ddc 55 | set DCRM_FINAL_DDC_OUTPUT_FILE ${DESIGN_NAME}.mapped.ddc 56 | set DCRM_FINAL_PG_VERILOG_OUTPUT_FILE ${DESIGN_NAME}.mapped.pg.v 57 | set DCRM_FINAL_VERILOG_OUTPUT_FILE ${DESIGN_NAME}.mapped.v 58 | set DCRM_FINAL_SDC_OUTPUT_FILE ${DESIGN_NAME}.mapped.sdc 59 | set DCRM_FINAL_DESIGN_ICC2 ICC2_files 60 | 61 | 62 | # The following procedures are used to control the naming of the updated blocks 63 | # after transparent interface optimization. 64 | # Modify this procedure if you want to use different names. 65 | 66 | proc dcrm_compile_ultra_tio_filename { design } { 67 | return $design.compile_ultra.tio.ddc 68 | } 69 | proc dcrm_mapped_tio_filename { design } { 70 | return $design.mapped.tio.ddc 71 | } 72 | 73 | ################################################################################# 74 | # DCE Flow Files 75 | ################################################################################# 76 | 77 | ############### 78 | # DCE Reports # 79 | ############### 80 | 81 | set DCRM_DCE_MISSING_CONSTRAINTS_REPORT ${DESIGN_NAME}.missing_constraints.rpt 82 | set DCRM_DCE_DESIGN_MISMATCH_REPORT ${DESIGN_NAME}.design_mismatch.rpt 83 | 84 | ################################################################################# 85 | # DCT Flow Files 86 | ################################################################################# 87 | 88 | ################### 89 | # DCT Input Files # 90 | ################### 91 | 92 | set DCRM_DCT_DEF_INPUT_FILE ${DESIGN_NAME}.def 93 | set DCRM_DCT_FLOORPLAN_INPUT_FILE ${DESIGN_NAME}.fp 94 | set DCRM_DCT_PHYSICAL_CONSTRAINTS_INPUT_FILE ${DESIGN_NAME}.physical_constraints.tcl 95 | 96 | 97 | ############### 98 | # DCT Reports # 99 | ############### 100 | 101 | set DCRM_DCT_PHYSICAL_CONSTRAINTS_REPORT ${DESIGN_NAME}.physical_constraints.rpt 102 | 103 | set DCRM_DCT_FINAL_CONGESTION_REPORT ${DESIGN_NAME}.mapped.congestion.rpt 104 | set DCRM_DCT_FINAL_CONGESTION_MAP_OUTPUT_FILE ${DESIGN_NAME}.mapped.congestion_map.png 105 | set DCRM_DCT_FINAL_CONGESTION_MAP_WINDOW_OUTPUT_FILE ${DESIGN_NAME}.mapped.congestion_map_window.png 106 | set DCRM_ANALYZE_RTL_CONGESTION_REPORT_FILE ${DESIGN_NAME}.analyze_rtl_congetion.rpt 107 | 108 | set DCRM_DCT_FINAL_QOR_SNAPSHOT_FOLDER ${DESIGN_NAME}.qor_snapshot 109 | set DCRM_DCT_FINAL_QOR_SNAPSHOT_REPORT ${DESIGN_NAME}.qor_snapshot.rpt 110 | 111 | #################### 112 | # DCT Output Files # 113 | #################### 114 | 115 | set DCRM_DCT_FLOORPLAN_OUTPUT_FILE ${DESIGN_NAME}.initial.fp 116 | 117 | set DCRM_DCT_FINAL_FLOORPLAN_OUTPUT_FILE ${DESIGN_NAME}.mapped.fp 118 | set DCRM_DCT_FINAL_SPEF_OUTPUT_FILE ${DESIGN_NAME}.mapped.spef 119 | set DCRM_DCT_FINAL_SDF_OUTPUT_FILE ${DESIGN_NAME}.mapped.sdf 120 | 121 | # Uncomment the DCRM_DCT_SPG_PLACEMENT_OUTPUT_FILE variable setting to save the 122 | # standard cell placement for physical guidance flow when ASCII hand-off to IC Compiler 123 | # is used. 124 | 125 | # set DCRM_DCT_SPG_PLACEMENT_OUTPUT_FILE ${DESIGN_NAME}.mapped.std_cell.def 126 | 127 | ################################################################################# 128 | # DFT Flow Files 129 | ################################################################################# 130 | 131 | ################### 132 | # DFT Input Files # 133 | ################### 134 | 135 | set DCRM_DFT_SIGNAL_SETUP_INPUT_FILE ${DESIGN_NAME}.dft_signal_defs.tcl 136 | set DCRM_DFT_AUTOFIX_CONFIG_INPUT_FILE ${DESIGN_NAME}.dft_autofix_config.tcl 137 | 138 | ############### 139 | # DFT Reports # 140 | ############### 141 | 142 | set DCRM_DFT_DRC_CONFIGURED_VERBOSE_REPORT ${DESIGN_NAME}.dft_drc_configured.rpt 143 | set DCRM_DFT_SCAN_CONFIGURATION_REPORT ${DESIGN_NAME}.scan_config.rpt 144 | set DCRM_DFT_COMPRESSION_CONFIGURATION_REPORT ${DESIGN_NAME}.compression_config.rpt 145 | set DCRM_DFT_PREVIEW_CONFIGURATION_REPORT ${DESIGN_NAME}.report_dft_insertion_config.preview_dft.rpt 146 | set DCRM_DFT_PREVIEW_DFT_SUMMARY_REPORT ${DESIGN_NAME}.preview_dft_summary.rpt 147 | set DCRM_DFT_PREVIEW_DFT_ALL_REPORT ${DESIGN_NAME}.preview_dft.rpt 148 | 149 | set DCRM_DFT_FINAL_SCAN_PATH_REPORT ${DESIGN_NAME}.mapped.scanpath.rpt 150 | set DCRM_DFT_DRC_FINAL_REPORT ${DESIGN_NAME}.mapped.dft_drc_inserted.rpt 151 | set DCRM_DFT_FINAL_SCAN_COMPR_SCAN_PATH_REPORT ${DESIGN_NAME}.mapped.scanpath.scan_compression.rpt 152 | set DCRM_DFT_DRC_FINAL_SCAN_COMPR_REPORT ${DESIGN_NAME}.mapped.dft_drc_inserted.scan_compression.rpt 153 | set DCRM_DFT_FINAL_CHECK_SCAN_DEF_REPORT ${DESIGN_NAME}.mapped.check_scan_def.rpt 154 | set DCRM_DFT_FINAL_DFT_SIGNALS_REPORT ${DESIGN_NAME}.mapped.dft_signals.rpt 155 | 156 | #################### 157 | # DFT Output Files # 158 | #################### 159 | 160 | set DCRM_DFT_FINAL_SCANDEF_OUTPUT_FILE ${DESIGN_NAME}.mapped.scandef 161 | set DCRM_DFT_FINAL_EXPANDED_SCANDEF_OUTPUT_FILE ${DESIGN_NAME}.mapped.expanded.scandef 162 | set DCRM_DFT_FINAL_CTL_OUTPUT_FILE ${DESIGN_NAME}.mapped.ctl 163 | set DCRM_DFT_FINAL_PROTOCOL_OUTPUT_FILE ${DESIGN_NAME}.mapped.scan.spf 164 | set DCRM_DFT_FINAL_SCAN_COMPR_PROTOCOL_OUTPUT_FILE ${DESIGN_NAME}.mapped.scancompress.spf 165 | 166 | 167 | ################################################################################# 168 | # MV Flow Files 169 | ################################################################################# 170 | 171 | ################### 172 | # MV Input Files # 173 | ################### 174 | 175 | set DCRM_MV_UPF_INPUT_FILE ${DESIGN_NAME}.upf 176 | set DCRM_MV_SET_VOLTAGE_INPUT_FILE ${DESIGN_NAME}.set_voltage.tcl 177 | set DCRM_MV_DCT_VOLTAGE_AREA_INPUT_FILE ${DESIGN_NAME}.create_voltage_area.tcl 178 | set MVRCRM_RTL_READ_SCRIPT ${DESIGN_NAME}.MVRC.read_design.tcl 179 | set VCLPRM_RTL_READ_SCRIPT ${DESIGN_NAME}.VCLP.read_design.tcl 180 | 181 | ############## 182 | # MV Reports # 183 | ############## 184 | 185 | set DCRM_MV_DRC_FINAL_SUMMARY_REPORT ${DESIGN_NAME}.mv_drc.final_summary.rpt 186 | set DCRM_MV_DRC_FINAL_VERBOSE_REPORT ${DESIGN_NAME}.mv_drc.final.rpt 187 | set DCRM_MV_FINAL_POWER_DOMAIN_REPORT ${DESIGN_NAME}.mapped.power_domain.rpt 188 | set DCRM_MV_FINAL_POWER_SWITCH_REPORT ${DESIGN_NAME}.mapped.power_switch.rpt 189 | set DCRM_MV_FINAL_SUPPLY_NET_REPORT ${DESIGN_NAME}.mapped.supply_net.rpt 190 | set DCRM_MV_FINAL_PST_REPORT ${DESIGN_NAME}.mapped.pst.rpt 191 | set DCRM_MV_FINAL_LEVEL_SHIFTER_REPORT ${DESIGN_NAME}.mapped.level_shifter.rpt 192 | set DCRM_MV_FINAL_ISOLATION_CELL_REPORT ${DESIGN_NAME}.mapped.isolation_cell.rpt 193 | set DCRM_MV_FINAL_RETENTION_CELL_REPORT ${DESIGN_NAME}.mapped.retention_cell.rpt 194 | 195 | #################### 196 | # MV Output Files # 197 | #################### 198 | 199 | set DCRM_MV_FINAL_UPF_OUTPUT_FILE ${DESIGN_NAME}.mapped.upf 200 | set DCRM_MV_FINAL_LINK_LIBRARY_OUTPUT_FILE ${DESIGN_NAME}.link_library.tcl 201 | 202 | ################################################################################# 203 | # Formality Flow Files 204 | ################################################################################# 205 | 206 | set DCRM_SVF_OUTPUT_FILE ${DESIGN_NAME}.mapped.svf 207 | 208 | set FMRM_UNMATCHED_POINTS_REPORT ${DESIGN_NAME}.fmv_unmatched_points.rpt 209 | 210 | set FMRM_FAILING_SESSION_NAME ${DESIGN_NAME} 211 | set FMRM_FAILING_POINTS_REPORT ${DESIGN_NAME}.fmv_failing_points.rpt 212 | set FMRM_ABORTED_POINTS_REPORT ${DESIGN_NAME}.fmv_aborted_points.rpt 213 | set FMRM_ANALYZE_POINTS_REPORT ${DESIGN_NAME}.fmv_analyze_points.rpt 214 | -------------------------------------------------------------------------------- /syn/scripts/dc/snpsll_hpdu_synth.tcl: -------------------------------------------------------------------------------- 1 | ################################################################################################################################################################ 2 | # Example Tcl file for dont_use list to be used with Synopsys DesignWare logic libraries on TSMC16FFC process. 3 | # Script: snpsll_hpdu_synth.tcl 4 | # Version: M-2016.12-SP2 (April 3, 2017) 5 | # Copyright (C) 2007-2017 Synopsys, Inc. All rights reserved. 6 | ################################################################################################################################################################### 7 | # The LIBRARY_DONT_USE_PRE_COMPILE_LIST variable automatically points to the snpsll_hpdu_synth.tcl file when the "Synopsys Logic Library" option is set to TRUE. 8 | # Open a SolvNet case for details about the snpsll_hpdu_synth.tcl file and to get additional dont_use lists for standard cell libraries. 9 | ################################################################################################################################################################### 10 | remove_attribute [get_lib_cells */*] dont_use 11 | 12 | set_dont_use [get_lib_cells */*CKGT*0P*] -power 13 | 14 | # Uncomment the below lines to achieve a higher frequency when using Synopsys DesignWare Logic Libraries 15 | #set_dont_use [get_lib_cells */*FSD*] 16 | #set_dont_use [get_lib_cells */*FD*] 17 | #remove_attribute [get_lib_cells */*FSD*QO*] dont_use 18 | 19 | set dont_use_list [list *_0P* *_16 *_20 *_24 *_32 *_DEL* *_TIE* *ECO* *MMCK* *_CK_* *LP* *_MM_* *_S_* ] 20 | foreach dont_use ${dont_use_list} { 21 | echo "[get_attribute [get_lib_cells */${dont_use}] full_name]" 22 | set_dont_use [get_lib_cells */${dont_use} ] 23 | } 24 | -------------------------------------------------------------------------------- /syn/sdc/SystolicArray.sdc: -------------------------------------------------------------------------------- 1 | set sdc_version 2.0 2 | 3 | # Create each clock in the design 4 | create_clock "clock" -name "clock" -period 1 5 | 6 | # Input delay 7 | set_input_delay 0.1 -clock "clock" [list a b c] 8 | 9 | # Output delay 10 | set_output_delay 0.1 -clock "clock" [list mac] 11 | 12 | # Max delay 13 | set_max_delay 10 -from reset 14 | --------------------------------------------------------------------------------