├── .gitignore ├── LICENSE ├── README.md ├── dm.pdf ├── drc ├── custom_device.lydrc ├── drc.lydrc └── netlist.lydrc ├── process.xs ├── samples ├── devices.gds ├── devices_with_tie.gds ├── devices_with_tie.lyp ├── drc_errors.gds ├── models.cir ├── ringo.cir ├── ringo.gds ├── ringo_simplified.cir ├── ringo_testbench.cir ├── ringo_with_hierarchical_nets.gds ├── ringo_with_hierarchical_nets.lyp ├── vdiv.cir ├── vdiv.gds ├── vdiv_simplified.cir └── xs.gds ├── tech.lyp └── xs.lyp /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | This is free and unencumbered software released into the public domain. 2 | 3 | Anyone is free to copy, modify, publish, use, compile, sell, or 4 | distribute this software, either in source code form or as a compiled 5 | binary, for any purpose, commercial or non-commercial, and by any 6 | means. 7 | 8 | In jurisdictions that recognize copyright laws, the author or authors 9 | of this software dedicate any and all copyright interest in the 10 | software to the public domain. We make this dedication for the benefit 11 | of the public at large and to the detriment of our heirs and 12 | successors. We intend this dedication to be an overt act of 13 | relinquishment in perpetuity of all present and future rights to this 14 | software under copyright law. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 19 | IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 | OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 | ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 | OTHER DEALINGS IN THE SOFTWARE. 23 | 24 | For more information, please refer to 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # si4all 2 | 3 | A fake "technology" to play with. 4 | 5 | This is in preparation of the talk at FSiC2019 (https://wiki.f-si.org/index.php/FSiC2019). 6 | 7 | DISLAIMER: The technology described in this project is 8 | entirely fake. All numbers given are just guesses. Any similarity 9 | to a real technology is just coincidence. 10 | 11 | Here is a rough table of contents: 12 | 13 | * "Design manual": ```dm.pdf``` 14 | * XSection file: ```process.xs``` and ```xs.lyp``` (for display) 15 | * Scripts: 16 | * DRC: ```drc/drc.lydrc``` 17 | * Netlisting script: ```drc/netlist.lydrc``` 18 | * Custom device (resistor) example: ```drc/custom_device.lydrc``` 19 | * Layout samples: 20 | * Device samples: ```devices.gds``` 21 | * DRC test layout: ```drc_errors.gds``` 22 | * Circuit sample: 23 | * ```ringo.gds``` (layout) 24 | * ```ringo.cir``` (netlist extracted with ```drc/netlist.lydrc``` 25 | * ```ringo_simplified.cir``` (simplified netlist) 26 | * ```ringo_testbench.cir``` (testbench for ringo circuit) 27 | * ```models.cir``` (fake models for testbench) 28 | * Small circuit sample (resistor devices) 29 | * ```vdiv.gds``` (layout) 30 | * ```vdiv.cir``` (netlist extracted with ```drc/custom_device.lydrc``` 31 | * ```vdiv_simplified.cir``` (simplified netlist) 32 | * Cross-section generation layout: ```xs.gds``` 33 | 34 | -------------------------------------------------------------------------------- /dm.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/dm.pdf -------------------------------------------------------------------------------- /drc/custom_device.lydrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | drc 6 | 7 | 8 | 9 | false 10 | false 11 | 12 | true 13 | drc_scripts 14 | tools_menu.drc.end 15 | dsl 16 | drc-dsl-xml 17 | 18 | # Silicon4All NCC-1701 Technology 19 | # Design Manual V1 20 | # 21 | # NOT CONFIDENTIAL 22 | # COPY AS YOU LIKE! 23 | 24 | # Intentionally flat at we don't have a way to flatten 25 | # the device cells currently! 26 | 27 | # Drawing layers 28 | 29 | nwell = input(1, 0) 30 | diff = input(2, 0) 31 | pplus = input(3, 0) 32 | nplus = input(4, 0) 33 | poly = input(5, 0) 34 | thickox = input(6, 0) 35 | polyres = input(7, 0) 36 | contact = input(8, 0) 37 | metal1 = input(9, 0) 38 | via = input(10, 0) 39 | metal2 = input(11, 0) 40 | 41 | # Special layer for bulk terminals 42 | 43 | bulk = make_layer 44 | 45 | # Computed layers 46 | 47 | poly_not_res = poly - polyres 48 | poly_in_res = poly & polyres 49 | 50 | diff_in_nwell = diff & nwell 51 | pdiff = diff_in_nwell - nplus 52 | ntie = diff_in_nwell & nplus 53 | pgate = pdiff & poly_not_res 54 | psd = pdiff - pgate 55 | hv_pgate = pgate & thickox 56 | lv_pgate = pgate - hv_pgate 57 | hv_psd = psd & thickox 58 | lv_psd = psd - thickox 59 | 60 | diff_outside_nwell = diff - nwell 61 | ndiff = diff_outside_nwell - pplus 62 | ptie = diff_outside_nwell & pplus 63 | ngate = ndiff & poly_not_res 64 | nsd = ndiff - ngate 65 | hv_ngate = ngate & thickox 66 | lv_ngate = ngate - hv_ngate 67 | hv_nsd = nsd & thickox 68 | lv_nsd = nsd - thickox 69 | 70 | # Resistor device extraction 71 | 72 | class CustomResistorExtraction < RBA::GenericDeviceExtractor 73 | 74 | def initialize(name, sheet_rho) 75 | self.name = name 76 | @sheet_rho = sheet_rho 77 | end 78 | 79 | def setup 80 | 81 | define_layer("C", "Conductor") 82 | define_layer("R", "Resistor") 83 | 84 | register_device_class(RBA::DeviceClassResistor::new) 85 | 86 | end 87 | 88 | def extract_devices(layer_geometry) 89 | 90 | # layer_geometry provides the input layers in the order they are 91 | # defined with "define_layer" 92 | # conductor is supposed to be "conductor outside marker" 93 | # resistor is supposed to be "conductor inside marker" 94 | conductor = layer_geometry[0] 95 | resistor = layer_geometry[1] 96 | 97 | # the index of the conductor layer (needed to make the terminals) 98 | conductor_geometry_index = 0 99 | 100 | resistor_merged = resistor.merged 101 | 102 | # this will be the edge where the resistor turns into conductor 103 | marker_edges = conductor.merged.edges & resistor_merged.edges 104 | 105 | resistor_merged.each do |r| 106 | 107 | # identify the edges where this resistor shape ends 108 | interface_edges = marker_edges.interacting(RBA::Region::new(r)) 109 | 110 | # form terminal shapes from these edges 111 | terminals = interface_edges.extended_out(1) 112 | 113 | if terminals.size != 2 114 | error("Resistor shape does not touch marker border in exactly two places", r) 115 | else 116 | 117 | # A = L*W 118 | # P = 2*(L+W) 119 | # -> L = p+sqrt(p*p-A) 120 | # -> W = p-sqrt(p*p-A) 121 | # (p=P/4) 122 | 123 | p = 0.25 * r.perimeter 124 | a = r.area 125 | 126 | d = Math.sqrt(p * p - a) 127 | l = p + d 128 | w = p - d 129 | 130 | if w > 1e-3 131 | 132 | device = create_device 133 | 134 | device.set_parameter(RBA::DeviceClassResistor::PARAM_R, @sheet_rho * l / w); 135 | 136 | define_terminal(device, RBA::DeviceClassResistor::TERMINAL_A, conductor_geometry_index, terminals[0]); 137 | define_terminal(device, RBA::DeviceClassResistor::TERMINAL_B, conductor_geometry_index, terminals[1]); 138 | 139 | end 140 | 141 | end 142 | 143 | end 144 | 145 | end 146 | 147 | def get_connectivity(layout, layers) 148 | 149 | # the layer definition is marker, conductor, resistor 150 | # * resistor is used for extraction 151 | # * conductor is used for producing the terminals 152 | 153 | conductor = layers[0] 154 | resistor = layers[1] 155 | 156 | conn = RBA::Connectivity::new 157 | 158 | conn.connect(resistor, resistor) 159 | conn.connect(conductor, resistor) 160 | 161 | return conn 162 | 163 | end 164 | 165 | end 166 | 167 | 168 | 169 | # Resistor 170 | 171 | # Assumes a sheet rho of 150 Ohm/Square 172 | res_ex = CustomResistorExtraction::new("RES", 150.0) 173 | extract_devices(res_ex, { "C" => poly_not_res, "R" => poly_in_res }) 174 | 175 | # PMOS transistor device extraction 176 | 177 | hvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVPMOS") 178 | extract_devices(hvpmos_ex, { "SD" => psd, "G" => hv_pgate, "P" => poly_not_res, "W" => nwell }) 179 | 180 | lvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVPMOS") 181 | extract_devices(lvpmos_ex, { "SD" => psd, "G" => lv_pgate, "P" => poly_not_res, "W" => nwell }) 182 | 183 | # NMOS transistor device extraction 184 | 185 | lvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVNMOS") 186 | extract_devices(lvnmos_ex, { "SD" => nsd, "G" => lv_ngate, "P" => poly_not_res, "W" => bulk }) 187 | 188 | hvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVNMOS") 189 | extract_devices(hvnmos_ex, { "SD" => nsd, "G" => hv_ngate, "P" => poly_not_res, "W" => bulk }) 190 | 191 | 192 | # Define connectivity for netlist extraction 193 | 194 | # Inter-layer 195 | connect(contact, ntie) 196 | connect(contact, ptie) 197 | connect(nwell, ntie) 198 | connect(psd, contact) 199 | connect(nsd, contact) 200 | connect(poly_not_res, contact) 201 | connect(contact, metal1) 202 | connect(metal1, via) 203 | connect(via, metal2) 204 | 205 | # Global connections 206 | connect_global(ptie, "BULK") 207 | connect_global(bulk, "BULK") 208 | 209 | # Actually performs the extraction 210 | 211 | netlist = l2n_data.netlist 212 | 213 | # Write the netlist 214 | 215 | writer = RBA::NetlistSpiceWriter::new 216 | 217 | path = RBA::CellView::active.filename.sub(/\.[^\.]*$/, ".cir") 218 | netlist.write(path, writer, "Netlist before simplification") 219 | puts "Netlist written to #{path}" 220 | 221 | # Netlist simplification 222 | 223 | # NOTE: use make_top_level_pins before combine_devices as the pin 224 | # stops the three resistors to be combined into one 225 | netlist.make_top_level_pins 226 | netlist.combine_devices 227 | netlist.purge 228 | netlist.purge_nets 229 | 230 | path = RBA::CellView::active.filename.sub(/\.[^\.]*$/, "_simplified.cir") 231 | netlist.write(path, writer, "Netlist after simplification") 232 | puts "Netlist written to #{path}" 233 | 234 | 235 | 236 | -------------------------------------------------------------------------------- /drc/drc.lydrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | NCC1701 4 | 5 | drc 6 | 7 | 8 | 9 | false 10 | false 11 | 12 | true 13 | drc_scripts 14 | tools_menu.drc.end 15 | dsl 16 | drc-dsl-xml 17 | 18 | # Silicon4All NCC-1701 Technology 19 | # Design Manual V1 20 | # 21 | # NOT CONFIDENTIAL 22 | # COPY AS YOU LIKE! 23 | 24 | report("DRC report") 25 | 26 | # Drawing layers 27 | 28 | nwell = input(1, 0) 29 | diff = input(2, 0) 30 | pplus = input(3, 0) 31 | nplus = input(4, 0) 32 | poly = input(5, 0) 33 | thickox = input(6, 0) 34 | polyres = input(7, 0) 35 | contact = input(8, 0) 36 | metal1 = input(9, 0) 37 | via = input(10, 0) 38 | metal2 = input(11, 0) 39 | pad = input(12, 0) 40 | border = input(13, 0) 41 | 42 | all_drawing = [ 43 | :nwell, :diff, :pplus, :nplus, :poly, 44 | :thickox, :polyres, 45 | :contact, :metal1, :via, :metal2, :pad 46 | ] 47 | 48 | 49 | # Compute some layers required layer (saves duplicate computation) 50 | 51 | gate = poly & diff 52 | poly_edges = poly.edges 53 | poly_gate_edges = poly_edges.interacting(diff) 54 | other_poly_edges = poly_edges.not_interacting(diff) 55 | 56 | 57 | # Rules 58 | 59 | # --------------------------------- 60 | # CONT_S 61 | 62 | min_cont_s = 360.nm 63 | 64 | r_cont_s = contact.space(square, min_cont_s) 65 | r_cont_s.output("CONT_S: contact space < #{'%.12g' % min_cont_s} µm") 66 | 67 | # --------------------------------- 68 | # CONT_W 69 | 70 | exact_cont_w = 180.nm 71 | 72 | r_cont_wa = contact.width(square, exact_cont_w) 73 | r_cont_wa.output("CONT_Wa: contact width < #{'%.12g' % exact_cont_w} µm") 74 | 75 | exact_cont_a = exact_cont_w * exact_cont_w 76 | r_cont_wb = contact.without_area(exact_cont_a) 77 | r_cont_wb.output("CONT_Wb: contact area != #{'%.12g' % exact_cont_a} µm²") 78 | 79 | # --------------------------------- 80 | # CONT_X 81 | 82 | r_cont_x = contact - (contact.inside(diff) + contact.inside(poly)) 83 | r_cont_x.output("CONT_X: contact not entirely inside diff or poly") 84 | 85 | # --------------------------------- 86 | # DIFF_A 87 | 88 | min_diff_a = 0.5.um2 89 | 90 | r_diff_a = diff.with_area(0, min_diff_a) 91 | r_diff_a.output("DIFF_A: diff area < #{'%.12g' % min_diff_a} µm²") 92 | 93 | # --------------------------------- 94 | # DIFF_CONT_O 95 | 96 | min_diff_cont_o = 110.nm 97 | 98 | r_diff_cont_o = diff.enclosing(contact, min_diff_cont_o) 99 | r_diff_cont_o.output("DIFF_CONT_O: diff overlap over contact < #{'%.12g' % min_diff_cont_o} µm") 100 | 101 | # --------------------------------- 102 | # DIFF_GATE_O 103 | 104 | min_diff_gate_o = 420.nm 105 | 106 | r_diff_gate_o = diff.enclosing(poly, min_diff_gate_o) 107 | r_diff_gate_o.output("DIFF_GATE_O: diff overlap over poly < #{'%.12g' % min_diff_gate_o} µm") 108 | 109 | # --------------------------------- 110 | # DIFF_NPLUS_X 111 | 112 | r_diff_nplus_x = diff.overlapping(nplus) - nplus 113 | r_diff_nplus_x.output("DIFF_NPLUS_X: diff must be either inside or outside nplus") 114 | 115 | # --------------------------------- 116 | # DIFF_NWELL_S 117 | 118 | min_diff_nwell_s = 300.nm 119 | 120 | r_diff_nwell_s = diff.separation(nwell, min_diff_nwell_s) 121 | r_diff_nwell_s.output("DIFF_NWELL_S: diff to nwell distance < #{'%.12g' % min_diff_nwell_s} µm") 122 | 123 | # --------------------------------- 124 | # DIFF_NWELL_X 125 | 126 | r_diff_nwell_x = diff.overlapping(nwell) - nwell 127 | r_diff_nwell_x.output("DIFF_NWELL_X: diff must be either inside or outside nwell") 128 | 129 | # --------------------------------- 130 | # DIFF_POLY_S 131 | 132 | min_diff_poly_s = 100.nm 133 | 134 | r_diff_poly_s = diff.separation(poly, min_diff_poly_s) 135 | r_diff_poly_s.output("DIFF_POLY_S: diff to poly distance < #{'%.12g' % min_diff_poly_s} µm") 136 | 137 | # --------------------------------- 138 | # DIFF_PPLUS_X 139 | 140 | r_diff_pplus_x = diff.overlapping(pplus) - pplus 141 | r_diff_pplus_x.output("DIFF_PPLUS_X: diff must be either inside or outside pplus") 142 | 143 | # --------------------------------- 144 | # DIFF_S 145 | 146 | min_diff_s = 600.nm 147 | 148 | r_diff_s = diff.space(min_diff_s) 149 | r_diff_s.output("DIFF_S: diff space < #{'%.12g' % min_diff_s} µm") 150 | 151 | # --------------------------------- 152 | # DIFF_W 153 | 154 | min_diff_w = 500.nm 155 | 156 | r_diff_w = diff.width(min_diff_w) 157 | r_diff_w.output("DIFF_W: diff width < #{'%.12g' % min_diff_w} µm") 158 | 159 | # --------------------------------- 160 | # METAL1_CONT_O 161 | 162 | min_metal1_cont_o = 60.nm 163 | 164 | r_metal1_cont_o = metal1.enclosing(contact, min_metal1_cont_o) 165 | r_metal1_cont_o.output("METAL1_CONT_O: metal1 overlap over contact < #{'%.12g' % min_metal1_cont_o} µm") 166 | 167 | # --------------------------------- 168 | # METAL1_CONT_X 169 | 170 | r_metal1_cont_x = contact - metal1 171 | r_metal1_cont_x.output("METAL1_CONT_X: no contact without metal1") 172 | 173 | # --------------------------------- 174 | # METAL1_S 175 | 176 | min_metal1_s = 300.nm 177 | 178 | r_metal1_s = metal1.space(min_metal1_s) 179 | r_metal1_s.output("METAL1_S: metal1 space < #{'%.12g' % min_metal1_s} µm") 180 | 181 | # --------------------------------- 182 | # METAL1_VIA_O 183 | 184 | min_metal1_via_o = 50.nm 185 | 186 | r_metal1_via_o = metal1.enclosing(via, min_metal1_via_o) 187 | r_metal1_via_o.output("METAL1_VIA_O: metal1 overlap over via < #{'%.12g' % min_metal1_via_o} µm") 188 | 189 | # --------------------------------- 190 | # METAL1_VIA_X 191 | 192 | r_metal1_via_x = via - metal1 193 | r_metal1_via_x.output("METAL1_VIA_X: no via without metal1") 194 | 195 | # --------------------------------- 196 | # METAL1_W 197 | 198 | min_metal1_w = 300.nm 199 | 200 | r_metal1_w = metal1.width(min_metal1_w) 201 | r_metal1_w.output("METAL1_W: metal1 width < #{'%.12g' % min_metal1_w} µm") 202 | 203 | # --------------------------------- 204 | # METAL1_x 205 | 206 | min_metal1_dens = 0.2 207 | max_metal1_dens = 0.8 208 | 209 | metal1_area = metal1.area 210 | border_area = border.area 211 | if border_area >= 1.dbu * 1.dbu 212 | 213 | r_min_dens = polygon_layer 214 | r_max_dens = polygon_layer 215 | 216 | dens = metal1_area / border_area 217 | 218 | if dens < min_metal1_dens 219 | # copy border as min density marker 220 | r_min_dens = border 221 | end 222 | 223 | if dens > max_metal1_dens 224 | # copy border as max density marker 225 | r_max_dens = border 226 | end 227 | 228 | r_min_dens.output("METAL1_Xa: metal1 density (#{'%.2f' % (dens * 100)}%) below threshold of #{'%.12g' % (min_metal1_dens * 100)}%") 229 | r_max_dens.output("METAL1_Xb: metal1 density (#{'%.2f' % (dens * 100)}%) above threshold of #{'%.12g' % (max_metal1_dens * 100)}%") 230 | 231 | end 232 | 233 | # --------------------------------- 234 | # METAL2_PAD_O 235 | 236 | min_metal2_pad_o = 2.um 237 | 238 | r_metal2_pad_o = metal2.enclosing(pad, min_metal2_pad_o) 239 | r_metal2_pad_o.output("METAL2_PAD_O: metal2 overlap over pad < #{'%.12g' % min_metal2_pad_o} µm") 240 | 241 | # --------------------------------- 242 | # METAL2_PAD_X 243 | 244 | r_metal2_pad_x = pad - metal2 245 | r_metal2_pad_x.output("METAL2_PAD_X: no pad without metal2") 246 | 247 | # --------------------------------- 248 | # METAL2_S 249 | 250 | min_metal2_s = 500.nm 251 | 252 | r_metal2_s = metal2.space(min_metal2_s) 253 | r_metal2_s.output("METAL2_S: metal2 space < #{'%.12g' % min_metal2_s} µm") 254 | 255 | # --------------------------------- 256 | # METAL2_SW 257 | 258 | min_metal2_s = 700.nm 259 | min_metal2_wide_w = 3.um 260 | 261 | wide_metal2 = metal2 - metal2.width(min_metal2_wide_w, projection).polygons 262 | wide_metal2_edges = wide_metal2.edges 263 | narrow_metal2_edges = metal2.edges - wide_metal2_edges 264 | r_metal2_sw = wide_metal2_edges.separation(narrow_metal2_edges, min_metal2_s) 265 | r_metal2_sw.output("METAL2_SW: metal2 space < #{'%.12g' % min_metal2_s} for wide metal1 (>= #{'%.12g' % min_metal2_wide_w}) to narrow/wide") 266 | 267 | # --------------------------------- 268 | # METAL2_VIA_O 269 | 270 | min_metal2_via_o = 100.nm 271 | 272 | r_metal2_via_o = metal2.enclosing(via, min_metal2_via_o) 273 | r_metal2_via_o.output("METAL2_VIA_O: metal2 overlap over via < #{'%.12g' % min_metal2_via_o} µm") 274 | 275 | # --------------------------------- 276 | # METAL2_VIA_X 277 | 278 | r_metal2_via_x = via - metal2 279 | r_metal2_via_x.output("METAL2_VIA_X: no via without metal2") 280 | 281 | # --------------------------------- 282 | # METAL2_W 283 | 284 | min_metal2_w = 400.nm 285 | 286 | r_metal2_w = metal2.width(min_metal2_w) 287 | r_metal2_w.output("METAL2_W: metal2 width < #{'%.12g' % min_metal2_w} µm") 288 | 289 | # --------------------------------- 290 | # NWELL_A 291 | 292 | min_nwell_a = 2.um2 293 | 294 | r_nwell_a = nwell.with_area(0, min_nwell_a) 295 | r_nwell_a.output("NWELL_A: nwell area < #{'%.12g' % min_nwell_a} µm²") 296 | 297 | # --------------------------------- 298 | # NWELL_DIFF_O 299 | 300 | min_nwell_diff_o = 400.nm 301 | 302 | r_nwell_diff_o = nwell.enclosing(diff, min_nwell_diff_o) 303 | r_nwell_diff_o.output("NWELL_DIFF_O: nwell overlap over diff < #{'%.12g' % min_nwell_diff_o} µm") 304 | 305 | # --------------------------------- 306 | # NWELL_S 307 | 308 | min_nwell_s = 1.um 309 | 310 | r_nwell_s = nwell.space(min_nwell_s, projection) 311 | r_nwell_s.output("NWELL_S: nwell space < #{'%.12g' % min_nwell_s} µm") 312 | 313 | # --------------------------------- 314 | # NWELL_W 315 | 316 | min_nwell_w = 1.2.um 317 | 318 | r_nwell_w = nwell.width(min_nwell_w) 319 | r_nwell_w.output("NWELL_W: nwell width < #{'%.12g' % min_nwell_w} µm") 320 | 321 | # --------------------------------- 322 | # PAD_S 323 | 324 | min_pad_s = 10.um 325 | 326 | r_pad_s = pad.space(min_pad_s) 327 | r_pad_s.output("PAD_S: pad space < #{'%.12g' % min_pad_s} µm") 328 | 329 | # --------------------------------- 330 | # PAD_W 331 | 332 | min_pad_w = 10.um 333 | 334 | r_pad_w = pad.width(min_pad_w) 335 | r_pad_w.output("PAD_W: pad width < #{'%.12g' % min_pad_w} µm") 336 | 337 | # --------------------------------- 338 | # POLY_CONT_O 339 | 340 | min_poly_cont_o = 60.nm 341 | 342 | r_poly_cont_o = poly.enclosing(contact, min_poly_cont_o) 343 | r_poly_cont_o.output("POLY_CONT_O: poly overlap over contact < #{'%.12g' % min_poly_cont_o} µm") 344 | 345 | # --------------------------------- 346 | # POLY_CONT_S 347 | 348 | min_poly_cont_s = 130.nm 349 | 350 | r_poly_cont_s = poly.separation(contact, min_poly_cont_s) 351 | r_poly_cont_s.output("POLY_CONT_S: poly to contact space < #{'%.12g' % min_poly_cont_s} µm") 352 | 353 | # --------------------------------- 354 | # POLY_S 355 | 356 | min_poly_s = 300.nm 357 | 358 | r_poly_s = poly.space(min_poly_s) 359 | r_poly_s.output("POLY_S: poly space < #{'%.12g' % min_poly_s} µm") 360 | 361 | # --------------------------------- 362 | # POLY_W 363 | 364 | min_poly_w = 250.nm 365 | 366 | r_poly_w = poly.width(min_poly_w) 367 | r_poly_w.output("POLY_W: pad width < #{'%.12g' % min_poly_w} µm") 368 | 369 | # --------------------------------- 370 | # POLY_X1 371 | 372 | min_poly_edge_length = 70.nm 373 | 374 | r_poly_x1 = poly.edges.with_length(0, min_poly_edge_length) 375 | r_poly_x1.output("POLY_X1: edge length < #{'%.12g' % min_poly_edge_length} µm") 376 | 377 | # --------------------------------- 378 | # POLY_X2 379 | 380 | min_poly_ext_over_diff = 250.nm 381 | 382 | other_poly_edges_close_to_diff = other_poly_edges.separation(diff.edges, min_poly_ext_over_diff, projection).first_edges 383 | 384 | r_poly_x2 = other_poly_edges_close_to_diff.interacting(poly_gate_edges) 385 | r_poly_x2.output("POLY_X2: poly extension over gate < #{'%.12g' % min_poly_ext_over_diff} µm") 386 | 387 | # --------------------------------- 388 | # POLYRES_POLY_O 389 | 390 | min_polyres_poly_o = 300.nm 391 | 392 | r_polyres_poly_o = polyres.enclosing(poly, min_polyres_poly_o) 393 | r_polyres_poly_o.output("POLYRES_POLY_O: polyres overlap poly contact < #{'%.12g' % min_polyres_poly_o} µm") 394 | 395 | # --------------------------------- 396 | # POLYRES_X 397 | 398 | r_polyres_x = diff & polyres 399 | r_polyres_x.output("POLYRES_X: diff not allowed under polyres") 400 | 401 | # --------------------------------- 402 | # VIA_S 403 | 404 | min_via_s = 250.nm 405 | 406 | r_via_s = via.space(min_via_s) 407 | r_via_s.output("VIA_S: via space < #{'%.12g' % min_via_s} µm") 408 | 409 | # --------------------------------- 410 | # VIA_W 411 | 412 | exact_via_w = 200.nm 413 | 414 | r_via_wa = via.width(square, exact_via_w) 415 | r_via_wa.output("VIA_Wa: via width < #{'%.12g' % exact_via_w} µm") 416 | 417 | exact_via_a = exact_via_w * exact_via_w 418 | r_via_wb = via.without_area(exact_via_a) 419 | r_via_wb.output("VIA_Wb: via area != #{'%.12g' % exact_via_a} µm²") 420 | 421 | 422 | # --------------------------------- 423 | # MANHATTAN 424 | 425 | all_drawing.each do |dwg| 426 | 427 | # a Ruby idiom to get the value of a variable whose name is in "dwg" (as symbol) 428 | layer = binding.local_variable_get(dwg) 429 | 430 | # reduce the input to the part we really need to consider (-> performance) 431 | non_recilinear = layer.non_rectilinear 432 | non_recilinear_polygon_all_edges = non_recilinear.edges 433 | 434 | # isolate the edges which don't have 0 or 90 degree 435 | horizontal = non_recilinear_polygon_all_edges.with_angle(0) 436 | vertical = non_recilinear_polygon_all_edges.with_angle(90) 437 | r_nonmanhattan = non_recilinear_polygon_all_edges - horizontal - vertical 438 | 439 | r_nonmanhattan.output("MANHATTAN: edges are neigther vertical nor horizontal") 440 | 441 | end 442 | 443 | # --------------------------------- 444 | # ONGRID 445 | 446 | grid = 5.nm 447 | 448 | all_drawing.each do |dwg| 449 | 450 | # a Ruby idiom to get the value of a variable whose name is in "dwg" (as symbol) 451 | layer = binding.local_variable_get(dwg) 452 | 453 | r_grid = layer.ongrid(grid).polygons(10.nm) 454 | r_grid.output("GRID: vertexes on layer #{dwg} not on grid of #{'%.12g' % grid}") 455 | 456 | end 457 | 458 | # --------------------------------- 459 | # GATE_WELLFORMED 460 | 461 | # A wellformed gate simply means not polygon corners appear inside the 462 | # diff area. We also check whether the gate regions are rectangles 463 | 464 | # size the output shapes a little to improve visibility 465 | r_gate_malformed_a = (poly.corners & diff).sized(10.nm) 466 | r_gate_malformed_a.output("GATE_WELLFORMED: poly corners appear inside diff") 467 | 468 | r_gate_malformed_b = gate.non_rectangles 469 | r_gate_malformed_b.output("GATE_WELLFORMED: gate shapes not rectangular") 470 | 471 | # --------------------------------- 472 | # INSIDE_BORDER 473 | 474 | r_inside_border = extent - border 475 | r_inside_border.output("INSIDE_BORDER: there is drawing outside border") 476 | 477 | 478 | 479 | -------------------------------------------------------------------------------- /drc/netlist.lydrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | drc 6 | 7 | 8 | 9 | false 10 | false 11 | 12 | true 13 | drc_scripts 14 | tools_menu.drc.end 15 | dsl 16 | drc-dsl-xml 17 | 18 | # Silicon4All NCC-1701 Technology 19 | # Design Manual V1 20 | # 21 | # NOT CONFIDENTIAL 22 | # COPY AS YOU LIKE! 23 | 24 | # Hierarchical extraction 25 | 26 | deep 27 | 28 | # Drawing layers 29 | 30 | nwell = input(1, 0) 31 | diff = input(2, 0) 32 | pplus = input(3, 0) 33 | nplus = input(4, 0) 34 | poly = input(5, 0) 35 | thickox = input(6, 0) 36 | polyres = input(7, 0) 37 | contact = input(8, 0) 38 | metal1 = input(9, 0) 39 | via = input(10, 0) 40 | metal2 = input(11, 0) 41 | 42 | # Special layer for bulk terminals 43 | 44 | bulk = make_layer 45 | 46 | # Computed layers 47 | 48 | diff_in_nwell = diff & nwell 49 | pdiff = diff_in_nwell - nplus 50 | ntie = diff_in_nwell & nplus 51 | pgate = pdiff & poly 52 | psd = pdiff - pgate 53 | hv_pgate = pgate & thickox 54 | lv_pgate = pgate - hv_pgate 55 | hv_psd = psd & thickox 56 | lv_psd = psd - thickox 57 | 58 | diff_outside_nwell = diff - nwell 59 | ndiff = diff_outside_nwell - pplus 60 | ptie = diff_outside_nwell & pplus 61 | ngate = ndiff & poly 62 | nsd = ndiff - ngate 63 | hv_ngate = ngate & thickox 64 | lv_ngate = ngate - hv_ngate 65 | hv_nsd = nsd & thickox 66 | lv_nsd = nsd - thickox 67 | 68 | # PMOS transistor device extraction 69 | 70 | hvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVPMOS") 71 | extract_devices(hvpmos_ex, { "SD" => psd, "G" => hv_pgate, "P" => poly, "W" => nwell }) 72 | 73 | lvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVPMOS") 74 | extract_devices(lvpmos_ex, { "SD" => psd, "G" => lv_pgate, "P" => poly, "W" => nwell }) 75 | 76 | # NMOS transistor device extraction 77 | 78 | lvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVNMOS") 79 | extract_devices(lvnmos_ex, { "SD" => nsd, "G" => lv_ngate, "P" => poly, "W" => bulk }) 80 | 81 | hvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVNMOS") 82 | extract_devices(hvnmos_ex, { "SD" => nsd, "G" => hv_ngate, "P" => poly, "W" => bulk }) 83 | 84 | 85 | # Define connectivity for netlist extraction 86 | 87 | # Inter-layer 88 | connect(contact, ntie) 89 | connect(contact, ptie) 90 | connect(nwell, ntie) 91 | connect(psd, contact) 92 | connect(nsd, contact) 93 | connect(poly, contact) 94 | connect(contact, metal1) 95 | connect(metal1, via) 96 | connect(via, metal2) 97 | 98 | # Global connections 99 | connect_global(ptie, "BULK") 100 | connect_global(bulk, "BULK") 101 | 102 | # Actually performs the extraction 103 | 104 | netlist = l2n_data.netlist 105 | 106 | # Write the netlist 107 | 108 | writer = RBA::NetlistSpiceWriter::new 109 | 110 | path = RBA::CellView::active.filename.sub(/\.[^\.]*$/, ".cir") 111 | netlist.write(path, writer, "Netlist before simplification") 112 | puts "Netlist written to #{path}" 113 | 114 | 115 | # Further processing examples 116 | 117 | # 1.) Produce all nets as cells with subcells 118 | 119 | if true # set to true to enable 120 | 121 | cellmap = l2n_data.cell_mapping_into(source.layout, source.cell_obj) 122 | 123 | # build a map of layer indexes (in target layout) to layer objects 124 | to_layout = source.layout 125 | lmap = {} 126 | { 2000 => ntie, 2001 => ptie, 2002 => nwell, 2003 => nsd, 2004 => psd, 127 | 2005 => contact, 2006 => poly, 2007 => metal1, 2008 => via, 2009 => metal2 }.each do |n,l| 128 | lmap[to_layout.layer(n, 0)] = l.data 129 | end 130 | 131 | l2n_data.build_all_nets(cellmap, to_layout, lmap, "NET_", "CIRCUIT_") 132 | 133 | end 134 | 135 | # 2.) Probe the net at a specific location 136 | 137 | if false # set to true to enable 138 | 139 | probe_point = RBA::DPoint::new(10.0.um, 7.0.um) 140 | net = l2n_data.probe_net(metal1.data, probe_point) 141 | net && puts("Net at #{probe_point}: #{net.name}") 142 | 143 | end 144 | 145 | # 3.) Produce the shapes of a specific net (here: VDD) 146 | 147 | if false # set to true to enable 148 | 149 | # Gets the Circuit object for the top level cell 150 | top_circuit = l2n_data.netlist.circuit_by_name(source.layout.top_cell.name) 151 | 152 | # Finds the Net object for the "VDD" net 153 | net = top_circuit.net_by_name("VDD") 154 | 155 | # outputs the shapes for this net to layers 1000 (ntie), 1001 (ptie), 1002 (nwell) 156 | # etc ... 157 | { 2000 => ntie, 2001 => ptie, 2002 => nwell, 2003 => nsd, 2004 => psd, 158 | 2005 => contact, 2006 => poly, 2007 => metal1, 2008 => via, 2009 => metal2 }.each do |n,l| 159 | DRC::DRCLayer::new(self, l2n_data.shapes_of_net(net, l.data, true)).output(n, 0) 160 | end 161 | 162 | end 163 | 164 | # Netlist simplification 165 | 166 | netlist.combine_devices 167 | netlist.make_top_level_pins 168 | netlist.purge 169 | netlist.purge_nets 170 | 171 | path = RBA::CellView::active.filename.sub(/\.[^\.]*$/, "_simplified.cir") 172 | netlist.write(path, writer, "Netlist after simplification") 173 | puts "Netlist written to #{path}" 174 | 175 | 176 | 177 | -------------------------------------------------------------------------------- /process.xs: -------------------------------------------------------------------------------- 1 | 2 | # Input layers 3 | 4 | height(4.0) 5 | depth(2.0) 6 | 7 | nwell = layer("1/0") 8 | diff = layer("2/0") 9 | pplus = layer("3/0") 10 | nplus = layer("4/0") 11 | poly = layer("5/0") 12 | thickox = layer("6/0") 13 | polyres = layer("7/0") 14 | contact = layer("8/0") 15 | metal1 = layer("9/0") 16 | via = layer("10/0") 17 | metal2 = layer("11/0") 18 | pad = layer("12/0") 19 | 20 | pbulk = bulk 21 | 22 | nw = mask(nwell).grow(0.8, 0.2, :mode => :round, :into => pbulk) 23 | 24 | pp = mask(pplus.not(poly).sized(-0.02)).grow(0.1, 0.03, :mode => :round, :into => [ nw, pbulk ]) 25 | np = mask(nplus.not(poly).sized(-0.02)).grow(0.1, 0.03, :mode => :round, :into => [ nw, pbulk ]) 26 | 27 | mask(diff.inverted.sized(0.05)).etch(0.3, 0.05, :mode => :round, :into => [ nw, pbulk, pp, np ]) 28 | 29 | fieldox = grow(0.3) 30 | planarize(:downto => pp, :into => fieldox) 31 | 32 | gateox = grow(0.01) 33 | 34 | po = mask(poly).grow(0.2, :taper => 3.0) 35 | 36 | etch(0.01, :into => gateox) 37 | 38 | ox1 = grow(0.4) 39 | planarize(:to => 0.4, :into => ox1) 40 | mask(contact).etch(0.4, :taper => 3.0, :into => ox1) 41 | ct = grow(0.4) 42 | planarize(:downto => ox1, :into => ct) 43 | 44 | ox2 = grow(0.25) 45 | planarize(:to => 0.65, :into => ox2) 46 | mask(metal1).etch(0.25, :taper => 3.0, :into => ox2) 47 | m1 = grow(0.25) 48 | planarize(:downto => ox2, :into => m1) 49 | 50 | ox3 = grow(0.3) 51 | planarize(:to => 0.95, :into => ox3) 52 | mask(via).etch(0.3, :taper => 3.0, :into => ox3) 53 | v1 = grow(0.3) 54 | planarize(:downto => ox3, :into => v1) 55 | 56 | ox4 = grow(0.4) 57 | planarize(:to => 1.35, :into => ox4) 58 | mask(metal2).etch(0.4, :taper => 3.0, :into => ox4) 59 | m2 = grow(0.4) 60 | planarize(:downto => ox4, :into => m2) 61 | 62 | imid = mask(pad.inverted).grow(1.5, -0.3, :mode => :round) 63 | 64 | output("1/0", pbulk) 65 | output("2/0", nw) 66 | output("3/0", pp) 67 | output("4/0", np) 68 | output("5/0", po) 69 | output("6/0", ct) 70 | output("7/0", m1) 71 | output("8/0", v1) 72 | output("9/0", m2) 73 | output("10/0", MaterialData::new(gateox.data + fieldox.data, true)) 74 | output("11/0", MaterialData::new(ox1.data + ox2.data + ox3.data + ox4.data, true)) 75 | output("12/0", imid) 76 | 77 | 78 | -------------------------------------------------------------------------------- /samples/devices.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/devices.gds -------------------------------------------------------------------------------- /samples/devices_with_tie.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/devices_with_tie.gds -------------------------------------------------------------------------------- /samples/devices_with_tie.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #c0c0c0 5 | #c0c0c0 6 | 0 7 | 0 8 | C2 9 | I2 10 | true 11 | true 12 | false 13 | 2 14 | false 15 | false 16 | 0 17 | 1 - NWELL 18 | 1/0@1 19 | 20 | 21 | #ff8000 22 | #ff8000 23 | 0 24 | 0 25 | C0 26 | I4 27 | true 28 | true 29 | false 30 | 1 31 | false 32 | false 33 | 0 34 | 3 - PPLUS 35 | 3/0@1 36 | 37 | 38 | #008000 39 | #008000 40 | 16 41 | 16 42 | C1 43 | I4 44 | true 45 | true 46 | false 47 | 1 48 | false 49 | false 50 | 0 51 | 4 - NPLUS 52 | 4/0@1 53 | 54 | 55 | #ff0000 56 | #ff9d9d 57 | -64 58 | -64 59 | I3 60 | I2 61 | true 62 | true 63 | false 64 | 2 65 | false 66 | false 67 | 0 68 | 2 - DIFF 69 | 2/0@1 70 | 71 | 72 | #91ff00 73 | #91ff00 74 | -48 75 | -48 76 | I8 77 | 78 | true 79 | true 80 | false 81 | 2 82 | false 83 | false 84 | 0 85 | 5 - POLY 86 | 5/0@1 87 | 88 | 89 | #000000 90 | #000000 91 | 0 92 | 0 93 | I3 94 | I2 95 | true 96 | true 97 | false 98 | 3 99 | false 100 | false 101 | 0 102 | 6 - THICKOX 103 | THICKOX 6/0@1 104 | 105 | 106 | #805000 107 | #805000 108 | 0 109 | 0 110 | I3 111 | I4 112 | true 113 | true 114 | false 115 | 1 116 | false 117 | false 118 | 0 119 | 7 - POLYRES 120 | '7 - SALBL' 7/0@1 121 | 122 | 123 | #ff00ff 124 | #ffffff 125 | 0 126 | 0 127 | I0 128 | 129 | true 130 | true 131 | false 132 | 2 133 | false 134 | true 135 | 0 136 | 8 - CONTACT 137 | 8/0@1 138 | 139 | 140 | #8000ff 141 | #9580ff 142 | 0 143 | 0 144 | I4 145 | 146 | true 147 | true 148 | false 149 | 2 150 | false 151 | false 152 | 0 153 | 9 - METAL1 154 | 9/0@1 155 | 156 | 157 | #e872ff 158 | #e872ff 159 | -48 160 | -48 161 | I1 162 | 163 | true 164 | true 165 | false 166 | 2 167 | false 168 | true 169 | 0 170 | 10 - VIA 171 | 10/0@1 172 | 173 | 174 | #0000ff 175 | #8086ff 176 | 0 177 | 0 178 | I8 179 | 180 | true 181 | true 182 | false 183 | 2 184 | false 185 | false 186 | 0 187 | 11 - METAL2 188 | 11/0@1 189 | 190 | 191 | #808080 192 | #c0c0c0 193 | 0 194 | 128 195 | I43 196 | 197 | true 198 | true 199 | true 200 | 1 201 | false 202 | false 203 | 0 204 | 12 - PAD 205 | 12/0@1 206 | 207 | 208 | #c0c0c0 209 | #c0c0c0 210 | 0 211 | 0 212 | I1 213 | I4 214 | true 215 | true 216 | false 217 | 1 218 | false 219 | false 220 | 0 221 | 13 - BORDER 222 | 13/0@1 223 | 224 | 225 | #606060 226 | #606060 227 | 0 228 | 0 229 | I1 230 | I2 231 | true 232 | true 233 | false 234 | 1 235 | false 236 | true 237 | 0 238 | 1000 - MARKING 1 239 | 1000/0@1 240 | 241 | 242 | #000000 243 | #000000 244 | 0 245 | 0 246 | I1 247 | I2 248 | true 249 | true 250 | false 251 | 1 252 | false 253 | false 254 | 0 255 | 1001 - MARKING 2 256 | 1001/0@1 257 | 258 | 259 | 260 | 261 | ........................ 262 | ........................ 263 | ............******...... 264 | ............*******..... 265 | ............**...***.... 266 | ............**....**.... 267 | ............**....**.... 268 | ............**...***.... 269 | ............*******..... 270 | ............******...... 271 | ............**.......... 272 | ............**.......... 273 | ........................ 274 | ........................ 275 | ******.................. 276 | *******................. 277 | **...***................ 278 | **....**................ 279 | **....**................ 280 | **...***................ 281 | *******................. 282 | ******.................. 283 | **...................... 284 | **...................... 285 | 286 | 1 287 | custom plus 288 | 289 | 290 | 291 | ........................ 292 | ........................ 293 | ............**....**.... 294 | ............**....**.... 295 | ............***...**.... 296 | ............****..**.... 297 | ............*****.**.... 298 | ............**.*****.... 299 | ............**..****.... 300 | ............**...***.... 301 | ............**....**.... 302 | ............**....**.... 303 | ........................ 304 | ........................ 305 | **....**................ 306 | **....**................ 307 | ***...**................ 308 | ****..**................ 309 | *****.**................ 310 | **.*****................ 311 | **..****................ 312 | **...***................ 313 | **....**................ 314 | **....**................ 315 | 316 | 2 317 | custom minus 318 | 319 | 320 | 321 | ........................ 322 | ........................ 323 | ........................ 324 | ........................ 325 | ..............*.***..... 326 | ..............**...*.... 327 | ..............*....*.... 328 | ..............*....*.... 329 | ..............*....*.... 330 | ..............*....*.... 331 | ........................ 332 | ........................ 333 | ........................ 334 | ........................ 335 | ........................ 336 | ........................ 337 | ..*.***................. 338 | ..**...*................ 339 | ..*....*................ 340 | ..*....*................ 341 | ..*....*................ 342 | ..*....*................ 343 | ........................ 344 | ........................ 345 | 346 | 3 347 | 348 | 349 | 350 | -------------------------------------------------------------------------------- /samples/drc_errors.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/drc_errors.gds -------------------------------------------------------------------------------- /samples/models.cir: -------------------------------------------------------------------------------- 1 | 2 | * FOR DEMONSTRATION PURPOSES ONLY! 3 | * 4 | * 180nm models obtained from http://ptm.asu.edu/modelcard/180nm_bulk.txt 5 | 6 | * 7 | * Predictive Technology Model Beta Version 8 | * 180nm NMOS SPICE Parametersv (normal one) 9 | * 10 | 11 | .model MLVNMOS NMOS 12 | +Level = 49 13 | 14 | +Lint = 4.e-08 Tox = 4.e-09 15 | +Vth0 = 0.3999 Rdsw = 250 16 | 17 | +lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1 18 | +Xj= 6.0000000E-08 Nch= 5.9500000E+17 19 | +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 20 | +wwn= 0.00 ll= 0.00 21 | +lw= 0.00 lwl= 0.00 wint= 0.00 22 | +wl= 0.00 ww= 0.00 wwl= 0.00 23 | +Mobmod= 1 binunit= 2 xl= 0 24 | +xw= 0 binflag= 0 25 | +Dwg= 0.00 Dwb= 0.00 26 | 27 | +K1= 0.5613000 K2= 1.0000000E-02 28 | +K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000 29 | +Dvt2= 8.0000000E-03 Dvt0w= 0.00 Dvt1w= 0.00 30 | +Dvt2w= 0.00 Nlx= 1.6500000E-07 W0= 0.00 31 | +K3b= 0.00 Ngate= 5.0000000E+20 32 | 33 | +Vsat= 1.3800000E+05 Ua= -7.0000000E-10 Ub= 3.5000000E-18 34 | +Uc= -5.2500000E-11 Prwb= 0.00 35 | +Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E-02 36 | +A0= 1.1000000 Keta= 4.0000000E-02 A1= 0.00 37 | +A2= 1.0000000 Ags= -1.0000000E-02 B0= 0.00 38 | +B1= 0.00 39 | 40 | +Voff= -0.12350000 NFactor= 0.9000000 Cit= 0.00 41 | +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 42 | +Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000 43 | 44 | +Pclm= 5.0000000E-02 Pdiblc1= 1.2000000E-02 Pdiblc2= 7.5000000E-03 45 | +Pdiblcb= -1.3500000E-02 Drout= 1.7999999E-02 Pscbe1= 8.6600000E+08 46 | +Pscbe2= 1.0000000E-20 Pvag= -0.2800000 Delta= 1.0000000E-02 47 | +Alpha0= 0.00 Beta0= 30.0000000 48 | 49 | +kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04 50 | +Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19 51 | +Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00 52 | 53 | +Cj= 0.00365 Mj= 0.54 Pb= 0.982 54 | +Cjsw= 7.9E-10 Mjsw= 0.31 Php= 0.841 55 | +Cta= 0 Ctp= 0 Pta= 0 56 | +Ptp= 0 JS=1.50E-08 JSW=2.50E-13 57 | +N=1.0 Xti=3.0 Cgdo=2.786E-10 58 | +Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2 59 | +NQSMOD= 0 Elm= 5 Xpart= 1 60 | +Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886 61 | +Cf= 1.069e-10 Clc= 0.0000001 Cle= 0.6 62 | +Dlc= 4E-08 Dwc= 0 Vfbcv= -1 63 | 64 | 65 | * 66 | * Predictive Technology Model Beta Version 67 | * 180nm PMOS SPICE Parametersv (normal one) 68 | * 69 | 70 | .model MLVPMOS PMOS 71 | +Level = 49 72 | 73 | +Lint = 3.e-08 Tox = 4.2e-09 74 | +Vth0 = -0.42 Rdsw = 450 75 | 76 | +lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1 77 | +Xj= 7.0000000E-08 Nch= 5.9200000E+17 78 | +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 79 | +wwn= 0.00 ll= 0.00 80 | +lw= 0.00 lwl= 0.00 wint= 0.00 81 | +wl= 0.00 ww= 0.00 wwl= 0.00 82 | +Mobmod= 1 binunit= 2 xl= 0.00 83 | +xw= 0.00 84 | +binflag= 0 Dwg= 0.00 Dwb= 0.00 85 | 86 | +ACM= 0 ldif=0.00 hdif=0.00 87 | +rsh= 0 rd= 0 rs= 0 88 | +rsc= 0 rdc= 0 89 | 90 | +K1= 0.5560000 K2= 0.00 91 | +K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000 92 | +Dvt2= -1.0000000E-02 Dvt0w= 0.00 Dvt1w= 0.00 93 | +Dvt2w= 0.00 Nlx= 9.5000000E-08 W0= 0.00 94 | +K3b= 0.00 Ngate= 5.0000000E+20 95 | 96 | +Vsat= 1.0500000E+05 Ua= -1.2000000E-10 Ub= 1.0000000E-18 97 | +Uc= -2.9999999E-11 Prwb= 0.00 98 | +Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E-03 99 | +A0= 2.1199999 Keta= 2.9999999E-02 A1= 0.00 100 | +A2= 0.4000000 Ags= -0.1000000 B0= 0.00 101 | +B1= 0.00 102 | 103 | +Voff= -6.40000000E-02 NFactor= 1.4000000 Cit= 0.00 104 | +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 105 | +Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000 106 | 107 | +Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2= 8.0000000E-05 108 | +Pdiblcb= 0.1450000 Drout= 5.0000000E-02 Pscbe1= 1.0000000E-20 109 | +Pscbe2= 1.0000000E-20 Pvag= -6.0000000E-02 Delta= 1.0000000E-02 110 | +Alpha0= 0.00 Beta0= 30.0000000 111 | 112 | +kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04 113 | +Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19 114 | +Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00 115 | 116 | +Cj= 0.00138 Mj= 1.05 Pb= 1.24 117 | +Cjsw= 1.44E-09 Mjsw= 0.43 Php= 0.841 118 | +Cta= 0.00093 Ctp= 0 Pta= 0.00153 119 | +Ptp= 0 JS=1.50E-08 JSW=2.50E-13 120 | +N=1.0 Xti=3.0 Cgdo=2.786E-10 121 | +Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2 122 | +NQSMOD= 0 Elm= 5 Xpart= 1 123 | +Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886 124 | +Cf= 1.058e-10 Clc= 0.0000001 Cle= 0.6 125 | +Dlc= 3E-08 Dwc= 0 Vfbcv= -1 126 | 127 | -------------------------------------------------------------------------------- /samples/ringo.cir: -------------------------------------------------------------------------------- 1 | * Netlist before simplification 2 | 3 | * cell RINGO 4 | .SUBCKT RINGO 5 | * net 11 FB 6 | * net 12 VDD 7 | * net 15 OUT 8 | * net 16 ENABLE 9 | * net 19 BULK,VSS 10 | * cell instance $1 r0 *1 1.8,0 11 | X$1 12 1 19 12 11 16 19 ND2X1 12 | * cell instance $2 r0 *1 4.2,0 13 | X$2 12 2 19 12 1 19 INVX1 14 | * cell instance $3 r0 *1 6,0 15 | X$3 12 3 19 12 2 19 INVX1 16 | * cell instance $4 r0 *1 7.8,0 17 | X$4 12 4 19 12 3 19 INVX1 18 | * cell instance $5 r0 *1 9.6,0 19 | X$5 12 5 19 12 4 19 INVX1 20 | * cell instance $6 r0 *1 11.4,0 21 | X$6 12 6 19 12 5 19 INVX1 22 | * cell instance $7 r0 *1 13.2,0 23 | X$7 12 7 19 12 6 19 INVX1 24 | * cell instance $8 r0 *1 15,0 25 | X$8 12 8 19 12 7 19 INVX1 26 | * cell instance $9 r0 *1 16.8,0 27 | X$9 12 9 19 12 8 19 INVX1 28 | * cell instance $10 r0 *1 18.6,0 29 | X$10 12 10 19 12 9 19 INVX1 30 | * cell instance $11 r0 *1 20.4,0 31 | X$11 12 11 19 12 10 19 INVX1 32 | * cell instance $12 r0 *1 22.2,0 33 | X$12 12 15 19 12 11 19 INVX1 34 | * cell instance $13 r0 *1 3.28,4 35 | X$13 11 M1M2 36 | * cell instance $14 r0 *1 21.42,4 37 | X$14 11 M1M2 38 | * cell instance $15 r0 *1 0.6,0 39 | X$15 12 19 TIE 40 | * cell instance $16 r0 *1 0,0 41 | X$16 12 19 12 EMPTY 42 | * cell instance $17 r0 *1 24,0 43 | X$17 12 19 TIE 44 | * cell instance $18 r0 *1 25.2,0 45 | X$18 12 19 12 EMPTY 46 | * cell instance $19 r0 *1 23.6,4 47 | X$19 15 M1M2 48 | * cell instance $20 r0 *1 2.6,3.1 49 | X$20 16 M1M2 50 | .ENDS RINGO 51 | 52 | * cell ND2X1 53 | * pin VDD 54 | * pin OUT 55 | * pin VSS 56 | * pin 57 | * pin B 58 | * pin A 59 | * pin BULK 60 | .SUBCKT ND2X1 1 2 3 4 5 6 9 61 | * net 1 VDD 62 | * net 2 OUT 63 | * net 3 VSS 64 | * net 5 B 65 | * net 6 A 66 | * net 9 BULK 67 | * cell instance $1 r0 *1 0.3,5.05 68 | X$1 6 1 2 PMOS3 69 | * cell instance $2 r0 *1 1,5.05 70 | X$2 5 2 1 PMOS3 71 | * cell instance $3 r0 *1 1,1.66 72 | X$3 5 2 10 NMOS2 73 | * cell instance $4 r0 *1 0.3,1.66 74 | X$4 6 10 3 NMOS2 75 | * cell instance $5 r0 *1 1.48,4 76 | X$5 5 POLYM1 77 | * cell instance $6 r0 *1 0.8,3.1 78 | X$6 6 POLYM1 79 | * device instance $1 0.85,5.8 LVPMOS 80 | M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U 81 | * device instance $2 1.55,5.8 LVPMOS 82 | M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U 83 | * device instance $3 0.85,2.135 LVNMOS 84 | M$3 3 6 10 9 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U 85 | * device instance $4 1.55,2.135 LVNMOS 86 | M$4 10 5 2 9 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U 87 | .ENDS ND2X1 88 | 89 | * cell INVX1 90 | * pin VDD 91 | * pin OUT 92 | * pin VSS 93 | * pin 94 | * pin IN 95 | * pin BULK 96 | .SUBCKT INVX1 1 2 3 4 5 7 97 | * net 1 VDD 98 | * net 2 OUT 99 | * net 3 VSS 100 | * net 5 IN 101 | * net 7 BULK 102 | * cell instance $1 r0 *1 0.3,5.05 103 | X$1 5 2 1 PMOS3 104 | * cell instance $2 r0 *1 0.3,1.66 105 | X$2 5 2 3 NMOS2 106 | * cell instance $3 r0 *1 0.6,3.1 107 | X$3 5 POLYM1 108 | * device instance $1 0.85,5.8 LVPMOS 109 | M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U 110 | * device instance $2 0.85,2.135 LVNMOS 111 | M$2 3 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U 112 | .ENDS INVX1 113 | 114 | * cell M1M2 115 | * pin 116 | .SUBCKT M1M2 1 117 | .ENDS M1M2 118 | 119 | * cell TIE 120 | * pin VDD 121 | * pin BULK,VSS 122 | .SUBCKT TIE 2 3 123 | * net 2 VDD 124 | * net 3 BULK,VSS 125 | .ENDS TIE 126 | 127 | * cell EMPTY 128 | * pin 129 | * pin 130 | * pin 131 | .SUBCKT EMPTY 1 2 3 132 | .ENDS EMPTY 133 | 134 | * cell POLYM1 135 | * pin 136 | .SUBCKT POLYM1 1 137 | .ENDS POLYM1 138 | 139 | * cell NMOS2 140 | * pin 141 | * pin 142 | * pin 143 | .SUBCKT NMOS2 1 2 3 144 | .ENDS NMOS2 145 | 146 | * cell PMOS3 147 | * pin 148 | * pin 149 | * pin 150 | .SUBCKT PMOS3 1 2 3 151 | .ENDS PMOS3 152 | -------------------------------------------------------------------------------- /samples/ringo.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/ringo.gds -------------------------------------------------------------------------------- /samples/ringo_simplified.cir: -------------------------------------------------------------------------------- 1 | * Netlist after simplification 2 | 3 | * cell RINGO 4 | * pin FB 5 | * pin VDD 6 | * pin OUT 7 | * pin ENABLE 8 | * pin BULK,VSS 9 | .SUBCKT RINGO 11 12 13 14 15 10 | * net 11 FB 11 | * net 12 VDD 12 | * net 13 OUT 13 | * net 14 ENABLE 14 | * net 15 BULK,VSS 15 | * cell instance $1 r0 *1 1.8,0 16 | X$1 12 1 15 12 11 14 15 ND2X1 17 | * cell instance $2 r0 *1 4.2,0 18 | X$2 12 2 15 12 1 15 INVX1 19 | * cell instance $3 r0 *1 6,0 20 | X$3 12 3 15 12 2 15 INVX1 21 | * cell instance $4 r0 *1 7.8,0 22 | X$4 12 4 15 12 3 15 INVX1 23 | * cell instance $5 r0 *1 9.6,0 24 | X$5 12 5 15 12 4 15 INVX1 25 | * cell instance $6 r0 *1 11.4,0 26 | X$6 12 6 15 12 5 15 INVX1 27 | * cell instance $7 r0 *1 13.2,0 28 | X$7 12 7 15 12 6 15 INVX1 29 | * cell instance $8 r0 *1 15,0 30 | X$8 12 8 15 12 7 15 INVX1 31 | * cell instance $9 r0 *1 16.8,0 32 | X$9 12 9 15 12 8 15 INVX1 33 | * cell instance $10 r0 *1 18.6,0 34 | X$10 12 10 15 12 9 15 INVX1 35 | * cell instance $11 r0 *1 20.4,0 36 | X$11 12 11 15 12 10 15 INVX1 37 | * cell instance $12 r0 *1 22.2,0 38 | X$12 12 13 15 12 11 15 INVX1 39 | .ENDS RINGO 40 | 41 | * cell ND2X1 42 | * pin VDD 43 | * pin OUT 44 | * pin VSS 45 | * pin 46 | * pin B 47 | * pin A 48 | * pin BULK 49 | .SUBCKT ND2X1 1 2 3 4 5 6 7 50 | * net 1 VDD 51 | * net 2 OUT 52 | * net 3 VSS 53 | * net 5 B 54 | * net 6 A 55 | * net 7 BULK 56 | * device instance $1 0.85,5.8 LVPMOS 57 | M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U 58 | * device instance $2 1.55,5.8 LVPMOS 59 | M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U 60 | * device instance $3 0.85,2.135 LVNMOS 61 | M$3 3 6 8 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U 62 | * device instance $4 1.55,2.135 LVNMOS 63 | M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U 64 | .ENDS ND2X1 65 | 66 | * cell INVX1 67 | * pin VDD 68 | * pin OUT 69 | * pin VSS 70 | * pin 71 | * pin IN 72 | * pin BULK 73 | .SUBCKT INVX1 1 2 3 4 5 6 74 | * net 1 VDD 75 | * net 2 OUT 76 | * net 3 VSS 77 | * net 5 IN 78 | * net 6 BULK 79 | * device instance $1 0.85,5.8 LVPMOS 80 | M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U 81 | * device instance $2 0.85,2.135 LVNMOS 82 | M$2 3 5 2 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U 83 | .ENDS INVX1 84 | -------------------------------------------------------------------------------- /samples/ringo_testbench.cir: -------------------------------------------------------------------------------- 1 | 2 | .INCLUDE "models.cir" 3 | 4 | .INCLUDE "ringo_simplified.cir" 5 | 6 | VDD VDD 0 1.8V 7 | VPULSE EN 0 PULSE(0,1.8V,1NS,1NS) 8 | 9 | XRINGO FB VDD OUT EN 0 RINGO 10 | 11 | .TRAN 0.01NS 100NS 12 | 13 | .PRINT TRAN V(EN) V(FB) V(OUT) 14 | 15 | -------------------------------------------------------------------------------- /samples/ringo_with_hierarchical_nets.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/ringo_with_hierarchical_nets.gds -------------------------------------------------------------------------------- /samples/ringo_with_hierarchical_nets.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #c0c0c0 5 | #c0c0c0 6 | 0 7 | 0 8 | I9 9 | I2 10 | true 11 | true 12 | false 13 | 2 14 | false 15 | false 16 | 0 17 | 1 - NWELL 18 | 1/0@1 19 | 20 | 21 | #c0c0c0 22 | #c0c0c0 23 | 48 24 | 48 25 | C0 26 | I4 27 | true 28 | true 29 | false 30 | 1 31 | false 32 | false 33 | 0 34 | 3 - PPLUS 35 | 3/0@1 36 | 37 | 38 | #c0c0c0 39 | #c0c0c0 40 | 48 41 | 48 42 | C1 43 | I4 44 | true 45 | true 46 | false 47 | 1 48 | false 49 | false 50 | 0 51 | 4 - NPLUS 52 | 4/0@1 53 | 54 | 55 | #ff0000 56 | #ff9d9d 57 | -64 58 | -64 59 | I3 60 | I2 61 | true 62 | true 63 | false 64 | 2 65 | false 66 | false 67 | 0 68 | 2 - DIFF 69 | 2/0@1 70 | 71 | 72 | #91ff00 73 | #91ff00 74 | -48 75 | -48 76 | I8 77 | 78 | true 79 | true 80 | false 81 | 2 82 | false 83 | false 84 | 0 85 | 5 - POLY 86 | 5/0@1 87 | 88 | 89 | #008000 90 | #808000 91 | 0 92 | 0 93 | I3 94 | I4 95 | true 96 | true 97 | false 98 | 1 99 | false 100 | false 101 | 0 102 | 6 - THICKOX 103 | THICKOX 6/0@1 104 | 105 | 106 | #805000 107 | #805000 108 | 0 109 | 0 110 | I3 111 | I4 112 | true 113 | true 114 | false 115 | 1 116 | false 117 | false 118 | 0 119 | 7 - POLYRES 120 | '7 - SALBL' 7/0@1 121 | 122 | 123 | #ff00ff 124 | #ffffff 125 | 0 126 | 0 127 | I0 128 | 129 | true 130 | true 131 | false 132 | 2 133 | false 134 | true 135 | 0 136 | 8 - CONTACT 137 | 8/0@1 138 | 139 | 140 | #8000ff 141 | #9580ff 142 | 0 143 | 0 144 | I4 145 | 146 | true 147 | true 148 | false 149 | 2 150 | false 151 | false 152 | 0 153 | 9 - METAL1 154 | 9/0@1 155 | 156 | 157 | #e872ff 158 | #e872ff 159 | -48 160 | -48 161 | I1 162 | 163 | true 164 | true 165 | false 166 | 2 167 | false 168 | true 169 | 0 170 | 10 - VIA 171 | 10/0@1 172 | 173 | 174 | #0000ff 175 | #8086ff 176 | 0 177 | 0 178 | I8 179 | 180 | true 181 | true 182 | false 183 | 2 184 | false 185 | false 186 | 0 187 | 11 - METAL2 188 | 11/0@1 189 | 190 | 191 | #808080 192 | #c0c0c0 193 | 0 194 | 128 195 | I43 196 | 197 | true 198 | true 199 | true 200 | 1 201 | false 202 | false 203 | 0 204 | 12 - PAD 205 | 12/0@1 206 | 207 | 208 | #c0c0c0 209 | #c0c0c0 210 | 0 211 | 0 212 | I1 213 | I4 214 | true 215 | true 216 | false 217 | 1 218 | false 219 | false 220 | 0 221 | 13 - BORDER 222 | 13/0@1 223 | 224 | 225 | #606060 226 | #606060 227 | 0 228 | 0 229 | I1 230 | I2 231 | true 232 | false 233 | false 234 | 1 235 | false 236 | true 237 | 0 238 | 1000 - MARKING 1 239 | 1000/0@1 240 | 241 | 242 | #000000 243 | #000000 244 | 0 245 | 0 246 | I1 247 | I2 248 | true 249 | false 250 | false 251 | 1 252 | false 253 | false 254 | 0 255 | 1001 - MARKING 2 256 | 1001/0@1 257 | 258 | 259 | #ff8000 260 | #ff8000 261 | 0 262 | 0 263 | I6 264 | 265 | true 266 | true 267 | false 268 | 1 269 | false 270 | false 271 | 0 272 | 273 | 2000/0@1 274 | 275 | 276 | #ff8000 277 | #ff8000 278 | 0 279 | 0 280 | I10 281 | 282 | true 283 | true 284 | false 285 | 1 286 | false 287 | false 288 | 0 289 | 290 | 2001/0@1 291 | 292 | 293 | #ff8000 294 | #ff8000 295 | 0 296 | 0 297 | I6 298 | 299 | true 300 | true 301 | false 302 | 1 303 | false 304 | false 305 | 0 306 | 307 | 2002/0@1 308 | 309 | 310 | #ff8000 311 | #ff8000 312 | 0 313 | 0 314 | I10 315 | 316 | true 317 | true 318 | false 319 | 1 320 | false 321 | false 322 | 0 323 | 324 | 2003/0@1 325 | 326 | 327 | #ff8000 328 | #ff8000 329 | 0 330 | 0 331 | I6 332 | 333 | true 334 | true 335 | false 336 | 1 337 | false 338 | false 339 | 0 340 | 341 | 2004/0@1 342 | 343 | 344 | #ff8000 345 | #ff8000 346 | 0 347 | 0 348 | I10 349 | 350 | true 351 | true 352 | false 353 | 1 354 | false 355 | false 356 | 0 357 | 358 | 2005/0@1 359 | 360 | 361 | #ff8000 362 | #ff8000 363 | 0 364 | 0 365 | I6 366 | 367 | true 368 | true 369 | false 370 | 1 371 | false 372 | false 373 | 0 374 | 375 | 2006/0@1 376 | 377 | 378 | #ff8000 379 | #ff8000 380 | 0 381 | 0 382 | I10 383 | 384 | true 385 | true 386 | false 387 | 1 388 | false 389 | false 390 | 0 391 | 392 | 2007/0@1 393 | 394 | 395 | #ff8000 396 | #ff8000 397 | 0 398 | 0 399 | I6 400 | 401 | true 402 | true 403 | false 404 | 1 405 | false 406 | false 407 | 0 408 | 409 | 2008/0@1 410 | 411 | 412 | #ff8000 413 | #ff8000 414 | 0 415 | 0 416 | I10 417 | 418 | true 419 | true 420 | false 421 | 1 422 | false 423 | false 424 | 0 425 | 426 | 2009/0@1 427 | 428 | 429 | 430 | 431 | ................ 432 | ...*............ 433 | ...*............ 434 | ...*............ 435 | *******......... 436 | ...*............ 437 | ...*............ 438 | ...*............ 439 | ................ 440 | ...........*.... 441 | ...........*.... 442 | ...........*.... 443 | ........*******. 444 | ...........*.... 445 | ...........*.... 446 | ...........*.... 447 | 448 | 1 449 | custom plus 450 | 451 | 452 | 453 | ................ 454 | ................ 455 | ................ 456 | ................ 457 | *******......... 458 | ................ 459 | ................ 460 | ................ 461 | ................ 462 | ................ 463 | ................ 464 | ................ 465 | ........*******. 466 | ................ 467 | ................ 468 | ................ 469 | 470 | 2 471 | 472 | 473 | 474 | -------------------------------------------------------------------------------- /samples/vdiv.cir: -------------------------------------------------------------------------------- 1 | * Netlist before simplification 2 | 3 | * cell TOP 4 | .SUBCKT TOP 5 | * net 1 OUT 6 | * net 2 GND 7 | * net 4 IN 8 | * net 6 VDD 9 | * device instance $1 1.255,0.335 RES 10 | R$1 5 1 7650 11 | * device instance $2 3.08,0.335 RES 12 | R$2 3 1 7650 13 | * device instance $3 4.945,0.335 RES 14 | R$3 3 2 2670 15 | * device instance $4 1.765,7.485 HVPMOS 16 | M$4 5 4 6 6 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U 17 | .ENDS TOP 18 | -------------------------------------------------------------------------------- /samples/vdiv.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/vdiv.gds -------------------------------------------------------------------------------- /samples/vdiv_simplified.cir: -------------------------------------------------------------------------------- 1 | * Netlist after simplification 2 | 3 | * cell TOP 4 | * pin OUT 5 | * pin GND 6 | * pin IN 7 | * pin VDD 8 | .SUBCKT TOP 1 2 3 5 9 | * net 1 OUT 10 | * net 2 GND 11 | * net 3 IN 12 | * net 5 VDD 13 | * device instance $1 1.255,0.335 RES 14 | R$1 4 1 7650 15 | * device instance $2 3.08,0.335 RES 16 | R$2 2 1 10320 17 | * device instance $4 1.765,7.485 HVPMOS 18 | M$4 4 3 5 5 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U 19 | .ENDS TOP 20 | -------------------------------------------------------------------------------- /samples/xs.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/klayoutmatthias/si4all/51bff19ee59377e46fc373b6c3b74fd153c6e53a/samples/xs.gds -------------------------------------------------------------------------------- /tech.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #c0c0c0 5 | #c0c0c0 6 | 0 7 | 0 8 | I9 9 | I2 10 | true 11 | true 12 | false 13 | 2 14 | false 15 | false 16 | 0 17 | 1 - NWELL 18 | 1/0@1 19 | 20 | 21 | #c0c0c0 22 | #c0c0c0 23 | 48 24 | 48 25 | C0 26 | I4 27 | true 28 | true 29 | false 30 | 1 31 | false 32 | false 33 | 0 34 | 3 - PPLUS 35 | 3/0@1 36 | 37 | 38 | #c0c0c0 39 | #c0c0c0 40 | 48 41 | 48 42 | C1 43 | I4 44 | true 45 | true 46 | false 47 | 1 48 | false 49 | false 50 | 0 51 | 4 - NPLUS 52 | 4/0@1 53 | 54 | 55 | #ff0000 56 | #ff9d9d 57 | -64 58 | -64 59 | I3 60 | I2 61 | true 62 | true 63 | false 64 | 2 65 | false 66 | false 67 | 0 68 | 2 - DIFF 69 | 2/0@1 70 | 71 | 72 | #91ff00 73 | #91ff00 74 | -48 75 | -48 76 | I8 77 | 78 | true 79 | true 80 | false 81 | 2 82 | false 83 | false 84 | 0 85 | 5 - POLY 86 | 5/0@1 87 | 88 | 89 | #008000 90 | #808000 91 | 0 92 | 0 93 | I3 94 | I4 95 | true 96 | true 97 | false 98 | 1 99 | false 100 | false 101 | 0 102 | 6 - THICKOX 103 | THICKOX 6/0@1 104 | 105 | 106 | #805000 107 | #805000 108 | 0 109 | 0 110 | I3 111 | I4 112 | true 113 | true 114 | false 115 | 1 116 | false 117 | false 118 | 0 119 | 7 - POLYRES 120 | '7 - SALBL' 7/0@1 121 | 122 | 123 | #ff00ff 124 | #ffffff 125 | 0 126 | 0 127 | I0 128 | 129 | true 130 | true 131 | false 132 | 2 133 | false 134 | true 135 | 0 136 | 8 - CONTACT 137 | 8/0@1 138 | 139 | 140 | #8000ff 141 | #9580ff 142 | 0 143 | 0 144 | I4 145 | 146 | true 147 | true 148 | false 149 | 2 150 | false 151 | false 152 | 0 153 | 9 - METAL1 154 | 9/0@1 155 | 156 | 157 | #e872ff 158 | #e872ff 159 | -48 160 | -48 161 | I1 162 | 163 | true 164 | true 165 | false 166 | 2 167 | false 168 | true 169 | 0 170 | 10 - VIA 171 | 10/0@1 172 | 173 | 174 | #0000ff 175 | #8086ff 176 | 0 177 | 0 178 | I8 179 | 180 | true 181 | true 182 | false 183 | 2 184 | false 185 | false 186 | 0 187 | 11 - METAL2 188 | 11/0@1 189 | 190 | 191 | #808080 192 | #c0c0c0 193 | 0 194 | 128 195 | I43 196 | 197 | true 198 | true 199 | true 200 | 1 201 | false 202 | false 203 | 0 204 | 12 - PAD 205 | 12/0@1 206 | 207 | 208 | #c0c0c0 209 | #c0c0c0 210 | 0 211 | 0 212 | I1 213 | I4 214 | true 215 | true 216 | false 217 | 1 218 | false 219 | false 220 | 0 221 | 13 - BORDER 222 | 13/0@1 223 | 224 | 225 | #606060 226 | #606060 227 | 0 228 | 0 229 | I1 230 | I2 231 | true 232 | true 233 | false 234 | 1 235 | false 236 | true 237 | 0 238 | 1000 - MARKING 1 239 | 1000/0@1 240 | 241 | 242 | #000000 243 | #000000 244 | 0 245 | 0 246 | I1 247 | I2 248 | true 249 | true 250 | false 251 | 1 252 | false 253 | false 254 | 0 255 | 1001 - MARKING 2 256 | 1001/0@1 257 | 258 | 259 | 260 | 261 | ................ 262 | ...*............ 263 | ...*............ 264 | ...*............ 265 | *******......... 266 | ...*............ 267 | ...*............ 268 | ...*............ 269 | ................ 270 | ...........*.... 271 | ...........*.... 272 | ...........*.... 273 | ........*******. 274 | ...........*.... 275 | ...........*.... 276 | ...........*.... 277 | 278 | 1 279 | custom plus 280 | 281 | 282 | 283 | ................ 284 | ................ 285 | ................ 286 | ................ 287 | *******......... 288 | ................ 289 | ................ 290 | ................ 291 | ................ 292 | ................ 293 | ................ 294 | ................ 295 | ........*******. 296 | ................ 297 | ................ 298 | ................ 299 | 300 | 2 301 | 302 | 303 | 304 | -------------------------------------------------------------------------------- /xs.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #808080 5 | #808080 6 | 0 7 | 0 8 | I3 9 | 10 | true 11 | true 12 | false 13 | 0 14 | false 15 | false 16 | 0 17 | 18 | 1/0@1 19 | 20 | 21 | #c0c0c0 22 | #c0c0c0 23 | 0 24 | 0 25 | I5 26 | I4 27 | true 28 | true 29 | false 30 | 2 31 | false 32 | false 33 | 0 34 | 35 | 2/0@1 36 | 37 | 38 | #008000 39 | #008000 40 | 64 41 | 64 42 | I8 43 | 44 | true 45 | true 46 | false 47 | 2 48 | false 49 | false 50 | 0 51 | 52 | 3/0@1 53 | 54 | 55 | #ff0000 56 | #ff0000 57 | 0 58 | 0 59 | I4 60 | I0 61 | true 62 | true 63 | false 64 | 2 65 | false 66 | false 67 | 0 68 | 69 | 4/0@1 70 | 71 | 72 | #afff80 73 | #afff80 74 | -32 75 | -32 76 | I0 77 | 78 | true 79 | true 80 | false 81 | 1 82 | false 83 | false 84 | 0 85 | 86 | 5/0@1 87 | 88 | 89 | #ff00ff 90 | #ff00ff 91 | -48 92 | -48 93 | I0 94 | 95 | true 96 | true 97 | false 98 | 1 99 | false 100 | false 101 | 0 102 | 103 | 6/0@1 104 | 105 | 106 | #800080 107 | #800080 108 | 0 109 | 0 110 | I0 111 | 112 | true 113 | true 114 | false 115 | 1 116 | false 117 | false 118 | 0 119 | 120 | 7/0@1 121 | 122 | 123 | #008080 124 | #008080 125 | 0 126 | 0 127 | I0 128 | 129 | true 130 | true 131 | false 132 | 1 133 | false 134 | false 135 | 0 136 | 137 | 8/0@1 138 | 139 | 140 | #000080 141 | #000080 142 | 0 143 | 0 144 | I0 145 | 146 | true 147 | true 148 | false 149 | 1 150 | false 151 | false 152 | 0 153 | 154 | 9/0@1 155 | 156 | 157 | #800080 158 | #800080 159 | 0 160 | 0 161 | I8 162 | 163 | true 164 | true 165 | false 166 | 2 167 | false 168 | false 169 | 0 170 | 171 | 10/0@1 172 | 173 | 174 | #0080ff 175 | #0080ff 176 | 0 177 | 0 178 | I3 179 | 180 | true 181 | true 182 | false 183 | 0 184 | false 185 | false 186 | 0 187 | 188 | 11/0@1 189 | 190 | 191 | #800000 192 | #800000 193 | 0 194 | 0 195 | I2 196 | 197 | true 198 | true 199 | false 200 | 0 201 | false 202 | false 203 | 0 204 | 205 | 12/0@1 206 | 207 | 208 | 209 | --------------------------------------------------------------------------------