├── .editorconfig ├── .gitignore ├── LICENSE ├── README.md └── ch559 ├── examples ├── Makefile.include ├── advanced_blink │ ├── Makefile │ └── main.c ├── blink │ ├── Makefile │ └── blink.c └── uart │ ├── Makefile │ └── main.c └── lib ├── ch559.h ├── compiler.h ├── uart.c └── uart.h /.editorconfig: -------------------------------------------------------------------------------- 1 | root = true 2 | 3 | [*] 4 | indent_style = tab 5 | indent_size = tab 6 | trim_trailing_whitespace = true 7 | insert_final_newline = true -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Assembly files 5 | *.asm 6 | 7 | # Object files 8 | *.o 9 | *.ko 10 | *.obj 11 | *.elf 12 | 13 | # Linker output 14 | *.ilk 15 | *.map 16 | *.exp 17 | *.lk 18 | 19 | # Precompiled Headers 20 | *.gch 21 | *.pch 22 | 23 | # Libraries 24 | *.lib 25 | *.a 26 | *.la 27 | *.lo 28 | *.rel 29 | 30 | # Shared objects (inc. Windows DLLs) 31 | *.dll 32 | *.so 33 | *.so.* 34 | *.dylib 35 | 36 | # Executables 37 | *.exe 38 | *.out 39 | *.app 40 | *.i*86 41 | *.x86_64 42 | *.hex 43 | *.bin 44 | *.ihx 45 | 46 | # Debug files 47 | *.dSYM/ 48 | *.su 49 | *.idb 50 | *.pdb 51 | 52 | # Kernel Module Compile Results 53 | *.mod* 54 | *.cmd 55 | .tmp_versions/ 56 | modules.order 57 | Module.symvers 58 | Mkfile.old 59 | dkms.conf 60 | 61 | # Other files 62 | 63 | *.lst 64 | *.mem 65 | *.rst 66 | *.sym 67 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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It is safest 289 | to attach them to the start of each source file to most effectively 290 | convey the exclusion of warranty; and each file should have at least 291 | the "copyright" line and a pointer to where the full notice is found. 292 | 293 | 294 | Copyright (C) 295 | 296 | This program is free software; you can redistribute it and/or modify 297 | it under the terms of the GNU General Public License as published by 298 | the Free Software Foundation; either version 2 of the License, or 299 | (at your option) any later version. 300 | 301 | This program is distributed in the hope that it will be useful, 302 | but WITHOUT ANY WARRANTY; without even the implied warranty of 303 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 304 | GNU General Public License for more details. 305 | 306 | You should have received a copy of the GNU General Public License along 307 | with this program; if not, write to the Free Software Foundation, Inc., 308 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this 313 | when it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author 316 | Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 317 | This is free software, and you are welcome to redistribute it 318 | under certain conditions; type `show c' for details. 319 | 320 | The hypothetical commands `show w' and `show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | , 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ch55x_bare_metal 2 | 3 | A simple peripheral library for CH55x microcontrollers. This library is for my series of [blog posts](https://kprasadvnsi.com/posts/bare-metal-ch559-pt1/) on CH55x microcontrollers. 4 | 5 | # Credits 6 | 7 | - [Blinkinlabs/ch554_sdcc](https://github.com/Blinkinlabs/ch554_sdcc) for their Makefiles. 8 | -------------------------------------------------------------------------------- /ch559/examples/Makefile.include: -------------------------------------------------------------------------------- 1 | ####################################################### 2 | 3 | # toolchain 4 | CC = sdcc 5 | OBJCOPY = objcopy 6 | PACK_HEX = packihx 7 | WCHISP = wchisptool 8 | 9 | ####################################################### 10 | 11 | ifndef FREQ_SYS 12 | FREQ_SYS = 12000000 13 | endif 14 | 15 | ifndef XRAM_SIZE 16 | XRAM_SIZE = 0x1800 17 | endif 18 | 19 | ifndef XRAM_LOC 20 | XRAM_LOC = 0x0000 21 | endif 22 | 23 | ifndef CODE_SIZE 24 | CODE_SIZE = 0xF000 25 | endif 26 | 27 | ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) 28 | 29 | CFLAGS := -V -mmcs51 --model-small \ 30 | --xram-size $(XRAM_SIZE) --xram-loc $(XRAM_LOC) \ 31 | --code-size $(CODE_SIZE) \ 32 | -I$(ROOT_DIR)../lib -DFREQ_SYS=$(FREQ_SYS) \ 33 | $(EXTRA_FLAGS) 34 | 35 | LFLAGS := $(CFLAGS) 36 | 37 | RELS := $(C_FILES:.c=.rel) 38 | 39 | print-% : ; @echo $* = $($*) 40 | 41 | %.rel : %.c 42 | $(CC) -c $(CFLAGS) $< 43 | 44 | # Note: SDCC will dump all of the temporary files into this one, so strip the paths from RELS 45 | # For now, get around this by stripping the paths off of the RELS list. 46 | 47 | $(TARGET).ihx: $(RELS) 48 | $(CC) $(notdir $(RELS)) $(LFLAGS) -o $(TARGET).ihx 49 | 50 | $(TARGET).hex: $(TARGET).ihx 51 | $(PACK_HEX) $(TARGET).ihx > $(TARGET).hex 52 | 53 | $(TARGET).bin: $(TARGET).ihx 54 | $(OBJCOPY) -I ihex -O binary $(TARGET).ihx $(TARGET).bin 55 | 56 | flash: $(TARGET).bin pre-flash 57 | $(WCHISP) -f $(TARGET).bin -g 58 | 59 | .DEFAULT_GOAL := all 60 | all: $(TARGET).bin $(TARGET).hex 61 | 62 | clean: 63 | rm -f \ 64 | $(notdir $(RELS:.rel=.asm)) \ 65 | $(notdir $(RELS:.rel=.lst)) \ 66 | $(notdir $(RELS:.rel=.mem)) \ 67 | $(notdir $(RELS:.rel=.rel)) \ 68 | $(notdir $(RELS:.rel=.rst)) \ 69 | $(notdir $(RELS:.rel=.sym)) \ 70 | $(notdir $(RELS:.rel=.adb)) \ 71 | $(TARGET).lk \ 72 | $(TARGET).map \ 73 | $(TARGET).mem \ 74 | $(TARGET).ihx \ 75 | $(TARGET).hex \ 76 | $(TARGET).bin 77 | -------------------------------------------------------------------------------- /ch559/examples/advanced_blink/Makefile: -------------------------------------------------------------------------------- 1 | TARGET = adv_blink 2 | 3 | C_FILES = \ 4 | main.c 5 | 6 | include ../Makefile.include 7 | -------------------------------------------------------------------------------- /ch559/examples/advanced_blink/main.c: -------------------------------------------------------------------------------- 1 | 2 | // Blink LEDs connected to port P0 3 | 4 | #include 5 | #include 6 | 7 | #define MASK_P0_OC 0x0F 8 | 9 | static inline void delay() { 10 | uint32_t i; 11 | for (i = 0; i < (5 * 12000UL); i++){} 12 | __asm__("nop"); 13 | } 14 | 15 | void run_led () { 16 | uint8_t i; 17 | for(i=0; i<8; i++) { 18 | P0 = (1 << i); 19 | delay(); 20 | } 21 | } 22 | 23 | void main() { 24 | 25 | PORT_CFG |= bP0_DRV | (MASK_P0_OC & ~bP0_OC); // Set port P0 driving current and output mode. 26 | P0_DIR = 0xFF; // Set all bits to output mode 27 | 28 | // Turning all bits to high 29 | P0 = 0xFF; 30 | delay(); 31 | delay(); 32 | delay(); 33 | delay(); 34 | 35 | 36 | // Turning all bits to low 37 | P0 = 0x00; 38 | delay(); 39 | delay(); 40 | delay(); 41 | delay(); 42 | 43 | // Turning alternate bits to high 44 | P0 = 0xAA; 45 | delay(); 46 | delay(); 47 | delay(); 48 | delay(); 49 | 50 | // Turning upper half bits to high 51 | P0 = 0xF0; 52 | delay(); 53 | delay(); 54 | delay(); 55 | delay(); 56 | 57 | // Turning lower half bits to high 58 | P0 = 0x0F; 59 | delay(); 60 | delay(); 61 | delay(); 62 | delay(); 63 | 64 | while (1) { 65 | run_led(); 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /ch559/examples/blink/Makefile: -------------------------------------------------------------------------------- 1 | TARGET = blink 2 | 3 | C_FILES = \ 4 | blink.c 5 | 6 | include ../Makefile.include 7 | -------------------------------------------------------------------------------- /ch559/examples/blink/blink.c: -------------------------------------------------------------------------------- 1 | 2 | // Blink a LED connected to pin 1.6 3 | 4 | #include 5 | #include 6 | 7 | static inline void delay() { 8 | uint32_t i; 9 | for (i = 0; i < (120000UL); i++){} 10 | __asm__("nop"); 11 | } 12 | 13 | void main() { 14 | PORT_CFG = 0b00101101; 15 | P1_DIR = 0b11110000; 16 | P1 = 0x00; 17 | 18 | while (1) { 19 | delay(); 20 | P1_6 = !P1_6; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /ch559/examples/uart/Makefile: -------------------------------------------------------------------------------- 1 | TARGET = uart 2 | 3 | C_FILES = \ 4 | main.c \ 5 | ../../lib/uart.c 6 | 7 | include ../Makefile.include 8 | -------------------------------------------------------------------------------- /ch559/examples/uart/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | /* 7 | * Redirect stdout to UART0 8 | */ 9 | int putchar(int c) { 10 | uart0_write(c); 11 | return 0; 12 | } 13 | 14 | /* 15 | * Redirect stdin to UART0 16 | */ 17 | int getchar() { 18 | return uart0_read(); 19 | } 20 | 21 | void main() { 22 | uart0_init(); 23 | printf("Hello World!\n"); 24 | while (1) {} 25 | } 26 | -------------------------------------------------------------------------------- /ch559/lib/ch559.h: -------------------------------------------------------------------------------- 1 | /* 2 | v1.1 changes 3 | - new record defs for XSFRs see USBXSFR and LEDXSFR 4 | */ 5 | 6 | #ifndef CH559_H_ 7 | 8 | #include "compiler.h" 9 | /* System Registers */ 10 | SFR_(PSW,0xD0); // program status word 11 | SBIT_(CY,0xD0,7); // carry flag 12 | SBIT_(AC,0xD0,6); // auxiliary carry flag 13 | SBIT_(F0,0xD0,5); // bit addressable general purpose flag 0 14 | SBIT_(RS1,0xD0,4); // register R0-R7 bank selection high bit 15 | SBIT_(RS0,0xD0,3); // register R0-R7 bank selection low bit 16 | SBIT_(OV,0xD0,2); // overflow flag 17 | SBIT_(F1,0xD0,1); // bit addressable general purpose flag 1 18 | SBIT_(P,0xD0,0); // ReadOnly: parity flag 19 | 20 | #define MASK_PSW_RS 0x18 // bit mask of register R0-R7 bank selection 21 | // RS1 & RS0: register R0-R7 bank selection 22 | // 00 - bank 0, R0-R7 @ address 0x00-0x07 23 | // 01 - bank 1, R0-R7 @ address 0x08-0x0F 24 | // 10 - bank 2, R0-R7 @ address 0x10-0x17 25 | // 11 - bank 3, R0-R7 @ address 0x18-0x1F 26 | SFR_(ACC,0xE0); // accumulator 27 | SBIT_(ACC7,0xE0,7); 28 | SBIT_(ACC6,0xE0,6); 29 | SBIT_(ACC5,0xE0,5); 30 | SBIT_(ACC4,0xE0,4); 31 | SBIT_(ACC3,0xE0,3); 32 | SBIT_(ACC2,0xE0,2); 33 | SBIT_(ACC1,0xE0,1); 34 | SBIT_(ACC0,0xE0,0); 35 | SFR_(B,0xF0); // general purpose register B 36 | SBIT_(B07,0xF0,7); 37 | SBIT_(B06,0xF0,6); 38 | SBIT_(B05,0xF0,5); 39 | SBIT_(B04,0xF0,4); 40 | SBIT_(B03,0xF0,3); 41 | SBIT_(B02,0xF0,2); 42 | SBIT_(B01,0xF0,1); 43 | SBIT_(B00,0xF0,0); 44 | SFR_(SP,0x81); // stack pointer 45 | SFR_(DPL,0x82); // data pointer low 46 | SFR_(DPH,0x83); // data pointer high 47 | SFR_(SAFE_MOD,0xA1); // WriteOnly: writing safe mode 48 | SFR_(CHIP_ID,0xA1); // ReadOnly: reading chip ID 49 | SFR_(GLOBAL_CFG,0xB1); // global config, Write@SafeMode 50 | #define bBOOT_LOAD 0x20 // ReadOnly: boot loader status for discriminating BootLoader or Application: set 1 by power on reset, clear 0 by software reset 51 | #define bSW_RESET 0x10 // software reset bit, auto clear by hardware 52 | #define bCODE_WE 0x08 // enable flash-ROM (include code & data area) being program or erasing: 0=writing protect, 1=enable program and erase 53 | #define bDATA_WE 0x04 // enable Data-Flash (flash-ROM data area) being program or erasing: 0=writing protect, 1=enable program and erase 54 | #define bXIR_XSFR 0x02 // force MOVX_@R0/@R1 only for xSFR area: 0=MOVX_@R0/@R1 for standard xdata area inclde xRAM&xBUS&xSFR, 1=MOVX_@R0/@R1 for xSFR only 55 | #define bWDOG_EN 0x01 // enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow 56 | 57 | /* Clock and Sleep and Power Registers */ 58 | SFR_(PCON,0x87); // power control and reset flag 59 | #define SMOD 0x80 // baud rate selection for UART0 mode 1/2/3: 0=slow(Fsys/128 @mode2, TF1/32 @mode1/3, no effect for TF2), 60 | // 1=fast(Fsys/32 @mode2, TF1/16 @mode1/3, no effect for TF2) 61 | #define bRST_FLAG1 0x20 // ReadOnly: recent reset flag high bit 62 | #define bRST_FLAG0 0x10 // ReadOnly: recent reset flag low bit 63 | #define MASK_RST_FLAG 0x30 // ReadOnly: bit mask of recent reset flag 64 | #define RST_FLAG_SW 0x00 65 | #define RST_FLAG_POR 0x10 66 | #define RST_FLAG_WDOG 0x20 67 | #define RST_FLAG_PIN 0x30 68 | #define GF1 0x08 // general purpose flag bit 1 69 | #define GF0 0x04 // general purpose flag bit 0 70 | #define PD 0x02 // power-down enable bit, auto clear by wake-up hardware 71 | // bPC_RST_FLAG1 & bPC_RST_FLAG0: recent reset flag 72 | // 00 - software reset, by bSW_RESET=1 @(bBOOT_LOAD=0 or bWDOG_EN=1) 73 | // 01 - power on reset 74 | // 10 - watch-dog timer overflow reset 75 | // 11 - external input manual reset by RST pin 76 | 77 | SFR_(PLL_CFG,0xB2); // PLL clock config: lower 5 bits for PLL clock Fpll, upper 3 bits for USB 4x clock Fusb4x, Write@SafeMode 78 | #define MASK_PLL_MULT 0x1F// bit mask of PLL clock Fpll multiple 79 | #define MASK_USB_4X_DIV 0xE0// bit mask of USB 4x clock Fusb4x divisor, value 000b means 1000b 80 | SFR_(CLOCK_CFG,0xB3); // system clock config: lower 5 bits for system clock Fsys, Write@SafeMode 81 | #define bOSC_EN_INT 0x80// internal oscillator enable and original clock selection: 1=enable & select internal clock, 0=disable & select external clock 82 | #define bOSC_EN_XT 0x40// external oscillator enable, need quartz crystal or ceramic resonator between X1 and X2 pins 83 | #define bWDOG_IF_TO 0x20// ReadOnly: watch-dog timer overflow interrupt flag, cleared by reload watch-dog count or auto cleared when MCU enter interrupt routine 84 | #define MASK_SYS_CK_DIV 0x1F// bit mask of system clock Fsys divisor, value 00000b means 100000b 85 | /* 86 | Fxt = 4MHz~20MHz, from external oscillator @XI&XO 87 | Fosc = bOSC_EN_INT ? 12MHz : Fxt 88 | Fpll = Fosc * ( PLL_CFG & MASK_PLL_MULT ) => 288MHz (24MHz~350MHz) 89 | Kusb = ( PLL_CFG & MASK_USB_4X_DIV ) >> 5 90 | Fusb4x = Fpll / ( Kusb ? Kusb : 8 ) => 48MHz (Fixed) 91 | Ksys = CLOCK_CFG & MASK_SYS_CK_DIV 92 | Fsys = Fpll / ( Ksys ? Ksys : 32 ) => 12MHz (1MHz~56MHz) 93 | */ 94 | SFR_(SLEEP_CTRL,0xEA); // sleep control, Write@SafeMode 95 | #define bSLP_OFF_USB 0x80// clock off for USB 96 | #define bSLP_OFF_ADC 0x40// clock off for ADC 97 | #define bSLP_OFF_UART1 0x20// clock off for UART1 98 | #define bSLP_OFF_P1S1 0x10// clock off for PWM1 / SPI1 99 | #define bSLP_OFF_SPI0 0x08// clock off for SPI0 100 | #define bSLP_OFF_TMR3 0x04// clock off for timer3 101 | #define bSLP_OFF_LED 0x02// clock off for LED 102 | #define bSLP_OFF_XRAM 0x01// clock off for xRAM 103 | SFR_(WAKE_CTRL,0xEB); // wake-up control, Write@SafeMode 104 | #define bWAK_BY_USB 0x80// enable wake-up by USB event 105 | #define bWAK_RXD1_LO 0x40// enable wake-up by RXD1 low level 106 | #define bWAK_P1_5_LO 0x20// enable wake-up by pin P1.5 low level 107 | #define bWAK_P1_4_LO 0x10// enable wake-up by pin P1.4 low level 108 | #define bWAK_P0_3_LO 0x08// enable wake-up by pin P0.3 low level 109 | #define bWAK_CAP3_LO 0x04// enable wake-up by CAP3 low level 110 | #define bWAK_P3_2E_3L 0x02// enable wake-up by pin P3.2 (INT0) edge or pin P3.3 (INT1) low level 111 | #define bWAK_RXD0_LO 0x01// enable wake-up by RXD0 low level 112 | SFR_(RESET_KEEP,0xFE); // value keeper during reset 113 | SFR_(WDOG_COUNT,0xFF); // watch-dog count, count by clock frequency Fsys/262144 114 | 115 | /* Interrupt Registers */ 116 | SFR_(IE,0xA8); // interrupt enable 117 | SBIT_(EA,0xA8,7); // enable global interrupts: 0=disable, 1=enable if E_DIS=0 118 | SBIT_(E_DIS,0xA8,6); // disable global interrupts, intend to inhibit interrupt during some flash-ROM operation: 0=enable if EA=1, 1=disable 119 | SBIT_(ET2,0xA8,5); // enable timer2 interrupt 120 | SBIT_(ES,0xA8,4); // enable UART0 interrupt 121 | SBIT_(ET1,0xA8,3); // enable timer1 interrupt 122 | SBIT_(EX1,0xA8,2); // enable external interrupt INT1 123 | SBIT_(ET0,0xA8,1); // enable timer0 interrupt 124 | SBIT_(EX0,0xA8,0); // enable external interrupt INT0 or LED interrupt 125 | SFR_(IP,0xB8); // interrupt priority and current priority 126 | SBIT_(PH_FLAG,0xB8,7); // ReadOnly: high level priority action flag 127 | SBIT_(PL_FLAG,0xB8,6); // ReadOnly: low level priority action flag0xA8// PH_FLAG & PL_FLAG: current interrupt priority 128 | SBIT_(PT2,0xB8,5); // timer2 interrupt priority level 129 | SBIT_(PS ,0xB8,4); // UART0 interrupt priority level 130 | SBIT_(PT1,0xB8,3); // timer1 interrupt priority level 131 | SBIT_(PX1,0xB8,2); // external interrupt INT1 priority level 132 | SBIT_(PT0,0xB8,1); // timer0 interrupt priority level 133 | SBIT_(PX0,0xB8,0); // external interrupt INT0 priority level 134 | // 00 - no interrupt now 135 | // 01 - low level priority interrupt action now 136 | // 10 - high level priority interrupt action now 137 | // 11 - unknown error 138 | SFR_(IE_EX,0xE8); // extend interrupt enable 139 | SBIT_(IE_WDOG ,0xE8,7); // enable watch-dog timer interrupt 140 | SBIT_(IE_GPIO ,0xE8,6); // enable GPIO input interrupt 141 | SBIT_(IE_PWM1 ,0xE8,5); // enable PWM1 interrupt 142 | SBIT_(IE_UART1,0xE8,4); // enable UART1 interrupt 143 | SBIT_(IE_ADC ,0xE8,3); // enable ADC interrupt 144 | SBIT_(IE_USB ,0xE8,2); // enable USB interrupt 145 | SBIT_(IE_TMR3 ,0xE8,1); // enable timer3 interrupt 146 | SBIT_(IE_SPI0 ,0xE8,0); // enable SPI0 interrupt 147 | SFR_(IP_EX,0xE9); // extend interrupt priority 148 | #define bIP_LEVEL 0x80 // ReadOnly: current interrupt nested level: 0=no interrupt or two levels, 1=one level 149 | #define bIP_GPIO 0x40 // GPIO input interrupt priority level 150 | #define bIP_PWM1 0x20 // PWM1 interrupt priority level 151 | #define bIP_UART1 0x10 // UART1 interrupt priority level 152 | #define bIP_ADC 0x08 // ADC interrupt priority level 153 | #define bIP_USB 0x04 // USB interrupt priority level 154 | #define bIP_TMR3 0x02 // timer3 interrupt priority level 155 | #define bIP_SPI0 0x01 // SPI0 interrupt priority level 156 | SFR_(GPIO_IE,0xCF); // GPIO interrupt enable 157 | #define bIE_IO_EDGE 0x80 // enable GPIO edge interrupt: 0=low/high level, 1=falling/rising edge 158 | #define bIE_RXD1_LO 0x40 // enable interrupt by RXD1 low level / falling edge 159 | #define bIE_P5_5_HI 0x20 // enable interrupt by pin P5.5 high level / rising edge 160 | #define bIE_P1_4_LO 0x10 // enable interrupt by pin P1.4 low level / falling edge 161 | #define bIE_P0_3_LO 0x08 // enable interrupt by pin P0.3 low level / falling edge 162 | #define bIE_P5_7_HI 0x04 // enable interrupt by pin P5.7 (RST) high level / rising edge 163 | #define bIE_P4_1_LO 0x02 // enable interrupt by pin P4.1 low level / falling edge 164 | #define bIE_RXD0_LO 0x01 // enable interrupt by RXD0 low level / falling edge 165 | 166 | /* FlashROM and Data-Flash Registers */ 167 | #ifndef __UC__ 168 | SFR16_(ROM_ADDR,0x84); // address for flash-ROM, little-endian 169 | SFR16_(ROM_DATA,0x8E); // data for flash-ROM writing, little-endian 170 | #endif 171 | SFR_(ROM_ADDR_L,0x84); // address low byte for flash-ROM 172 | SFR_(ROM_ADDR_H,0x85); // address high byte for flash-ROM 173 | SFR_(ROM_DATA_L,0x8E); // data low byte for flash-ROM writing 174 | SFR_(ROM_DATA_H,0x8F); // data high byte for flash-ROM writing 175 | SFR_(ROM_CTRL ,0x86); // WriteOnly: flash-ROM control 176 | SFR_(ROM_STATUS,0x86); // ReadOnly: flash-ROM status 177 | #define ROM_CMD_PROG 0x9A // WriteOnly: flash-ROM word program operation command, for changing some ROM bit of a word from 1 to 0 178 | #define ROM_CMD_ERASE 0xA6 // WriteOnly: flash-ROM sector erase operation command, for changing all ROM bit of 1KBytes from 0 to 1 179 | #define bROM_ADDR_OK 0x40 // ReadOnly: flash-ROM operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid 180 | #define bROM_CMD_ERR 0x02 // ReadOnly: flash-ROM operation command error flag: 0=command accepted, 1=unknown command 181 | #define bROM_CMD_TOUT 0x01 // ReadOnly: flash-ROM operation result: 0=success, 1=operation time out 182 | 183 | /* Port Registers */ 184 | SFR_(P0,0x80); // port 0 input & output 185 | SBIT_(P0_7,0x80,7); // generic port bits 186 | SBIT_(P0_6,0x80,6); 187 | SBIT_(P0_5,0x80,5); 188 | SBIT_(P0_4,0x80,4); 189 | SBIT_(P0_3,0x80,3); 190 | SBIT_(P0_2,0x80,2); 191 | SBIT_(P0_1,0x80,1); 192 | SBIT_(P0_0,0x80,0); 193 | 194 | SBIT_(UDCD,0x80,7); // DCD input for UART1 195 | SBIT_(URI ,0x80,6); // RI input for UART1 196 | SBIT_(UDSR,0x80,5); // DSR input for UART1 197 | SBIT_(UCTS,0x80,4); // CTS input for UART1 198 | SBIT_(TXD_,0x80,3); // alternate pin for TXD of UART0 199 | SBIT_(RXD_,0x80,2); // alternate pin for RXD of UART0 200 | SBIT_(URTS,0x80,1); // RTS output for UART1 201 | SBIT_(UDTR,0x80,0); // DTR output for UART1 202 | SFR_(P0_DIR,0xC4); // port 0 direction 203 | #define bUDCD 0x80 // DCD input for UART1 204 | #define bURI 0x40 // RI input for UART1 205 | #define bUDSR 0x20 // DSR input for UART1 206 | #define bUCTS 0x10 // CTS input for UART1 207 | #define bTXD_ 0x08 // alternate pin for TXD of UART0 208 | #define bRXD_ 0x04 // alternate pin for RXD of UART0 209 | #define bURTS 0x02 // RTS output for UART1 210 | #define bUDTR 0x01 // DTR output for UART1 211 | SFR_(P0_PU,0xC5); // port 0 pullup enable 212 | SFR_(P1 ,0x90); // port 1 input & output, not 5VT 213 | SBIT_(P1_0,0x90,0); // generic port bits 214 | SBIT_(P1_1,0x90,1); 215 | SBIT_(P1_2,0x90,2); 216 | SBIT_(P1_3,0x90,3); 217 | SBIT_(P1_4,0x90,4); 218 | SBIT_(P1_5,0x90,5); 219 | SBIT_(P1_6,0x90,6); 220 | SBIT_(P1_7,0x90,7); 221 | 222 | SBIT_(AIN7,0x90,7); // AIN7 for ADC, not 5VT 223 | SBIT_(AIN6,0x90,6); // AIN6 for ADC, not 5VT 224 | SBIT_(AIN5,0x90,5); // AIN5 for ADC, not 5VT 225 | SBIT_(AIN4,0x90,4); // AIN4 for ADC, not 5VT 226 | SBIT_(AIN3,0x90,3); // AIN3 for ADC, not 5VT 227 | SBIT_(AIN2,0x90,2); // AIN2 for ADC, not 5VT 228 | SBIT_(AIN1,0x90,1); // AIN1 for ADC, not 5VT 229 | SBIT_(AIN0,0x90,0); // AIN0 for ADC, not 5VT 230 | 231 | SBIT_(SCK ,0x90,7); // serial clock for SPI0, not 5VT 232 | SBIT_(MISO,0x90,6); // master serial data input or slave serial data output for SPI0, not 5VT 233 | SBIT_(MOSI,0x90,5); // master serial data output or slave serial data input for SPI0, not 5VT 234 | SBIT_(SCS ,0x90,4); // slave chip-selection input for SPI0, not 5VT 235 | SBIT_(PWM3,0x90,2); // PWM output for timer3, not 5VT 236 | SBIT_(CAP3,0x90,2); // capture input for timer3, not 5VT 237 | SBIT_(T2EX,0x90,1); // external trigger input for timer2 reload & capture, not 5VT 238 | SBIT_(CAP2,0x90,1); // capture2 input for timer2, not 5VT 239 | SBIT_(T2 ,0x90,0); // external count input, not 5VT 240 | SBIT_(CAP1,0x90,0); // capture1 input for timer2, not 5VT 241 | SFR_(P1_IE,0xB9); // port 1 input enable 242 | #define bSCK 0x80 // serial clock for SPI0 243 | #define bMISO 0x40 // master serial data input or slave serial data output for SPI0 244 | #define bMOSI 0x20 // master serial data output or slave serial data input for SPI0 245 | #define bSCS 0x10 // slave chip-selection input for SPI0 246 | #define bPWM3 0x04 // PWM output for timer3 247 | #define bCAP3 0x04 // capture input for timer3 248 | #define bT2EX 0x02 // external trigger input for timer2 reload & capture 249 | #define bCAP2 0x02 // capture2 input for timer2 250 | #define bT2 0x01 // external count input or clock output for timer2 251 | #define bCAP1 0x01 // capture1 input for timer2 252 | SFR_(P1_DIR,0xBA); // port 1 direction 253 | SFR_(P1_PU ,0xBB); // port 1 pullup enable 254 | SFR_(P2 ,0xA0); // port 2 input & output 255 | SBIT_(P2_0,0xA0,0); // generic port bits 256 | SBIT_(P2_1,0xA0,1); 257 | SBIT_(P2_2,0xA0,2); 258 | SBIT_(P2_3,0xA0,3); 259 | SBIT_(P2_4,0xA0,4); 260 | SBIT_(P2_5,0xA0,5); 261 | SBIT_(P2_6,0xA0,6); 262 | SBIT_(P2_7,0xA0,7); 263 | 264 | SBIT_(TXD1 ,0xA0,7); // TXD output for UART1 265 | SBIT_(DA7 ,0xA0,7); // address 7 output for direct low address mode 266 | SBIT_(RXD1 ,0xA0,6); // RXD input for UART1 267 | SBIT_(TNOW ,0xA0,5); // tx now output for UART1, indicate transmitting 268 | SBIT_(PWM2 ,0xA0,5); // second PWM output for PWM1 269 | SBIT_(T2EX_,0xA0,5); // alternate pin for T2EX 270 | SBIT_(CAP2_,0xA0,5); // alternate pin for CAP2 271 | SBIT_(PWM1 ,0xA0,4); // PWM output for PWM1 272 | SBIT_(SCK1 ,0xA0,3); // serial clock output for SPI1 273 | SBIT_(MISO1,0xA0,2); // master serial data input for SPI1 274 | SBIT_(MOSI1,0xA0,1); // master serial data output for SPI1 275 | SFR_(P2_DIR,0xBC); // port 2 direction 276 | #define bTXD1 0x80 // TXD output for UART1 277 | #define bDA7 0x80 // address 7 output for direct low address mode 278 | #define bRXD1 0x40 // RXD input for UART1 279 | #define bTNOW 0x20 // tx now output for UART1, indicate transmitting 280 | #define bPWM2 0x20 // second PWM output for PWM1 281 | #define bT2EX_ 0x20 // alternate pin for T2EX 282 | #define bCAP2_ 0x20 // alternate pin for CAP2 283 | #define bPWM1 0x10 // PWM output for PWM1 284 | #define bSCK1 0x08 // serial clock output for SPI1 285 | #define bMISO1 0x04 // master serial data input for SPI1 286 | #define bMOSI1 0x02 // master serial data output for SPI1 287 | SFR_(P2_PU,0xBD); // port 2 pullup enable 288 | SFR_(P3 ,0xB0); // port 3 input & output 289 | SBIT_(P3_0,0xB0,0); 290 | SBIT_(P3_1,0xB0,1); 291 | SBIT_(P3_2,0xB0,2); 292 | SBIT_(P3_3,0xB0,3); 293 | SBIT_(P3_4,0xB0,4); 294 | SBIT_(P3_5,0xB0,5); 295 | SBIT_(P3_6,0xB0,6); 296 | SBIT_(P3_7,0xB0,7); 297 | 298 | SBIT_(RD ,0xB0,7); // xdata or xBUS read strobe output 299 | SBIT_(WR ,0xB0,6); // xdata or xBUS write strobe output 300 | SBIT_(DA6 ,0xB0,5); // address 6 output for direct low address mode 301 | SBIT_(T1 ,0xB0,5); // external count input for timer1 302 | SBIT_(LEDC,0xB0,4); // LEDC clock output for LED 303 | SBIT_(XCS0,0xB0,4); // xBUS chip-selection 0# output, for address range 0x4000~0x7FFF 304 | SBIT_(T0 ,0xB0,4); // external count input for timer0 305 | SBIT_(LED1,0xB0,3); // LED1 data output 306 | SBIT_(INT1,0xB0,3); // external interrupt 1 input 307 | SBIT_(LED0,0xB0,2); // LED0 data output 308 | SBIT_(INT0,0xB0,2); // external interrupt 0 input 309 | SBIT_(TXD ,0xB0,1); // TXD output for UART0 310 | SBIT_(RXD ,0xB0,0); // RXD input for UART0 311 | SFR_(P3_DIR,0xBE); // port 3 direction 312 | #define bRD 0x80 // xdata or xBUS read strobe output 313 | #define bWR 0x40 // xdata or xBUS write strobe output 314 | #define bDA6 0x20 // address 6 output for direct low address mode 315 | #define bT1 0x20 // external count input for timer1 316 | #define bLEDC 0x10 // LEDC clock output for LED 317 | #define bXCS0 0x10 // xBUS chip-selection 0# output, for address range 0x4000~0x7FFF 318 | #define bT0 0x10 // external count input for timer0 319 | #define bLED1 0x08 // LED1 data output 320 | #define bINT1 0x08 // external interrupt 1 input 321 | #define bLED0 0x04 // LED0 data output 322 | #define bINT0 0x04 // external interrupt 0 input 323 | #define bTXD 0x02 // TXD output for UART0 324 | #define bRXD 0x01 // RXD input for UART0 325 | SFR_(P3_PU ,0xBF); // port 3 pullup enable 326 | SFR_(P4_OUT,0xC0); // port 4 output 327 | SBIT_(P4_0,0xC0,0); 328 | SBIT_(P4_1,0xC0,1); 329 | SBIT_(P4_2,0xC0,2); 330 | SBIT_(P4_3,0xC0,3); 331 | SBIT_(P4_4,0xC0,4); 332 | SBIT_(P4_5,0xC0,5); 333 | SBIT_(P4_6,0xC0,6); 334 | SBIT_(P4_7,0xC0,7); 335 | 336 | SBIT_(SCK_ ,0xC0,7); // alternate pin for SCK 337 | SBIT_(SCS_ ,0xC0,6); // alternate pin for SCS 338 | SBIT_(PWM2_,0xC0,5); // alternate pin for PWM2 339 | SBIT_(LED3 ,0xC0,4); // LED3 data output 340 | SBIT_(TNOW_,0xC0,4); // alternate pin for TNOW 341 | SBIT_(TXD1_,0xC0,4); // alternate pin for TXD1 342 | SBIT_(PWM1_,0xC0,3); // alternate pin for PWM1 343 | SBIT_(PWM3_,0xC0,2); // alternate pin for PWM3 344 | SBIT_(CAP3_,0xC0,2); // alternate pin for CAP3 345 | SBIT_(LED2 ,0xC0,0); // LED2 data output 346 | SBIT_(RXD1_,0xC0,0); // alternate pin for RXD1 347 | SFR_(P4_IN,0xC1); // ReadOnly: port 4 input 348 | #define bSCK_ 0x80 // alternate pin for SCK, not 5VT 349 | #define bSCS_ 0x40 // alternate pin for SCS, not 5VT 350 | #define bPWM2_ 0x20 // alternate pin for PWM2 351 | #define bLED3 0x10 // LED3 data output 352 | #define bTNOW_ 0x10 // alternate pin for TNOW 353 | #define bTXD1_ 0x10 // alternate pin for TXD1 354 | #define bPWM1_ 0x08 // alternate pin for PWM1 355 | #define bPWM3_ 0x04 // alternate pin for PWM3 356 | #define bCAP3_ 0x04 // alternate pin for CAP3 357 | #define bLED2 0x01 // LED2 data output 358 | #define bRXD1_ 0x01 // alternate pin for RXD1 359 | SFR_(P4_DIR,0xC2); // port 4 direction 360 | SFR_(P4_PU ,0xC3); // port 4 pullup enable 361 | SFR_(P5_IN ,0xC7); // ReadOnly: port 5 input 362 | #define bRST 0x80 // ReadOnly: pin RST input, not 5VT 363 | #define bIO_INT_ACT 0x40 // ReadOnly: GPIO interrupt request action status 364 | #define bHP 0x20 // ReadOnly: pin HP input 365 | #define bHM 0x10 // ReadOnly: pin HM input 366 | #define bDP 0x02 // ReadOnly: pin DP input 367 | #define bDM 0x01 // ReadOnly: pin DM input 368 | SFR_(P4_CFG,0xC7); // port 4 config 369 | #define bSPI0_PIN_X 0x08 // SPI0 SCS/SCK alternate pin enable: 0=SCS/SCK on P1.4/P1.7, 1=SCS/SCK on P4.6/P4.7 370 | #define bP4_DRV 0x04 // P4 driving capability: 0=5mA, 1=20mA 371 | SFR_(PORT_CFG,0xC6); // port 0/1/2/3 config 372 | #define bP3_DRV 0x80 // P3 driving capability: 0=5mA, 1=20mA 373 | #define bP2_DRV 0x40 // P2 driving capability: 0=5mA, 1=20mA 374 | #define bP1_DRV 0x20 // P1 driving capability: 0=5mA, 1=10mA 375 | #define bP0_DRV 0x10 // P0 driving capability: 0=5mA, 1=20mA 376 | #define bP3_OC 0x08 // P3 open-drain output enable: 0=push-pull output, 1=open-drain output 377 | #define bP2_OC 0x04 // P2 open-drain output enable: 0=push-pull output, 1=open-drain output 378 | #define bP1_OC 0x02 // P1 open-drain output enable: 0=push-pull output, 1=open-drain output 379 | #define bP0_OC 0x01 // P0 open-drain output enable: 0=push-pull output, 1=open-drain output 380 | // bPn_OC & Pn_DIR & Pn_PU: 381 | // pin input & output configuration for Pn (n=0/1/2/3) 382 | // 0 0 0: input only, without pullup resistance 383 | // 0 0 1: input only, with pullup resistance 384 | // 0 1 x: push-pull output, strong driving high level and low level 385 | // 1 0 0: open-drain output without pullup, support input 386 | // 1 1 0: open-drain output without pullup, support input, just driving high level strongly for 2 clocks if turning output level from low to high 387 | // 1 0 1: quasi-bidirectional (simulated 8051 mode), open-drain output with pullup resistance 388 | // 1 1 1: quasi-bidirectional (standard 8051 mode), open-drain output with pullup resistance, just driving high level strongly for 2 clocks if turning output level from low to high 389 | SFR_(PIN_FUNC,0xCE); // pin function selection 390 | #define bPWM1_PIN_X 0x80 // PWM1/PWM2 alternate pin enable: 0=PWM1/PWM2 on P2.4/P2.5, 1=PWM1/PWM2 on P4.3/P4.5 391 | #define bTMR3_PIN_X 0x40 // PWM3/CAP3 alternate pin enable: 0=PWM3/CAP3 on P1.2, 1=PWM3/CAP3 on P4.2 392 | #define bT2EX_PIN_X 0x20 // T2EX/CAP2 alternate pin enable: 0=T2EX/CAP2 on P1.1, 1=T2EX/CAP2 on P2.5 393 | #define bUART0_PIN_X 0x10 // UART0 alternate pin enable: 0=RXD0/TXD0 on P3.0/P3.1, 1=RXD0/TXD0 on P0.2/P0.3 394 | #define bXBUS_EN 0x08 // xBUS function enable: 0=disable, 1=enable port 0 used as data bus and P3.6/P3.7 used as bus writing/reading strobe during accessing xBUS 395 | #define bXBUS_CS_OE 0x04 // xBUS chip-selection output enable: 0=disable output, 396 | // 1=output CS0 (chip-selection 0#, low action) at P3.4, output inversion of address_15 (be equal to CS1, low action) at P3.3 if ALE disabled 397 | #define bXBUS_AH_OE 0x02 // xBUS high address output enable: 0=disable output, 1=output address_8~15 at P2.0~P2.7 during accessing xBUS by MOVX_@DPTR instruction 398 | #define bXBUS_AL_OE 0x01 // xBUS low address output enable: 0=multiplex low address and data bus during accessing xBUS, 1=output address_0~7 at P4.0~P4.5 & P3.5 & P2.7 directly 399 | SFR_(XBUS_AUX,0xA2); // xBUS auxiliary setting 400 | #define bUART0_TX 0x80 // ReadOnly: indicate UART0 transmittal status 401 | #define bUART0_RX 0x40 // ReadOnly: indicate UART0 receiving status 402 | #define bSAFE_MOD_ACT 0x20 // ReadOnly: safe mode action status 403 | #define bALE_CLK_EN 0x10 // enable ALE output 1/12 Fsys clock during non xBUS operation 404 | #define GF2 0x08 // general purpose flag bit 2 405 | #define bDPTR_AUTO_INC 0x04 // enable DPTR auto increase if finished MOVX_@DPTR instruction 406 | #define DPS 0x01 // dual DPTR selection: 0=DPTR0 selected, 1=DPTR1 selected 407 | SFR_(XBUS_SPEED,0xFD); // xBUS speed config 408 | #define bXBUS1_SETUP 0x80 // xBUS chip-selection 1# setup time: 0=2 clocks, 1=3 clocks 409 | #define bXBUS1_HOLD 0x40 // xBUS chip-selection 1# hold time: 0=1 clocks, 1=2 clocks 410 | #define bXBUS1_WIDTH1 0x20 // xBUS chip-selection 1# access pulse width high bit 411 | #define bXBUS1_WIDTH0 0x10 // xBUS chip-selection 1# access pulse width low bit 412 | #define MASK_XBUS1_WIDTH 0x30 // bit mask of xBUS chip-selection 1# access pulse width 413 | #define bXBUS0_SETUP 0x08 // xBUS chip-selection 0# setup time: 0=2 clocks, 1=3 clocks 414 | #define bXBUS0_HOLD 0x04 // xBUS chip-selection 0# hold time: 0=1 clocks, 1=2 clocks 415 | #define bXBUS0_WIDTH1 0x02 // xBUS chip-selection 0# access pulse width high bit 416 | #define bXBUS0_WIDTH0 0x01 // xBUS chip-selection 0# access pulse width low bit 417 | #define MASK_XBUS0_WIDTH 0x03 // bit mask of xBUS chip-selection 0# access pulse width 418 | // bXBUSn_WIDTH1 & bXBUSn_WIDTH0: 419 | // read or write pulse width for xBUS chip-selection n# peripheral 420 | // 00: 2 clocks 421 | // 01: 4 clocks 422 | // 10: 8 clocks 423 | // 11: 16 clocks 424 | 425 | /* Timer0/1 Registers */ 426 | SFR_(TCON,0x88); // timer 0/1 control and external interrupt control 427 | SBIT_(TF1,0x88,7); // timer1 overflow & interrupt flag, auto cleared when MCU enter interrupt routine 428 | SBIT_(TR1,0x88,6); // timer1 run enable 429 | SBIT_(TF0,0x88,5); // timer0 overflow & interrupt flag, auto cleared when MCU enter interrupt routine 430 | SBIT_(TR0,0x88,4); // timer0 run enable 431 | SBIT_(IE1,0x88,3); // INT1 interrupt flag, auto cleared when MCU enter interrupt routine 432 | SBIT_(IT1,0x88,2); // INT1 interrupt type: 0=low level action, 1=falling edge action 433 | SBIT_(IE0,0x88,1); // INT0 interrupt flag, auto cleared when MCU enter interrupt routine 434 | SBIT_(IT0,0x88,0); // INT0 interrupt type: 0=low level action, 1=falling edge action 435 | SFR_(TMOD,0x89); // timer 0/1 mode 436 | #define bT1_GATE 0x80 // gate control of timer1: 0=timer1 run enable while TR1=1, 1=timer1 run enable while P3.3 (INT1) pin is high and TR1=1 437 | #define bT1_CT 0x40 // counter or timer mode selection for timer1: 0=timer, use internal clock, 1=counter, use P3.5 (T1) pin falling edge as clock 438 | #define bT1_M1 0x20 // timer1 mode high bit 439 | #define bT1_M0 0x10 // timer1 mode low bit 440 | #define MASK_T1_MOD 0x30 // bit mask of timer1 mode 441 | #define bT0_GATE 0x08 // gate control of timer0: 0=timer0 run enable while TR0=1, 1=timer0 run enable while P3.2 (INT0) pin is high and TR0=1 442 | #define bT0_CT 0x04 // counter or timer mode selection for timer0: 0=timer, use internal clock, 1=counter, use P3.4 (T0) pin falling edge as clock 443 | #define bT0_M1 0x02 // timer0 mode high bit 444 | #define bT0_M0 0x01 // timer0 mode low bit 445 | #define MASK_T0_MOD 0x03 // bit mask of timer0 mode 446 | // bT1_M1 & bT1_M0: 447 | // timer1 mode 448 | // 00: mode 0, 13-bit timer or counter by cascaded TH1 and lower 5 bits of TL1, the upper 3 bits of TL1 are ignored 449 | // 01: mode 1, 16-bit timer or counter by cascaded TH1 and TL1 450 | // 10: mode 2, TL1 operates as 8-bit timer or counter, and TH1 provide initial value for TL1 auto-reload 451 | // 11: mode 3, stop timer1 452 | // bT0_M1 & bT0_M0: 453 | // timer0 mode 454 | // 00: mode 0, 13-bit timer or counter by cascaded TH0 and lower 5 bits of TL0, the upper 3 bits of TL0 are ignored 455 | // 01: mode 1, 16-bit timer or counter by cascaded TH0 and TL0 456 | // 10: mode 2, TL0 operates as 8-bit timer or counter, and TH0 provide initial value for TL0 auto-reload 457 | // 11: mode 3, TL0 is 8-bit timer or counter controlled by standard timer0 bits, TH0 is 8-bit timer using TF1 and controlled by TR1, timer1 run enable if it is not mode 3 458 | SFR_(TL0,0x8A); // low byte of timer 0 count 459 | SFR_(TL1,0x8B); // low byte of timer 1 count 460 | SFR_(TH0,0x8C); // high byte of timer 0 count 461 | SFR_(TH1,0x8D); // high byte of timer 1 count 462 | 463 | /* UART0 Registers */ 464 | SFR_(SCON,0x98); // UART0 control (serial port control) 465 | SBIT_(SM0,0x98,7); // UART0 mode bit0, selection data bit: 0=8 bits data, 1=9 bits data 466 | SBIT_(SM1,0x98,6); // UART0 mode bit1, selection baud rate: 0=fixed, 1=variable 467 | SBIT_(SM2,0x98,5); // enable multi-device communication in mode 2/3 468 | SBIT_(REN,0x98,4); // enable UART0 receiving 469 | SBIT_(TB8,0x98,3); // the 9th transmitted data bit in mode 2/3 470 | SBIT_(RB8,0x98,2); // 9th data bit received in mode 2/3, or stop bit received for mode 1 471 | SBIT_(TI ,0x98,1); // transmit interrupt flag, set by hardware after completion of a serial transmittal, need software clear 472 | SBIT_(RI ,0x98,0); // receive interrupt flag, set by hardware after completion of a serial receiving, need software clear 473 | #define MASK_UART0_MOD 0xE0 // bit mask of UART0 mode 474 | // SM0 & SM1: 475 | // UART0 mode 476 | // 00 - mode 0, shift Register, baud rate fixed at: Fsys/12 477 | // 01 - mode 1, 8-bit UART, baud rate = variable by timer1 or timer2 overflow rate 478 | // 10 - mode 2, 9-bit UART, baud rate fixed at: Fsys/128@SMOD=0, Fsys/32@SMOD=1 479 | // 11 - mode 3, 9-bit UART, baud rate = variable by timer1 or timer2 overflow rate 480 | 481 | SFR_(SBUF,0x99); // UART0 data buffer: reading for receiving, writing for transmittal 482 | 483 | /* Timer2/Capture2 Registers */ 484 | SFR_(T2CON,0xC8); // timer 2 control 485 | SBIT_(TF2 ,0xC8,7); // timer2 overflow & interrupt flag, need software clear, the flag will not be set when either RCLK=1 or TCLK=1 486 | SBIT_(CAP1F,0xC8,7); // timer2 capture 1 interrupt flag, set by T2 edge trigger if bT2_CAP1_EN=1, need software clear 487 | SBIT_(EXF2 ,0xC8,6); // timer2 external flag, set by T2EX edge trigger if EXEN2=1, need software clear 488 | SBIT_(RCLK ,0xC8,5); // selection UART0 receiving clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse 489 | SBIT_(TCLK ,0xC8,4); // selection UART0 transmittal clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse 490 | SBIT_(EXEN2,0xC8,3); // enable T2EX trigger function: 0=ignore T2EX, 1=trigger reload or capture by T2EX edge 491 | SBIT_(TR2 ,0xC8,2); // timer2 run enable 492 | SBIT_(C_T2 ,0xC8,1); // timer2 clock source selection: 0=timer base internal clock, 1=external edge counter base T2 falling edge 493 | SBIT_(CP_RL,0xC8,0); // timer2 function selection (force 0 if RCLK=1 or TCLK=1): 0=timer and auto reload if count overflow or T2EX edge, 1=capture by T2EX edge 494 | SFR_(T2MOD,0xC9); // timer 2 mode and timer 0/1/2 clock mode 495 | #define bTMR_CLK 0x80 // fastest internal clock mode for timer 0/1/2 under faster clock mode: 0=use divided clock, 1=use original Fsys as clock without dividing 496 | #define bT2_CLK 0x40 // timer2 internal clock frequency selection: 0=standard clock, Fsys/12 for timer mode, Fsys/4 for UART0 clock mode, 497 | // 1=faster clock, Fsys/4 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for timer mode, Fsys/2 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for UART0 clock mode 498 | #define bT1_CLK 0x20 // timer1 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1 499 | #define bT0_CLK 0x10 // timer0 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1 500 | #define bT2_CAP_M1 0x08 // timer2 capture mode high bit 501 | #define bT2_CAP_M0 0x04 // timer2 capture mode low bit 502 | #define T2OE 0x02 // enable timer2 generated clock output: 0=disable output, 1=enable clock output at T2 pin, frequency = TF2/2 503 | #define bT2_CAP1_EN 0x01 // enable T2 trigger function for capture 1 of timer2 if RCLK=0 & TCLK=0 & CP_RL2=1 & C_T2=0 & T2OE=0 504 | // bT2_CAP_M1 & bT2_CAP_M0: 505 | //timer2 capture point selection 506 | // x0: from falling edge to falling edge 507 | // 01: from any edge to any edge (level changing) 508 | // 11: from rising edge to rising edge 509 | 510 | SFR_(RCAP2L,0xCA); // low byte of reload & capture value 511 | SFR_(RCAP2H,0xCB); // high byte of reload & capture value 512 | #ifndef __UC__ 513 | SFR16_(RCAP2 ,0xCA); // reload & capture value, little-endian 514 | SFR16_(T2COUNT,0xCC); // counter, little-endian 515 | SFR16_(T2CAP1 ,0xCC); // ReadOnly: capture 1 value for timer2 516 | #endif 517 | SFR_(TL2 ,0xCC); // low byte of timer 2 count 518 | SFR_(T2CAP1L,0xCC); // ReadOnly: capture 1 value low byte for timer2 519 | SFR_(TH2 ,0xCD); // high byte of timer 2 count 520 | SFR_(T2CAP1H,0xCD); // ReadOnly: capture 1 value high byte for timer2 521 | 522 | 523 | /* Timer3/Capture3/PWM3 Registers */ 524 | SFR_(T3_SETUP,0xA3); // timer 3 setup 525 | #define bT3_IE_END 0x80 // enable interrupt for capture mode count timeout (exceed end value) or PWM mode cycle end 526 | #define bT3_IE_FIFO_OV 0x40 // enable interrupt for FIFO overflow 527 | #define bT3_IE_FIFO_REQ 0x20 // enable interrupt for capture mode FIFO >=4 or PWM mode FIFO <=3 528 | #define bT3_IE_ACT 0x10 // enable interrupt for capture mode input action or PWM mode trigger 529 | #define bT3_CAP_IN 0x04 // ReadOnly: current capture input level after noise filtrating 530 | #define bT3_CAP_CLK 0x02 // force no minimum pulse width limit for capture input if T3_CK_SE=1 531 | #define bT3_EN_CK_SE 0x01 // enable to accessing divisor setting register, else enable to accessing current count register 532 | 533 | SFR_(T3_COUNT_L,0xA4); // ReadOnly: current count low byte 534 | SFR_(T3_COUNT_H,0xA5); // ReadOnly: current count high byte 535 | SFR_(T3_CK_SE_L,0xA4); // clock divisor setting low byte 536 | SFR_(T3_CK_SE_H,0xA5); // clock divisor setting high byte, lower 4 bits valid only 537 | #ifndef __UC__ 538 | SFR16_(T3_COUNT,0xA4); // ReadOnly: current count value, little-endian 539 | SFR16_(T3_CK_SE,0xA4); // clock divisor setting, little-endian, lower 12 bits valid only 540 | SFR16_(T3_END ,0xA6); // end value for count, little-endian 541 | #endif 542 | SFR_(T3_END_L,0xA6); // low byte of end value for count 543 | SFR_(T3_END_H,0xA7); // high byte of end value for count 544 | SFR_(T3_STAT ,0xA9); // timer 3 status 545 | #define bT3_IF_DMA_END 0x80 // interrupt flag for DMA completion, write 1 to clear or write T3_DMA_CN to clear 546 | #define bT3_IF_FIFO_OV 0x40 // interrupt flag for FIFO overflow, write 1 to clear 547 | #define bT3_IF_FIFO_REQ 0x20 // interrupt flag for request FIFO data (capture mode FIFO >=4 or PWM mode FIFO <=3), write 1 to clear 548 | #define bT3_IF_ACT 0x10 // interrupt flag for capture mode input action or PWM mode trigger if bT3_IE_ACT=1, write 1 to clear or accessing FIFO to clear 549 | #define bT3_IF_END 0x10 // interrupt flag for capture mode count timeout (exceed end value) or PWM mode cycle end if bT3_IE_ACT=0, write 1 to clear 550 | #define MASK_T3_FIFO_CNT 0x0F// ReadOnly: bit mask of timer3 FIFO count 551 | SFR_(T3_CTRL,0xAA); // timer 3 control 552 | #define bT3_CAP_M1 0x80 // timer3 capture mode high bit 553 | #define bT3_CAP_M0 0x40 // timer3 capture mode low bit 554 | #define bT3_PWM_POLAR 0x20 // timer3 PWM output polarity: 0=default low and high action, 1=default high and low action 555 | #define bT3_CAP_WIDTH 0x20 // minimum pulse width for timer3 capture: 0=4 divided clocks, 1=1 divided clock 556 | #define bT3_DMA_EN 0x10 // DMA enable and DMA interrupt enable for timer3 557 | #define bT3_OUT_EN 0x08 // timer3 output enable 558 | #define bT3_CNT_EN 0x04 // timer3 count enable 559 | #define bT3_CLR_ALL 0x02 // force clear FIFO and count of timer3 560 | #define bT3_MOD_CAP 0x01 // timer3 mode: 0=timer or PWM, 1=capture 561 | // bT3_CAP_M1 & bT3_CAP_M0: 562 | // timer3 capture point selection 563 | // 00: disable capture 564 | // 01: from any edge to any edge (level changing) 565 | // 10: from falling edge to falling edge 566 | // 11: from rising edge to rising edge 567 | 568 | SFR_(T3_DMA_CN,0xAB); // DMA remainder word count, automatic decreasing after DMA 569 | SFR_(T3_DMA_AL,0xAC); // DMA address low byte, automatic increasing after DMA 570 | SFR_(T3_DMA_AH,0xAD); // DMA address high byte, automatic increasing after DMA 571 | SFR_(T3_FIFO_L,0xAE); // FIFO low byte 572 | SFR_(T3_FIFO_H,0xAF); // FIFO high byte 573 | #ifndef __UC__ 574 | SFR16_(T3_FIFO,0xAE); // FIFO word, little-endian 575 | SFR16_(T3_DMA ,0xAC); // DMA address, must even address, little-endian, automatic increasing after DMA 576 | #endif 577 | /* PWM1/2 Registers */ 578 | SFR_(PWM_DATA2,0x9B); // PWM data for PWM2 579 | SFR_(PWM_DATA ,0x9C); // PWM data for PWM1 580 | SFR_(PWM_CTRL ,0x9D); // PWM 1/2 control 581 | #define bPWM_IE_END 0x80 // enable interrupt for PWM mode cycle end or MFM empty buffer 582 | #define bPWM2_POLAR 0x40 // PWM2 output polarity if bPWM_MOD_MFM=0: 0=default low and high action, 1=default high and low action 583 | #define bMFM_BUF_EMPTY 0x40 // ReadOnly: MFM empty buffer status if bPWM_MOD_MFM=1 584 | #define bPWM_POLAR 0x20 // PWM output polarity: 0=default low and high action, 1=default high and low action 585 | #define bPWM_IF_END 0x10 // interrupt flag for cycle end, write 1 to clear or write PWM_CYCLE or load new data to clear 586 | #define bPWM_OUT_EN 0x08 // PWM1 output enable 587 | #define bPWM2_OUT_EN 0x04 // PWM2 output enable if bPWM_MOD_MFM=0 588 | #define bMFM_BIT_CNT2 0x04 // ReadOnly: MFM encode bit count status if bPWM_MOD_MFM=1: 0=lower 4 bits, 1=upper 4 bits 589 | #define bPWM_CLR_ALL 0x02 // force clear FIFO and count of PWM1/2 590 | #define bPWM_MOD_MFM 0x01 // MFM encode mode for PWM: 0=PWM, 1=MFM encode 591 | SFR_(PWM_CK_SE,0x9E); // clock divisor setting 592 | SFR_(PWM_CYCLE,0x9F); // PWM cycle 593 | 594 | /* SPI0/Master0/Slave Registers */ 595 | SFR_(SPI0_STAT,0xF8); // SPI 0 status 596 | SBIT_(S0_FST_ACT ,0xF8,7); // ReadOnly: indicate first byte received status for SPI0 597 | SBIT_(S0_IF_OV ,0xF8,6); // interrupt flag for slave mode FIFO overflow, direct bit address clear or write 1 to clear 598 | SBIT_(S0_IF_FIRST,0xF8,5); // interrupt flag for first byte received, direct bit address clear or write 1 to clear 599 | SBIT_(S0_IF_BYTE ,0xF8,4); // interrupt flag for a byte data exchanged, direct bit address clear or write 1 to clear or accessing FIFO to clear if bS0_AUTO_IF=1 600 | SBIT_(S0_FREE ,0xF8,3); // ReadOnly: SPI0 free status 601 | SBIT_(S0_T_FIFO ,0xF8,2); // ReadOnly: tx FIFO count for SPI0 602 | SBIT_(S0_R_FIFO1 ,0xF8,1); // ReadOnly: rx FIFO count bit1 for SPI0 603 | SBIT_(S0_R_FIFO0 ,0xF8,0); // ReadOnly: rx FIFO count bit0 for SPI0 604 | #define MASK_S0_RFIFO_CNT 0x03// ReadOnly: bit mask of SPI0 rx FIFO count 605 | SFR_(SPI0_DATA,0xF9); // FIFO data port: reading for receiving, writing for transmittal 606 | SFR_(SPI0_CTRL,0xFA); // SPI 0 control 607 | #define bS0_MISO_OE 0x80 // SPI0 MISO output enable 608 | #define bS0_MOSI_OE 0x40 // SPI0 MOSI output enable 609 | #define bS0_SCK_OE 0x20 // SPI0 SCK output enable 610 | #define bS0_DATA_DIR 0x10 // SPI0 data direction: 0=out(master_write), 1=in(master_read) 611 | #define bS0_MST_CLK 0x08 // SPI0 master clock mode: 0=mode 0 with default low, 1=mode 3 with default high 612 | #define bS0_2_WIRE 0x04 // enable SPI0 two wire mode: 0=3 wire (SCK+MOSI+MISO), 1=2 wire (SCK+MISO) 613 | #define bS0_CLR_ALL 0x02 // force clear FIFO and count of SPI0 614 | #define bS0_AUTO_IF 0x01 // enable FIFO accessing to auto clear S0_IF_BYTE interrupt flag 615 | SFR_(SPI0_CK_SE,0xFB); // clock divisor setting 616 | SFR_(SPI0_S_PRE,0xFB); // preset value for SPI slave 617 | SFR_(SPI0_SETUP,0xFC); // SPI 0 setup 618 | #define bS0_MODE_SLV 0x80 // SPI0 slave mode: 0=master, 1=slave 619 | #define bS0_IE_FIFO_OV 0x40 // enable interrupt for slave mode FIFO overflow 620 | #define bS0_IE_FIRST 0x20 // enable interrupt for first byte received for SPI0 slave mode 621 | #define bS0_IE_BYTE 0x10 // enable interrupt for a byte received 622 | #define bS0_BIT_ORDER 0x08 // SPI0 bit data order: 0=MSB first, 1=LSB first 623 | #define bS0_SLV_SELT 0x02 // ReadOnly: SPI0 slave mode chip selected status: 0=unselected, 1=selected 624 | #define bS0_SLV_PRELOAD 0x01 // ReadOnly: SPI0 slave mode data pre-loading status just after chip-selection 625 | 626 | /* SPI1/Master1 Registers */ 627 | SFR_(SPI1_STAT,0xB4); // SPI 1 status 628 | #define bS1_IF_BYTE 0x10 // interrupt flag for a byte data exchanged, write 1 to clear or accessing FIFO to clear if bS1_AUTO_IF=1 629 | #define bS1_FREE 0x08 // ReadOnly: SPI1 free status 630 | SFR_(SPI1_DATA,0xB5); // data port: reading for receiving, writing for transmittal 631 | SFR_(SPI1_CTRL,0xB6); // SPI 1 control 632 | #define bS1_MISO_OE 0x80 // SPI1 MISO output enable 633 | #define bS1_SCK_OE 0x20 // SPI1 SCK output enable, MOSI output enable if bS1_2_WIRE=0 634 | #define bS1_DATA_DIR 0x10 // SPI1 data direction: 0=out(master_write), 1=in(master_read) 635 | #define bS1_MST_CLK 0x08 // SPI1 master clock mode: 0=mode 0 with default low, 1=mode 3 with default high 636 | #define bS1_2_WIRE 0x04 // enable SPI1 two wire mode: 0=3 wire (SCK+MOSI+MISO), 1=2 wire (SCK+MISO) 637 | #define bS1_CLR_ALL 0x02 // force clear FIFO and count of SPI1 638 | #define bS1_AUTO_IF 0x01 // enable FIFO accessing to auto clear bS1_IF_BYTE interrupt flag 639 | SFR_(SPI1_CK_SE,0xB7); // clock divisor setting 640 | 641 | /* UART1/iRS485 Registers */ 642 | SFR_(SER1_FIFO,0x9A); // UART1 FIFO data port: reading for receiving, writing for transmittal 643 | SFR_(SER1_RBR ,0x9A); // ReadOnly: UART1 receiver buffer 644 | SFR_(SER1_THR ,0x9A); // WriteOnly: UART1 transmitter holding 645 | SFR_(SER1_IER ,0x91); // UART1 interrupt enable 646 | #define bIER_RESET 0x80 // UART1 software reset control, high action, auto clear 647 | #define bIER_EN_MODEM_O 0x40 // enable UART1 modem output signal, DTR connect P0.0, RTS connect P0.1 648 | #define bIER_PIN_MOD1 0x20 // UART1 pin mode high bit 649 | #define bIER_PIN_MOD0 0x10 // UART1 pin mode low bit 650 | #define MASK_U1_PIN_MOD 0x70 // bit mask of UART1 pin mode 651 | // RS485EN & bIER_PIN_MOD1 & bIER_PIN_MOD0: 652 | //UART1 pin mode 653 | // RS485EN = bUH1_DISABLE & ~ ( bXBUS_CS_OE & ~ bXBUS_AL_OE | bALE_CLK_EN ) 654 | // x00: RXD1 connect P4.0, disable TXD1 655 | // 010: RXD1/TXD1 connect P2.6/P2.7 656 | // 001: RXD1/TXD1 connect P4.0/P4.4 657 | // 011: RXD1/TXD1/TNOW connect P2.6/P2.7/P2.5 658 | // 110: RXD1/TXD1 connect iRS485 pins XA/XB 659 | // 101: RXD1/TXD1 connect iRS485 pins XA/XB, TNOW connect P4.4 660 | // 111: RXD1/TXD1 connect iRS485 pins XA/XB, TNOW connect P2.5 661 | #define bIER_MODEM_CHG 0x08 // UART1 interrupt enable for modem status change 662 | #define bIER_LINE_STAT 0x04 // UART1 interrupt enable for receiver line status 663 | #define bIER_THR_EMPTY 0x02 // UART1 interrupt enable for THR empty 664 | #define bIER_RECV_RDY 0x01 // UART1 interrupt enable for receiver data ready 665 | SFR_(SER1_IIR,0x92); // ReadOnly: UART1 interrupt identification 666 | #define MASK_U1_IIR_ID 0xC0 // ReadOnly: bit mask of UART1 IIR, FIFO enabled flag 667 | #define bIIR_INT_FLAG3 0x08 // ReadOnly: UART1 interrupt flag bit 3 668 | #define bIIR_INT_FLAG2 0x04 // ReadOnly: UART1 interrupt flag bit 2 669 | #define bIIR_INT_FLAG1 0x02 // ReadOnly: UART1 interrupt flag bit 1 670 | #define bIIR_INT_FLAG0 0x01 // ReadOnly: UART1 interrupt flag bit 0 671 | #define MASK_U1_IIR_INT 0x0F // ReadOnly: bit mask of UART1 interrupt flag 672 | // bIIR_INT_FLAG3 & bIIR_INT_FLAG2 & bIIR_INT_FLAG1 & bIIR_INT_FLAG0: 673 | // UART1 interrupt flag, list follow: 674 | #define U1_INT_SLV_ADDR 0x0E// UART1 interrupt by slave address match 675 | #define U1_INT_LINE_STAT 0x06// UART1 interrupt by receiver line status 676 | #define U1_INT_RECV_RDY 0x04// UART1 interrupt by receiver data available 677 | #define U1_INT_RECV_TOUT 0x0C// UART1 interrupt by receiver FIFO timeout 678 | #define U1_INT_THR_EMPTY 0x02// UART1 interrupt by THR empty 679 | #define U1_INT_MODEM_CHG 0x00// UART1 interrupt by modem status change 680 | #define U1_INT_NO_INTER 0x01// no UART interrupt is pending 681 | #define bIIR_NO_INT 0x01// UART1 no interrupt flag: 0=interrupt action, 1=no interrupt 682 | SFR_(SER1_FCR,0x92); // WriteOnly: UART1 FIFO control 683 | #define bFCR_FIFO_TRIG1 0x80// UART1 receiver FIFO trigger level high bit 684 | #define bFCR_FIFO_TRIG0 0x40// UART1 receiver FIFO trigger level low bit 685 | #define MASK_U1_FIFO_TRIG 0xC0// bit mask of UART1 receiver FIFO trigger level 686 | #define bFCR_T_FIFO_CLR 0x04// clear UART1 transmitter FIFO, high action, auto clear 687 | #define bFCR_R_FIFO_CLR 0x02// clear UART1 receiver FIFO, high action, auto clear 688 | #define bFCR_FIFO_EN 0x01// UART1 FIFO enable 689 | // bFCR_FIFO_TRIG1 & bFCR_FIFO_TRIG0: 690 | // UART1 receiver FIFO trigger level 691 | // 00: 1 byte 692 | // 01: 2 bytes 693 | // 10: 4 bytes 694 | // 11: 7 bytes 695 | SFR_(SER1_LCR,0x93); // UART1 line control 696 | #define bLCR_DLAB 0x80 // UART1 divisor latch access bit 697 | #define bLCR_BREAK_EN 0x40 // UART1 break control enable 698 | #define bLCR_PAR_MOD1 0x20 // UART1 parity mode high bit 699 | #define bLCR_PAR_MOD0 0x10 // UART1 parity mode low bit 700 | #define MASK_U1_PAR_MOD 0x30 // bit mask of UART1 parity mode 701 | #define U1_PAR_MOD_ODD 0x00 702 | #define U1_PAR_MOD_EVEN 0x10 703 | #define U1_PAR_MOD_MARK 0x20 704 | #define U1_PAR_MOD_SPACE 0x30 705 | #define bLCR_PAR_EN 0x08 // UART1 parity enable 706 | #define bLCR_STOP_BIT 0x04 // UART1 stop bit length: 0=1 bit, 1=2 bits 707 | #define bLCR_WORD_SZ1 0x02 // UART1 word bit length high 708 | #define bLCR_WORD_SZ0 0x01 // UART1 word bit length low 709 | #define MASK_U1_WORD_SZ 0x03 // bit mask of UART1 word bit length 710 | // bLCR_PAR_MOD1 & bLCR_PAR_MOD0: 711 | // UART1 parity mode if bLCR_PAR_EN=1, else ignored 712 | // 00: the 9th bit is odd parity bit 713 | // 01: the 9th bit is even parity bit 714 | // 10: the 9th bit is mark bit 715 | // 11: the 9th bit is space bit 716 | // bLCR_WORD_SZ1 & bLCR_WORD_SZ0: 717 | // UART1 word bit length (exclude parity bit) 718 | // 00: 5 bits 719 | // 01: 6 bits 720 | // 10: 7 bits 721 | // 11: 8 bits 722 | SFR_(SER1_MCR,0x94); // UART1 modem control 723 | #define bMCR_HALF 0x80 // UART1 enable half-duplex mode 724 | #define bMCR_TNOW 0x40 // UART1 enable TNOW output on DTR pin 725 | #define bMCR_AUTO_FLOW 0x20 // UART1 enable autoflow control by CTS & RTS pin 726 | #define bMCR_LOOP 0x10 // UART1 enable local loop back for testing 727 | #define bMCR_OUT2 0x08 // UART1 control OUT2, enable interrupt request output 728 | #define bMCR_OUT1 0x04 // UART1 control OUT1, not real pin 729 | #define bMCR_RTS 0x02 // UART1 control RTS 730 | #define bMCR_DTR 0x01 // UART1 control DTR 731 | SFR_(SER1_LSR,0x95); // ReadOnly: UART1 line status 732 | #define bLSR_ERR_R_FIFO 0x80 // ReadOnly: error in UART1 receiver fifo, read to clear 733 | #define bLSR_T_ALL_EMP 0x40 // ReadOnly: UART1 transmitter all empty status 734 | #define bLSR_T_FIFO_EMP 0x20 // ReadOnly: UART1 transmitter FIFO empty status 735 | #define bLSR_BREAK_ERR 0x10 // ReadOnly: UART1 receiver break error, read to clear 736 | #define bLSR_FRAME_ERR 0x08 // ReadOnly: UART1 receiver frame error, read to clear 737 | #define bLSR_PAR_ERR 0x04 // ReadOnly: UART1 receiver parity error, read to clear 738 | #define bLSR_OVER_ERR 0x02 // ReadOnly: UART1 receiver overrun error, read to clear 739 | #define bLSR_DATA_RDY 0x01 // ReadOnly: UART1 receiver FIFO data ready status 740 | SFR_(SER1_MSR,0x96); // ReadOnly: UART1 modem status 741 | #define bMSR_DCD 0x80 // ReadOnly: UART1 DCD action status 742 | #define bMSR_RI 0x40 // ReadOnly: UART1 RI action status 743 | #define bMSR_DSR 0x20 // ReadOnly: UART1 DSR action status 744 | #define bMSR_CTS 0x10 // ReadOnly: UART1 CTS action status 745 | #define bMSR_DCD_CHG 0x08 // ReadOnly: UART1 DCD changed status, high action, read to clear 746 | #define bMSR_RI_CHG 0x04 // ReadOnly: UART1 RI changed status, high action, read to clear 747 | #define bMSR_DSR_CHG 0x02 // ReadOnly: UART1 DSR changed status, high action, read to clear 748 | #define bMSR_CTS_CHG 0x01 // ReadOnly: UART1 CTS changed status, high action, read to clear 749 | SFR_(SER1_ADDR,0x97); // UART1 slave address for multi-device communication, value 0xFF is disable 750 | SFR_(SER1_DLL,0x9A); // UART1 divisor latch LSB byte if bLCR_DLAB=1 751 | SFR_(SER1_DLM,0x91); // UART1 divisor latch MSB byte if bLCR_DLAB=1 752 | SFR_(SER1_DIV,0x97); // UART1 pre-divisor latch byte if bLCR_DLAB=1 753 | 754 | /* ADC Registers */ 755 | #ifndef __UC__ 756 | SFR16_(ADC_DMA ,0xEC); // DMA address, must even address, little-endian, automatic increasing after DMA 757 | #endif 758 | SFR_(ADC_DMA_AL,0xEC); // DMA address low byte, automatic increasing after DMA 759 | SFR_(ADC_DMA_AH,0xED); // DMA address high byte, automatic increasing after DMA 760 | SFR_(ADC_DMA_CN,0xEE); // DMA remainder word count, automatic decreasing after DMA 761 | SFR_(ADC_CK_SE ,0xEF); // ADC clock divisor setting 762 | #define MASK_ADC_CK_SE 0x7F// bit mask of ADC clock divisor 763 | #define bADC_CHK_CLK_SEL 0x80// AIN7 level check delay clock frequency selection: 0=slow(1x), 1=fast(4x) 764 | SFR_(ADC_STAT,0xF1); // ADC status 765 | #define bADC_IF_DMA_END 0x80// interrupt flag for DMA completion, write 1 to clear or write ADC_DMA_CN to clear 766 | #define bADC_IF_FIFO_OV 0x40// interrupt flag for FIFO overflow, write 1 to clear 767 | #define bADC_IF_AIN7_LOW 0x20// interrupt flag for AIN7 low level, write 1 to clear 768 | #define bADC_IF_ACT 0x10// interrupt flag for a ADC finished, write 1 to clear 769 | #define bADC_AIN7_INT 0x08// ReadOnly: current AIN7 low level delay status 770 | #define bADC_CHANN_ID 0x04// ReadOnly: current channel ID for channel automatic switch mode: 0=AIN0 or AIN6, 1=AIN1 or AIN4 or AIN7 771 | #define bADC_DATA_OK 0x04// ReadOnly: ADC end and data ready flag for channel manual selection mode: 0=data not ready, 1=data ready 772 | #define bADC_FIFO_CNT1 0x02// ReadOnly: ADC FIFO count bit 1 773 | #define bADC_FIFO_CNT0 0x01// ReadOnly: ADC FIFO count bit 0 774 | #define MASK_ADC_FIFO_CNT 0x03// ReadOnly: bit mask of ADC FIFO count 775 | // bADC_FIFO_CNT1 & bADC_FIFO_CNT0: 776 | // ADC FIFO count 777 | // 00: empty FIFO, return current ADC result if reading FIFO 778 | // 01: 1 result in FIFO 779 | // 01: 2 results in FIFO, FIFO full 780 | // 11: unknown error 781 | SFR_(ADC_CTRL,0xF2); // ADC control 782 | #define bADC_SAMPLE 0x80 // automatic or manual sample pulse control, high action 783 | #define bADC_SAMP_WIDTH 0x40 // automatic sample pulse width: 0=1 ADC clock, 1=2 ADC clocks 784 | #define bADC_CHANN_MOD1 0x20 // ADC channel control mode high bit 785 | #define bADC_CHANN_MOD0 0x10 // ADC channel control mode low bit 786 | #define MASK_ADC_CHANN 0x30 // bit mask of ADC channel control mode 787 | #define MASK_ADC_CYCLE 0x0F // bit mask of ADC cycle (ADC clock number): 0=manual sample, others=set cycle number for automatic sample 788 | // bADC_CHANN_MOD1 & bADC_CHANN_MOD0: 789 | // ADC channel control mode 790 | // 00: manual selection by ADC_CHANN bit 791 | // 01: automatic switch between AIN0 and AIN1 792 | // 10: automatic switch between AIN6 and AIN4 793 | // 11: automatic switch between AIN6 and AIN7 794 | SFR_( ADC_CHANN ,0xF3); // ADC channel seletion 795 | #ifndef __UC__ 796 | SFR16_( ADC_FIFO,0xF4); // ReadOnly: FIFO word, little-endian 797 | #endif 798 | SFR_( ADC_FIFO_L,0xF4); // ReadOnly: FIFO low byte 799 | SFR_( ADC_FIFO_H,0xF5); // ReadOnly: FIFO high byte 800 | SFR_( ADC_SETUP ,0xF6); // ADC setup 801 | #define bADC_DMA_EN 0x80// DMA enable and DMA interrupt enable for ADC 802 | #define bADC_IE_FIFO_OV 0x40// enable interrupt for FIFO overflow 803 | #define bADC_IE_AIN7_LOW 0x20// enable interrupt for AIN7 low level 804 | #define bADC_IE_ACT 0x10// enable interrupt for a ADC finished 805 | #define bADC_CLOCK 0x08// ReadOnly: current level of ADC clock 806 | #define bADC_POWER_EN 0x04// control ADC power: 0=shut down ADC, 1=enable power for ADC 807 | #define bADC_EXT_SW_EN 0x02// control extend switch module power: 0=shut down, 1=enable power for extend switch 808 | #define bADC_AIN7_CHK_EN 0x01// control AIN7 level check module power: 0=shut down, 1=enable power for AIN7 level check 809 | SFR_(ADC_EX_SW,0xF7); // ADC extend switch control 810 | #define bADC_SW_AIN7_H 0x80// internal AIN7 extend switch control: 0=float AIN7, 1=tie AIN7 to high level VDD33 811 | #define bADC_SW_AIN6_L 0x40// internal AIN6 extend switch control: 0=float AIN6, 1=tie AIN6 to low level GND 812 | #define bADC_SW_AIN5_H 0x20// internal AIN5 extend switch control: 0=float AIN5, 1=tie AIN5 to high level VDD33 813 | #define bADC_SW_AIN4_L 0x10// internal AIN4 extend switch control: 0=float AIN4, 1=tie AIN4 to low level GND 814 | #define bADC_EXT_SW_SEL 0x08// extend switch resistance selection: 0=high resistance, 1=low resistance 815 | #define bADC_RESOLUTION 0x04// ADC resolution: 0=10 bits, 1=11 bits 816 | #define bADC_AIN7_DLY1 0x02// AIN7 level check delay control bit 1 817 | #define bADC_AIN7_DLY0 0x01// AIN7 level check delay control bit 0 818 | #define MASK_ADC_AIN7_DLY 0x03// bit mask for AIN7 check delay control: 01=longest, 10=longer, 11=shorter, 00=shortest (no delay) 819 | 820 | /* USB/Host/Device Registers */ 821 | SFR_(USB_RX_LEN,0xD1); // ReadOnly: USB receiving length 822 | SFR_(UEP1_CTRL ,0xD2); // endpoint 1 control 823 | #define bUEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 824 | #define bUEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 825 | #define bUEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 826 | #define bUEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) 827 | #define bUEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) 828 | #define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) 829 | #define UEP_R_RES_ACK 0x00 830 | #define UEP_R_RES_TOUT 0x04 831 | #define UEP_R_RES_NAK 0x08 832 | #define UEP_R_RES_STALL 0x0C 833 | #define bUEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) 834 | #define bUEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) 835 | #define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) 836 | #define UEP_T_RES_ACK 0x00 837 | #define UEP_T_RES_TOUT 0x01 838 | #define UEP_T_RES_NAK 0x02 839 | #define UEP_T_RES_STALL 0x03 840 | // bUEP_R_RES1 & bUEP_R_RES0: 841 | // handshake response type for USB endpoint X receiving (OUT) 842 | // 00: ACK (ready) 843 | // 01: no response, time out to host, for non-zero endpoint isochronous transactions 844 | // 10: NAK (busy) 845 | // 11: STALL (error) 846 | // bUEP_T_RES1 & bUEP_T_RES0: 847 | // handshake response type for USB endpoint X transmittal (IN) 848 | // 00: DATA0 or DATA1 then expecting ACK (ready) 849 | // 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions 850 | // 10: NAK (busy) 851 | // 11: STALL (error) 852 | SFR_(UEP1_T_LEN,0xD3); // endpoint 1 transmittal length 853 | SFR_(UEP2_CTRL ,0xD4); // endpoint 2 control 854 | SFR_(UEP2_T_LEN,0xD5); // endpoint 2 transmittal length 855 | SFR_(UEP3_CTRL ,0xD6); // endpoint 3 control 856 | SFR_(UEP3_T_LEN,0xD7); // endpoint 3 transmittal length 857 | SFR_(USB_INT_FG,0xD8); // USB interrupt flag 858 | SBIT_(U_IS_NAK ,0xD8,7); // ReadOnly: indicate current USB transfer is NAK received 859 | SBIT_(U_TOG_OK ,0xD8,6); // ReadOnly: indicate current USB transfer toggle is OK 860 | SBIT_(U_SIE_FREE ,0xD8,5); // ReadOnly: indicate USB SIE free status 861 | SBIT_(UIF_FIFO_OV ,0xD8,4); // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear 862 | SBIT_(UIF_HST_SOF ,0xD8,3); // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear 863 | SBIT_(UIF_SUSPEND ,0xD8,2); // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear 864 | SBIT_(UIF_TRANSFER,0xD8,1); // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear 865 | SBIT_(UIF_DETECT ,0xD8,0); // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear 866 | SBIT_(UIF_BUS_RST ,0xD8,0); // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear 867 | SFR_(USB_INT_ST,0xD9); // ReadOnly: USB interrupt status 868 | #define bUIS_IS_NAK 0x80 // ReadOnly: indicate current USB transfer is NAK received for USB device mode 869 | #define bUIS_TOG_OK 0x40 // ReadOnly: indicate current USB transfer toggle is OK 870 | #define bUIS_TOKEN1 0x20 // ReadOnly: current token PID code bit 1 received for USB device mode 871 | #define bUIS_TOKEN0 0x10 // ReadOnly: current token PID code bit 0 received for USB device mode 872 | #define MASK_UIS_TOKEN 0x30 // ReadOnly: bit mask of current token PID code received for USB device mode 873 | #define UIS_TOKEN_OUT 0x00 874 | #define UIS_TOKEN_SOF 0x10 875 | #define UIS_TOKEN_IN 0x20 876 | #define UIS_TOKEN_SETUP 0x30 877 | // bUIS_TOKEN1 & bUIS_TOKEN0: 878 | // current token PID code received for USB device mode 879 | // 00: OUT token PID received 880 | // 01: SOF token PID received 881 | // 10: IN token PID received 882 | // 11: SETUP token PID received 883 | #define MASK_UIS_ENDP 0x0F // ReadOnly: bit mask of current transfer endpoint number for USB device mode 884 | #define MASK_UIS_H_RES 0x0F // ReadOnly: bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received 885 | SFR_(USB_MIS_ST,0xDA); // ReadOnly: USB miscellaneous status 886 | #define bUMS_SOF_PRES 0x80 // ReadOnly: indicate host SOF timer presage status 887 | #define bUMS_SOF_ACT 0x40 // ReadOnly: indicate host SOF timer action status for USB host 888 | #define bUMS_SIE_FREE 0x20 // ReadOnly: indicate USB SIE free status 889 | #define bUMS_R_FIFO_RDY 0x10 // ReadOnly: indicate USB receiving FIFO ready status (not empty) 890 | #define bUMS_BUS_RESET 0x08 // ReadOnly: indicate USB bus reset status 891 | #define bUMS_SUSPEND 0x04 // ReadOnly: indicate USB suspend status 892 | #define bUMS_H1_ATTACH 0x02 // ReadOnly: indicate device attached status on USB hub1 HP/HM 893 | #define bUMS_H0_ATTACH 0x01 // ReadOnly: indicate device attached status on USB hub0 DP/DM 894 | SFR_(USB_HUB_ST,0xDB); // ReadOnly: USB host hub status 895 | #define bUHS_H1_ATTACH 0x80 // ReadOnly: indicate device attached status on USB hub1 HP/HM 896 | #define bUHS_HM_LEVEL 0x40 // ReadOnly: indicate HM level saved at device attached to USB hub1 897 | #define bUHS_HP_PIN 0x20 // ReadOnly: indicate current HP pin level 898 | #define bUHS_HM_PIN 0x10 // ReadOnly: indicate current HM pin level 899 | #define bUHS_H0_ATTACH 0x08 // ReadOnly: indicate device attached status on USB hub0 DP/DM 900 | #define bUHS_DM_LEVEL 0x04 // ReadOnly: indicate DM level saved at device attached to USB hub0 901 | #define bUHS_DP_PIN 0x02 // ReadOnly: indicate current DP pin level 902 | #define bUHS_DM_PIN 0x01 // ReadOnly: indicate current DM pin level 903 | SFR_(UEP0_CTRL ,0xDC); // endpoint 0 control 904 | SFR_(UEP0_T_LEN,0xDD); // endpoint 0 transmittal length 905 | SFR_(UEP4_CTRL ,0xDE); // endpoint 4 control 906 | SFR_(UEP4_T_LEN,0xDF); // endpoint 4 transmittal length 907 | SFR_(USB_INT_EN,0xE1); // USB interrupt enable 908 | #define bUIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode 909 | #define bUIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode 910 | #define bUIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow 911 | #define bUIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode 912 | #define bUIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event 913 | #define bUIE_TRANSFER 0x02 // enable interrupt for USB transfer completion 914 | #define bUIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode 915 | #define bUIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode 916 | SFR_(USB_CTRL,0xE2); // USB base control 917 | #define bUC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode 918 | #define bUC_LOW_SPEED 0x40 // enable USB low speed: 0=full speed, 1=low speed 919 | #define bUC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable 920 | #define bUC_SYS_CTRL1 0x20 // USB system control high bit 921 | #define bUC_SYS_CTRL0 0x10 // USB system control low bit 922 | #define MASK_UC_SYS_CTRL 0x30// bit mask of USB system control 923 | // bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: 924 | // USB system control 925 | // 0 00: disable USB device and disable internal pullup resistance 926 | // 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance 927 | // 0 10: enable USB device and enable internal pullup resistance 928 | // 0 11: enable USB device and enable internal weak pullup resistance 929 | // 1 00: enable USB host and normal status 930 | // 1 01: enable USB host and force DP/DM output SE0 state 931 | // 1 10: enable USB host and force DP/DM output J state 932 | // 1 11: enable USB host and force DP/DM output resume or K state 933 | #define bUC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid 934 | #define bUC_RESET_SIE 0x04 // force reset USB SIE, need software clear 935 | #define bUC_CLR_ALL 0x02 // force clear FIFO and count of USB 936 | #define bUC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB 937 | SFR_(USB_DEV_AD,0xE3); // USB device address, lower 7 bits for USB device address 938 | #define bUDA_GP_BIT 0x80 // general purpose bit 939 | #define MASK_USB_ADDR 0x7F // bit mask for USB device address 940 | SFR_(UDEV_CTRL,0xE4); // USB device physical port control 941 | #define bUD_RECV_DIS 0x40 // disable USB physical port receiver: 0=enable receiver, 1=disable receiver 942 | #define bUD_DP_PD_DIS 0x20 // disable USB DP pulldown resistance: 0=enable pulldown, 1=disable 943 | #define bUD_DM_PD_DIS 0x10 // disable USB DM pulldown resistance: 0=enable pulldown, 1=disable 944 | #define bUD_DIFF_IN 0x08 // ReadOnly: indicate current DP/DM difference input status 945 | #define bUD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed 946 | #define bUD_GP_BIT 0x02 // general purpose bit 947 | #define bUD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable 948 | SFR_(UHUB0_CTRL,0xE4); // USB hub0 control 949 | #define bUH_RECV_DIS 0x40 // disable USB hub receiver: 0=enable hub receiver, 1=disable hub receiver 950 | #define bUH_DP_PD_DIS 0x20 // disable USB DP or HP pulldown resistance: 0=enable pulldown, 1=disable 951 | #define bUH_DM_PD_DIS 0x10 // disable USB DM or HM pulldown resistance: 0=enable pulldown, 1=disable 952 | #define bUH_DIFF_IN 0x08 // ReadOnly: indicate current DP/DM or HP/HM difference input status 953 | #define bUH_LOW_SPEED 0x04 // enable USB hub low speed: 0=full speed, 1=low speed 954 | #define bUH_BUS_RESET 0x02 // control USB hub bus reset: 0=normal, 1=force bus reset 955 | #define bUH_PORT_EN 0x01 // enable USB hub port: 0=disable, 1=enable port, automatic disabled if USB device detached 956 | SFR_(UHUB1_CTRL,0xE5); // USB hub1 control 957 | #define bUH1_DISABLE 0x80 // disable USB hub1 pin: 0=enable hub1 and using HP/HM pin, 1=disable hub1 and releasing HP/HM pin 958 | #ifndef __UC__ 959 | SFR16_(USB_DMA, 0xE6); // ReadOnly: current DMA address, little-endian 960 | #endif 961 | SFR_(USB_DMA_AL,0xE6); // ReadOnly: current DMA address low byte 962 | SFR_(USB_DMA_AH,0xE7); // ReadOnly: current DMA address high byte 963 | SFR_(UH_SETUP ,0xD2); // host aux setup 964 | #define bUH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub 965 | #define bUH_SOF_EN 0x40 // USB host automatic SOF enable 966 | SFR_(UH_RX_CTRL,0xD4); // host receiver endpoint control 967 | #define bUH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 968 | #define bUH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle 969 | #define bUH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions 970 | SFR_(UH_EP_PID,0xD5); // host endpoint and token PID, lower 4 bits for endpoint number, upper 4 bits for token PID 971 | #define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer 972 | #define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer 973 | SFR_(UH_TX_CTRL,0xD6); // host transmittal endpoint control 974 | #define bUH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 975 | #define bUH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle 976 | #define bUH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions 977 | SFR_(UH_TX_LEN,0xD7); // host transmittal endpoint transmittal length 978 | 979 | /*----- XDATA: xRAM, xBUS, xSFR ------------------------------------------*/ 980 | #define XDATA_RAM_SIZE 0x1800 // size of expanded xRAM, xdata SRAM embedded chip 981 | #define XDATA_XBUS_ADDR 0x4000 // xdata xBUS start address 982 | #define XDATA_XBUS_CS0 0x4000 // xdata xBUS chip-selection 0# 983 | #define XDATA_XCS0_SIZE 0x4000 // size of xdata xBUS chip-selection 0#: @0x4000~0x7FFF 984 | #define XDATA_XBUS_CS1 0x8000 // xdata xBUS chip-selection 1# 985 | #define XDATA_XCS1_SIZE 0x8000 // size of xdata xBUS chip-selection 1#: @0x8000~0xFFFF 986 | 987 | 988 | #define bUEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) 989 | #define bUEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) 990 | #define bUEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 991 | #define bUEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) 992 | #define bUEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) 993 | // bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: 994 | // USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA 995 | // 0 0 x: disable endpoint and disable buffer 996 | // 1 0 0: 64 bytes buffer for receiving (OUT endpoint) 997 | // 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes 998 | // 0 1 0: 64 bytes buffer for transmittal (IN endpoint) 999 | // 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes 1000 | // 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes 1001 | // 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes 1002 | // bUEP4_RX_EN & bUEP4_TX_EN: 1003 | // USB endpoint 4 buffer mode, buffer start address is UEP0_DMA 1004 | // 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) 1005 | // 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes 1006 | // 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes 1007 | // 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) 1008 | // + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes 1009 | //extern unsigned char volatile XDATA UEP2_3_MOD; 1010 | #define bUEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) 1011 | #define bUEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) 1012 | #define bUEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 1013 | #define bUEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) 1014 | #define bUEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) 1015 | #define bUEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 1016 | 1017 | //UINT8XV UH_EP_MOD _at_ 0x2447; // host endpoint mode 1018 | #define bUH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal 1019 | #define bUH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint 1020 | #define bUH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving 1021 | #define bUH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint 1022 | 1023 | // bUH_EP_TX_EN & bUH_EP_TBUF_MOD: 1024 | // USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA 1025 | // 0 x: disable endpoint and disable buffer 1026 | // 1 0: 64 bytes buffer for transmittal (OUT endpoint) 1027 | // 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes 1028 | // bUH_EP_RX_EN & bUH_EP_RBUF_MOD: 1029 | // USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA 1030 | // 0 x: disable endpoint and disable buffer 1031 | // 1 0: 64 bytes buffer for receiving (IN endpoint) 1032 | // 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes 1033 | 1034 | /* LED Registers on xDATA, xSFR */ 1035 | #define REG_LED_BASE 0x2880 // LED registers base address 1036 | 1037 | //LED_STAT; 1038 | #define bLED_IF_DMA_END 0x80 // interrupt flag for DMA completion, write 1 to clear or write LED_DMA_CN to clear 1039 | #define bLED_FIFO_EMPTY 0x40 // ReadOnly: indicate FIFO empty status 1040 | #define bLED_IF_FIFO_REQ 0x20 // interrupt flag for request FIFO data ( FIFO <=2), write 1 to clear 1041 | #define bLED_CLOCK 0x10 // ReadOnly: current LED clock level 1042 | #define MASK_LED_FIFO_CNT 0x07 // ReadOnly: bit mask of LED FIFO count 1043 | 1044 | //LED_CTRL; 1045 | #define bLED_CHAN_MOD1 0x80 // LED channel mode high bit 1046 | #define bLED_CHAN_MOD0 0x40 // LED channel mode low bit 1047 | #define MASK_LED_CHAN_MOD 0xC0 // bit mask of LED channel mode 1048 | #define bLED_IE_FIFO_REQ 0x20 // enable interrupt for FIFO <=2 1049 | #define bLED_DMA_EN 0x10 // DMA enable and DMA interrupt enable for LED 1050 | #define bLED_OUT_EN 0x08 // LED output enable 1051 | #define bLED_OUT_POLAR 0x04 // LED output polarity: 0=pass, 1=invert 1052 | #define bLED_CLR_ALL 0x02 // force clear FIFO and count of LED 1053 | #define bLED_BIT_ORDER 0x01 // LED bit data order: 0=LSB first, 1=MSB 1054 | 1055 | // bLED_CHAN_MOD1 & bLED_CHAN_MOD0: 1056 | // LED channel mode 1057 | // 00: single channel output, LED0 1058 | // 01: dual channels output, LED0/1 1059 | // 10: 4 channels output, LED0~3 1060 | // 11: 4 channels output and LED2/3 from aux buffer, LED0~3 1061 | 1062 | 1063 | //*********************** new in v1.1 ************************************* 1064 | typedef struct _LEDXSFR 1065 | { 1066 | unsigned char volatile LED_STAT; 1067 | unsigned char volatile LED_CTRL; 1068 | unsigned char volatile LED_FIFO_CN; 1069 | unsigned char volatile LED_CK_SE; 1070 | unsigned char volatile LED_DMA_AH; // DMA address, must even address, automatic increasing after DMA 1071 | unsigned char volatile LED_DMA_AL; 1072 | unsigned char volatile LED_DMA_CN; 1073 | unsigned char volatile reserved; 1074 | unsigned char volatile LED_DMA_XH; // aux buffer DMA address, must even address, automatic increasing after DMA 1075 | unsigned char volatile LED_DMA_XL; 1076 | }LEDXSFR; 1077 | 1078 | /* 1079 | device example: 1080 | USBXSFR XDATA XUSB _at_ USB_XSFR_BASE; 1081 | void UsbDeviceInit(void) 1082 | { 1083 | ... 1084 | XUSB.DEVICE.UEP0_DMA_H = ((uint16_t) EP0_Buffer) >> 8; 1085 | XUSB.DEVICE.UEP0_DMA_L = ((uint16_t) EP0_Buffer) & 0xFF; 1086 | ... 1087 | } 1088 | host example: 1089 | void UsbHostInit(void) 1090 | { 1091 | ... 1092 | XUSB.HOST.UH_RX_DMA_H = ((uint16_t) HostRx_Buffer) >> 8; 1093 | XUSB.HOST.UH_RX_DMA_L = ((uint16_t) HostRx_Buffer) & 0xFF; 1094 | ... 1095 | } 1096 | 1097 | */ 1098 | #define USB_XSFR_BASE 0x2440 //originally REG_USB_AUX_BASE 1099 | typedef struct _USBDEVICE 1100 | { 1101 | unsigned char reserve[6]; // 0x2440 1102 | unsigned char volatile UEP4_1_MOD ; // 0x2446 1103 | unsigned char volatile UEP2_3_MOD ; // 0x2447 1104 | unsigned char volatile UEP0_DMA_H ; // EP0 & EP4 address, must be even 1105 | unsigned char volatile UEP0_DMA_L ; 1106 | unsigned char volatile UEP1_DMA_H ; // EP1 address, must be even 1107 | unsigned char volatile UEP1_DMA_L ; 1108 | unsigned char volatile UEP2_DMA_H ; // EP2 address, must be even 1109 | unsigned char volatile UEP2_DMA_L ; 1110 | unsigned char volatile UEP3_DMA_H ; // EP3 address, must be even 1111 | unsigned char volatile UEP3_DMA_L ; 1112 | }USBDEV; 1113 | 1114 | typedef struct _USBHOST 1115 | { 1116 | unsigned char reserve0[7]; // 0x2440 1117 | unsigned char volatile UH_EP_MOD ; // host mode cfg 1118 | unsigned char reserve1[4]; // 0x2448 1119 | unsigned char volatile UH_RX_DMA_H; // host rxbuffer addr, must be even 1120 | unsigned char volatile UH_RX_DMA_L; 1121 | unsigned char volatile UH_TX_DMA_H; // hOST txbuffer addr, must be even 1122 | unsigned char volatile UH_TX_DMA_L; 1123 | }USBHOST; 1124 | 1125 | typedef union _USBXSFR // device mode and hostmode share the XSFRs 1126 | { 1127 | USBDEV DEVICE; 1128 | USBHOST HOST; 1129 | }USBXSFR; 1130 | 1131 | 1132 | /*----- Reference Information --------------------------------------------*/ 1133 | #define ID_CH559 0x59 // chip ID 1134 | 1135 | /* Interrupt routine address and interrupt number */ 1136 | #define INT_ADDR_INT0 0x0003 // interrupt vector address for INT0 or LED 1137 | #define INT_ADDR_TMR0 0x000B // interrupt vector address for timer0 1138 | #define INT_ADDR_INT1 0x0013 // interrupt vector address for INT1 1139 | #define INT_ADDR_TMR1 0x001B // interrupt vector address for timer1 1140 | #define INT_ADDR_UART0 0x0023 // interrupt vector address for UART0 1141 | #define INT_ADDR_TMR2 0x002B // interrupt vector address for timer2 1142 | #define INT_ADDR_SPI0 0x0033 // interrupt vector address for SPI0 1143 | #define INT_ADDR_TMR3 0x003B // interrupt vector address for timer3 1144 | #define INT_ADDR_USB 0x0043 // interrupt vector address for USB 1145 | #define INT_ADDR_ADC 0x004B // interrupt vector address for ADC 1146 | #define INT_ADDR_UART1 0x0053 // interrupt vector address for UART1 1147 | #define INT_ADDR_PWM1 0x005B // interrupt vector address for PWM1 1148 | #define INT_ADDR_GPIO 0x0063 // interrupt vector address for GPIO 1149 | #define INT_ADDR_WDOG 0x006B // interrupt vector address for watch-dog timer 1150 | #define INT_NO_INT0 0 // interrupt number for INT0 or LED 1151 | #define INT_NO_TMR0 1 // interrupt number for timer0 1152 | #define INT_NO_INT1 2 // interrupt number for INT1 1153 | #define INT_NO_TMR1 3 // interrupt number for timer1 1154 | #define INT_NO_UART0 4 // interrupt number for UART0 1155 | #define INT_NO_TMR2 5 // interrupt number for timer2 1156 | #define INT_NO_SPI0 6 // interrupt number for SPI0 1157 | #define INT_NO_TMR3 7 // interrupt number for timer3 1158 | #define INT_NO_USB 8 // interrupt number for USB 1159 | #define INT_NO_ADC 9 // interrupt number for ADC 1160 | #define INT_NO_UART1 10 // interrupt number for UART1 1161 | #define INT_NO_PWM1 11 // interrupt number for PWM1 1162 | #define INT_NO_GPIO 12 // interrupt number for GPIO 1163 | #define INT_NO_WDOG 13 // interrupt number for watch-dog timer 1164 | 1165 | /* Special Program Space */ 1166 | #define DATA_FLASH_ADDR 0xF000 // start address of Data-Flash 1167 | #define BOOT_LOAD_ADDR 0xF400 // start address of boot loader program 1168 | #define ROM_CFG_ADDR 0xFFFE // chip configuration information address 1169 | // new in V1.1 1170 | #define DATA_FLASH_SIZE 0x0400 1171 | #define UUID_ADDR 0x0020 1172 | #define CODE_FLASH_SIZE 0xF000 1173 | 1174 | 1175 | #define CH559_H_ 1176 | #endif 1177 | -------------------------------------------------------------------------------- /ch559/lib/compiler.h: -------------------------------------------------------------------------------- 1 | #ifndef COMPILER_H_ 2 | /* 3 | Compiler settings inspired from compiler_defs.h found on the net 4 | it does not use #elif because uc51 does not support #elif 5 | Tasking CC51 is untested. Especially its unclear if it is big endian 6 | 7 | for each compiler the following macros should be defined 8 | 9 | SFR_() defines a reg in the SFR area 0x80..0xFF 10 | SBIT_() defines a single bit within the SFR 11 | Note: only valid for SFRs divideable by 8 12 | SFR16_() defines a 16 bit sfr in little endian 13 | Note: the order of access is not guaranted 14 | NOP() greates a nop istruction 15 | */ 16 | 17 | #ifdef BIG_ENDIAN_ 18 | #undef BIG_ENDIAN_ 19 | #endif 20 | 21 | #ifdef __RC51__ // Raisonance seems dead now 22 | #define DATA data 23 | #define IDATA idata 24 | #define XDATA xdata 25 | #define PDATA pdata 26 | #define CODE code 27 | #define BDATA bdata 28 | #define BIT bit 29 | #define BIG_ENDIAN_ 30 | 31 | #define SFR(name_,adr_) sfr at adr_ name_ 32 | #define SBIT(name_,adr_, pos_) at (adr_+pos_) sbit name_ 33 | #define SFR16(name_,adr_) sfr16 at adr_ name_ 34 | #define NOP() asm { 0x00 } 35 | #endif 36 | 37 | #ifdef __C51__ // keil 38 | #define DATA data 39 | #define IDATA idata 40 | #define XDATA xdata 41 | #define PDATA pdata 42 | #define CODE code 43 | #define BDATA bdata 44 | #define BIT bit 45 | #define BIG_ENDIAN_ 46 | 47 | #define SFR_(name_,adr_) sfr name_ = adr_ 48 | #define SFR16_(name_,adr_) sfr16 name_ = adr_ 49 | #define SBIT_(name_,adr_,pos_) sbit name_ = adr_^pos_ 50 | #include 51 | #define NOP() _nop_() 52 | #endif 53 | 54 | #ifdef __SDCC_mcs51 // SDCC 55 | #define DATA __data 56 | #define IDATA __idata 57 | #define XDATA __xdata 58 | #define PDATA __pdata 59 | #define CODE __code 60 | #define BDATA __bdata 61 | #define BIT __bit 62 | #define MAKE16(adr_) (((adr_+1) << 8)+adr_) //helper 63 | #define SFR_(name_,adr_) __sfr __at (adr_) name_ 64 | #define SBIT_(name_,adr_,pos_) __sbit __at (adr_+pos_) name_ 65 | #define SFR16_(name_,adr_) __sfr16 __at (MAKE16(adr_)) name_ 66 | #define NOP() __asm__ ("nop") 67 | #endif 68 | 69 | #ifdef __IAR_SYSTEMS_ICC__ // iar 70 | #define DATA __data 71 | #define IDATA __idata 72 | #define XDATA __xdata 73 | #define PDATA __pdata 74 | #define CODE __code 75 | #define BDATA __bdata 76 | #define BIT __bit 77 | 78 | #include 79 | #define SFR_(name_, adr_) __sfr __no_init volatile unsigned char name_ @ adr_ 80 | #define SBIT_(name_, adr_, pos_) __bit __no_init volatile bool name_ @ (adr_+pos_) 81 | #define SFR16_(name_, adr_) __sfr __no_init volatile unsigned int name_ @ adr_ 82 | #define NOP() asm ("nop") 83 | #endif 84 | 85 | #ifdef __UC__ // wickenhaeuser uc51 dead demo at www.batronics.com 86 | #define BIG_ENDIAN_ 87 | 88 | #define SFR_(name_,adr_) near unsigned char name_ @ adr_ 89 | #define SBIT_(name_,adr_,pos_) unsigned char bit name_ @ adr_+pos_ 90 | #define SFR16_(name_,adr_) // not supported 91 | extern void _nop_(void); 92 | #define NOP() _nop_() 93 | #endif 94 | 95 | #ifdef _CC51 //tasking not tested at all 96 | #define DATA _data 97 | #define IDATA _idat 98 | #define XDATA _xdat 99 | #define PDATA _pdat 100 | #define CODE _rom 101 | #define BDATA _bdat 102 | #define BIT _bit 103 | #define BIG_ENDIAN_ //not shure but keyword _little inticades it 104 | 105 | #define SFR_(name_, adr_) _sfrbyte name_ _at(adr_) 106 | #define SBIT_(name_, adr_, pos_) _sfrbit name_ _at(adr_+pos_) 107 | #define SFR16_(name_, adr_) _sfrword _little name_ _at(adr_) 108 | extern void _nop (void); 109 | #define NOP() _nop() 110 | #endif 111 | 112 | // do a simple check if we have a unknown compiler 113 | #ifndef SFR_ 114 | #error "Error Compiler unknown" 115 | stop compiling 116 | #endif 117 | 118 | #define COMPILER_H_ 119 | #endif 120 | -------------------------------------------------------------------------------- /ch559/lib/uart.c: -------------------------------------------------------------------------------- 1 | #include "ch559.h" 2 | #include "uart.h" 3 | 4 | /* 5 | * P3.0 -> RX 6 | * P3.1 -> TX 7 | */ 8 | 9 | // Initlize UART0 using T1 timer for baud generation. 10 | void uart0_init() { 11 | 12 | // SM0 & SM1: UART0 mode 13 | // 00 - mode 0, shift Register, baud rate fixed at: Fsys/12 14 | // 01 - mode 1, 8-bit UART, baud rate = variable by timer1 or timer2 overflow rate 15 | // 10 - mode 2, 9-bit UART, baud rate fixed at: Fsys/128@SMOD=0, Fsys/32@SMOD=1 16 | // 11 - mode 3, 9-bit UART, baud rate = variable by timer1 or timer2 overflow rate 17 | SM0 = 0; 18 | SM1 = 1; 19 | 20 | // RCLK select UART0 receiving clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse 21 | // TCLK select UART0 transmittal clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse 22 | RCLK = 0; 23 | TCLK = 0; 24 | 25 | // bT1_M1 & bT1_M0: timer1 mode 26 | // 00: mode 0, 13-bit timer or counter by cascaded TH1 and lower 5 bits of TL1, the upper 3 bits of TL1 are ignored 27 | // 01: mode 1, 16-bit timer or counter by cascaded TH1 and TL1 28 | // 10: mode 2, TL1 operates as 8-bit timer or counter, and TH1 provide initial value for TL1 auto-reload 29 | // 11: mode 3, stop timer1 30 | TMOD = MASK_T1_MOD & (bT1_M1 | ~bT1_M0); 31 | 32 | PCON |= SMOD; 33 | T2MOD = T2MOD | bTMR_CLK | bT1_CLK; 34 | TH1 = 256 - FREQ_SYS/16/UART0_BAUD; 35 | 36 | TR1 = 1; 37 | TI = 1; 38 | REN = 1; 39 | } 40 | 41 | // Map UART0 to alternative pins P0.2/P0.3 42 | void uart0_alter() { 43 | 44 | } 45 | 46 | // Receive one byte data from UART0 47 | uint8_t uart0_read() { 48 | while(!RI); 49 | RI = 0; 50 | return SBUF; 51 | } 52 | 53 | // Send one byte data to UART0 54 | void uart0_write(uint8_t data) { 55 | while (!TI); 56 | TI = 0; 57 | SBUF = data & 0xFF; 58 | } 59 | -------------------------------------------------------------------------------- /ch559/lib/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef __UART_H__ 2 | #define __UART_H__ 3 | 4 | #include 5 | 6 | #ifndef FREQ_SYS 7 | #define FREQ_SYS 12000000 // System frequency is 12MHz 8 | #endif 9 | 10 | 11 | #ifndef UART0_BAUD 12 | #define UART0_BAUD 9600 13 | #endif 14 | 15 | void uart0_init(); // Initlize UART0 using T1 timer for baud generation. 16 | void uart0_alter(); // Map UART0 to alternative pins P0.2/P0.3 17 | uint8_t uart0_read(); // Receive one byte data from UART0 18 | void uart0_write(uint8_t data); // Send one byte data to UART0 19 | 20 | 21 | #endif // __UART_H__ 22 | --------------------------------------------------------------------------------