├── .gitmodules ├── main.h ├── .gitignore ├── cmake ├── stm32f410rb.cmake └── stm32cubef4.cmake ├── linker_script.ld ├── LICENSE ├── CMakeLists.txt ├── core ├── stm32f4xx_it.h ├── syscalls.c ├── stm32f4xx_hal_msp.c ├── stm32f4xx_it.c ├── STM32F410RBTx_FLASH.ld ├── stm32f4xx_hal_conf.h ├── startup_stm32f410rx.s └── system_stm32f4xx.c ├── README.md └── main.c /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "vendor/STM32CubeF4"] 2 | path = vendor/STM32CubeF4 3 | url = https://github.com/STMicroelectronics/STM32CubeF4 4 | -------------------------------------------------------------------------------- /main.h: -------------------------------------------------------------------------------- 1 | #ifndef MAIN_H 2 | #define MAIN_H 3 | 4 | #include "stm32f4xx.h" 5 | 6 | #define LED_PIN GPIO_PIN_5 7 | #define LED_PORT GPIOA 8 | 9 | extern UART_HandleTypeDef uart2; 10 | 11 | #endif -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Editor settings 2 | .vscode 3 | .project 4 | .settings 5 | compile_commands.json 6 | 7 | # Build output 8 | *.o 9 | *.elf 10 | /build* 11 | 12 | # Temporary files 13 | /tmp 14 | /temp -------------------------------------------------------------------------------- /cmake/stm32f410rb.cmake: -------------------------------------------------------------------------------- 1 | set(CMAKE_SYSTEM_NAME Generic) 2 | set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) 3 | 4 | set(CMAKE_C_COMPILER arm-none-eabi-gcc) 5 | set(CMAKE_CXX_COMPILER arm-none-eabi-g++) 6 | set(CMAKE_ASM_COMPILER arm-none-eabi-gcc) 7 | 8 | # https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html 9 | set(MCU_FLAGS "-mcpu=cortex-m4 -mthumb") 10 | 11 | set(CMAKE_C_FLAGS_INIT ${MCU_FLAGS}) 12 | set(CMAKE_CXX_FLAGS_INIT ${MCU_FLAGS}) 13 | set(CMAKE_ASM_FLAGS_INIT ${MCU_FLAGS}) 14 | 15 | add_compile_definitions(STM32F410Rx) -------------------------------------------------------------------------------- /cmake/stm32cubef4.cmake: -------------------------------------------------------------------------------- 1 | set(STM32CUBEF4_DIR "${CMAKE_SOURCE_DIR}/vendor/STM32CubeF4") 2 | set(HAL_ROOT_DIR "${STM32CUBEF4_DIR}/Drivers/STM32F4xx_HAL_Driver") 3 | set(HAL_SOURCE_DIR "${HAL_ROOT_DIR}/Src") 4 | set(HAL_INCLUDE_DIR "${HAL_ROOT_DIR}/Inc") 5 | 6 | set(HAL_SOURCES 7 | "${HAL_SOURCE_DIR}/stm32f4xx_hal.c" 8 | "${HAL_SOURCE_DIR}/stm32f4xx_hal_rcc.c" 9 | "${HAL_SOURCE_DIR}/stm32f4xx_hal_cortex.c" 10 | "${HAL_SOURCE_DIR}/stm32f4xx_hal_gpio.c" 11 | "${HAL_SOURCE_DIR}/stm32f4xx_hal_uart.c" 12 | "${HAL_SOURCE_DIR}/stm32f4xx_hal_dma.c") 13 | 14 | add_library(stm32cubef4 STATIC ${HAL_SOURCES}) 15 | 16 | target_include_directories(stm32cubef4 PUBLIC 17 | ${STM32CUBEF4_DIR}/Drivers/CMSIS/Core/Include 18 | ${STM32CUBEF4_DIR}/Drivers/CMSIS/Device/ST/STM32F4xx/Include 19 | ${STM32CUBEF4_DIR}/Drivers/STM32F4xx_HAL_Driver/Inc 20 | ${CMAKE_SOURCE_DIR}/core) 21 | -------------------------------------------------------------------------------- /linker_script.ld: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | FLASH (rx): ORIGIN = 0x08000000, LENGTH = 128K 4 | SRAM (rwx): ORIGIN = 0x20000000, LENGTH = 32K 5 | } 6 | 7 | ENTRY(Reset_Handler) 8 | 9 | _estack = ORIGIN(SRAM) + LENGTH(SRAM); 10 | 11 | SECTIONS 12 | { 13 | .isr_vector : 14 | { 15 | KEEP(*(.isr_vector)) 16 | } >FLASH 17 | 18 | .text : 19 | { 20 | . = ALIGN(4); 21 | 22 | *(.text) 23 | *(.text.*) 24 | *(.rodata) 25 | *(.rodata.*) 26 | KEEP(*(.init)) 27 | KEEP(*(.fini)) 28 | *(.eh_frame) 29 | *(.ARM.exidx) 30 | 31 | . = ALIGN(4); 32 | _etext = .; 33 | } >FLASH 34 | 35 | _sidata = LOADADDR(.data); 36 | 37 | .data : 38 | { 39 | . = ALIGN(4); 40 | _sdata = .; 41 | 42 | *(.data) 43 | *(.data.*) 44 | KEEP(*(.init_array)) 45 | KEEP(*(.fini_array)) 46 | 47 | . = ALIGN(4); 48 | _edata = .; 49 | } >SRAM AT> FLASH 50 | 51 | .bss : 52 | { 53 | . = ALIGN(4); 54 | _sbss = .; 55 | __bss_start__ = _sbss; 56 | 57 | *(.bss) 58 | *(.bss.*) 59 | 60 | . = ALIGN(4); 61 | _ebss = .; 62 | __bss_end__ = _ebss; 63 | } >SRAM 64 | } 65 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Kristian Klein-Wengel 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | project(stm32-without-cubeide 4 | LANGUAGES C ASM) 5 | 6 | add_compile_definitions(USE_HAL_DRIVER) 7 | add_compile_options(-g -O0) # Global compile flags 8 | 9 | set(BLINK_SOURCES 10 | main.c 11 | core/syscalls.c 12 | core/startup_stm32f410rx.s 13 | core/system_stm32f4xx.c 14 | core/stm32f4xx_hal_msp.c 15 | core/stm32f4xx_it.c) 16 | 17 | add_executable(blink ${BLINK_SOURCES}) 18 | 19 | set_target_properties(blink PROPERTIES OUTPUT_NAME "blink.elf") 20 | 21 | target_include_directories(blink PRIVATE 22 | ${CMAKE_SOURCE_DIR} 23 | ${CMAKE_SOURCE_DIR}/core) 24 | 25 | target_compile_options(blink PRIVATE 26 | --specs=nano.specs) 27 | 28 | target_link_options(blink PRIVATE 29 | -T ${CMAKE_SOURCE_DIR}/core/STM32F410RBTx_FLASH.ld 30 | -u _printf_float) 31 | 32 | include(cmake/stm32cubef4.cmake) 33 | target_link_libraries(blink stm32cubef4) 34 | 35 | set(PROGRAMMER openocd) 36 | set(PROGRAMMER_FLAGS -f interface/stlink.cfg -f target/stm32f4x.cfg) 37 | 38 | add_custom_target(flash 39 | COMMAND ${PROGRAMMER} ${PROGRAMMER_FLAGS} -c "program $ verify reset exit" 40 | DEPENDS blink 41 | VERBATIM) 42 | -------------------------------------------------------------------------------- /core/stm32f4xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Templates/Inc/stm32f4xx_it.h 4 | * @author MCD Application Team 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __STM32F4xx_IT_H 21 | #define __STM32F4xx_IT_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | 33 | void NMI_Handler(void); 34 | void HardFault_Handler(void); 35 | void MemManage_Handler(void); 36 | void BusFault_Handler(void); 37 | void UsageFault_Handler(void); 38 | void SVC_Handler(void); 39 | void DebugMon_Handler(void); 40 | void PendSV_Handler(void); 41 | void SysTick_Handler(void); 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | 47 | #endif /* __STM32F4xx_IT_H */ 48 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32 without CubeIDE 2 | 3 | Code for the blog post series "STM32 without CubeIDE" at https://kleinembedded.com 4 | 5 | - [Part 1: The bare necessities](https://kleinembedded.com/stm32-without-cubeide-part-1-the-bare-necessities) 6 | - [Part 2: CMSIS, make and clock configuration](https://kleinembedded.com/stm32-without-cubeide-part-2-cmsis-make-and-clock-configuration) 7 | - [Part 3: The C Standard Library and printf](https://kleinembedded.com/stm32-without-cubeide-part-3-the-c-standard-library-and-printf) 8 | - [Part 4: CMake, FPU and STM32 libraries](https://kleinembedded.com/stm32-without-cubeide-part-4-cmake-fpu-and-stm32-libraries) 9 | 10 | ## Initializing submodules 11 | From part 4 of this series, the official STM32CubeF4 package is added as a git submodule. This makes it easy to get the newest updates and bugfixes whenever a new version is published. 12 | 13 | After cloning the stm32-without-cubeide repository, initialize the top-level submodule: 14 | 15 | `git submodule update --init` 16 | 17 | Enter the submodule and initialize the CMSIS device driver and the HAL/LL library: 18 | 19 | ```shell 20 | cd vendor/STM32CubeF4 21 | git submodule update --init Drivers/CMSIS/Device/ST/STM32F4xx/ Drivers/STM32F4xx_HAL_Driver/ 22 | ``` 23 | 24 | In order to update STM32CubeF4 to the newest version, simply navigate to the submodule's root directory, pull from remote and update the 25 | (already initialized) submodules: 26 | 27 | ```shell 28 | cd vendor/STM32CubeF4 29 | git pull origin master 30 | git submodule update --recursive 31 | ``` 32 | 33 | ## Building with CMake 34 | After cloning the repository and initializing the submodules as described 35 | above, you can configure and build the project with CMake from the root 36 | project directory: 37 | 38 | ```shell 39 | cmake -Bbuild -DCMAKE_TOOLCHAIN_FILE=cmake/stm32f410rb.cmake 40 | cmake --build build 41 | ``` 42 | 43 | Then flash the program to the target with: 44 | 45 | ```shell 46 | cmake --build build --target flash 47 | ``` 48 | -------------------------------------------------------------------------------- /core/syscalls.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "main.h" 4 | #include 5 | #undef errno 6 | extern int errno; 7 | 8 | void _exit(int exit_code) 9 | { 10 | while (1) 11 | { 12 | 13 | } 14 | } 15 | 16 | int _close(int file) { 17 | return -1; 18 | } 19 | 20 | char *__env[1] = { 0 }; 21 | char **environ = __env; 22 | 23 | int _execve(char *name, char **argv, char **env) { 24 | errno = ENOMEM; 25 | return -1; 26 | } 27 | 28 | int _fork(void) { 29 | errno = EAGAIN; 30 | return -1; 31 | } 32 | 33 | 34 | int _fstat(int file, struct stat *st) { 35 | st->st_mode = S_IFCHR; 36 | return 0; 37 | } 38 | 39 | int _getpid(void) { 40 | return 1; 41 | } 42 | 43 | int _isatty(int file) { 44 | return 1; 45 | } 46 | 47 | int _kill(int pid, int sig) { 48 | errno = EINVAL; 49 | return -1; 50 | } 51 | 52 | int _link(char *old, char *new) { 53 | errno = EMLINK; 54 | return -1; 55 | } 56 | 57 | int _lseek(int file, int ptr, int dir) { 58 | return 0; 59 | } 60 | 61 | int _open(const char *name, int flags, int mode) { 62 | return -1; 63 | } 64 | 65 | int _read(int file, char *ptr, int len) { 66 | return 0; 67 | } 68 | 69 | register char * stack_ptr asm("sp"); 70 | 71 | caddr_t _sbrk(int incr) { 72 | extern char __bss_end__; /* Defined by the linker */ 73 | static char *heap_end; 74 | char *prev_heap_end; 75 | 76 | if (heap_end == 0) { 77 | heap_end = &__bss_end__; 78 | } 79 | prev_heap_end = heap_end; 80 | if (heap_end + incr > stack_ptr) { 81 | while (1) 82 | { 83 | // Heap and stack collision 84 | } 85 | } 86 | 87 | heap_end += incr; 88 | return (caddr_t) prev_heap_end; 89 | } 90 | 91 | int _stat(char *file, struct stat *st) { 92 | st->st_mode = S_IFCHR; 93 | return 0; 94 | } 95 | 96 | int _times(struct tms *buf) { 97 | return -1; 98 | } 99 | 100 | int _unlink(char *name) { 101 | errno = ENOENT; 102 | return -1; 103 | } 104 | 105 | int _wait(int *status) { 106 | errno = ECHILD; 107 | return -1; 108 | } 109 | 110 | int _write(int file, char *ptr, int len) { 111 | (void) file; 112 | HAL_UART_Transmit(&uart2, ptr, len, HAL_MAX_DELAY); 113 | return len; 114 | } -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "main.h" 4 | 5 | UART_HandleTypeDef uart2; 6 | 7 | void clock_init(); 8 | 9 | void main(void) 10 | { 11 | HAL_Init(); 12 | clock_init(); 13 | SystemCoreClockUpdate(); // Update the internal clock frequency variable 14 | 15 | // Initialize LED GPIO 16 | __HAL_RCC_GPIOA_CLK_ENABLE(); 17 | 18 | GPIO_InitTypeDef gpio_init = {0}; 19 | gpio_init.Pin = LED_PIN; 20 | gpio_init.Mode = GPIO_MODE_OUTPUT_PP; 21 | gpio_init.Pull = GPIO_NOPULL; 22 | gpio_init.Speed = GPIO_SPEED_LOW; 23 | gpio_init.Alternate = 0; 24 | 25 | HAL_GPIO_Init(LED_PORT, &gpio_init); 26 | 27 | // Initialize UART 28 | uart2.Instance = USART2; 29 | uart2.Init.BaudRate = 115200; 30 | uart2.Init.Mode = UART_MODE_TX; 31 | uart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 32 | uart2.Init.WordLength = UART_WORDLENGTH_8B; 33 | uart2.Init.StopBits = UART_STOPBITS_1; 34 | uart2.Init.Parity = UART_PARITY_NONE; 35 | uart2.Init.OverSampling = UART_OVERSAMPLING_16; 36 | if (HAL_UART_Init(&uart2) != HAL_OK) 37 | { 38 | while(1); 39 | } 40 | 41 | // Dummy write, because the first byte seems to always be dropped 42 | USART2->DR = 0; 43 | while (!(USART2->SR & USART_SR_TC)); 44 | 45 | while(1) 46 | { 47 | HAL_GPIO_TogglePin(LED_PORT, LED_PIN); 48 | printf("[%.3f] Hello, World!\r\n", HAL_GetTick()/1000.0f); 49 | HAL_Delay(500); 50 | } 51 | } 52 | 53 | void clock_init() 54 | { 55 | /* By default HSI (16 MHz RC oscillator) is selected as system clock. 56 | * We want to use the HSE (8 MHz MCO from ST-LINK connected to OSC_IN) 57 | * through the PLL to get 100 MHz system clock. 58 | */ 59 | 60 | // Enable power controller and set voltage scale mode 1 61 | __HAL_RCC_PWR_CLK_ENABLE(); 62 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 63 | 64 | // Configure PLL dividers and multiplier 65 | /* Input to PLL should be 1-2 MHz (preferably 2 MHz). Choosing M=4 gives 66 | * us 8 MHz / 4 = 2 MHz. 67 | * The output of the PLL should be 100-438 MHz, so setting the feedback 68 | * multiplier to N=200 gives us 2 MHz * 200 = 400 MHz. 69 | * The system clock should be 100 MHz. Choosing P=4 gives us 70 | * 400 MHz / 4 = 100 MHz 71 | */ 72 | RCC_OscInitTypeDef osc_init = {0}; 73 | osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE; 74 | osc_init.HSEState = RCC_HSE_BYPASS; 75 | osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; 76 | osc_init.PLL.PLLState = RCC_PLL_ON; 77 | osc_init.PLL.PLLM = 4; 78 | osc_init.PLL.PLLN = 200; 79 | osc_init.PLL.PLLP = RCC_PLLP_DIV4; 80 | osc_init.PLL.PLLQ = 8; 81 | if (HAL_RCC_OscConfig(&osc_init) != HAL_OK) 82 | { 83 | while(1); 84 | } 85 | 86 | /* Set PLL output as the source for the system clock. 87 | * Since APB1 clock must not be more than 50 MHz, set the PCKL1 divider to 2. 88 | */ 89 | RCC_ClkInitTypeDef clock_init = {0}; 90 | clock_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK; 91 | clock_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 92 | clock_init.AHBCLKDivider = RCC_SYSCLK_DIV1; 93 | clock_init.APB1CLKDivider = RCC_HCLK_DIV2; 94 | clock_init.APB2CLKDivider = RCC_HCLK_DIV1; 95 | 96 | if (HAL_RCC_ClockConfig(&clock_init, FLASH_LATENCY_3) != HAL_OK) // Configure flash controller for 3V3 supply and 100 MHz -> 3 wait states 97 | { 98 | while(1); 99 | } 100 | } 101 | -------------------------------------------------------------------------------- /core/stm32f4xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_msp_template.c 4 | * @author MCD Application Team 5 | * @brief This file contains the HAL System and Peripheral (PPP) MSP initialization 6 | * and de-initialization functions. 7 | * It should be copied to the application folder and renamed into 'stm32f4xx_hal_msp.c'. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * Copyright (c) 2017 STMicroelectronics. 12 | * All rights reserved. 13 | * 14 | * This software is licensed under terms that can be found in the LICENSE file 15 | * in the root directory of this software component. 16 | * If no LICENSE file comes with this software, it is provided AS-IS. 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f4xx_hal.h" 23 | 24 | /** @addtogroup STM32F4xx_HAL_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup HAL_MSP HAL MSP 29 | * @brief HAL MSP module. 30 | * @{ 31 | */ 32 | 33 | /* Private typedef -----------------------------------------------------------*/ 34 | /* Private define ------------------------------------------------------------*/ 35 | /* Private macro -------------------------------------------------------------*/ 36 | /* Private variables ---------------------------------------------------------*/ 37 | /* Private function prototypes -----------------------------------------------*/ 38 | /* Private functions ---------------------------------------------------------*/ 39 | 40 | /** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief Initializes the Global MSP. 46 | * @note This function is called from HAL_Init() function to perform system 47 | * level initialization (GPIOs, clock, DMA, interrupt). 48 | * @retval None 49 | */ 50 | void HAL_MspInit(void) 51 | { 52 | 53 | } 54 | 55 | /** 56 | * @brief DeInitializes the Global MSP. 57 | * @note This functiona is called from HAL_DeInit() function to perform system 58 | * level de-initialization (GPIOs, clock, DMA, interrupt). 59 | * @retval None 60 | */ 61 | void HAL_MspDeInit(void) 62 | { 63 | 64 | } 65 | 66 | /** 67 | * @brief Initializes the PPP MSP. 68 | * @note This functiona is called from HAL_PPP_Init() function to perform 69 | * peripheral(PPP) system level initialization (GPIOs, clock, DMA, interrupt) 70 | * @retval None 71 | */ 72 | void HAL_PPP_MspInit(void) 73 | { 74 | 75 | } 76 | 77 | /** 78 | * @brief DeInitializes the PPP MSP. 79 | * @note This functiona is called from HAL_PPP_DeInit() function to perform 80 | * peripheral(PPP) system level de-initialization (GPIOs, clock, DMA, interrupt) 81 | * @retval None 82 | */ 83 | void HAL_PPP_MspDeInit(void) 84 | { 85 | 86 | } 87 | 88 | /** 89 | * @} 90 | */ 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** 97 | * @} 98 | */ 99 | 100 | 101 | void HAL_UART_MspInit(UART_HandleTypeDef *huart) 102 | { 103 | if (huart->Instance == USART2) 104 | { 105 | __HAL_RCC_USART2_CLK_ENABLE(); 106 | __HAL_RCC_GPIOA_CLK_ENABLE(); 107 | 108 | GPIO_InitTypeDef rx_tx_init = {0}; 109 | rx_tx_init.Pin = GPIO_PIN_2 | GPIO_PIN_3; 110 | rx_tx_init.Mode = GPIO_MODE_AF_PP; 111 | rx_tx_init.Alternate = GPIO_AF7_USART2; 112 | rx_tx_init.Pull = GPIO_NOPULL; 113 | rx_tx_init.Speed = GPIO_SPEED_FAST; 114 | 115 | HAL_GPIO_Init(GPIOA, &rx_tx_init); 116 | } 117 | } -------------------------------------------------------------------------------- /core/stm32f4xx_it.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Templates/Src/stm32f4xx_it.c 4 | * @author MCD Application Team 5 | * @brief Main Interrupt Service Routines. 6 | * This file provides template for all exceptions handler and 7 | * peripherals interrupt service routine. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * Copyright (c) 2017 STMicroelectronics. 12 | * All rights reserved. 13 | * 14 | * This software is licensed under terms that can be found in the LICENSE file 15 | * in the root directory of this software component. 16 | * If no LICENSE file comes with this software, it is provided AS-IS. 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32f4xx_it.h" 24 | 25 | /** @addtogroup STM32F4xx_HAL_Examples 26 | * @{ 27 | */ 28 | 29 | /** @addtogroup Templates 30 | * @{ 31 | */ 32 | 33 | /* Private typedef -----------------------------------------------------------*/ 34 | /* Private define ------------------------------------------------------------*/ 35 | /* Private macro -------------------------------------------------------------*/ 36 | /* Private variables ---------------------------------------------------------*/ 37 | /* Private function prototypes -----------------------------------------------*/ 38 | /* Private functions ---------------------------------------------------------*/ 39 | 40 | /******************************************************************************/ 41 | /* Cortex-M4 Processor Exceptions Handlers */ 42 | /******************************************************************************/ 43 | 44 | /** 45 | * @brief This function handles NMI exception. 46 | * @param None 47 | * @retval None 48 | */ 49 | void NMI_Handler(void) 50 | { 51 | } 52 | 53 | /** 54 | * @brief This function handles Hard Fault exception. 55 | * @param None 56 | * @retval None 57 | */ 58 | void HardFault_Handler(void) 59 | { 60 | /* Go to infinite loop when Hard Fault exception occurs */ 61 | while (1) 62 | { 63 | } 64 | } 65 | 66 | /** 67 | * @brief This function handles Memory Manage exception. 68 | * @param None 69 | * @retval None 70 | */ 71 | void MemManage_Handler(void) 72 | { 73 | /* Go to infinite loop when Memory Manage exception occurs */ 74 | while (1) 75 | { 76 | } 77 | } 78 | 79 | /** 80 | * @brief This function handles Bus Fault exception. 81 | * @param None 82 | * @retval None 83 | */ 84 | void BusFault_Handler(void) 85 | { 86 | /* Go to infinite loop when Bus Fault exception occurs */ 87 | while (1) 88 | { 89 | } 90 | } 91 | 92 | /** 93 | * @brief This function handles Usage Fault exception. 94 | * @param None 95 | * @retval None 96 | */ 97 | void UsageFault_Handler(void) 98 | { 99 | /* Go to infinite loop when Usage Fault exception occurs */ 100 | while (1) 101 | { 102 | } 103 | } 104 | 105 | /** 106 | * @brief This function handles SVCall exception. 107 | * @param None 108 | * @retval None 109 | */ 110 | void SVC_Handler(void) 111 | { 112 | } 113 | 114 | /** 115 | * @brief This function handles Debug Monitor exception. 116 | * @param None 117 | * @retval None 118 | */ 119 | void DebugMon_Handler(void) 120 | { 121 | } 122 | 123 | /** 124 | * @brief This function handles PendSVC exception. 125 | * @param None 126 | * @retval None 127 | */ 128 | void PendSV_Handler(void) 129 | { 130 | } 131 | 132 | /** 133 | * @brief This function handles SysTick Handler. 134 | * @param None 135 | * @retval None 136 | */ 137 | void SysTick_Handler(void) 138 | { 139 | HAL_IncTick(); 140 | } 141 | 142 | /******************************************************************************/ 143 | /* STM32F4xx Peripherals Interrupt Handlers */ 144 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ 145 | /* available peripheral interrupt handler's name please refer to the startup */ 146 | /* file (startup_stm32f4xx.s). */ 147 | /******************************************************************************/ 148 | 149 | /** 150 | * @brief This function handles PPP interrupt request. 151 | * @param None 152 | * @retval None 153 | */ 154 | /*void PPP_IRQHandler(void) 155 | { 156 | }*/ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /** 163 | * @} 164 | */ 165 | -------------------------------------------------------------------------------- /core/STM32F410RBTx_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ***************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** @author : Auto-generated by STM32CubeIDE 8 | ** 9 | ** Abstract : Linker script for STM32F410RBTx Device with 10 | ** 128KByte FLASH, 32KByte RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used. 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** 20 | ** Distribution: The file is distributed as is, without any warranty 21 | ** of any kind. 22 | ** 23 | ***************************************************************************** 24 | ** @attention 25 | ** 26 | ** Copyright (c) 2023 STMicroelectronics. 27 | ** All rights reserved. 28 | ** 29 | ** This software is licensed under terms that can be found in the LICENSE file 30 | ** in the root directory of this software component. 31 | ** If no LICENSE file comes with this software, it is provided AS-IS. 32 | ** 33 | ****************************************************************************** 34 | */ 35 | 36 | /* Entry Point */ 37 | ENTRY(Reset_Handler) 38 | 39 | /* Highest address of the user mode stack */ 40 | _estack = 0x20008000; /* end of RAM */ 41 | /* Generate a link error if heap and stack don't fit into RAM */ 42 | _Min_Heap_Size = 0x200; /* required amount of heap */ 43 | _Min_Stack_Size = 0x400; /* required amount of stack */ 44 | 45 | /* Specify the memory areas */ 46 | MEMORY 47 | { 48 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K 49 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K 50 | } 51 | 52 | /* Define output sections */ 53 | SECTIONS 54 | { 55 | /* The startup code goes first into FLASH */ 56 | .isr_vector : 57 | { 58 | . = ALIGN(4); 59 | KEEP(*(.isr_vector)) /* Startup code */ 60 | . = ALIGN(4); 61 | } >FLASH 62 | 63 | /* The program code and other data goes into FLASH */ 64 | .text : 65 | { 66 | . = ALIGN(4); 67 | *(.text) /* .text sections (code) */ 68 | *(.text*) /* .text* sections (code) */ 69 | *(.glue_7) /* glue arm to thumb code */ 70 | *(.glue_7t) /* glue thumb to arm code */ 71 | *(.eh_frame) 72 | 73 | KEEP (*(.init)) 74 | KEEP (*(.fini)) 75 | 76 | . = ALIGN(4); 77 | _etext = .; /* define a global symbols at end of code */ 78 | } >FLASH 79 | 80 | /* Constant data goes into FLASH */ 81 | .rodata : 82 | { 83 | . = ALIGN(4); 84 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 85 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 86 | . = ALIGN(4); 87 | } >FLASH 88 | 89 | .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ 90 | { 91 | *(.ARM.extab* .gnu.linkonce.armextab.*) 92 | } >FLASH 93 | .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ 94 | { 95 | __exidx_start = .; 96 | *(.ARM.exidx*) 97 | __exidx_end = .; 98 | } >FLASH 99 | 100 | .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ 101 | { 102 | PROVIDE_HIDDEN (__preinit_array_start = .); 103 | KEEP (*(.preinit_array*)) 104 | PROVIDE_HIDDEN (__preinit_array_end = .); 105 | } >FLASH 106 | .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ 107 | { 108 | PROVIDE_HIDDEN (__init_array_start = .); 109 | KEEP (*(SORT(.init_array.*))) 110 | KEEP (*(.init_array*)) 111 | PROVIDE_HIDDEN (__init_array_end = .); 112 | } >FLASH 113 | .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ 114 | { 115 | PROVIDE_HIDDEN (__fini_array_start = .); 116 | KEEP (*(SORT(.fini_array.*))) 117 | KEEP (*(.fini_array*)) 118 | PROVIDE_HIDDEN (__fini_array_end = .); 119 | } >FLASH 120 | 121 | /* used by the startup to initialize data */ 122 | _sidata = LOADADDR(.data); 123 | 124 | /* Initialized data sections goes into RAM, load LMA copy after code */ 125 | .data : 126 | { 127 | . = ALIGN(4); 128 | _sdata = .; /* create a global symbol at data start */ 129 | *(.data) /* .data sections */ 130 | *(.data*) /* .data* sections */ 131 | 132 | . = ALIGN(4); 133 | _edata = .; /* define a global symbol at data end */ 134 | } >RAM AT> FLASH 135 | 136 | 137 | /* Uninitialized data section */ 138 | . = ALIGN(4); 139 | .bss : 140 | { 141 | /* This is used by the startup in order to initialize the .bss section */ 142 | _sbss = .; /* define a global symbol at bss start */ 143 | __bss_start__ = _sbss; 144 | *(.bss) 145 | *(.bss*) 146 | *(COMMON) 147 | 148 | . = ALIGN(4); 149 | _ebss = .; /* define a global symbol at bss end */ 150 | __bss_end__ = _ebss; 151 | } >RAM 152 | 153 | /* User_heap_stack section, used to check that there is enough RAM left */ 154 | ._user_heap_stack : 155 | { 156 | . = ALIGN(8); 157 | PROVIDE ( end = . ); 158 | PROVIDE ( _end = . ); 159 | . = . + _Min_Heap_Size; 160 | . = . + _Min_Stack_Size; 161 | . = ALIGN(8); 162 | } >RAM 163 | 164 | 165 | 166 | /* Remove information from the standard libraries */ 167 | /DISCARD/ : 168 | { 169 | libc.a ( * ) 170 | libm.a ( * ) 171 | libgcc.a ( * ) 172 | } 173 | 174 | .ARM.attributes 0 : { *(.ARM.attributes) } 175 | } 176 | 177 | 178 | -------------------------------------------------------------------------------- /core/stm32f4xx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_conf.h 4 | * @author MCD Application Team 5 | * @brief HAL configuration file. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __STM32F4xx_HAL_CONF_H 21 | #define __STM32F4xx_HAL_CONF_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Exported types ------------------------------------------------------------*/ 28 | /* Exported constants --------------------------------------------------------*/ 29 | 30 | /* ########################## Module Selection ############################## */ 31 | /** 32 | * @brief This is the list of modules to be used in the HAL driver 33 | */ 34 | #define HAL_MODULE_ENABLED 35 | #define HAL_ADC_MODULE_ENABLED 36 | #define HAL_CAN_MODULE_ENABLED 37 | /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ 38 | #define HAL_CRC_MODULE_ENABLED 39 | #define HAL_CEC_MODULE_ENABLED 40 | #define HAL_CRYP_MODULE_ENABLED 41 | #define HAL_DAC_MODULE_ENABLED 42 | #define HAL_DCMI_MODULE_ENABLED 43 | #define HAL_DMA_MODULE_ENABLED 44 | #define HAL_DMA2D_MODULE_ENABLED 45 | #define HAL_ETH_MODULE_ENABLED 46 | #define HAL_EXTI_MODULE_ENABLED 47 | #define HAL_FLASH_MODULE_ENABLED 48 | #define HAL_NAND_MODULE_ENABLED 49 | #define HAL_NOR_MODULE_ENABLED 50 | #define HAL_PCCARD_MODULE_ENABLED 51 | #define HAL_SRAM_MODULE_ENABLED 52 | #define HAL_SDRAM_MODULE_ENABLED 53 | #define HAL_HASH_MODULE_ENABLED 54 | #define HAL_GPIO_MODULE_ENABLED 55 | #define HAL_I2C_MODULE_ENABLED 56 | #define HAL_I2S_MODULE_ENABLED 57 | #define HAL_IWDG_MODULE_ENABLED 58 | /* #define HAL_LTDC_MODULE_ENABLED */ 59 | #define HAL_DSI_MODULE_ENABLED 60 | #define HAL_PWR_MODULE_ENABLED 61 | #define HAL_QSPI_MODULE_ENABLED 62 | #define HAL_RCC_MODULE_ENABLED 63 | #define HAL_RNG_MODULE_ENABLED 64 | #define HAL_RTC_MODULE_ENABLED 65 | #define HAL_SAI_MODULE_ENABLED 66 | #define HAL_SD_MODULE_ENABLED 67 | #define HAL_SPI_MODULE_ENABLED 68 | #define HAL_TIM_MODULE_ENABLED 69 | #define HAL_UART_MODULE_ENABLED 70 | #define HAL_USART_MODULE_ENABLED 71 | #define HAL_IRDA_MODULE_ENABLED 72 | #define HAL_SMARTCARD_MODULE_ENABLED 73 | #define HAL_WWDG_MODULE_ENABLED 74 | #define HAL_CORTEX_MODULE_ENABLED 75 | #define HAL_PCD_MODULE_ENABLED 76 | #define HAL_HCD_MODULE_ENABLED 77 | #define HAL_FMPI2C_MODULE_ENABLED 78 | #define HAL_SPDIFRX_MODULE_ENABLED 79 | #define HAL_LPTIM_MODULE_ENABLED 80 | 81 | /* ########################## HSE/HSI Values adaptation ##################### */ 82 | /** 83 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 84 | * This value is used by the RCC HAL module to compute the system frequency 85 | * (when HSE is used as system clock source, directly or through the PLL). 86 | */ 87 | #if !defined (HSE_VALUE) 88 | #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ 89 | #endif /* HSE_VALUE */ 90 | 91 | #if !defined (HSE_STARTUP_TIMEOUT) 92 | #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ 93 | #endif /* HSE_STARTUP_TIMEOUT */ 94 | 95 | /** 96 | * @brief Internal High Speed oscillator (HSI) value. 97 | * This value is used by the RCC HAL module to compute the system frequency 98 | * (when HSI is used as system clock source, directly or through the PLL). 99 | */ 100 | #if !defined (HSI_VALUE) 101 | #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ 102 | #endif /* HSI_VALUE */ 103 | 104 | /** 105 | * @brief Internal Low Speed oscillator (LSI) value. 106 | */ 107 | #if !defined (LSI_VALUE) 108 | #define LSI_VALUE (32000U) /*!< LSI Typical Value in Hz*/ 109 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 110 | The real value may vary depending on the variations 111 | in voltage and temperature.*/ 112 | /** 113 | * @brief External Low Speed oscillator (LSE) value. 114 | */ 115 | #if !defined (LSE_VALUE) 116 | #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ 117 | #endif /* LSE_VALUE */ 118 | 119 | #if !defined (LSE_STARTUP_TIMEOUT) 120 | #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ 121 | #endif /* LSE_STARTUP_TIMEOUT */ 122 | 123 | /** 124 | * @brief External clock source for I2S peripheral 125 | * This value is used by the I2S HAL module to compute the I2S clock source 126 | * frequency, this source is inserted directly through I2S_CKIN pad. 127 | */ 128 | #if !defined (EXTERNAL_CLOCK_VALUE) 129 | #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the external oscillator in Hz*/ 130 | #endif /* EXTERNAL_CLOCK_VALUE */ 131 | 132 | /* Tip: To avoid modifying this file each time you need to use different HSE, 133 | === you can define the HSE value in your toolchain compiler preprocessor. */ 134 | 135 | /* ########################### System Configuration ######################### */ 136 | /** 137 | * @brief This is the HAL system configuration section 138 | */ 139 | #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ 140 | #define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ 141 | #define USE_RTOS 0 142 | #define PREFETCH_ENABLE 1 143 | #define INSTRUCTION_CACHE_ENABLE 1 144 | #define DATA_CACHE_ENABLE 1U 145 | 146 | #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ 147 | #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ 148 | #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ 149 | #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ 150 | #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ 151 | #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ 152 | #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ 153 | #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ 154 | #define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ 155 | #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ 156 | #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ 157 | #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ 158 | #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ 159 | #define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ 160 | #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ 161 | #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ 162 | #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ 163 | #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ 164 | #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ 165 | #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ 166 | #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ 167 | #define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ 168 | #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ 169 | #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ 170 | #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ 171 | #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ 172 | #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ 173 | #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ 174 | #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ 175 | #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ 176 | #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ 177 | #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ 178 | #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ 179 | #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ 180 | #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ 181 | #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ 182 | #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ 183 | #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ 184 | 185 | /* ########################## Assert Selection ############################## */ 186 | /** 187 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 188 | * HAL drivers code 189 | */ 190 | /* #define USE_FULL_ASSERT 1 */ 191 | 192 | /* ################## SPI peripheral configuration ########################## */ 193 | 194 | /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver 195 | * Activated: CRC code is present inside driver 196 | * Deactivated: CRC code cleaned from driver 197 | */ 198 | 199 | #define USE_SPI_CRC 1U 200 | 201 | /* Includes ------------------------------------------------------------------*/ 202 | /** 203 | * @brief Include module's header file 204 | */ 205 | 206 | #ifdef HAL_RCC_MODULE_ENABLED 207 | #include "stm32f4xx_hal_rcc.h" 208 | #endif /* HAL_RCC_MODULE_ENABLED */ 209 | 210 | #ifdef HAL_EXTI_MODULE_ENABLED 211 | #include "stm32f4xx_hal_exti.h" 212 | #endif /* HAL_EXTI_MODULE_ENABLED */ 213 | 214 | #ifdef HAL_GPIO_MODULE_ENABLED 215 | #include "stm32f4xx_hal_gpio.h" 216 | #endif /* HAL_GPIO_MODULE_ENABLED */ 217 | 218 | #ifdef HAL_DMA_MODULE_ENABLED 219 | #include "stm32f4xx_hal_dma.h" 220 | #endif /* HAL_DMA_MODULE_ENABLED */ 221 | 222 | #ifdef HAL_CORTEX_MODULE_ENABLED 223 | #include "stm32f4xx_hal_cortex.h" 224 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 225 | 226 | #ifdef HAL_ADC_MODULE_ENABLED 227 | #include "stm32f4xx_hal_adc.h" 228 | #endif /* HAL_ADC_MODULE_ENABLED */ 229 | 230 | #ifdef HAL_CAN_MODULE_ENABLED 231 | #include "stm32f4xx_hal_can.h" 232 | #endif /* HAL_CAN_MODULE_ENABLED */ 233 | 234 | #ifdef HAL_CAN_LEGACY_MODULE_ENABLED 235 | #include "stm32f4xx_hal_can_legacy.h" 236 | #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ 237 | 238 | #ifdef HAL_CRC_MODULE_ENABLED 239 | #include "stm32f4xx_hal_crc.h" 240 | #endif /* HAL_CRC_MODULE_ENABLED */ 241 | 242 | #ifdef HAL_CRYP_MODULE_ENABLED 243 | #include "stm32f4xx_hal_cryp.h" 244 | #endif /* HAL_CRYP_MODULE_ENABLED */ 245 | 246 | #ifdef HAL_DMA2D_MODULE_ENABLED 247 | #include "stm32f4xx_hal_dma2d.h" 248 | #endif /* HAL_DMA2D_MODULE_ENABLED */ 249 | 250 | #ifdef HAL_DAC_MODULE_ENABLED 251 | #include "stm32f4xx_hal_dac.h" 252 | #endif /* HAL_DAC_MODULE_ENABLED */ 253 | 254 | #ifdef HAL_DCMI_MODULE_ENABLED 255 | #include "stm32f4xx_hal_dcmi.h" 256 | #endif /* HAL_DCMI_MODULE_ENABLED */ 257 | 258 | #ifdef HAL_ETH_MODULE_ENABLED 259 | #include "stm32f4xx_hal_eth.h" 260 | #endif /* HAL_ETH_MODULE_ENABLED */ 261 | 262 | #ifdef HAL_FLASH_MODULE_ENABLED 263 | #include "stm32f4xx_hal_flash.h" 264 | #endif /* HAL_FLASH_MODULE_ENABLED */ 265 | 266 | #ifdef HAL_SRAM_MODULE_ENABLED 267 | #include "stm32f4xx_hal_sram.h" 268 | #endif /* HAL_SRAM_MODULE_ENABLED */ 269 | 270 | #ifdef HAL_NOR_MODULE_ENABLED 271 | #include "stm32f4xx_hal_nor.h" 272 | #endif /* HAL_NOR_MODULE_ENABLED */ 273 | 274 | #ifdef HAL_NAND_MODULE_ENABLED 275 | #include "stm32f4xx_hal_nand.h" 276 | #endif /* HAL_NAND_MODULE_ENABLED */ 277 | 278 | #ifdef HAL_PCCARD_MODULE_ENABLED 279 | #include "stm32f4xx_hal_pccard.h" 280 | #endif /* HAL_PCCARD_MODULE_ENABLED */ 281 | 282 | #ifdef HAL_SDRAM_MODULE_ENABLED 283 | #include "stm32f4xx_hal_sdram.h" 284 | #endif /* HAL_SDRAM_MODULE_ENABLED */ 285 | 286 | #ifdef HAL_HASH_MODULE_ENABLED 287 | #include "stm32f4xx_hal_hash.h" 288 | #endif /* HAL_HASH_MODULE_ENABLED */ 289 | 290 | #ifdef HAL_I2C_MODULE_ENABLED 291 | #include "stm32f4xx_hal_i2c.h" 292 | #endif /* HAL_I2C_MODULE_ENABLED */ 293 | 294 | #ifdef HAL_I2S_MODULE_ENABLED 295 | #include "stm32f4xx_hal_i2s.h" 296 | #endif /* HAL_I2S_MODULE_ENABLED */ 297 | 298 | #ifdef HAL_IWDG_MODULE_ENABLED 299 | #include "stm32f4xx_hal_iwdg.h" 300 | #endif /* HAL_IWDG_MODULE_ENABLED */ 301 | 302 | #ifdef HAL_LTDC_MODULE_ENABLED 303 | #include "stm32f4xx_hal_ltdc.h" 304 | #endif /* HAL_LTDC_MODULE_ENABLED */ 305 | 306 | #ifdef HAL_PWR_MODULE_ENABLED 307 | #include "stm32f4xx_hal_pwr.h" 308 | #endif /* HAL_PWR_MODULE_ENABLED */ 309 | 310 | #ifdef HAL_RNG_MODULE_ENABLED 311 | #include "stm32f4xx_hal_rng.h" 312 | #endif /* HAL_RNG_MODULE_ENABLED */ 313 | 314 | #ifdef HAL_RTC_MODULE_ENABLED 315 | #include "stm32f4xx_hal_rtc.h" 316 | #endif /* HAL_RTC_MODULE_ENABLED */ 317 | 318 | #ifdef HAL_SAI_MODULE_ENABLED 319 | #include "stm32f4xx_hal_sai.h" 320 | #endif /* HAL_SAI_MODULE_ENABLED */ 321 | 322 | #ifdef HAL_SD_MODULE_ENABLED 323 | #include "stm32f4xx_hal_sd.h" 324 | #endif /* HAL_SD_MODULE_ENABLED */ 325 | 326 | #ifdef HAL_SPI_MODULE_ENABLED 327 | #include "stm32f4xx_hal_spi.h" 328 | #endif /* HAL_SPI_MODULE_ENABLED */ 329 | 330 | #ifdef HAL_TIM_MODULE_ENABLED 331 | #include "stm32f4xx_hal_tim.h" 332 | #endif /* HAL_TIM_MODULE_ENABLED */ 333 | 334 | #ifdef HAL_UART_MODULE_ENABLED 335 | #include "stm32f4xx_hal_uart.h" 336 | #endif /* HAL_UART_MODULE_ENABLED */ 337 | 338 | #ifdef HAL_USART_MODULE_ENABLED 339 | #include "stm32f4xx_hal_usart.h" 340 | #endif /* HAL_USART_MODULE_ENABLED */ 341 | 342 | #ifdef HAL_IRDA_MODULE_ENABLED 343 | #include "stm32f4xx_hal_irda.h" 344 | #endif /* HAL_IRDA_MODULE_ENABLED */ 345 | 346 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 347 | #include "stm32f4xx_hal_smartcard.h" 348 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 349 | 350 | #ifdef HAL_WWDG_MODULE_ENABLED 351 | #include "stm32f4xx_hal_wwdg.h" 352 | #endif /* HAL_WWDG_MODULE_ENABLED */ 353 | 354 | #ifdef HAL_PCD_MODULE_ENABLED 355 | #include "stm32f4xx_hal_pcd.h" 356 | #endif /* HAL_PCD_MODULE_ENABLED */ 357 | 358 | #ifdef HAL_HCD_MODULE_ENABLED 359 | #include "stm32f4xx_hal_hcd.h" 360 | #endif /* HAL_HCD_MODULE_ENABLED */ 361 | 362 | #ifdef HAL_DSI_MODULE_ENABLED 363 | #include "stm32f4xx_hal_dsi.h" 364 | #endif /* HAL_DSI_MODULE_ENABLED */ 365 | 366 | #ifdef HAL_QSPI_MODULE_ENABLED 367 | #include "stm32f4xx_hal_qspi.h" 368 | #endif /* HAL_QSPI_MODULE_ENABLED */ 369 | 370 | #ifdef HAL_CEC_MODULE_ENABLED 371 | #include "stm32f4xx_hal_cec.h" 372 | #endif /* HAL_CEC_MODULE_ENABLED */ 373 | 374 | #ifdef HAL_FMPI2C_MODULE_ENABLED 375 | #include "stm32f4xx_hal_fmpi2c.h" 376 | #endif /* HAL_FMPI2C_MODULE_ENABLED */ 377 | 378 | #ifdef HAL_SPDIFRX_MODULE_ENABLED 379 | #include "stm32f4xx_hal_spdifrx.h" 380 | #endif /* HAL_SPDIFRX_MODULE_ENABLED */ 381 | 382 | #ifdef HAL_LPTIM_MODULE_ENABLED 383 | #include "stm32f4xx_hal_lptim.h" 384 | #endif /* HAL_LPTIM_MODULE_ENABLED */ 385 | 386 | /* Exported macro ------------------------------------------------------------*/ 387 | #ifdef USE_FULL_ASSERT 388 | /** 389 | * @brief The assert_param macro is used for function's parameters check. 390 | * @param expr: If expr is false, it calls assert_failed function 391 | * which reports the name of the source file and the source 392 | * line number of the call that failed. 393 | * If expr is true, it returns no value. 394 | * @retval None 395 | */ 396 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 397 | /* Exported functions ------------------------------------------------------- */ 398 | void assert_failed(uint8_t* file, uint32_t line); 399 | #else 400 | #define assert_param(expr) ((void)0U) 401 | #endif /* USE_FULL_ASSERT */ 402 | 403 | 404 | #ifdef __cplusplus 405 | } 406 | #endif 407 | 408 | #endif /* __STM32F4xx_HAL_CONF_H */ 409 | -------------------------------------------------------------------------------- /core/startup_stm32f410rx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f410rx.s 4 | * @author MCD Application Team 5 | * @brief STM32F410Rx Devices vector table for GCC based toolchains. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M4 processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | * Copyright (c) 2017 STMicroelectronics. 18 | * All rights reserved. 19 | * 20 | * This software is licensed under terms that can be found in the LICENSE file 21 | * in the root directory of this software component. 22 | * If no LICENSE file comes with this software, it is provided AS-IS. 23 | * 24 | ****************************************************************************** 25 | */ 26 | 27 | .syntax unified 28 | .cpu cortex-m4 29 | .fpu softvfp 30 | .thumb 31 | 32 | .global g_pfnVectors 33 | .global Default_Handler 34 | 35 | /* start address for the initialization values of the .data section. 36 | defined in linker script */ 37 | .word _sidata 38 | /* start address for the .data section. defined in linker script */ 39 | .word _sdata 40 | /* end address for the .data section. defined in linker script */ 41 | .word _edata 42 | /* start address for the .bss section. defined in linker script */ 43 | .word _sbss 44 | /* end address for the .bss section. defined in linker script */ 45 | .word _ebss 46 | /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ 47 | 48 | /** 49 | * @brief This is the code that gets called when the processor first 50 | * starts execution following a reset event. Only the absolutely 51 | * necessary set is performed, after which the application 52 | * supplied main() routine is called. 53 | * @param None 54 | * @retval : None 55 | */ 56 | 57 | .section .text.Reset_Handler 58 | .weak Reset_Handler 59 | .type Reset_Handler, %function 60 | Reset_Handler: 61 | ldr sp, =_estack /* set stack pointer */ 62 | 63 | /* Call the clock system initialization function.*/ 64 | bl SystemInit 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | ldr r0, =_sdata 68 | ldr r1, =_edata 69 | ldr r2, =_sidata 70 | movs r3, #0 71 | b LoopCopyDataInit 72 | 73 | CopyDataInit: 74 | ldr r4, [r2, r3] 75 | str r4, [r0, r3] 76 | adds r3, r3, #4 77 | 78 | LoopCopyDataInit: 79 | adds r4, r0, r3 80 | cmp r4, r1 81 | bcc CopyDataInit 82 | 83 | /* Zero fill the bss segment. */ 84 | ldr r2, =_sbss 85 | ldr r4, =_ebss 86 | movs r3, #0 87 | b LoopFillZerobss 88 | 89 | FillZerobss: 90 | str r3, [r2] 91 | adds r2, r2, #4 92 | 93 | LoopFillZerobss: 94 | cmp r2, r4 95 | bcc FillZerobss 96 | 97 | /* Call static constructors */ 98 | bl __libc_init_array 99 | /* Call the application's entry point.*/ 100 | bl main 101 | bx lr 102 | .size Reset_Handler, .-Reset_Handler 103 | 104 | /** 105 | * @brief This is the code that gets called when the processor receives an 106 | * unexpected interrupt. This simply enters an infinite loop, preserving 107 | * the system state for examination by a debugger. 108 | * @param None 109 | * @retval None 110 | */ 111 | .section .text.Default_Handler,"ax",%progbits 112 | Default_Handler: 113 | Infinite_Loop: 114 | b Infinite_Loop 115 | .size Default_Handler, .-Default_Handler 116 | /****************************************************************************** 117 | * 118 | * The minimal vector table for a Cortex M3. Note that the proper constructs 119 | * must be placed on this to ensure that it ends up at physical address 120 | * 0x0000.0000. 121 | * 122 | *******************************************************************************/ 123 | .section .isr_vector,"a",%progbits 124 | .type g_pfnVectors, %object 125 | 126 | g_pfnVectors: 127 | .word _estack 128 | .word Reset_Handler 129 | .word NMI_Handler 130 | .word HardFault_Handler 131 | .word MemManage_Handler 132 | .word BusFault_Handler 133 | .word UsageFault_Handler 134 | .word 0 135 | .word 0 136 | .word 0 137 | .word 0 138 | .word SVC_Handler 139 | .word DebugMon_Handler 140 | .word 0 141 | .word PendSV_Handler 142 | .word SysTick_Handler 143 | 144 | /* External Interrupts */ 145 | .word WWDG_IRQHandler /* Window WatchDog */ 146 | .word PVD_IRQHandler /* PVD through EXTI Line detection */ 147 | .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ 148 | .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ 149 | .word FLASH_IRQHandler /* FLASH */ 150 | .word RCC_IRQHandler /* RCC */ 151 | .word EXTI0_IRQHandler /* EXTI Line0 */ 152 | .word EXTI1_IRQHandler /* EXTI Line1 */ 153 | .word EXTI2_IRQHandler /* EXTI Line2 */ 154 | .word EXTI3_IRQHandler /* EXTI Line3 */ 155 | .word EXTI4_IRQHandler /* EXTI Line4 */ 156 | .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ 157 | .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ 158 | .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ 159 | .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ 160 | .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ 161 | .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ 162 | .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ 163 | .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ 164 | .word 0 /* Reserved */ 165 | .word 0 /* Reserved */ 166 | .word 0 /* Reserved */ 167 | .word 0 /* Reserved */ 168 | .word EXTI9_5_IRQHandler /* External Line[9:5]s */ 169 | .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ 170 | .word TIM1_UP_IRQHandler /* TIM1 Update */ 171 | .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ 172 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 173 | .word 0 /* Reserved */ 174 | .word 0 /* Reserved */ 175 | .word 0 /* Reserved */ 176 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 177 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 178 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 179 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 180 | .word SPI1_IRQHandler /* SPI1 */ 181 | .word SPI2_IRQHandler /* SPI2 */ 182 | .word USART1_IRQHandler /* USART1 */ 183 | .word USART2_IRQHandler /* USART2 */ 184 | .word 0 /* Reserved */ 185 | .word EXTI15_10_IRQHandler /* External Line[15:10]s */ 186 | .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ 187 | .word 0 /* Reserved */ 188 | .word 0 /* Reserved */ 189 | .word 0 /* Reserved */ 190 | .word 0 /* Reserved */ 191 | .word 0 /* Reserved */ 192 | .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ 193 | .word 0 /* Reserved */ 194 | .word 0 /* Reserved */ 195 | .word TIM5_IRQHandler /* TIM5 */ 196 | .word 0 /* Reserved */ 197 | .word 0 /* Reserved */ 198 | .word 0 /* Reserved */ 199 | .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ 200 | .word 0 /* Reserved */ 201 | .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ 202 | .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ 203 | .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ 204 | .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ 205 | .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ 206 | .word 0 /* Reserved */ 207 | .word 0 /* Reserved */ 208 | .word 0 /* Reserved */ 209 | .word 0 /* Reserved */ 210 | .word 0 /* Reserved */ 211 | .word 0 /* Reserved */ 212 | .word 0 /* Reserved */ 213 | .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ 214 | .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ 215 | .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ 216 | .word USART6_IRQHandler /* USART6 */ 217 | .word 0 /* Reserved */ 218 | .word 0 /* Reserved */ 219 | .word 0 /* Reserved */ 220 | .word 0 /* Reserved */ 221 | .word 0 /* Reserved */ 222 | .word 0 /* Reserved */ 223 | .word 0 /* Reserved */ 224 | .word 0 /* Reserved */ 225 | .word RNG_IRQHandler /* RNG */ 226 | .word FPU_IRQHandler /* FPU */ 227 | .word 0 /* Reserved */ 228 | .word 0 /* Reserved */ 229 | .word 0 /* Reserved */ 230 | .word SPI5_IRQHandler /* SPI5 */ 231 | .word 0 /* Reserved */ 232 | .word 0 /* Reserved */ 233 | .word 0 /* Reserved */ 234 | .word 0 /* Reserved */ 235 | .word 0 /* Reserved */ 236 | .word 0 /* Reserved */ 237 | .word 0 /* Reserved */ 238 | .word 0 /* Reserved */ 239 | .word 0 /* Reserved */ 240 | .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ 241 | .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ 242 | .word LPTIM1_IRQHandler /* LP TIM1 */ 243 | 244 | 245 | .size g_pfnVectors, .-g_pfnVectors 246 | 247 | /******************************************************************************* 248 | * 249 | * Provide weak aliases for each Exception handler to the Default_Handler. 250 | * As they are weak aliases, any function with the same name will override 251 | * this definition. 252 | * 253 | *******************************************************************************/ 254 | .weak NMI_Handler 255 | .thumb_set NMI_Handler,Default_Handler 256 | 257 | .weak HardFault_Handler 258 | .thumb_set HardFault_Handler,Default_Handler 259 | 260 | .weak MemManage_Handler 261 | .thumb_set MemManage_Handler,Default_Handler 262 | 263 | .weak BusFault_Handler 264 | .thumb_set BusFault_Handler,Default_Handler 265 | 266 | .weak UsageFault_Handler 267 | .thumb_set UsageFault_Handler,Default_Handler 268 | 269 | .weak SVC_Handler 270 | .thumb_set SVC_Handler,Default_Handler 271 | 272 | .weak DebugMon_Handler 273 | .thumb_set DebugMon_Handler,Default_Handler 274 | 275 | .weak PendSV_Handler 276 | .thumb_set PendSV_Handler,Default_Handler 277 | 278 | .weak SysTick_Handler 279 | .thumb_set SysTick_Handler,Default_Handler 280 | 281 | .weak WWDG_IRQHandler 282 | .thumb_set WWDG_IRQHandler,Default_Handler 283 | 284 | .weak PVD_IRQHandler 285 | .thumb_set PVD_IRQHandler,Default_Handler 286 | 287 | .weak TAMP_STAMP_IRQHandler 288 | .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 289 | 290 | .weak RTC_WKUP_IRQHandler 291 | .thumb_set RTC_WKUP_IRQHandler,Default_Handler 292 | 293 | .weak FLASH_IRQHandler 294 | .thumb_set FLASH_IRQHandler,Default_Handler 295 | 296 | .weak RCC_IRQHandler 297 | .thumb_set RCC_IRQHandler,Default_Handler 298 | 299 | .weak EXTI0_IRQHandler 300 | .thumb_set EXTI0_IRQHandler,Default_Handler 301 | 302 | .weak EXTI1_IRQHandler 303 | .thumb_set EXTI1_IRQHandler,Default_Handler 304 | 305 | .weak EXTI2_IRQHandler 306 | .thumb_set EXTI2_IRQHandler,Default_Handler 307 | 308 | .weak EXTI3_IRQHandler 309 | .thumb_set EXTI3_IRQHandler,Default_Handler 310 | 311 | .weak EXTI4_IRQHandler 312 | .thumb_set EXTI4_IRQHandler,Default_Handler 313 | 314 | .weak DMA1_Stream0_IRQHandler 315 | .thumb_set DMA1_Stream0_IRQHandler,Default_Handler 316 | 317 | .weak DMA1_Stream1_IRQHandler 318 | .thumb_set DMA1_Stream1_IRQHandler,Default_Handler 319 | 320 | .weak DMA1_Stream2_IRQHandler 321 | .thumb_set DMA1_Stream2_IRQHandler,Default_Handler 322 | 323 | .weak DMA1_Stream3_IRQHandler 324 | .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 325 | 326 | .weak DMA1_Stream4_IRQHandler 327 | .thumb_set DMA1_Stream4_IRQHandler,Default_Handler 328 | 329 | .weak DMA1_Stream5_IRQHandler 330 | .thumb_set DMA1_Stream5_IRQHandler,Default_Handler 331 | 332 | .weak DMA1_Stream6_IRQHandler 333 | .thumb_set DMA1_Stream6_IRQHandler,Default_Handler 334 | 335 | .weak ADC_IRQHandler 336 | .thumb_set ADC_IRQHandler,Default_Handler 337 | 338 | .weak EXTI9_5_IRQHandler 339 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 340 | 341 | .weak TIM1_BRK_TIM9_IRQHandler 342 | .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler 343 | 344 | .weak TIM1_UP_IRQHandler 345 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 346 | 347 | .weak TIM1_TRG_COM_TIM11_IRQHandler 348 | .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler 349 | 350 | .weak TIM1_CC_IRQHandler 351 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 352 | 353 | .weak I2C1_EV_IRQHandler 354 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 355 | 356 | .weak I2C1_ER_IRQHandler 357 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 358 | 359 | .weak I2C2_EV_IRQHandler 360 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 361 | 362 | .weak I2C2_ER_IRQHandler 363 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 364 | 365 | .weak SPI1_IRQHandler 366 | .thumb_set SPI1_IRQHandler,Default_Handler 367 | 368 | .weak SPI2_IRQHandler 369 | .thumb_set SPI2_IRQHandler,Default_Handler 370 | 371 | .weak USART1_IRQHandler 372 | .thumb_set USART1_IRQHandler,Default_Handler 373 | 374 | .weak USART2_IRQHandler 375 | .thumb_set USART2_IRQHandler,Default_Handler 376 | 377 | .weak EXTI15_10_IRQHandler 378 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 379 | 380 | .weak RTC_Alarm_IRQHandler 381 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 382 | 383 | .weak DMA1_Stream7_IRQHandler 384 | .thumb_set DMA1_Stream7_IRQHandler,Default_Handler 385 | 386 | .weak TIM5_IRQHandler 387 | .thumb_set TIM5_IRQHandler,Default_Handler 388 | 389 | .weak TIM6_DAC_IRQHandler 390 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 391 | 392 | .weak DMA2_Stream0_IRQHandler 393 | .thumb_set DMA2_Stream0_IRQHandler,Default_Handler 394 | 395 | .weak DMA2_Stream1_IRQHandler 396 | .thumb_set DMA2_Stream1_IRQHandler,Default_Handler 397 | 398 | .weak DMA2_Stream2_IRQHandler 399 | .thumb_set DMA2_Stream2_IRQHandler,Default_Handler 400 | 401 | .weak DMA2_Stream3_IRQHandler 402 | .thumb_set DMA2_Stream3_IRQHandler,Default_Handler 403 | 404 | .weak DMA2_Stream4_IRQHandler 405 | .thumb_set DMA2_Stream4_IRQHandler,Default_Handler 406 | 407 | .weak DMA2_Stream5_IRQHandler 408 | .thumb_set DMA2_Stream5_IRQHandler,Default_Handler 409 | 410 | .weak DMA2_Stream6_IRQHandler 411 | .thumb_set DMA2_Stream6_IRQHandler,Default_Handler 412 | 413 | .weak DMA2_Stream7_IRQHandler 414 | .thumb_set DMA2_Stream7_IRQHandler,Default_Handler 415 | 416 | .weak USART6_IRQHandler 417 | .thumb_set USART6_IRQHandler,Default_Handler 418 | 419 | .weak RNG_IRQHandler 420 | .thumb_set RNG_IRQHandler,Default_Handler 421 | 422 | .weak FPU_IRQHandler 423 | .thumb_set FPU_IRQHandler,Default_Handler 424 | 425 | .weak SPI5_IRQHandler 426 | .thumb_set SPI5_IRQHandler,Default_Handler 427 | 428 | .weak FMPI2C1_EV_IRQHandler 429 | .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler 430 | 431 | .weak FMPI2C1_ER_IRQHandler 432 | .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler 433 | 434 | .weak LPTIM1_IRQHandler 435 | .thumb_set LPTIM1_IRQHandler,Default_Handler 436 | -------------------------------------------------------------------------------- /core/system_stm32f4xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f4xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 22 | ****************************************************************************** 23 | * @attention 24 | * 25 | * Copyright (c) 2017 STMicroelectronics. 26 | * All rights reserved. 27 | * 28 | * This software is licensed under terms that can be found in the LICENSE file 29 | * in the root directory of this software component. 30 | * If no LICENSE file comes with this software, it is provided AS-IS. 31 | * 32 | ****************************************************************************** 33 | */ 34 | 35 | /** @addtogroup CMSIS 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup stm32f4xx_system 40 | * @{ 41 | */ 42 | 43 | /** @addtogroup STM32F4xx_System_Private_Includes 44 | * @{ 45 | */ 46 | 47 | 48 | #include "stm32f4xx.h" 49 | 50 | #if !defined (HSE_VALUE) 51 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ 52 | #endif /* HSE_VALUE */ 53 | 54 | #if !defined (HSI_VALUE) 55 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 56 | #endif /* HSI_VALUE */ 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 63 | * @{ 64 | */ 65 | 66 | /** 67 | * @} 68 | */ 69 | 70 | /** @addtogroup STM32F4xx_System_Private_Defines 71 | * @{ 72 | */ 73 | 74 | /************************* Miscellaneous Configuration ************************/ 75 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ 76 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 77 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 78 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 79 | /* #define DATA_IN_ExtSRAM */ 80 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ 81 | STM32F412Zx || STM32F412Vx */ 82 | 83 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 84 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 85 | /* #define DATA_IN_ExtSDRAM */ 86 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ 87 | STM32F479xx */ 88 | 89 | /* Note: Following vector table addresses must be defined in line with linker 90 | configuration. */ 91 | /*!< Uncomment the following line if you need to relocate the vector table 92 | anywhere in Flash or Sram, else the vector table is kept at the automatic 93 | remap of boot address selected */ 94 | /* #define USER_VECT_TAB_ADDRESS */ 95 | 96 | #if defined(USER_VECT_TAB_ADDRESS) 97 | /*!< Uncomment the following line if you need to relocate your vector Table 98 | in Sram else user remap will be done in Flash. */ 99 | /* #define VECT_TAB_SRAM */ 100 | #if defined(VECT_TAB_SRAM) 101 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 102 | This value must be a multiple of 0x200. */ 103 | #else 104 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 105 | This value must be a multiple of 0x200. */ 106 | #endif /* VECT_TAB_SRAM */ 107 | #if !defined(VECT_TAB_OFFSET) 108 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. 109 | This value must be a multiple of 0x200. */ 110 | #endif /* VECT_TAB_OFFSET */ 111 | #endif /* USER_VECT_TAB_ADDRESS */ 112 | /******************************************************************************/ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /** @addtogroup STM32F4xx_System_Private_Macros 119 | * @{ 120 | */ 121 | 122 | /** 123 | * @} 124 | */ 125 | 126 | /** @addtogroup STM32F4xx_System_Private_Variables 127 | * @{ 128 | */ 129 | /* This variable is updated in three ways: 130 | 1) by calling CMSIS function SystemCoreClockUpdate() 131 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 132 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 133 | Note: If you use this function to configure the system clock; then there 134 | is no need to call the 2 first functions listed above, since SystemCoreClock 135 | variable is updated automatically. 136 | */ 137 | uint32_t SystemCoreClock = 16000000; 138 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 139 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 140 | /** 141 | * @} 142 | */ 143 | 144 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes 145 | * @{ 146 | */ 147 | 148 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 149 | static void SystemInit_ExtMemCtl(void); 150 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /** @addtogroup STM32F4xx_System_Private_Functions 157 | * @{ 158 | */ 159 | 160 | /** 161 | * @brief Setup the microcontroller system 162 | * Initialize the FPU setting, vector table location and External memory 163 | * configuration. 164 | * @param None 165 | * @retval None 166 | */ 167 | void SystemInit(void) 168 | { 169 | /* FPU settings ------------------------------------------------------------*/ 170 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 171 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 172 | #endif 173 | 174 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 175 | SystemInit_ExtMemCtl(); 176 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 177 | 178 | /* Configure the Vector Table location -------------------------------------*/ 179 | #if defined(USER_VECT_TAB_ADDRESS) 180 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 181 | #endif /* USER_VECT_TAB_ADDRESS */ 182 | } 183 | 184 | /** 185 | * @brief Update SystemCoreClock variable according to Clock Register Values. 186 | * The SystemCoreClock variable contains the core clock (HCLK), it can 187 | * be used by the user application to setup the SysTick timer or configure 188 | * other parameters. 189 | * 190 | * @note Each time the core clock (HCLK) changes, this function must be called 191 | * to update SystemCoreClock variable value. Otherwise, any configuration 192 | * based on this variable will be incorrect. 193 | * 194 | * @note - The system frequency computed by this function is not the real 195 | * frequency in the chip. It is calculated based on the predefined 196 | * constant and the selected clock source: 197 | * 198 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 199 | * 200 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 201 | * 202 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 203 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 204 | * 205 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 206 | * 16 MHz) but the real value may vary depending on the variations 207 | * in voltage and temperature. 208 | * 209 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value 210 | * depends on the application requirements), user has to ensure that HSE_VALUE 211 | * is same as the real frequency of the crystal used. Otherwise, this function 212 | * may have wrong result. 213 | * 214 | * - The result of this function could be not correct when using fractional 215 | * value for HSE crystal. 216 | * 217 | * @param None 218 | * @retval None 219 | */ 220 | void SystemCoreClockUpdate(void) 221 | { 222 | uint32_t tmp, pllvco, pllp, pllsource, pllm; 223 | 224 | /* Get SYSCLK source -------------------------------------------------------*/ 225 | tmp = RCC->CFGR & RCC_CFGR_SWS; 226 | 227 | switch (tmp) 228 | { 229 | case 0x00: /* HSI used as system clock source */ 230 | SystemCoreClock = HSI_VALUE; 231 | break; 232 | case 0x04: /* HSE used as system clock source */ 233 | SystemCoreClock = HSE_VALUE; 234 | break; 235 | case 0x08: /* PLL used as system clock source */ 236 | 237 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 238 | SYSCLK = PLL_VCO / PLL_P 239 | */ 240 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 241 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 242 | 243 | if (pllsource != 0) 244 | { 245 | /* HSE used as PLL clock source */ 246 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 247 | } 248 | else 249 | { 250 | /* HSI used as PLL clock source */ 251 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 252 | } 253 | 254 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 255 | SystemCoreClock = pllvco/pllp; 256 | break; 257 | default: 258 | SystemCoreClock = HSI_VALUE; 259 | break; 260 | } 261 | /* Compute HCLK frequency --------------------------------------------------*/ 262 | /* Get HCLK prescaler */ 263 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 264 | /* HCLK frequency */ 265 | SystemCoreClock >>= tmp; 266 | } 267 | 268 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) 269 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 270 | || defined(STM32F469xx) || defined(STM32F479xx) 271 | /** 272 | * @brief Setup the external memory controller. 273 | * Called in startup_stm32f4xx.s before jump to main. 274 | * This function configures the external memories (SRAM/SDRAM) 275 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 276 | * @param None 277 | * @retval None 278 | */ 279 | void SystemInit_ExtMemCtl(void) 280 | { 281 | __IO uint32_t tmp = 0x00; 282 | 283 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 284 | register __IO uint32_t index; 285 | 286 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ 287 | RCC->AHB1ENR |= 0x000001F8; 288 | 289 | /* Delay after an RCC peripheral clock enabling */ 290 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 291 | 292 | /* Connect PDx pins to FMC Alternate function */ 293 | GPIOD->AFR[0] = 0x00CCC0CC; 294 | GPIOD->AFR[1] = 0xCCCCCCCC; 295 | /* Configure PDx pins in Alternate function mode */ 296 | GPIOD->MODER = 0xAAAA0A8A; 297 | /* Configure PDx pins speed to 100 MHz */ 298 | GPIOD->OSPEEDR = 0xFFFF0FCF; 299 | /* Configure PDx pins Output type to push-pull */ 300 | GPIOD->OTYPER = 0x00000000; 301 | /* No pull-up, pull-down for PDx pins */ 302 | GPIOD->PUPDR = 0x00000000; 303 | 304 | /* Connect PEx pins to FMC Alternate function */ 305 | GPIOE->AFR[0] = 0xC00CC0CC; 306 | GPIOE->AFR[1] = 0xCCCCCCCC; 307 | /* Configure PEx pins in Alternate function mode */ 308 | GPIOE->MODER = 0xAAAA828A; 309 | /* Configure PEx pins speed to 100 MHz */ 310 | GPIOE->OSPEEDR = 0xFFFFC3CF; 311 | /* Configure PEx pins Output type to push-pull */ 312 | GPIOE->OTYPER = 0x00000000; 313 | /* No pull-up, pull-down for PEx pins */ 314 | GPIOE->PUPDR = 0x00000000; 315 | 316 | /* Connect PFx pins to FMC Alternate function */ 317 | GPIOF->AFR[0] = 0xCCCCCCCC; 318 | GPIOF->AFR[1] = 0xCCCCCCCC; 319 | /* Configure PFx pins in Alternate function mode */ 320 | GPIOF->MODER = 0xAA800AAA; 321 | /* Configure PFx pins speed to 50 MHz */ 322 | GPIOF->OSPEEDR = 0xAA800AAA; 323 | /* Configure PFx pins Output type to push-pull */ 324 | GPIOF->OTYPER = 0x00000000; 325 | /* No pull-up, pull-down for PFx pins */ 326 | GPIOF->PUPDR = 0x00000000; 327 | 328 | /* Connect PGx pins to FMC Alternate function */ 329 | GPIOG->AFR[0] = 0xCCCCCCCC; 330 | GPIOG->AFR[1] = 0xCCCCCCCC; 331 | /* Configure PGx pins in Alternate function mode */ 332 | GPIOG->MODER = 0xAAAAAAAA; 333 | /* Configure PGx pins speed to 50 MHz */ 334 | GPIOG->OSPEEDR = 0xAAAAAAAA; 335 | /* Configure PGx pins Output type to push-pull */ 336 | GPIOG->OTYPER = 0x00000000; 337 | /* No pull-up, pull-down for PGx pins */ 338 | GPIOG->PUPDR = 0x00000000; 339 | 340 | /* Connect PHx pins to FMC Alternate function */ 341 | GPIOH->AFR[0] = 0x00C0CC00; 342 | GPIOH->AFR[1] = 0xCCCCCCCC; 343 | /* Configure PHx pins in Alternate function mode */ 344 | GPIOH->MODER = 0xAAAA08A0; 345 | /* Configure PHx pins speed to 50 MHz */ 346 | GPIOH->OSPEEDR = 0xAAAA08A0; 347 | /* Configure PHx pins Output type to push-pull */ 348 | GPIOH->OTYPER = 0x00000000; 349 | /* No pull-up, pull-down for PHx pins */ 350 | GPIOH->PUPDR = 0x00000000; 351 | 352 | /* Connect PIx pins to FMC Alternate function */ 353 | GPIOI->AFR[0] = 0xCCCCCCCC; 354 | GPIOI->AFR[1] = 0x00000CC0; 355 | /* Configure PIx pins in Alternate function mode */ 356 | GPIOI->MODER = 0x0028AAAA; 357 | /* Configure PIx pins speed to 50 MHz */ 358 | GPIOI->OSPEEDR = 0x0028AAAA; 359 | /* Configure PIx pins Output type to push-pull */ 360 | GPIOI->OTYPER = 0x00000000; 361 | /* No pull-up, pull-down for PIx pins */ 362 | GPIOI->PUPDR = 0x00000000; 363 | 364 | /*-- FMC Configuration -------------------------------------------------------*/ 365 | /* Enable the FMC interface clock */ 366 | RCC->AHB3ENR |= 0x00000001; 367 | /* Delay after an RCC peripheral clock enabling */ 368 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 369 | 370 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 371 | FMC_Bank5_6->SDTR[0] = 0x01115351; 372 | 373 | /* SDRAM initialization sequence */ 374 | /* Clock enable command */ 375 | FMC_Bank5_6->SDCMR = 0x00000011; 376 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 377 | while((tmpreg != 0) && (timeout-- > 0)) 378 | { 379 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 380 | } 381 | 382 | /* Delay */ 383 | for (index = 0; index<1000; index++); 384 | 385 | /* PALL command */ 386 | FMC_Bank5_6->SDCMR = 0x00000012; 387 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 388 | timeout = 0xFFFF; 389 | while((tmpreg != 0) && (timeout-- > 0)) 390 | { 391 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 392 | } 393 | 394 | /* Auto refresh command */ 395 | FMC_Bank5_6->SDCMR = 0x00000073; 396 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 397 | timeout = 0xFFFF; 398 | while((tmpreg != 0) && (timeout-- > 0)) 399 | { 400 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 401 | } 402 | 403 | /* MRD register program */ 404 | FMC_Bank5_6->SDCMR = 0x00046014; 405 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 406 | timeout = 0xFFFF; 407 | while((tmpreg != 0) && (timeout-- > 0)) 408 | { 409 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 410 | } 411 | 412 | /* Set refresh count */ 413 | tmpreg = FMC_Bank5_6->SDRTR; 414 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 415 | 416 | /* Disable write protection */ 417 | tmpreg = FMC_Bank5_6->SDCR[0]; 418 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 419 | 420 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 421 | /* Configure and enable Bank1_SRAM2 */ 422 | FMC_Bank1->BTCR[2] = 0x00001011; 423 | FMC_Bank1->BTCR[3] = 0x00000201; 424 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 425 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 426 | #if defined(STM32F469xx) || defined(STM32F479xx) 427 | /* Configure and enable Bank1_SRAM2 */ 428 | FMC_Bank1->BTCR[2] = 0x00001091; 429 | FMC_Bank1->BTCR[3] = 0x00110212; 430 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 431 | #endif /* STM32F469xx || STM32F479xx */ 432 | 433 | (void)(tmp); 434 | } 435 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 436 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 437 | /** 438 | * @brief Setup the external memory controller. 439 | * Called in startup_stm32f4xx.s before jump to main. 440 | * This function configures the external memories (SRAM/SDRAM) 441 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 442 | * @param None 443 | * @retval None 444 | */ 445 | void SystemInit_ExtMemCtl(void) 446 | { 447 | __IO uint32_t tmp = 0x00; 448 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 449 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 450 | #if defined (DATA_IN_ExtSDRAM) 451 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 452 | register __IO uint32_t index; 453 | 454 | #if defined(STM32F446xx) 455 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface 456 | clock */ 457 | RCC->AHB1ENR |= 0x0000007D; 458 | #else 459 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 460 | clock */ 461 | RCC->AHB1ENR |= 0x000001F8; 462 | #endif /* STM32F446xx */ 463 | /* Delay after an RCC peripheral clock enabling */ 464 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 465 | 466 | #if defined(STM32F446xx) 467 | /* Connect PAx pins to FMC Alternate function */ 468 | GPIOA->AFR[0] |= 0xC0000000; 469 | GPIOA->AFR[1] |= 0x00000000; 470 | /* Configure PDx pins in Alternate function mode */ 471 | GPIOA->MODER |= 0x00008000; 472 | /* Configure PDx pins speed to 50 MHz */ 473 | GPIOA->OSPEEDR |= 0x00008000; 474 | /* Configure PDx pins Output type to push-pull */ 475 | GPIOA->OTYPER |= 0x00000000; 476 | /* No pull-up, pull-down for PDx pins */ 477 | GPIOA->PUPDR |= 0x00000000; 478 | 479 | /* Connect PCx pins to FMC Alternate function */ 480 | GPIOC->AFR[0] |= 0x00CC0000; 481 | GPIOC->AFR[1] |= 0x00000000; 482 | /* Configure PDx pins in Alternate function mode */ 483 | GPIOC->MODER |= 0x00000A00; 484 | /* Configure PDx pins speed to 50 MHz */ 485 | GPIOC->OSPEEDR |= 0x00000A00; 486 | /* Configure PDx pins Output type to push-pull */ 487 | GPIOC->OTYPER |= 0x00000000; 488 | /* No pull-up, pull-down for PDx pins */ 489 | GPIOC->PUPDR |= 0x00000000; 490 | #endif /* STM32F446xx */ 491 | 492 | /* Connect PDx pins to FMC Alternate function */ 493 | GPIOD->AFR[0] = 0x000000CC; 494 | GPIOD->AFR[1] = 0xCC000CCC; 495 | /* Configure PDx pins in Alternate function mode */ 496 | GPIOD->MODER = 0xA02A000A; 497 | /* Configure PDx pins speed to 50 MHz */ 498 | GPIOD->OSPEEDR = 0xA02A000A; 499 | /* Configure PDx pins Output type to push-pull */ 500 | GPIOD->OTYPER = 0x00000000; 501 | /* No pull-up, pull-down for PDx pins */ 502 | GPIOD->PUPDR = 0x00000000; 503 | 504 | /* Connect PEx pins to FMC Alternate function */ 505 | GPIOE->AFR[0] = 0xC00000CC; 506 | GPIOE->AFR[1] = 0xCCCCCCCC; 507 | /* Configure PEx pins in Alternate function mode */ 508 | GPIOE->MODER = 0xAAAA800A; 509 | /* Configure PEx pins speed to 50 MHz */ 510 | GPIOE->OSPEEDR = 0xAAAA800A; 511 | /* Configure PEx pins Output type to push-pull */ 512 | GPIOE->OTYPER = 0x00000000; 513 | /* No pull-up, pull-down for PEx pins */ 514 | GPIOE->PUPDR = 0x00000000; 515 | 516 | /* Connect PFx pins to FMC Alternate function */ 517 | GPIOF->AFR[0] = 0xCCCCCCCC; 518 | GPIOF->AFR[1] = 0xCCCCCCCC; 519 | /* Configure PFx pins in Alternate function mode */ 520 | GPIOF->MODER = 0xAA800AAA; 521 | /* Configure PFx pins speed to 50 MHz */ 522 | GPIOF->OSPEEDR = 0xAA800AAA; 523 | /* Configure PFx pins Output type to push-pull */ 524 | GPIOF->OTYPER = 0x00000000; 525 | /* No pull-up, pull-down for PFx pins */ 526 | GPIOF->PUPDR = 0x00000000; 527 | 528 | /* Connect PGx pins to FMC Alternate function */ 529 | GPIOG->AFR[0] = 0xCCCCCCCC; 530 | GPIOG->AFR[1] = 0xCCCCCCCC; 531 | /* Configure PGx pins in Alternate function mode */ 532 | GPIOG->MODER = 0xAAAAAAAA; 533 | /* Configure PGx pins speed to 50 MHz */ 534 | GPIOG->OSPEEDR = 0xAAAAAAAA; 535 | /* Configure PGx pins Output type to push-pull */ 536 | GPIOG->OTYPER = 0x00000000; 537 | /* No pull-up, pull-down for PGx pins */ 538 | GPIOG->PUPDR = 0x00000000; 539 | 540 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 541 | || defined(STM32F469xx) || defined(STM32F479xx) 542 | /* Connect PHx pins to FMC Alternate function */ 543 | GPIOH->AFR[0] = 0x00C0CC00; 544 | GPIOH->AFR[1] = 0xCCCCCCCC; 545 | /* Configure PHx pins in Alternate function mode */ 546 | GPIOH->MODER = 0xAAAA08A0; 547 | /* Configure PHx pins speed to 50 MHz */ 548 | GPIOH->OSPEEDR = 0xAAAA08A0; 549 | /* Configure PHx pins Output type to push-pull */ 550 | GPIOH->OTYPER = 0x00000000; 551 | /* No pull-up, pull-down for PHx pins */ 552 | GPIOH->PUPDR = 0x00000000; 553 | 554 | /* Connect PIx pins to FMC Alternate function */ 555 | GPIOI->AFR[0] = 0xCCCCCCCC; 556 | GPIOI->AFR[1] = 0x00000CC0; 557 | /* Configure PIx pins in Alternate function mode */ 558 | GPIOI->MODER = 0x0028AAAA; 559 | /* Configure PIx pins speed to 50 MHz */ 560 | GPIOI->OSPEEDR = 0x0028AAAA; 561 | /* Configure PIx pins Output type to push-pull */ 562 | GPIOI->OTYPER = 0x00000000; 563 | /* No pull-up, pull-down for PIx pins */ 564 | GPIOI->PUPDR = 0x00000000; 565 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 566 | 567 | /*-- FMC Configuration -------------------------------------------------------*/ 568 | /* Enable the FMC interface clock */ 569 | RCC->AHB3ENR |= 0x00000001; 570 | /* Delay after an RCC peripheral clock enabling */ 571 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 572 | 573 | /* Configure and enable SDRAM bank1 */ 574 | #if defined(STM32F446xx) 575 | FMC_Bank5_6->SDCR[0] = 0x00001954; 576 | #else 577 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 578 | #endif /* STM32F446xx */ 579 | FMC_Bank5_6->SDTR[0] = 0x01115351; 580 | 581 | /* SDRAM initialization sequence */ 582 | /* Clock enable command */ 583 | FMC_Bank5_6->SDCMR = 0x00000011; 584 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 585 | while((tmpreg != 0) && (timeout-- > 0)) 586 | { 587 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 588 | } 589 | 590 | /* Delay */ 591 | for (index = 0; index<1000; index++); 592 | 593 | /* PALL command */ 594 | FMC_Bank5_6->SDCMR = 0x00000012; 595 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 596 | timeout = 0xFFFF; 597 | while((tmpreg != 0) && (timeout-- > 0)) 598 | { 599 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 600 | } 601 | 602 | /* Auto refresh command */ 603 | #if defined(STM32F446xx) 604 | FMC_Bank5_6->SDCMR = 0x000000F3; 605 | #else 606 | FMC_Bank5_6->SDCMR = 0x00000073; 607 | #endif /* STM32F446xx */ 608 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 609 | timeout = 0xFFFF; 610 | while((tmpreg != 0) && (timeout-- > 0)) 611 | { 612 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 613 | } 614 | 615 | /* MRD register program */ 616 | #if defined(STM32F446xx) 617 | FMC_Bank5_6->SDCMR = 0x00044014; 618 | #else 619 | FMC_Bank5_6->SDCMR = 0x00046014; 620 | #endif /* STM32F446xx */ 621 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 622 | timeout = 0xFFFF; 623 | while((tmpreg != 0) && (timeout-- > 0)) 624 | { 625 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 626 | } 627 | 628 | /* Set refresh count */ 629 | tmpreg = FMC_Bank5_6->SDRTR; 630 | #if defined(STM32F446xx) 631 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); 632 | #else 633 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 634 | #endif /* STM32F446xx */ 635 | 636 | /* Disable write protection */ 637 | tmpreg = FMC_Bank5_6->SDCR[0]; 638 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 639 | #endif /* DATA_IN_ExtSDRAM */ 640 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 641 | 642 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 643 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 644 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 645 | 646 | #if defined(DATA_IN_ExtSRAM) 647 | /*-- GPIOs Configuration -----------------------------------------------------*/ 648 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 649 | RCC->AHB1ENR |= 0x00000078; 650 | /* Delay after an RCC peripheral clock enabling */ 651 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); 652 | 653 | /* Connect PDx pins to FMC Alternate function */ 654 | GPIOD->AFR[0] = 0x00CCC0CC; 655 | GPIOD->AFR[1] = 0xCCCCCCCC; 656 | /* Configure PDx pins in Alternate function mode */ 657 | GPIOD->MODER = 0xAAAA0A8A; 658 | /* Configure PDx pins speed to 100 MHz */ 659 | GPIOD->OSPEEDR = 0xFFFF0FCF; 660 | /* Configure PDx pins Output type to push-pull */ 661 | GPIOD->OTYPER = 0x00000000; 662 | /* No pull-up, pull-down for PDx pins */ 663 | GPIOD->PUPDR = 0x00000000; 664 | 665 | /* Connect PEx pins to FMC Alternate function */ 666 | GPIOE->AFR[0] = 0xC00CC0CC; 667 | GPIOE->AFR[1] = 0xCCCCCCCC; 668 | /* Configure PEx pins in Alternate function mode */ 669 | GPIOE->MODER = 0xAAAA828A; 670 | /* Configure PEx pins speed to 100 MHz */ 671 | GPIOE->OSPEEDR = 0xFFFFC3CF; 672 | /* Configure PEx pins Output type to push-pull */ 673 | GPIOE->OTYPER = 0x00000000; 674 | /* No pull-up, pull-down for PEx pins */ 675 | GPIOE->PUPDR = 0x00000000; 676 | 677 | /* Connect PFx pins to FMC Alternate function */ 678 | GPIOF->AFR[0] = 0x00CCCCCC; 679 | GPIOF->AFR[1] = 0xCCCC0000; 680 | /* Configure PFx pins in Alternate function mode */ 681 | GPIOF->MODER = 0xAA000AAA; 682 | /* Configure PFx pins speed to 100 MHz */ 683 | GPIOF->OSPEEDR = 0xFF000FFF; 684 | /* Configure PFx pins Output type to push-pull */ 685 | GPIOF->OTYPER = 0x00000000; 686 | /* No pull-up, pull-down for PFx pins */ 687 | GPIOF->PUPDR = 0x00000000; 688 | 689 | /* Connect PGx pins to FMC Alternate function */ 690 | GPIOG->AFR[0] = 0x00CCCCCC; 691 | GPIOG->AFR[1] = 0x000000C0; 692 | /* Configure PGx pins in Alternate function mode */ 693 | GPIOG->MODER = 0x00085AAA; 694 | /* Configure PGx pins speed to 100 MHz */ 695 | GPIOG->OSPEEDR = 0x000CAFFF; 696 | /* Configure PGx pins Output type to push-pull */ 697 | GPIOG->OTYPER = 0x00000000; 698 | /* No pull-up, pull-down for PGx pins */ 699 | GPIOG->PUPDR = 0x00000000; 700 | 701 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ 702 | /* Enable the FMC/FSMC interface clock */ 703 | RCC->AHB3ENR |= 0x00000001; 704 | 705 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 706 | /* Delay after an RCC peripheral clock enabling */ 707 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 708 | /* Configure and enable Bank1_SRAM2 */ 709 | FMC_Bank1->BTCR[2] = 0x00001011; 710 | FMC_Bank1->BTCR[3] = 0x00000201; 711 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 712 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 713 | #if defined(STM32F469xx) || defined(STM32F479xx) 714 | /* Delay after an RCC peripheral clock enabling */ 715 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 716 | /* Configure and enable Bank1_SRAM2 */ 717 | FMC_Bank1->BTCR[2] = 0x00001091; 718 | FMC_Bank1->BTCR[3] = 0x00110212; 719 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 720 | #endif /* STM32F469xx || STM32F479xx */ 721 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ 722 | || defined(STM32F412Zx) || defined(STM32F412Vx) 723 | /* Delay after an RCC peripheral clock enabling */ 724 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); 725 | /* Configure and enable Bank1_SRAM2 */ 726 | FSMC_Bank1->BTCR[2] = 0x00001011; 727 | FSMC_Bank1->BTCR[3] = 0x00000201; 728 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; 729 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ 730 | 731 | #endif /* DATA_IN_ExtSRAM */ 732 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ 733 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ 734 | (void)(tmp); 735 | } 736 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ 737 | /** 738 | * @} 739 | */ 740 | 741 | /** 742 | * @} 743 | */ 744 | 745 | /** 746 | * @} 747 | */ 748 | --------------------------------------------------------------------------------