├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── linker_script.ld ├── main.c ├── startup.c ├── syscalls.c ├── usart.c ├── usart.h └── vendor └── CMSIS ├── CMSIS └── Core │ └── Include │ ├── cmsis_compiler.h │ ├── cmsis_gcc.h │ ├── cmsis_version.h │ ├── core_cm4.h │ └── mpu_armv7.h ├── Device └── ST │ └── STM32F4 │ ├── Include │ ├── stm32f410rx.h │ ├── stm32f4xx.h │ └── system_stm32f4xx.h │ ├── LICENSE.md │ ├── README.md │ └── Source │ └── Templates │ └── system_stm32f4xx.c ├── LICENSE.txt └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | # Editor settings 2 | .vscode 3 | .project 4 | .settings 5 | 6 | # Build putput 7 | *.o 8 | *.elf 9 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Kristian Klein-Wengel 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | CC=arm-none-eabi-gcc 2 | CFLAGS=-mcpu=cortex-m4 -mthumb --specs=nano.specs 3 | CPPFLAGS=-DSTM32F410Rx \ 4 | -Ivendor/CMSIS/Device/ST/STM32F4/Include \ 5 | -Ivendor/CMSIS/CMSIS/Core/Include 6 | 7 | LINKER_FILE=linker_script.ld 8 | LDFLAGS=-T $(LINKER_FILE) -u _printf_float 9 | 10 | BINARY = blink.elf 11 | 12 | PROGRAMMER = openocd 13 | PROGRAMMER_FLAGS = -f interface/stlink.cfg -f target/stm32f4x.cfg 14 | 15 | all: $(BINARY) 16 | 17 | $(BINARY): main.o startup.o system_stm32f4xx.o syscalls.o usart.o 18 | $(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) $^ -o $(BINARY) 19 | 20 | main.o: main.c 21 | $(CC) $(CFLAGS) $(CPPFLAGS) $^ -c 22 | 23 | startup.o: startup.c 24 | $(CC) $(CFLAGS) $(CPPFLAGS) $^ -c 25 | 26 | system_stm32f4xx.o: vendor/CMSIS/Device/ST/STM32F4/Source/Templates/system_stm32f4xx.c 27 | $(CC) $(CFLAGS) $(CPPFLAGS) $^ -c 28 | 29 | syscalls.o: syscalls.c 30 | $(CC) $(CFLAGS) $(CPPFLAGS) $^ -c 31 | 32 | usart.o: usart.c 33 | $(CC) $(CFLAGS) $(CPPFLAGS) $^ -c 34 | 35 | .PHONY: clean 36 | clean: 37 | rm -f *.o *.elf 38 | 39 | flash: $(BINARY) 40 | $(PROGRAMMER) $(PROGRAMMER_FLAGS) -c "program $(BINARY) verify reset exit" -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32 without CubeIDE 2 | 3 | Code for the blog post series "STM32 without CubeIDE" at https://kleinembedded.com 4 | 5 | - [Part 1: The bare necessities](https://kleinembedded.com/stm32-without-cubeide-part-1-the-bare-necessities) 6 | - [Part 2: CMSIS, make and clock configuration](https://kleinembedded.com/stm32-without-cubeide-part-2-cmsis-make-and-clock-configuration) 7 | - [Part 3: The C Standard Library and printf](https://kleinembedded.com/stm32-without-cubeide-part-3-the-c-standard-library-and-printf) -------------------------------------------------------------------------------- /linker_script.ld: -------------------------------------------------------------------------------- 1 | ENTRY(reset_handler) 2 | 3 | MEMORY 4 | { 5 | FLASH (rx): ORIGIN = 0x08000000, LENGTH = 128K 6 | SRAM (rwx): ORIGIN = 0x20000000, LENGTH = 32K 7 | } 8 | 9 | SECTIONS 10 | { 11 | .isr_vector : 12 | { 13 | KEEP(*(.isr_vector)) 14 | } >FLASH 15 | 16 | .text : 17 | { 18 | . = ALIGN(4); 19 | 20 | *(.text) 21 | *(.text.*) 22 | *(.rodata) 23 | *(.rodata.*) 24 | KEEP(*(.init)) 25 | KEEP(*(.fini)) 26 | *(.eh_frame) 27 | *(.ARM.exidx) 28 | 29 | . = ALIGN(4); 30 | _etext = .; 31 | } >FLASH 32 | 33 | _sidata = LOADADDR(.data); 34 | 35 | .data : 36 | { 37 | . = ALIGN(4); 38 | _sdata = .; 39 | 40 | *(.data) 41 | *(.data.*) 42 | KEEP(*(.init_array)) 43 | KEEP(*(.fini_array)) 44 | 45 | . = ALIGN(4); 46 | _edata = .; 47 | } >SRAM AT> FLASH 48 | 49 | .bss : 50 | { 51 | . = ALIGN(4); 52 | _sbss = .; 53 | __bss_start__ = _sbss; 54 | 55 | *(.bss) 56 | *(.bss.*) 57 | 58 | . = ALIGN(4); 59 | _ebss = .; 60 | __bss_end__ = _ebss; 61 | } >SRAM 62 | } 63 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "stm32f4xx.h" 4 | #include "usart.h" 5 | 6 | #define LED_PIN 5 7 | 8 | void clock_init(); 9 | void delay_ms(uint32_t milliseconds); 10 | 11 | volatile uint32_t ticks; 12 | 13 | void main(void) 14 | { 15 | clock_init(); 16 | SystemCoreClockUpdate(); // Update the internal clock frequency variable 17 | 18 | RCC->AHB1ENR |= (1 << RCC_AHB1ENR_GPIOAEN_Pos); 19 | 20 | // do two dummy reads after enabling the peripheral clock, as per the errata 21 | volatile uint32_t dummy; 22 | dummy = RCC->AHB1ENR; 23 | dummy = RCC->AHB1ENR; 24 | 25 | GPIOA->MODER |= (1 << GPIO_MODER_MODER5_Pos); 26 | 27 | SysTick_Config(100000); 28 | __enable_irq(); 29 | 30 | usart_init(USART2); 31 | 32 | while(1) 33 | { 34 | GPIOA->ODR ^= (1 << LED_PIN); 35 | printf("[%.3f] Hello, World!\r\n", (float)ticks/1000.0); 36 | delay_ms(500); 37 | } 38 | } 39 | 40 | void clock_init() 41 | { 42 | /* By default HSI (16 MHz RC oscillator) is selected as system clock. 43 | * We want to use the HSE (8 MHz MCO from ST-LINK connected to OSC_IN) 44 | * through the PLL to get 100 MHz system clock. 45 | */ 46 | 47 | // Enable power controller and set voltage scale mode 1 48 | RCC->APB1ENR |= RCC_APB1ENR_PWREN_Msk; 49 | volatile uint32_t dummy; 50 | dummy = RCC->APB1ENR; 51 | dummy = RCC->APB1ENR; 52 | PWR->CR |= (0b11 << PWR_CR_VOS_Pos); 53 | 54 | // Configure flash controller for 3V3 supply and 100 MHz -> 3 wait states 55 | FLASH->ACR |= FLASH_ACR_LATENCY_3WS; 56 | 57 | // Set HSE bypass (to use external clock on OSC_IN, not a crystal) and enable HSE 58 | RCC->CR |= RCC_CR_HSEBYP_Msk | RCC_CR_HSEON_Msk; 59 | while (!(RCC->CR & RCC_CR_HSERDY_Msk)); 60 | 61 | // Configure PLL dividers and multiplier 62 | /* Input to PLL should be 1-2 MHz (preferably 2 MHz). Choosing M=4 gives 63 | * us 8 MHz / 4 = 2 MHz. 64 | * The output of the PLL should be 100-438 MHz, so setting the feedback 65 | * multiplier to 200 gives us 2 MHz * 200 = 400 MHz. 66 | * The system clock should be 100 MHz. Choosing P=4 gives us 67 | * 400 MHz / 4 = 100 MHz 68 | * 69 | * Since APB1 clock must not be more than 50 MHz, set the PPRE1 divider to 2. 70 | */ 71 | // Clear PLLM, PLLN and PLLP bits 72 | RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLM_Msk | RCC_PLLCFGR_PLLN_Msk | RCC_PLLCFGR_PLLP_Msk); 73 | 74 | // Set PLLM, PLLN and PLLP, and select HSE as PLL source 75 | RCC->PLLCFGR |= ((4 << RCC_PLLCFGR_PLLM_Pos) | (200 << RCC_PLLCFGR_PLLN_Pos) | (1 << RCC_PLLCFGR_PLLP_Pos) | (1 << RCC_PLLCFGR_PLLSRC_Pos)); 76 | 77 | // Set APB1 prescaler to 2 78 | RCC->CFGR |= (0b100 << RCC_CFGR_PPRE1_Pos); 79 | 80 | // Enable PLL and wait for ready 81 | RCC->CR |= RCC_CR_PLLON_Msk; 82 | while (! (RCC->CR & RCC_CR_PLLRDY_Msk)); 83 | 84 | // Select PLL output as system clock 85 | RCC->CFGR |= (RCC_CFGR_SW_PLL << RCC_CFGR_SW_Pos); 86 | while (! (RCC->CFGR & RCC_CFGR_SWS_PLL)); 87 | } 88 | 89 | void systick_handler() 90 | { 91 | ticks++; 92 | } 93 | 94 | void delay_ms(uint32_t milliseconds) 95 | { 96 | uint32_t start = ticks; 97 | uint32_t end = start + milliseconds; 98 | 99 | if (end < start) // overflow 100 | { 101 | while (ticks > start); // wait for ticks to wrap 102 | } 103 | 104 | while (ticks < end); 105 | } 106 | -------------------------------------------------------------------------------- /startup.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define SRAM_START (0x20000000U) 4 | #define SRAM_SIZE (32U * 1024U) 5 | #define SRAM_END (SRAM_START + SRAM_SIZE) 6 | #define STACK_POINTER_INIT_ADDRESS (SRAM_END) 7 | #define ISR_VECTOR_SIZE_WORDS 114 8 | 9 | void reset_handler(void); 10 | void default_handler(void); 11 | 12 | // Cortex-M system exceptions 13 | void nmi_handler(void) __attribute__((weak, alias("default_handler"))); 14 | void hard_fault_handler(void) __attribute__((weak, alias("default_handler"))); 15 | void bus_fault_handler(void) __attribute__((weak, alias("default_handler"))); 16 | void usage_fault_handler(void) __attribute__((weak, alias("default_handler"))); 17 | void svcall_handler(void) __attribute__((weak, alias("default_handler"))); 18 | void debug_monitor_handler(void) __attribute__((weak, alias("default_handler"))); 19 | void pendsv_handler(void) __attribute__((weak, alias("default_handler"))); 20 | void systick_handler(void) __attribute__((weak, alias("default_handler"))); 21 | 22 | // STM32F410RB interrupt handlers 23 | void wwdg_handler(void) __attribute__((weak, alias("default_handler"))); 24 | void pvd_handler(void) __attribute__((weak, alias("default_handler"))); 25 | void exti21_tamp_stamp_handler(void) __attribute__((weak, alias("default_handler"))); 26 | void exti22_rtc_wkup_handler(void) __attribute__((weak, alias("default_handler"))); 27 | void flash_handler(void) __attribute__((weak, alias("default_handler"))); 28 | void rcc_handler(void) __attribute__((weak, alias("default_handler"))); 29 | void exti0_handler(void) __attribute__((weak, alias("default_handler"))); 30 | void exti1_handler(void) __attribute__((weak, alias("default_handler"))); 31 | void exti2_handler(void) __attribute__((weak, alias("default_handler"))); 32 | void exti3_handler(void) __attribute__((weak, alias("default_handler"))); 33 | void exti4_handler(void) __attribute__((weak, alias("default_handler"))); 34 | void dma1_stream0_handler(void) __attribute__((weak, alias("default_handler"))); 35 | void dma1_stream1_handler(void) __attribute__((weak, alias("default_handler"))); 36 | void dma1_stream2_handler(void) __attribute__((weak, alias("default_handler"))); 37 | void dma1_stream3_handler(void) __attribute__((weak, alias("default_handler"))); 38 | void dma1_stream4_handler(void) __attribute__((weak, alias("default_handler"))); 39 | void dma1_stream5_handler(void) __attribute__((weak, alias("default_handler"))); 40 | void dma1_stream6_handler(void) __attribute__((weak, alias("default_handler"))); 41 | void adc_handler(void) __attribute__((weak, alias("default_handler"))); 42 | void exti9_5_handler(void) __attribute__((weak, alias("default_handler"))); 43 | void tim1_brk_tim9_handler(void) __attribute__((weak, alias("default_handler"))); 44 | void tim1_up_handler(void) __attribute__((weak, alias("default_handler"))); 45 | void tim1_trg_com_tim11_handler(void) __attribute__((weak, alias("default_handler"))); 46 | void tim1_cc_handler(void) __attribute__((weak, alias("default_handler"))); 47 | void i2c1_ev_handler(void) __attribute__((weak, alias("default_handler"))); 48 | void i2c1_er_handler(void) __attribute__((weak, alias("default_handler"))); 49 | void i2c2_ev_handler(void) __attribute__((weak, alias("default_handler"))); 50 | void i2c2_er_handler(void) __attribute__((weak, alias("default_handler"))); 51 | void spi1_handler(void) __attribute__((weak, alias("default_handler"))); 52 | void spi2_handler(void) __attribute__((weak, alias("default_handler"))); 53 | void usart1_handler(void) __attribute__((weak, alias("default_handler"))); 54 | void usart2_handler(void) __attribute__((weak, alias("default_handler"))); 55 | void exti15_10_handler(void) __attribute__((weak, alias("default_handler"))); 56 | void exti17_rtc_alarm_handler(void) __attribute__((weak, alias("default_handler"))); 57 | void dma1_stream7_handler(void) __attribute__((weak, alias("default_handler"))); 58 | void tim5_handler(void) __attribute__((weak, alias("default_handler"))); 59 | void tim6_dac_handler(void) __attribute__((weak, alias("default_handler"))); 60 | void dma2_stream0_handler(void) __attribute__((weak, alias("default_handler"))); 61 | void dma2_stream1_handler(void) __attribute__((weak, alias("default_handler"))); 62 | void dma2_stream2_handler(void) __attribute__((weak, alias("default_handler"))); 63 | void dma2_stream3_handler(void) __attribute__((weak, alias("default_handler"))); 64 | void dma2_stream4_handler(void) __attribute__((weak, alias("default_handler"))); 65 | void exti19_handler(void) __attribute__((weak, alias("default_handler"))); 66 | void dma2_stream5_handler(void) __attribute__((weak, alias("default_handler"))); 67 | void dma2_stream6_handler(void) __attribute__((weak, alias("default_handler"))); 68 | void dma2_stream7_handler(void) __attribute__((weak, alias("default_handler"))); 69 | void usart6_handler(void) __attribute__((weak, alias("default_handler"))); 70 | void exti20_handler(void) __attribute__((weak, alias("default_handler"))); 71 | void rng_handler(void) __attribute__((weak, alias("default_handler"))); 72 | void fpu_handler(void) __attribute__((weak, alias("default_handler"))); 73 | void spi5_handler(void) __attribute__((weak, alias("default_handler"))); 74 | void i2c4_ev_handler(void) __attribute__((weak, alias("default_handler"))); 75 | void i2c4_er_handler(void) __attribute__((weak, alias("default_handler"))); 76 | void lptim1_exti23_handler(void) __attribute__((weak, alias("default_handler"))); 77 | 78 | uint32_t isr_vector[ISR_VECTOR_SIZE_WORDS] __attribute__((section(".isr_vector"))) = { 79 | STACK_POINTER_INIT_ADDRESS, 80 | // Cortex-M system exceptions 81 | (uint32_t)&reset_handler, 82 | (uint32_t)&nmi_handler, 83 | (uint32_t)&hard_fault_handler, 84 | (uint32_t)&bus_fault_handler, 85 | (uint32_t)&usage_fault_handler, 86 | 0, 87 | 0, 88 | 0, 89 | 0, 90 | 0, 91 | (uint32_t)&svcall_handler, 92 | (uint32_t)&debug_monitor_handler, 93 | 0, 94 | (uint32_t)&pendsv_handler, 95 | (uint32_t)&systick_handler, 96 | // STM32F410 interrupt handlers 97 | (uint32_t)&wwdg_handler, 98 | (uint32_t)&pvd_handler, 99 | (uint32_t)&exti21_tamp_stamp_handler, 100 | (uint32_t)&exti22_rtc_wkup_handler, 101 | (uint32_t)&flash_handler, 102 | (uint32_t)&rcc_handler, 103 | (uint32_t)&exti0_handler, 104 | (uint32_t)&exti1_handler, 105 | (uint32_t)&exti2_handler, 106 | (uint32_t)&exti3_handler, 107 | (uint32_t)&exti4_handler, 108 | (uint32_t)&dma1_stream0_handler, 109 | (uint32_t)&dma1_stream1_handler, 110 | (uint32_t)&dma1_stream2_handler, 111 | (uint32_t)&dma1_stream3_handler, 112 | (uint32_t)&dma1_stream4_handler, 113 | (uint32_t)&dma1_stream5_handler, 114 | (uint32_t)&dma1_stream6_handler, 115 | (uint32_t)&adc_handler, 116 | 0, 117 | 0, 118 | 0, 119 | 0, 120 | (uint32_t)&exti9_5_handler, 121 | (uint32_t)&tim1_brk_tim9_handler, 122 | (uint32_t)&tim1_up_handler, 123 | (uint32_t)&tim1_trg_com_tim11_handler, 124 | (uint32_t)&tim1_cc_handler, 125 | 0, 126 | 0, 127 | 0, 128 | (uint32_t)&i2c1_ev_handler, 129 | (uint32_t)&i2c1_er_handler, 130 | (uint32_t)&i2c2_ev_handler, 131 | (uint32_t)&i2c2_er_handler, 132 | (uint32_t)&spi1_handler, 133 | (uint32_t)&spi2_handler, 134 | (uint32_t)&usart1_handler, 135 | (uint32_t)&usart2_handler, 136 | 0, 137 | (uint32_t)&exti15_10_handler, 138 | (uint32_t)&exti17_rtc_alarm_handler, 139 | 0, 140 | 0, 141 | 0, 142 | 0, 143 | 0, 144 | (uint32_t)&dma1_stream7_handler, 145 | 0, 146 | 0, 147 | (uint32_t)&tim5_handler, 148 | 0, 149 | 0, 150 | 0, 151 | (uint32_t)&tim6_dac_handler, 152 | 0, 153 | (uint32_t)&dma2_stream0_handler, 154 | (uint32_t)&dma2_stream1_handler, 155 | (uint32_t)&dma2_stream2_handler, 156 | (uint32_t)&dma2_stream3_handler, 157 | (uint32_t)&dma2_stream4_handler, 158 | 0, 159 | (uint32_t)&exti19_handler, 160 | 0, 161 | 0, 162 | 0, 163 | 0, 164 | 0, 165 | (uint32_t)&dma2_stream5_handler, 166 | (uint32_t)&dma2_stream6_handler, 167 | (uint32_t)&dma2_stream7_handler, 168 | (uint32_t)&usart6_handler, 169 | 0, 170 | 0, 171 | 0, 172 | 0, 173 | (uint32_t)&exti20_handler, 174 | 0, 175 | 0, 176 | 0, 177 | (uint32_t)&rng_handler, 178 | (uint32_t)&fpu_handler, 179 | 0, 180 | 0, 181 | 0, 182 | (uint32_t)&spi5_handler, 183 | 0, 184 | 0, 185 | 0, 186 | 0, 187 | 0, 188 | 0, 189 | 0, 190 | 0, 191 | 0, 192 | (uint32_t)&i2c4_ev_handler, 193 | (uint32_t)&i2c4_er_handler, 194 | (uint32_t)&lptim1_exti23_handler 195 | }; 196 | 197 | extern uint32_t _etext, _sdata, _edata, _sbss, _ebss, _sidata; 198 | 199 | void main(void); 200 | void __libc_init_array(); 201 | 202 | void reset_handler(void) 203 | { 204 | // Copy .data from FLASH to SRAM 205 | uint32_t data_size = (uint32_t)&_edata - (uint32_t)&_sdata; 206 | uint8_t *flash_data = (uint8_t*) &_sidata; // Data load address (in flash) 207 | uint8_t *sram_data = (uint8_t*) &_sdata; // Data virtual address (in sram) 208 | 209 | for (uint32_t i = 0; i < data_size; i++) 210 | { 211 | sram_data[i] = flash_data[i]; 212 | } 213 | 214 | // Zero-fill .bss section in SRAM 215 | uint32_t bss_size = (uint32_t)&_ebss - (uint32_t)&_sbss; 216 | uint8_t *bss = (uint8_t*) &_sbss; 217 | 218 | for (uint32_t i = 0; i < bss_size; i++) 219 | { 220 | bss[i] = 0; 221 | } 222 | 223 | __libc_init_array(); 224 | main(); 225 | } 226 | 227 | void default_handler(void) 228 | { 229 | while(1); 230 | } -------------------------------------------------------------------------------- /syscalls.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "usart.h" 4 | #include 5 | #undef errno 6 | extern int errno; 7 | 8 | void _exit(int exit_code) 9 | { 10 | while (1) 11 | { 12 | 13 | } 14 | } 15 | 16 | int _close(int file) { 17 | return -1; 18 | } 19 | 20 | char *__env[1] = { 0 }; 21 | char **environ = __env; 22 | 23 | int _execve(char *name, char **argv, char **env) { 24 | errno = ENOMEM; 25 | return -1; 26 | } 27 | 28 | int _fork(void) { 29 | errno = EAGAIN; 30 | return -1; 31 | } 32 | 33 | 34 | int _fstat(int file, struct stat *st) { 35 | st->st_mode = S_IFCHR; 36 | return 0; 37 | } 38 | 39 | int _getpid(void) { 40 | return 1; 41 | } 42 | 43 | int _isatty(int file) { 44 | return 1; 45 | } 46 | 47 | int _kill(int pid, int sig) { 48 | errno = EINVAL; 49 | return -1; 50 | } 51 | 52 | int _link(char *old, char *new) { 53 | errno = EMLINK; 54 | return -1; 55 | } 56 | 57 | int _lseek(int file, int ptr, int dir) { 58 | return 0; 59 | } 60 | 61 | int _open(const char *name, int flags, int mode) { 62 | return -1; 63 | } 64 | 65 | int _read(int file, char *ptr, int len) { 66 | return 0; 67 | } 68 | 69 | register char * stack_ptr asm("sp"); 70 | 71 | caddr_t _sbrk(int incr) { 72 | extern char __bss_end__; /* Defined by the linker */ 73 | static char *heap_end; 74 | char *prev_heap_end; 75 | 76 | if (heap_end == 0) { 77 | heap_end = &__bss_end__; 78 | } 79 | prev_heap_end = heap_end; 80 | if (heap_end + incr > stack_ptr) { 81 | while (1) 82 | { 83 | // Heap and stack collision 84 | } 85 | } 86 | 87 | heap_end += incr; 88 | return (caddr_t) prev_heap_end; 89 | } 90 | 91 | int _stat(char *file, struct stat *st) { 92 | st->st_mode = S_IFCHR; 93 | return 0; 94 | } 95 | 96 | int _times(struct tms *buf) { 97 | return -1; 98 | } 99 | 100 | int _unlink(char *name) { 101 | errno = ENOENT; 102 | return -1; 103 | } 104 | 105 | int _wait(int *status) { 106 | errno = ECHILD; 107 | return -1; 108 | } 109 | 110 | int _write(int file, char *ptr, int len) { 111 | (void) file; 112 | 113 | for (uint32_t i = 0; i < len; i++) 114 | { 115 | usart_write(USART2, *ptr++); 116 | } 117 | 118 | return len; 119 | } -------------------------------------------------------------------------------- /usart.c: -------------------------------------------------------------------------------- 1 | #include "usart.h" 2 | 3 | void usart_init(USART_TypeDef *usart) 4 | { 5 | /* 6 | Enable USART clock 7 | Enable GPIO clock (PA2 and PA3?) 8 | Set alternate GPIO function 9 | Optional: Enable RX interrupt (and NVIC controller) 10 | 11 | Set: 12 | baudrate 13 | hardware flow control 14 | start bit 15 | parity bit 16 | stop bit 17 | data word 18 | */ 19 | 20 | /* 21 | 22 | 23 | Baud rate register - mantissa and fraction, basically fixed point 12Q4 format, check if oversampling is set to 8 or 16 bits 24 | 115200 baud (bits/sec) 25 | 26 | Control register 1: 27 | - USART enable 28 | - Word length 29 | - Parity control enable (use parity bit) 30 | - Parity selection (odd/even) 31 | 32 | CR2: 33 | - STOP bits 34 | - CPOL (clock polarity) 35 | - CPHA (clock phase) 36 | - 37 | 38 | 39 | */ 40 | 41 | /* Enable USART2 clock */ 42 | RCC->APB1ENR |= (1 << RCC_APB1ENR_USART2EN_Pos); 43 | // do two dummy reads after enabling the peripheral clock, as per the errata 44 | volatile uint32_t dummy; 45 | dummy = RCC->APB1ENR; 46 | dummy = RCC->APB1ENR; 47 | 48 | /* Enable GPIOA clock*/ 49 | RCC->AHB1ENR |= (1 << RCC_AHB1ENR_GPIOAEN); 50 | // do two dummy reads after enabling the peripheral clock, as per the errata 51 | dummy = RCC->AHB1ENR; 52 | dummy = RCC->AHB1ENR; 53 | 54 | /* Set PA2 and PA3 to alternate function */ 55 | GPIOA->MODER &= ~(GPIO_MODER_MODE2_Msk | GPIO_MODER_MODE3_Msk); 56 | GPIOA->MODER |= (0b10 << GPIO_MODER_MODE2_Pos) | (0b10 << GPIO_MODER_MODE3_Pos); 57 | 58 | /* USART2 is AF7 (found in datasheet) */ 59 | GPIOA->AFR[0] &= ~(GPIO_AFRL_AFRL2 | GPIO_AFRL_AFRL3); 60 | GPIOA->AFR[0] |= (7 << GPIO_AFRL_AFSEL2_Pos) | (7 << GPIO_AFRL_AFSEL3_Pos); 61 | 62 | /* Configure and enable USART2 */ 63 | USART2->BRR = 434; // 115200 baud @ 50 MHz APB1 clock and 16x oversampling 64 | USART2->CR1 |= USART_CR1_UE | USART_CR1_TE; // USART enable and transmitter enable 65 | 66 | // Dummy write, because the first byte seems to always be dropped 67 | USART2->DR = 0; 68 | while (!(USART2->SR & USART_SR_TC)); 69 | } 70 | 71 | void usart_write(USART_TypeDef *usart, char c) 72 | { 73 | usart->DR = c; 74 | while (!(usart->SR & USART_SR_TC)); 75 | } 76 | -------------------------------------------------------------------------------- /usart.h: -------------------------------------------------------------------------------- 1 | #ifndef _USART_H_ 2 | #define _USART_H_ 3 | #include "stm32f4xx.h" 4 | 5 | void usart_init(USART_TypeDef *usart); 6 | void usart_write(USART_TypeDef *usart, char c); 7 | 8 | #endif 9 | -------------------------------------------------------------------------------- /vendor/CMSIS/CMSIS/Core/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /vendor/CMSIS/CMSIS/Core/Include/cmsis_gcc.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_gcc.h 3 | * @brief CMSIS compiler GCC header file 4 | * @version V5.4.1 5 | * @date 27. May 2021 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_GCC_H 26 | #define __CMSIS_GCC_H 27 | 28 | /* ignore some GCC warnings */ 29 | #pragma GCC diagnostic push 30 | #pragma GCC diagnostic ignored "-Wsign-conversion" 31 | #pragma GCC diagnostic ignored "-Wconversion" 32 | #pragma GCC diagnostic ignored "-Wunused-parameter" 33 | 34 | /* Fallback for __has_builtin */ 35 | #ifndef __has_builtin 36 | #define __has_builtin(x) (0) 37 | #endif 38 | 39 | /* CMSIS compiler specific defines */ 40 | #ifndef __ASM 41 | #define __ASM __asm 42 | #endif 43 | #ifndef __INLINE 44 | #define __INLINE inline 45 | #endif 46 | #ifndef __STATIC_INLINE 47 | #define __STATIC_INLINE static inline 48 | #endif 49 | #ifndef __STATIC_FORCEINLINE 50 | #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51 | #endif 52 | #ifndef __NO_RETURN 53 | #define __NO_RETURN __attribute__((__noreturn__)) 54 | #endif 55 | #ifndef __USED 56 | #define __USED __attribute__((used)) 57 | #endif 58 | #ifndef __WEAK 59 | #define __WEAK __attribute__((weak)) 60 | #endif 61 | #ifndef __PACKED 62 | #define __PACKED __attribute__((packed, aligned(1))) 63 | #endif 64 | #ifndef __PACKED_STRUCT 65 | #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66 | #endif 67 | #ifndef __PACKED_UNION 68 | #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69 | #endif 70 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 71 | #pragma GCC diagnostic push 72 | #pragma GCC diagnostic ignored "-Wpacked" 73 | #pragma GCC diagnostic ignored "-Wattributes" 74 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75 | #pragma GCC diagnostic pop 76 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77 | #endif 78 | #ifndef __UNALIGNED_UINT16_WRITE 79 | #pragma GCC diagnostic push 80 | #pragma GCC diagnostic ignored "-Wpacked" 81 | #pragma GCC diagnostic ignored "-Wattributes" 82 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83 | #pragma GCC diagnostic pop 84 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 85 | #endif 86 | #ifndef __UNALIGNED_UINT16_READ 87 | #pragma GCC diagnostic push 88 | #pragma GCC diagnostic ignored "-Wpacked" 89 | #pragma GCC diagnostic ignored "-Wattributes" 90 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91 | #pragma GCC diagnostic pop 92 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32_WRITE 95 | #pragma GCC diagnostic push 96 | #pragma GCC diagnostic ignored "-Wpacked" 97 | #pragma GCC diagnostic ignored "-Wattributes" 98 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99 | #pragma GCC diagnostic pop 100 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT32_READ 103 | #pragma GCC diagnostic push 104 | #pragma GCC diagnostic ignored "-Wpacked" 105 | #pragma GCC diagnostic ignored "-Wattributes" 106 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107 | #pragma GCC diagnostic pop 108 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 109 | #endif 110 | #ifndef __ALIGNED 111 | #define __ALIGNED(x) __attribute__((aligned(x))) 112 | #endif 113 | #ifndef __RESTRICT 114 | #define __RESTRICT __restrict 115 | #endif 116 | #ifndef __COMPILER_BARRIER 117 | #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118 | #endif 119 | 120 | /* ######################### Startup and Lowlevel Init ######################## */ 121 | 122 | #ifndef __PROGRAM_START 123 | 124 | /** 125 | \brief Initializes data and bss sections 126 | \details This default implementations initialized all data and additional bss 127 | sections relying on .copy.table and .zero.table specified properly 128 | in the used linker script. 129 | 130 | */ 131 | __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132 | { 133 | extern void _start(void) __NO_RETURN; 134 | 135 | typedef struct { 136 | uint32_t const* src; 137 | uint32_t* dest; 138 | uint32_t wlen; 139 | } __copy_table_t; 140 | 141 | typedef struct { 142 | uint32_t* dest; 143 | uint32_t wlen; 144 | } __zero_table_t; 145 | 146 | extern const __copy_table_t __copy_table_start__; 147 | extern const __copy_table_t __copy_table_end__; 148 | extern const __zero_table_t __zero_table_start__; 149 | extern const __zero_table_t __zero_table_end__; 150 | 151 | for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { 152 | for(uint32_t i=0u; iwlen; ++i) { 153 | pTable->dest[i] = pTable->src[i]; 154 | } 155 | } 156 | 157 | for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { 158 | for(uint32_t i=0u; iwlen; ++i) { 159 | pTable->dest[i] = 0u; 160 | } 161 | } 162 | 163 | _start(); 164 | } 165 | 166 | #define __PROGRAM_START __cmsis_start 167 | #endif 168 | 169 | #ifndef __INITIAL_SP 170 | #define __INITIAL_SP __StackTop 171 | #endif 172 | 173 | #ifndef __STACK_LIMIT 174 | #define __STACK_LIMIT __StackLimit 175 | #endif 176 | 177 | #ifndef __VECTOR_TABLE 178 | #define __VECTOR_TABLE __Vectors 179 | #endif 180 | 181 | #ifndef __VECTOR_TABLE_ATTRIBUTE 182 | #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) 183 | #endif 184 | 185 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 186 | #ifndef __STACK_SEAL 187 | #define __STACK_SEAL __StackSeal 188 | #endif 189 | 190 | #ifndef __TZ_STACK_SEAL_SIZE 191 | #define __TZ_STACK_SEAL_SIZE 8U 192 | #endif 193 | 194 | #ifndef __TZ_STACK_SEAL_VALUE 195 | #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL 196 | #endif 197 | 198 | 199 | __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 200 | *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 201 | } 202 | #endif 203 | 204 | 205 | /* ########################## Core Instruction Access ######################### */ 206 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 207 | Access to dedicated instructions 208 | @{ 209 | */ 210 | 211 | /* Define macros for porting to both thumb1 and thumb2. 212 | * For thumb1, use low register (r0-r7), specified by constraint "l" 213 | * Otherwise, use general registers, specified by constraint "r" */ 214 | #if defined (__thumb__) && !defined (__thumb2__) 215 | #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 216 | #define __CMSIS_GCC_RW_REG(r) "+l" (r) 217 | #define __CMSIS_GCC_USE_REG(r) "l" (r) 218 | #else 219 | #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 220 | #define __CMSIS_GCC_RW_REG(r) "+r" (r) 221 | #define __CMSIS_GCC_USE_REG(r) "r" (r) 222 | #endif 223 | 224 | /** 225 | \brief No Operation 226 | \details No Operation does nothing. This instruction can be used for code alignment purposes. 227 | */ 228 | #define __NOP() __ASM volatile ("nop") 229 | 230 | /** 231 | \brief Wait For Interrupt 232 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 233 | */ 234 | #define __WFI() __ASM volatile ("wfi":::"memory") 235 | 236 | 237 | /** 238 | \brief Wait For Event 239 | \details Wait For Event is a hint instruction that permits the processor to enter 240 | a low-power state until one of a number of events occurs. 241 | */ 242 | #define __WFE() __ASM volatile ("wfe":::"memory") 243 | 244 | 245 | /** 246 | \brief Send Event 247 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 248 | */ 249 | #define __SEV() __ASM volatile ("sev") 250 | 251 | 252 | /** 253 | \brief Instruction Synchronization Barrier 254 | \details Instruction Synchronization Barrier flushes the pipeline in the processor, 255 | so that all instructions following the ISB are fetched from cache or memory, 256 | after the instruction has been completed. 257 | */ 258 | __STATIC_FORCEINLINE void __ISB(void) 259 | { 260 | __ASM volatile ("isb 0xF":::"memory"); 261 | } 262 | 263 | 264 | /** 265 | \brief Data Synchronization Barrier 266 | \details Acts as a special kind of Data Memory Barrier. 267 | It completes when all explicit memory accesses before this instruction complete. 268 | */ 269 | __STATIC_FORCEINLINE void __DSB(void) 270 | { 271 | __ASM volatile ("dsb 0xF":::"memory"); 272 | } 273 | 274 | 275 | /** 276 | \brief Data Memory Barrier 277 | \details Ensures the apparent order of the explicit memory operations before 278 | and after the instruction, without ensuring their completion. 279 | */ 280 | __STATIC_FORCEINLINE void __DMB(void) 281 | { 282 | __ASM volatile ("dmb 0xF":::"memory"); 283 | } 284 | 285 | 286 | /** 287 | \brief Reverse byte order (32 bit) 288 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 289 | \param [in] value Value to reverse 290 | \return Reversed value 291 | */ 292 | __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 293 | { 294 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 295 | return __builtin_bswap32(value); 296 | #else 297 | uint32_t result; 298 | 299 | __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 300 | return result; 301 | #endif 302 | } 303 | 304 | 305 | /** 306 | \brief Reverse byte order (16 bit) 307 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 308 | \param [in] value Value to reverse 309 | \return Reversed value 310 | */ 311 | __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 312 | { 313 | uint32_t result; 314 | 315 | __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 316 | return result; 317 | } 318 | 319 | 320 | /** 321 | \brief Reverse byte order (16 bit) 322 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 323 | \param [in] value Value to reverse 324 | \return Reversed value 325 | */ 326 | __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 327 | { 328 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 329 | return (int16_t)__builtin_bswap16(value); 330 | #else 331 | int16_t result; 332 | 333 | __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 334 | return result; 335 | #endif 336 | } 337 | 338 | 339 | /** 340 | \brief Rotate Right in unsigned value (32 bit) 341 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 342 | \param [in] op1 Value to rotate 343 | \param [in] op2 Number of Bits to rotate 344 | \return Rotated value 345 | */ 346 | __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 347 | { 348 | op2 %= 32U; 349 | if (op2 == 0U) 350 | { 351 | return op1; 352 | } 353 | return (op1 >> op2) | (op1 << (32U - op2)); 354 | } 355 | 356 | 357 | /** 358 | \brief Breakpoint 359 | \details Causes the processor to enter Debug state. 360 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. 361 | \param [in] value is ignored by the processor. 362 | If required, a debugger can use it to store additional information about the breakpoint. 363 | */ 364 | #define __BKPT(value) __ASM volatile ("bkpt "#value) 365 | 366 | 367 | /** 368 | \brief Reverse bit order of value 369 | \details Reverses the bit order of the given value. 370 | \param [in] value Value to reverse 371 | \return Reversed value 372 | */ 373 | __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 374 | { 375 | uint32_t result; 376 | 377 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 378 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 379 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 380 | __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); 381 | #else 382 | uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 383 | 384 | result = value; /* r will be reversed bits of v; first get LSB of v */ 385 | for (value >>= 1U; value != 0U; value >>= 1U) 386 | { 387 | result <<= 1U; 388 | result |= value & 1U; 389 | s--; 390 | } 391 | result <<= s; /* shift when v's highest bits are zero */ 392 | #endif 393 | return result; 394 | } 395 | 396 | 397 | /** 398 | \brief Count leading zeros 399 | \details Counts the number of leading zeros of a data value. 400 | \param [in] value Value to count the leading zeros 401 | \return number of leading zeros in value 402 | */ 403 | __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 404 | { 405 | /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 406 | __builtin_clz(0) is undefined behaviour, so handle this case specially. 407 | This guarantees ARM-compatible results if happening to compile on a non-ARM 408 | target, and ensures the compiler doesn't decide to activate any 409 | optimisations using the logic "value was passed to __builtin_clz, so it 410 | is non-zero". 411 | ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 412 | single CLZ instruction. 413 | */ 414 | if (value == 0U) 415 | { 416 | return 32U; 417 | } 418 | return __builtin_clz(value); 419 | } 420 | 421 | 422 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 423 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 424 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 425 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 426 | /** 427 | \brief LDR Exclusive (8 bit) 428 | \details Executes a exclusive LDR instruction for 8 bit value. 429 | \param [in] ptr Pointer to data 430 | \return value of type uint8_t at (*ptr) 431 | */ 432 | __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 433 | { 434 | uint32_t result; 435 | 436 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 437 | __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 438 | #else 439 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 440 | accepted by assembler. So has to use following less efficient pattern. 441 | */ 442 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 443 | #endif 444 | return ((uint8_t) result); /* Add explicit type cast here */ 445 | } 446 | 447 | 448 | /** 449 | \brief LDR Exclusive (16 bit) 450 | \details Executes a exclusive LDR instruction for 16 bit values. 451 | \param [in] ptr Pointer to data 452 | \return value of type uint16_t at (*ptr) 453 | */ 454 | __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 455 | { 456 | uint32_t result; 457 | 458 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 459 | __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 460 | #else 461 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 462 | accepted by assembler. So has to use following less efficient pattern. 463 | */ 464 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 465 | #endif 466 | return ((uint16_t) result); /* Add explicit type cast here */ 467 | } 468 | 469 | 470 | /** 471 | \brief LDR Exclusive (32 bit) 472 | \details Executes a exclusive LDR instruction for 32 bit values. 473 | \param [in] ptr Pointer to data 474 | \return value of type uint32_t at (*ptr) 475 | */ 476 | __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 477 | { 478 | uint32_t result; 479 | 480 | __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 481 | return(result); 482 | } 483 | 484 | 485 | /** 486 | \brief STR Exclusive (8 bit) 487 | \details Executes a exclusive STR instruction for 8 bit values. 488 | \param [in] value Value to store 489 | \param [in] ptr Pointer to location 490 | \return 0 Function succeeded 491 | \return 1 Function failed 492 | */ 493 | __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 494 | { 495 | uint32_t result; 496 | 497 | __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 498 | return(result); 499 | } 500 | 501 | 502 | /** 503 | \brief STR Exclusive (16 bit) 504 | \details Executes a exclusive STR instruction for 16 bit values. 505 | \param [in] value Value to store 506 | \param [in] ptr Pointer to location 507 | \return 0 Function succeeded 508 | \return 1 Function failed 509 | */ 510 | __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 511 | { 512 | uint32_t result; 513 | 514 | __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 515 | return(result); 516 | } 517 | 518 | 519 | /** 520 | \brief STR Exclusive (32 bit) 521 | \details Executes a exclusive STR instruction for 32 bit values. 522 | \param [in] value Value to store 523 | \param [in] ptr Pointer to location 524 | \return 0 Function succeeded 525 | \return 1 Function failed 526 | */ 527 | __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 528 | { 529 | uint32_t result; 530 | 531 | __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 532 | return(result); 533 | } 534 | 535 | 536 | /** 537 | \brief Remove the exclusive lock 538 | \details Removes the exclusive lock which is created by LDREX. 539 | */ 540 | __STATIC_FORCEINLINE void __CLREX(void) 541 | { 542 | __ASM volatile ("clrex" ::: "memory"); 543 | } 544 | 545 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 546 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 547 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 548 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 549 | 550 | 551 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 552 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 553 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 554 | /** 555 | \brief Signed Saturate 556 | \details Saturates a signed value. 557 | \param [in] ARG1 Value to be saturated 558 | \param [in] ARG2 Bit position to saturate to (1..32) 559 | \return Saturated value 560 | */ 561 | #define __SSAT(ARG1, ARG2) \ 562 | __extension__ \ 563 | ({ \ 564 | int32_t __RES, __ARG1 = (ARG1); \ 565 | __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 566 | __RES; \ 567 | }) 568 | 569 | 570 | /** 571 | \brief Unsigned Saturate 572 | \details Saturates an unsigned value. 573 | \param [in] ARG1 Value to be saturated 574 | \param [in] ARG2 Bit position to saturate to (0..31) 575 | \return Saturated value 576 | */ 577 | #define __USAT(ARG1, ARG2) \ 578 | __extension__ \ 579 | ({ \ 580 | uint32_t __RES, __ARG1 = (ARG1); \ 581 | __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 582 | __RES; \ 583 | }) 584 | 585 | 586 | /** 587 | \brief Rotate Right with Extend (32 bit) 588 | \details Moves each bit of a bitstring right by one bit. 589 | The carry input is shifted in at the left end of the bitstring. 590 | \param [in] value Value to rotate 591 | \return Rotated value 592 | */ 593 | __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 594 | { 595 | uint32_t result; 596 | 597 | __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 598 | return(result); 599 | } 600 | 601 | 602 | /** 603 | \brief LDRT Unprivileged (8 bit) 604 | \details Executes a Unprivileged LDRT instruction for 8 bit value. 605 | \param [in] ptr Pointer to data 606 | \return value of type uint8_t at (*ptr) 607 | */ 608 | __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 609 | { 610 | uint32_t result; 611 | 612 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 613 | __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 614 | #else 615 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 616 | accepted by assembler. So has to use following less efficient pattern. 617 | */ 618 | __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 619 | #endif 620 | return ((uint8_t) result); /* Add explicit type cast here */ 621 | } 622 | 623 | 624 | /** 625 | \brief LDRT Unprivileged (16 bit) 626 | \details Executes a Unprivileged LDRT instruction for 16 bit values. 627 | \param [in] ptr Pointer to data 628 | \return value of type uint16_t at (*ptr) 629 | */ 630 | __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 631 | { 632 | uint32_t result; 633 | 634 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 635 | __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 636 | #else 637 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 638 | accepted by assembler. So has to use following less efficient pattern. 639 | */ 640 | __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 641 | #endif 642 | return ((uint16_t) result); /* Add explicit type cast here */ 643 | } 644 | 645 | 646 | /** 647 | \brief LDRT Unprivileged (32 bit) 648 | \details Executes a Unprivileged LDRT instruction for 32 bit values. 649 | \param [in] ptr Pointer to data 650 | \return value of type uint32_t at (*ptr) 651 | */ 652 | __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 653 | { 654 | uint32_t result; 655 | 656 | __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 657 | return(result); 658 | } 659 | 660 | 661 | /** 662 | \brief STRT Unprivileged (8 bit) 663 | \details Executes a Unprivileged STRT instruction for 8 bit values. 664 | \param [in] value Value to store 665 | \param [in] ptr Pointer to location 666 | */ 667 | __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 668 | { 669 | __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 670 | } 671 | 672 | 673 | /** 674 | \brief STRT Unprivileged (16 bit) 675 | \details Executes a Unprivileged STRT instruction for 16 bit values. 676 | \param [in] value Value to store 677 | \param [in] ptr Pointer to location 678 | */ 679 | __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 680 | { 681 | __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 682 | } 683 | 684 | 685 | /** 686 | \brief STRT Unprivileged (32 bit) 687 | \details Executes a Unprivileged STRT instruction for 32 bit values. 688 | \param [in] value Value to store 689 | \param [in] ptr Pointer to location 690 | */ 691 | __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 692 | { 693 | __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 694 | } 695 | 696 | #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 697 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 698 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 699 | 700 | /** 701 | \brief Signed Saturate 702 | \details Saturates a signed value. 703 | \param [in] value Value to be saturated 704 | \param [in] sat Bit position to saturate to (1..32) 705 | \return Saturated value 706 | */ 707 | __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 708 | { 709 | if ((sat >= 1U) && (sat <= 32U)) 710 | { 711 | const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 712 | const int32_t min = -1 - max ; 713 | if (val > max) 714 | { 715 | return max; 716 | } 717 | else if (val < min) 718 | { 719 | return min; 720 | } 721 | } 722 | return val; 723 | } 724 | 725 | /** 726 | \brief Unsigned Saturate 727 | \details Saturates an unsigned value. 728 | \param [in] value Value to be saturated 729 | \param [in] sat Bit position to saturate to (0..31) 730 | \return Saturated value 731 | */ 732 | __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 733 | { 734 | if (sat <= 31U) 735 | { 736 | const uint32_t max = ((1U << sat) - 1U); 737 | if (val > (int32_t)max) 738 | { 739 | return max; 740 | } 741 | else if (val < 0) 742 | { 743 | return 0U; 744 | } 745 | } 746 | return (uint32_t)val; 747 | } 748 | 749 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 750 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 751 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 752 | 753 | 754 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 755 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 756 | /** 757 | \brief Load-Acquire (8 bit) 758 | \details Executes a LDAB instruction for 8 bit value. 759 | \param [in] ptr Pointer to data 760 | \return value of type uint8_t at (*ptr) 761 | */ 762 | __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 763 | { 764 | uint32_t result; 765 | 766 | __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 767 | return ((uint8_t) result); 768 | } 769 | 770 | 771 | /** 772 | \brief Load-Acquire (16 bit) 773 | \details Executes a LDAH instruction for 16 bit values. 774 | \param [in] ptr Pointer to data 775 | \return value of type uint16_t at (*ptr) 776 | */ 777 | __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 778 | { 779 | uint32_t result; 780 | 781 | __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 782 | return ((uint16_t) result); 783 | } 784 | 785 | 786 | /** 787 | \brief Load-Acquire (32 bit) 788 | \details Executes a LDA instruction for 32 bit values. 789 | \param [in] ptr Pointer to data 790 | \return value of type uint32_t at (*ptr) 791 | */ 792 | __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 793 | { 794 | uint32_t result; 795 | 796 | __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 797 | return(result); 798 | } 799 | 800 | 801 | /** 802 | \brief Store-Release (8 bit) 803 | \details Executes a STLB instruction for 8 bit values. 804 | \param [in] value Value to store 805 | \param [in] ptr Pointer to location 806 | */ 807 | __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 808 | { 809 | __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 810 | } 811 | 812 | 813 | /** 814 | \brief Store-Release (16 bit) 815 | \details Executes a STLH instruction for 16 bit values. 816 | \param [in] value Value to store 817 | \param [in] ptr Pointer to location 818 | */ 819 | __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 820 | { 821 | __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 822 | } 823 | 824 | 825 | /** 826 | \brief Store-Release (32 bit) 827 | \details Executes a STL instruction for 32 bit values. 828 | \param [in] value Value to store 829 | \param [in] ptr Pointer to location 830 | */ 831 | __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 832 | { 833 | __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 834 | } 835 | 836 | 837 | /** 838 | \brief Load-Acquire Exclusive (8 bit) 839 | \details Executes a LDAB exclusive instruction for 8 bit value. 840 | \param [in] ptr Pointer to data 841 | \return value of type uint8_t at (*ptr) 842 | */ 843 | __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) 844 | { 845 | uint32_t result; 846 | 847 | __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 848 | return ((uint8_t) result); 849 | } 850 | 851 | 852 | /** 853 | \brief Load-Acquire Exclusive (16 bit) 854 | \details Executes a LDAH exclusive instruction for 16 bit values. 855 | \param [in] ptr Pointer to data 856 | \return value of type uint16_t at (*ptr) 857 | */ 858 | __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) 859 | { 860 | uint32_t result; 861 | 862 | __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 863 | return ((uint16_t) result); 864 | } 865 | 866 | 867 | /** 868 | \brief Load-Acquire Exclusive (32 bit) 869 | \details Executes a LDA exclusive instruction for 32 bit values. 870 | \param [in] ptr Pointer to data 871 | \return value of type uint32_t at (*ptr) 872 | */ 873 | __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) 874 | { 875 | uint32_t result; 876 | 877 | __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 878 | return(result); 879 | } 880 | 881 | 882 | /** 883 | \brief Store-Release Exclusive (8 bit) 884 | \details Executes a STLB exclusive instruction for 8 bit values. 885 | \param [in] value Value to store 886 | \param [in] ptr Pointer to location 887 | \return 0 Function succeeded 888 | \return 1 Function failed 889 | */ 890 | __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 891 | { 892 | uint32_t result; 893 | 894 | __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 895 | return(result); 896 | } 897 | 898 | 899 | /** 900 | \brief Store-Release Exclusive (16 bit) 901 | \details Executes a STLH exclusive instruction for 16 bit values. 902 | \param [in] value Value to store 903 | \param [in] ptr Pointer to location 904 | \return 0 Function succeeded 905 | \return 1 Function failed 906 | */ 907 | __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 908 | { 909 | uint32_t result; 910 | 911 | __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 912 | return(result); 913 | } 914 | 915 | 916 | /** 917 | \brief Store-Release Exclusive (32 bit) 918 | \details Executes a STL exclusive instruction for 32 bit values. 919 | \param [in] value Value to store 920 | \param [in] ptr Pointer to location 921 | \return 0 Function succeeded 922 | \return 1 Function failed 923 | */ 924 | __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 925 | { 926 | uint32_t result; 927 | 928 | __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 929 | return(result); 930 | } 931 | 932 | #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 933 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 934 | 935 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 936 | 937 | 938 | /* ########################### Core Function Access ########################### */ 939 | /** \ingroup CMSIS_Core_FunctionInterface 940 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 941 | @{ 942 | */ 943 | 944 | /** 945 | \brief Enable IRQ Interrupts 946 | \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. 947 | Can only be executed in Privileged modes. 948 | */ 949 | __STATIC_FORCEINLINE void __enable_irq(void) 950 | { 951 | __ASM volatile ("cpsie i" : : : "memory"); 952 | } 953 | 954 | 955 | /** 956 | \brief Disable IRQ Interrupts 957 | \details Disables IRQ interrupts by setting special-purpose register PRIMASK. 958 | Can only be executed in Privileged modes. 959 | */ 960 | __STATIC_FORCEINLINE void __disable_irq(void) 961 | { 962 | __ASM volatile ("cpsid i" : : : "memory"); 963 | } 964 | 965 | 966 | /** 967 | \brief Get Control Register 968 | \details Returns the content of the Control Register. 969 | \return Control Register value 970 | */ 971 | __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 972 | { 973 | uint32_t result; 974 | 975 | __ASM volatile ("MRS %0, control" : "=r" (result) ); 976 | return(result); 977 | } 978 | 979 | 980 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 981 | /** 982 | \brief Get Control Register (non-secure) 983 | \details Returns the content of the non-secure Control Register when in secure mode. 984 | \return non-secure Control Register value 985 | */ 986 | __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 987 | { 988 | uint32_t result; 989 | 990 | __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 991 | return(result); 992 | } 993 | #endif 994 | 995 | 996 | /** 997 | \brief Set Control Register 998 | \details Writes the given value to the Control Register. 999 | \param [in] control Control Register value to set 1000 | */ 1001 | __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 1002 | { 1003 | __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 1004 | __ISB(); 1005 | } 1006 | 1007 | 1008 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1009 | /** 1010 | \brief Set Control Register (non-secure) 1011 | \details Writes the given value to the non-secure Control Register when in secure state. 1012 | \param [in] control Control Register value to set 1013 | */ 1014 | __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 1015 | { 1016 | __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 1017 | __ISB(); 1018 | } 1019 | #endif 1020 | 1021 | 1022 | /** 1023 | \brief Get IPSR Register 1024 | \details Returns the content of the IPSR Register. 1025 | \return IPSR Register value 1026 | */ 1027 | __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 1028 | { 1029 | uint32_t result; 1030 | 1031 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 1032 | return(result); 1033 | } 1034 | 1035 | 1036 | /** 1037 | \brief Get APSR Register 1038 | \details Returns the content of the APSR Register. 1039 | \return APSR Register value 1040 | */ 1041 | __STATIC_FORCEINLINE uint32_t __get_APSR(void) 1042 | { 1043 | uint32_t result; 1044 | 1045 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 1046 | return(result); 1047 | } 1048 | 1049 | 1050 | /** 1051 | \brief Get xPSR Register 1052 | \details Returns the content of the xPSR Register. 1053 | \return xPSR Register value 1054 | */ 1055 | __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 1056 | { 1057 | uint32_t result; 1058 | 1059 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 1060 | return(result); 1061 | } 1062 | 1063 | 1064 | /** 1065 | \brief Get Process Stack Pointer 1066 | \details Returns the current value of the Process Stack Pointer (PSP). 1067 | \return PSP Register value 1068 | */ 1069 | __STATIC_FORCEINLINE uint32_t __get_PSP(void) 1070 | { 1071 | uint32_t result; 1072 | 1073 | __ASM volatile ("MRS %0, psp" : "=r" (result) ); 1074 | return(result); 1075 | } 1076 | 1077 | 1078 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1079 | /** 1080 | \brief Get Process Stack Pointer (non-secure) 1081 | \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. 1082 | \return PSP Register value 1083 | */ 1084 | __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 1085 | { 1086 | uint32_t result; 1087 | 1088 | __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 1089 | return(result); 1090 | } 1091 | #endif 1092 | 1093 | 1094 | /** 1095 | \brief Set Process Stack Pointer 1096 | \details Assigns the given value to the Process Stack Pointer (PSP). 1097 | \param [in] topOfProcStack Process Stack Pointer value to set 1098 | */ 1099 | __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 1100 | { 1101 | __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 1102 | } 1103 | 1104 | 1105 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1106 | /** 1107 | \brief Set Process Stack Pointer (non-secure) 1108 | \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. 1109 | \param [in] topOfProcStack Process Stack Pointer value to set 1110 | */ 1111 | __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 1112 | { 1113 | __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 1114 | } 1115 | #endif 1116 | 1117 | 1118 | /** 1119 | \brief Get Main Stack Pointer 1120 | \details Returns the current value of the Main Stack Pointer (MSP). 1121 | \return MSP Register value 1122 | */ 1123 | __STATIC_FORCEINLINE uint32_t __get_MSP(void) 1124 | { 1125 | uint32_t result; 1126 | 1127 | __ASM volatile ("MRS %0, msp" : "=r" (result) ); 1128 | return(result); 1129 | } 1130 | 1131 | 1132 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1133 | /** 1134 | \brief Get Main Stack Pointer (non-secure) 1135 | \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. 1136 | \return MSP Register value 1137 | */ 1138 | __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 1139 | { 1140 | uint32_t result; 1141 | 1142 | __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 1143 | return(result); 1144 | } 1145 | #endif 1146 | 1147 | 1148 | /** 1149 | \brief Set Main Stack Pointer 1150 | \details Assigns the given value to the Main Stack Pointer (MSP). 1151 | \param [in] topOfMainStack Main Stack Pointer value to set 1152 | */ 1153 | __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 1154 | { 1155 | __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 1156 | } 1157 | 1158 | 1159 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1160 | /** 1161 | \brief Set Main Stack Pointer (non-secure) 1162 | \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 1163 | \param [in] topOfMainStack Main Stack Pointer value to set 1164 | */ 1165 | __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 1166 | { 1167 | __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 1168 | } 1169 | #endif 1170 | 1171 | 1172 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1173 | /** 1174 | \brief Get Stack Pointer (non-secure) 1175 | \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 1176 | \return SP Register value 1177 | */ 1178 | __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 1179 | { 1180 | uint32_t result; 1181 | 1182 | __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 1183 | return(result); 1184 | } 1185 | 1186 | 1187 | /** 1188 | \brief Set Stack Pointer (non-secure) 1189 | \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 1190 | \param [in] topOfStack Stack Pointer value to set 1191 | */ 1192 | __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 1193 | { 1194 | __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 1195 | } 1196 | #endif 1197 | 1198 | 1199 | /** 1200 | \brief Get Priority Mask 1201 | \details Returns the current state of the priority mask bit from the Priority Mask Register. 1202 | \return Priority Mask value 1203 | */ 1204 | __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 1205 | { 1206 | uint32_t result; 1207 | 1208 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); 1209 | return(result); 1210 | } 1211 | 1212 | 1213 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1214 | /** 1215 | \brief Get Priority Mask (non-secure) 1216 | \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. 1217 | \return Priority Mask value 1218 | */ 1219 | __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 1220 | { 1221 | uint32_t result; 1222 | 1223 | __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); 1224 | return(result); 1225 | } 1226 | #endif 1227 | 1228 | 1229 | /** 1230 | \brief Set Priority Mask 1231 | \details Assigns the given value to the Priority Mask Register. 1232 | \param [in] priMask Priority Mask 1233 | */ 1234 | __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 1235 | { 1236 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 1237 | } 1238 | 1239 | 1240 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1241 | /** 1242 | \brief Set Priority Mask (non-secure) 1243 | \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 1244 | \param [in] priMask Priority Mask 1245 | */ 1246 | __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 1247 | { 1248 | __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 1249 | } 1250 | #endif 1251 | 1252 | 1253 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1254 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1255 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 1256 | /** 1257 | \brief Enable FIQ 1258 | \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. 1259 | Can only be executed in Privileged modes. 1260 | */ 1261 | __STATIC_FORCEINLINE void __enable_fault_irq(void) 1262 | { 1263 | __ASM volatile ("cpsie f" : : : "memory"); 1264 | } 1265 | 1266 | 1267 | /** 1268 | \brief Disable FIQ 1269 | \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. 1270 | Can only be executed in Privileged modes. 1271 | */ 1272 | __STATIC_FORCEINLINE void __disable_fault_irq(void) 1273 | { 1274 | __ASM volatile ("cpsid f" : : : "memory"); 1275 | } 1276 | 1277 | 1278 | /** 1279 | \brief Get Base Priority 1280 | \details Returns the current value of the Base Priority register. 1281 | \return Base Priority register value 1282 | */ 1283 | __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 1284 | { 1285 | uint32_t result; 1286 | 1287 | __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 1288 | return(result); 1289 | } 1290 | 1291 | 1292 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1293 | /** 1294 | \brief Get Base Priority (non-secure) 1295 | \details Returns the current value of the non-secure Base Priority register when in secure state. 1296 | \return Base Priority register value 1297 | */ 1298 | __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 1299 | { 1300 | uint32_t result; 1301 | 1302 | __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 1303 | return(result); 1304 | } 1305 | #endif 1306 | 1307 | 1308 | /** 1309 | \brief Set Base Priority 1310 | \details Assigns the given value to the Base Priority register. 1311 | \param [in] basePri Base Priority value to set 1312 | */ 1313 | __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 1314 | { 1315 | __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 1316 | } 1317 | 1318 | 1319 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1320 | /** 1321 | \brief Set Base Priority (non-secure) 1322 | \details Assigns the given value to the non-secure Base Priority register when in secure state. 1323 | \param [in] basePri Base Priority value to set 1324 | */ 1325 | __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 1326 | { 1327 | __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 1328 | } 1329 | #endif 1330 | 1331 | 1332 | /** 1333 | \brief Set Base Priority with condition 1334 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 1335 | or the new value increases the BASEPRI priority level. 1336 | \param [in] basePri Base Priority value to set 1337 | */ 1338 | __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 1339 | { 1340 | __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 1341 | } 1342 | 1343 | 1344 | /** 1345 | \brief Get Fault Mask 1346 | \details Returns the current value of the Fault Mask register. 1347 | \return Fault Mask register value 1348 | */ 1349 | __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 1350 | { 1351 | uint32_t result; 1352 | 1353 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 1354 | return(result); 1355 | } 1356 | 1357 | 1358 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1359 | /** 1360 | \brief Get Fault Mask (non-secure) 1361 | \details Returns the current value of the non-secure Fault Mask register when in secure state. 1362 | \return Fault Mask register value 1363 | */ 1364 | __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 1365 | { 1366 | uint32_t result; 1367 | 1368 | __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 1369 | return(result); 1370 | } 1371 | #endif 1372 | 1373 | 1374 | /** 1375 | \brief Set Fault Mask 1376 | \details Assigns the given value to the Fault Mask register. 1377 | \param [in] faultMask Fault Mask value to set 1378 | */ 1379 | __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 1380 | { 1381 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 1382 | } 1383 | 1384 | 1385 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1386 | /** 1387 | \brief Set Fault Mask (non-secure) 1388 | \details Assigns the given value to the non-secure Fault Mask register when in secure state. 1389 | \param [in] faultMask Fault Mask value to set 1390 | */ 1391 | __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 1392 | { 1393 | __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 1394 | } 1395 | #endif 1396 | 1397 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1398 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1399 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 1400 | 1401 | 1402 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1403 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1404 | 1405 | /** 1406 | \brief Get Process Stack Pointer Limit 1407 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1408 | Stack Pointer Limit register hence zero is returned always in non-secure 1409 | mode. 1410 | 1411 | \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 1412 | \return PSPLIM Register value 1413 | */ 1414 | __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 1415 | { 1416 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1417 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1418 | // without main extensions, the non-secure PSPLIM is RAZ/WI 1419 | return 0U; 1420 | #else 1421 | uint32_t result; 1422 | __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 1423 | return result; 1424 | #endif 1425 | } 1426 | 1427 | #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 1428 | /** 1429 | \brief Get Process Stack Pointer Limit (non-secure) 1430 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1431 | Stack Pointer Limit register hence zero is returned always. 1432 | 1433 | \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 1434 | \return PSPLIM Register value 1435 | */ 1436 | __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 1437 | { 1438 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1439 | // without main extensions, the non-secure PSPLIM is RAZ/WI 1440 | return 0U; 1441 | #else 1442 | uint32_t result; 1443 | __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 1444 | return result; 1445 | #endif 1446 | } 1447 | #endif 1448 | 1449 | 1450 | /** 1451 | \brief Set Process Stack Pointer Limit 1452 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1453 | Stack Pointer Limit register hence the write is silently ignored in non-secure 1454 | mode. 1455 | 1456 | \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 1457 | \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 1458 | */ 1459 | __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 1460 | { 1461 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1462 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1463 | // without main extensions, the non-secure PSPLIM is RAZ/WI 1464 | (void)ProcStackPtrLimit; 1465 | #else 1466 | __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 1467 | #endif 1468 | } 1469 | 1470 | 1471 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1472 | /** 1473 | \brief Set Process Stack Pointer (non-secure) 1474 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1475 | Stack Pointer Limit register hence the write is silently ignored. 1476 | 1477 | \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 1478 | \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 1479 | */ 1480 | __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 1481 | { 1482 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1483 | // without main extensions, the non-secure PSPLIM is RAZ/WI 1484 | (void)ProcStackPtrLimit; 1485 | #else 1486 | __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 1487 | #endif 1488 | } 1489 | #endif 1490 | 1491 | 1492 | /** 1493 | \brief Get Main Stack Pointer Limit 1494 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1495 | Stack Pointer Limit register hence zero is returned always in non-secure 1496 | mode. 1497 | 1498 | \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 1499 | \return MSPLIM Register value 1500 | */ 1501 | __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 1502 | { 1503 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1504 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1505 | // without main extensions, the non-secure MSPLIM is RAZ/WI 1506 | return 0U; 1507 | #else 1508 | uint32_t result; 1509 | __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 1510 | return result; 1511 | #endif 1512 | } 1513 | 1514 | 1515 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1516 | /** 1517 | \brief Get Main Stack Pointer Limit (non-secure) 1518 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1519 | Stack Pointer Limit register hence zero is returned always. 1520 | 1521 | \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. 1522 | \return MSPLIM Register value 1523 | */ 1524 | __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 1525 | { 1526 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1527 | // without main extensions, the non-secure MSPLIM is RAZ/WI 1528 | return 0U; 1529 | #else 1530 | uint32_t result; 1531 | __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 1532 | return result; 1533 | #endif 1534 | } 1535 | #endif 1536 | 1537 | 1538 | /** 1539 | \brief Set Main Stack Pointer Limit 1540 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1541 | Stack Pointer Limit register hence the write is silently ignored in non-secure 1542 | mode. 1543 | 1544 | \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 1545 | \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 1546 | */ 1547 | __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 1548 | { 1549 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1550 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1551 | // without main extensions, the non-secure MSPLIM is RAZ/WI 1552 | (void)MainStackPtrLimit; 1553 | #else 1554 | __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 1555 | #endif 1556 | } 1557 | 1558 | 1559 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1560 | /** 1561 | \brief Set Main Stack Pointer Limit (non-secure) 1562 | Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1563 | Stack Pointer Limit register hence the write is silently ignored. 1564 | 1565 | \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. 1566 | \param [in] MainStackPtrLimit Main Stack Pointer value to set 1567 | */ 1568 | __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 1569 | { 1570 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1571 | // without main extensions, the non-secure MSPLIM is RAZ/WI 1572 | (void)MainStackPtrLimit; 1573 | #else 1574 | __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 1575 | #endif 1576 | } 1577 | #endif 1578 | 1579 | #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1580 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 1581 | 1582 | 1583 | /** 1584 | \brief Get FPSCR 1585 | \details Returns the current value of the Floating Point Status/Control register. 1586 | \return Floating Point Status/Control register value 1587 | */ 1588 | __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 1589 | { 1590 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 1591 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 1592 | #if __has_builtin(__builtin_arm_get_fpscr) 1593 | // Re-enable using built-in when GCC has been fixed 1594 | // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 1595 | /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 1596 | return __builtin_arm_get_fpscr(); 1597 | #else 1598 | uint32_t result; 1599 | 1600 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 1601 | return(result); 1602 | #endif 1603 | #else 1604 | return(0U); 1605 | #endif 1606 | } 1607 | 1608 | 1609 | /** 1610 | \brief Set FPSCR 1611 | \details Assigns the given value to the Floating Point Status/Control register. 1612 | \param [in] fpscr Floating Point Status/Control value to set 1613 | */ 1614 | __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 1615 | { 1616 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 1617 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 1618 | #if __has_builtin(__builtin_arm_set_fpscr) 1619 | // Re-enable using built-in when GCC has been fixed 1620 | // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 1621 | /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 1622 | __builtin_arm_set_fpscr(fpscr); 1623 | #else 1624 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 1625 | #endif 1626 | #else 1627 | (void)fpscr; 1628 | #endif 1629 | } 1630 | 1631 | 1632 | /*@} end of CMSIS_Core_RegAccFunctions */ 1633 | 1634 | 1635 | /* ################### Compiler specific Intrinsics ########################### */ 1636 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 1637 | Access to dedicated SIMD instructions 1638 | @{ 1639 | */ 1640 | 1641 | #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) 1642 | 1643 | __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) 1644 | { 1645 | uint32_t result; 1646 | 1647 | __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1648 | return(result); 1649 | } 1650 | 1651 | __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) 1652 | { 1653 | uint32_t result; 1654 | 1655 | __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1656 | return(result); 1657 | } 1658 | 1659 | __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) 1660 | { 1661 | uint32_t result; 1662 | 1663 | __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1664 | return(result); 1665 | } 1666 | 1667 | __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) 1668 | { 1669 | uint32_t result; 1670 | 1671 | __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1672 | return(result); 1673 | } 1674 | 1675 | __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) 1676 | { 1677 | uint32_t result; 1678 | 1679 | __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1680 | return(result); 1681 | } 1682 | 1683 | __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) 1684 | { 1685 | uint32_t result; 1686 | 1687 | __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1688 | return(result); 1689 | } 1690 | 1691 | 1692 | __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) 1693 | { 1694 | uint32_t result; 1695 | 1696 | __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1697 | return(result); 1698 | } 1699 | 1700 | __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) 1701 | { 1702 | uint32_t result; 1703 | 1704 | __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1705 | return(result); 1706 | } 1707 | 1708 | __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) 1709 | { 1710 | uint32_t result; 1711 | 1712 | __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1713 | return(result); 1714 | } 1715 | 1716 | __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) 1717 | { 1718 | uint32_t result; 1719 | 1720 | __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1721 | return(result); 1722 | } 1723 | 1724 | __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) 1725 | { 1726 | uint32_t result; 1727 | 1728 | __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1729 | return(result); 1730 | } 1731 | 1732 | __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) 1733 | { 1734 | uint32_t result; 1735 | 1736 | __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1737 | return(result); 1738 | } 1739 | 1740 | 1741 | __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) 1742 | { 1743 | uint32_t result; 1744 | 1745 | __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1746 | return(result); 1747 | } 1748 | 1749 | __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) 1750 | { 1751 | uint32_t result; 1752 | 1753 | __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1754 | return(result); 1755 | } 1756 | 1757 | __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) 1758 | { 1759 | uint32_t result; 1760 | 1761 | __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1762 | return(result); 1763 | } 1764 | 1765 | __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) 1766 | { 1767 | uint32_t result; 1768 | 1769 | __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1770 | return(result); 1771 | } 1772 | 1773 | __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) 1774 | { 1775 | uint32_t result; 1776 | 1777 | __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1778 | return(result); 1779 | } 1780 | 1781 | __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) 1782 | { 1783 | uint32_t result; 1784 | 1785 | __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1786 | return(result); 1787 | } 1788 | 1789 | __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) 1790 | { 1791 | uint32_t result; 1792 | 1793 | __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1794 | return(result); 1795 | } 1796 | 1797 | __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) 1798 | { 1799 | uint32_t result; 1800 | 1801 | __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1802 | return(result); 1803 | } 1804 | 1805 | __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) 1806 | { 1807 | uint32_t result; 1808 | 1809 | __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1810 | return(result); 1811 | } 1812 | 1813 | __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) 1814 | { 1815 | uint32_t result; 1816 | 1817 | __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1818 | return(result); 1819 | } 1820 | 1821 | __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) 1822 | { 1823 | uint32_t result; 1824 | 1825 | __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1826 | return(result); 1827 | } 1828 | 1829 | __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) 1830 | { 1831 | uint32_t result; 1832 | 1833 | __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1834 | return(result); 1835 | } 1836 | 1837 | __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) 1838 | { 1839 | uint32_t result; 1840 | 1841 | __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1842 | return(result); 1843 | } 1844 | 1845 | __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) 1846 | { 1847 | uint32_t result; 1848 | 1849 | __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1850 | return(result); 1851 | } 1852 | 1853 | __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) 1854 | { 1855 | uint32_t result; 1856 | 1857 | __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1858 | return(result); 1859 | } 1860 | 1861 | __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) 1862 | { 1863 | uint32_t result; 1864 | 1865 | __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1866 | return(result); 1867 | } 1868 | 1869 | __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) 1870 | { 1871 | uint32_t result; 1872 | 1873 | __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1874 | return(result); 1875 | } 1876 | 1877 | __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) 1878 | { 1879 | uint32_t result; 1880 | 1881 | __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1882 | return(result); 1883 | } 1884 | 1885 | __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) 1886 | { 1887 | uint32_t result; 1888 | 1889 | __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1890 | return(result); 1891 | } 1892 | 1893 | __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) 1894 | { 1895 | uint32_t result; 1896 | 1897 | __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1898 | return(result); 1899 | } 1900 | 1901 | __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) 1902 | { 1903 | uint32_t result; 1904 | 1905 | __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1906 | return(result); 1907 | } 1908 | 1909 | __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) 1910 | { 1911 | uint32_t result; 1912 | 1913 | __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1914 | return(result); 1915 | } 1916 | 1917 | __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) 1918 | { 1919 | uint32_t result; 1920 | 1921 | __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1922 | return(result); 1923 | } 1924 | 1925 | __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) 1926 | { 1927 | uint32_t result; 1928 | 1929 | __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1930 | return(result); 1931 | } 1932 | 1933 | __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) 1934 | { 1935 | uint32_t result; 1936 | 1937 | __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1938 | return(result); 1939 | } 1940 | 1941 | __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) 1942 | { 1943 | uint32_t result; 1944 | 1945 | __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1946 | return(result); 1947 | } 1948 | 1949 | #define __SSAT16(ARG1, ARG2) \ 1950 | __extension__ \ 1951 | ({ \ 1952 | int32_t __RES, __ARG1 = (ARG1); \ 1953 | __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 1954 | __RES; \ 1955 | }) 1956 | 1957 | #define __USAT16(ARG1, ARG2) \ 1958 | __extension__ \ 1959 | ({ \ 1960 | uint32_t __RES, __ARG1 = (ARG1); \ 1961 | __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 1962 | __RES; \ 1963 | }) 1964 | 1965 | __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) 1966 | { 1967 | uint32_t result; 1968 | 1969 | __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); 1970 | return(result); 1971 | } 1972 | 1973 | __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) 1974 | { 1975 | uint32_t result; 1976 | 1977 | __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1978 | return(result); 1979 | } 1980 | 1981 | __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) 1982 | { 1983 | uint32_t result; 1984 | 1985 | __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); 1986 | return(result); 1987 | } 1988 | 1989 | __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) 1990 | { 1991 | uint32_t result; 1992 | if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { 1993 | __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); 1994 | } else { 1995 | result = __SXTB16(__ROR(op1, rotate)) ; 1996 | } 1997 | return result; 1998 | } 1999 | 2000 | __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) 2001 | { 2002 | uint32_t result; 2003 | 2004 | __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2005 | return(result); 2006 | } 2007 | 2008 | __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) 2009 | { 2010 | uint32_t result; 2011 | if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { 2012 | __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); 2013 | } else { 2014 | result = __SXTAB16(op1, __ROR(op2, rotate)); 2015 | } 2016 | return result; 2017 | } 2018 | 2019 | 2020 | __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) 2021 | { 2022 | uint32_t result; 2023 | 2024 | __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2025 | return(result); 2026 | } 2027 | 2028 | __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) 2029 | { 2030 | uint32_t result; 2031 | 2032 | __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2033 | return(result); 2034 | } 2035 | 2036 | __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) 2037 | { 2038 | uint32_t result; 2039 | 2040 | __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 2041 | return(result); 2042 | } 2043 | 2044 | __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) 2045 | { 2046 | uint32_t result; 2047 | 2048 | __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 2049 | return(result); 2050 | } 2051 | 2052 | __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) 2053 | { 2054 | union llreg_u{ 2055 | uint32_t w32[2]; 2056 | uint64_t w64; 2057 | } llr; 2058 | llr.w64 = acc; 2059 | 2060 | #ifndef __ARMEB__ /* Little endian */ 2061 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 2062 | #else /* Big endian */ 2063 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 2064 | #endif 2065 | 2066 | return(llr.w64); 2067 | } 2068 | 2069 | __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) 2070 | { 2071 | union llreg_u{ 2072 | uint32_t w32[2]; 2073 | uint64_t w64; 2074 | } llr; 2075 | llr.w64 = acc; 2076 | 2077 | #ifndef __ARMEB__ /* Little endian */ 2078 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 2079 | #else /* Big endian */ 2080 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 2081 | #endif 2082 | 2083 | return(llr.w64); 2084 | } 2085 | 2086 | __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) 2087 | { 2088 | uint32_t result; 2089 | 2090 | __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2091 | return(result); 2092 | } 2093 | 2094 | __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) 2095 | { 2096 | uint32_t result; 2097 | 2098 | __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2099 | return(result); 2100 | } 2101 | 2102 | __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) 2103 | { 2104 | uint32_t result; 2105 | 2106 | __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 2107 | return(result); 2108 | } 2109 | 2110 | __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) 2111 | { 2112 | uint32_t result; 2113 | 2114 | __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 2115 | return(result); 2116 | } 2117 | 2118 | __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) 2119 | { 2120 | union llreg_u{ 2121 | uint32_t w32[2]; 2122 | uint64_t w64; 2123 | } llr; 2124 | llr.w64 = acc; 2125 | 2126 | #ifndef __ARMEB__ /* Little endian */ 2127 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 2128 | #else /* Big endian */ 2129 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 2130 | #endif 2131 | 2132 | return(llr.w64); 2133 | } 2134 | 2135 | __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) 2136 | { 2137 | union llreg_u{ 2138 | uint32_t w32[2]; 2139 | uint64_t w64; 2140 | } llr; 2141 | llr.w64 = acc; 2142 | 2143 | #ifndef __ARMEB__ /* Little endian */ 2144 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 2145 | #else /* Big endian */ 2146 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 2147 | #endif 2148 | 2149 | return(llr.w64); 2150 | } 2151 | 2152 | __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) 2153 | { 2154 | uint32_t result; 2155 | 2156 | __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2157 | return(result); 2158 | } 2159 | 2160 | __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) 2161 | { 2162 | int32_t result; 2163 | 2164 | __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2165 | return(result); 2166 | } 2167 | 2168 | __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) 2169 | { 2170 | int32_t result; 2171 | 2172 | __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 2173 | return(result); 2174 | } 2175 | 2176 | 2177 | #define __PKHBT(ARG1,ARG2,ARG3) \ 2178 | __extension__ \ 2179 | ({ \ 2180 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ 2181 | __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ 2182 | __RES; \ 2183 | }) 2184 | 2185 | #define __PKHTB(ARG1,ARG2,ARG3) \ 2186 | __extension__ \ 2187 | ({ \ 2188 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ 2189 | if (ARG3 == 0) \ 2190 | __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ 2191 | else \ 2192 | __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ 2193 | __RES; \ 2194 | }) 2195 | 2196 | 2197 | __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) 2198 | { 2199 | int32_t result; 2200 | 2201 | __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); 2202 | return(result); 2203 | } 2204 | 2205 | #endif /* (__ARM_FEATURE_DSP == 1) */ 2206 | /*@} end of group CMSIS_SIMD_intrinsics */ 2207 | 2208 | 2209 | #pragma GCC diagnostic pop 2210 | 2211 | #endif /* __CMSIS_GCC_H */ 2212 | -------------------------------------------------------------------------------- /vendor/CMSIS/CMSIS/Core/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.5 5 | * @date 02. February 2022 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2022 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /vendor/CMSIS/CMSIS/Core/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.1.2 5 | * @date 25. May 2020 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2020 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ 109 | (((MPU_RASR_ENABLE_Msk)))) 110 | 111 | /** 112 | * MPU Region Attribute and Size Register Value 113 | * 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 117 | * \param IsShareable Region is shareable between multiple bus masters. 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 120 | * \param SubRegionDisable Sub-region disable field. 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. 122 | */ 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 125 | 126 | /** 127 | * MPU Memory Access Attribute for strongly ordered memory. 128 | * - TEX: 000b 129 | * - Shareable 130 | * - Non-cacheable 131 | * - Non-bufferable 132 | */ 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 134 | 135 | /** 136 | * MPU Memory Access Attribute for device memory. 137 | * - TEX: 000b (if shareable) or 010b (if non-shareable) 138 | * - Shareable or non-shareable 139 | * - Non-cacheable 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 141 | * 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. 143 | */ 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 145 | 146 | /** 147 | * MPU Memory Access Attribute for normal memory. 148 | * - TEX: 1BBb (reflecting outer cacheability rules) 149 | * - Shareable or non-shareable 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 152 | * 153 | * \param OuterCp Configures the outer cache policy. 154 | * \param InnerCp Configures the inner cache policy. 155 | * \param IsShareable Configures the memory as shareable or non-shareable. 156 | */ 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute non-cacheable policy. 161 | */ 162 | #define ARM_MPU_CACHEP_NOCACHE 0U 163 | 164 | /** 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. 166 | */ 167 | #define ARM_MPU_CACHEP_WB_WRA 1U 168 | 169 | /** 170 | * MPU Memory Access Attribute write-through, no write allocate policy. 171 | */ 172 | #define ARM_MPU_CACHEP_WT_NWA 2U 173 | 174 | /** 175 | * MPU Memory Access Attribute write-back, no write allocate policy. 176 | */ 177 | #define ARM_MPU_CACHEP_WB_NWA 3U 178 | 179 | 180 | /** 181 | * Struct for a single MPU Region 182 | */ 183 | typedef struct { 184 | uint32_t RBAR; //!< The region base address register value (RBAR) 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 186 | } ARM_MPU_Region_t; 187 | 188 | /** Enable the MPU. 189 | * \param MPU_Control Default access permissions for unconfigured regions. 190 | */ 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 192 | { 193 | __DMB(); 194 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 195 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 196 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 197 | #endif 198 | __DSB(); 199 | __ISB(); 200 | } 201 | 202 | /** Disable the MPU. 203 | */ 204 | __STATIC_INLINE void ARM_MPU_Disable(void) 205 | { 206 | __DMB(); 207 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 208 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 209 | #endif 210 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 211 | __DSB(); 212 | __ISB(); 213 | } 214 | 215 | /** Clear and disable the given MPU region. 216 | * \param rnr Region number to be cleared. 217 | */ 218 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 219 | { 220 | MPU->RNR = rnr; 221 | MPU->RASR = 0U; 222 | } 223 | 224 | /** Configure an MPU region. 225 | * \param rbar Value for RBAR register. 226 | * \param rasr Value for RASR register. 227 | */ 228 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 229 | { 230 | MPU->RBAR = rbar; 231 | MPU->RASR = rasr; 232 | } 233 | 234 | /** Configure the given MPU region. 235 | * \param rnr Region number to be configured. 236 | * \param rbar Value for RBAR register. 237 | * \param rasr Value for RASR register. 238 | */ 239 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 240 | { 241 | MPU->RNR = rnr; 242 | MPU->RBAR = rbar; 243 | MPU->RASR = rasr; 244 | } 245 | 246 | /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). 247 | * \param dst Destination data is copied to. 248 | * \param src Source data is copied from. 249 | * \param len Amount of data words to be copied. 250 | */ 251 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 252 | { 253 | uint32_t i; 254 | for (i = 0U; i < len; ++i) 255 | { 256 | dst[i] = src[i]; 257 | } 258 | } 259 | 260 | /** Load the given number of MPU regions from a table. 261 | * \param table Pointer to the MPU configuration table. 262 | * \param cnt Amount of regions to be configured. 263 | */ 264 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 265 | { 266 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 267 | while (cnt > MPU_TYPE_RALIASES) { 268 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 269 | table += MPU_TYPE_RALIASES; 270 | cnt -= MPU_TYPE_RALIASES; 271 | } 272 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 273 | } 274 | 275 | #endif 276 | -------------------------------------------------------------------------------- /vendor/CMSIS/Device/ST/STM32F4/Include/stm32f4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32F4xx device used in the target application 11 | * - To use or not the peripheral's drivers in application code(i.e. 12 | * code will be based on direct access to peripheral's registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | * Copyright (c) 2017 STMicroelectronics. 20 | * All rights reserved. 21 | * 22 | * This software is licensed under terms that can be found in the LICENSE file 23 | * in the root directory of this software component. 24 | * If no LICENSE file comes with this software, it is provided AS-IS. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /** @addtogroup CMSIS 30 | * @{ 31 | */ 32 | 33 | /** @addtogroup stm32f4xx 34 | * @{ 35 | */ 36 | 37 | #ifndef __STM32F4xx_H 38 | #define __STM32F4xx_H 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif /* __cplusplus */ 43 | 44 | /** @addtogroup Library_configuration_section 45 | * @{ 46 | */ 47 | 48 | /** 49 | * @brief STM32 Family 50 | */ 51 | #if !defined (STM32F4) 52 | #define STM32F4 53 | #endif /* STM32F4 */ 54 | 55 | /* Uncomment the line below according to the target STM32 device used in your 56 | application 57 | */ 58 | #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ 59 | !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ 60 | !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ 61 | !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ 62 | !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \ 63 | !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) 64 | /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ 65 | /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ 66 | /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ 67 | /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ 68 | /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ 69 | /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ 70 | /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 71 | STM32F439NI, STM32F429IG and STM32F429II Devices */ 72 | /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 73 | STM32F439NI, STM32F439IG and STM32F439II Devices */ 74 | /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ 75 | /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ 76 | /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ 77 | /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ 78 | /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ 79 | /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ 80 | /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 81 | and STM32F446ZE Devices */ 82 | /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 83 | STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ 84 | /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 85 | and STM32F479NG Devices */ 86 | /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */ 87 | /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */ 88 | /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */ 89 | /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */ 90 | /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, 91 | STM32F413RG, STM32F413VG and STM32F413ZG Devices */ 92 | /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */ 93 | #endif 94 | 95 | /* Tip: To avoid modifying this file each time you need to switch between these 96 | devices, you can define the device in your toolchain compiler preprocessor. 97 | */ 98 | #if !defined (USE_HAL_DRIVER) 99 | /** 100 | * @brief Comment the line below if you will not use the peripherals drivers. 101 | In this case, these drivers will not be included and the application code will 102 | be based on direct access to peripherals registers 103 | */ 104 | /*#define USE_HAL_DRIVER */ 105 | #endif /* USE_HAL_DRIVER */ 106 | 107 | /** 108 | * @brief CMSIS version number V2.6.8 109 | */ 110 | #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ 111 | #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ 112 | #define __STM32F4xx_CMSIS_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ 113 | #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 114 | #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ 115 | |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ 116 | |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ 117 | |(__STM32F4xx_CMSIS_VERSION_RC)) 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @addtogroup Device_Included 124 | * @{ 125 | */ 126 | 127 | #if defined(STM32F405xx) 128 | #include "stm32f405xx.h" 129 | #elif defined(STM32F415xx) 130 | #include "stm32f415xx.h" 131 | #elif defined(STM32F407xx) 132 | #include "stm32f407xx.h" 133 | #elif defined(STM32F417xx) 134 | #include "stm32f417xx.h" 135 | #elif defined(STM32F427xx) 136 | #include "stm32f427xx.h" 137 | #elif defined(STM32F437xx) 138 | #include "stm32f437xx.h" 139 | #elif defined(STM32F429xx) 140 | #include "stm32f429xx.h" 141 | #elif defined(STM32F439xx) 142 | #include "stm32f439xx.h" 143 | #elif defined(STM32F401xC) 144 | #include "stm32f401xc.h" 145 | #elif defined(STM32F401xE) 146 | #include "stm32f401xe.h" 147 | #elif defined(STM32F410Tx) 148 | #include "stm32f410tx.h" 149 | #elif defined(STM32F410Cx) 150 | #include "stm32f410cx.h" 151 | #elif defined(STM32F410Rx) 152 | #include "stm32f410rx.h" 153 | #elif defined(STM32F411xE) 154 | #include "stm32f411xe.h" 155 | #elif defined(STM32F446xx) 156 | #include "stm32f446xx.h" 157 | #elif defined(STM32F469xx) 158 | #include "stm32f469xx.h" 159 | #elif defined(STM32F479xx) 160 | #include "stm32f479xx.h" 161 | #elif defined(STM32F412Cx) 162 | #include "stm32f412cx.h" 163 | #elif defined(STM32F412Zx) 164 | #include "stm32f412zx.h" 165 | #elif defined(STM32F412Rx) 166 | #include "stm32f412rx.h" 167 | #elif defined(STM32F412Vx) 168 | #include "stm32f412vx.h" 169 | #elif defined(STM32F413xx) 170 | #include "stm32f413xx.h" 171 | #elif defined(STM32F423xx) 172 | #include "stm32f423xx.h" 173 | #else 174 | #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" 175 | #endif 176 | 177 | /** 178 | * @} 179 | */ 180 | 181 | /** @addtogroup Exported_types 182 | * @{ 183 | */ 184 | typedef enum 185 | { 186 | RESET = 0U, 187 | SET = !RESET 188 | } FlagStatus, ITStatus; 189 | 190 | typedef enum 191 | { 192 | DISABLE = 0U, 193 | ENABLE = !DISABLE 194 | } FunctionalState; 195 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 196 | 197 | typedef enum 198 | { 199 | SUCCESS = 0U, 200 | ERROR = !SUCCESS 201 | } ErrorStatus; 202 | 203 | /** 204 | * @} 205 | */ 206 | 207 | 208 | /** @addtogroup Exported_macro 209 | * @{ 210 | */ 211 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 212 | 213 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 214 | 215 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 216 | 217 | #define CLEAR_REG(REG) ((REG) = (0x0)) 218 | 219 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 220 | 221 | #define READ_REG(REG) ((REG)) 222 | 223 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 224 | 225 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 226 | 227 | /* Use of CMSIS compiler intrinsics for register exclusive access */ 228 | /* Atomic 32-bit register access macro to set one or several bits */ 229 | #define ATOMIC_SET_BIT(REG, BIT) \ 230 | do { \ 231 | uint32_t val; \ 232 | do { \ 233 | val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ 234 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 235 | } while(0) 236 | 237 | /* Atomic 32-bit register access macro to clear one or several bits */ 238 | #define ATOMIC_CLEAR_BIT(REG, BIT) \ 239 | do { \ 240 | uint32_t val; \ 241 | do { \ 242 | val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ 243 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 244 | } while(0) 245 | 246 | /* Atomic 32-bit register access macro to clear and set one or several bits */ 247 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 248 | do { \ 249 | uint32_t val; \ 250 | do { \ 251 | val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 252 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 253 | } while(0) 254 | 255 | /* Atomic 16-bit register access macro to set one or several bits */ 256 | #define ATOMIC_SETH_BIT(REG, BIT) \ 257 | do { \ 258 | uint16_t val; \ 259 | do { \ 260 | val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ 261 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 262 | } while(0) 263 | 264 | /* Atomic 16-bit register access macro to clear one or several bits */ 265 | #define ATOMIC_CLEARH_BIT(REG, BIT) \ 266 | do { \ 267 | uint16_t val; \ 268 | do { \ 269 | val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ 270 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 271 | } while(0) 272 | 273 | /* Atomic 16-bit register access macro to clear and set one or several bits */ 274 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ 275 | do { \ 276 | uint16_t val; \ 277 | do { \ 278 | val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 279 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 280 | } while(0) 281 | 282 | /** 283 | * @} 284 | */ 285 | 286 | #if defined (USE_HAL_DRIVER) 287 | #include "stm32f4xx_hal.h" 288 | #endif /* USE_HAL_DRIVER */ 289 | 290 | #ifdef __cplusplus 291 | } 292 | #endif /* __cplusplus */ 293 | 294 | #endif /* __STM32F4xx_H */ 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | -------------------------------------------------------------------------------- /vendor/CMSIS/Device/ST/STM32F4/Include/system_stm32f4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /** @addtogroup CMSIS 20 | * @{ 21 | */ 22 | 23 | /** @addtogroup stm32f4xx_system 24 | * @{ 25 | */ 26 | 27 | /** 28 | * @brief Define to prevent recursive inclusion 29 | */ 30 | #ifndef __SYSTEM_STM32F4XX_H 31 | #define __SYSTEM_STM32F4XX_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /** @addtogroup STM32F4xx_System_Includes 38 | * @{ 39 | */ 40 | 41 | /** 42 | * @} 43 | */ 44 | 45 | 46 | /** @addtogroup STM32F4xx_System_Exported_types 47 | * @{ 48 | */ 49 | /* This variable is updated in three ways: 50 | 1) by calling CMSIS function SystemCoreClockUpdate() 51 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 52 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 53 | Note: If you use this function to configure the system clock; then there 54 | is no need to call the 2 first functions listed above, since SystemCoreClock 55 | variable is updated automatically. 56 | */ 57 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 58 | 59 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 60 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32F4xx_System_Exported_Constants 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32F4xx_System_Exported_Macros 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @addtogroup STM32F4xx_System_Exported_Functions 83 | * @{ 84 | */ 85 | 86 | extern void SystemInit(void); 87 | extern void SystemCoreClockUpdate(void); 88 | /** 89 | * @} 90 | */ 91 | 92 | #ifdef __cplusplus 93 | } 94 | #endif 95 | 96 | #endif /*__SYSTEM_STM32F4XX_H */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | -------------------------------------------------------------------------------- /vendor/CMSIS/Device/ST/STM32F4/LICENSE.md: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. 66 | 67 | END OF TERMS AND CONDITIONS 68 | 69 | APPENDIX: 70 | 71 | Copyright [2019] [STMicroelectronics] 72 | 73 | Licensed under the Apache License, Version 2.0 (the "License"); 74 | you may not use this file except in compliance with the License. 75 | You may obtain a copy of the License at 76 | 77 | http://www.apache.org/licenses/LICENSE-2.0 78 | 79 | Unless required by applicable law or agreed to in writing, software 80 | distributed under the License is distributed on an "AS IS" BASIS, 81 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 82 | See the License for the specific language governing permissions and 83 | limitations under the License. 84 | -------------------------------------------------------------------------------- /vendor/CMSIS/Device/ST/STM32F4/README.md: -------------------------------------------------------------------------------- 1 | # STM32CubeF4 CMSIS Device MCU Component 2 | 3 | ![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_f4.svg?color=brightgreen) 4 | 5 | ## Overview 6 | 7 | **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. 8 | 9 | **STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. 10 | * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. 11 | * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. 12 | * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. 13 | * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... 14 | * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. 15 | 16 | Two models of publication are proposed for the STM32Cube embedded software: 17 | * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). 18 | * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. 19 | 20 | ## Description 21 | 22 | This **cmsis_device_f4** MCU component repo is one element of the STM32CubeF4 MCU embedded software package, providing the **cmsis device** part. 23 | 24 | ## Release note 25 | 26 | Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_f4/blob/master/Release_Notes.html). 27 | 28 | ## Compatibility information 29 | 30 | In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: 31 | 32 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package 33 | --------------- | ---------- | ------------------------------------- 34 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 35 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 36 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 37 | Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 38 | Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 39 | Tag v2.6.8 | Tag v5.4.0_cm4 | Tag v1.27.0 40 | 41 | The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). 42 | 43 | ## Troubleshooting 44 | If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_f4/issues/new). 45 | 46 | For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus). -------------------------------------------------------------------------------- /vendor/CMSIS/Device/ST/STM32F4/Source/Templates/system_stm32f4xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f4xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 22 | ****************************************************************************** 23 | * @attention 24 | * 25 | * Copyright (c) 2017 STMicroelectronics. 26 | * All rights reserved. 27 | * 28 | * This software is licensed under terms that can be found in the LICENSE file 29 | * in the root directory of this software component. 30 | * If no LICENSE file comes with this software, it is provided AS-IS. 31 | * 32 | ****************************************************************************** 33 | */ 34 | 35 | /** @addtogroup CMSIS 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup stm32f4xx_system 40 | * @{ 41 | */ 42 | 43 | /** @addtogroup STM32F4xx_System_Private_Includes 44 | * @{ 45 | */ 46 | 47 | 48 | #include "stm32f4xx.h" 49 | 50 | #if !defined (HSE_VALUE) 51 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ 52 | #endif /* HSE_VALUE */ 53 | 54 | #if !defined (HSI_VALUE) 55 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 56 | #endif /* HSI_VALUE */ 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 63 | * @{ 64 | */ 65 | 66 | /** 67 | * @} 68 | */ 69 | 70 | /** @addtogroup STM32F4xx_System_Private_Defines 71 | * @{ 72 | */ 73 | 74 | /************************* Miscellaneous Configuration ************************/ 75 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ 76 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 77 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 78 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 79 | /* #define DATA_IN_ExtSRAM */ 80 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ 81 | STM32F412Zx || STM32F412Vx */ 82 | 83 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 84 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 85 | /* #define DATA_IN_ExtSDRAM */ 86 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ 87 | STM32F479xx */ 88 | 89 | /* Note: Following vector table addresses must be defined in line with linker 90 | configuration. */ 91 | /*!< Uncomment the following line if you need to relocate the vector table 92 | anywhere in Flash or Sram, else the vector table is kept at the automatic 93 | remap of boot address selected */ 94 | /* #define USER_VECT_TAB_ADDRESS */ 95 | 96 | #if defined(USER_VECT_TAB_ADDRESS) 97 | /*!< Uncomment the following line if you need to relocate your vector Table 98 | in Sram else user remap will be done in Flash. */ 99 | /* #define VECT_TAB_SRAM */ 100 | #if defined(VECT_TAB_SRAM) 101 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 102 | This value must be a multiple of 0x200. */ 103 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 104 | This value must be a multiple of 0x200. */ 105 | #else 106 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 107 | This value must be a multiple of 0x200. */ 108 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 109 | This value must be a multiple of 0x200. */ 110 | #endif /* VECT_TAB_SRAM */ 111 | #endif /* USER_VECT_TAB_ADDRESS */ 112 | /******************************************************************************/ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /** @addtogroup STM32F4xx_System_Private_Macros 119 | * @{ 120 | */ 121 | 122 | /** 123 | * @} 124 | */ 125 | 126 | /** @addtogroup STM32F4xx_System_Private_Variables 127 | * @{ 128 | */ 129 | /* This variable is updated in three ways: 130 | 1) by calling CMSIS function SystemCoreClockUpdate() 131 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 132 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 133 | Note: If you use this function to configure the system clock; then there 134 | is no need to call the 2 first functions listed above, since SystemCoreClock 135 | variable is updated automatically. 136 | */ 137 | uint32_t SystemCoreClock = 16000000; 138 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 139 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 140 | /** 141 | * @} 142 | */ 143 | 144 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes 145 | * @{ 146 | */ 147 | 148 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 149 | static void SystemInit_ExtMemCtl(void); 150 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /** @addtogroup STM32F4xx_System_Private_Functions 157 | * @{ 158 | */ 159 | 160 | /** 161 | * @brief Setup the microcontroller system 162 | * Initialize the FPU setting, vector table location and External memory 163 | * configuration. 164 | * @param None 165 | * @retval None 166 | */ 167 | void SystemInit(void) 168 | { 169 | /* FPU settings ------------------------------------------------------------*/ 170 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 171 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 172 | #endif 173 | 174 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 175 | SystemInit_ExtMemCtl(); 176 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 177 | 178 | /* Configure the Vector Table location -------------------------------------*/ 179 | #if defined(USER_VECT_TAB_ADDRESS) 180 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 181 | #endif /* USER_VECT_TAB_ADDRESS */ 182 | } 183 | 184 | /** 185 | * @brief Update SystemCoreClock variable according to Clock Register Values. 186 | * The SystemCoreClock variable contains the core clock (HCLK), it can 187 | * be used by the user application to setup the SysTick timer or configure 188 | * other parameters. 189 | * 190 | * @note Each time the core clock (HCLK) changes, this function must be called 191 | * to update SystemCoreClock variable value. Otherwise, any configuration 192 | * based on this variable will be incorrect. 193 | * 194 | * @note - The system frequency computed by this function is not the real 195 | * frequency in the chip. It is calculated based on the predefined 196 | * constant and the selected clock source: 197 | * 198 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 199 | * 200 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 201 | * 202 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 203 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 204 | * 205 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 206 | * 16 MHz) but the real value may vary depending on the variations 207 | * in voltage and temperature. 208 | * 209 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value 210 | * depends on the application requirements), user has to ensure that HSE_VALUE 211 | * is same as the real frequency of the crystal used. Otherwise, this function 212 | * may have wrong result. 213 | * 214 | * - The result of this function could be not correct when using fractional 215 | * value for HSE crystal. 216 | * 217 | * @param None 218 | * @retval None 219 | */ 220 | void SystemCoreClockUpdate(void) 221 | { 222 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 223 | 224 | /* Get SYSCLK source -------------------------------------------------------*/ 225 | tmp = RCC->CFGR & RCC_CFGR_SWS; 226 | 227 | switch (tmp) 228 | { 229 | case 0x00: /* HSI used as system clock source */ 230 | SystemCoreClock = HSI_VALUE; 231 | break; 232 | case 0x04: /* HSE used as system clock source */ 233 | SystemCoreClock = HSE_VALUE; 234 | break; 235 | case 0x08: /* PLL used as system clock source */ 236 | 237 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 238 | SYSCLK = PLL_VCO / PLL_P 239 | */ 240 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 241 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 242 | 243 | if (pllsource != 0) 244 | { 245 | /* HSE used as PLL clock source */ 246 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 247 | } 248 | else 249 | { 250 | /* HSI used as PLL clock source */ 251 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 252 | } 253 | 254 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 255 | SystemCoreClock = pllvco/pllp; 256 | break; 257 | default: 258 | SystemCoreClock = HSI_VALUE; 259 | break; 260 | } 261 | /* Compute HCLK frequency --------------------------------------------------*/ 262 | /* Get HCLK prescaler */ 263 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 264 | /* HCLK frequency */ 265 | SystemCoreClock >>= tmp; 266 | } 267 | 268 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) 269 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 270 | || defined(STM32F469xx) || defined(STM32F479xx) 271 | /** 272 | * @brief Setup the external memory controller. 273 | * Called in startup_stm32f4xx.s before jump to main. 274 | * This function configures the external memories (SRAM/SDRAM) 275 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 276 | * @param None 277 | * @retval None 278 | */ 279 | void SystemInit_ExtMemCtl(void) 280 | { 281 | __IO uint32_t tmp = 0x00; 282 | 283 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 284 | register __IO uint32_t index; 285 | 286 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ 287 | RCC->AHB1ENR |= 0x000001F8; 288 | 289 | /* Delay after an RCC peripheral clock enabling */ 290 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 291 | 292 | /* Connect PDx pins to FMC Alternate function */ 293 | GPIOD->AFR[0] = 0x00CCC0CC; 294 | GPIOD->AFR[1] = 0xCCCCCCCC; 295 | /* Configure PDx pins in Alternate function mode */ 296 | GPIOD->MODER = 0xAAAA0A8A; 297 | /* Configure PDx pins speed to 100 MHz */ 298 | GPIOD->OSPEEDR = 0xFFFF0FCF; 299 | /* Configure PDx pins Output type to push-pull */ 300 | GPIOD->OTYPER = 0x00000000; 301 | /* No pull-up, pull-down for PDx pins */ 302 | GPIOD->PUPDR = 0x00000000; 303 | 304 | /* Connect PEx pins to FMC Alternate function */ 305 | GPIOE->AFR[0] = 0xC00CC0CC; 306 | GPIOE->AFR[1] = 0xCCCCCCCC; 307 | /* Configure PEx pins in Alternate function mode */ 308 | GPIOE->MODER = 0xAAAA828A; 309 | /* Configure PEx pins speed to 100 MHz */ 310 | GPIOE->OSPEEDR = 0xFFFFC3CF; 311 | /* Configure PEx pins Output type to push-pull */ 312 | GPIOE->OTYPER = 0x00000000; 313 | /* No pull-up, pull-down for PEx pins */ 314 | GPIOE->PUPDR = 0x00000000; 315 | 316 | /* Connect PFx pins to FMC Alternate function */ 317 | GPIOF->AFR[0] = 0xCCCCCCCC; 318 | GPIOF->AFR[1] = 0xCCCCCCCC; 319 | /* Configure PFx pins in Alternate function mode */ 320 | GPIOF->MODER = 0xAA800AAA; 321 | /* Configure PFx pins speed to 50 MHz */ 322 | GPIOF->OSPEEDR = 0xAA800AAA; 323 | /* Configure PFx pins Output type to push-pull */ 324 | GPIOF->OTYPER = 0x00000000; 325 | /* No pull-up, pull-down for PFx pins */ 326 | GPIOF->PUPDR = 0x00000000; 327 | 328 | /* Connect PGx pins to FMC Alternate function */ 329 | GPIOG->AFR[0] = 0xCCCCCCCC; 330 | GPIOG->AFR[1] = 0xCCCCCCCC; 331 | /* Configure PGx pins in Alternate function mode */ 332 | GPIOG->MODER = 0xAAAAAAAA; 333 | /* Configure PGx pins speed to 50 MHz */ 334 | GPIOG->OSPEEDR = 0xAAAAAAAA; 335 | /* Configure PGx pins Output type to push-pull */ 336 | GPIOG->OTYPER = 0x00000000; 337 | /* No pull-up, pull-down for PGx pins */ 338 | GPIOG->PUPDR = 0x00000000; 339 | 340 | /* Connect PHx pins to FMC Alternate function */ 341 | GPIOH->AFR[0] = 0x00C0CC00; 342 | GPIOH->AFR[1] = 0xCCCCCCCC; 343 | /* Configure PHx pins in Alternate function mode */ 344 | GPIOH->MODER = 0xAAAA08A0; 345 | /* Configure PHx pins speed to 50 MHz */ 346 | GPIOH->OSPEEDR = 0xAAAA08A0; 347 | /* Configure PHx pins Output type to push-pull */ 348 | GPIOH->OTYPER = 0x00000000; 349 | /* No pull-up, pull-down for PHx pins */ 350 | GPIOH->PUPDR = 0x00000000; 351 | 352 | /* Connect PIx pins to FMC Alternate function */ 353 | GPIOI->AFR[0] = 0xCCCCCCCC; 354 | GPIOI->AFR[1] = 0x00000CC0; 355 | /* Configure PIx pins in Alternate function mode */ 356 | GPIOI->MODER = 0x0028AAAA; 357 | /* Configure PIx pins speed to 50 MHz */ 358 | GPIOI->OSPEEDR = 0x0028AAAA; 359 | /* Configure PIx pins Output type to push-pull */ 360 | GPIOI->OTYPER = 0x00000000; 361 | /* No pull-up, pull-down for PIx pins */ 362 | GPIOI->PUPDR = 0x00000000; 363 | 364 | /*-- FMC Configuration -------------------------------------------------------*/ 365 | /* Enable the FMC interface clock */ 366 | RCC->AHB3ENR |= 0x00000001; 367 | /* Delay after an RCC peripheral clock enabling */ 368 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 369 | 370 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 371 | FMC_Bank5_6->SDTR[0] = 0x01115351; 372 | 373 | /* SDRAM initialization sequence */ 374 | /* Clock enable command */ 375 | FMC_Bank5_6->SDCMR = 0x00000011; 376 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 377 | while((tmpreg != 0) && (timeout-- > 0)) 378 | { 379 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 380 | } 381 | 382 | /* Delay */ 383 | for (index = 0; index<1000; index++); 384 | 385 | /* PALL command */ 386 | FMC_Bank5_6->SDCMR = 0x00000012; 387 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 388 | timeout = 0xFFFF; 389 | while((tmpreg != 0) && (timeout-- > 0)) 390 | { 391 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 392 | } 393 | 394 | /* Auto refresh command */ 395 | FMC_Bank5_6->SDCMR = 0x00000073; 396 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 397 | timeout = 0xFFFF; 398 | while((tmpreg != 0) && (timeout-- > 0)) 399 | { 400 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 401 | } 402 | 403 | /* MRD register program */ 404 | FMC_Bank5_6->SDCMR = 0x00046014; 405 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 406 | timeout = 0xFFFF; 407 | while((tmpreg != 0) && (timeout-- > 0)) 408 | { 409 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 410 | } 411 | 412 | /* Set refresh count */ 413 | tmpreg = FMC_Bank5_6->SDRTR; 414 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 415 | 416 | /* Disable write protection */ 417 | tmpreg = FMC_Bank5_6->SDCR[0]; 418 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 419 | 420 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 421 | /* Configure and enable Bank1_SRAM2 */ 422 | FMC_Bank1->BTCR[2] = 0x00001011; 423 | FMC_Bank1->BTCR[3] = 0x00000201; 424 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 425 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 426 | #if defined(STM32F469xx) || defined(STM32F479xx) 427 | /* Configure and enable Bank1_SRAM2 */ 428 | FMC_Bank1->BTCR[2] = 0x00001091; 429 | FMC_Bank1->BTCR[3] = 0x00110212; 430 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 431 | #endif /* STM32F469xx || STM32F479xx */ 432 | 433 | (void)(tmp); 434 | } 435 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 436 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 437 | /** 438 | * @brief Setup the external memory controller. 439 | * Called in startup_stm32f4xx.s before jump to main. 440 | * This function configures the external memories (SRAM/SDRAM) 441 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 442 | * @param None 443 | * @retval None 444 | */ 445 | void SystemInit_ExtMemCtl(void) 446 | { 447 | __IO uint32_t tmp = 0x00; 448 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 449 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 450 | #if defined (DATA_IN_ExtSDRAM) 451 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 452 | register __IO uint32_t index; 453 | 454 | #if defined(STM32F446xx) 455 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface 456 | clock */ 457 | RCC->AHB1ENR |= 0x0000007D; 458 | #else 459 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 460 | clock */ 461 | RCC->AHB1ENR |= 0x000001F8; 462 | #endif /* STM32F446xx */ 463 | /* Delay after an RCC peripheral clock enabling */ 464 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 465 | 466 | #if defined(STM32F446xx) 467 | /* Connect PAx pins to FMC Alternate function */ 468 | GPIOA->AFR[0] |= 0xC0000000; 469 | GPIOA->AFR[1] |= 0x00000000; 470 | /* Configure PDx pins in Alternate function mode */ 471 | GPIOA->MODER |= 0x00008000; 472 | /* Configure PDx pins speed to 50 MHz */ 473 | GPIOA->OSPEEDR |= 0x00008000; 474 | /* Configure PDx pins Output type to push-pull */ 475 | GPIOA->OTYPER |= 0x00000000; 476 | /* No pull-up, pull-down for PDx pins */ 477 | GPIOA->PUPDR |= 0x00000000; 478 | 479 | /* Connect PCx pins to FMC Alternate function */ 480 | GPIOC->AFR[0] |= 0x00CC0000; 481 | GPIOC->AFR[1] |= 0x00000000; 482 | /* Configure PDx pins in Alternate function mode */ 483 | GPIOC->MODER |= 0x00000A00; 484 | /* Configure PDx pins speed to 50 MHz */ 485 | GPIOC->OSPEEDR |= 0x00000A00; 486 | /* Configure PDx pins Output type to push-pull */ 487 | GPIOC->OTYPER |= 0x00000000; 488 | /* No pull-up, pull-down for PDx pins */ 489 | GPIOC->PUPDR |= 0x00000000; 490 | #endif /* STM32F446xx */ 491 | 492 | /* Connect PDx pins to FMC Alternate function */ 493 | GPIOD->AFR[0] = 0x000000CC; 494 | GPIOD->AFR[1] = 0xCC000CCC; 495 | /* Configure PDx pins in Alternate function mode */ 496 | GPIOD->MODER = 0xA02A000A; 497 | /* Configure PDx pins speed to 50 MHz */ 498 | GPIOD->OSPEEDR = 0xA02A000A; 499 | /* Configure PDx pins Output type to push-pull */ 500 | GPIOD->OTYPER = 0x00000000; 501 | /* No pull-up, pull-down for PDx pins */ 502 | GPIOD->PUPDR = 0x00000000; 503 | 504 | /* Connect PEx pins to FMC Alternate function */ 505 | GPIOE->AFR[0] = 0xC00000CC; 506 | GPIOE->AFR[1] = 0xCCCCCCCC; 507 | /* Configure PEx pins in Alternate function mode */ 508 | GPIOE->MODER = 0xAAAA800A; 509 | /* Configure PEx pins speed to 50 MHz */ 510 | GPIOE->OSPEEDR = 0xAAAA800A; 511 | /* Configure PEx pins Output type to push-pull */ 512 | GPIOE->OTYPER = 0x00000000; 513 | /* No pull-up, pull-down for PEx pins */ 514 | GPIOE->PUPDR = 0x00000000; 515 | 516 | /* Connect PFx pins to FMC Alternate function */ 517 | GPIOF->AFR[0] = 0xCCCCCCCC; 518 | GPIOF->AFR[1] = 0xCCCCCCCC; 519 | /* Configure PFx pins in Alternate function mode */ 520 | GPIOF->MODER = 0xAA800AAA; 521 | /* Configure PFx pins speed to 50 MHz */ 522 | GPIOF->OSPEEDR = 0xAA800AAA; 523 | /* Configure PFx pins Output type to push-pull */ 524 | GPIOF->OTYPER = 0x00000000; 525 | /* No pull-up, pull-down for PFx pins */ 526 | GPIOF->PUPDR = 0x00000000; 527 | 528 | /* Connect PGx pins to FMC Alternate function */ 529 | GPIOG->AFR[0] = 0xCCCCCCCC; 530 | GPIOG->AFR[1] = 0xCCCCCCCC; 531 | /* Configure PGx pins in Alternate function mode */ 532 | GPIOG->MODER = 0xAAAAAAAA; 533 | /* Configure PGx pins speed to 50 MHz */ 534 | GPIOG->OSPEEDR = 0xAAAAAAAA; 535 | /* Configure PGx pins Output type to push-pull */ 536 | GPIOG->OTYPER = 0x00000000; 537 | /* No pull-up, pull-down for PGx pins */ 538 | GPIOG->PUPDR = 0x00000000; 539 | 540 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 541 | || defined(STM32F469xx) || defined(STM32F479xx) 542 | /* Connect PHx pins to FMC Alternate function */ 543 | GPIOH->AFR[0] = 0x00C0CC00; 544 | GPIOH->AFR[1] = 0xCCCCCCCC; 545 | /* Configure PHx pins in Alternate function mode */ 546 | GPIOH->MODER = 0xAAAA08A0; 547 | /* Configure PHx pins speed to 50 MHz */ 548 | GPIOH->OSPEEDR = 0xAAAA08A0; 549 | /* Configure PHx pins Output type to push-pull */ 550 | GPIOH->OTYPER = 0x00000000; 551 | /* No pull-up, pull-down for PHx pins */ 552 | GPIOH->PUPDR = 0x00000000; 553 | 554 | /* Connect PIx pins to FMC Alternate function */ 555 | GPIOI->AFR[0] = 0xCCCCCCCC; 556 | GPIOI->AFR[1] = 0x00000CC0; 557 | /* Configure PIx pins in Alternate function mode */ 558 | GPIOI->MODER = 0x0028AAAA; 559 | /* Configure PIx pins speed to 50 MHz */ 560 | GPIOI->OSPEEDR = 0x0028AAAA; 561 | /* Configure PIx pins Output type to push-pull */ 562 | GPIOI->OTYPER = 0x00000000; 563 | /* No pull-up, pull-down for PIx pins */ 564 | GPIOI->PUPDR = 0x00000000; 565 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 566 | 567 | /*-- FMC Configuration -------------------------------------------------------*/ 568 | /* Enable the FMC interface clock */ 569 | RCC->AHB3ENR |= 0x00000001; 570 | /* Delay after an RCC peripheral clock enabling */ 571 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 572 | 573 | /* Configure and enable SDRAM bank1 */ 574 | #if defined(STM32F446xx) 575 | FMC_Bank5_6->SDCR[0] = 0x00001954; 576 | #else 577 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 578 | #endif /* STM32F446xx */ 579 | FMC_Bank5_6->SDTR[0] = 0x01115351; 580 | 581 | /* SDRAM initialization sequence */ 582 | /* Clock enable command */ 583 | FMC_Bank5_6->SDCMR = 0x00000011; 584 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 585 | while((tmpreg != 0) && (timeout-- > 0)) 586 | { 587 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 588 | } 589 | 590 | /* Delay */ 591 | for (index = 0; index<1000; index++); 592 | 593 | /* PALL command */ 594 | FMC_Bank5_6->SDCMR = 0x00000012; 595 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 596 | timeout = 0xFFFF; 597 | while((tmpreg != 0) && (timeout-- > 0)) 598 | { 599 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 600 | } 601 | 602 | /* Auto refresh command */ 603 | #if defined(STM32F446xx) 604 | FMC_Bank5_6->SDCMR = 0x000000F3; 605 | #else 606 | FMC_Bank5_6->SDCMR = 0x00000073; 607 | #endif /* STM32F446xx */ 608 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 609 | timeout = 0xFFFF; 610 | while((tmpreg != 0) && (timeout-- > 0)) 611 | { 612 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 613 | } 614 | 615 | /* MRD register program */ 616 | #if defined(STM32F446xx) 617 | FMC_Bank5_6->SDCMR = 0x00044014; 618 | #else 619 | FMC_Bank5_6->SDCMR = 0x00046014; 620 | #endif /* STM32F446xx */ 621 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 622 | timeout = 0xFFFF; 623 | while((tmpreg != 0) && (timeout-- > 0)) 624 | { 625 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 626 | } 627 | 628 | /* Set refresh count */ 629 | tmpreg = FMC_Bank5_6->SDRTR; 630 | #if defined(STM32F446xx) 631 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); 632 | #else 633 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 634 | #endif /* STM32F446xx */ 635 | 636 | /* Disable write protection */ 637 | tmpreg = FMC_Bank5_6->SDCR[0]; 638 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 639 | #endif /* DATA_IN_ExtSDRAM */ 640 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 641 | 642 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 643 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 644 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 645 | 646 | #if defined(DATA_IN_ExtSRAM) 647 | /*-- GPIOs Configuration -----------------------------------------------------*/ 648 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 649 | RCC->AHB1ENR |= 0x00000078; 650 | /* Delay after an RCC peripheral clock enabling */ 651 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); 652 | 653 | /* Connect PDx pins to FMC Alternate function */ 654 | GPIOD->AFR[0] = 0x00CCC0CC; 655 | GPIOD->AFR[1] = 0xCCCCCCCC; 656 | /* Configure PDx pins in Alternate function mode */ 657 | GPIOD->MODER = 0xAAAA0A8A; 658 | /* Configure PDx pins speed to 100 MHz */ 659 | GPIOD->OSPEEDR = 0xFFFF0FCF; 660 | /* Configure PDx pins Output type to push-pull */ 661 | GPIOD->OTYPER = 0x00000000; 662 | /* No pull-up, pull-down for PDx pins */ 663 | GPIOD->PUPDR = 0x00000000; 664 | 665 | /* Connect PEx pins to FMC Alternate function */ 666 | GPIOE->AFR[0] = 0xC00CC0CC; 667 | GPIOE->AFR[1] = 0xCCCCCCCC; 668 | /* Configure PEx pins in Alternate function mode */ 669 | GPIOE->MODER = 0xAAAA828A; 670 | /* Configure PEx pins speed to 100 MHz */ 671 | GPIOE->OSPEEDR = 0xFFFFC3CF; 672 | /* Configure PEx pins Output type to push-pull */ 673 | GPIOE->OTYPER = 0x00000000; 674 | /* No pull-up, pull-down for PEx pins */ 675 | GPIOE->PUPDR = 0x00000000; 676 | 677 | /* Connect PFx pins to FMC Alternate function */ 678 | GPIOF->AFR[0] = 0x00CCCCCC; 679 | GPIOF->AFR[1] = 0xCCCC0000; 680 | /* Configure PFx pins in Alternate function mode */ 681 | GPIOF->MODER = 0xAA000AAA; 682 | /* Configure PFx pins speed to 100 MHz */ 683 | GPIOF->OSPEEDR = 0xFF000FFF; 684 | /* Configure PFx pins Output type to push-pull */ 685 | GPIOF->OTYPER = 0x00000000; 686 | /* No pull-up, pull-down for PFx pins */ 687 | GPIOF->PUPDR = 0x00000000; 688 | 689 | /* Connect PGx pins to FMC Alternate function */ 690 | GPIOG->AFR[0] = 0x00CCCCCC; 691 | GPIOG->AFR[1] = 0x000000C0; 692 | /* Configure PGx pins in Alternate function mode */ 693 | GPIOG->MODER = 0x00085AAA; 694 | /* Configure PGx pins speed to 100 MHz */ 695 | GPIOG->OSPEEDR = 0x000CAFFF; 696 | /* Configure PGx pins Output type to push-pull */ 697 | GPIOG->OTYPER = 0x00000000; 698 | /* No pull-up, pull-down for PGx pins */ 699 | GPIOG->PUPDR = 0x00000000; 700 | 701 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ 702 | /* Enable the FMC/FSMC interface clock */ 703 | RCC->AHB3ENR |= 0x00000001; 704 | 705 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 706 | /* Delay after an RCC peripheral clock enabling */ 707 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 708 | /* Configure and enable Bank1_SRAM2 */ 709 | FMC_Bank1->BTCR[2] = 0x00001011; 710 | FMC_Bank1->BTCR[3] = 0x00000201; 711 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 712 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 713 | #if defined(STM32F469xx) || defined(STM32F479xx) 714 | /* Delay after an RCC peripheral clock enabling */ 715 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 716 | /* Configure and enable Bank1_SRAM2 */ 717 | FMC_Bank1->BTCR[2] = 0x00001091; 718 | FMC_Bank1->BTCR[3] = 0x00110212; 719 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 720 | #endif /* STM32F469xx || STM32F479xx */ 721 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ 722 | || defined(STM32F412Zx) || defined(STM32F412Vx) 723 | /* Delay after an RCC peripheral clock enabling */ 724 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); 725 | /* Configure and enable Bank1_SRAM2 */ 726 | FSMC_Bank1->BTCR[2] = 0x00001011; 727 | FSMC_Bank1->BTCR[3] = 0x00000201; 728 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; 729 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ 730 | 731 | #endif /* DATA_IN_ExtSRAM */ 732 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ 733 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ 734 | (void)(tmp); 735 | } 736 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ 737 | /** 738 | * @} 739 | */ 740 | 741 | /** 742 | * @} 743 | */ 744 | 745 | /** 746 | * @} 747 | */ 748 | -------------------------------------------------------------------------------- /vendor/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions. 11 | 12 | A [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release). 13 | 14 | ## Overview of CMSIS Components 15 | 16 | The following is an list of all CMSIS components that are available. 17 | 18 | | CMSIS-... | Target Processors | Description | 19 | |:----------|:--------------------|:-------------| 20 | |[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.| 21 | |[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.| 22 | |[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.| 23 | |[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.| 24 | |[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.| 25 | |[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. | 26 | |[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM).
Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). | 27 | |[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.
Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). | 28 | |[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.| 29 | |[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. | 30 | |[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. | 31 | 32 | **Note:** CMSIS-DSP moved off into its [own repository](https://github.com/ARM-software/CMSIS-DSP), see below. 33 | 34 | ## Other related GitHub repositories 35 | 36 | | Repository | Description | 37 | |:--------------------------- |:--------------------------------------------------------- | 38 | | [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support | 39 | | [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS | 40 | | [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. | 41 | | [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system | 42 | | [CMSIS-DSP](https://github.com/ARM-software/CMSIS-DSP) | DSP library collection with hundreds of functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Armv7E-M and later devices. | 43 | | [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates | 44 | | [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series | 45 | | [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)| 46 | | [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.| 47 | 48 | 49 | ## Directory Structure 50 | 51 | | Directory | Content | 52 | |:-------------------- |:--------------------------------------------------------- | 53 | | CMSIS/Core | CMSIS-Core(M) related files (for release) | 54 | | CMSIS/Core_A | CMSIS-Core(A) related files (for release) | 55 | | CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) | 56 | | CMSIS/DAP | CMSIS-DAP related files and examples | 57 | | CMSIS/Driver | CMSIS-Driver API headers and template files | 58 | | CMSIS/NN | CMSIS-NN related files | 59 | | CMSIS/RTOS | RTOS v1 related files (for Cortex-M) | 60 | | CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) | 61 | | CMSIS/Pack | CMSIS-Pack examples and tutorials | 62 | | CMSIS/DoxyGen | Source of the documentation | 63 | | CMSIS/Utilities | Utility programs | 64 | 65 | ## Generate CMSIS Pack for Release 66 | 67 | This GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2). 68 | In order to generate a full pack one needs to have the build environment available to build these libraries. 69 | This causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s) 70 | in the future. 71 | 72 | To build a complete CMSIS pack for installation the following additional tools are required: 73 | - **doxygen.exe** Version: 1.8.6 (Documentation Generator) 74 | - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter) 75 | - **7z.exe (7-Zip)** Version: 16.02 (File Archiver) 76 | 77 | Using these tools, you can generate on a Windows PC: 78 | - **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen). 79 | - **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities). 80 | The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5 81 | are not included within this repository. 82 | 83 | The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation. 84 | 85 | ## License 86 | 87 | Arm CMSIS is licensed under Apache 2.0. 88 | 89 | ## Contributions and Pull Requests 90 | 91 | Contributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code. 92 | 93 | ### Issues and Labels 94 | 95 | Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues) 96 | to report misbehavior (i.e. bugs) or start discussions about enhancements. This 97 | is your best way to interact directly with the maintenance team and the community. 98 | We encourage you to append implementation suggestions as this helps to decrease the 99 | workload of the very limited maintenance team. 100 | 101 | We will be monitoring and responding to issues as best we can. 102 | Please attempt to avoid filing duplicates of open or closed items when possible. 103 | In the spirit of openness we will be tagging issues with the following: 104 | 105 | - **bug** – We consider this issue to be a bug that will be investigated. 106 | 107 | - **wontfix** - We appreciate this issue but decided not to change the current behavior. 108 | 109 | - **enhancement** – Denotes something that will be implemented soon. 110 | 111 | - **future** - Denotes something not yet schedule for implementation. 112 | 113 | - **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work. 114 | 115 | - **question** – We have further questions to this issue. Please review and provide feedback. 116 | 117 | - **documentation** - This issue is a documentation flaw that will be improved in future. 118 | 119 | - **review** - This issue is under review. Please be patient. 120 | 121 | - **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week. 122 | 123 | - **duplicate** - This issue is already addressed elsewhere, see comment with provided references. 124 | 125 | - **Important Information** - We provide essential information regarding planned or resolved major enhancements. 126 | 127 | --------------------------------------------------------------------------------