├── .gitignore ├── Images ├── img1.jpg ├── img2.jpg ├── img3.jpg ├── img4.jpg ├── img5.jpg └── img6.jpg ├── README.md └── code for APB ├── Design_APB.v └── TB_APB.v /.gitignore: -------------------------------------------------------------------------------- 1 | # Build and Release Folders 2 | bin-debug/ 3 | bin-release/ 4 | [Oo]bj/ 5 | [Bb]in/ 6 | 7 | # Other files and folders 8 | .settings/ 9 | 10 | # Executables 11 | *.swf 12 | *.air 13 | *.ipa 14 | *.apk 15 | 16 | # Project files, i.e. `.project`, `.actionScriptProperties` and `.flexProperties` 17 | # should NOT be excluded as they contain compiler settings and other important 18 | # information for Eclipse / Flash Builder. 19 | -------------------------------------------------------------------------------- /Images/img1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kumarraj5364/AMBA-APB-PROTOCOL/bd5f6eded1f7a6ebf4850e65c54bb2a195524b48/Images/img1.jpg -------------------------------------------------------------------------------- /Images/img2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kumarraj5364/AMBA-APB-PROTOCOL/bd5f6eded1f7a6ebf4850e65c54bb2a195524b48/Images/img2.jpg -------------------------------------------------------------------------------- /Images/img3.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kumarraj5364/AMBA-APB-PROTOCOL/bd5f6eded1f7a6ebf4850e65c54bb2a195524b48/Images/img3.jpg -------------------------------------------------------------------------------- /Images/img4.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kumarraj5364/AMBA-APB-PROTOCOL/bd5f6eded1f7a6ebf4850e65c54bb2a195524b48/Images/img4.jpg -------------------------------------------------------------------------------- /Images/img5.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kumarraj5364/AMBA-APB-PROTOCOL/bd5f6eded1f7a6ebf4850e65c54bb2a195524b48/Images/img5.jpg -------------------------------------------------------------------------------- /Images/img6.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kumarraj5364/AMBA-APB-PROTOCOL/bd5f6eded1f7a6ebf4850e65c54bb2a195524b48/Images/img6.jpg -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # AMBA-APB-PROTOCOL 2 | ### Raj Kumar Laldev 3 | Advance VLSI Lab 4 | Silicon institute of technology Bhubaneswar,India 5 | rajbihar5364@gmail.com 6 | # Table of Contents 7 | - [Introduction of AMBA](#Introduction-of-AMBA) 8 | - [AMBA Bus architecture](#AMBA-Bus-Architechture) 9 | * [Types of AMBA Bus](#Types-of-AMBA-Bus) 10 | * [AHB VS APB](#AHB-VS-APB) 11 | - [Advanced Peripheral Bus](#Advanced-Peripheral-Bus) 12 | * [APB Block Diagram](#APB-Block-Diagram) 13 | * [Signal specification of APB](#signal-specification-of-APB) 14 | - [Design and operating states of APB](#Design-and-operating-states-of-APB) 15 | * [Write operation](#Write-operation) 16 | * [Read operation](#Read-operation) 17 | - [Simulation results of APB design](#Simulation-results-of-APB-design) 18 | - [Conclusion](#Conclusion) 19 | - [Acknowledgement](#Acknowledgement) 20 | - [References](#References) 21 | 22 | # Introduction of AMBA 23 | - Advanced microcontroller bus architecture (AMBA) is an architecture that is widely used in system-on-chip designs, which are found on chip buses. 24 | - The AMBA specification standard is used for designing high-level embedded microcontrollers. 25 | - AMBA’s major objective is to provide technology independence and to encourage modular system design. Furthermore, it strongly encourages the development of reusable peripheral devices while minimizing silicon infrastructure. 26 | - Today, AMBA is widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones. 27 | 28 | AMBA was introduced by ARM in 1996. The first AMBA buses were the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). 29 | In its second version, AMBA 2 in 1999, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. 30 | In 2003, ARM introduced the third generation, AMBA 3, including Advanced eXtensible Interface (AXI) to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. 31 | In 2010, the AMBA 4 specifications were introduced starting with AMBA 4 AXI4, then 32 | in 2011, extending system-wide coherency with AMBA 4 AXI Coherency Extensions (ACE). 33 | In 2013, the AMBA 5 Coherent Hub Interface (CHI) specification was introduced, with a re-designed high-speed transport layer and features designed to reduce congestion. 34 | 35 | 36 | # AMBA Bus architecture 37 | - AMBA is an open specification that specifies a strategy on the management of the functional blocks that sort system on chip (SoC) architecture. 38 | - It is a high-speed, high-bandwidth bus that supports multimaster bus management to get the most out of system performance. 39 | - AMBA specifications are able to maximize the use of system bus bandwidth during dead time. After defining a common backbone for SoC modules, it enhances a reusable design methodology. 40 | - This system has emerged as the defacto standard for IP library progress and SoC interconnection. 41 | 42 | ![Alt](Images/img1.jpg) 43 | 44 | - This is development of embedded microcontroller products with one or more CPUs or signal processors. 45 | - This is highly reusable peripheral appropriate for full-custom, standard cell and gate array technologies. 46 | - It provides a road-map for advanced cached CPU cores and the development of peripheral libraries to minimize the silicon infrastructure required to support efficient on-chip. 47 | An AMBA is having backbone bus AMBA AHB or AMBA ASB. It sustains external memory bandwidth, on which the CPU, on-chip memory and other Direct Memory Access (DMA) devices abide. This bus provides a high-bandwidth interface between the elements that are involved in the majority of transfers. Also it is a bridge to the lower bandwidth APB. 48 | 49 | ## Types of AMBA Bus 50 | 51 | Five interfaces are defined within the AMBA specification: 52 | - Advanced system bus (ASB) 53 | - Advanced peripheral bus (APB) 54 | - Advanced high-performance bus (AHB) 55 | - Advanced extensible interface (AXI) 56 | - Advanced trace bus (ATB) 57 | 58 | ## AHB VS APB 59 | - AHB stands for Advanced High-performance Bus and APB sands for Advanced Peripheral Bus. Both the Advanced High-performance Bus and the Advanced Peripheral Bus are part of the Advanced Microprocessor Bus Architecture (AMBA). Though both the AHB and the APB belong to AMBA, they differ in many way. 60 | - Difference between the two, the AHB uses a full duplex parallel communication whereas the APB uses massive memory-I/O accesses. Both the AHB and the APB are on chip Bus standards. The Advanced High-performance Bus is capable of waits, errors and bursts. The ADH, which is pipelined, mainly connects to memories. 61 | - When comparing the usage, the APB is simpler than the AHB. Unlike the AHB, there is no pipelining in APB. The APB is mainly proposed for connecting to simple peripherals. Looking at the AHB and the APB, it can be seen that the APB comes with a low power peripheral. 62 | - It can also be seen that Advanced Peripheral Bus is sometimes optimized for reduced interface complexity and minimal power consumption for supporting peripheral functions. This Bus can also be used in union with either version of the system bus. 63 | - When looking at the features of AHB, it has a single edge clock protocol, several bus masters, split transactions, single-cycle bus master handover, burst transfers, large bus widths. 64 | - In AHB, the transaction consists of an address phase and a data phase. In case of AHB, there is only one Bus master at a time. When compared to Advanced High-performance Bus, the Advanced Peripheral Bus is only used for low bandwidth control accesses. Though the APB has an address phase and data phase as like that of the AHB, it comes with a list of low complexity signal. 65 | 66 | # Advanced Peripheral Bus 67 | - The Advanced Peripheral Bus (APB) is part of the Advanced Micro controller Bus Architecture (AMBA) . 68 | - APB is optimized for minimal power consumption and reduced interface complexity. 69 | - The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface. 70 | - The AMBA APB appears as a local secondary bus that is encapsulated as a single AHB or ASB slave device. 71 | - AMBA APB provides the basic peripheral macro cell communications infrastructure as a secondary bus from the higher bandwidth pipelined main system bus. It consist of interfaces which are memory-mapped registers. 72 | 73 | ## APB block diagram 74 | 75 | ![Alt](Images/img2.jpg) 76 | 77 | ## Signal specification of APB 78 | **PCLK Clock:** The rising edge of PCLK times all transfers on the APB. 79 | **PRESET:** System bus equivalent Reset. The APB reset signal is active LOW. 80 | **PADDR:** 32 bit address bus PSEL The slave device is selected and that a data transfer is required. 81 | **PENABLE Enable:** This signal indicates the second and subsequent cycles of an APB transfer. 82 | **PWRITE:** Access when HIGH. 83 | **PWDATA:** 32 bits Write data PWRITE is HIGH. 84 | **PREADY:** Ready To extend an APB transfer. 85 | **PRDATA:** 32 bits Read data and PWRITE is LOW. 86 | **PSLAVERR Slave error:** This signal indicates a transfer failure. 87 | 88 | # Design and operating states of APB 89 | 90 | ![Alt](Images/img3.jpg) 91 | 92 | 93 | **IDLE :** This is the default state of the APB. 94 | **SETUP:** When a transfer is required the bus moves into the SETUP state, where the appropriate select signal, **PSELx**, is asserted. The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock. 95 | **ACCESS:** The enable signal, **PENABLE**, is asserted in the ACCESS state. The address, write, select, and write data signals must remain stable during the transition from the SETUP to ACCESS state. 96 | Exit from the ACCESS state is controlled by the **PREADY** signal from the slave: 97 | - If PREADY is held LOW by the slave then the peripheral bus remains in the ACCESS state. 98 | - If PREADY is driven HIGH by the slave then the ACCESS state is exited and the bus returns to the IDLE state if no more transfers are required. Alternatively, the bus moves directly to the SETUP state if another transfer follows. 99 | 100 | # Write operation 101 | 102 | ![Alt](Images/img4.jpg) 103 | 104 | - At T1, a write transfer starts with PADDR, PWDATA, PWRITE, and PSEL, being registered at the rising edge of PCLK. It is called the SETUP cycle. 105 | - At the next rising edge of the clock T2 it is called ACCESS cycle, PENABLE, and PREADY, are registered. When asserted, PENABLE indicates starting of Access phase of the transfer. When asserted, PREADY indicates that the slave can complete the transfer at the next rising edge of PCLK. 106 | - The PADDR, PWDATA, and control signals all remain valid until the transfer completes at T3, the end of the Access phase. 107 | - The PENABLE, is disabled at the end of the transfer. The select signal PSEL is also disabled unless the transfer is to be followed immediately by another transfer to the same peripheral. 108 | 109 | 110 | # Read operation 111 | 112 | ![Alt](Images/img5.jpg) 113 | 114 | - During read operation the PENABLE, PSEL, PADDR PWRITE, signals are asserted at the clock edge T1 (**SETUP cycle**). 115 | - At the clock edge T2, (**ACCESS cycle**), the PENABLE, PREADY are asserted and PRDATA is also read during this phase. The slave must provide the data before the end of the read transfer. 116 | 117 | # Simulation results of APB design 118 | ![Alt](Images/img6.jpg) 119 | Verilog implementation of Operating states of APB. please [click here](https://www.edaplayground.com/x/2gvY) 120 | 121 | # Conclusion 122 | - This paper gives an outline of the AMBA bus architecture and explain the APB bus in detail. The APB bus is designed using the Verilog HDL according to the specification and is verified using **EDAplaground**. 123 | - The simulation results show that the data read from a particular memory location is same as the data written to the given memory location. 124 | - The results obtained after the simulation will be compared with the results. 125 | 126 | # Acknowledgement 127 | 128 | I would like to thank our Institution for equipping us with Advanced VLSI Lab facilities to successfully execute our project. I am also grateful to our mentor, [Dr. Saroj Rout](https://www.linkedin.com/in/sroutk?lipi=urn%3Ali%3Apage%3Ad_flagship3_profile_view_base_contact_details%3BGPdq1QbhS6mnLJPpjzlEIQ%3D%3D) and [Prof: Santunu sarangi](https://www.linkedin.com/in/santunu-sarangi-b731305b?lipi=urn%3Ali%3Apage%3Ad_flagship3_profile_view_base_contact_details%3Bg9BX%2F0YtQ0yyTenaLLJTog%3D%3D) for their constant advice and guidance throughout the project duration. 129 | 130 | # References 131 | 132 | [1] ARM, “AMBA Specification Overview”, available at [URL](http://www.arm.com/) 133 | [2] ARM, “AMBA Specification (Rev 2.0)”, available at [URL](http://www.arm.com) 134 | [3] URL: [click here](http://www.differencebetween.net/technology/difference-between-ahb-and-apb) 135 | [4] Samir Palnitkar, “Verilog HDL: A guide to Digital Design and Synthesis (2nd Edition), Pearson, 2008. 136 | [5] URL:[click here](http://www.testbench.com) 137 | -------------------------------------------------------------------------------- /code for APB/Design_APB.v: -------------------------------------------------------------------------------- 1 | // Code your design here 2 | module AMBA_APB(P_clk,P_rst,P_addr,P_selx,P_enable,P_write,P_wdata,P_ready,P_slverr,P_rdata); 3 | //input configration 4 | input P_clk; 5 | input P_rst; 6 | input [31:0]P_addr; 7 | 8 | input P_selx; 9 | input P_enable; 10 | input P_write; 11 | input [31:0]P_wdata; 12 | 13 | //output configration 14 | output reg P_ready; 15 | output reg P_slverr; 16 | output reg [31:0]P_rdata; 17 | //memory decleration 18 | reg [31:0]mem[31:0]; 19 | //state declaration communication 20 | parameter [1:0] idle=2'b00; 21 | parameter [1:0] setup=2'b01; 22 | parameter [1:0] access=2'b10; 23 | 24 | //state declaration of present and next 25 | reg [1:0] present_state,next_state; 26 | 27 | always @(posedge P_clk) begin 28 | if(P_rst) present_state <= idle; 29 | else 30 | present_state <= next_state; 31 | end 32 | always @(*) begin 33 | //next_state =present_state; 34 | case (present_state) 35 | idle:begin 36 | if (P_selx & !P_enable) 37 | next_state = setup; 38 | P_ready=0; 39 | end 40 | 41 | setup:begin if (!P_enable | !P_selx) 42 | next_state = idle; 43 | else begin 44 | next_state =access; 45 | 46 | if(P_write ==1) begin 47 | mem[P_addr]= P_wdata; 48 | P_ready=1; 49 | P_slverr=0; 50 | end 51 | else begin 52 | P_rdata=mem[P_addr]; 53 | P_ready=1; 54 | P_slverr=0; 55 | end 56 | end 57 | end 58 | access :begin 59 | if (!P_enable | !P_selx) begin 60 | next_state = idle; 61 | P_ready =0; 62 | end 63 | end 64 | endcase 65 | end 66 | endmodule -------------------------------------------------------------------------------- /code for APB/TB_APB.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | //input configration 3 | reg P_clk; 4 | reg P_rst; 5 | reg [31:0]P_addr; 6 | 7 | reg P_selx; 8 | reg P_enable; 9 | reg P_write; 10 | reg [31:0]P_wdata; 11 | 12 | //output configration 13 | wire P_ready; 14 | wire P_slverr; 15 | wire [31:0]P_rdata; 16 | 17 | //intantiation of all port 18 | AMBA_APB dut1(P_clk,P_rst,P_addr,P_selx,P_enable,P_write,P_wdata,P_ready,P_slverr,P_rdata); 19 | 20 | always #5 P_clk=~P_clk; 21 | 22 | task initialization; 23 | begin 24 | P_clk=0; 25 | P_rst=0; 26 | P_addr=0; 27 | P_selx=0; 28 | P_enable=0; 29 | P_write=0; 30 | end 31 | endtask 32 | // task reset. 33 | task reset; 34 | begin 35 | P_rst=1; 36 | #10 P_rst=0; 37 | end 38 | endtask 39 | 40 | 41 | task write_stimulus; 42 | begin 43 | @(posedge P_clk); 44 | P_selx=1; 45 | P_write=1; 46 | P_wdata={$random}%10; 47 | P_addr=P_addr+1; 48 | 49 | @(posedge P_clk); 50 | P_enable=1; 51 | P_selx=1; 52 | @(posedge P_clk); 53 | P_enable=0; 54 | P_selx=0; 55 | 56 | @(posedge P_clk); 57 | $strobe ("writing data into memory data_in=%0d adress_in=%0d" , P_wdata,P_addr); 58 | end 59 | endtask 60 | 61 | task read_stimulus; 62 | begin 63 | @(posedge P_clk); 64 | P_write=0; 65 | P_selx=1; 66 | P_enable=0; 67 | //P_addr=P_addr+1; 68 | @(posedge P_clk); 69 | P_enable=1; 70 | P_selx=1; 71 | P_addr<=P_addr+1; 72 | @(posedge P_clk); 73 | P_enable=0; 74 | P_selx=0; 75 | 76 | @(posedge P_clk); 77 | $strobe("reading data from memory data_out=%0d address_out=%0d",P_rdata,P_addr); 78 | end 79 | endtask 80 | 81 | task read_write; 82 | begin 83 | repeat(2) begin 84 | write_stimulus; 85 | end 86 | #1 87 | P_addr=0; 88 | repeat(3) begin 89 | read_stimulus; 90 | end 91 | end 92 | endtask 93 | 94 | initial begin 95 | $dumpfile("dump.vcd"); 96 | $dumpvars; 97 | initialization;//initialize input values 98 | reset;// generate signal 99 | read_write; 100 | #80; $finish; 101 | end 102 | endmodule --------------------------------------------------------------------------------