├── DC_WORKSHOP ├── README.md ├── lib │ ├── sky130_fd_sc_hd__tt_025C_1v80.db │ └── sky130_fd_sc_hd__tt_025C_1v80.lib └── verilog_files │ ├── a_trans │ ├── bad_case.v │ ├── bad_counter.v │ ├── bad_latch.v │ ├── bad_latch_2.v │ ├── bad_mux.v │ ├── bad_shift_reg.v │ ├── bad_shift_reg2.v │ ├── bal_check.ddc │ ├── bal_check.v │ ├── blocking_caveat.v │ ├── boundary.ddc │ ├── cg.net.v │ ├── check.v │ ├── check_boundary.ddc │ ├── check_boundary.v │ ├── check_clock_gating.v │ ├── check_code.v │ ├── check_logic_sharing.v │ ├── check_reg_retime.v │ ├── command.log │ ├── comp_case.v │ ├── counter_opt.v │ ├── counter_opt2.v │ ├── demux_case.v │ ├── demux_generate.v │ ├── dff_ares.net.v │ ├── dff_async_set.v │ ├── dff_asyncres.v │ ├── dff_asyncres_syncres.v │ ├── dff_const1.v │ ├── dff_const2.v │ ├── dff_const3.v │ ├── dff_const4.v │ ├── dff_const5.v │ ├── dff_syncres.v │ ├── en_128.v │ ├── fa.v │ ├── good_counter.v │ ├── good_latch.v │ ├── good_mux.v │ ├── good_shift_reg.v │ ├── incomp_case.v │ ├── incomp_if.v │ ├── incomp_if2.v │ ├── lab14.ddc │ ├── lab14_circuit.v │ ├── lab1_flop_with_en.v │ ├── lab5_desgin.v │ ├── lab8_circuit.ddc │ ├── lab8_circuit.v │ ├── lab8_circuit_modified.v │ ├── lab8_cons.tcl │ ├── lab8_cons_modified.tcl │ ├── mc │ ├── mcp_check.v │ ├── mcp_check_cons.tcl │ ├── mult.ddc │ ├── mult_2.v │ ├── mult_8.v │ ├── multiple_module_opt.v │ ├── multiple_module_opt2.v │ ├── multiple_modules.v │ ├── multiple_modules_flat.v │ ├── multiple_modules_hier.v │ ├── mux_generate.v │ ├── mux_spice.v │ ├── my_script.tcl │ ├── net.v │ ├── net1.v │ ├── op_path.rpt │ ├── opt_check.ddc │ ├── opt_check.v │ ├── opt_check2.v │ ├── opt_check3.v │ ├── opt_check4.v │ ├── out_load │ ├── partial_case_assign.v │ ├── pattern_detect_fsm.v │ ├── pattern_detect_fsm_bad_style.v │ ├── query_clock_pin.tcl │ ├── rca.v │ ├── reg_retime_cons.tcl │ ├── resource_sharing_mult_check.v │ ├── retimed.ddc │ ├── ripple_counter.v │ ├── tb_bad_case.v │ ├── tb_bad_counter.v │ ├── tb_bad_latch.v │ ├── tb_bad_latch2.v │ ├── tb_bad_mux.v │ ├── tb_bad_shift_reg.v │ ├── tb_bad_shift_reg2.v │ ├── tb_blocking_caveat.v │ ├── tb_comp_case.v │ ├── tb_counter_opt.v │ ├── tb_demux_case.v │ ├── tb_demux_generate.v │ ├── tb_dff_async_set.v │ ├── tb_dff_asyncres.v │ ├── tb_dff_asyncres_syncres.v │ ├── tb_dff_const1.v │ ├── tb_dff_const2.v │ ├── tb_dff_const3.v │ ├── tb_dff_const3.vcd │ ├── tb_dff_const4.v │ ├── tb_dff_const5.v │ ├── tb_dff_syncres.v │ ├── tb_good_counter.v │ ├── tb_good_latch.v │ ├── tb_good_mux.v │ ├── tb_good_shift_reg.v │ ├── tb_incomp_case.v │ ├── tb_incomp_if.v │ ├── tb_incomp_if2.v │ ├── tb_lab1_flop_with_en.v │ ├── tb_lab1_flop_with_en.vcd │ ├── tb_multiple_modules.v │ ├── tb_mux_generate.v │ ├── tb_opt_check.v │ ├── tb_opt_check2.v │ ├── tb_opt_check3.v │ ├── tb_partial_case_assign.v │ ├── tb_pattern_detect_fsm.v │ ├── tb_rca.v │ ├── tb_ripple_counter.v │ ├── tb_ternary_operator_mux.v │ ├── tb_up_dn_cntr.v │ ├── tb_up_dn_cntr_with_load.v │ ├── tb_up_dn_cntr_with_load_with_start_stop.v │ ├── tb_upcntr.v │ ├── ternary_operator_mux.v │ ├── up_dn_cntr.v │ ├── up_dn_cntr_with_load.v │ ├── up_dn_cntr_with_load_with_start_stop.v │ └── upcntr.v ├── README.md ├── lib └── sky130_fd_sc_hd__tt_025C_1v80.lib ├── my_lib └── verilog_model │ ├── primitives.v │ └── sky130_fd_sc_hd.v ├── verilog_files ├── bad_case.v ├── bad_case_net.v ├── bad_counter.v ├── bad_latch.v ├── bad_latch_2.v ├── bad_latch_net.v ├── bad_mux.v ├── bad_mux_net.v ├── bad_shift_reg.v ├── bad_shift_reg2.v ├── blocking_caveat.v ├── blocking_caveat_net.v ├── comp_case.v ├── counter_opt.v ├── counter_opt2.v ├── demux_case.v ├── demux_generate.v ├── dff_ares.net.v ├── dff_async_set.v ├── dff_asyncres.v ├── dff_asyncres_net.v ├── dff_asyncres_syncres.v ├── dff_const1.v ├── dff_const2.v ├── dff_const3.v ├── dff_const4.v ├── dff_const5.v ├── dff_net.v ├── dff_syncres.v ├── fa.v ├── good_counter.v ├── good_latch.v ├── good_mux.v ├── good_mux_netlist.v ├── good_shift_reg.v ├── incomp_case.v ├── incomp_if.v ├── incomp_if2.v ├── mul2_net.v ├── mult_2.v ├── mult_8.v ├── multiple_module_opt.v ├── multiple_module_opt2.v ├── multiple_modules.v ├── multiple_modules_flat.v ├── multiple_modules_hier.v ├── mux_generate.v ├── mux_spice.v ├── net.v ├── opt_check.v ├── opt_check2.v ├── opt_check3.v ├── opt_check4.v ├── partial_case_assign.v ├── pattern_detect_fsm.v ├── pattern_detect_fsm_bad_style.v ├── rca.v ├── ripple_counter.v ├── tb_bad_case.v ├── tb_bad_counter.v ├── tb_bad_latch.v ├── tb_bad_latch2.v ├── tb_bad_mux.v ├── tb_bad_shift_reg.v ├── tb_bad_shift_reg2.v ├── tb_blocking_caveat.v ├── tb_comp_case.v ├── tb_counter_opt.v ├── tb_demux_case.v ├── tb_demux_generate.v ├── tb_dff_async_set.v ├── tb_dff_asyncres.v ├── tb_dff_asyncres_syncres.v ├── tb_dff_const1.v ├── tb_dff_const2.v ├── tb_dff_const3.v ├── tb_dff_const4.v ├── tb_dff_const5.v ├── tb_dff_syncres.v ├── tb_good_counter.v ├── tb_good_latch.v ├── tb_good_mux.v ├── tb_good_shift_reg.v ├── tb_incomp_case.v ├── tb_incomp_if.v ├── tb_incomp_if2.v ├── tb_multiple_modules.v ├── tb_mux_generate.v ├── tb_opt_check.v ├── tb_opt_check2.v ├── tb_opt_check3.v ├── tb_partial_case_assign.v ├── tb_pattern_detect_fsm.v ├── tb_rca.v ├── tb_ripple_counter.v ├── tb_ternary_operator_mux.v ├── tb_up_dn_cntr.v ├── tb_up_dn_cntr_with_load.v ├── tb_up_dn_cntr_with_load_with_start_stop.v ├── tb_upcntr.v ├── ternary_operator_mux.v ├── ternary_operator_mux_net.v ├── up_dn_cntr.v ├── up_dn_cntr_with_load.v ├── up_dn_cntr_with_load_with_start_stop.v └── upcntr.v └── yosys_run.sh /DC_WORKSHOP/README.md: -------------------------------------------------------------------------------- 1 | DC Workshop 2 | -------------------------------------------------------------------------------- /DC_WORKSHOP/lib/sky130_fd_sc_hd__tt_025C_1v80.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/lib/sky130_fd_sc_hd__tt_025C_1v80.db -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/a_trans: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : timing 4 | -path full 5 | -delay max 6 | -max_paths 1 7 | -transition_time 8 | -capacitance 9 | Design : lab8_circuit 10 | Version: R-2020.09-SP5 11 | Date : Sat Aug 7 07:48:31 2021 12 | **************************************** 13 | 14 | Operating Conditions: tt_025C_1v80 Library: sky130_fd_sc_hd__tt_025C_1v80 15 | Wire Load Model Mode: top 16 | 17 | Startpoint: IN_A (input port clocked by MYCLK) 18 | Endpoint: REGA_reg (rising edge-triggered flip-flop clocked by MYCLK) 19 | Path Group: MYCLK 20 | Path Type: max 21 | 22 | Point Cap Trans Incr Path 23 | ------------------------------------------------------------------------------------ 24 | clock MYCLK (rise edge) 0.00 0.00 25 | clock network delay (ideal) 3.00 3.00 26 | input external delay 5.00 8.00 f 27 | IN_A (in) 0.00 0.30 0.00 8.00 f 28 | U11/Y (sky130_fd_sc_hd__nor2_1) 0.01 0.16 0.22 8.22 r 29 | U13/Y (sky130_fd_sc_hd__clkinv_1) 0.00 0.05 0.07 8.29 f 30 | REGA_reg/D (sky130_fd_sc_hd__dfrtp_1) 0.05 0.00 8.29 f 31 | data arrival time 8.29 32 | 33 | clock MYCLK (rise edge) 10.00 10.00 34 | clock network delay (ideal) 3.00 13.00 35 | clock uncertainty -0.50 12.50 36 | REGA_reg/CLK (sky130_fd_sc_hd__dfrtp_1) 0.00 12.50 r 37 | library setup time -0.13 12.37 38 | data required time 12.37 39 | ------------------------------------------------------------------------------------ 40 | data required time 12.37 41 | data arrival time -8.29 42 | ------------------------------------------------------------------------------------ 43 | slack (MET) 4.08 44 | 45 | 46 | 1 47 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_case.v: -------------------------------------------------------------------------------- 1 | module bad_case (input i0 , input i1, input i2, input i3 , input [1:0] sel, output reg y); 2 | always @(*) 3 | begin 4 | case(sel) 5 | 2'b00: y = i0; 6 | 2'b01: y = i1; 7 | 2'b10: y = i2; 8 | 2'b1?: y = i3; 9 | //2'b11: y = i3; 10 | endcase 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_counter.v: -------------------------------------------------------------------------------- 1 | module bad_counter (input clk , input reset , output reg [1:0] cnt); 2 | wire res_int; 3 | 4 | assign res_int = (cnt == 2'b11) | reset; 5 | 6 | always @(posedge clk , posedge res_int) 7 | begin 8 | if(res_int) 9 | cnt <= 2'b00; 10 | else 11 | cnt <= cnt+1; 12 | end 13 | 14 | 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_latch.v: -------------------------------------------------------------------------------- 1 | 2 | module bad_latch (input clk , input reset , input d , output reg q); 3 | always @ (clk,reset) 4 | begin 5 | if(reset) 6 | q <= 1'b0; 7 | else if(clk) 8 | q <= d; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_latch_2.v: -------------------------------------------------------------------------------- 1 | module bad_latch (input clk , input reset , input d , output reg q); 2 | always @ (clk,reset) 3 | begin 4 | if(reset) 5 | q <= 1'b0; 6 | else 7 | q <= d; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_mux.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module bad_mux (input i0 , input i1 , input sel , output reg y); 4 | always @ (sel) 5 | begin 6 | if(sel) 7 | y <= i1; 8 | else 9 | y <= i0; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_shift_reg.v: -------------------------------------------------------------------------------- 1 | 2 | module bad_shift_reg (input clk , input reset , input d , output reg dout); 3 | reg q1; 4 | always @ (posedge clk , posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q1 = 1'b0; 9 | dout = 1'b0; 10 | end 11 | else 12 | begin 13 | q1 = d; 14 | dout = q1; 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bad_shift_reg2.v: -------------------------------------------------------------------------------- 1 | 2 | module bad_shift_reg2 (input clk , input reset , input d , output reg dout); 3 | reg q1; 4 | always @ (posedge clk , posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q1 = 1'b0; 9 | dout = 1'b0; 10 | end 11 | else 12 | begin 13 | dout = q1; 14 | q1 = d; 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bal_check.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/bal_check.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/bal_check.v: -------------------------------------------------------------------------------- 1 | module bal_check (input a , input b , input c , input d , input e, output y , input clk , input res); 2 | 3 | reg rega, regb , regc ; 4 | 5 | always @ (posedge clk , posedge res) 6 | begin 7 | if(res) 8 | begin 9 | rega <= 1'b0; 10 | regb <= 1'b0; 11 | regc <= 1'b0; 12 | end 13 | else 14 | begin 15 | rega <= a; 16 | regb <= b; 17 | regc <= c; 18 | end 19 | end 20 | 21 | assign y = rega & regb & regc & d & e; 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/blocking_caveat.v: -------------------------------------------------------------------------------- 1 | module blocking_caveat (input a , input b , input c, output reg d); 2 | reg x; 3 | always @ (*) 4 | begin 5 | d = x & c; 6 | x = a | b; 7 | end 8 | endmodule 9 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/boundary.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/boundary.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/cg.net.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////// 2 | // Created by: Synopsys DC Ultra(TM) in wire load mode 3 | // Version : R-2020.09-SP5 4 | // Date : Mon Aug 2 14:57:38 2021 5 | ///////////////////////////////////////////////////////////// 6 | 7 | 8 | module check_clock_gating ( clk, res, d, val, en ); 9 | input [31:0] d; 10 | output [31:0] val; 11 | input clk, res, en; 12 | wire n42, n43, n44; 13 | 14 | sky130_fd_sc_hd__dfrtp_1 \val_reg[31] ( .D(d[31]), .CLK(n43), .RESET_B(n42), 15 | .Q(val[31]) ); 16 | sky130_fd_sc_hd__dfrtp_1 \val_reg[30] ( .D(d[30]), .CLK(n43), .RESET_B(n42), 17 | .Q(val[30]) ); 18 | sky130_fd_sc_hd__dfrtp_1 \val_reg[29] ( .D(d[29]), .CLK(n43), .RESET_B(n42), 19 | .Q(val[29]) ); 20 | sky130_fd_sc_hd__dfrtp_1 \val_reg[28] ( .D(d[28]), .CLK(n43), .RESET_B(n42), 21 | .Q(val[28]) ); 22 | sky130_fd_sc_hd__dfrtp_1 \val_reg[27] ( .D(d[27]), .CLK(n43), .RESET_B(n42), 23 | .Q(val[27]) ); 24 | sky130_fd_sc_hd__dfrtp_1 \val_reg[26] ( .D(d[26]), .CLK(n43), .RESET_B(n42), 25 | .Q(val[26]) ); 26 | sky130_fd_sc_hd__dfrtp_1 \val_reg[25] ( .D(d[25]), .CLK(n43), .RESET_B(n42), 27 | .Q(val[25]) ); 28 | sky130_fd_sc_hd__dfrtp_1 \val_reg[24] ( .D(d[24]), .CLK(n43), .RESET_B(n42), 29 | .Q(val[24]) ); 30 | sky130_fd_sc_hd__dfrtp_1 \val_reg[23] ( .D(d[23]), .CLK(n43), .RESET_B(n42), 31 | .Q(val[23]) ); 32 | sky130_fd_sc_hd__dfrtp_1 \val_reg[22] ( .D(d[22]), .CLK(n43), .RESET_B(n42), 33 | .Q(val[22]) ); 34 | sky130_fd_sc_hd__dfrtp_1 \val_reg[21] ( .D(d[21]), .CLK(n43), .RESET_B(n42), 35 | .Q(val[21]) ); 36 | sky130_fd_sc_hd__dfrtp_1 \val_reg[20] ( .D(d[20]), .CLK(n43), .RESET_B(n42), 37 | .Q(val[20]) ); 38 | sky130_fd_sc_hd__dfrtp_1 \val_reg[19] ( .D(d[19]), .CLK(n43), .RESET_B(n42), 39 | .Q(val[19]) ); 40 | sky130_fd_sc_hd__dfrtp_1 \val_reg[18] ( .D(d[18]), .CLK(n43), .RESET_B(n42), 41 | .Q(val[18]) ); 42 | sky130_fd_sc_hd__dfrtp_1 \val_reg[16] ( .D(d[16]), .CLK(n43), .RESET_B(n42), 43 | .Q(val[16]) ); 44 | sky130_fd_sc_hd__dfrtp_1 \val_reg[15] ( .D(d[15]), .CLK(n43), .RESET_B(n42), 45 | .Q(val[15]) ); 46 | sky130_fd_sc_hd__dfrtp_1 \val_reg[14] ( .D(d[14]), .CLK(n43), .RESET_B(n42), 47 | .Q(val[14]) ); 48 | sky130_fd_sc_hd__dfrtp_1 \val_reg[13] ( .D(d[13]), .CLK(n43), .RESET_B(n42), 49 | .Q(val[13]) ); 50 | sky130_fd_sc_hd__dfrtp_1 \val_reg[12] ( .D(d[12]), .CLK(n43), .RESET_B(n42), 51 | .Q(val[12]) ); 52 | sky130_fd_sc_hd__dfrtp_1 \val_reg[11] ( .D(d[11]), .CLK(n43), .RESET_B(n42), 53 | .Q(val[11]) ); 54 | sky130_fd_sc_hd__dfrtp_1 \val_reg[10] ( .D(d[10]), .CLK(n43), .RESET_B(n42), 55 | .Q(val[10]) ); 56 | sky130_fd_sc_hd__dfrtp_1 \val_reg[9] ( .D(d[9]), .CLK(n43), .RESET_B(n42), 57 | .Q(val[9]) ); 58 | sky130_fd_sc_hd__dfrtp_1 \val_reg[8] ( .D(d[8]), .CLK(n43), .RESET_B(n42), 59 | .Q(val[8]) ); 60 | sky130_fd_sc_hd__dfrtp_1 \val_reg[7] ( .D(d[7]), .CLK(n43), .RESET_B(n42), 61 | .Q(val[7]) ); 62 | sky130_fd_sc_hd__dfrtp_1 \val_reg[6] ( .D(d[6]), .CLK(n43), .RESET_B(n42), 63 | .Q(val[6]) ); 64 | sky130_fd_sc_hd__dfrtp_1 \val_reg[5] ( .D(d[5]), .CLK(n43), .RESET_B(n42), 65 | .Q(val[5]) ); 66 | sky130_fd_sc_hd__dfrtp_1 \val_reg[4] ( .D(d[4]), .CLK(n43), .RESET_B(n42), 67 | .Q(val[4]) ); 68 | sky130_fd_sc_hd__dfrtp_1 \val_reg[3] ( .D(d[3]), .CLK(n43), .RESET_B(n42), 69 | .Q(val[3]) ); 70 | sky130_fd_sc_hd__dfrtp_1 \val_reg[1] ( .D(d[1]), .CLK(n43), .RESET_B(n42), 71 | .Q(val[1]) ); 72 | sky130_fd_sc_hd__dfrtp_1 \val_reg[17] ( .D(d[17]), .CLK(n43), .RESET_B(n42), 73 | .Q(val[17]) ); 74 | sky130_fd_sc_hd__dfrtp_1 \val_reg[2] ( .D(d[2]), .CLK(n43), .RESET_B(n42), 75 | .Q(val[2]) ); 76 | sky130_fd_sc_hd__dfrtp_1 \val_reg[0] ( .D(d[0]), .CLK(n43), .RESET_B(n42), 77 | .Q(val[0]) ); 78 | SNPS_CLOCK_GATE_HIGH_check_clock_gating_0 clk_gate_val_reg ( .CLK(clk), .EN( 79 | en), .ENCLK(n43), .TE(n44) ); 80 | sky130_fd_sc_hd__clkinv_1 U138 ( .A(res), .Y(n42) ); 81 | sky130_fd_sc_hd__conb_1 U139 ( .LO(n44) ); 82 | endmodule 83 | 84 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////// 2 | // Created by: Synopsys DC Ultra(TM) in wire load mode 3 | // Version : R-2020.09-SP5 4 | // Date : Mon Aug 2 15:51:22 2021 5 | ///////////////////////////////////////////////////////////// 6 | 7 | 8 | module check_reg_retime ( clk, a, b, c, reset ); 9 | input [3:0] a; 10 | input [3:0] b; 11 | output [4:0] c; 12 | input clk, reset; 13 | wire n6, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, 14 | n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, 15 | n43, n44, n45, n46; 16 | wire [4:0] mult; 17 | wire [4:0] q1; 18 | wire [4:0] q2; 19 | 20 | sky130_fd_sc_hd__dfrtp_1 \q1_reg[4] ( .D(mult[4]), .CLK(clk), .RESET_B(n6), 21 | .Q(q1[4]) ); 22 | sky130_fd_sc_hd__dfrtp_1 \q1_reg[3] ( .D(mult[3]), .CLK(clk), .RESET_B(n6), 23 | .Q(q1[3]) ); 24 | sky130_fd_sc_hd__dfrtp_1 \q1_reg[2] ( .D(mult[2]), .CLK(clk), .RESET_B(n6), 25 | .Q(q1[2]) ); 26 | sky130_fd_sc_hd__dfrtp_1 \q1_reg[1] ( .D(mult[1]), .CLK(clk), .RESET_B(n6), 27 | .Q(q1[1]) ); 28 | sky130_fd_sc_hd__dfrtp_1 \q1_reg[0] ( .D(mult[0]), .CLK(clk), .RESET_B(n6), 29 | .Q(q1[0]) ); 30 | sky130_fd_sc_hd__dfrtp_1 \q2_reg[4] ( .D(q1[4]), .CLK(clk), .RESET_B(n6), 31 | .Q(q2[4]) ); 32 | sky130_fd_sc_hd__dfrtp_1 \q3_reg[4] ( .D(q2[4]), .CLK(clk), .RESET_B(n6), 33 | .Q(c[4]) ); 34 | sky130_fd_sc_hd__dfrtp_1 \q2_reg[3] ( .D(q1[3]), .CLK(clk), .RESET_B(n6), 35 | .Q(q2[3]) ); 36 | sky130_fd_sc_hd__dfrtp_1 \q3_reg[3] ( .D(q2[3]), .CLK(clk), .RESET_B(n6), 37 | .Q(c[3]) ); 38 | sky130_fd_sc_hd__dfrtp_1 \q2_reg[2] ( .D(q1[2]), .CLK(clk), .RESET_B(n6), 39 | .Q(q2[2]) ); 40 | sky130_fd_sc_hd__dfrtp_1 \q3_reg[2] ( .D(q2[2]), .CLK(clk), .RESET_B(n6), 41 | .Q(c[2]) ); 42 | sky130_fd_sc_hd__dfrtp_1 \q2_reg[1] ( .D(q1[1]), .CLK(clk), .RESET_B(n6), 43 | .Q(q2[1]) ); 44 | sky130_fd_sc_hd__dfrtp_1 \q3_reg[1] ( .D(q2[1]), .CLK(clk), .RESET_B(n6), 45 | .Q(c[1]) ); 46 | sky130_fd_sc_hd__dfrtp_1 \q2_reg[0] ( .D(q1[0]), .CLK(clk), .RESET_B(n6), 47 | .Q(q2[0]) ); 48 | sky130_fd_sc_hd__dfrtp_1 \q3_reg[0] ( .D(q2[0]), .CLK(clk), .RESET_B(n6), 49 | .Q(c[0]) ); 50 | sky130_fd_sc_hd__clkinv_1 U18 ( .A(b[2]), .Y(n25) ); 51 | sky130_fd_sc_hd__clkinv_1 U19 ( .A(a[1]), .Y(n26) ); 52 | sky130_fd_sc_hd__clkinv_1 U20 ( .A(a[0]), .Y(n19) ); 53 | sky130_fd_sc_hd__fa_2 U21 ( .A(n34), .B(n33), .CIN(n32), .COUT(n38), .SUM( 54 | mult[3]) ); 55 | sky130_fd_sc_hd__clkinv_1 U22 ( .A(b[1]), .Y(n21) ); 56 | sky130_fd_sc_hd__clkinv_1 U23 ( .A(a[2]), .Y(n20) ); 57 | sky130_fd_sc_hd__and2_0 U24 ( .A(b[3]), .B(a[0]), .X(n31) ); 58 | sky130_fd_sc_hd__clkinv_1 U25 ( .A(b[0]), .Y(n16) ); 59 | sky130_fd_sc_hd__and2_0 U26 ( .A(a[3]), .B(b[0]), .X(n35) ); 60 | sky130_fd_sc_hd__and2_0 U27 ( .A(b[2]), .B(a[2]), .X(n43) ); 61 | sky130_fd_sc_hd__clkinv_1 U28 ( .A(reset), .Y(n6) ); 62 | sky130_fd_sc_hd__nor2_1 U29 ( .A(n26), .B(n16), .Y(n18) ); 63 | sky130_fd_sc_hd__nor2_1 U30 ( .A(n21), .B(n19), .Y(n17) ); 64 | sky130_fd_sc_hd__nor2_1 U31 ( .A(n16), .B(n19), .Y(mult[0]) ); 65 | sky130_fd_sc_hd__nor2_1 U32 ( .A(n20), .B(n16), .Y(n24) ); 66 | sky130_fd_sc_hd__ha_1 U33 ( .A(n18), .B(n17), .COUT(n23), .SUM(mult[1]) ); 67 | sky130_fd_sc_hd__nor2_1 U34 ( .A(n25), .B(n19), .Y(n28) ); 68 | sky130_fd_sc_hd__nor2_1 U35 ( .A(n26), .B(n21), .Y(n27) ); 69 | sky130_fd_sc_hd__nor2_1 U36 ( .A(n21), .B(n20), .Y(n36) ); 70 | sky130_fd_sc_hd__fa_1 U37 ( .A(n24), .B(n23), .CIN(n22), .COUT(n33), .SUM( 71 | mult[2]) ); 72 | sky130_fd_sc_hd__nor2_1 U38 ( .A(n26), .B(n25), .Y(n30) ); 73 | sky130_fd_sc_hd__ha_1 U39 ( .A(n28), .B(n27), .COUT(n29), .SUM(n22) ); 74 | sky130_fd_sc_hd__nand2_1 U40 ( .A(b[3]), .B(a[1]), .Y(n46) ); 75 | sky130_fd_sc_hd__fa_1 U41 ( .A(n31), .B(n30), .CIN(n29), .COUT(n42), .SUM( 76 | n32) ); 77 | sky130_fd_sc_hd__nand2_1 U42 ( .A(b[1]), .B(a[3]), .Y(n40) ); 78 | sky130_fd_sc_hd__ha_1 U43 ( .A(n36), .B(n35), .COUT(n37), .SUM(n34) ); 79 | sky130_fd_sc_hd__xor2_1 U44 ( .A(n38), .B(n37), .X(n39) ); 80 | sky130_fd_sc_hd__xnor2_1 U45 ( .A(n40), .B(n39), .Y(n41) ); 81 | sky130_fd_sc_hd__xnor2_1 U46 ( .A(n42), .B(n41), .Y(n44) ); 82 | sky130_fd_sc_hd__xnor2_1 U47 ( .A(n44), .B(n43), .Y(n45) ); 83 | sky130_fd_sc_hd__o2bb2ai_1 U48 ( .B1(n46), .B2(n45), .A1_N(n46), .A2_N(n45), 84 | .Y(mult[4]) ); 85 | endmodule 86 | 87 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check_boundary.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/check_boundary.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check_boundary.v: -------------------------------------------------------------------------------- 1 | module check_boundary (input clk , input res , input [3:0] val_in , output reg [3:0] val_out); 2 | wire en; 3 | internal_module u_im (.clk(clk) , .res(res) , .cnt_roll(en)); 4 | 5 | always @ (posedge clk , posedge res) 6 | begin 7 | if(res) 8 | val_out <= 4'b0; 9 | else if(en) 10 | val_out <= val_in; 11 | end 12 | endmodule 13 | 14 | 15 | module internal_module (input clk , input res , output cnt_roll); 16 | reg [2:0] cnt; 17 | 18 | always @(posedge clk , posedge res) 19 | begin 20 | if(res) 21 | cnt <= 3'b0; 22 | else 23 | cnt <= cnt + 1; 24 | end 25 | 26 | assign cnt_roll = (cnt == 3'b111); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check_clock_gating.v: -------------------------------------------------------------------------------- 1 | module check_clock_gating (input clk , input res , input [31:0] d , output reg [31:0] val , input en); 2 | 3 | always @ (posedge clk , posedge res) 4 | begin 5 | if(res) 6 | val <= 31'b0; 7 | else if (en) 8 | val <= d; 9 | 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check_code.v: -------------------------------------------------------------------------------- 1 | module check_code (input clk , input res , input d, output reg q); 2 | 3 | always @ (posedge clk ,posedge res) 4 | begin 5 | if(res) 6 | q <= d; 7 | else 8 | q <= 1'b0; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check_logic_sharing.v: -------------------------------------------------------------------------------- 1 | module check_logic_sharing (input a , input b , input c , output x , output y); 2 | 3 | assign x = a & b & c; 4 | assign y = (a & b) | c; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/check_reg_retime.v: -------------------------------------------------------------------------------- 1 | module check_reg_retime (input clk , input [3:0] a, input [3:0] b , output [7:0] c , input reset); 2 | 3 | wire [7:0] mult; 4 | assign mult = a * b; 5 | reg [7:0] q1; 6 | reg [7:0] q2; 7 | reg [7:0] q3; 8 | 9 | 10 | 11 | 12 | always @ (posedge clk , posedge reset) 13 | begin 14 | if(reset) 15 | begin 16 | q1 <= 8'b0; 17 | q2 <= 8'b0; 18 | q3 <= 8'b0; 19 | end 20 | else 21 | begin 22 | q1 <= mult; 23 | q2 <= q1; 24 | q3 <= q2; 25 | end 26 | end 27 | assign c = q3; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/comp_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module comp_case (input i0 , input i1 , input i2 , input [1:0] sel, output reg y); 4 | always @ (*) 5 | begin 6 | case(sel) 7 | 2'b00 : y = i0; 8 | 2'b01 : y = i1; 9 | default : y = i2; 10 | endcase 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/counter_opt.v: -------------------------------------------------------------------------------- 1 | module counter_opt (input clk , input en, input reset , output q); 2 | reg [3:0] count; 3 | assign q = count[0]; 4 | 5 | always @(posedge clk ,posedge reset) 6 | begin 7 | if(reset) 8 | count <= 4'b0000; 9 | else if(en) 10 | count <= count + 1; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/counter_opt2.v: -------------------------------------------------------------------------------- 1 | module counter_opt (input clk , input reset , output q); 2 | reg [2:0] count; 3 | assign q = (count[2:0] == 3'b100); 4 | 5 | always @(posedge clk ,posedge reset) 6 | begin 7 | if(reset) 8 | count <= 3'b000; 9 | else 10 | count <= count + 1; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/demux_case.v: -------------------------------------------------------------------------------- 1 | module demux_case (output o0 , output o1, output o2 , output o3, output o4, output o5, output o6 , output o7 , input [2:0] sel , input i); 2 | reg [7:0]y_int; 3 | assign {o7,o6,o5,o4,o3,o2,o1,o0} = y_int; 4 | integer k; 5 | always @ (*) 6 | begin 7 | y_int = 8'b0; 8 | case(sel) 9 | 3'b000 : y_int[0] = i; 10 | 3'b001 : y_int[1] = i; 11 | 3'b010 : y_int[2] = i; 12 | 3'b011 : y_int[3] = i; 13 | 3'b100 : y_int[4] = i; 14 | 3'b101 : y_int[5] = i; 15 | 3'b110 : y_int[6] = i; 16 | 3'b111 : y_int[7] = i; 17 | endcase 18 | 19 | end 20 | endmodule 21 | 22 | 23 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/demux_generate.v: -------------------------------------------------------------------------------- 1 | 2 | module demux_generate (output o0 , output o1, output o2 , output o3, output o4, output o5, output o6 , output o7 , input [2:0] sel , input i); 3 | reg [7:0]y_int; 4 | assign {o7,o6,o5,o4,o3,o2,o1,o0} = y_int; 5 | integer k; 6 | always @ (*) 7 | begin 8 | y_int = 8'b0; 9 | for(k = 0; k < 8; k++) begin 10 | if(k == sel) 11 | y_int[k] = i; 12 | end 13 | end 14 | endmodule 15 | 16 | 17 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_ares.net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | (* top = 1 *) 4 | (* src = "dff_asyncres.v:2" *) 5 | module dff_asyncres(clk, async_reset, d, q); 6 | wire _0_; 7 | wire _1_; 8 | wire _2_; 9 | (* src = "dff_asyncres.v:2" *) 10 | input async_reset; 11 | (* src = "dff_asyncres.v:2" *) 12 | input clk; 13 | (* src = "dff_asyncres.v:2" *) 14 | input d; 15 | (* src = "dff_asyncres.v:2" *) 16 | output q; 17 | sky130_fd_sc_hd__clkinv_1 _3_ ( 18 | .A(_0_), 19 | .Y(_1_) 20 | ); 21 | sky130_fd_sc_hd__dfrtp_1 _4_ ( 22 | .CLK(clk), 23 | .D(d), 24 | .Q(q), 25 | .RESET_B(_2_) 26 | ); 27 | assign _0_ = async_reset; 28 | assign _2_ = _1_; 29 | endmodule 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_async_set.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module dff_async_set ( input clk , input async_set , input d , output reg q ); 4 | always @ (posedge clk , posedge async_set) 5 | begin 6 | if(async_set) 7 | q <= 1'b1; 8 | else 9 | q <= d; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_asyncres.v: -------------------------------------------------------------------------------- 1 | 2 | module dff_asyncres ( input clk , input async_reset , input d , output reg q ); 3 | always @ (posedge clk , posedge async_reset) 4 | begin 5 | if(async_reset) 6 | q <= 1'b0; 7 | else 8 | q <= d; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_asyncres_syncres.v: -------------------------------------------------------------------------------- 1 | module dff_asyncres_syncres ( input clk , input async_reset , input sync_reset , input d , output reg q ); 2 | always @ (posedge clk , posedge async_reset) 3 | begin 4 | if(async_reset) 5 | q <= 1'b0; 6 | else if (sync_reset) 7 | q <= 1'b0; 8 | else 9 | q <= d; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_const1.v: -------------------------------------------------------------------------------- 1 | module dff_const1(input clk, input reset, output reg q); 2 | always @(posedge clk, posedge reset) 3 | begin 4 | if(reset) 5 | q <= 1'b0; 6 | else 7 | q <= 1'b1; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_const2.v: -------------------------------------------------------------------------------- 1 | module dff_const2(input clk, input reset, output reg q); 2 | always @(posedge clk, posedge reset) 3 | begin 4 | if(reset) 5 | q <= 1'b1; 6 | else 7 | q <= 1'b1; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_const3.v: -------------------------------------------------------------------------------- 1 | module dff_const3(input clk, input reset, output reg q); 2 | reg q1; 3 | 4 | always @(posedge clk, posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q <= 1'b1; 9 | q1 <= 1'b0; 10 | end 11 | else 12 | begin 13 | q1 <= 1'b1; 14 | q <= q1; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_const4.v: -------------------------------------------------------------------------------- 1 | module dff_const4(input clk, input reset, output reg q); 2 | reg q1; 3 | 4 | always @(posedge clk, posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q <= 1'b1; 9 | q1 <= 1'b1; 10 | end 11 | else 12 | begin 13 | q1 <= 1'b1; 14 | q <= q1; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_const5.v: -------------------------------------------------------------------------------- 1 | 2 | module dff_const5(input clk, input reset, output reg q); 3 | reg q1; 4 | 5 | always @(posedge clk, posedge reset) 6 | begin 7 | if(reset) 8 | begin 9 | q <= 1'b0; 10 | q1 <= 1'b0; 11 | end 12 | else 13 | begin 14 | q1 <= 1'b1; 15 | q <= q1; 16 | end 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/dff_syncres.v: -------------------------------------------------------------------------------- 1 | 2 | module dff_syncres ( input clk , input async_reset , input sync_reset , input d , output reg q ); 3 | always @ (posedge clk ) 4 | begin 5 | if (sync_reset) 6 | q <= 1'b0; 7 | else 8 | q <= d; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/en_128.v: -------------------------------------------------------------------------------- 1 | module en_128 (input [127:0] x , output [127:0] y , input en); 2 | assign y[127:0] = en ?x[127:0]:128'b0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/fa.v: -------------------------------------------------------------------------------- 1 | module fa (input a , input b , input c, output co , output sum); 2 | assign {co,sum} = a + b + c ; 3 | endmodule 4 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/good_counter.v: -------------------------------------------------------------------------------- 1 | module good_counter (input clk , input reset , output reg [1:0] cnt); 2 | wire comp; 3 | 4 | assign comp = (cnt == 2'b10); 5 | 6 | always @(posedge clk , posedge reset) 7 | begin 8 | if(reset) 9 | cnt <= 2'b00; 10 | else if(comp) 11 | cnt <= 2'b00; 12 | else 13 | cnt <= cnt+1; 14 | end 15 | 16 | 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/good_latch.v: -------------------------------------------------------------------------------- 1 | module good_latch (input clk , input reset , input d , output reg q); 2 | always @ (clk,reset,d) 3 | begin 4 | if(reset) 5 | q <= 1'b0; 6 | else if(clk) 7 | q <= d; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/good_mux.v: -------------------------------------------------------------------------------- 1 | 2 | module good_mux (input i0 , input i1 , input sel , output reg y); 3 | always @ (*) 4 | begin 5 | if(sel) 6 | y <= i1; 7 | else 8 | y <= i0; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/good_shift_reg.v: -------------------------------------------------------------------------------- 1 | module good_shift_reg (input clk , input reset , input d , output reg dout); 2 | reg q1; 3 | always @ (posedge clk , posedge reset) 4 | begin 5 | if(reset) 6 | begin 7 | q1 <= 1'b0; 8 | dout <= 1'b0; 9 | end 10 | else 11 | begin 12 | dout <= q1; 13 | q1 <= d; 14 | end 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/incomp_case.v: -------------------------------------------------------------------------------- 1 | 2 | module incomp_case (input i0 , input i1 , input i2 , input [1:0] sel, output reg y); 3 | always @ (*) 4 | begin 5 | case(sel) 6 | 2'b00 : y = i0; 7 | 2'b01 : y = i1; 8 | endcase 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/incomp_if.v: -------------------------------------------------------------------------------- 1 | module incomp_if (input i0 , input i1 , input i2 , output reg y); 2 | always @ (*) 3 | begin 4 | if(i0) 5 | y <= i1; 6 | end 7 | endmodule 8 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/incomp_if2.v: -------------------------------------------------------------------------------- 1 | 2 | module incomp_if2 (input i0 , input i1 , input i2 , input i3, output reg y); 3 | always @ (*) 4 | begin 5 | if(i0) 6 | y <= i1; 7 | else if (i2) 8 | y <= i3; 9 | 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab14.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/lab14.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab14_circuit.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module lab8_circuit (input rst, input clk , input IN_A , input IN_B , output OUT_Y , output out_clk , output reg out_div_clk , input IN_C , input IN_D , output OUT_Z ); 4 | reg REGA , REGB , REGC ; 5 | 6 | always @ (posedge clk , posedge rst) 7 | begin 8 | if(rst) 9 | begin 10 | REGA <= 1'b0; 11 | REGB <= 1'b0; 12 | REGC <= 1'b0; 13 | out_div_clk <= 1'b0; 14 | end 15 | else 16 | begin 17 | REGA <= IN_A | IN_B; 18 | REGB <= IN_A ^ IN_B; 19 | REGC <= !(REGA & REGB); 20 | out_div_clk <= ~out_div_clk; 21 | end 22 | end 23 | 24 | assign OUT_Y = ~REGC; 25 | 26 | assign out_clk = clk; 27 | assign OUT_Z = IN_C ^ IN_D ; 28 | 29 | 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab1_flop_with_en.v: -------------------------------------------------------------------------------- 1 | module lab1_flop_with_en ( input res , input clk , input d , input en , output reg q); 2 | always @ (posedge clk , posedge res) 3 | begin 4 | if(res) 5 | q <= 1'b0; 6 | else if(en) 7 | q <= d; 8 | end 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab5_desgin.v: -------------------------------------------------------------------------------- 1 | module lab5_design (input a , input b , input clk , input res, output y); 2 | 3 | //internal signals 4 | reg reg1; 5 | reg reg2; 6 | reg reg3; 7 | 8 | always @ (posedge clk , posedge res) 9 | begin 10 | if(res) 11 | begin 12 | reg1 <= 1'b0; 13 | reg2 <= 1'b0; 14 | reg3 <= 1'b0; 15 | end 16 | else 17 | begin 18 | reg1 <= ( a | b ) & reg1; 19 | reg2 <= a & b & reg1; 20 | reg3 <= reg1 ^ reg2; 21 | end 22 | end 23 | 24 | assign y = ~reg3; 25 | 26 | endmodule 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab8_circuit.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/lab8_circuit.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab8_circuit.v: -------------------------------------------------------------------------------- 1 | module lab8_circuit (input rst, input clk , input IN_A , input IN_B , output OUT_Y , output out_clk); 2 | reg REGA , REGB , REGC ; 3 | 4 | always @ (posedge clk , posedge rst) 5 | begin 6 | if(rst) 7 | begin 8 | REGA <= 1'b0; 9 | REGB <= 1'b0; 10 | REGC <= 1'b0; 11 | end 12 | else 13 | begin 14 | REGA <= IN_A | IN_B; 15 | REGB <= IN_A ^ IN_B; 16 | REGC <= !(REGA & REGB); 17 | end 18 | end 19 | 20 | assign OUT_Y = ~REGC; 21 | 22 | assign out_clk = clk; 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab8_circuit_modified.v: -------------------------------------------------------------------------------- 1 | 2 | module lab8_circuit (input rst, input clk , input IN_A , input IN_B , output OUT_Y , output out_clk , output reg out_div_clk); 3 | reg REGA , REGB , REGC ; 4 | 5 | always @ (posedge clk , posedge rst) 6 | begin 7 | if(rst) 8 | begin 9 | REGA <= 1'b0; 10 | REGB <= 1'b0; 11 | REGC <= 1'b0; 12 | out_div_clk <= 1'b0; 13 | end 14 | else 15 | begin 16 | REGA <= IN_A | IN_B; 17 | REGB <= IN_A ^ IN_B; 18 | REGC <= !(REGA & REGB); 19 | out_div_clk <= ~out_div_clk; 20 | end 21 | end 22 | 23 | assign OUT_Y = ~REGC; 24 | 25 | assign out_clk = clk; 26 | 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab8_cons.tcl: -------------------------------------------------------------------------------- 1 | create_clock -name MYCLK -per 10 [get_ports clk]; 2 | set_clock_latency -source 2 [get_clocks MYCLK]; 3 | set_clock_latency 1 [get_clocks MYCLK]; 4 | set_clock_uncertainty -setup 0.5 [get_clocks MYCLK]; 5 | set_clock_uncertainty -hold 0.1 [get_clocks MYCLK]; 6 | set_input_delay -max 5 -clock [get_clocks MYCLK] [get_ports IN_A]; 7 | set_input_delay -max 5 -clock [get_clocks MYCLK] [get_ports IN_B]; 8 | set_input_delay -min 1 -clock [get_clocks MYCLK] [get_ports IN_A]; 9 | set_input_delay -min 1 -clock [get_clocks MYCLK] [get_ports IN_B]; 10 | set_input_transition -max 0.4 [get_ports IN_A]; 11 | set_input_transition -max 0.4 [get_ports IN_B]; 12 | set_input_transition -min 0.1 [get_ports IN_A]; 13 | set_input_transition -min 0.1 [get_ports IN_B]; 14 | create_generated_clock -name MYGEN_CLK -master MYCLK -source [get_ports clk] -div 1 [get_ports out_clk]; 15 | create_generated_clock -name MYGEN_DIV_CLK -master MYCLK -source [get_ports clk] -div 2 [get_ports out_div_clk]; 16 | set_output_delay -max 5 -clock [get_clocks MYGEN_CLK] [get_ports OUT_Y]; 17 | set_output_delay -min 1 -clock [get_clocks MYGEN_CLK] [get_ports OUT_Y]; 18 | set_load -max 0.4 [get_ports OUT_Y]; 19 | set_load -min 0.1 [get_ports OUT_Y]; 20 | 21 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/lab8_cons_modified.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_clock -name MYCLK -per 10 [get_ports clk]; 3 | 4 | set_clock_latency -source 2 [get_clocks MYCLK]; 5 | set_clock_latency 1 [get_clocks MYCLK]; 6 | set_clock_uncertainty -setup 0.5 [get_clocks MYCLK]; 7 | set_clock_uncertainty -hold 0.1 [get_clocks MYCLK]; 8 | 9 | set_input_delay -max 4 -clock [get_clocks MYCLK] [get_ports IN_A]; 10 | set_input_delay -max 4 -clock [get_clocks MYCLK] [get_ports IN_B]; 11 | set_input_delay -min 1 -clock [get_clocks MYCLK] [get_ports IN_A]; 12 | set_input_delay -min 1 -clock [get_clocks MYCLK] [get_ports IN_B]; 13 | 14 | set_input_transition -max 0.4 [get_ports IN_A]; 15 | set_input_transition -max 0.4 [get_ports IN_B]; 16 | set_input_transition -min 0.1 [get_ports IN_A]; 17 | set_input_transition -min 0.1 [get_ports IN_B]; 18 | 19 | create_generated_clock -name MYGEN_CLK -master MYCLK -source [get_ports clk] -div 1 [get_ports out_clk]; 20 | create_generated_clock -name MYGEN_DIV_CLK -master MYCLK -source [get_ports clk] -div 2 [get_ports out_div_clk]; 21 | 22 | set_output_delay -max 4 -clock [get_clocks MYGEN_CLK] [get_ports OUT_Y]; 23 | set_output_delay -min 1 -clock [get_clocks MYGEN_CLK] [get_ports OUT_Y]; 24 | 25 | set_load -max 0.4 [get_ports OUT_Y]; 26 | set_load -min 0.1 [get_ports OUT_Y]; 27 | 28 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mc: -------------------------------------------------------------------------------- 1 | 2. Synopsys Commands Command Reference 2 | compile_ultra 3 | 4 | NAME 5 | compile_ultra 6 | Performs a high-effort compile on the current design for better 7 | quality of results (QoR). 8 | 9 | SYNTAX 10 | status compile_ultra 11 | [-incremental] 12 | [-scan] 13 | [-exact_map] 14 | [-no_autoungroup] 15 | [-no_seq_output_inversion] 16 | [-no_boundary_optimization] 17 | [-no_design_rule | -only_design_rule] 18 | [-timing_high_effort_script 19 | | -area_high_effort_script] 20 | [-top] 21 | [-retime] 22 | [-gate_clock] 23 | [-self_gating] 24 | [-check_only] 25 | [-congestion] 26 | [-spg] 27 | [-no_auto_layer_optimization] 28 | 29 | ARGUMENTS 30 | -incremental 31 | Runs compile_ultra in incremental mode. In the incremental 32 | mode, the tool does not run the mapping or implementation selec- 33 | tion stages. 34 | 35 | -scan Enables the examination of the impact of scan insertion on mis- 36 | sion-mode constraints during optimization, as in a normal com- 37 | pile. Use this option to replace all sequential elements during 38 | optimization. Some scan-replaced sequential cells can be con- 39 | verted to nonscan cells later in the test synthesis process 40 | because of test design rule violations or explicit specifica- 41 | tions. 42 | 43 | -exact_map 44 | Specifies that sequential cells are mapped exactly as indicated 45 | in the HDL code. Use of the -exact_map option does not mean the 46 | QN pin won't be used in the mapped sequential element. Use of 47 | the -exact_map option would disable sequential output inversion. 48 | For more information, see compile_seqmap_enable_output_inver- 49 | sion. 50 | 51 | -no_autoungroup 52 | Specifies that automatic ungrouping is completely disabled. All 53 | hierarchies are preserved unless otherwise specified. 54 | 55 | -no_seq_output_inversion 56 | Disables sequential output inversion. The phase sequential of 57 | all sequential elements is the same as in the RTL. Without this 58 | option, compile_ultra is free to invert sequential elements dur- 59 | ing mapping and optimization. For more information, see the man 60 | page for the compile_seqmap_enable_output_inversion variable. 61 | 62 | -no_boundary_optimization 63 | Specifies that no hierarchical boundary optimization is to be 64 | performed. By default, boundary optimization is turned on dur- 65 | ing compile_ultra activity. 66 | 67 | Specifies that no hierarchical boundary optimization is to be 68 | performed. By default, the -no_boundary_optimization option 69 | does not disable constant propagation across design hierarchies. 70 | To disable constant propagation with the -no_boundary_optimiza- 71 | tion option, set the compile_enable_constant_propaga- 72 | tion_with_no_boundary_opt variable to false. 73 | 74 | This option sets the compile_preserve_subdesign_interfaces vari- 75 | able to true. 76 | 77 | -no_design_rule 78 | Determines whether the command fixes design rule violations 79 | before exiting. The -no_design_rule option specifies for the 80 | command to exit before fixing design rule violations, thus 81 | allowing you to check the results in a constraint report before 82 | fixing the violations. The default is to perform both design 83 | rule fixing and mapping optimizations before exiting. 84 | 85 | The -no_design_rule and -only_design_rule options are mutually 86 | exclusive. Use only one option. 87 | 88 | -only_design_rule 89 | Determines whether the command fixes design rule violations 90 | before exiting. The -only_design_rule option specifies for the 91 | command to perform only design rule fixing; that is, mapping 92 | optimizations are not performed. The default is to perform both 93 | design rule fixing and mapping optimizations before exiting. 94 | 95 | The -no_design_rule and -only_design_rule options are mutually 96 | exclusive. Use only one option. The -only_design_rule option 97 | can be used only with the -incremental option. 98 | 99 | -timing_high_effort_script 100 | This option is available in the tool to support backward compat- 101 | ibility with existing scripts and is ignored for optimization 102 | purposes. 103 | 104 | -area_high_effort_script 105 | This option is available in the tool to support backward compat- 106 | ibility with existing scripts and is ignored for optimization 107 | purposes. 108 | 109 | -top Fixes design rule and top-level timing violations in a design. 110 | By default, this option fixes all design rule violations, but 111 | only those timing violations whose paths cross top-level hierar- 112 | chical boundaries. If you want this option to fix timing viola- 113 | tions for all paths, set the compile_top_all_paths variable to 114 | true. 115 | 116 | -retime 117 | Uses the adaptive retiming algorithm during optimization to 118 | improve delay. This option is ignored if the -only_design_rule 119 | option or the -top option is chosen at the same time. 120 | 121 | -gate_clock 122 | Enables clock gating optimization: clock gates are automatically 123 | inserted or removed. The -gate_clock option cannot be used in 124 | combination with the -only_design_rule option. When used with 125 | the -exact_map option, it might not be possible to honor the 126 | -exact_map option for those registers that are involved with 127 | clock gating optimization. 128 | 129 | A clock gating cell is not modified or removed if it or its par- 130 | ent hierarchical cell is marked dont_touch with the 131 | set_dont_touch command. 132 | 133 | -self_gating 134 | Enables the execution of XOR self-gating insertion. 135 | 136 | Self-gating is an XOR based clock gating technique that opti- 137 | mizes dynamic power by gating the clock signal in those cycles 138 | in which the data saved in a register remains unchanged. An 139 | enable condition is computed by comparing the stored data with 140 | the new data arriving at the data pin, and that signal is used 141 | to drive the inserted self-gating cell. 142 | 143 | A self-gating cell can be shared across several registers by 144 | creating a combined enable condition so that the area and power 145 | overhead due to the inserted cells is minimized. 146 | 147 | The selection of registers to be gated and the grouping of them 148 | to form the self-gating banks are driven by the switching activ- 149 | ity at the registers' data pins, the timing slack available, and 150 | the physical proximity between the registers to be grouped. 151 | 152 | This option is only supported in Design Compiler topographical 153 | mode. 154 | 155 | The -self_gating option cannot be used in combination with the 156 | -only_design_rule option. 157 | 158 | -check_only 159 | Checks whether the design and libraries have all the data that 160 | compile_ultra requires to run successfully. This option is 161 | available only in Design Compiler topographical mode. 162 | 163 | -congestion 164 | This option will be obsolete in a future release. See the -spg 165 | option for information about congestion optimization. 166 | 167 | -spg This option is available only in Design Compiler topographical 168 | mode. Enables physical guidance, congestion optimization, and 169 | automatic layer optimization. Congestion optimization reduces 170 | routing-related congestion. Physical guidance enables Design 171 | Compiler Graphical to save coarse placement information and pass 172 | this coarse placement information to IC Compiler. With this 173 | coarse placement, IC Compiler can begin the implementation flow 174 | with the place_opt command. 175 | 176 | IC Compiler no longer needs to re-create the coarse placement by 177 | running commands such as create_placement, remove_buffer_tree, 178 | or psynopt. By using the Design Compiler coarse placement as a 179 | starting point for placement, runtime and area correlation with 180 | IC Compiler are improved. 181 | 182 | Design Compiler Graphical automatically performs layer-aware 183 | optimization when you use the -spg option, modeling parasitic 184 | variation across metal layers in a way that benefits optimiza- 185 | tion. This optimization helps remove excess pessimism, leading 186 | to better area and power. 187 | 188 | In addition to the default layer-aware optimization, you can 189 | also specify net constraints for layer optimization by setting 190 | specific constraints using the set_net_routing_layer_constraints 191 | command or by creating a net-search pattern. 192 | 193 | In the net-search pattern approach, you define a net-search pat- 194 | tern by using the create_net_search_pattern command and then 195 | define associated minimum and maximum routing layer constraints 196 | for the search pattern by using the set_net_search_pat- 197 | tern_delay_estimation_options command. Design Compiler invokes 198 | net-pattern identification after the high-fanout synthesis step 199 | in compile_ultra and assigns the minimum and maximum constraints 200 | to the matching nets. The subsequent optimizations consider the 201 | effects of the constraints (for example, the unit resistance and 202 | capacitance values of matching nets will change) during buffer- 203 | ing and buffer removal. You can define as many net-search pat- 204 | terns and associated layer constraints as needed. In general, 205 | however, it is recommended to start with very long nets (for 206 | example, 500 um) with top routing layers (for example, M7 and 207 | M8). You should consider this approach when your design shows 208 | significant unit resistance variation (see RCEX-011 resistance 209 | values) across all available routing layers. 210 | 211 | Note that the user-constraints and net-pattern layer optimiza- 212 | tion methods might affect runtime. 213 | 214 | -no_auto_layer_optimization 215 | The -no_auto_layer_optimization option is obsolete. Running the 216 | option has no effect on layer optimization. 217 | 218 | DESCRIPTION 219 | The compile_ultra command performs a high-effort compile on the current 220 | design for better quality of results (QoR). As with the compile com- 221 | mand, optimization is controlled by constraints that you specify on the 222 | design. This command is targeted toward high-performance designs with 223 | very tight timing constraints. It provides you with a simple approach 224 | to achieve critical delay optimization. The compile_ultra command 225 | packages all the DC Ultra features and enables them by default. It 226 | requires a DC Ultra license plus a DesignWare Foundation license. This 227 | command provides the best strategy for optimum overall QoR and perfor- 228 | mance. 229 | 230 | When used in conjunction with the set_host_options command, com- 231 | pile_ultra uses up to the user-specified number of CPU cores on the 232 | same computer for parallel execution. See the description of the 233 | -max_cores option in the set_host_options man page for more informa- 234 | tion. 235 | 236 | This command can be used in the same manner as the compile command. 237 | 238 | By default, compile_ultra incorporates two ungrouping phases for design 239 | hierarchies. The first phase is performed before "Pass1 Mapping" and 240 | attempts to ungroup small design hierarchies. This first ungrouping 241 | phase can be turned off using the following command: 242 | 243 | set compile_ultra_ungroup_small_hierarchies false 244 | 245 | The second ungrouping phase is performed during "Mapping Optimization" 246 | and applies a delay-based ungrouping strategy for design hierarchies. 247 | If you need to preserve all design hierarchies, use the -no_autoungroup 248 | option. If you want to preserve the hierarchies for a specific block, 249 | use the set_ungroup command. 250 | 251 | By default, if dw_foundation.sldb is not in the synthetic_library list, 252 | and the DesignWare license is successfully checked out, dw_founda- 253 | tion.sldb is automatically added to the synthetic_library to use the 254 | QoR benefit provided by the licensed DesignWare architectures. This 255 | behavior occurs in the current command only, and it does not affect the 256 | user-specified synthetic_library and link_library list. 257 | 258 | By default, all DesignWare hierarchies are unconditionally ungrouped in 259 | the second pass of compile. You can set the compile_ultra_ungroup_dw 260 | variable to control the ungrouping process of DesignWare components. 261 | 262 | By default, hierarchical boundary optimization is performed on the 263 | design. This can change the function of the design so that it can 264 | operate only in its current environment. If input or output ports are 265 | complemented as a result of this optimization, port names are changed 266 | according to the port_complement_naming_style variable. Use the 267 | -no_boundary_optimization option to turn off the boundary optimization 268 | feature. 269 | 270 | By default, the tool applies a compile strategy intended to improve the 271 | resulting area of the design, possibly at the cost of additional run- 272 | time. The strategy can make changes to variables or constraints that 273 | modify compile_ultra behavior and perform additional passes to achieve 274 | better area. 275 | 276 | EXAMPLES 277 | The following example turns off boundary optimization for cell U1: 278 | 279 | prompt> set_boundary_optimization [get_cells U1] false 280 | prompt> compile_ultra 281 | 282 | SEE ALSO 283 | compile(2) 284 | set_host_options(2) 285 | create_net_search_pattern(2) 286 | set_net_search_pattern_delay_estimation_options(2) 287 | 288 | Version R-2020.09-SP5 289 | Copyright (c) 2021 Synopsys, Inc. All rights reserved. 290 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mcp_check.v: -------------------------------------------------------------------------------- 1 | module mcp_check (input clk , input res , input [7:0] a , input [7:0] b, input en , output reg [15:0] prod); 2 | 3 | reg valid; 4 | 5 | always @ (posedge clk , posedge res) 6 | begin 7 | if(res) 8 | valid <= 1'b0; 9 | else 10 | valid <= en; 11 | end 12 | 13 | 14 | 15 | always @ (posedge clk , posedge res) 16 | begin 17 | if(res) 18 | prod <= 16'b0; 19 | else if (valid) 20 | prod <= a * b; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mcp_check_cons.tcl: -------------------------------------------------------------------------------- 1 | #create the clock 2 | create_clock -per 4 -name myclk [get_ports clk]; 3 | 4 | #model the practicality of the clock 5 | set_clock_uncertainty -setup 0.5 [get_clocks myclk]; 6 | set_clock_uncertainty -hold 0.2 [get_clocks myclk]; 7 | 8 | #Annotate the IO Delays 9 | set_input_delay -max 3.0 -clock myclk [all_inputs]; 10 | set_input_delay -min 0.5 -clock myclk [all_inputs]; 11 | 12 | set_output_delay -max 2.5 -clock myclk [all_outputs]; 13 | set_output_delay -min 0.5 -clock myclk [all_outputs]; 14 | 15 | #Model the practicalities of the IOs 16 | set_input_transition -max 0.3 [all_inputs]; 17 | set_input_transition -min 0.05 [all_inputs]; 18 | 19 | set_load -max 0.4 [all_outputs]; 20 | set_load -min 0.05 [all_outputs]; 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mult.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/mult.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mult_2.v: -------------------------------------------------------------------------------- 1 | module mul2 (input [2:0] a, output [3:0] y); 2 | assign y = a * 2; 3 | endmodule 4 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mult_8.v: -------------------------------------------------------------------------------- 1 | module mult8 (input [2:0] a , output [5:0] y); 2 | assign y = a * 9; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/multiple_module_opt.v: -------------------------------------------------------------------------------- 1 | module sub_module1(input a , input b , output y); 2 | assign y = a & b; 3 | endmodule 4 | 5 | 6 | module sub_module2(input a , input b , output y); 7 | assign y = a^b; 8 | endmodule 9 | 10 | 11 | module multiple_module_opt(input a , input b , input c , input d , output y); 12 | wire n1,n2,n3; 13 | 14 | sub_module1 U1 (.a(a) , .b(1'b1) , .y(n1)); 15 | sub_module2 U2 (.a(n1), .b(1'b0) , .y(n2)); 16 | sub_module2 U3 (.a(b), .b(d) , .y(n3)); 17 | 18 | assign y = c | (b & n1); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/multiple_module_opt2.v: -------------------------------------------------------------------------------- 1 | 2 | module sub_module(input a , input b , output y); 3 | assign y = a & b; 4 | endmodule 5 | 6 | 7 | 8 | module multiple_module_opt2(input a , input b , input c , input d , output y); 9 | wire n1,n2,n3; 10 | 11 | sub_module U1 (.a(a) , .b(1'b0) , .y(n1)); 12 | sub_module U2 (.a(b), .b(c) , .y(n2)); 13 | sub_module U3 (.a(n2), .b(d) , .y(n3)); 14 | sub_module U4 (.a(n3), .b(n1) , .y(y)); 15 | 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/multiple_modules.v: -------------------------------------------------------------------------------- 1 | module sub_module2 (input a, input b, output y); 2 | assign y = a | b; 3 | endmodule 4 | 5 | module sub_module1 (input a, input b, output y); 6 | assign y = a&b; 7 | endmodule 8 | 9 | 10 | module multiple_modules (input a, input b, input c , output y); 11 | wire net1; 12 | sub_module1 u1(.a(a),.b(b),.y(net1)); //net1 = a&b 13 | sub_module2 u2(.a(net1),.b(c),.y(y)); //y = net1|c ,ie y = a&b + c; 14 | endmodule 15 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/multiple_modules_flat.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module multiple_modules(a, b, c, y); 4 | wire _00_; 5 | wire _01_; 6 | wire _02_; 7 | wire _03_; 8 | wire _04_; 9 | wire _05_; 10 | wire _06_; 11 | wire _07_; 12 | input a; 13 | input b; 14 | input c; 15 | wire net1; 16 | wire \u1.a ; 17 | wire \u1.b ; 18 | wire \u1.y ; 19 | wire \u2.a ; 20 | wire \u2.b ; 21 | wire \u2.y ; 22 | output y; 23 | sky130_fd_sc_hd__and2_2 _08_ ( 24 | .A(_00_), 25 | .B(_01_), 26 | .X(_02_) 27 | ); 28 | sky130_fd_sc_hd__clkinv_1 _09_ ( 29 | .A(_03_), 30 | .Y(_06_) 31 | ); 32 | sky130_fd_sc_hd__clkinv_1 _10_ ( 33 | .A(_04_), 34 | .Y(_07_) 35 | ); 36 | sky130_fd_sc_hd__nand2_1 _11_ ( 37 | .A(_06_), 38 | .B(_07_), 39 | .Y(_05_) 40 | ); 41 | assign \u1.a = a; 42 | assign \u1.b = b; 43 | assign net1 = \u1.y ; 44 | assign _00_ = \u1.b ; 45 | assign _01_ = \u1.a ; 46 | assign \u1.y = _02_; 47 | assign \u2.a = net1; 48 | assign \u2.b = c; 49 | assign y = \u2.y ; 50 | assign _03_ = \u2.b ; 51 | assign _04_ = \u2.a ; 52 | assign \u2.y = _05_; 53 | endmodule 54 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/multiple_modules_hier.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module multiple_modules(a, b, c, y); 4 | input a; 5 | input b; 6 | input c; 7 | wire net1; 8 | output y; 9 | sub_module1 u1 ( 10 | .a(a), 11 | .b(b), 12 | .y(net1) 13 | ); 14 | sub_module2 u2 ( 15 | .a(net1), 16 | .b(c), 17 | .y(y) 18 | ); 19 | endmodule 20 | 21 | module sub_module1(a, b, y); 22 | wire _0_; 23 | wire _1_; 24 | wire _2_; 25 | input a; 26 | input b; 27 | output y; 28 | sky130_fd_sc_hd__and2_2 _3_ ( 29 | .A(_0_), 30 | .B(_1_), 31 | .X(_2_) 32 | ); 33 | assign _0_ = b; 34 | assign _1_ = a; 35 | assign y = _2_; 36 | endmodule 37 | 38 | module sub_module2(a, b, y); 39 | wire _0_; 40 | wire _1_; 41 | wire _2_; 42 | wire _3_; 43 | wire _4_; 44 | input a; 45 | input b; 46 | output y; 47 | sky130_fd_sc_hd__clkinv_1 _5_ ( 48 | .A(_0_), 49 | .Y(_3_) 50 | ); 51 | sky130_fd_sc_hd__clkinv_1 _6_ ( 52 | .A(_1_), 53 | .Y(_4_) 54 | ); 55 | sky130_fd_sc_hd__nand2_1 _7_ ( 56 | .A(_3_), 57 | .B(_4_), 58 | .Y(_2_) 59 | ); 60 | assign _0_ = b; 61 | assign _1_ = a; 62 | assign y = _2_; 63 | endmodule 64 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mux_generate.v: -------------------------------------------------------------------------------- 1 | module mux_generate (input i0 , input i1, input i2 , input i3 , input [1:0] sel , output reg y); 2 | wire [3:0] i_int; 3 | assign i_int = {i3,i2,i1,i0}; 4 | integer k; 5 | always @ (*) 6 | begin 7 | for(k = 0; k < 4; k=k+1) begin 8 | if(k == sel) 9 | y = i_int[k]; 10 | end 11 | end 12 | endmodule 13 | 14 | 15 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/mux_spice.v: -------------------------------------------------------------------------------- 1 | * SPICE netlist generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) 2 | 3 | X0 i0 1 sky130_fd_sc_hd__clkinv_1 4 | X1 i1 sel 2 sky130_fd_sc_hd__nand2_1 5 | X2 3 sel 1 2 sky130_fd_sc_hd__o21ai_0 6 | V0 4 i0 DC 0 7 | V1 5 i1 DC 0 8 | V2 6 sel DC 0 9 | V3 y 3 DC 0 10 | 11 | ************************ 12 | * end of SPICE netlist * 13 | ************************ 14 | 15 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/my_script.tcl: -------------------------------------------------------------------------------- 1 | set my_list [list sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand3b_1 \ 2 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand3b_2 \ 3 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand3b_4 \ 4 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand4_1 \ 5 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand4_2 \ 6 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand4_4 \ 7 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand4b_1 \ 8 | sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand4b_2 ] 9 | 10 | 11 | #For each cell in the list , find the output pin name and its functionality 12 | 13 | 14 | foreach my_cell $my_list { 15 | foreach_in_collection my_lib_pin [get_lib_pins ${my_cell}/*] { 16 | set my_lib_pin_name [get_object_name $my_lib_pin]; 17 | set a [get_lib_attribute $my_lib_pin_name direction]; 18 | if { $a == 2 } { 19 | set fn [get_lib_attribute $my_lib_pin_name function]; 20 | echo $my_lib_pin_name $a $fn; 21 | } 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | (* top = 1 *) 4 | (* src = "multiple_modules.v:10" *) 5 | module multiple_modules(a, b, c, y); 6 | (* src = "multiple_modules.v:10" *) 7 | input a; 8 | (* src = "multiple_modules.v:10" *) 9 | input b; 10 | (* src = "multiple_modules.v:10" *) 11 | input c; 12 | (* src = "multiple_modules.v:11" *) 13 | wire net1; 14 | (* src = "multiple_modules.v:10" *) 15 | output y; 16 | (* src = "multiple_modules.v:12" *) 17 | sub_module1 u1 ( 18 | .a(a), 19 | .b(b), 20 | .y(net1) 21 | ); 22 | (* src = "multiple_modules.v:13" *) 23 | sub_module2 u2 ( 24 | .a(net1), 25 | .b(c), 26 | .y(y) 27 | ); 28 | endmodule 29 | 30 | (* src = "multiple_modules.v:5" *) 31 | module sub_module1(a, b, y); 32 | wire _0_; 33 | wire _1_; 34 | wire _2_; 35 | (* src = "multiple_modules.v:5" *) 36 | input a; 37 | (* src = "multiple_modules.v:5" *) 38 | input b; 39 | (* src = "multiple_modules.v:5" *) 40 | output y; 41 | sky130_fd_sc_hd__and2_2 _3_ ( 42 | .A(_0_), 43 | .B(_1_), 44 | .X(_2_) 45 | ); 46 | assign _0_ = b; 47 | assign _1_ = a; 48 | assign y = _2_; 49 | endmodule 50 | 51 | (* src = "multiple_modules.v:1" *) 52 | module sub_module2(a, b, y); 53 | wire _0_; 54 | wire _1_; 55 | wire _2_; 56 | wire _3_; 57 | wire _4_; 58 | (* src = "multiple_modules.v:1" *) 59 | input a; 60 | (* src = "multiple_modules.v:1" *) 61 | input b; 62 | (* src = "multiple_modules.v:1" *) 63 | output y; 64 | sky130_fd_sc_hd__clkinv_1 _5_ ( 65 | .A(_0_), 66 | .Y(_3_) 67 | ); 68 | sky130_fd_sc_hd__clkinv_1 _6_ ( 69 | .A(_1_), 70 | .Y(_4_) 71 | ); 72 | sky130_fd_sc_hd__nand2_1 _7_ ( 73 | .A(_3_), 74 | .B(_4_), 75 | .Y(_2_) 76 | ); 77 | assign _0_ = b; 78 | assign _1_ = a; 79 | assign y = _2_; 80 | endmodule 81 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/net1.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////// 2 | // Created by: Synopsys DC Expert(TM) in wire load mode 3 | // Version : R-2020.09-SP5 4 | // Date : Sun Aug 1 14:39:54 2021 5 | ///////////////////////////////////////////////////////////// 6 | 7 | 8 | module lab5_design ( a, b, clk, res, y ); 9 | input a, b, clk, res; 10 | output y; 11 | wire N0, N1, reg3, reg2, reg1, N2, n1, n5, n6; 12 | 13 | sky130_fd_sc_hd__dfrtp_1 reg1_reg ( .D(N0), .CLK(clk), .RESET_B(n1), .Q(reg1) ); 14 | sky130_fd_sc_hd__dfrtp_1 reg2_reg ( .D(N1), .CLK(clk), .RESET_B(n1), .Q(reg2) ); 15 | sky130_fd_sc_hd__dfrtp_1 reg3_reg ( .D(N2), .CLK(clk), .RESET_B(n1), .Q(reg3) ); 16 | sky130_fd_sc_hd__clkinv_1 U10 ( .A(reg3), .Y(y) ); 17 | sky130_fd_sc_hd__clkinv_1 U11 ( .A(res), .Y(n1) ); 18 | sky130_fd_sc_hd__xor2_1 U12 ( .A(reg2), .B(reg1), .X(N2) ); 19 | sky130_fd_sc_hd__nor2_1 U13 ( .A(n5), .B(n6), .Y(N1) ); 20 | sky130_fd_sc_hd__nand2_1 U14 ( .A(n6), .B(n5), .Y(N0) ); 21 | sky130_fd_sc_hd__clkinv_1 U15 ( .A(a), .Y(n5) ); 22 | sky130_fd_sc_hd__clkinv_1 U16 ( .A(b), .Y(n6) ); 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/op_path.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : timing 4 | -path full 5 | -delay max 6 | -input_pins 7 | -max_paths 1 8 | -transition_time 9 | -capacitance 10 | Design : mcp_check 11 | Version: R-2020.09-SP5 12 | Date : Sun Aug 8 14:07:39 2021 13 | **************************************** 14 | 15 | Operating Conditions: tt_025C_1v80 Library: sky130_fd_sc_hd__tt_025C_1v80 16 | Wire Load Model Mode: top 17 | 18 | Startpoint: prod_reg[13] 19 | (rising edge-triggered flip-flop clocked by myclk) 20 | Endpoint: prod[13] (output port clocked by myclk) 21 | Path Group: myclk 22 | Path Type: max 23 | 24 | Point Cap Trans Incr Path 25 | ------------------------------------------------------------------------------------ 26 | clock myclk (rise edge) 0.0000 0.0000 27 | clock network delay (ideal) 0.0000 0.0000 28 | prod_reg[13]/CLK (sky130_fd_sc_hd__dfrbp_1) 0.0000 0.0000 0.0000 r 29 | prod_reg[13]/Q (sky130_fd_sc_hd__dfrbp_1) 0.0049 0.0719 0.3439 0.3439 r 30 | U443/A (sky130_fd_sc_hd__buf_6) 0.0719 0.0000 0.3439 r 31 | U443/X (sky130_fd_sc_hd__buf_6) 0.4000 0.7706 0.6217 0.9656 r 32 | prod[13] (out) 0.7706 0.0000 0.9656 r 33 | data arrival time 0.9656 34 | 35 | clock myclk (rise edge) 4.0000 4.0000 36 | clock network delay (ideal) 0.0000 4.0000 37 | clock uncertainty -0.5000 3.5000 38 | output external delay -2.5000 1.0000 39 | data required time 1.0000 40 | ------------------------------------------------------------------------------------ 41 | data required time 1.0000 42 | data arrival time -0.9656 43 | ------------------------------------------------------------------------------------ 44 | slack (MET) 0.0344 45 | 46 | 47 | 1 48 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/opt_check.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/opt_check.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/opt_check.v: -------------------------------------------------------------------------------- 1 | module opt_check (input a , input b , input c , output y1, output y2); 2 | wire a1; 3 | assign y1 = a?b:0; 4 | assign y2 = ~((a1 & b) | c); 5 | assign a1 = 1'b0; 6 | endmodule 7 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/opt_check2.v: -------------------------------------------------------------------------------- 1 | module opt_check2 (input a , input b , output y); 2 | assign y = a?1:b; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/opt_check3.v: -------------------------------------------------------------------------------- 1 | 2 | module opt_check3 (input a , input b, input c , output y); 3 | assign y = a?(c?b:0):0; 4 | endmodule 5 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/opt_check4.v: -------------------------------------------------------------------------------- 1 | module opt_check4 (input a , input b , input c , output y); 2 | assign y = a?(b?(a & c ):c):(!c); 3 | endmodule 4 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/out_load: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : timing 4 | -path full 5 | -delay max 6 | -max_paths 1 7 | -transition_time 8 | -capacitance 9 | Design : lab8_circuit 10 | Version: R-2020.09-SP5 11 | Date : Sat Aug 7 07:53:44 2021 12 | **************************************** 13 | 14 | Operating Conditions: tt_025C_1v80 Library: sky130_fd_sc_hd__tt_025C_1v80 15 | Wire Load Model Mode: top 16 | 17 | Startpoint: REGC_reg (rising edge-triggered flip-flop clocked by MYCLK) 18 | Endpoint: OUT_Y (output port clocked by MYCLK) 19 | Path Group: MYCLK 20 | Path Type: max 21 | 22 | Point Cap Trans Incr Path 23 | ------------------------------------------------------------------------------------ 24 | clock MYCLK (rise edge) 0.00 0.00 25 | clock network delay (ideal) 3.00 3.00 26 | REGC_reg/CLK (sky130_fd_sc_hd__dfrtp_1) 0.00 0.00 3.00 r 27 | REGC_reg/Q (sky130_fd_sc_hd__dfrtp_1) 0.00 0.05 0.30 3.30 r 28 | U10/Y (sky130_fd_sc_hd__clkinv_1) 0.40 3.07 2.32 5.62 f 29 | OUT_Y (out) 3.07 0.00 5.62 f 30 | data arrival time 5.62 31 | 32 | clock MYCLK (rise edge) 10.00 10.00 33 | clock network delay (ideal) 3.00 13.00 34 | clock uncertainty -0.50 12.50 35 | output external delay -5.00 7.50 36 | data required time 7.50 37 | ------------------------------------------------------------------------------------ 38 | data required time 7.50 39 | data arrival time -5.62 40 | ------------------------------------------------------------------------------------ 41 | slack (MET) 1.88 42 | 43 | 44 | 1 45 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/partial_case_assign.v: -------------------------------------------------------------------------------- 1 | module partial_case_assign (input i0 , input i1 , input i2 , input [1:0] sel, output reg y , output reg x); 2 | always @ (*) 3 | begin 4 | case(sel) 5 | 2'b00 : begin 6 | y = i0; 7 | x = i2; 8 | end 9 | 2'b01 : y = i1; 10 | default : begin 11 | x = i1; 12 | y = i2; 13 | end 14 | endcase 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/pattern_detect_fsm.v: -------------------------------------------------------------------------------- 1 | module pattern_detect_fsm (input clk , input reset, input din , output reg pattern_detect); 2 | reg [1:0] present_state , next_state; 3 | always @ (posedge clk, posedge reset) 4 | begin 5 | if(reset) 6 | begin 7 | preset_state <= 2'b00; 8 | else 9 | present_state <= next_state; 10 | end 11 | 12 | 13 | always & (*) 14 | begin 15 | next_state = present_state; 16 | pattern_detect = 1'b0; 17 | case(present_state): 18 | 19 | 2'b00 : begin 20 | if(din) 21 | next_state = 2'b01; 22 | end 23 | 24 | 2'b01 : begin 25 | if(!din) 26 | next_state = 2'b10; 27 | end 28 | 29 | 2'b10 : begin 30 | if(din) 31 | next_state = 2'b11; 32 | else 33 | next_state = 2'b00; 34 | end 35 | 36 | 2'b11 : begin 37 | next_state = 2'b00; 38 | pattern_detect = 1'b1; 39 | 40 | end 41 | 42 | default : begin 43 | next_state = present_state; 44 | pattern_detect = 1'b0; 45 | end 46 | endcase 47 | 48 | 49 | end 50 | 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/pattern_detect_fsm_bad_style.v: -------------------------------------------------------------------------------- 1 | module pattern_detect_fsm_bad_style (input clk , input reset, input din , output reg pattern_detect); 2 | reg [1:0] present_state , next_state; 3 | always @ (posedge clk, posedge reset) 4 | begin 5 | if(reset) 6 | begin 7 | preset_state <= 2'b00; 8 | else 9 | present_state <= next_state; 10 | end 11 | 12 | 13 | always & (*) 14 | begin 15 | case(present_state): 16 | 17 | 2'b00 : begin 18 | if(din) 19 | begin 20 | next_state = 2'b01; 21 | pattern_detect = 1'b0; 22 | end 23 | else 24 | begin 25 | next_state = 2'b00; 26 | pattern_detect = 1'b0; 27 | end 28 | end 29 | 30 | 2'b01 : begin 31 | if(!din) 32 | begin 33 | next_state = 2'b10; 34 | pattern_detect = 1'b0; 35 | end 36 | else 37 | begin 38 | next_state = 2'b01; 39 | pattern_detect = 1'b0; 40 | end 41 | 42 | 43 | end 44 | 45 | 2'b10 : begin 46 | if(din) 47 | begin 48 | next_state = 2'b11; 49 | pattern_detect = 1'b0; 50 | end 51 | else 52 | begin 53 | next_state = 2'b00; 54 | pattern_detect = 1'b0; 55 | end 56 | end 57 | 58 | 2'b11 : begin 59 | next_state = 2'b00; 60 | pattern_detect = 1'b1; 61 | 62 | end 63 | 64 | default : begin 65 | next_state = present_state; 66 | pattern_detect = 1'b0; 67 | end 68 | endcase 69 | 70 | 71 | end 72 | 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/query_clock_pin.tcl: -------------------------------------------------------------------------------- 1 | foreach_in_collection my_pin [get_pins *] { 2 | set my_pin_name [get_object_name $my_pin]; 3 | set dir [get_attribute [get_pins $my_pin_name] direction]; 4 | if { [regexp $dir in] } { 5 | if { [get_attribute [get_pins $my_pin_name] clock ] } { 6 | set clk [get_attribute [get_pins $my_pin_name] clocks]; # set clk_name [get_object_name [get_attribute [get_pins $my_pin_name] clocks]]; 7 | set clk_name [get_object_name $clk]; 8 | echo $my_pin_name $clk_name; 9 | 10 | } 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/rca.v: -------------------------------------------------------------------------------- 1 | module rca (input [7:0] num1 , input [7:0] num2 , output [8:0] sum); 2 | wire [7:0] int_sum; 3 | wire [7:0]int_co; 4 | 5 | genvar i; 6 | generate 7 | for (i = 1 ; i < 8; i=i+1) begin 8 | fa u_fa_1 (.a(num1[i]),.b(num2[i]),.c(int_co[i-1]),.co(int_co[i]),.sum(int_sum[i])); 9 | end 10 | 11 | endgenerate 12 | fa u_fa_0 (.a(num1[0]),.b(num2[0]),.c(1'b0),.co(int_co[0]),.sum(int_sum[0])); 13 | 14 | 15 | assign sum[7:0] = int_sum; 16 | assign sum[8] = int_co[7]; 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/reg_retime_cons.tcl: -------------------------------------------------------------------------------- 1 | #create_the_clocks 2 | create_clock -name myclk -per 2 [get_ports clk]; 3 | #model the practicalities of the clock 4 | set_clock_uncertainty -setup 0.3 [get_clocks myclk]; 5 | set_clock_uncertainty -hold 0.1 [get_clocks myclk]; 6 | 7 | #model IO delays 8 | set_input_delay -max 1.2 -clock [get_clocks myclk] [all_inputs]; 9 | set_output_delay -max 1.2 -clock [get_clocks myclk] [all_outputs]; 10 | 11 | set_input_delay -min 0.5 -clock [get_clocks myclk] [all_inputs]; 12 | set_output_delay -min 0.5 -clock [get_clocks myclk] [all_outputs]; 13 | 14 | set_input_transition -max 0.2 [all_inputs]; 15 | set_input_transition -min 0.05 [all_inputs]; 16 | 17 | set_load -max 0.2 [all_outputs]; 18 | set_load -min 0.05 [all_outputs]; 19 | 20 | 21 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/resource_sharing_mult_check.v: -------------------------------------------------------------------------------- 1 | module resource_sharing_mult_check (input [3:0] a , input [3:0] b, input [3:0] c , input [3:0] d, output [7:0] y , input sel); 2 | assign y = sel ? (a*b) : (c*d); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/retimed.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop/eb29a38c8125be9020b3577dfeabbe6843bca1fa/DC_WORKSHOP/verilog_files/retimed.ddc -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/ripple_counter.v: -------------------------------------------------------------------------------- 1 | module ripple_counter (input clk , input reset , output [1:0] q); 2 | reg [1:0]q_int; 3 | 4 | always @ (posedge clk, posedge reset) 5 | begin 6 | if(reset) 7 | q_int[0] <= 1'b0; 8 | else 9 | q_int[0] <= ~q_int[0]; 10 | end 11 | 12 | 13 | always @ (posedge q_int[0], posedge reset) 14 | begin 15 | 16 | if(reset) 17 | q_int[1] <= 1'b0; 18 | else 19 | q_int[1] <= ~q_int[1]; 20 | 21 | end 22 | 23 | assign q = q_int; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_case; 5 | // TB_SIGNALS 6 | reg clk, reset ; 7 | //input 8 | reg i0,i1,i2,i3; 9 | reg [1:0] sel; 10 | // Output 11 | wire y; 12 | 13 | // Instantiate the Unit Under Test (UUT) 14 | bad_case uut ( 15 | .i0(i0), 16 | .i1(i1), 17 | .i2(i2), 18 | .i3(i3), 19 | .sel(sel), 20 | .y(y) 21 | ); 22 | 23 | initial begin 24 | $dumpfile("tb_bad_case.vcd"); 25 | $dumpvars(0,tb_bad_case); 26 | // Initialize Inputs 27 | clk = 0; 28 | i0 = 1'b0; 29 | i1 = 1'b0; 30 | i2 = 1'b0; 31 | i3 = 1'b0 ; 32 | reset = 1'b0; #1; 33 | reset = 1'b1; #10; 34 | reset = 1'b0; 35 | 36 | #3000 $finish; 37 | end 38 | 39 | always #200 clk = ~clk; 40 | always #17 i0 = ~i0; 41 | always #37 i1 = ~i1; 42 | always #57 i2 = ~i2; 43 | always #97 i3 = ~i3; 44 | 45 | always @ (posedge clk , posedge reset) 46 | begin 47 | if(reset) 48 | sel <= 2'b00; 49 | else 50 | sel <= sel + 1; 51 | end 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_counter.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_bad_counter; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire [1:0] cnt; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | bad_counter uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .cnt(cnt) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_bad_counter.vcd"); 18 | $dumpvars(0,tb_bad_counter); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_latch.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_latch; 5 | // Inputs 6 | reg clk, reset, d; 7 | // Outputs 8 | wire q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | bad_latch uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .d(d), 15 | .q(q) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_bad_latch.vcd"); 20 | $dumpvars(0,tb_bad_latch); 21 | // Initialize Inputs 22 | clk = 0; 23 | reset = 1; 24 | d = 0; 25 | #300 $finish; 26 | end 27 | 28 | always #20 clk = ~clk; 29 | always #23 d = ~d; 30 | always #15 reset=0; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_latch2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_bad_latch; 3 | // Inputs 4 | reg clk, reset, d; 5 | // Outputs 6 | wire q; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | bad_latch uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .d(d), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_bad_latch.vcd"); 18 | $dumpvars(0,tb_bad_latch); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | d = 0; 23 | #300 $finish; 24 | end 25 | 26 | always #20 clk = ~clk; 27 | always #23 d = ~d; 28 | always #15 reset=0; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_mux.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_mux; 5 | // Inputs 6 | reg i0,i1,sel; 7 | // Outputs 8 | wire y; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | bad_mux uut ( 12 | .sel(sel), 13 | .i0(i0), 14 | .i1(i1), 15 | .y(y) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_bad_mux.vcd"); 20 | $dumpvars(0,tb_bad_mux); 21 | // Initialize Inputs 22 | sel = 1'b0; 23 | i0 = 1'b0; 24 | i1 = 1'b0; 25 | #300 $finish; 26 | end 27 | 28 | always #75 sel = ~sel; 29 | always #10 i0 = ~i0; 30 | always #55 i1 = ~i1; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_shift_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_bad_shift_reg; 3 | // Inputs 4 | reg clk, reset, d; 5 | // Outputs 6 | wire dout; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | bad_shift_reg uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .d(d), 13 | .dout(dout) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_bad_shift_reg.vcd"); 18 | $dumpvars(0,tb_bad_shift_reg); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | d = 0; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #173 d = ~d; 28 | always #123 reset=0; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_bad_shift_reg2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_shift_reg2; 5 | // Inputs 6 | reg clk, reset, d; 7 | // Outputs 8 | wire dout; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | bad_shift_reg2 uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .d(d), 15 | .dout(dout) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_bad_shift_reg2.vcd"); 20 | $dumpvars(0,tb_bad_shift_reg2); 21 | // Initialize Inputs 22 | clk = 0; 23 | reset = 1; 24 | d = 0; 25 | #3000 $finish; 26 | end 27 | 28 | always #20 clk = ~clk; 29 | always #223 d = ~d; 30 | always #113 reset = 0; 31 | endmodule 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_blocking_caveat.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_blocking_caveat; 4 | // Inputs 5 | reg a,b,c ; 6 | // Output 7 | wire d; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | blocking_caveat uut ( 11 | .a(a), 12 | .b(b), 13 | .c(c), 14 | .d(d) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_blocking_caveat.vcd"); 19 | $dumpvars(0,tb_blocking_caveat); 20 | // Initialize Inputs 21 | a = 0; 22 | b = 0; 23 | c = 0; 24 | #3000 $finish; 25 | end 26 | 27 | always #10 a = ~a; 28 | always #100 c =~c; 29 | always #50 b = ~b; 30 | endmodule 31 | 32 | 33 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_comp_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | `timescale 1ns / 1ps 7 | module tb_comp_case; 8 | //input 9 | reg i0,i1,i2; 10 | reg [1:0] sel; 11 | // Output 12 | wire y; 13 | //TB_SIGNALS 14 | reg clk,reset; 15 | 16 | // Instantiate the Unit Under Test (UUT) 17 | comp_case uut ( 18 | .sel(sel), 19 | .i0(i0), 20 | .i1(i1), 21 | .i2(i2), 22 | .y(y) 23 | ); 24 | 25 | initial begin 26 | $dumpfile("tb_comp_case.vcd"); 27 | $dumpvars(0,tb_comp_case); 28 | // Initialize Inputs 29 | i0 = 1'b0; 30 | i1 = 1'b0; 31 | i2 = 1'b0; 32 | clk = 1'b0; 33 | reset = 1'b0; #1; 34 | reset = 1'b1; #10; 35 | reset = 1'b0; 36 | 37 | 38 | #5000 $finish; 39 | end 40 | 41 | always #317 i0 = ~i0; 42 | always #600 clk = ~clk; 43 | always #37 i1 = ~i1; 44 | always #57 i2 = ~i2; 45 | 46 | 47 | always @(posedge clk , posedge reset) 48 | begin 49 | if(reset) 50 | sel <= 2'b00; 51 | else 52 | sel <= sel + 1; 53 | end 54 | endmodule 55 | 56 | 57 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_counter_opt.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_counter_opt; 5 | // Inputs 6 | reg clk, reset ; 7 | // Output 8 | wire q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | counter_opt uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_counter_opt.vcd"); 19 | $dumpvars(0,tb_counter_opt); 20 | // Initialize Inputs 21 | clk = 0; 22 | reset = 1; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #1547 reset=~reset; 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_demux_case.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_demux_case; 4 | // Inputs 5 | reg i; 6 | reg [2:0] sel; 7 | 8 | //TB Signals 9 | reg clk,reset; 10 | 11 | // Outputs 12 | wire o7,o6,o5,o4,o3,o2,o1,o0; 13 | 14 | // Instantiate the Unit Under Test (UUT) 15 | demux_case uut ( 16 | .sel(sel), 17 | .o0(o0), 18 | .o1(o1), 19 | .o2(o2), 20 | .o3(o3), 21 | .o4(o4), 22 | .o5(o5), 23 | .o6(o6), 24 | .o7(o7), 25 | .i(i) 26 | ); 27 | 28 | initial begin 29 | $dumpfile("tb_demux_case.vcd"); 30 | $dumpvars(0,tb_demux_case); 31 | // Initialize Inputs 32 | i = 1'b0; 33 | clk = 1'b0; 34 | reset = 1'b0 ; #1; 35 | reset = 1'b1 ; #10; 36 | reset = 1'b0; 37 | 38 | #3900 $finish; 39 | end 40 | 41 | always #17 i = ~i; 42 | always #300 clk = ~clk; 43 | 44 | always @ (posedge clk , posedge reset) 45 | begin 46 | if(reset) 47 | sel <= 3'b000; 48 | else 49 | sel <= sel + 1; 50 | end 51 | 52 | 53 | 54 | endmodule 55 | 56 | 57 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_demux_generate.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_demux_generate; 5 | // Inputs 6 | reg i; 7 | reg [2:0] sel; 8 | 9 | //TB Signals 10 | reg clk,reset; 11 | 12 | // Outputs 13 | wire o7,o6,o5,o4,o3,o2,o1,o0; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | demux_generate uut ( 17 | .sel(sel), 18 | .o0(o0), 19 | .o1(o1), 20 | .o2(o2), 21 | .o3(o3), 22 | .o4(o4), 23 | .o5(o5), 24 | .o6(o6), 25 | .o7(o7), 26 | .i(i) 27 | ); 28 | 29 | initial begin 30 | $dumpfile("tb_demux_generate.vcd"); 31 | $dumpvars(0,tb_demux_generate); 32 | // Initialize Inputs 33 | i = 1'b0; 34 | clk = 1'b0; 35 | reset = 1'b0 ; #1; 36 | reset = 1'b1 ; #10; 37 | reset = 1'b0; 38 | 39 | #3900 $finish; 40 | end 41 | 42 | always #17 i = ~i; 43 | always #300 clk = ~clk; 44 | 45 | always @ (posedge clk , posedge reset) 46 | begin 47 | if(reset) 48 | sel <= 3'b000; 49 | else 50 | sel <= sel + 1; 51 | end 52 | 53 | 54 | 55 | endmodule 56 | 57 | 58 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_async_set.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_dff_async_set; 5 | // Inputs 6 | reg clk, async_set, d; 7 | // Outputs 8 | wire q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | dff_async_set uut ( 12 | .clk(clk), 13 | .async_set(async_set), 14 | .d(d), 15 | .q(q) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_dff_async_set.vcd"); 20 | $dumpvars(0,tb_dff_async_set); 21 | // Initialize Inputs 22 | clk = 0; 23 | async_set = 1; 24 | d = 0; 25 | #3000 $finish; 26 | end 27 | 28 | always #10 clk = ~clk; 29 | always #23 d = ~d; 30 | always #547 async_set=~async_set; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_asyncres.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_asyncres; 4 | // Inputs 5 | reg clk, async_reset, d; 6 | // Outputs 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_asyncres uut ( 11 | .clk(clk), 12 | .async_reset(async_reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_dff_asyncres.vcd"); 19 | $dumpvars(0,tb_dff_asyncres); 20 | // Initialize Inputs 21 | clk = 0; 22 | async_reset = 1; 23 | d = 0; 24 | #3000 $finish; 25 | end 26 | 27 | always #10 clk = ~clk; 28 | always #23 d = ~d; 29 | always #547 async_reset=~async_reset; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_asyncres_syncres.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_dff_asyncres_syncres; 3 | // Inputs 4 | reg clk, async_reset, sync_reset, d; 5 | // Outputs 6 | wire q; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | dff_asyncres_syncres uut ( 10 | .clk(clk), 11 | .async_reset(async_reset), 12 | .sync_reset(sync_reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_dff_asyncres_syncres.vcd"); 19 | $dumpvars(0,tb_dff_asyncres_syncres); 20 | // Initialize Inputs 21 | clk = 0; 22 | async_reset = 1; 23 | sync_reset = 0; 24 | d = 0; 25 | #3000 $finish; 26 | end 27 | 28 | always #10 clk = ~clk; 29 | always #23 d = ~d; 30 | always #113 sync_reset = ~sync_reset; 31 | always #547 async_reset=~async_reset; 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_const1.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const1; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const1 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const1.vcd"); 18 | $dumpvars(0,tb_dff_const1); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_const2.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const2; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const2 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const2.vcd"); 18 | $dumpvars(0,tb_dff_const2); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_const3.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const3; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const3 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const3.vcd"); 18 | $dumpvars(0,tb_dff_const3); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_const3.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Aug 8 10:57:50 2021 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module tb_dff_const3 $end 11 | $var wire 1 ! q $end 12 | $var reg 1 " clk $end 13 | $var reg 1 # reset $end 14 | $scope module uut $end 15 | $var wire 1 " clk $end 16 | $var wire 1 # reset $end 17 | $var reg 1 ! q $end 18 | $var reg 1 $ q1 $end 19 | $upscope $end 20 | $upscope $end 21 | $enddefinitions $end 22 | #0 23 | $dumpvars 24 | 0$ 25 | 1# 26 | 0" 27 | 1! 28 | $end 29 | #10000 30 | 1" 31 | #20000 32 | 0" 33 | #30000 34 | 1" 35 | #40000 36 | 0" 37 | #50000 38 | 1" 39 | #60000 40 | 0" 41 | #70000 42 | 1" 43 | #80000 44 | 0" 45 | #90000 46 | 1" 47 | #100000 48 | 0" 49 | #110000 50 | 1" 51 | #120000 52 | 0" 53 | #130000 54 | 1" 55 | #140000 56 | 0" 57 | #150000 58 | 1" 59 | #160000 60 | 0" 61 | #170000 62 | 1" 63 | #180000 64 | 0" 65 | #190000 66 | 1" 67 | #200000 68 | 0" 69 | #210000 70 | 1" 71 | #220000 72 | 0" 73 | #230000 74 | 1" 75 | #240000 76 | 0" 77 | #250000 78 | 1" 79 | #260000 80 | 0" 81 | #270000 82 | 1" 83 | #280000 84 | 0" 85 | #290000 86 | 1" 87 | #300000 88 | 0" 89 | #310000 90 | 1" 91 | #320000 92 | 0" 93 | #330000 94 | 1" 95 | #340000 96 | 0" 97 | #350000 98 | 1" 99 | #360000 100 | 0" 101 | #370000 102 | 1" 103 | #380000 104 | 0" 105 | #390000 106 | 1" 107 | #400000 108 | 0" 109 | #410000 110 | 1" 111 | #420000 112 | 0" 113 | #430000 114 | 1" 115 | #440000 116 | 0" 117 | #450000 118 | 1" 119 | #460000 120 | 0" 121 | #470000 122 | 1" 123 | #480000 124 | 0" 125 | #490000 126 | 1" 127 | #500000 128 | 0" 129 | #510000 130 | 1" 131 | #520000 132 | 0" 133 | #530000 134 | 1" 135 | #540000 136 | 0" 137 | #550000 138 | 1" 139 | #560000 140 | 0" 141 | #570000 142 | 1" 143 | #580000 144 | 0" 145 | #590000 146 | 1" 147 | #600000 148 | 0" 149 | #610000 150 | 1" 151 | #620000 152 | 0" 153 | #630000 154 | 1" 155 | #640000 156 | 0" 157 | #650000 158 | 1" 159 | #660000 160 | 0" 161 | #670000 162 | 1" 163 | #680000 164 | 0" 165 | #690000 166 | 1" 167 | #700000 168 | 0" 169 | #710000 170 | 1" 171 | #720000 172 | 0" 173 | #730000 174 | 1" 175 | #740000 176 | 0" 177 | #750000 178 | 1" 179 | #760000 180 | 0" 181 | #770000 182 | 1" 183 | #780000 184 | 0" 185 | #790000 186 | 1" 187 | #800000 188 | 0" 189 | #810000 190 | 1" 191 | #820000 192 | 0" 193 | #830000 194 | 1" 195 | #840000 196 | 0" 197 | #850000 198 | 1" 199 | #860000 200 | 0" 201 | #870000 202 | 1" 203 | #880000 204 | 0" 205 | #890000 206 | 1" 207 | #900000 208 | 0" 209 | #910000 210 | 1" 211 | #920000 212 | 0" 213 | #930000 214 | 1" 215 | #940000 216 | 0" 217 | #950000 218 | 1" 219 | #960000 220 | 0" 221 | #970000 222 | 1" 223 | #980000 224 | 0" 225 | #990000 226 | 1" 227 | #1000000 228 | 0" 229 | #1010000 230 | 1" 231 | #1020000 232 | 0" 233 | #1030000 234 | 1" 235 | #1040000 236 | 0" 237 | #1050000 238 | 1" 239 | #1060000 240 | 0" 241 | #1070000 242 | 1" 243 | #1080000 244 | 0" 245 | #1090000 246 | 1" 247 | #1100000 248 | 0" 249 | #1110000 250 | 1" 251 | #1120000 252 | 0" 253 | #1130000 254 | 1" 255 | #1140000 256 | 0" 257 | #1150000 258 | 1" 259 | #1160000 260 | 0" 261 | #1170000 262 | 1" 263 | #1180000 264 | 0" 265 | #1190000 266 | 1" 267 | #1200000 268 | 0" 269 | #1210000 270 | 1" 271 | #1220000 272 | 0" 273 | #1230000 274 | 1" 275 | #1240000 276 | 0" 277 | #1250000 278 | 1" 279 | #1260000 280 | 0" 281 | #1270000 282 | 1" 283 | #1280000 284 | 0" 285 | #1290000 286 | 1" 287 | #1300000 288 | 0" 289 | #1310000 290 | 1" 291 | #1320000 292 | 0" 293 | #1330000 294 | 1" 295 | #1340000 296 | 0" 297 | #1350000 298 | 1" 299 | #1360000 300 | 0" 301 | #1370000 302 | 1" 303 | #1380000 304 | 0" 305 | #1390000 306 | 1" 307 | #1400000 308 | 0" 309 | #1410000 310 | 1" 311 | #1420000 312 | 0" 313 | #1430000 314 | 1" 315 | #1440000 316 | 0" 317 | #1450000 318 | 1" 319 | #1460000 320 | 0" 321 | #1470000 322 | 1" 323 | #1480000 324 | 0" 325 | #1490000 326 | 1" 327 | #1500000 328 | 0" 329 | #1510000 330 | 1" 331 | #1520000 332 | 0" 333 | #1530000 334 | 1" 335 | #1540000 336 | 0" 337 | #1547000 338 | 0# 339 | #1550000 340 | 0! 341 | 1$ 342 | 1" 343 | #1560000 344 | 0" 345 | #1570000 346 | 1! 347 | 1" 348 | #1580000 349 | 0" 350 | #1590000 351 | 1" 352 | #1600000 353 | 0" 354 | #1610000 355 | 1" 356 | #1620000 357 | 0" 358 | #1630000 359 | 1" 360 | #1640000 361 | 0" 362 | #1650000 363 | 1" 364 | #1660000 365 | 0" 366 | #1670000 367 | 1" 368 | #1680000 369 | 0" 370 | #1690000 371 | 1" 372 | #1700000 373 | 0" 374 | #1710000 375 | 1" 376 | #1720000 377 | 0" 378 | #1730000 379 | 1" 380 | #1740000 381 | 0" 382 | #1750000 383 | 1" 384 | #1760000 385 | 0" 386 | #1770000 387 | 1" 388 | #1780000 389 | 0" 390 | #1790000 391 | 1" 392 | #1800000 393 | 0" 394 | #1810000 395 | 1" 396 | #1820000 397 | 0" 398 | #1830000 399 | 1" 400 | #1840000 401 | 0" 402 | #1850000 403 | 1" 404 | #1860000 405 | 0" 406 | #1870000 407 | 1" 408 | #1880000 409 | 0" 410 | #1890000 411 | 1" 412 | #1900000 413 | 0" 414 | #1910000 415 | 1" 416 | #1920000 417 | 0" 418 | #1930000 419 | 1" 420 | #1940000 421 | 0" 422 | #1950000 423 | 1" 424 | #1960000 425 | 0" 426 | #1970000 427 | 1" 428 | #1980000 429 | 0" 430 | #1990000 431 | 1" 432 | #2000000 433 | 0" 434 | #2010000 435 | 1" 436 | #2020000 437 | 0" 438 | #2030000 439 | 1" 440 | #2040000 441 | 0" 442 | #2050000 443 | 1" 444 | #2060000 445 | 0" 446 | #2070000 447 | 1" 448 | #2080000 449 | 0" 450 | #2090000 451 | 1" 452 | #2100000 453 | 0" 454 | #2110000 455 | 1" 456 | #2120000 457 | 0" 458 | #2130000 459 | 1" 460 | #2140000 461 | 0" 462 | #2150000 463 | 1" 464 | #2160000 465 | 0" 466 | #2170000 467 | 1" 468 | #2180000 469 | 0" 470 | #2190000 471 | 1" 472 | #2200000 473 | 0" 474 | #2210000 475 | 1" 476 | #2220000 477 | 0" 478 | #2230000 479 | 1" 480 | #2240000 481 | 0" 482 | #2250000 483 | 1" 484 | #2260000 485 | 0" 486 | #2270000 487 | 1" 488 | #2280000 489 | 0" 490 | #2290000 491 | 1" 492 | #2300000 493 | 0" 494 | #2310000 495 | 1" 496 | #2320000 497 | 0" 498 | #2330000 499 | 1" 500 | #2340000 501 | 0" 502 | #2350000 503 | 1" 504 | #2360000 505 | 0" 506 | #2370000 507 | 1" 508 | #2380000 509 | 0" 510 | #2390000 511 | 1" 512 | #2400000 513 | 0" 514 | #2410000 515 | 1" 516 | #2420000 517 | 0" 518 | #2430000 519 | 1" 520 | #2440000 521 | 0" 522 | #2450000 523 | 1" 524 | #2460000 525 | 0" 526 | #2470000 527 | 1" 528 | #2480000 529 | 0" 530 | #2490000 531 | 1" 532 | #2500000 533 | 0" 534 | #2510000 535 | 1" 536 | #2520000 537 | 0" 538 | #2530000 539 | 1" 540 | #2540000 541 | 0" 542 | #2550000 543 | 1" 544 | #2560000 545 | 0" 546 | #2570000 547 | 1" 548 | #2580000 549 | 0" 550 | #2590000 551 | 1" 552 | #2600000 553 | 0" 554 | #2610000 555 | 1" 556 | #2620000 557 | 0" 558 | #2630000 559 | 1" 560 | #2640000 561 | 0" 562 | #2650000 563 | 1" 564 | #2660000 565 | 0" 566 | #2670000 567 | 1" 568 | #2680000 569 | 0" 570 | #2690000 571 | 1" 572 | #2700000 573 | 0" 574 | #2710000 575 | 1" 576 | #2720000 577 | 0" 578 | #2730000 579 | 1" 580 | #2740000 581 | 0" 582 | #2750000 583 | 1" 584 | #2760000 585 | 0" 586 | #2770000 587 | 1" 588 | #2780000 589 | 0" 590 | #2790000 591 | 1" 592 | #2800000 593 | 0" 594 | #2810000 595 | 1" 596 | #2820000 597 | 0" 598 | #2830000 599 | 1" 600 | #2840000 601 | 0" 602 | #2850000 603 | 1" 604 | #2860000 605 | 0" 606 | #2870000 607 | 1" 608 | #2880000 609 | 0" 610 | #2890000 611 | 1" 612 | #2900000 613 | 0" 614 | #2910000 615 | 1" 616 | #2920000 617 | 0" 618 | #2930000 619 | 1" 620 | #2940000 621 | 0" 622 | #2950000 623 | 1" 624 | #2960000 625 | 0" 626 | #2970000 627 | 1" 628 | #2980000 629 | 0" 630 | #2990000 631 | 1" 632 | #3000000 633 | 0" 634 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_const4.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const4; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const4 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const4.vcd"); 18 | $dumpvars(0,tb_dff_const4); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_const5.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const5; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const5 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const5.vcd"); 18 | $dumpvars(0,tb_dff_const5); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_dff_syncres.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_syncres; 4 | // Inputs 5 | reg clk, sync_reset, d; 6 | // Outputs 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_syncres uut ( 11 | .clk(clk), 12 | .sync_reset(sync_reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_dff_syncres.vcd"); 19 | $dumpvars(0,tb_dff_syncres); 20 | // Initialize Inputs 21 | clk = 0; 22 | sync_reset = 0; 23 | d = 0; 24 | #3000 $finish; 25 | end 26 | 27 | always #10 clk = ~clk; 28 | always #23 d = ~d; 29 | always #113 sync_reset = ~sync_reset; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_good_counter.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_good_counter; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire [1:0] cnt; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | good_counter uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .cnt(cnt) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_good_counter.vcd"); 18 | $dumpvars(0,tb_good_counter); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_good_latch.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_good_latch; 4 | // Inputs 5 | reg clk, reset, d; 6 | // Outputs 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | good_latch uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_good_latch.vcd"); 19 | $dumpvars(0,tb_good_latch); 20 | // Initialize Inputs 21 | clk = 0; 22 | reset = 1; 23 | d = 0; 24 | #300 $finish; 25 | end 26 | 27 | always #20 clk = ~clk; 28 | always #23 d = ~d; 29 | always #15 reset=0; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_good_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_good_mux; 3 | // Inputs 4 | reg i0,i1,sel; 5 | // Outputs 6 | wire y; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | good_mux uut ( 10 | .sel(sel), 11 | .i0(i0), 12 | .i1(i1), 13 | .y(y) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_good_mux.vcd"); 18 | $dumpvars(0,tb_good_mux); 19 | // Initialize Inputs 20 | sel = 0; 21 | i0 = 0; 22 | i1 = 0; 23 | #300 $finish; 24 | end 25 | 26 | always #75 sel = ~sel; 27 | always #10 i0 = ~i0; 28 | always #55 i1 = ~i1; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_good_shift_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_good_shift_reg; 3 | // Inputs 4 | reg clk, reset, d; 5 | // Outputs 6 | wire dout; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | good_shift_reg uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .d(d), 13 | .dout(dout) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_good_shift_reg.vcd"); 18 | $dumpvars(0,tb_good_shift_reg); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | d = 0; 23 | #3000 $finish; 24 | end 25 | 26 | always #20 clk = ~clk; 27 | always #223 d = ~d; 28 | always #147 reset = 0; 29 | endmodule 30 | 31 | 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_incomp_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | `timescale 1ns / 1ps 6 | module tb_incomp_case; 7 | //input 8 | reg i0,i1,i2; 9 | reg [1:0] sel; 10 | // Output 11 | wire y; 12 | //TB_SIGNALS 13 | reg clk,reset; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | incomp_case uut ( 17 | .sel(sel), 18 | .i0(i0), 19 | .i1(i1), 20 | .i2(i2), 21 | .y(y) 22 | ); 23 | 24 | initial begin 25 | $dumpfile("tb_incomp_case.vcd"); 26 | $dumpvars(0,tb_incomp_case); 27 | // Initialize Inputs 28 | i0 = 1'b0; 29 | i1 = 1'b0; 30 | i2 = 1'b0; 31 | clk = 1'b0; 32 | reset = 1'b0; #1; 33 | reset = 1'b1; #10; 34 | reset = 1'b0; 35 | 36 | 37 | #5000 $finish; 38 | end 39 | 40 | always #317 i0 = ~i0; 41 | always #600 clk = ~clk; 42 | always #37 i1 = ~i1; 43 | always #57 i2 = ~i2; 44 | 45 | 46 | always @(posedge clk , posedge reset) 47 | begin 48 | if(reset) 49 | sel <= 2'b00; 50 | else 51 | sel <= sel + 1; 52 | end 53 | endmodule 54 | 55 | 56 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_incomp_if.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 1ps 5 | module tb_incomp_if; 6 | //input 7 | reg i0,i1,i2; 8 | // Output 9 | wire y; 10 | 11 | // Instantiate the Unit Under Test (UUT) 12 | incomp_if uut ( 13 | .i0(i0), 14 | .i1(i1), 15 | .i2(i2), 16 | .y(y) 17 | ); 18 | 19 | initial begin 20 | $dumpfile("tb_incomp_if.vcd"); 21 | $dumpvars(0,tb_incomp_if); 22 | // Initialize Inputs 23 | i0 = 1'b0; 24 | i1 = 1'b0; 25 | i2 = 1'b0; 26 | 27 | #3000 $finish; 28 | end 29 | 30 | always #317 i0 = ~i0; 31 | always #37 i1 = ~i1; 32 | always #57 i2 = ~i2; 33 | 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_incomp_if2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 1ps 5 | module tb_incomp_if2; 6 | //input 7 | reg i0,i1,i2,i3; 8 | // Output 9 | wire y; 10 | 11 | // Instantiate the Unit Under Test (UUT) 12 | incomp_if2 uut ( 13 | .i0(i0), 14 | .i1(i1), 15 | .i2(i2), 16 | .i3(i3), 17 | .y(y) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("tb_incomp_if2.vcd"); 22 | $dumpvars(0,tb_incomp_if2); 23 | // Initialize Inputs 24 | i0 = 1'b0; 25 | i1 = 1'b0; 26 | i2 = 1'b0; 27 | i3 = 1'b0; 28 | 29 | #3000 $finish; 30 | end 31 | 32 | always #317 i0 = ~i0; 33 | always #37 i1 = ~i1; 34 | always #157 i2 = ~i2; 35 | always #67 i3 = ~i3; 36 | 37 | endmodule 38 | 39 | 40 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_lab1_flop_with_en.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_lab1_flop_with_en (); 3 | 4 | reg clk , d , res, en; 5 | wire q; 6 | 7 | lab1_flop_with_en uut ( 8 | .clk (clk), 9 | .res(res), 10 | .d(d), 11 | .en(en), 12 | .q(q)); 13 | 14 | initial 15 | begin 16 | $dumpfile("tb_lab1_flop_with_en.vcd"); 17 | $dumpvars(0,tb_lab1_flop_with_en); 18 | clk = 1'b0; 19 | d = 1'b0; 20 | en = 1'b0; 21 | res = 1'b1; # 200; 22 | res = 1'b0; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #33 d = ~d; 28 | always #77 en = ~en; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_lab1_flop_with_en.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Aug 1 11:02:30 2021 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module tb_lab1_flop_with_en $end 11 | $var wire 1 ! q $end 12 | $var reg 1 " clk $end 13 | $var reg 1 # d $end 14 | $var reg 1 $ en $end 15 | $var reg 1 % res $end 16 | $scope module uut $end 17 | $var wire 1 " clk $end 18 | $var wire 1 # d $end 19 | $var wire 1 $ en $end 20 | $var wire 1 % res $end 21 | $var reg 1 ! q $end 22 | $upscope $end 23 | $upscope $end 24 | $enddefinitions $end 25 | #0 26 | $dumpvars 27 | 1% 28 | 0$ 29 | 0# 30 | 0" 31 | 0! 32 | $end 33 | #10000 34 | 1" 35 | #20000 36 | 0" 37 | #30000 38 | 1" 39 | #33000 40 | 1# 41 | #40000 42 | 0" 43 | #50000 44 | 1" 45 | #60000 46 | 0" 47 | #66000 48 | 0# 49 | #70000 50 | 1" 51 | #77000 52 | 1$ 53 | #80000 54 | 0" 55 | #90000 56 | 1" 57 | #99000 58 | 1# 59 | #100000 60 | 0" 61 | #110000 62 | 1" 63 | #120000 64 | 0" 65 | #130000 66 | 1" 67 | #132000 68 | 0# 69 | #140000 70 | 0" 71 | #150000 72 | 1" 73 | #154000 74 | 0$ 75 | #160000 76 | 0" 77 | #165000 78 | 1# 79 | #170000 80 | 1" 81 | #180000 82 | 0" 83 | #190000 84 | 1" 85 | #198000 86 | 0# 87 | #200000 88 | 0" 89 | 0% 90 | #210000 91 | 1" 92 | #220000 93 | 0" 94 | #230000 95 | 1" 96 | #231000 97 | 1# 98 | 1$ 99 | #240000 100 | 0" 101 | #250000 102 | 1! 103 | 1" 104 | #260000 105 | 0" 106 | #264000 107 | 0# 108 | #270000 109 | 0! 110 | 1" 111 | #280000 112 | 0" 113 | #290000 114 | 1" 115 | #297000 116 | 1# 117 | #300000 118 | 0" 119 | #308000 120 | 0$ 121 | #310000 122 | 1" 123 | #320000 124 | 0" 125 | #330000 126 | 1" 127 | 0# 128 | #340000 129 | 0" 130 | #350000 131 | 1" 132 | #360000 133 | 0" 134 | #363000 135 | 1# 136 | #370000 137 | 1" 138 | #380000 139 | 0" 140 | #385000 141 | 1$ 142 | #390000 143 | 1! 144 | 1" 145 | #396000 146 | 0# 147 | #400000 148 | 0" 149 | #410000 150 | 0! 151 | 1" 152 | #420000 153 | 0" 154 | #429000 155 | 1# 156 | #430000 157 | 1! 158 | 1" 159 | #440000 160 | 0" 161 | #450000 162 | 1" 163 | #460000 164 | 0" 165 | #462000 166 | 0# 167 | 0$ 168 | #470000 169 | 1" 170 | #480000 171 | 0" 172 | #490000 173 | 1" 174 | #495000 175 | 1# 176 | #500000 177 | 0" 178 | #510000 179 | 1" 180 | #520000 181 | 0" 182 | #528000 183 | 0# 184 | #530000 185 | 1" 186 | #539000 187 | 1$ 188 | #540000 189 | 0" 190 | #550000 191 | 0! 192 | 1" 193 | #560000 194 | 0" 195 | #561000 196 | 1# 197 | #570000 198 | 1! 199 | 1" 200 | #580000 201 | 0" 202 | #590000 203 | 1" 204 | #594000 205 | 0# 206 | #600000 207 | 0" 208 | #610000 209 | 0! 210 | 1" 211 | #616000 212 | 0$ 213 | #620000 214 | 0" 215 | #627000 216 | 1# 217 | #630000 218 | 1" 219 | #640000 220 | 0" 221 | #650000 222 | 1" 223 | #660000 224 | 0" 225 | 0# 226 | #670000 227 | 1" 228 | #680000 229 | 0" 230 | #690000 231 | 1" 232 | #693000 233 | 1# 234 | 1$ 235 | #700000 236 | 0" 237 | #710000 238 | 1! 239 | 1" 240 | #720000 241 | 0" 242 | #726000 243 | 0# 244 | #730000 245 | 0! 246 | 1" 247 | #740000 248 | 0" 249 | #750000 250 | 1" 251 | #759000 252 | 1# 253 | #760000 254 | 0" 255 | #770000 256 | 1" 257 | 0$ 258 | #780000 259 | 0" 260 | #790000 261 | 1" 262 | #792000 263 | 0# 264 | #800000 265 | 0" 266 | #810000 267 | 1" 268 | #820000 269 | 0" 270 | #825000 271 | 1# 272 | #830000 273 | 1" 274 | #840000 275 | 0" 276 | #847000 277 | 1$ 278 | #850000 279 | 1! 280 | 1" 281 | #858000 282 | 0# 283 | #860000 284 | 0" 285 | #870000 286 | 0! 287 | 1" 288 | #880000 289 | 0" 290 | #890000 291 | 1" 292 | #891000 293 | 1# 294 | #900000 295 | 0" 296 | #910000 297 | 1! 298 | 1" 299 | #920000 300 | 0" 301 | #924000 302 | 0# 303 | 0$ 304 | #930000 305 | 1" 306 | #940000 307 | 0" 308 | #950000 309 | 1" 310 | #957000 311 | 1# 312 | #960000 313 | 0" 314 | #970000 315 | 1" 316 | #980000 317 | 0" 318 | #990000 319 | 1" 320 | 0# 321 | #1000000 322 | 0" 323 | #1001000 324 | 1$ 325 | #1010000 326 | 0! 327 | 1" 328 | #1020000 329 | 0" 330 | #1023000 331 | 1# 332 | #1030000 333 | 1! 334 | 1" 335 | #1040000 336 | 0" 337 | #1050000 338 | 1" 339 | #1056000 340 | 0# 341 | #1060000 342 | 0" 343 | #1070000 344 | 0! 345 | 1" 346 | #1078000 347 | 0$ 348 | #1080000 349 | 0" 350 | #1089000 351 | 1# 352 | #1090000 353 | 1" 354 | #1100000 355 | 0" 356 | #1110000 357 | 1" 358 | #1120000 359 | 0" 360 | #1122000 361 | 0# 362 | #1130000 363 | 1" 364 | #1140000 365 | 0" 366 | #1150000 367 | 1" 368 | #1155000 369 | 1# 370 | 1$ 371 | #1160000 372 | 0" 373 | #1170000 374 | 1! 375 | 1" 376 | #1180000 377 | 0" 378 | #1188000 379 | 0# 380 | #1190000 381 | 0! 382 | 1" 383 | #1200000 384 | 0" 385 | #1210000 386 | 1" 387 | #1220000 388 | 0" 389 | #1221000 390 | 1# 391 | #1230000 392 | 1! 393 | 1" 394 | #1232000 395 | 0$ 396 | #1240000 397 | 0" 398 | #1250000 399 | 1" 400 | #1254000 401 | 0# 402 | #1260000 403 | 0" 404 | #1270000 405 | 1" 406 | #1280000 407 | 0" 408 | #1287000 409 | 1# 410 | #1290000 411 | 1" 412 | #1300000 413 | 0" 414 | #1309000 415 | 1$ 416 | #1310000 417 | 1" 418 | #1320000 419 | 0" 420 | 0# 421 | #1330000 422 | 0! 423 | 1" 424 | #1340000 425 | 0" 426 | #1350000 427 | 1" 428 | #1353000 429 | 1# 430 | #1360000 431 | 0" 432 | #1370000 433 | 1! 434 | 1" 435 | #1380000 436 | 0" 437 | #1386000 438 | 0# 439 | 0$ 440 | #1390000 441 | 1" 442 | #1400000 443 | 0" 444 | #1410000 445 | 1" 446 | #1419000 447 | 1# 448 | #1420000 449 | 0" 450 | #1430000 451 | 1" 452 | #1440000 453 | 0" 454 | #1450000 455 | 1" 456 | #1452000 457 | 0# 458 | #1460000 459 | 0" 460 | #1463000 461 | 1$ 462 | #1470000 463 | 0! 464 | 1" 465 | #1480000 466 | 0" 467 | #1485000 468 | 1# 469 | #1490000 470 | 1! 471 | 1" 472 | #1500000 473 | 0" 474 | #1510000 475 | 1" 476 | #1518000 477 | 0# 478 | #1520000 479 | 0" 480 | #1530000 481 | 0! 482 | 1" 483 | #1540000 484 | 0" 485 | 0$ 486 | #1550000 487 | 1" 488 | #1551000 489 | 1# 490 | #1560000 491 | 0" 492 | #1570000 493 | 1" 494 | #1580000 495 | 0" 496 | #1584000 497 | 0# 498 | #1590000 499 | 1" 500 | #1600000 501 | 0" 502 | #1610000 503 | 1" 504 | #1617000 505 | 1# 506 | 1$ 507 | #1620000 508 | 0" 509 | #1630000 510 | 1! 511 | 1" 512 | #1640000 513 | 0" 514 | #1650000 515 | 0! 516 | 1" 517 | 0# 518 | #1660000 519 | 0" 520 | #1670000 521 | 1" 522 | #1680000 523 | 0" 524 | #1683000 525 | 1# 526 | #1690000 527 | 1! 528 | 1" 529 | #1694000 530 | 0$ 531 | #1700000 532 | 0" 533 | #1710000 534 | 1" 535 | #1716000 536 | 0# 537 | #1720000 538 | 0" 539 | #1730000 540 | 1" 541 | #1740000 542 | 0" 543 | #1749000 544 | 1# 545 | #1750000 546 | 1" 547 | #1760000 548 | 0" 549 | #1770000 550 | 1" 551 | #1771000 552 | 1$ 553 | #1780000 554 | 0" 555 | #1782000 556 | 0# 557 | #1790000 558 | 0! 559 | 1" 560 | #1800000 561 | 0" 562 | #1810000 563 | 1" 564 | #1815000 565 | 1# 566 | #1820000 567 | 0" 568 | #1830000 569 | 1! 570 | 1" 571 | #1840000 572 | 0" 573 | #1848000 574 | 0# 575 | 0$ 576 | #1850000 577 | 1" 578 | #1860000 579 | 0" 580 | #1870000 581 | 1" 582 | #1880000 583 | 0" 584 | #1881000 585 | 1# 586 | #1890000 587 | 1" 588 | #1900000 589 | 0" 590 | #1910000 591 | 1" 592 | #1914000 593 | 0# 594 | #1920000 595 | 0" 596 | #1925000 597 | 1$ 598 | #1930000 599 | 0! 600 | 1" 601 | #1940000 602 | 0" 603 | #1947000 604 | 1# 605 | #1950000 606 | 1! 607 | 1" 608 | #1960000 609 | 0" 610 | #1970000 611 | 1" 612 | #1980000 613 | 0" 614 | 0# 615 | #1990000 616 | 0! 617 | 1" 618 | #2000000 619 | 0" 620 | #2002000 621 | 0$ 622 | #2010000 623 | 1" 624 | #2013000 625 | 1# 626 | #2020000 627 | 0" 628 | #2030000 629 | 1" 630 | #2040000 631 | 0" 632 | #2046000 633 | 0# 634 | #2050000 635 | 1" 636 | #2060000 637 | 0" 638 | #2070000 639 | 1" 640 | #2079000 641 | 1# 642 | 1$ 643 | #2080000 644 | 0" 645 | #2090000 646 | 1! 647 | 1" 648 | #2100000 649 | 0" 650 | #2110000 651 | 1" 652 | #2112000 653 | 0# 654 | #2120000 655 | 0" 656 | #2130000 657 | 0! 658 | 1" 659 | #2140000 660 | 0" 661 | #2145000 662 | 1# 663 | #2150000 664 | 1! 665 | 1" 666 | #2156000 667 | 0$ 668 | #2160000 669 | 0" 670 | #2170000 671 | 1" 672 | #2178000 673 | 0# 674 | #2180000 675 | 0" 676 | #2190000 677 | 1" 678 | #2200000 679 | 0" 680 | #2210000 681 | 1" 682 | #2211000 683 | 1# 684 | #2220000 685 | 0" 686 | #2230000 687 | 1" 688 | #2233000 689 | 1$ 690 | #2240000 691 | 0" 692 | #2244000 693 | 0# 694 | #2250000 695 | 0! 696 | 1" 697 | #2260000 698 | 0" 699 | #2270000 700 | 1" 701 | #2277000 702 | 1# 703 | #2280000 704 | 0" 705 | #2290000 706 | 1! 707 | 1" 708 | #2300000 709 | 0" 710 | #2310000 711 | 1" 712 | 0# 713 | 0$ 714 | #2320000 715 | 0" 716 | #2330000 717 | 1" 718 | #2340000 719 | 0" 720 | #2343000 721 | 1# 722 | #2350000 723 | 1" 724 | #2360000 725 | 0" 726 | #2370000 727 | 1" 728 | #2376000 729 | 0# 730 | #2380000 731 | 0" 732 | #2387000 733 | 1$ 734 | #2390000 735 | 0! 736 | 1" 737 | #2400000 738 | 0" 739 | #2409000 740 | 1# 741 | #2410000 742 | 1! 743 | 1" 744 | #2420000 745 | 0" 746 | #2430000 747 | 1" 748 | #2440000 749 | 0" 750 | #2442000 751 | 0# 752 | #2450000 753 | 0! 754 | 1" 755 | #2460000 756 | 0" 757 | #2464000 758 | 0$ 759 | #2470000 760 | 1" 761 | #2475000 762 | 1# 763 | #2480000 764 | 0" 765 | #2490000 766 | 1" 767 | #2500000 768 | 0" 769 | #2508000 770 | 0# 771 | #2510000 772 | 1" 773 | #2520000 774 | 0" 775 | #2530000 776 | 1" 777 | #2540000 778 | 0" 779 | #2541000 780 | 1# 781 | 1$ 782 | #2550000 783 | 1! 784 | 1" 785 | #2560000 786 | 0" 787 | #2570000 788 | 1" 789 | #2574000 790 | 0# 791 | #2580000 792 | 0" 793 | #2590000 794 | 0! 795 | 1" 796 | #2600000 797 | 0" 798 | #2607000 799 | 1# 800 | #2610000 801 | 1! 802 | 1" 803 | #2618000 804 | 0$ 805 | #2620000 806 | 0" 807 | #2630000 808 | 1" 809 | #2640000 810 | 0" 811 | 0# 812 | #2650000 813 | 1" 814 | #2660000 815 | 0" 816 | #2670000 817 | 1" 818 | #2673000 819 | 1# 820 | #2680000 821 | 0" 822 | #2690000 823 | 1" 824 | #2695000 825 | 1$ 826 | #2700000 827 | 0" 828 | #2706000 829 | 0# 830 | #2710000 831 | 0! 832 | 1" 833 | #2720000 834 | 0" 835 | #2730000 836 | 1" 837 | #2739000 838 | 1# 839 | #2740000 840 | 0" 841 | #2750000 842 | 1! 843 | 1" 844 | #2760000 845 | 0" 846 | #2770000 847 | 1" 848 | #2772000 849 | 0# 850 | 0$ 851 | #2780000 852 | 0" 853 | #2790000 854 | 1" 855 | #2800000 856 | 0" 857 | #2805000 858 | 1# 859 | #2810000 860 | 1" 861 | #2820000 862 | 0" 863 | #2830000 864 | 1" 865 | #2838000 866 | 0# 867 | #2840000 868 | 0" 869 | #2849000 870 | 1$ 871 | #2850000 872 | 0! 873 | 1" 874 | #2860000 875 | 0" 876 | #2870000 877 | 1" 878 | #2871000 879 | 1# 880 | #2880000 881 | 0" 882 | #2890000 883 | 1! 884 | 1" 885 | #2900000 886 | 0" 887 | #2904000 888 | 0# 889 | #2910000 890 | 0! 891 | 1" 892 | #2920000 893 | 0" 894 | #2926000 895 | 0$ 896 | #2930000 897 | 1" 898 | #2937000 899 | 1# 900 | #2940000 901 | 0" 902 | #2950000 903 | 1" 904 | #2960000 905 | 0" 906 | #2970000 907 | 1" 908 | 0# 909 | #2980000 910 | 0" 911 | #2990000 912 | 1" 913 | #3000000 914 | 0" 915 | #3003000 916 | 1# 917 | 1$ 918 | #3010000 919 | 1! 920 | 1" 921 | #3020000 922 | 0" 923 | #3030000 924 | 1" 925 | #3036000 926 | 0# 927 | #3040000 928 | 0" 929 | #3050000 930 | 0! 931 | 1" 932 | #3060000 933 | 0" 934 | #3069000 935 | 1# 936 | #3070000 937 | 1! 938 | 1" 939 | #3080000 940 | 0" 941 | 0$ 942 | #3090000 943 | 1" 944 | #3100000 945 | 0" 946 | #3102000 947 | 0# 948 | #3110000 949 | 1" 950 | #3120000 951 | 0" 952 | #3130000 953 | 1" 954 | #3135000 955 | 1# 956 | #3140000 957 | 0" 958 | #3150000 959 | 1" 960 | #3157000 961 | 1$ 962 | #3160000 963 | 0" 964 | #3168000 965 | 0# 966 | #3170000 967 | 0! 968 | 1" 969 | #3180000 970 | 0" 971 | #3190000 972 | 1" 973 | #3200000 974 | 0" 975 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_multiple_modules.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 1ps 5 | module tb_multiple_modules; 6 | // Inputs 7 | reg a,b,c; 8 | // Outputs 9 | wire y; 10 | 11 | // Instantiate the Unit Under Test (UUT) 12 | multiple_modules uut ( 13 | .a(a), 14 | .b(b), 15 | .c(c), 16 | .y(y) 17 | ); 18 | 19 | initial begin 20 | $dumpfile("tb_multiple_modules.vcd"); 21 | $dumpvars(0,tb_multiple_modules); 22 | // Initialize Inputs 23 | a = 0; 24 | b = 0; 25 | c = 0; 26 | #300 $finish; 27 | end 28 | 29 | always #10 a = ~a; 30 | always #55 b = ~b; 31 | always #75 c = ~c; 32 | endmodule 33 | 34 | 35 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_mux_generate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_mux_generate; 3 | // Inputs 4 | reg i0,i1; 5 | reg i2,i3; 6 | reg [1:0] sel; 7 | 8 | //TB Signals 9 | reg clk,reset; 10 | 11 | // Outputs 12 | wire y; 13 | 14 | // Instantiate the Unit Under Test (UUT) 15 | mux_generate uut ( 16 | .sel(sel), 17 | .i0(i0), 18 | .i1(i1), 19 | .i2(i2), 20 | .i3(i3), 21 | .y(y) 22 | ); 23 | 24 | initial begin 25 | $dumpfile("tb_mux_generate.vcd"); 26 | $dumpvars(0,tb_mux_generate); 27 | // Initialize Inputs 28 | i0 = 1'b0; 29 | i1 = 1'b0; 30 | i2 = 1'b0; 31 | i3 = 1'b0; 32 | clk = 1'b0; 33 | reset = 1'b0 ; #1; 34 | reset = 1'b1 ; #10; 35 | reset = 1'b0; 36 | 37 | #3000 $finish; 38 | end 39 | 40 | always #17 i0 = ~i0; 41 | always #37 i1 = ~i1; 42 | always #88 i2 = ~i2; 43 | always #155 i3 = ~i3; 44 | always #300 clk = ~clk; 45 | 46 | always @ (posedge clk , posedge reset) 47 | begin 48 | if(reset) 49 | sel <= 2'b00; 50 | else 51 | sel <= sel + 1; 52 | end 53 | 54 | 55 | 56 | endmodule 57 | 58 | 59 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_opt_check.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_opt_check; 4 | // Inputs 5 | reg a,b; 6 | // Outputs 7 | wire y; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | opt_check uut ( 11 | .a(a), 12 | .b(b), 13 | .y(y) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_opt_check.vcd"); 18 | $dumpvars(0,tb_opt_check); 19 | // Initialize Inputs 20 | a = 0; 21 | b = 0; 22 | #300 $finish; 23 | end 24 | 25 | always #10 a = ~a; 26 | always #55 b = ~b; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_opt_check2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_opt_check2; 5 | // Inputs 6 | reg a,b; 7 | // Outputs 8 | wire y; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | opt_check2 uut ( 12 | .a(a), 13 | .b(b), 14 | .y(y) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_opt_check2.vcd"); 19 | $dumpvars(0,tb_opt_check2); 20 | // Initialize Inputs 21 | a = 0; 22 | b = 0; 23 | #300 $finish; 24 | end 25 | 26 | always #10 a = ~a; 27 | always #55 b = ~b; 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_opt_check3.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_opt_check3; 5 | // Inputs 6 | reg a,b,c; 7 | // Outputs 8 | wire y; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | opt_check3 uut ( 12 | .a(a), 13 | .b(b), 14 | .c(c), 15 | .y(y) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_opt_check3.vcd"); 20 | $dumpvars(0,tb_opt_check3); 21 | // Initialize Inputs 22 | a = 0; 23 | b = 0; 24 | c = 0; 25 | #300 $finish; 26 | end 27 | 28 | always #10 a = ~a; 29 | always #55 b = ~b; 30 | always #75 c = ~c; 31 | endmodule 32 | 33 | 34 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_partial_case_assign.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | `timescale 1ns / 1ps 7 | module tb_partial_case_assign.v; 8 | //input 9 | reg i0,i1,i2,sel; 10 | // Output 11 | wire x,y; 12 | //TB_SIGNALS 13 | reg clk,reset; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | partial_case_assign.v uut ( 17 | .sel(sel), 18 | .i0(i0), 19 | .i1(i1), 20 | .i2(i2), 21 | .i3(i3), 22 | .x(x), 23 | .y(y) 24 | ); 25 | 26 | initial begin 27 | $dumpfile("tb_partial_case_assign.v.vcd"); 28 | $dumpvars(0,tb_partial_case_assign.v); 29 | // Initialize Inputs 30 | i0 = 1'b0; 31 | i1 = 1'b0; 32 | i2 = 1'b0; 33 | clk = 1'b0; 34 | reset = 1'b0; #1; 35 | reset = 1'b1; #10; 36 | reset = 1'b0; 37 | 38 | 39 | #5000 $finish; 40 | end 41 | 42 | always #317 i0 = ~i0; 43 | always #600 clk = ~clk; 44 | always #37 i1 = ~i1; 45 | always #57 i2 = ~i2; 46 | 47 | 48 | always @(posedge clk , posedge reset) 49 | begin 50 | if(reset) 51 | sel <= 2'b00; 52 | else 53 | sel <= sel + 1; 54 | end 55 | endmodule 56 | 57 | 58 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_pattern_detect_fsm.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_upcntr; 3 | // Inputs 4 | reg clk, reset; 5 | // Outputs 6 | wire [3:0] cnt; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | upcntr uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .din(din), 13 | .pattern_detect(pattern_detect) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_upcntr.vcd"); 18 | $dumpvars(0,tb_upcntr); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #123 reset=0; 27 | endmodule 28 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_rca.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_rca; 3 | // TB_SIGNALS 4 | reg clk, reset ; 5 | reg [7:0] num1 ; 6 | reg [7:0] num2; 7 | wire [8:0] sum_out; 8 | // Instantiate the Unit Under Test (UUT) 9 | rca uut ( 10 | .num1(num1), 11 | .num2(num2), 12 | .sum(sum_out) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("tb_rca.vcd"); 17 | $dumpvars(0,tb_rca); 18 | // Initialize Inputs 19 | clk = 0; 20 | reset = 0; 21 | reset = 1; #1; 22 | reset = 0; #10; 23 | #30000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | 28 | 29 | always @ (clk,reset) 30 | begin 31 | if(reset) 32 | begin 33 | num1 <= 8'b0; 34 | num2 <= 8'b0; 35 | end 36 | else 37 | begin 38 | num1 = num1 + 1; 39 | if(num1[3:0] == 4'b1111) 40 | num2 = num2+1; 41 | end 42 | 43 | end 44 | 45 | 46 | endmodule 47 | 48 | 49 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_ripple_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_ripple_counter; 3 | // Inputs 4 | reg clk, reset ; 5 | // Output 6 | wire [1:0] q; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | ripple_counter uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .q(q) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("tb_ripple_counter.vcd"); 17 | $dumpvars(0,tb_ripple_counter); 18 | // Initialize Inputs 19 | clk = 0; 20 | reset = 1; 21 | #3000 $finish; 22 | end 23 | 24 | always #10 clk = ~clk; 25 | always #1547 reset=~reset; 26 | endmodule 27 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_ternary_operator_mux.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_ternary_operator_mux; 4 | // Inputs 5 | reg i0,i1,sel; 6 | // Outputs 7 | wire y; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | ternary_operator_mux uut ( 11 | .sel(sel), 12 | .i0(i0), 13 | .i1(i1), 14 | .y(y) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_ternary_operator_mux.vcd"); 19 | $dumpvars(0,tb_ternary_operator_mux); 20 | // Initialize Inputs 21 | sel = 0; 22 | i0 = 0; 23 | i1 = 0; 24 | #300 $finish; 25 | end 26 | 27 | always #75 sel = ~sel; 28 | always #10 i0 = ~i0; 29 | always #55 i1 = ~i1; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_up_dn_cntr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_up_dn_cntr; 3 | // Inputs 4 | reg clk, reset, up_dnb; 5 | // Outputs 6 | wire [3:0] cnt; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | up_dn_cntr uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .up_dnb(up_dnb), 13 | .cnt(cnt) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_up_dn_cntr.vcd"); 18 | $dumpvars(0,tb_up_dn_cntr); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | up_dnb = 1; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #501 up_dnb = ~up_dnb; 28 | always #123 reset=0; 29 | endmodule 30 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_up_dn_cntr_with_load.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_up_dn_cntr_with_load; 3 | // Inputs 4 | reg clk, reset, load_en , up_dnb ; 5 | reg [3:0] load_data; 6 | reg load_en_1 , load_en_2; 7 | // Outputs 8 | wire [3:0] cnt; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | up_dn_cntr_with_load uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .load_en(load_en), 15 | .load_data(load_data), 16 | .up_dnb(up_dnb), 17 | .cnt(cnt) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("tb_up_dn_cntr_with_load.vcd"); 22 | $dumpvars(0,tb_up_dn_cntr_with_load); 23 | // Initialize Inputs 24 | clk = 0; 25 | reset = 1; 26 | up_dnb = 1; 27 | load_en_1 = 0; 28 | load_en_2 = 0; 29 | load_data = 4'b0000; 30 | #3000 $finish; 31 | end 32 | 33 | always #5 clk = ~clk; 34 | always #123 reset = 0; 35 | always #130 load_data = load_data + 1; 36 | always #540 load_en_1 = ~load_en_1; 37 | always #1340 up_dnb = ~up_dnb; 38 | always #1 load_en = load_en_1 ^ load_en_2; 39 | 40 | always @ (posedge clk , posedge reset) 41 | begin 42 | if(reset) 43 | load_en_2 = 1'b0; 44 | else 45 | load_en_2 = load_en_1; 46 | end 47 | 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_up_dn_cntr_with_load_with_start_stop.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_up_dn_cntr_with_load_with_start_stop; 3 | // Inputs 4 | reg clk, reset, load_en , up_dnb , start_stop_b ; 5 | reg [3:0] load_data; 6 | reg load_en_1 , load_en_2; 7 | // Outputs 8 | wire [3:0] cnt; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | up_dn_cntr_with_load_with_start_stop uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .load_en(load_en), 15 | .load_data(load_data), 16 | .up_dnb(up_dnb), 17 | .start_stop_b(start_stop_b), 18 | .cnt(cnt) 19 | ); 20 | 21 | initial begin 22 | $dumpfile("tb_up_dn_cntr_with_load_with_start_stop.vcd"); 23 | $dumpvars(0,tb_up_dn_cntr_with_load_with_start_stop); 24 | // Initialize Inputs 25 | clk = 0; 26 | reset = 1; 27 | up_dnb = 1; 28 | load_en_1 = 0; 29 | load_en_2 = 0; 30 | load_data = 4'b0000; 31 | start_stop_b = 1'b0; 32 | #7000 $finish; 33 | end 34 | 35 | always #5 clk = ~clk; 36 | always #123 reset = 0; 37 | always #130 load_data = load_data + 1; 38 | always #540 load_en_1 = ~load_en_1; 39 | always #1340 up_dnb = ~up_dnb; 40 | always #880 start_stop_b = ~start_stop_b; 41 | always #1 load_en = load_en_1 ^ load_en_2; 42 | 43 | always @ (posedge clk , posedge reset) 44 | begin 45 | if(reset) 46 | load_en_2 = 1'b0; 47 | else 48 | load_en_2 = load_en_1; 49 | end 50 | 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/tb_upcntr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_upcntr; 3 | // Inputs 4 | reg clk, reset; 5 | // Outputs 6 | wire [3:0] cnt; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | upcntr uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .cnt(cnt) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("tb_upcntr.vcd"); 17 | $dumpvars(0,tb_upcntr); 18 | // Initialize Inputs 19 | clk = 0; 20 | reset = 1; 21 | #3000 $finish; 22 | end 23 | 24 | always #10 clk = ~clk; 25 | always #123 reset=0; 26 | endmodule 27 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/ternary_operator_mux.v: -------------------------------------------------------------------------------- 1 | module ternary_operator_mux (input i0 , input i1 , input sel , output y); 2 | assign y = sel?i1:i0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/up_dn_cntr.v: -------------------------------------------------------------------------------- 1 | 2 | module up_dn_cntr (input clk , input reset,input up_dnb , output reg [3:0] cnt); 3 | always @ (posedge clk , posedge reset) 4 | begin 5 | if(reset) 6 | cnt <= 4'b0000; 7 | else 8 | begin 9 | if(up_dnb) 10 | cnt <= cnt + 1; 11 | else 12 | cnt <= cnt - 1; 13 | end 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/up_dn_cntr_with_load.v: -------------------------------------------------------------------------------- 1 | 2 | module up_dn_cntr_with_load (input clk , input reset, input [3:0] load_data, input load_en , input up_dnb , output reg [3:0] cnt); 3 | 4 | always @ (posedge clk , posedge reset) 5 | begin 6 | if(reset) 7 | cnt <= 4'b0000; 8 | else 9 | begin 10 | if(load_en) 11 | cnt <= load_data; 12 | else 13 | begin 14 | if(up_dnb) 15 | cnt <= cnt + 1; 16 | else 17 | cnt <= cnt - 1; 18 | end 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/up_dn_cntr_with_load_with_start_stop.v: -------------------------------------------------------------------------------- 1 | module up_dn_cntr_with_load_with_start_stop (input clk , input reset, input [3:0] load_data, input load_en , input start_stop_b, input up_dnb , output reg [3:0] cnt); 2 | 3 | always @ (posedge clk , posedge reset) 4 | begin 5 | if(reset) 6 | cnt <= 4'b0000; 7 | else 8 | begin 9 | if(start_stop_b) 10 | begin 11 | if(load_en) 12 | cnt <= load_data; 13 | else 14 | begin 15 | if(up_dnb) 16 | cnt <= cnt + 1; 17 | else 18 | cnt <= cnt - 1; 19 | end 20 | end 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /DC_WORKSHOP/verilog_files/upcntr.v: -------------------------------------------------------------------------------- 1 | module upcntr (input clk , input reset, output reg [3:0] cnt); 2 | always @ (posedge clk , posedge reset) 3 | begin 4 | if(reset) 5 | cnt <= 4'b0000; 6 | else 7 | cnt <= cnt + 1; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | README 2 | 3 | This workshop contains collaterals for RTL Design and Synthesis Workshop using Sky130 PDK's 4 | In case of you any queries, please feel free to drop an email to kunalpghosh@gmail.com and vsd@vlsisystemdesign.com 5 | 6 | -------------------------------------------------------------------------------- /verilog_files/bad_case.v: -------------------------------------------------------------------------------- 1 | module bad_case (input i0 , input i1, input i2, input i3 , input [1:0] sel, output reg y); 2 | always @(*) 3 | begin 4 | case(sel) 5 | 2'b00: y = i0; 6 | 2'b01: y = i1; 7 | 2'b10: y = i2; 8 | 2'b1?: y = i3; 9 | //2'b11: y = i3; 10 | endcase 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilog_files/bad_case_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module bad_case(i0, i1, i2, i3, sel, y); 4 | wire _00_; 5 | wire _01_; 6 | wire _02_; 7 | wire _03_; 8 | wire _04_; 9 | wire _05_; 10 | wire _06_; 11 | wire _07_; 12 | wire _08_; 13 | wire _09_; 14 | wire _10_; 15 | wire _11_; 16 | wire _12_; 17 | wire _13_; 18 | wire _14_; 19 | wire _15_; 20 | wire _16_; 21 | wire _17_; 22 | wire _18_; 23 | wire _19_; 24 | wire _20_; 25 | input i0; 26 | input i1; 27 | input i2; 28 | input i3; 29 | input [1:0] sel; 30 | output y; 31 | sky130_fd_sc_hd__nor2_1 _21_ ( 32 | .A(_09_), 33 | .B(_10_), 34 | .Y(_18_) 35 | ); 36 | sky130_fd_sc_hd__clkinv_1 _22_ ( 37 | .A(_09_), 38 | .Y(_20_) 39 | ); 40 | sky130_fd_sc_hd__o21ai_0 _23_ ( 41 | .A1(_14_), 42 | .A2(_20_), 43 | .B1(_08_), 44 | .Y(_11_) 45 | ); 46 | sky130_fd_sc_hd__clkinv_1 _24_ ( 47 | .A(_08_), 48 | .Y(_12_) 49 | ); 50 | sky130_fd_sc_hd__or2b_2 _25_ ( 51 | .A(_19_), 52 | .B_N(_09_), 53 | .X(_13_) 54 | ); 55 | sky130_fd_sc_hd__o211ai_1 _26_ ( 56 | .A1(_09_), 57 | .A2(_17_), 58 | .B1(_12_), 59 | .C1(_13_), 60 | .Y(_15_) 61 | ); 62 | sky130_fd_sc_hd__o21ai_0 _27_ ( 63 | .A1(_18_), 64 | .A2(_11_), 65 | .B1(_15_), 66 | .Y(_16_) 67 | ); 68 | assign _08_ = sel[0]; 69 | assign _09_ = sel[1]; 70 | assign _17_ = i0; 71 | assign _19_ = i2; 72 | assign _10_ = i1; 73 | assign _14_ = i3; 74 | assign y = _16_; 75 | endmodule 76 | -------------------------------------------------------------------------------- /verilog_files/bad_counter.v: -------------------------------------------------------------------------------- 1 | module bad_counter (input clk , input reset , output reg [1:0] cnt); 2 | wire res_int; 3 | 4 | assign res_int = (cnt == 2'b11) | reset; 5 | 6 | always @(posedge clk , posedge res_int) 7 | begin 8 | if(res_int) 9 | cnt <= 2'b00; 10 | else 11 | cnt <= cnt+1; 12 | end 13 | 14 | 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /verilog_files/bad_latch.v: -------------------------------------------------------------------------------- 1 | 2 | module bad_latch (input clk , input reset , input d , output reg q); 3 | always @ (clk,reset) 4 | begin 5 | if(reset) 6 | q <= 1'b0; 7 | else if(clk) 8 | q <= d; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/bad_latch_2.v: -------------------------------------------------------------------------------- 1 | module bad_latch (input clk , input reset , input d , output reg q); 2 | always @ (clk,reset) 3 | begin 4 | if(reset) 5 | q <= 1'b0; 6 | else 7 | q <= d; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilog_files/bad_latch_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module bad_latch(clk, reset, d, q); 4 | wire _00_; 5 | wire _01_; 6 | wire _02_; 7 | wire _03_; 8 | wire _04_; 9 | wire _05_; 10 | wire _06_; 11 | wire _07_; 12 | wire _08_; 13 | wire _09_; 14 | input clk; 15 | input d; 16 | output q; 17 | input reset; 18 | sky130_fd_sc_hd__and2b_2 _10_ ( 19 | .A_N(_03_), 20 | .B(_04_), 21 | .X(_05_) 22 | ); 23 | sky130_fd_sc_hd__clkinv_1 _11_ ( 24 | .A(_03_), 25 | .Y(_08_) 26 | ); 27 | sky130_fd_sc_hd__clkinv_1 _12_ ( 28 | .A(_06_), 29 | .Y(_09_) 30 | ); 31 | sky130_fd_sc_hd__nand2_1 _13_ ( 32 | .A(_08_), 33 | .B(_09_), 34 | .Y(_07_) 35 | ); 36 | \$_DLATCH_P_ _14_ ( 37 | .D(_00_), 38 | .E(_02_), 39 | .Q(q) 40 | ); 41 | assign _03_ = reset; 42 | assign _04_ = d; 43 | assign _00_ = _05_; 44 | assign _06_ = clk; 45 | assign _02_ = _07_; 46 | endmodule 47 | -------------------------------------------------------------------------------- /verilog_files/bad_mux.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module bad_mux (input i0 , input i1 , input sel , output reg y); 4 | always @ (sel) 5 | begin 6 | if(sel) 7 | y <= i1; 8 | else 9 | y <= i0; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog_files/bad_mux_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module bad_mux(i0, i1, sel, y); 4 | wire _0_; 5 | wire _1_; 6 | wire _2_; 7 | wire _3_; 8 | wire _4_; 9 | wire _5_; 10 | input i0; 11 | input i1; 12 | input sel; 13 | output y; 14 | sky130_fd_sc_hd__clkinv_1 _6_ ( 15 | .A(_0_), 16 | .Y(_4_) 17 | ); 18 | sky130_fd_sc_hd__nand2_1 _7_ ( 19 | .A(_1_), 20 | .B(_2_), 21 | .Y(_5_) 22 | ); 23 | sky130_fd_sc_hd__o21ai_0 _8_ ( 24 | .A1(_2_), 25 | .A2(_4_), 26 | .B1(_5_), 27 | .Y(_3_) 28 | ); 29 | assign _0_ = i0; 30 | assign _1_ = i1; 31 | assign _2_ = sel; 32 | assign y = _3_; 33 | endmodule 34 | -------------------------------------------------------------------------------- /verilog_files/bad_shift_reg.v: -------------------------------------------------------------------------------- 1 | 2 | module bad_shift_reg (input clk , input reset , input d , output reg dout); 3 | reg q1; 4 | always @ (posedge clk , posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q1 = 1'b0; 9 | dout = 1'b0; 10 | end 11 | else 12 | begin 13 | q1 = d; 14 | dout = q1; 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilog_files/bad_shift_reg2.v: -------------------------------------------------------------------------------- 1 | 2 | module bad_shift_reg2 (input clk , input reset , input d , output reg dout); 3 | reg q1; 4 | always @ (posedge clk , posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q1 = 1'b0; 9 | dout = 1'b0; 10 | end 11 | else 12 | begin 13 | dout = q1; 14 | q1 = d; 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilog_files/blocking_caveat.v: -------------------------------------------------------------------------------- 1 | module blocking_caveat (input a , input b , input c, output reg d); 2 | reg x; 3 | always @ (*) 4 | begin 5 | d = x & c; 6 | x = a | b; 7 | end 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilog_files/blocking_caveat_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module blocking_caveat(a, b, c, d); 4 | wire _0_; 5 | wire _1_; 6 | wire _2_; 7 | wire _3_; 8 | wire _4_; 9 | input a; 10 | input b; 11 | input c; 12 | output d; 13 | sky130_fd_sc_hd__o21a_1 _5_ ( 14 | .A1(_1_), 15 | .A2(_2_), 16 | .B1(_3_), 17 | .X(_4_) 18 | ); 19 | assign _1_ = b; 20 | assign _2_ = a; 21 | assign _3_ = c; 22 | assign d = _4_; 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilog_files/comp_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module comp_case (input i0 , input i1 , input i2 , input [1:0] sel, output reg y); 4 | always @ (*) 5 | begin 6 | case(sel) 7 | 2'b00 : y = i0; 8 | 2'b01 : y = i1; 9 | default : y = i2; 10 | endcase 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilog_files/counter_opt.v: -------------------------------------------------------------------------------- 1 | module counter_opt (input clk , input reset , output q); 2 | reg [2:0] count; 3 | assign q = count[0]; 4 | 5 | always @(posedge clk ,posedge reset) 6 | begin 7 | if(reset) 8 | count <= 3'b000; 9 | else 10 | count <= count + 1; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilog_files/counter_opt2.v: -------------------------------------------------------------------------------- 1 | module counter_opt (input clk , input reset , output q); 2 | reg [2:0] count; 3 | assign q = (count[2:0] == 3'b100); 4 | 5 | always @(posedge clk ,posedge reset) 6 | begin 7 | if(reset) 8 | count <= 3'b000; 9 | else 10 | count <= count + 1; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilog_files/demux_case.v: -------------------------------------------------------------------------------- 1 | module demux_case (output o0 , output o1, output o2 , output o3, output o4, output o5, output o6 , output o7 , input [2:0] sel , input i); 2 | reg [7:0]y_int; 3 | assign {o7,o6,o5,o4,o3,o2,o1,o0} = y_int; 4 | integer k; 5 | always @ (*) 6 | begin 7 | y_int = 8'b0; 8 | case(sel) 9 | 3'b000 : y_int[0] = i; 10 | 3'b001 : y_int[1] = i; 11 | 3'b010 : y_int[2] = i; 12 | 3'b011 : y_int[3] = i; 13 | 3'b100 : y_int[4] = i; 14 | 3'b101 : y_int[5] = i; 15 | 3'b110 : y_int[6] = i; 16 | 3'b111 : y_int[7] = i; 17 | endcase 18 | 19 | end 20 | endmodule 21 | 22 | 23 | -------------------------------------------------------------------------------- /verilog_files/demux_generate.v: -------------------------------------------------------------------------------- 1 | 2 | module demux_generate (output o0 , output o1, output o2 , output o3, output o4, output o5, output o6 , output o7 , input [2:0] sel , input i); 3 | reg [7:0]y_int; 4 | assign {o7,o6,o5,o4,o3,o2,o1,o0} = y_int; 5 | integer k; 6 | always @ (*) 7 | begin 8 | y_int = 8'b0; 9 | for(k = 0; k < 8; k++) begin 10 | if(k == sel) 11 | y_int[k] = i; 12 | end 13 | end 14 | endmodule 15 | 16 | 17 | -------------------------------------------------------------------------------- /verilog_files/dff_ares.net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | (* top = 1 *) 4 | (* src = "dff_asyncres.v:2" *) 5 | module dff_asyncres(clk, async_reset, d, q); 6 | wire _0_; 7 | wire _1_; 8 | wire _2_; 9 | (* src = "dff_asyncres.v:2" *) 10 | input async_reset; 11 | (* src = "dff_asyncres.v:2" *) 12 | input clk; 13 | (* src = "dff_asyncres.v:2" *) 14 | input d; 15 | (* src = "dff_asyncres.v:2" *) 16 | output q; 17 | sky130_fd_sc_hd__clkinv_1 _3_ ( 18 | .A(_0_), 19 | .Y(_1_) 20 | ); 21 | sky130_fd_sc_hd__dfrtp_1 _4_ ( 22 | .CLK(clk), 23 | .D(d), 24 | .Q(q), 25 | .RESET_B(_2_) 26 | ); 27 | assign _0_ = async_reset; 28 | assign _2_ = _1_; 29 | endmodule 30 | -------------------------------------------------------------------------------- /verilog_files/dff_async_set.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module dff_async_set ( input clk , input async_set , input d , output reg q ); 4 | always @ (posedge clk , posedge async_set) 5 | begin 6 | if(async_set) 7 | q <= 1'b1; 8 | else 9 | q <= d; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog_files/dff_asyncres.v: -------------------------------------------------------------------------------- 1 | 2 | module dff_asyncres ( input clk , input async_reset , input d , output reg q ); 3 | always @ (posedge clk , posedge async_reset) 4 | begin 5 | if(async_reset) 6 | q <= 1'b0; 7 | else 8 | q <= d; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/dff_asyncres_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module dff_asyncres(clk, async_reset, d, q); 4 | wire _0_; 5 | wire _1_; 6 | wire _2_; 7 | input async_reset; 8 | input clk; 9 | input d; 10 | output q; 11 | sky130_fd_sc_hd__clkinv_1 _3_ ( 12 | .A(_0_), 13 | .Y(_1_) 14 | ); 15 | sky130_fd_sc_hd__dfrtp_1 _4_ ( 16 | .CLK(clk), 17 | .D(d), 18 | .Q(q), 19 | .RESET_B(_2_) 20 | ); 21 | assign _0_ = async_reset; 22 | assign _2_ = _1_; 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilog_files/dff_asyncres_syncres.v: -------------------------------------------------------------------------------- 1 | module dff_asyncres_syncres ( input clk , input async_reset , input sync_reset , input d , output reg q ); 2 | always @ (posedge clk , posedge async_reset) 3 | begin 4 | if(async_reset) 5 | q <= 1'b0; 6 | else if (sync_reset) 7 | q <= 1'b0; 8 | else 9 | q <= d; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog_files/dff_const1.v: -------------------------------------------------------------------------------- 1 | module dff_const1(input clk, input reset, output reg q); 2 | always @(posedge clk, posedge reset) 3 | begin 4 | if(reset) 5 | q <= 1'b0; 6 | else 7 | q <= 1'b1; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/dff_const2.v: -------------------------------------------------------------------------------- 1 | module dff_const2(input clk, input reset, output reg q); 2 | always @(posedge clk, posedge reset) 3 | begin 4 | if(reset) 5 | q <= 1'b1; 6 | else 7 | q <= 1'b1; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/dff_const3.v: -------------------------------------------------------------------------------- 1 | module dff_const3(input clk, input reset, output reg q); 2 | reg q1; 3 | 4 | always @(posedge clk, posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q <= 1'b1; 9 | q1 <= 1'b0; 10 | end 11 | else 12 | begin 13 | q1 <= 1'b1; 14 | q <= q1; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /verilog_files/dff_const4.v: -------------------------------------------------------------------------------- 1 | module dff_const4(input clk, input reset, output reg q); 2 | reg q1; 3 | 4 | always @(posedge clk, posedge reset) 5 | begin 6 | if(reset) 7 | begin 8 | q <= 1'b1; 9 | q1 <= 1'b1; 10 | end 11 | else 12 | begin 13 | q1 <= 1'b1; 14 | q <= q1; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /verilog_files/dff_const5.v: -------------------------------------------------------------------------------- 1 | 2 | module dff_const5(input clk, input reset, output reg q); 3 | reg q1; 4 | 5 | always @(posedge clk, posedge reset) 6 | begin 7 | if(reset) 8 | begin 9 | q <= 1'b0; 10 | q1 <= 1'b0; 11 | end 12 | else 13 | begin 14 | q1 <= 1'b1; 15 | q <= q1; 16 | end 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /verilog_files/dff_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | (* top = 1 *) 4 | (* src = "dff_syncres.v:2" *) 5 | module dff_syncres(clk, async_reset, sync_reset, d, q); 6 | (* src = "dff_syncres.v:3" *) 7 | wire _0_; 8 | wire _1_; 9 | wire _2_; 10 | wire _3_; 11 | wire _4_; 12 | (* src = "dff_syncres.v:2" *) 13 | input async_reset; 14 | (* src = "dff_syncres.v:2" *) 15 | input clk; 16 | (* src = "dff_syncres.v:2" *) 17 | input d; 18 | (* src = "dff_syncres.v:2" *) 19 | output q; 20 | (* src = "dff_syncres.v:2" *) 21 | input sync_reset; 22 | sky130_fd_sc_hd__and2b_2 _5_ ( 23 | .A_N(_4_), 24 | .B(_2_), 25 | .X(_3_) 26 | ); 27 | sky130_fd_sc_hd__dfxtp_1 _6_ ( 28 | .CLK(clk), 29 | .D(_0_), 30 | .Q(q) 31 | ); 32 | assign _2_ = d; 33 | assign _0_ = _3_; 34 | assign _4_ = sync_reset; 35 | endmodule 36 | -------------------------------------------------------------------------------- /verilog_files/dff_syncres.v: -------------------------------------------------------------------------------- 1 | 2 | module dff_syncres ( input clk , input async_reset , input sync_reset , input d , output reg q ); 3 | always @ (posedge clk ) 4 | begin 5 | if (sync_reset) 6 | q <= 1'b0; 7 | else 8 | q <= d; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/fa.v: -------------------------------------------------------------------------------- 1 | module fa (input a , input b , input c, output co , output sum); 2 | assign {co,sum} = a + b + c ; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilog_files/good_counter.v: -------------------------------------------------------------------------------- 1 | module good_counter (input clk , input reset , output reg [1:0] cnt); 2 | wire comp; 3 | 4 | assign comp = (cnt == 2'b10); 5 | 6 | always @(posedge clk , posedge reset) 7 | begin 8 | if(reset) 9 | cnt <= 2'b00; 10 | else if(comp) 11 | cnt <= 2'b00; 12 | else 13 | cnt <= cnt+1; 14 | end 15 | 16 | 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /verilog_files/good_latch.v: -------------------------------------------------------------------------------- 1 | module good_latch (input clk , input reset , input d , output reg q); 2 | always @ (clk,reset,d) 3 | begin 4 | if(reset) 5 | q <= 1'b0; 6 | else if(clk) 7 | q <= d; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilog_files/good_mux.v: -------------------------------------------------------------------------------- 1 | 2 | module good_mux (input i0 , input i1 , input sel , output reg y); 3 | always @ (*) 4 | begin 5 | if(sel) 6 | y <= i1; 7 | else 8 | y <= i0; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/good_mux_netlist.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module good_mux(i0, i1, sel, y); 4 | wire _0_; 5 | wire _1_; 6 | wire _2_; 7 | wire _3_; 8 | wire _4_; 9 | wire _5_; 10 | input i0; 11 | input i1; 12 | input sel; 13 | output y; 14 | sky130_fd_sc_hd__clkinv_1 _6_ ( 15 | .A(_0_), 16 | .Y(_4_) 17 | ); 18 | sky130_fd_sc_hd__nand2_1 _7_ ( 19 | .A(_1_), 20 | .B(_2_), 21 | .Y(_5_) 22 | ); 23 | sky130_fd_sc_hd__o21ai_0 _8_ ( 24 | .A1(_2_), 25 | .A2(_4_), 26 | .B1(_5_), 27 | .Y(_3_) 28 | ); 29 | assign _0_ = i0; 30 | assign _1_ = i1; 31 | assign _2_ = sel; 32 | assign y = _3_; 33 | endmodule 34 | -------------------------------------------------------------------------------- /verilog_files/good_shift_reg.v: -------------------------------------------------------------------------------- 1 | module good_shift_reg (input clk , input reset , input d , output reg dout); 2 | reg q1; 3 | always @ (posedge clk , posedge reset) 4 | begin 5 | if(reset) 6 | begin 7 | q1 <= 1'b0; 8 | dout <= 1'b0; 9 | end 10 | else 11 | begin 12 | dout <= q1; 13 | q1 <= d; 14 | end 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /verilog_files/incomp_case.v: -------------------------------------------------------------------------------- 1 | 2 | module incomp_case (input i0 , input i1 , input i2 , input [1:0] sel, output reg y); 3 | always @ (*) 4 | begin 5 | case(sel) 6 | 2'b00 : y = i0; 7 | 2'b01 : y = i1; 8 | endcase 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog_files/incomp_if.v: -------------------------------------------------------------------------------- 1 | module incomp_if (input i0 , input i1 , input i2 , output reg y); 2 | always @ (*) 3 | begin 4 | if(i0) 5 | y <= i1; 6 | end 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilog_files/incomp_if2.v: -------------------------------------------------------------------------------- 1 | 2 | module incomp_if2 (input i0 , input i1 , input i2 , input i3, output reg y); 3 | always @ (*) 4 | begin 5 | if(i0) 6 | y <= i1; 7 | else if (i2) 8 | y <= i3; 9 | 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog_files/mul2_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module mul2(a, y); 4 | input [2:0] a; 5 | output [3:0] y; 6 | assign y = { a, 1'b0 }; 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilog_files/mult_2.v: -------------------------------------------------------------------------------- 1 | module mul2 (input [2:0] a, output [3:0] y); 2 | assign y = a * 2; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilog_files/mult_8.v: -------------------------------------------------------------------------------- 1 | module mult8 (input [2:0] a , output [5:0] y); 2 | assign y = a * 9; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /verilog_files/multiple_module_opt.v: -------------------------------------------------------------------------------- 1 | module sub_module1(input a , input b , output y); 2 | assign y = a & b; 3 | endmodule 4 | 5 | 6 | module sub_module2(input a , input b , output y); 7 | assign y = a^b; 8 | endmodule 9 | 10 | 11 | module multiple_module_opt(input a , input b , input c , input d , output y); 12 | wire n1,n2,n3; 13 | 14 | sub_module1 U1 (.a(a) , .b(1'b1) , .y(n1)); 15 | sub_module2 U2 (.a(n1), .b(1'b0) , .y(n2)); 16 | sub_module2 U3 (.a(b), .b(d) , .y(n3)); 17 | 18 | assign y = c | (b & n1); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilog_files/multiple_module_opt2.v: -------------------------------------------------------------------------------- 1 | 2 | module sub_module(input a , input b , output y); 3 | assign y = a & b; 4 | endmodule 5 | 6 | 7 | 8 | module multiple_module_opt2(input a , input b , input c , input d , output y); 9 | wire n1,n2,n3; 10 | 11 | sub_module U1 (.a(a) , .b(1'b0) , .y(n1)); 12 | sub_module U2 (.a(b), .b(c) , .y(n2)); 13 | sub_module U3 (.a(n2), .b(d) , .y(n3)); 14 | sub_module U4 (.a(n3), .b(n1) , .y(y)); 15 | 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilog_files/multiple_modules.v: -------------------------------------------------------------------------------- 1 | module sub_module2 (input a, input b, output y); 2 | assign y = a | b; 3 | endmodule 4 | 5 | module sub_module1 (input a, input b, output y); 6 | assign y = a&b; 7 | endmodule 8 | 9 | 10 | module multiple_modules (input a, input b, input c , output y); 11 | wire net1; 12 | sub_module1 u1(.a(a),.b(b),.y(net1)); //net1 = a&b 13 | sub_module2 u2(.a(net1),.b(c),.y(y)); //y = net1|c ,ie y = a&b + c; 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilog_files/multiple_modules_flat.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module multiple_modules(a, b, c, y); 4 | wire _00_; 5 | wire _01_; 6 | wire _02_; 7 | wire _03_; 8 | wire _04_; 9 | wire _05_; 10 | wire _06_; 11 | wire _07_; 12 | input a; 13 | input b; 14 | input c; 15 | wire net1; 16 | wire \u1.a ; 17 | wire \u1.b ; 18 | wire \u1.y ; 19 | wire \u2.a ; 20 | wire \u2.b ; 21 | wire \u2.y ; 22 | output y; 23 | sky130_fd_sc_hd__and2_2 _08_ ( 24 | .A(_00_), 25 | .B(_01_), 26 | .X(_02_) 27 | ); 28 | sky130_fd_sc_hd__clkinv_1 _09_ ( 29 | .A(_03_), 30 | .Y(_06_) 31 | ); 32 | sky130_fd_sc_hd__clkinv_1 _10_ ( 33 | .A(_04_), 34 | .Y(_07_) 35 | ); 36 | sky130_fd_sc_hd__nand2_1 _11_ ( 37 | .A(_06_), 38 | .B(_07_), 39 | .Y(_05_) 40 | ); 41 | assign \u1.a = a; 42 | assign \u1.b = b; 43 | assign net1 = \u1.y ; 44 | assign _00_ = \u1.b ; 45 | assign _01_ = \u1.a ; 46 | assign \u1.y = _02_; 47 | assign \u2.a = net1; 48 | assign \u2.b = c; 49 | assign y = \u2.y ; 50 | assign _03_ = \u2.b ; 51 | assign _04_ = \u2.a ; 52 | assign \u2.y = _05_; 53 | endmodule 54 | -------------------------------------------------------------------------------- /verilog_files/multiple_modules_hier.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module multiple_modules(a, b, c, y); 4 | input a; 5 | input b; 6 | input c; 7 | wire net1; 8 | output y; 9 | sub_module1 u1 ( 10 | .a(a), 11 | .b(b), 12 | .y(net1) 13 | ); 14 | sub_module2 u2 ( 15 | .a(net1), 16 | .b(c), 17 | .y(y) 18 | ); 19 | endmodule 20 | 21 | module sub_module1(a, b, y); 22 | wire _0_; 23 | wire _1_; 24 | wire _2_; 25 | input a; 26 | input b; 27 | output y; 28 | sky130_fd_sc_hd__and2_2 _3_ ( 29 | .A(_0_), 30 | .B(_1_), 31 | .X(_2_) 32 | ); 33 | assign _0_ = b; 34 | assign _1_ = a; 35 | assign y = _2_; 36 | endmodule 37 | 38 | module sub_module2(a, b, y); 39 | wire _0_; 40 | wire _1_; 41 | wire _2_; 42 | wire _3_; 43 | wire _4_; 44 | input a; 45 | input b; 46 | output y; 47 | sky130_fd_sc_hd__clkinv_1 _5_ ( 48 | .A(_0_), 49 | .Y(_3_) 50 | ); 51 | sky130_fd_sc_hd__clkinv_1 _6_ ( 52 | .A(_1_), 53 | .Y(_4_) 54 | ); 55 | sky130_fd_sc_hd__nand2_1 _7_ ( 56 | .A(_3_), 57 | .B(_4_), 58 | .Y(_2_) 59 | ); 60 | assign _0_ = b; 61 | assign _1_ = a; 62 | assign y = _2_; 63 | endmodule 64 | -------------------------------------------------------------------------------- /verilog_files/mux_generate.v: -------------------------------------------------------------------------------- 1 | module mux_generate (input i0 , input i1, input i2 , input i3 , input [1:0] sel , output reg y); 2 | wire [3:0] i_int; 3 | assign i_int = {i3,i2,i1,i0}; 4 | integer k; 5 | always @ (*) 6 | begin 7 | for(k = 0; k < 4; k=k+1) begin 8 | if(k == sel) 9 | y = i_int[k]; 10 | end 11 | end 12 | endmodule 13 | 14 | 15 | -------------------------------------------------------------------------------- /verilog_files/mux_spice.v: -------------------------------------------------------------------------------- 1 | * SPICE netlist generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) 2 | 3 | X0 i0 1 sky130_fd_sc_hd__clkinv_1 4 | X1 i1 sel 2 sky130_fd_sc_hd__nand2_1 5 | X2 3 sel 1 2 sky130_fd_sc_hd__o21ai_0 6 | V0 4 i0 DC 0 7 | V1 5 i1 DC 0 8 | V2 6 sel DC 0 9 | V3 y 3 DC 0 10 | 11 | ************************ 12 | * end of SPICE netlist * 13 | ************************ 14 | 15 | -------------------------------------------------------------------------------- /verilog_files/net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | (* top = 1 *) 4 | (* src = "multiple_modules.v:10" *) 5 | module multiple_modules(a, b, c, y); 6 | (* src = "multiple_modules.v:10" *) 7 | input a; 8 | (* src = "multiple_modules.v:10" *) 9 | input b; 10 | (* src = "multiple_modules.v:10" *) 11 | input c; 12 | (* src = "multiple_modules.v:11" *) 13 | wire net1; 14 | (* src = "multiple_modules.v:10" *) 15 | output y; 16 | (* src = "multiple_modules.v:12" *) 17 | sub_module1 u1 ( 18 | .a(a), 19 | .b(b), 20 | .y(net1) 21 | ); 22 | (* src = "multiple_modules.v:13" *) 23 | sub_module2 u2 ( 24 | .a(net1), 25 | .b(c), 26 | .y(y) 27 | ); 28 | endmodule 29 | 30 | (* src = "multiple_modules.v:5" *) 31 | module sub_module1(a, b, y); 32 | wire _0_; 33 | wire _1_; 34 | wire _2_; 35 | (* src = "multiple_modules.v:5" *) 36 | input a; 37 | (* src = "multiple_modules.v:5" *) 38 | input b; 39 | (* src = "multiple_modules.v:5" *) 40 | output y; 41 | sky130_fd_sc_hd__and2_2 _3_ ( 42 | .A(_0_), 43 | .B(_1_), 44 | .X(_2_) 45 | ); 46 | assign _0_ = b; 47 | assign _1_ = a; 48 | assign y = _2_; 49 | endmodule 50 | 51 | (* src = "multiple_modules.v:1" *) 52 | module sub_module2(a, b, y); 53 | wire _0_; 54 | wire _1_; 55 | wire _2_; 56 | wire _3_; 57 | wire _4_; 58 | (* src = "multiple_modules.v:1" *) 59 | input a; 60 | (* src = "multiple_modules.v:1" *) 61 | input b; 62 | (* src = "multiple_modules.v:1" *) 63 | output y; 64 | sky130_fd_sc_hd__clkinv_1 _5_ ( 65 | .A(_0_), 66 | .Y(_3_) 67 | ); 68 | sky130_fd_sc_hd__clkinv_1 _6_ ( 69 | .A(_1_), 70 | .Y(_4_) 71 | ); 72 | sky130_fd_sc_hd__nand2_1 _7_ ( 73 | .A(_3_), 74 | .B(_4_), 75 | .Y(_2_) 76 | ); 77 | assign _0_ = b; 78 | assign _1_ = a; 79 | assign y = _2_; 80 | endmodule 81 | -------------------------------------------------------------------------------- /verilog_files/opt_check.v: -------------------------------------------------------------------------------- 1 | module opt_check (input a , input b , output y); 2 | assign y = a?b:0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilog_files/opt_check2.v: -------------------------------------------------------------------------------- 1 | module opt_check2 (input a , input b , output y); 2 | assign y = a?1:b; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /verilog_files/opt_check3.v: -------------------------------------------------------------------------------- 1 | 2 | module opt_check3 (input a , input b, input c , output y); 3 | assign y = a?(c?b:0):0; 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilog_files/opt_check4.v: -------------------------------------------------------------------------------- 1 | module opt_check4 (input a , input b , input c , output y); 2 | assign y = a?(b?(a & c ):c):(!c); 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilog_files/partial_case_assign.v: -------------------------------------------------------------------------------- 1 | module partial_case_assign (input i0 , input i1 , input i2 , input [1:0] sel, output reg y , output reg x); 2 | always @ (*) 3 | begin 4 | case(sel) 5 | 2'b00 : begin 6 | y = i0; 7 | x = i2; 8 | end 9 | 2'b01 : y = i1; 10 | default : begin 11 | x = i1; 12 | y = i2; 13 | end 14 | endcase 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /verilog_files/pattern_detect_fsm.v: -------------------------------------------------------------------------------- 1 | module pattern_detect_fsm (input clk , input reset, input din , output reg pattern_detect); 2 | reg [1:0] present_state , next_state; 3 | always @ (posedge clk, posedge reset) 4 | begin 5 | if(reset) 6 | begin 7 | preset_state <= 2'b00; 8 | else 9 | present_state <= next_state; 10 | end 11 | 12 | 13 | always & (*) 14 | begin 15 | next_state = present_state; 16 | pattern_detect = 1'b0; 17 | case(present_state): 18 | 19 | 2'b00 : begin 20 | if(din) 21 | next_state = 2'b01; 22 | end 23 | 24 | 2'b01 : begin 25 | if(!din) 26 | next_state = 2'b10; 27 | end 28 | 29 | 2'b10 : begin 30 | if(din) 31 | next_state = 2'b11; 32 | else 33 | next_state = 2'b00; 34 | end 35 | 36 | 2'b11 : begin 37 | next_state = 2'b00; 38 | pattern_detect = 1'b1; 39 | 40 | end 41 | 42 | default : begin 43 | next_state = present_state; 44 | pattern_detect = 1'b0; 45 | end 46 | endcase 47 | 48 | 49 | end 50 | 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /verilog_files/pattern_detect_fsm_bad_style.v: -------------------------------------------------------------------------------- 1 | module pattern_detect_fsm_bad_style (input clk , input reset, input din , output reg pattern_detect); 2 | reg [1:0] present_state , next_state; 3 | always @ (posedge clk, posedge reset) 4 | begin 5 | if(reset) 6 | begin 7 | preset_state <= 2'b00; 8 | else 9 | present_state <= next_state; 10 | end 11 | 12 | 13 | always & (*) 14 | begin 15 | case(present_state): 16 | 17 | 2'b00 : begin 18 | if(din) 19 | begin 20 | next_state = 2'b01; 21 | pattern_detect = 1'b0; 22 | end 23 | else 24 | begin 25 | next_state = 2'b00; 26 | pattern_detect = 1'b0; 27 | end 28 | end 29 | 30 | 2'b01 : begin 31 | if(!din) 32 | begin 33 | next_state = 2'b10; 34 | pattern_detect = 1'b0; 35 | end 36 | else 37 | begin 38 | next_state = 2'b01; 39 | pattern_detect = 1'b0; 40 | end 41 | 42 | 43 | end 44 | 45 | 2'b10 : begin 46 | if(din) 47 | begin 48 | next_state = 2'b11; 49 | pattern_detect = 1'b0; 50 | end 51 | else 52 | begin 53 | next_state = 2'b00; 54 | pattern_detect = 1'b0; 55 | end 56 | end 57 | 58 | 2'b11 : begin 59 | next_state = 2'b00; 60 | pattern_detect = 1'b1; 61 | 62 | end 63 | 64 | default : begin 65 | next_state = present_state; 66 | pattern_detect = 1'b0; 67 | end 68 | endcase 69 | 70 | 71 | end 72 | 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /verilog_files/rca.v: -------------------------------------------------------------------------------- 1 | module rca (input [7:0] num1 , input [7:0] num2 , output [8:0] sum); 2 | wire [7:0] int_sum; 3 | wire [7:0]int_co; 4 | 5 | genvar i; 6 | generate 7 | for (i = 1 ; i < 8; i=i+1) begin 8 | fa u_fa_1 (.a(num1[i]),.b(num2[i]),.c(int_co[i-1]),.co(int_co[i]),.sum(int_sum[i])); 9 | end 10 | 11 | endgenerate 12 | fa u_fa_0 (.a(num1[0]),.b(num2[0]),.c(1'b0),.co(int_co[0]),.sum(int_sum[0])); 13 | 14 | 15 | assign sum[7:0] = int_sum; 16 | assign sum[8] = int_co[7]; 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /verilog_files/ripple_counter.v: -------------------------------------------------------------------------------- 1 | module ripple_counter (input clk , input reset , output [1:0] q); 2 | reg [1:0]q_int; 3 | 4 | always @ (posedge clk, posedge reset) 5 | begin 6 | if(reset) 7 | q_int[0] <= 1'b0; 8 | else 9 | q_int[0] <= ~q_int[0]; 10 | end 11 | 12 | 13 | always @ (posedge q_int[0], posedge reset) 14 | begin 15 | 16 | if(reset) 17 | q_int[1] <= 1'b0; 18 | else 19 | q_int[1] <= ~q_int[1]; 20 | 21 | end 22 | 23 | assign q = q_int; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_case; 5 | // TB_SIGNALS 6 | reg clk, reset ; 7 | //input 8 | reg i0,i1,i2,i3; 9 | reg [1:0] sel; 10 | // Output 11 | wire y; 12 | 13 | // Instantiate the Unit Under Test (UUT) 14 | bad_case uut ( 15 | .i0(i0), 16 | .i1(i1), 17 | .i2(i2), 18 | .i3(i3), 19 | .sel(sel), 20 | .y(y) 21 | ); 22 | 23 | initial begin 24 | $dumpfile("tb_bad_case.vcd"); 25 | $dumpvars(0,tb_bad_case); 26 | // Initialize Inputs 27 | clk = 0; 28 | i0 = 1'b0; 29 | i1 = 1'b0; 30 | i2 = 1'b0; 31 | i3 = 1'b0 ; 32 | reset = 1'b0; #1; 33 | reset = 1'b1; #10; 34 | reset = 1'b0; 35 | 36 | #3000 $finish; 37 | end 38 | 39 | always #200 clk = ~clk; 40 | always #17 i0 = ~i0; 41 | always #37 i1 = ~i1; 42 | always #57 i2 = ~i2; 43 | always #97 i3 = ~i3; 44 | 45 | always @ (posedge clk , posedge reset) 46 | begin 47 | if(reset) 48 | sel <= 2'b00; 49 | else 50 | sel <= sel + 1; 51 | end 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_counter.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_bad_counter; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire [1:0] cnt; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | bad_counter uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .cnt(cnt) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_bad_counter.vcd"); 18 | $dumpvars(0,tb_bad_counter); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_latch.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_latch; 5 | // Inputs 6 | reg clk, reset, d; 7 | // Outputs 8 | wire q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | bad_latch uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .d(d), 15 | .q(q) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_bad_latch.vcd"); 20 | $dumpvars(0,tb_bad_latch); 21 | // Initialize Inputs 22 | clk = 0; 23 | reset = 1; 24 | d = 0; 25 | #300 $finish; 26 | end 27 | 28 | always #20 clk = ~clk; 29 | always #23 d = ~d; 30 | always #15 reset=0; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_latch2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_bad_latch; 3 | // Inputs 4 | reg clk, reset, d; 5 | // Outputs 6 | wire q; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | bad_latch uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .d(d), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_bad_latch.vcd"); 18 | $dumpvars(0,tb_bad_latch); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | d = 0; 23 | #300 $finish; 24 | end 25 | 26 | always #20 clk = ~clk; 27 | always #23 d = ~d; 28 | always #15 reset=0; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_mux.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_mux; 5 | // Inputs 6 | reg i0,i1,sel; 7 | // Outputs 8 | wire y; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | bad_mux uut ( 12 | .sel(sel), 13 | .i0(i0), 14 | .i1(i1), 15 | .y(y) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_bad_mux.vcd"); 20 | $dumpvars(0,tb_bad_mux); 21 | // Initialize Inputs 22 | sel = 1'b0; 23 | i0 = 1'b0; 24 | i1 = 1'b0; 25 | #300 $finish; 26 | end 27 | 28 | always #75 sel = ~sel; 29 | always #10 i0 = ~i0; 30 | always #55 i1 = ~i1; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_shift_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_bad_shift_reg; 3 | // Inputs 4 | reg clk, reset, d; 5 | // Outputs 6 | wire dout; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | bad_shift_reg uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .d(d), 13 | .dout(dout) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_bad_shift_reg.vcd"); 18 | $dumpvars(0,tb_bad_shift_reg); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | d = 0; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #173 d = ~d; 28 | always #123 reset=0; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /verilog_files/tb_bad_shift_reg2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_bad_shift_reg2; 5 | // Inputs 6 | reg clk, reset, d; 7 | // Outputs 8 | wire dout; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | bad_shift_reg2 uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .d(d), 15 | .dout(dout) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_bad_shift_reg2.vcd"); 20 | $dumpvars(0,tb_bad_shift_reg2); 21 | // Initialize Inputs 22 | clk = 0; 23 | reset = 1; 24 | d = 0; 25 | #3000 $finish; 26 | end 27 | 28 | always #20 clk = ~clk; 29 | always #223 d = ~d; 30 | always #113 reset = 0; 31 | endmodule 32 | -------------------------------------------------------------------------------- /verilog_files/tb_blocking_caveat.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_blocking_caveat; 4 | // Inputs 5 | reg a,b,c ; 6 | // Output 7 | wire d; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | blocking_caveat uut ( 11 | .a(a), 12 | .b(b), 13 | .c(c), 14 | .d(d) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_blocking_caveat.vcd"); 19 | $dumpvars(0,tb_blocking_caveat); 20 | // Initialize Inputs 21 | a = 0; 22 | b = 0; 23 | c = 0; 24 | #3000 $finish; 25 | end 26 | 27 | always #10 a = ~a; 28 | always #100 c =~c; 29 | always #50 b = ~b; 30 | endmodule 31 | 32 | 33 | -------------------------------------------------------------------------------- /verilog_files/tb_comp_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | `timescale 1ns / 1ps 7 | module tb_comp_case; 8 | //input 9 | reg i0,i1,i2; 10 | reg [1:0] sel; 11 | // Output 12 | wire y; 13 | //TB_SIGNALS 14 | reg clk,reset; 15 | 16 | // Instantiate the Unit Under Test (UUT) 17 | comp_case uut ( 18 | .sel(sel), 19 | .i0(i0), 20 | .i1(i1), 21 | .i2(i2), 22 | .y(y) 23 | ); 24 | 25 | initial begin 26 | $dumpfile("tb_comp_case.vcd"); 27 | $dumpvars(0,tb_comp_case); 28 | // Initialize Inputs 29 | i0 = 1'b0; 30 | i1 = 1'b0; 31 | i2 = 1'b0; 32 | clk = 1'b0; 33 | reset = 1'b0; #1; 34 | reset = 1'b1; #10; 35 | reset = 1'b0; 36 | 37 | 38 | #5000 $finish; 39 | end 40 | 41 | always #317 i0 = ~i0; 42 | always #600 clk = ~clk; 43 | always #37 i1 = ~i1; 44 | always #57 i2 = ~i2; 45 | 46 | 47 | always @(posedge clk , posedge reset) 48 | begin 49 | if(reset) 50 | sel <= 2'b00; 51 | else 52 | sel <= sel + 1; 53 | end 54 | endmodule 55 | 56 | 57 | -------------------------------------------------------------------------------- /verilog_files/tb_counter_opt.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_counter_opt; 5 | // Inputs 6 | reg clk, reset ; 7 | // Output 8 | wire q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | counter_opt uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_counter_opt.vcd"); 19 | $dumpvars(0,tb_counter_opt); 20 | // Initialize Inputs 21 | clk = 0; 22 | reset = 1; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #1547 reset=~reset; 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /verilog_files/tb_demux_case.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_demux_case; 4 | // Inputs 5 | reg i; 6 | reg [2:0] sel; 7 | 8 | //TB Signals 9 | reg clk,reset; 10 | 11 | // Outputs 12 | wire o7,o6,o5,o4,o3,o2,o1,o0; 13 | 14 | // Instantiate the Unit Under Test (UUT) 15 | demux_case uut ( 16 | .sel(sel), 17 | .o0(o0), 18 | .o1(o1), 19 | .o2(o2), 20 | .o3(o3), 21 | .o4(o4), 22 | .o5(o5), 23 | .o6(o6), 24 | .o7(o7), 25 | .i(i) 26 | ); 27 | 28 | initial begin 29 | $dumpfile("tb_demux_case.vcd"); 30 | $dumpvars(0,tb_demux_case); 31 | // Initialize Inputs 32 | i = 1'b0; 33 | clk = 1'b0; 34 | reset = 1'b0 ; #1; 35 | reset = 1'b1 ; #10; 36 | reset = 1'b0; 37 | 38 | #3900 $finish; 39 | end 40 | 41 | always #17 i = ~i; 42 | always #300 clk = ~clk; 43 | 44 | always @ (posedge clk , posedge reset) 45 | begin 46 | if(reset) 47 | sel <= 3'b000; 48 | else 49 | sel <= sel + 1; 50 | end 51 | 52 | 53 | 54 | endmodule 55 | 56 | 57 | -------------------------------------------------------------------------------- /verilog_files/tb_demux_generate.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_demux_generate; 5 | // Inputs 6 | reg i; 7 | reg [2:0] sel; 8 | 9 | //TB Signals 10 | reg clk,reset; 11 | 12 | // Outputs 13 | wire o7,o6,o5,o4,o3,o2,o1,o0; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | demux_generate uut ( 17 | .sel(sel), 18 | .o0(o0), 19 | .o1(o1), 20 | .o2(o2), 21 | .o3(o3), 22 | .o4(o4), 23 | .o5(o5), 24 | .o6(o6), 25 | .o7(o7), 26 | .i(i) 27 | ); 28 | 29 | initial begin 30 | $dumpfile("tb_demux_generate.vcd"); 31 | $dumpvars(0,tb_demux_generate); 32 | // Initialize Inputs 33 | i = 1'b0; 34 | clk = 1'b0; 35 | reset = 1'b0 ; #1; 36 | reset = 1'b1 ; #10; 37 | reset = 1'b0; 38 | 39 | #3900 $finish; 40 | end 41 | 42 | always #17 i = ~i; 43 | always #300 clk = ~clk; 44 | 45 | always @ (posedge clk , posedge reset) 46 | begin 47 | if(reset) 48 | sel <= 3'b000; 49 | else 50 | sel <= sel + 1; 51 | end 52 | 53 | 54 | 55 | endmodule 56 | 57 | 58 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_async_set.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_dff_async_set; 5 | // Inputs 6 | reg clk, async_set, d; 7 | // Outputs 8 | wire q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | dff_async_set uut ( 12 | .clk(clk), 13 | .async_set(async_set), 14 | .d(d), 15 | .q(q) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_dff_async_set.vcd"); 20 | $dumpvars(0,tb_dff_async_set); 21 | // Initialize Inputs 22 | clk = 0; 23 | async_set = 1; 24 | d = 0; 25 | #3000 $finish; 26 | end 27 | 28 | always #10 clk = ~clk; 29 | always #23 d = ~d; 30 | always #547 async_set=~async_set; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_asyncres.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_asyncres; 4 | // Inputs 5 | reg clk, async_reset, d; 6 | // Outputs 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_asyncres uut ( 11 | .clk(clk), 12 | .async_reset(async_reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_dff_asyncres.vcd"); 19 | $dumpvars(0,tb_dff_asyncres); 20 | // Initialize Inputs 21 | clk = 0; 22 | async_reset = 1; 23 | d = 0; 24 | #3000 $finish; 25 | end 26 | 27 | always #10 clk = ~clk; 28 | always #23 d = ~d; 29 | always #547 async_reset=~async_reset; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_asyncres_syncres.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_dff_asyncres_syncres; 3 | // Inputs 4 | reg clk, async_reset, sync_reset, d; 5 | // Outputs 6 | wire q; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | dff_asyncres_syncres uut ( 10 | .clk(clk), 11 | .async_reset(async_reset), 12 | .sync_reset(sync_reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_dff_asyncres_syncres.vcd"); 19 | $dumpvars(0,tb_dff_asyncres_syncres); 20 | // Initialize Inputs 21 | clk = 0; 22 | async_reset = 1; 23 | sync_reset = 0; 24 | d = 0; 25 | #3000 $finish; 26 | end 27 | 28 | always #10 clk = ~clk; 29 | always #23 d = ~d; 30 | always #113 sync_reset = ~sync_reset; 31 | always #547 async_reset=~async_reset; 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_const1.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const1; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const1 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const1.vcd"); 18 | $dumpvars(0,tb_dff_const1); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_const2.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const2; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const2 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const2.vcd"); 18 | $dumpvars(0,tb_dff_const2); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_const3.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const3; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const3 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const3.vcd"); 18 | $dumpvars(0,tb_dff_const3); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_const4.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const4; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const4 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const4.vcd"); 18 | $dumpvars(0,tb_dff_const4); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_const5.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_const5; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_const5 uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .q(q) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_dff_const5.vcd"); 18 | $dumpvars(0,tb_dff_const5); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /verilog_files/tb_dff_syncres.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_dff_syncres; 4 | // Inputs 5 | reg clk, sync_reset, d; 6 | // Outputs 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | dff_syncres uut ( 11 | .clk(clk), 12 | .sync_reset(sync_reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_dff_syncres.vcd"); 19 | $dumpvars(0,tb_dff_syncres); 20 | // Initialize Inputs 21 | clk = 0; 22 | sync_reset = 0; 23 | d = 0; 24 | #3000 $finish; 25 | end 26 | 27 | always #10 clk = ~clk; 28 | always #23 d = ~d; 29 | always #113 sync_reset = ~sync_reset; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /verilog_files/tb_good_counter.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_good_counter; 4 | // Inputs 5 | reg clk, reset ; 6 | // Output 7 | wire [1:0] cnt; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | good_counter uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .cnt(cnt) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_good_counter.vcd"); 18 | $dumpvars(0,tb_good_counter); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #1547 reset=~reset; 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /verilog_files/tb_good_latch.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_good_latch; 4 | // Inputs 5 | reg clk, reset, d; 6 | // Outputs 7 | wire q; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | good_latch uut ( 11 | .clk(clk), 12 | .reset(reset), 13 | .d(d), 14 | .q(q) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_good_latch.vcd"); 19 | $dumpvars(0,tb_good_latch); 20 | // Initialize Inputs 21 | clk = 0; 22 | reset = 1; 23 | d = 0; 24 | #300 $finish; 25 | end 26 | 27 | always #20 clk = ~clk; 28 | always #23 d = ~d; 29 | always #15 reset=0; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /verilog_files/tb_good_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_good_mux; 3 | // Inputs 4 | reg i0,i1,sel; 5 | // Outputs 6 | wire y; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | good_mux uut ( 10 | .sel(sel), 11 | .i0(i0), 12 | .i1(i1), 13 | .y(y) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_good_mux.vcd"); 18 | $dumpvars(0,tb_good_mux); 19 | // Initialize Inputs 20 | sel = 0; 21 | i0 = 0; 22 | i1 = 0; 23 | #300 $finish; 24 | end 25 | 26 | always #75 sel = ~sel; 27 | always #10 i0 = ~i0; 28 | always #55 i1 = ~i1; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /verilog_files/tb_good_shift_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_good_shift_reg; 3 | // Inputs 4 | reg clk, reset, d; 5 | // Outputs 6 | wire dout; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | good_shift_reg uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .d(d), 13 | .dout(dout) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_good_shift_reg.vcd"); 18 | $dumpvars(0,tb_good_shift_reg); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | d = 0; 23 | #3000 $finish; 24 | end 25 | 26 | always #20 clk = ~clk; 27 | always #223 d = ~d; 28 | always #147 reset = 0; 29 | endmodule 30 | 31 | 32 | -------------------------------------------------------------------------------- /verilog_files/tb_incomp_case.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | `timescale 1ns / 1ps 6 | module tb_incomp_case; 7 | //input 8 | reg i0,i1,i2; 9 | reg [1:0] sel; 10 | // Output 11 | wire y; 12 | //TB_SIGNALS 13 | reg clk,reset; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | incomp_case uut ( 17 | .sel(sel), 18 | .i0(i0), 19 | .i1(i1), 20 | .i2(i2), 21 | .y(y) 22 | ); 23 | 24 | initial begin 25 | $dumpfile("tb_incomp_case.vcd"); 26 | $dumpvars(0,tb_incomp_case); 27 | // Initialize Inputs 28 | i0 = 1'b0; 29 | i1 = 1'b0; 30 | i2 = 1'b0; 31 | clk = 1'b0; 32 | reset = 1'b0; #1; 33 | reset = 1'b1; #10; 34 | reset = 1'b0; 35 | 36 | 37 | #5000 $finish; 38 | end 39 | 40 | always #317 i0 = ~i0; 41 | always #600 clk = ~clk; 42 | always #37 i1 = ~i1; 43 | always #57 i2 = ~i2; 44 | 45 | 46 | always @(posedge clk , posedge reset) 47 | begin 48 | if(reset) 49 | sel <= 2'b00; 50 | else 51 | sel <= sel + 1; 52 | end 53 | endmodule 54 | 55 | 56 | -------------------------------------------------------------------------------- /verilog_files/tb_incomp_if.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 1ps 5 | module tb_incomp_if; 6 | //input 7 | reg i0,i1,i2; 8 | // Output 9 | wire y; 10 | 11 | // Instantiate the Unit Under Test (UUT) 12 | incomp_if uut ( 13 | .i0(i0), 14 | .i1(i1), 15 | .i2(i2), 16 | .y(y) 17 | ); 18 | 19 | initial begin 20 | $dumpfile("tb_incomp_if.vcd"); 21 | $dumpvars(0,tb_incomp_if); 22 | // Initialize Inputs 23 | i0 = 1'b0; 24 | i1 = 1'b0; 25 | i2 = 1'b0; 26 | 27 | #3000 $finish; 28 | end 29 | 30 | always #317 i0 = ~i0; 31 | always #37 i1 = ~i1; 32 | always #57 i2 = ~i2; 33 | 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /verilog_files/tb_incomp_if2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 1ps 5 | module tb_incomp_if2; 6 | //input 7 | reg i0,i1,i2,i3; 8 | // Output 9 | wire y; 10 | 11 | // Instantiate the Unit Under Test (UUT) 12 | incomp_if2 uut ( 13 | .i0(i0), 14 | .i1(i1), 15 | .i2(i2), 16 | .i3(i3), 17 | .y(y) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("tb_incomp_if2.vcd"); 22 | $dumpvars(0,tb_incomp_if2); 23 | // Initialize Inputs 24 | i0 = 1'b0; 25 | i1 = 1'b0; 26 | i2 = 1'b0; 27 | i3 = 1'b0; 28 | 29 | #3000 $finish; 30 | end 31 | 32 | always #317 i0 = ~i0; 33 | always #37 i1 = ~i1; 34 | always #157 i2 = ~i2; 35 | always #67 i3 = ~i3; 36 | 37 | endmodule 38 | 39 | 40 | -------------------------------------------------------------------------------- /verilog_files/tb_multiple_modules.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 1ps 5 | module tb_multiple_modules; 6 | // Inputs 7 | reg a,b,c; 8 | // Outputs 9 | wire y; 10 | 11 | // Instantiate the Unit Under Test (UUT) 12 | multiple_modules uut ( 13 | .a(a), 14 | .b(b), 15 | .c(c), 16 | .y(y) 17 | ); 18 | 19 | initial begin 20 | $dumpfile("tb_multiple_modules.vcd"); 21 | $dumpvars(0,tb_multiple_modules); 22 | // Initialize Inputs 23 | a = 0; 24 | b = 0; 25 | c = 0; 26 | #300 $finish; 27 | end 28 | 29 | always #10 a = ~a; 30 | always #55 b = ~b; 31 | always #75 c = ~c; 32 | endmodule 33 | 34 | 35 | -------------------------------------------------------------------------------- /verilog_files/tb_mux_generate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_mux_generate; 3 | // Inputs 4 | reg i0,i1; 5 | reg i2,i3; 6 | reg [1:0] sel; 7 | 8 | //TB Signals 9 | reg clk,reset; 10 | 11 | // Outputs 12 | wire y; 13 | 14 | // Instantiate the Unit Under Test (UUT) 15 | mux_generate uut ( 16 | .sel(sel), 17 | .i0(i0), 18 | .i1(i1), 19 | .i2(i2), 20 | .i3(i3), 21 | .y(y) 22 | ); 23 | 24 | initial begin 25 | $dumpfile("tb_mux_generate.vcd"); 26 | $dumpvars(0,tb_mux_generate); 27 | // Initialize Inputs 28 | i0 = 1'b0; 29 | i1 = 1'b0; 30 | i2 = 1'b0; 31 | i3 = 1'b0; 32 | clk = 1'b0; 33 | reset = 1'b0 ; #1; 34 | reset = 1'b1 ; #10; 35 | reset = 1'b0; 36 | 37 | #3000 $finish; 38 | end 39 | 40 | always #17 i0 = ~i0; 41 | always #37 i1 = ~i1; 42 | always #88 i2 = ~i2; 43 | always #155 i3 = ~i3; 44 | always #300 clk = ~clk; 45 | 46 | always @ (posedge clk , posedge reset) 47 | begin 48 | if(reset) 49 | sel <= 2'b00; 50 | else 51 | sel <= sel + 1; 52 | end 53 | 54 | 55 | 56 | endmodule 57 | 58 | 59 | -------------------------------------------------------------------------------- /verilog_files/tb_opt_check.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_opt_check; 4 | // Inputs 5 | reg a,b; 6 | // Outputs 7 | wire y; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | opt_check uut ( 11 | .a(a), 12 | .b(b), 13 | .y(y) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_opt_check.vcd"); 18 | $dumpvars(0,tb_opt_check); 19 | // Initialize Inputs 20 | a = 0; 21 | b = 0; 22 | #300 $finish; 23 | end 24 | 25 | always #10 a = ~a; 26 | always #55 b = ~b; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /verilog_files/tb_opt_check2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_opt_check2; 5 | // Inputs 6 | reg a,b; 7 | // Outputs 8 | wire y; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | opt_check2 uut ( 12 | .a(a), 13 | .b(b), 14 | .y(y) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_opt_check2.vcd"); 19 | $dumpvars(0,tb_opt_check2); 20 | // Initialize Inputs 21 | a = 0; 22 | b = 0; 23 | #300 $finish; 24 | end 25 | 26 | always #10 a = ~a; 27 | always #55 b = ~b; 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /verilog_files/tb_opt_check3.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `timescale 1ns / 1ps 4 | module tb_opt_check3; 5 | // Inputs 6 | reg a,b,c; 7 | // Outputs 8 | wire y; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | opt_check3 uut ( 12 | .a(a), 13 | .b(b), 14 | .c(c), 15 | .y(y) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("tb_opt_check3.vcd"); 20 | $dumpvars(0,tb_opt_check3); 21 | // Initialize Inputs 22 | a = 0; 23 | b = 0; 24 | c = 0; 25 | #300 $finish; 26 | end 27 | 28 | always #10 a = ~a; 29 | always #55 b = ~b; 30 | always #75 c = ~c; 31 | endmodule 32 | 33 | 34 | -------------------------------------------------------------------------------- /verilog_files/tb_partial_case_assign.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | `timescale 1ns / 1ps 7 | module tb_partial_case_assign.v; 8 | //input 9 | reg i0,i1,i2,sel; 10 | // Output 11 | wire x,y; 12 | //TB_SIGNALS 13 | reg clk,reset; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | partial_case_assign.v uut ( 17 | .sel(sel), 18 | .i0(i0), 19 | .i1(i1), 20 | .i2(i2), 21 | .i3(i3), 22 | .x(x), 23 | .y(y) 24 | ); 25 | 26 | initial begin 27 | $dumpfile("tb_partial_case_assign.v.vcd"); 28 | $dumpvars(0,tb_partial_case_assign.v); 29 | // Initialize Inputs 30 | i0 = 1'b0; 31 | i1 = 1'b0; 32 | i2 = 1'b0; 33 | clk = 1'b0; 34 | reset = 1'b0; #1; 35 | reset = 1'b1; #10; 36 | reset = 1'b0; 37 | 38 | 39 | #5000 $finish; 40 | end 41 | 42 | always #317 i0 = ~i0; 43 | always #600 clk = ~clk; 44 | always #37 i1 = ~i1; 45 | always #57 i2 = ~i2; 46 | 47 | 48 | always @(posedge clk , posedge reset) 49 | begin 50 | if(reset) 51 | sel <= 2'b00; 52 | else 53 | sel <= sel + 1; 54 | end 55 | endmodule 56 | 57 | 58 | -------------------------------------------------------------------------------- /verilog_files/tb_pattern_detect_fsm.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_upcntr; 3 | // Inputs 4 | reg clk, reset; 5 | // Outputs 6 | wire [3:0] cnt; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | upcntr uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .din(din), 13 | .pattern_detect(pattern_detect) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_upcntr.vcd"); 18 | $dumpvars(0,tb_upcntr); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | #3000 $finish; 23 | end 24 | 25 | always #10 clk = ~clk; 26 | always #123 reset=0; 27 | endmodule 28 | -------------------------------------------------------------------------------- /verilog_files/tb_rca.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_rca; 3 | // TB_SIGNALS 4 | reg clk, reset ; 5 | reg [7:0] num1 ; 6 | reg [7:0] num2; 7 | wire [8:0] sum_out; 8 | // Instantiate the Unit Under Test (UUT) 9 | rca uut ( 10 | .num1(num1), 11 | .num2(num2), 12 | .sum(sum_out) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("tb_rca.vcd"); 17 | $dumpvars(0,tb_rca); 18 | // Initialize Inputs 19 | clk = 0; 20 | reset = 0; 21 | reset = 1; #1; 22 | reset = 0; #10; 23 | #30000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | 28 | 29 | always @ (clk,reset) 30 | begin 31 | if(reset) 32 | begin 33 | num1 <= 8'b0; 34 | num2 <= 8'b0; 35 | end 36 | else 37 | begin 38 | num1 = num1 + 1; 39 | if(num1[3:0] == 4'b1111) 40 | num2 = num2+1; 41 | end 42 | 43 | end 44 | 45 | 46 | endmodule 47 | 48 | 49 | -------------------------------------------------------------------------------- /verilog_files/tb_ripple_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_ripple_counter; 3 | // Inputs 4 | reg clk, reset ; 5 | // Output 6 | wire [1:0] q; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | ripple_counter uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .q(q) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("tb_ripple_counter.vcd"); 17 | $dumpvars(0,tb_ripple_counter); 18 | // Initialize Inputs 19 | clk = 0; 20 | reset = 1; 21 | #3000 $finish; 22 | end 23 | 24 | always #10 clk = ~clk; 25 | always #1547 reset=~reset; 26 | endmodule 27 | -------------------------------------------------------------------------------- /verilog_files/tb_ternary_operator_mux.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module tb_ternary_operator_mux; 4 | // Inputs 5 | reg i0,i1,sel; 6 | // Outputs 7 | wire y; 8 | 9 | // Instantiate the Unit Under Test (UUT) 10 | ternary_operator_mux uut ( 11 | .sel(sel), 12 | .i0(i0), 13 | .i1(i1), 14 | .y(y) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("tb_ternary_operator_mux.vcd"); 19 | $dumpvars(0,tb_ternary_operator_mux); 20 | // Initialize Inputs 21 | sel = 0; 22 | i0 = 0; 23 | i1 = 0; 24 | #300 $finish; 25 | end 26 | 27 | always #75 sel = ~sel; 28 | always #10 i0 = ~i0; 29 | always #55 i1 = ~i1; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /verilog_files/tb_up_dn_cntr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_up_dn_cntr; 3 | // Inputs 4 | reg clk, reset, up_dnb; 5 | // Outputs 6 | wire [3:0] cnt; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | up_dn_cntr uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .up_dnb(up_dnb), 13 | .cnt(cnt) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("tb_up_dn_cntr.vcd"); 18 | $dumpvars(0,tb_up_dn_cntr); 19 | // Initialize Inputs 20 | clk = 0; 21 | reset = 1; 22 | up_dnb = 1; 23 | #3000 $finish; 24 | end 25 | 26 | always #10 clk = ~clk; 27 | always #501 up_dnb = ~up_dnb; 28 | always #123 reset=0; 29 | endmodule 30 | -------------------------------------------------------------------------------- /verilog_files/tb_up_dn_cntr_with_load.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_up_dn_cntr_with_load; 3 | // Inputs 4 | reg clk, reset, load_en , up_dnb ; 5 | reg [3:0] load_data; 6 | reg load_en_1 , load_en_2; 7 | // Outputs 8 | wire [3:0] cnt; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | up_dn_cntr_with_load uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .load_en(load_en), 15 | .load_data(load_data), 16 | .up_dnb(up_dnb), 17 | .cnt(cnt) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("tb_up_dn_cntr_with_load.vcd"); 22 | $dumpvars(0,tb_up_dn_cntr_with_load); 23 | // Initialize Inputs 24 | clk = 0; 25 | reset = 1; 26 | up_dnb = 1; 27 | load_en_1 = 0; 28 | load_en_2 = 0; 29 | load_data = 4'b0000; 30 | #3000 $finish; 31 | end 32 | 33 | always #5 clk = ~clk; 34 | always #123 reset = 0; 35 | always #130 load_data = load_data + 1; 36 | always #540 load_en_1 = ~load_en_1; 37 | always #1340 up_dnb = ~up_dnb; 38 | always #1 load_en = load_en_1 ^ load_en_2; 39 | 40 | always @ (posedge clk , posedge reset) 41 | begin 42 | if(reset) 43 | load_en_2 = 1'b0; 44 | else 45 | load_en_2 = load_en_1; 46 | end 47 | 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /verilog_files/tb_up_dn_cntr_with_load_with_start_stop.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_up_dn_cntr_with_load_with_start_stop; 3 | // Inputs 4 | reg clk, reset, load_en , up_dnb , start_stop_b ; 5 | reg [3:0] load_data; 6 | reg load_en_1 , load_en_2; 7 | // Outputs 8 | wire [3:0] cnt; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | up_dn_cntr_with_load_with_start_stop uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .load_en(load_en), 15 | .load_data(load_data), 16 | .up_dnb(up_dnb), 17 | .start_stop_b(start_stop_b), 18 | .cnt(cnt) 19 | ); 20 | 21 | initial begin 22 | $dumpfile("tb_up_dn_cntr_with_load_with_start_stop.vcd"); 23 | $dumpvars(0,tb_up_dn_cntr_with_load_with_start_stop); 24 | // Initialize Inputs 25 | clk = 0; 26 | reset = 1; 27 | up_dnb = 1; 28 | load_en_1 = 0; 29 | load_en_2 = 0; 30 | load_data = 4'b0000; 31 | start_stop_b = 1'b0; 32 | #7000 $finish; 33 | end 34 | 35 | always #5 clk = ~clk; 36 | always #123 reset = 0; 37 | always #130 load_data = load_data + 1; 38 | always #540 load_en_1 = ~load_en_1; 39 | always #1340 up_dnb = ~up_dnb; 40 | always #880 start_stop_b = ~start_stop_b; 41 | always #1 load_en = load_en_1 ^ load_en_2; 42 | 43 | always @ (posedge clk , posedge reset) 44 | begin 45 | if(reset) 46 | load_en_2 = 1'b0; 47 | else 48 | load_en_2 = load_en_1; 49 | end 50 | 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /verilog_files/tb_upcntr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb_upcntr; 3 | // Inputs 4 | reg clk, reset; 5 | // Outputs 6 | wire [3:0] cnt; 7 | 8 | // Instantiate the Unit Under Test (UUT) 9 | upcntr uut ( 10 | .clk(clk), 11 | .reset(reset), 12 | .cnt(cnt) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("tb_upcntr.vcd"); 17 | $dumpvars(0,tb_upcntr); 18 | // Initialize Inputs 19 | clk = 0; 20 | reset = 1; 21 | #3000 $finish; 22 | end 23 | 24 | always #10 clk = ~clk; 25 | always #123 reset=0; 26 | endmodule 27 | -------------------------------------------------------------------------------- /verilog_files/ternary_operator_mux.v: -------------------------------------------------------------------------------- 1 | module ternary_operator_mux (input i0 , input i1 , input sel , output y); 2 | assign y = sel?i1:i0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilog_files/ternary_operator_mux_net.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os) */ 2 | 3 | module ternary_operator_mux(i0, i1, sel, y); 4 | wire _0_; 5 | wire _1_; 6 | wire _2_; 7 | wire _3_; 8 | wire _4_; 9 | wire _5_; 10 | input i0; 11 | input i1; 12 | input sel; 13 | output y; 14 | sky130_fd_sc_hd__clkinv_1 _6_ ( 15 | .A(_0_), 16 | .Y(_4_) 17 | ); 18 | sky130_fd_sc_hd__nand2_1 _7_ ( 19 | .A(_1_), 20 | .B(_2_), 21 | .Y(_5_) 22 | ); 23 | sky130_fd_sc_hd__o21ai_0 _8_ ( 24 | .A1(_2_), 25 | .A2(_4_), 26 | .B1(_5_), 27 | .Y(_3_) 28 | ); 29 | assign _0_ = i0; 30 | assign _1_ = i1; 31 | assign _2_ = sel; 32 | assign y = _3_; 33 | endmodule 34 | -------------------------------------------------------------------------------- /verilog_files/up_dn_cntr.v: -------------------------------------------------------------------------------- 1 | 2 | module up_dn_cntr (input clk , input reset,input up_dnb , output reg [3:0] cnt); 3 | always @ (posedge clk , posedge reset) 4 | begin 5 | if(reset) 6 | cnt <= 4'b0000; 7 | else 8 | begin 9 | if(up_dnb) 10 | cnt <= cnt + 1; 11 | else 12 | cnt <= cnt - 1; 13 | end 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /verilog_files/up_dn_cntr_with_load.v: -------------------------------------------------------------------------------- 1 | 2 | module up_dn_cntr_with_load (input clk , input reset, input [3:0] load_data, input load_en , input up_dnb , output reg [3:0] cnt); 3 | 4 | always @ (posedge clk , posedge reset) 5 | begin 6 | if(reset) 7 | cnt <= 4'b0000; 8 | else 9 | begin 10 | if(load_en) 11 | cnt <= load_data; 12 | else 13 | begin 14 | if(up_dnb) 15 | cnt <= cnt + 1; 16 | else 17 | cnt <= cnt - 1; 18 | end 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilog_files/up_dn_cntr_with_load_with_start_stop.v: -------------------------------------------------------------------------------- 1 | module up_dn_cntr_with_load_with_start_stop (input clk , input reset, input [3:0] load_data, input load_en , input start_stop_b, input up_dnb , output reg [3:0] cnt); 2 | 3 | always @ (posedge clk , posedge reset) 4 | begin 5 | if(reset) 6 | cnt <= 4'b0000; 7 | else 8 | begin 9 | if(start_stop_b) 10 | begin 11 | if(load_en) 12 | cnt <= load_data; 13 | else 14 | begin 15 | if(up_dnb) 16 | cnt <= cnt + 1; 17 | else 18 | cnt <= cnt - 1; 19 | end 20 | end 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilog_files/upcntr.v: -------------------------------------------------------------------------------- 1 | module upcntr (input clk , input reset, output reg [3:0] cnt); 2 | always @ (posedge clk , posedge reset) 3 | begin 4 | if(reset) 5 | cnt <= 4'b0000; 6 | else 7 | cnt <= cnt + 1; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /yosys_run.sh: -------------------------------------------------------------------------------- 1 | # read design 2 | 3 | read_verilog 32bit_carry_ripple_adder.v 4 | 5 | # generic synthesis 6 | synth -top ripple_carry_adder 7 | 8 | # mapping to mycells.lib 9 | dfflibmap -liberty /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib 10 | abc -liberty /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib 11 | clean 12 | flatten 13 | # write synthesized design 14 | write_verilog -assert synth_ripple_carry_adder.v 15 | --------------------------------------------------------------------------------