├── .instr_ctrl.v.swp ├── .rsreg.v.swp ├── README.md ├── RSREG.v ├── _instr.txt ├── a.c ├── a.s ├── alu ├── alu.v ├── bc_instr.ans ├── bc_instr.txt ├── cpu.v ├── cpu_tb ├── cpu_tb.v ├── decoder ├── decoder.v ├── fifo.v ├── gen ├── gen.cpp ├── gen.exe ├── hazard1.txt ├── info ├── Basys3-FPGA-开发板实验参考资料.pdf ├── RISC.ppt ├── eetop.cn_riscv-spec-v2.1中文版.pdf ├── project-v1.0.pdf └── riscv-spec-v2.2.pdf ├── instr.bin ├── instr.txt ├── instr.zip ├── instr2.bin ├── instr_ctrl ├── instr_ctrl.v ├── instr_mem.v ├── mem.v ├── memory.v ├── opcode.h ├── out ├── ram.v ├── reg32.v ├── report.pptx ├── rs.v ├── rsreg ├── rsreg.v ├── sim ├── sim.cpp ├── test.in ├── test.vcd ├── trans ├── trans.cpp └── uart_comm.v /.instr_ctrl.v.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/kzoacn/RISCV-CPU/HEAD/.instr_ctrl.v.swp -------------------------------------------------------------------------------- /.rsreg.v.swp: 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