├── .ciignore ├── .circleci ├── README.md ├── build-extra-tests.sh ├── build-toolchains.sh ├── check-commit.sh ├── clean-old-files.sh ├── config.yml ├── create-hash.sh ├── defaults.sh ├── do-firesim-build.sh ├── do-rtl-build.sh ├── images │ ├── Dockerfile │ └── README.md ├── install-verilator.sh ├── run-firesim-tests.sh ├── run-midasexamples-tests.sh └── run-tests.sh ├── .ctags ├── .ctagsignore ├── .githooks └── ignore-certain-dirs-commit-msg ├── .github ├── ISSUE_TEMPLATE │ ├── bug-report.md │ ├── feature-request.md │ ├── other.md │ └── question.md └── PULL_REQUEST_TEMPLATE.md ├── .gitignore ├── .gitmodules ├── .readthedocs.yml ├── CHANGELOG.md ├── CONTRIBUTING.md ├── LICENSE ├── README.md ├── build.sbt ├── common.mk ├── docs ├── .gitignore ├── Advanced-Concepts │ ├── CDEs.rst │ ├── Chip-Communication.rst │ ├── Debugging-RTL.rst │ ├── Resources.rst │ ├── Top-Testharness.rst │ └── index.rst ├── Chipyard-Basics │ ├── Chipyard-Components.rst │ ├── Configs-Parameters-Mixins.rst │ ├── Development-Ecosystem.rst │ ├── Initial-Repo-Setup.rst │ └── index.rst ├── Customization │ ├── Boot-Process.rst │ ├── Custom-Chisel.rst │ ├── DMA-Devices.rst │ ├── Firrtl-Transforms.rst │ ├── Heterogeneous-SoCs.rst │ ├── IOBinders.rst │ ├── Incorporating-Verilog-Blocks.rst │ ├── Keys-Traits-Configs.rst │ ├── MMIO-Peripherals.rst │ ├── Memory-Hierarchy.rst │ ├── RoCC-Accelerators.rst │ ├── RoCC-or-MMIO.rst │ └── index.rst ├── Generators │ ├── Ariane.rst │ ├── BOOM.rst │ ├── Gemmini.rst │ ├── Hwacha.rst │ ├── IceNet.rst │ ├── Rocket-Chip.rst │ ├── Rocket.rst │ ├── SHA3.rst │ ├── SiFive-Generators.rst │ ├── TestChipIP.rst │ └── index.rst ├── Makefile ├── Simulation │ ├── FPGA-Accelerated-Simulation.rst │ ├── Software-RTL-Simulation.rst │ └── index.rst ├── Software │ ├── FireMarshal.rst │ ├── Spike.rst │ └── index.rst ├── TileLink-Diplomacy-Reference │ ├── Diplomacy-Connectors.rst │ ├── EdgeFunctions.rst │ ├── NodeTypes.rst │ ├── Register-Router.rst │ ├── Widgets.rst │ └── index.rst ├── Tools │ ├── Barstools.rst │ ├── Chisel-Testers.rst │ ├── Chisel.rst │ ├── Dsptools.rst │ ├── FIRRTL.rst │ ├── Treadle.rst │ └── index.rst ├── VLSI │ ├── Advanced-Usage.rst │ ├── Building-A-Chip.rst │ ├── Hammer.rst │ ├── Tutorial.rst │ └── index.rst ├── _static │ └── images │ │ ├── boom-pipeline-detailed.png │ │ ├── chip-bringup.png │ │ ├── chip-communication.png │ │ ├── chipyard-logo-full.png │ │ ├── chipyard-logo.png │ │ ├── chipyard-logo.svg │ │ ├── gemmini-system.png │ │ ├── gemmini-systolic-array.png │ │ ├── nic-design.png │ │ ├── rocketchip-diagram.png │ │ └── sha3.png ├── conf.py ├── index.rst └── requirements.txt ├── generators ├── chipyard │ └── src │ │ └── main │ │ ├── resources │ │ └── vsrc │ │ │ └── GCDMMIOBlackBox.v │ │ └── scala │ │ ├── ArianeConfigs.scala │ │ ├── ConfigFragments.scala │ │ ├── Generator.scala │ │ ├── IOBinders.scala │ │ ├── Subsystem.scala │ │ ├── System.scala │ │ ├── TestHarness.scala │ │ ├── TestSuites.scala │ │ ├── Top.scala │ │ ├── config │ │ ├── BoomConfigs.scala │ │ ├── HeteroConfigs.scala │ │ ├── RocketConfigs.scala │ │ ├── TracegenConfigs.scala │ │ └── TutorialConfigs.scala │ │ └── example │ │ ├── GCD.scala │ │ ├── InitZero.scala │ │ ├── NodeTypes.scala │ │ └── RegisterNodeExample.scala ├── firechip │ └── src │ │ ├── main │ │ └── scala │ │ │ ├── BridgeBinders.scala │ │ │ ├── FireSim.scala │ │ │ ├── Generator.scala │ │ │ ├── TargetConfigs.scala │ │ │ └── TargetLandTestSuites.scala │ │ └── test │ │ └── scala │ │ └── ScalaTestSuite.scala ├── tracegen │ └── src │ │ └── main │ │ └── scala │ │ ├── Configs.scala │ │ ├── System.scala │ │ └── Tile.scala └── utilities │ └── src │ └── main │ ├── resources │ ├── bootrom │ └── csrc │ │ └── emulator.cc │ └── scala │ └── Simulator.scala ├── project ├── build.properties └── plugins.sbt ├── scripts ├── add-githooks.sh ├── build-openocd.sh ├── build-toolchains.sh ├── build-util.sh ├── centos-req.sh ├── check-tracegen.sh ├── firesim-setup.sh ├── gen-tags.sh ├── init-submodules-no-riscv-tools-nolog.sh ├── init-submodules-no-riscv-tools.sh ├── init-vlsi.sh ├── tutorial-patches │ ├── RocketConfigs.scala.patch │ └── build.sbt.patch ├── tutorial-setup.sh └── ubuntu-req.sh ├── sims ├── vcs │ ├── .gitignore │ ├── Makefile │ └── dramsim2_ini └── verilator │ ├── .gitignore │ ├── Makefile │ └── dramsim2_ini ├── tests ├── .gitignore ├── Makefile ├── accum.c ├── big-blkdev.c ├── blkdev.c ├── blkdev.h ├── charcount.c ├── gcd.c ├── htif.ld ├── libgloss.mk ├── mmio.h ├── nic-loopback.c ├── nic.h ├── pingd.c ├── pwm.c └── rocc.h ├── variables.mk └── vlsi ├── .gitignore ├── Makefile ├── env.yml ├── example-vlsi ├── example.v ├── example.yml ├── extra_libraries └── example │ ├── ExampleDCO.gds │ ├── ExampleDCO.lef │ ├── ExampleDCO_PVT_0P63V_100C.lib │ └── ExampleDCO_PVT_0P77V_0C.lib └── view_gds.py /.ciignore: -------------------------------------------------------------------------------- 1 | docs/* 2 | -------------------------------------------------------------------------------- /.circleci/README.md: -------------------------------------------------------------------------------- 1 | Chipyard CI 2 | =========== 3 | 4 | Website: https://circleci.com/gh/ucb-bar/chipyard 5 | 6 | CircleCI Brief Explanation 7 | --------------------------- 8 | 9 | CircleCI is controlled by the `config.yml` script. 10 | It consists of a *workflow* which has a series of *jobs* within it that do particular tasks. 11 | All jobs in the workflow must pass for the CI run to be successful. 12 | 13 | At the bottom of the `config.yml` there is a `workflows:` section that specifies the order in which the jobs of the workflow should run. 14 | For example: 15 | 16 | - prepare-rocketchip: 17 | requires: 18 | - install-riscv-toolchain 19 | 20 | This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` steps to run before it can run. 21 | 22 | All jobs in the CI workflow are specified at the top of `config.yml` 23 | They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment. 24 | Finally, in the `steps:` section, the steps are run sequentially and state persists throughout a job. 25 | So when you run something like `checkout` the next step has the checked out code. 26 | Caching in the job is done by giving a file to cache on. 27 | `restore_cache:` loads the cache into the environment if the key matches while `save_cache:` writes to the cache with the key IF IT IS NOT PRESENT. 28 | Note, if the cache is already present for that key, the write to it is ignored. 29 | Here the key is built from a string where the `checksum` portion converts the file given into a hash. 30 | 31 | .circleci directory 32 | ------------------- 33 | 34 | This directory contains all the collateral for the Chipyard CI to work. 35 | The following is included: 36 | 37 | `build-toolchains.sh` # build either riscv-tools or esp-tools 38 | `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work 39 | `do-rtl-build.sh` # use verilator to build a sim executable (remotely) 40 | `config.yml` # main circleci config script to enumerate jobs/workflows 41 | `defaults.sh` # default variables used 42 | 43 | How things are setup for Chipyard 44 | --------------------------------- 45 | 46 | The steps for CI to run are as follows. 47 | 1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run). 48 | The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused). 49 | 2nd, create the simulator binary. 50 | This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. 51 | This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). 52 | 3rd, finally run the desired tests. 53 | 54 | Other CI Setup 55 | -------------- 56 | 57 | To get the CI to work correctly you need to setup CircleCI environment variables to point to the remote directory to build files and the server user/ip. 58 | In the project settings, you can find this under "Build Settings" "Environment Variables". 59 | You need to add two variables like the following: 60 | 61 | CI\_DIR = /path/to/where/you/want/to/store/remote/files 62 | SERVER = username@myserver.coolmachine.berkeley.edu 63 | 64 | Additionally, you need to add under the "PERMISSIONS" "SSH Permissions" section a private key that is on the build server that you are using. 65 | After adding a private key, it will show a fingerprint that should be added under the jobs that need to be run. 66 | 67 | Note: On the remote server you need to have the `*.pub` key file added to the `authorized_keys` file. 68 | -------------------------------------------------------------------------------- /.circleci/build-extra-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # turn echo on and error on earliest command 4 | set -ex 5 | 6 | # get shared variables 7 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 8 | source $SCRIPT_DIR/defaults.sh 9 | 10 | make -C $LOCAL_CHIPYARD_DIR/tests clean 11 | make -C $LOCAL_CHIPYARD_DIR/tests 12 | -------------------------------------------------------------------------------- /.circleci/build-toolchains.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # create the riscv tools/esp tools binaries 4 | # passed in as 5 | 6 | # turn echo on and error on earliest command 7 | set -ex 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | if [ ! -d "$HOME/$1-install" ]; then 14 | cd $HOME 15 | 16 | # init all submodules including the tools 17 | CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=2 $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 18 | fi 19 | -------------------------------------------------------------------------------- /.circleci/check-commit.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # check to see that submodule commits are present on the master branch 4 | 5 | # turn echo on and error on earliest command 6 | set -ex 7 | 8 | # get shared variables 9 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 10 | source $SCRIPT_DIR/defaults.sh 11 | 12 | # enter bhd repo 13 | cd $LOCAL_CHIPYARD_DIR 14 | 15 | # ignore the private vlsi submodules 16 | git config submodule.vlsi/hammer-cadence-plugins.update none 17 | git config submodule.vlsi/hammer-mentor-plugins.update none 18 | git config submodule.vlsi/hammer-synopsys-plugins.update none 19 | 20 | # initialize submodules and get the hashes 21 | git submodule update --init 22 | status=$(git submodule status) 23 | 24 | all_names=() 25 | 26 | 27 | search_submodule() { 28 | echo "Running check on submodule $submodule in $dir" 29 | hash=$(echo "$status" | grep "$dir.*$submodule " | awk '{print$1}' | grep -o "[[:alnum:]]*") 30 | for branch in "${branches[@]}" 31 | do 32 | echo "Searching for $hash in origin/$branch of $submodule" 33 | (git -C $dir/$submodule branch -r --contains "$hash" | grep "origin/$branch") && true # needs init'ed submodules 34 | if [ $? -eq 0 ] 35 | then 36 | all_names+=("$dir/$submodule $hash 0") 37 | return 38 | fi 39 | done 40 | all_names+=("$dir/$submodule $hash 1") 41 | return 42 | } 43 | 44 | search () { 45 | for submodule in "${submodules[@]}" 46 | do 47 | search_submodule 48 | done 49 | } 50 | 51 | submodules=("boom" "hwacha" "icenet" "sha3" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip" "gemmini") 52 | dir="generators" 53 | if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] 54 | then 55 | branches=("master") 56 | else 57 | branches=("master" "dev") 58 | fi 59 | search 60 | 61 | submodules=("riscv-gnu-toolchain" "riscv-isa-sim" "riscv-pk" "riscv-tests") 62 | dir="toolchains/esp-tools" 63 | branches=("master") 64 | search 65 | 66 | 67 | submodules=("riscv-gnu-toolchain" "riscv-isa-sim" "riscv-pk" "riscv-tests") 68 | dir="toolchains/riscv-tools" 69 | branches=("master") 70 | search 71 | 72 | # riscv-openocd doesn't use its master branch 73 | submodules=("riscv-openocd") 74 | dir="toolchains/riscv-tools" 75 | branches=("riscv") 76 | search 77 | 78 | submodules=("qemu" "libgloss") 79 | dir="toolchains" 80 | branches=("master") 81 | search 82 | 83 | submodules=("spec2017" "coremark") 84 | dir="software" 85 | branches=("master") 86 | search 87 | 88 | submodules=("axe" "barstools" "torture" "dsptools" "chisel-testers" "treadle" "firrtl-interpreter") 89 | dir="tools" 90 | if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] 91 | then 92 | branches=("master") 93 | else 94 | branches=("master" "dev") 95 | fi 96 | search 97 | 98 | submodules=("firesim") 99 | dir="sims" 100 | if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] 101 | then 102 | branches=("master") 103 | else 104 | branches=("master" "dev") 105 | fi 106 | search 107 | 108 | submodules=("hammer") 109 | dir="vlsi" 110 | branches=("master") 111 | search 112 | 113 | 114 | # turn off verbose printing to make this easier to read 115 | set +x 116 | 117 | # print all result strings 118 | for str in "${all_names[@]}"; 119 | do 120 | echo "$str" 121 | done 122 | 123 | # check if there was a non-zero return code 124 | for str in "${all_names[@]}"; 125 | do 126 | if [ ! 0 = $(echo "$str" | awk '{print$3}') ]; then 127 | exit 1 128 | fi 129 | done 130 | 131 | echo "Done checking all submodules" 132 | 133 | -------------------------------------------------------------------------------- /.circleci/clean-old-files.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # clean directories that are older than 30 days 4 | # argument is used as the directory to look in 5 | 6 | age () { 7 | local AGE_SEC 8 | local CUR_SEC 9 | local DIFF_SEC 10 | local SEC_PER_DAY 11 | 12 | SEC_PER_DAY=86400 13 | 14 | CUR_SEC=$(date +%s) 15 | AGE_SEC=$(stat -c %Y -- "$1") 16 | DIFF_SEC=$(expr $CUR_SEC - $AGE_SEC) 17 | 18 | echo $(expr $DIFF_SEC / $SEC_PER_DAY) 19 | } 20 | 21 | for d in $1/*/ ; do 22 | DIR_AGE="$(age $d)" 23 | if [ $DIR_AGE -ge 30 ]; then 24 | echo "Deleting $d since is it $DIR_AGE old" 25 | rm -rf $d 26 | else 27 | echo "Keep $d since it is $DIR_AGE old" 28 | fi 29 | done 30 | -------------------------------------------------------------------------------- /.circleci/create-hash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # get the hash of riscv-tools 4 | 5 | # turn echo on and error on earliest command 6 | set -ex 7 | set -o pipefail 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | # enter bhd repo 14 | cd $LOCAL_CHIPYARD_DIR 15 | 16 | # Use normalized output of git-submodule status as hashfile 17 | for tools in 'riscv-tools' 'esp-tools' ; do 18 | git submodule status "toolchains/${tools}" 'toolchains/libgloss' 'toolchains/qemu' | 19 | while read -r line ; do 20 | echo "${line#[!0-9a-f]}" 21 | done > "${HOME}/${tools}.hash" 22 | done 23 | echo "Hashfile for riscv-tools and esp-tools created in $HOME" 24 | -------------------------------------------------------------------------------- /.circleci/defaults.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | copy () { 4 | rsync -avzp -e 'ssh' $1 $2 5 | } 6 | 7 | run () { 8 | ssh -o "StrictHostKeyChecking no" -t $SERVER $@ 9 | } 10 | 11 | run_script () { 12 | ssh -o "StrictHostKeyChecking no" -t $SERVER 'bash -s' < $1 "$2" 13 | } 14 | 15 | clean () { 16 | # remove remote work dir 17 | run "rm -rf $REMOTE_WORK_DIR" 18 | } 19 | 20 | # make parallelism 21 | NPROC=8 22 | 23 | # verilator version 24 | VERILATOR_VERSION=v4.028 25 | 26 | # remote variables 27 | REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB 28 | REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install 29 | REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install 30 | REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard 31 | REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator 32 | REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim 33 | REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" 34 | REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install 35 | 36 | # local variables (aka within the docker container) 37 | LOCAL_CHECKOUT_DIR=$HOME/project 38 | LOCAL_RISCV_DIR=$HOME/riscv-tools-install 39 | LOCAL_ESP_DIR=$HOME/esp-tools-install 40 | LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR 41 | LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator 42 | LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim 43 | 44 | # key value store to get the build strings 45 | declare -A mapping 46 | mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" 47 | mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" 48 | mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" 49 | mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" 50 | mapping["rocketchip"]="SUB_PROJECT=rocketchip" 51 | mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" 52 | mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" 53 | mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" 54 | mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" 55 | mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" 56 | mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" 57 | mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" 58 | mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" 59 | mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config" 60 | -------------------------------------------------------------------------------- /.circleci/do-firesim-build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # create the different verilator builds 4 | # argument is the make command string 5 | 6 | # turn echo on and error on earliest command 7 | set -ex 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | # call clean on exit 14 | trap clean EXIT 15 | 16 | cd $LOCAL_CHIPYARD_DIR 17 | ./scripts/init-submodules-no-riscv-tools.sh 18 | cd $LOCAL_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib 19 | git submodule update --init elfutils libdwarf 20 | cd $LOCAL_CHIPYARD_DIR/sims/firesim 21 | ./scripts/build-libelf.sh 22 | ./scripts/build-libdwarf.sh 23 | cd $LOCAL_CHIPYARD_DIR 24 | 25 | 26 | # set stricthostkeychecking to no (must happen before rsync) 27 | run "echo \"Ping $SERVER\"" 28 | 29 | clean 30 | 31 | # copy over riscv/esp-tools, and chipyard to remote 32 | run "mkdir -p $REMOTE_CHIPYARD_DIR" 33 | copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR 34 | 35 | run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" 36 | run "cp -r ~/.sbt $REMOTE_WORK_DIR" 37 | 38 | TOOLS_DIR=$REMOTE_RISCV_DIR 39 | LD_LIB_DIR=$REMOTE_RISCV_DIR/lib 40 | 41 | if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then 42 | TOOLS_DIR=$REMOTE_ESP_DIR 43 | LD_LIB_DIR=$REMOTE_ESP_DIR/lib 44 | run "mkdir -p $REMOTE_ESP_DIR" 45 | copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR 46 | else 47 | run "mkdir -p $REMOTE_RISCV_DIR" 48 | copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR 49 | fi 50 | 51 | # Build MIDAS-level verilator sim 52 | FIRESIM_VARS="${mapping[$1]}" 53 | run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" 54 | run "export RISCV=\"$TOOLS_DIR\"; \ 55 | export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ 56 | export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ 57 | export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ 58 | export FIRESIM_ENV_SOURCED=1; \ 59 | make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator" 60 | run "rm -rf $REMOTE_CHIPYARD_DIR/project" 61 | 62 | # copy back the final build 63 | mkdir -p $LOCAL_CHIPYARD_DIR 64 | copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR 65 | 66 | # Fix dramsim2_ini symlink 67 | export $FIRESIM_VARS 68 | ln -sf $LOCAL_FIRESIM_DIR/midas/src/main/resources/dramsim2_ini $LOCAL_FIRESIM_DIR/generated-src/f1/${DESIGN}-${TARGET_CONFIG}-${PLATFORM_CONFIG}/dramsim2_ini 69 | -------------------------------------------------------------------------------- /.circleci/do-rtl-build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # create the different verilator builds 4 | # argument is the make command string 5 | 6 | # turn echo on and error on earliest command 7 | set -ex 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | # call clean on exit 14 | trap clean EXIT 15 | 16 | cd $LOCAL_CHIPYARD_DIR 17 | ./scripts/init-submodules-no-riscv-tools.sh 18 | 19 | # set stricthostkeychecking to no (must happen before rsync) 20 | run "echo \"Ping $SERVER\"" 21 | 22 | clean 23 | 24 | # copy over riscv/esp-tools, and chipyard to remote 25 | run "mkdir -p $REMOTE_CHIPYARD_DIR" 26 | copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR 27 | 28 | run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" 29 | run "cp -r ~/.sbt $REMOTE_WORK_DIR" 30 | 31 | TOOLS_DIR=$REMOTE_RISCV_DIR 32 | LD_LIB_DIR=$REMOTE_RISCV_DIR/lib 33 | 34 | if [ $1 = "chipyard-gemmini" ]; then 35 | export RISCV=$LOCAL_ESP_DIR 36 | export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib 37 | export PATH=$RISCV/bin:$PATH 38 | GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests 39 | cd $LOCAL_SIM_DIR/../../generators/gemmini/software 40 | git submodule update --init --recursive gemmini-rocc-tests 41 | cd gemmini-rocc-tests 42 | ./build.sh 43 | fi 44 | 45 | if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then 46 | TOOLS_DIR=$REMOTE_ESP_DIR 47 | LD_LIB_DIR=$REMOTE_ESP_DIR/lib 48 | run "mkdir -p $REMOTE_ESP_DIR" 49 | copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR 50 | else 51 | run "mkdir -p $REMOTE_RISCV_DIR" 52 | copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR 53 | fi 54 | 55 | # enter the verilator directory and build the specific config on remote server 56 | run "make -C $REMOTE_SIM_DIR clean" 57 | run "export RISCV=\"$TOOLS_DIR\"; \ 58 | export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ 59 | export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ 60 | export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ 61 | make -j$NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" 62 | run "rm -rf $REMOTE_CHIPYARD_DIR/project" 63 | 64 | # copy back the final build 65 | mkdir -p $LOCAL_CHIPYARD_DIR 66 | copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR 67 | -------------------------------------------------------------------------------- /.circleci/images/README.md: -------------------------------------------------------------------------------- 1 | General 2 | ------- 3 | This DockerFile contains the necessary steps to build a Docker container that can run 4 | projects with riscv-tools, chisel3, firrtl, and verilator. It installs the necessary 5 | apt-get packages and sets the environment variables needed in CircleCI. 6 | 7 | Build and Deploy the Container 8 | ------------------------------ 9 | 10 | sudo docker build . # to test build before building it with a tag 11 | sudo docker build -t :tag . # to build with tag (ex. 0.0.3) 12 | sudo docker login # login into the account to push to 13 | sudo docker push :tag # to push to repo with tag 14 | 15 | Path Names 16 | ---------- 17 | Older docker images (when this Dockerfile was in `riscv-boom/riscv-boom`) can be found in the `riscvboom/riscvboom-images`. 18 | Current up-to-date images are located in `ucbbar/chipyard-image` 19 | -------------------------------------------------------------------------------- /.circleci/install-verilator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # move verilator to the remote server 4 | 5 | # turn echo on and error on earliest command 6 | set -ex 7 | 8 | # get shared variables 9 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 10 | source $SCRIPT_DIR/defaults.sh 11 | 12 | run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR 13 | 14 | # set stricthostkeychecking to no (must happen before rsync) 15 | run "echo \"Ping $SERVER\"" 16 | 17 | run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \ 18 | cd $REMOTE_VERILATOR_DIR; \ 19 | git checkout $VERILATOR_VERSION; \ 20 | autoconf; \ 21 | export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \ 22 | ./configure; \ 23 | make -j$NPROC;" 24 | -------------------------------------------------------------------------------- /.circleci/run-firesim-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # turn echo on and error on earliest command 4 | set -ex 5 | 6 | # get remote exec variables 7 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 8 | source $SCRIPT_DIR/defaults.sh 9 | 10 | export FIRESIM_ENV_SOURCED=1 11 | 12 | SIMULATION_ARGS="${mapping[$1]}" 13 | 14 | cd $LOCAL_CHIPYARD_DIR/sims/firesim 15 | ./scripts/build-libelf.sh 16 | ./scripts/build-libdwarf.sh 17 | cd $LOCAL_CHIPYARD_DIR 18 | 19 | 20 | run_test_suite () { 21 | export RISCV=$LOCAL_RISCV_DIR 22 | export LD_LIBRARY_PATH=$LOCAL_RISCV_DIR/lib 23 | make -C $LOCAL_FIRESIM_DIR $SIMULATION_ARGS run-${1}-tests-fast 24 | } 25 | 26 | 27 | run_test_suite bmark 28 | run_test_suite nic 29 | run_test_suite blockdev 30 | -------------------------------------------------------------------------------- /.circleci/run-midasexamples-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # turn echo on and error on earliest command 4 | set -ex 5 | 6 | # get shared variables 7 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 8 | source $SCRIPT_DIR/defaults.sh 9 | 10 | # call clean on exit 11 | trap clean EXIT 12 | 13 | cd $LOCAL_CHIPYARD_DIR 14 | ./scripts/init-submodules-no-riscv-tools.sh 15 | cd sims/firesim/sim/midas 16 | 17 | # set stricthostkeychecking to no (must happen before rsync) 18 | run "echo \"Ping $SERVER\"" 19 | 20 | clean 21 | 22 | # copy over riscv-tools, and chipyard to remote 23 | run "mkdir -p $REMOTE_CHIPYARD_DIR" 24 | run "mkdir -p $REMOTE_RISCV_DIR" 25 | 26 | copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR 27 | copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR 28 | 29 | # Copy ivy2 and sbt directories 30 | 31 | run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" 32 | run "cp -r ~/.sbt $REMOTE_WORK_DIR" 33 | 34 | TOOLS_DIR=$REMOTE_RISCV_DIR 35 | LD_LIB_DIR=$REMOTE_RISCV_DIR/lib 36 | 37 | # Run midasexamples test 38 | 39 | run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" 40 | run "export RISCV=\"$TOOLS_DIR\"; \ 41 | export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ 42 | export FIRESIM_ENV_SOURCED=1; \ 43 | export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ 44 | export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ 45 | make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test" 46 | -------------------------------------------------------------------------------- /.circleci/run-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # run the different tests 4 | 5 | # turn echo on and error on earliest command 6 | set -ex 7 | 8 | # get remote exec variables 9 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 10 | source $SCRIPT_DIR/defaults.sh 11 | 12 | run_bmark () { 13 | make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ 14 | } 15 | 16 | run_asm () { 17 | make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ 18 | } 19 | 20 | run_both () { 21 | run_bmark $@ 22 | run_asm $@ 23 | } 24 | 25 | run_tracegen () { 26 | make tracegen -C $LOCAL_SIM_DIR $@ 27 | } 28 | 29 | # TODO BUG: the run-binary command forces a rebuild of the simulator in CI 30 | # instead, directly run the simulator binary 31 | case $1 in 32 | chipyard-rocket) 33 | run_bmark ${mapping[$1]} 34 | ;; 35 | chipyard-boom) 36 | run_bmark ${mapping[$1]} 37 | ;; 38 | chipyard-hetero) 39 | run_bmark ${mapping[$1]} 40 | ;; 41 | rocketchip) 42 | run_bmark ${mapping[$1]} 43 | ;; 44 | chipyard-hwacha) 45 | export RISCV=$LOCAL_ESP_DIR 46 | export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib 47 | export PATH=$RISCV/bin:$PATH 48 | make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} 49 | ;; 50 | chipyard-gemmini) 51 | export RISCV=$LOCAL_ESP_DIR 52 | export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib 53 | export PATH=$RISCV/bin:$PATH 54 | GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests 55 | rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests 56 | cd $LOCAL_SIM_DIR 57 | $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal 58 | $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal 59 | $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal 60 | ;; 61 | chipyard-sha3) 62 | (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) 63 | $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv 64 | ;; 65 | tracegen) 66 | run_tracegen ${mapping[$1]} 67 | ;; 68 | tracegen-boom) 69 | run_tracegen ${mapping[$1]} 70 | ;; 71 | chipyard-ariane) 72 | make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv 73 | ;; 74 | *) 75 | echo "No set of tests for $1. Did you spell it right?" 76 | exit 1 77 | ;; 78 | esac 79 | -------------------------------------------------------------------------------- /.ctags: -------------------------------------------------------------------------------- 1 | --langdef=scala 2 | --langmap=scala:.scala 3 | 4 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/ 5 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/ 6 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/ 7 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/ 8 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/ 9 | --regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/ 10 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/ 11 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/ 12 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/ 13 | --regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/ 14 | -------------------------------------------------------------------------------- /.ctagsignore: -------------------------------------------------------------------------------- 1 | */target 2 | sims 3 | toolchains 4 | -------------------------------------------------------------------------------- /.githooks/ignore-certain-dirs-commit-msg: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | if [[ ! -a .ciignore ]]; then 4 | exit # If .ciignore doesn't exists, just quit this Git hook 5 | fi 6 | 7 | # Load in every file that will be changed via this commit into an array 8 | changes=( `git diff --name-only --cached` ) 9 | 10 | # Load the patterns we want to skip into an array 11 | mapfile -t blacklist < .ciignore 12 | 13 | for i in "${blacklist[@]}" 14 | do 15 | # Remove the current pattern from the list of changes 16 | changes=( ${changes[@]/$i/} ) 17 | 18 | if [[ ${#changes[@]} -eq 0 ]]; then 19 | # If we've exhausted the list of changes before we've finished going 20 | # through patterns, that's okay, just quit the loop 21 | break 22 | fi 23 | done 24 | 25 | if [[ ${#changes[@]} -gt 0 ]]; then 26 | # If there's still changes left, then we have stuff to build, leave the commit alone. 27 | exit 28 | fi 29 | 30 | # Prefix the commit message with "[skip ci]" 31 | sed -i '1s/^/[skip ci] /' "$1" 32 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug-report.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Bug Report 3 | about: Report a problem with Chipyard 4 | labels: bug 5 | 6 | --- 7 | 8 | 9 | **Impact**: rtl | software | unknown | other 10 | 11 | **What is the current behavior?** 12 | 13 | **What is the expected behavior?** 14 | 15 | **Please tell us about your environment:** 16 | 21 | 22 | **Other information** 23 | 24 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/feature-request.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Feature Request 3 | about: Propose a change to Chipyard 4 | 5 | --- 6 | 7 | 8 | **Impact**: rtl | software | unknown | other 9 | 10 | **Description** 11 | 12 | 13 | **What is a motivating example for changing the behavior?** 14 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/other.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Other 3 | about: Something else! 4 | 5 | --- 6 | 7 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/question.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Question 3 | about: Ask a question 4 | labels: question 5 | 6 | --- 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | **Related issue**: 2 | 3 | 4 | **Type of change**: bug fix | new feature | other enhancement 5 | 6 | 7 | **Impact**: rtl change | software change | unknown | other 8 | 9 | **Release Notes** 10 | 11 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bootrom/* 2 | docs/warnings.txt 3 | /Makefrag.pkgs 4 | target 5 | *.jar 6 | *.stamp 7 | *.vcd 8 | *.swp 9 | *.log 10 | *# 11 | *~ 12 | .idea 13 | .DS_Store 14 | env.sh 15 | riscv-tools-install 16 | esp-tools-install 17 | tags 18 | *~ 19 | env-riscv-tools.sh 20 | env-esp-tools.sh 21 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | formats: all 3 | sphinx: 4 | configuration: docs/conf.py 5 | python: 6 | install: 7 | - requirements: docs/requirements.txt 8 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | 3 | This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ 4 | 5 | ## [1.2.0] - 2020-03-14 6 | 7 | A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418 8 | 9 | ### Added 10 | * Ring Topology System Bus NoC (#461) 11 | * Integration of the Ariane core into Chipyard (#448) 12 | * FireMarshal now generates an extra copy of linux kernel with dwarf debugging info for use in FirePerf (#427) 13 | * Add option to use blackboxed SimDRAM instead of SimAXIMem (#449) 14 | * Log `init-submodules` script (#433) 15 | * Moved the Docker image used for CI into Chipyard (prev. in BOOM) (#463) 16 | 17 | ### Changed 18 | * Bump FireSim to 1.9.0 - Includes FirePerf TracerV Flame Graph features 19 | * IOBinders and BuildTop unification between FireChip and Chipyard (#390) 20 | * Bump BOOM to version 2.2.4 (#463) 21 | * Bump Gemmini to version 0.2 (#469) 22 | * Update to CircleCI 2.1 config. syntax and cleanup CI file (#421) 23 | * FireMarshal moved from FireSim to Chipyard (#415) 24 | * Rename config. mixins to config fragments (#451) 25 | 26 | ### Fixed 27 | * `git status` should be clean. (Although you will need to manually cleanup the libgloss and qemu directories after first setup). (#411, #414) 28 | * Fix Hetero. BOOM + Rocket + Hwacha config (#413) 29 | * Fix VCS stdout (#417) 30 | * Add a git version check to the init scripts and make them work outside of the repo root (#459) 31 | * Fix generation of env.sh for zsh (#435) 32 | * GCD example bug (#465) 33 | 34 | ### Deprecated 35 | * N/A 36 | 37 | ### Removed 38 | * N/A 39 | 40 | 41 | 42 | ## [1.1.0] - 2020-01-25 43 | 44 | A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/367 45 | 46 | ### Added 47 | * Gemmini generator and config (PR #356 ) 48 | * Coremark + SPEC2017 benchmarks (PR #326, #338, #344) 49 | * Add Hwacha tests to CI (PR #284) 50 | * Add Hwacha tests to benchmark and assembly test suites (PR #284) 51 | * Added Hwacha + Large Boom Config (PR #315) 52 | * Add multi-core config with a small Rocket core attached on the side (PR #361 ) 53 | * Add UART and Test Harness UART Adapter to all configurations (PR #348) 54 | * User can specify $RISCV directory in build-toolchains.sh (PR #334) 55 | * Checksum offload in IceNet (PR #364) 56 | 57 | ### Changed 58 | * Rocketchip bumped to commit [4f0cdea](https://github.com/chipsalliance/rocket-chip/tree/4f0cdea85c8a2b849fd582ccc8497892001d06b0), for chisel version 3.2.0 which includes Async reset support 59 | * FireSim release 1.8.0 60 | * FireMarshal release 1.8.0 61 | * BOOM release 2.2.3 (PR #397) 62 | * baremetal software toolchains, using libgloss and newlib instead of in-house syscalls. 63 | * Add toolchain specific `env.sh` (PR #304) 64 | * `run-binary`-like interface now dumps `.log` (stdout) and `.out` (stderr) files (PR #308) 65 | * Split the VLSI build dir on type of design (PR #331) 66 | * Reduce Ctags runtime and only look at scala, C, C++, and Python files (PR #346) 67 | * Top/Top-level-traits now behave as a configurable generator (PR #347) 68 | * Test suite makefrag generator includes Hwacha test suites (PR #342) 69 | 70 | ### Fixed 71 | * Fix VLSI makefile requirements for SRAM generation (PR #318) 72 | * Only filter header files from common simulation files (PR #322) 73 | * Bump MacroCompiler for bugfixes (PR #332) 74 | * commit-on-master check has specific behavior based on source branch (PR #345) 75 | * Makefile filtering of blackbox resource files only omits .h files (PR #322) 76 | * Parallel make fixed (PR #386 #392) 77 | 78 | ### Deprecated 79 | * No longer need to specify `WithXTop`, default `Top` is a generator for all `Top`s (PR #347) 80 | 81 | ### Removed 82 | * N/A 83 | 84 | 85 | ## [1.0.0] - 2019-10-19 86 | 87 | ### Added 88 | 89 | * This repository used to be "project-template", a template for Chisel-based projects. Through tighter integration of multiple projects from the Berkeley Architecture Research group at UC Berkeley, this repository is re-released as Chipyard - a framework for agile hardware development of RISC-V based Systems-on-Chip. 90 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | Contributing to Chipyard 2 | ============================= 3 | 4 | ### Branch management: 5 | 6 | 1) github:com/ucb-bar/chipyard: master = stable release. All merges to master must go through PR. 7 | 2) github:com/ucb-bar/chipyard: dev = pre-release non-stable branch with latest features. All merges to dev must go through PR. 8 | 3) Other dependencies pointed at by Chipyard (e.g. firesim, boom): master should be the version submoduled in ucb-bar/chipyard master. 9 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2017-2020, The Regents of the University of California (Regents) 4 | All Rights Reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | 31 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ![CHIPYARD](https://github.com/ucb-bar/chipyard/raw/master/docs/_static/images/chipyard-logo-full.png) 2 | 3 | # Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/chipyard/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master) 4 | 5 | ## Using Chipyard 6 | 7 | To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/ 8 | 9 | ## What is Chipyard 10 | 11 | Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. 12 | It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. 13 | Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. 14 | Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). 15 | Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. 16 | 17 | ## Resources 18 | 19 | * Chipyard Documentation: https://chipyard.readthedocs.io/ 20 | * Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf 21 | * Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf 22 | 23 | ## Need help? 24 | 25 | * Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard 26 | * If you find a bug, post an issue on this repo 27 | 28 | ## Contributing 29 | 30 | * See [CONTRIBUTING.md](/CONTRIBUTING.md) 31 | 32 | ## Chipyard-related Publications 33 | 34 | These publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. 35 | 36 | * **Generators** 37 | * **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf). 38 | * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf). 39 | * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf). 40 | * **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925). 41 | * **Sims** 42 | * **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf). 43 | * **FireSim Micro Top Picks**: S. Karandikar, et al., *IEEE Micro, Top Picks 2018*. [PDF](https://sagark.org/assets/pubs/firesim-micro-top-picks2018.pdf). 44 | * **FASED**: D. Biancolin, et al., *FPGA'19*. [PDF](https://people.eecs.berkeley.edu/~biancolin/papers/fased-fpga19.pdf). 45 | * **Golden Gate**: A. Magyar, et al., *ICCAD'19*. [PDF](https://davidbiancolin.github.io/papers/goldengate-iccad19.pdf). 46 | * **FirePerf**: S. Karandikar, et al., *ASPLOS'20*. [PDF](https://sagark.org/assets/pubs/fireperf-asplos2020.pdf). 47 | * **Tools** 48 | * **Chisel**: J. Bachrach, et al., *DAC'12*. [PDF](https://people.eecs.berkeley.edu/~krste/papers/chisel-dac2012.pdf). 49 | * **FIRRTL**: A. Izraelevitz, et al., *ICCAD'17*. [PDF](https://ieeexplore.ieee.org/document/8203780). 50 | * **Chisel DSP**: A. Wang, et al., *DAC'18*. [PDF](https://ieeexplore.ieee.org/document/8465790). 51 | * **VLSI** 52 | * **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html). 53 | 54 | 55 | 56 | [hwacha]:http://hwacha.org 57 | [hammer]:https://github.com/ucb-bar/hammer 58 | [firesim]:https://fires.im 59 | [ucb-bar]: http://bar.eecs.berkeley.edu 60 | [eecs]: https://eecs.berkeley.edu 61 | [berkeley]: https://berkeley.edu 62 | [riscv]: https://riscv.org/ 63 | [rocket-chip]: https://github.com/freechipsproject/rocket-chip 64 | [boom]: https://github.com/ucb-bar/riscv-boom 65 | [firemarshal]: https://github.com/firesim/FireMarshal/ 66 | [ariane]: https://github.com/pulp-platform/ariane/ 67 | -------------------------------------------------------------------------------- /docs/.gitignore: -------------------------------------------------------------------------------- 1 | _build 2 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/Debugging-RTL.rst: -------------------------------------------------------------------------------- 1 | Debugging RTL 2 | ====================== 3 | 4 | While the packaged Chipyard configs and RTL have been tested to work, 5 | users will typically want to build custom chips by adding their own 6 | IP, or by modifying existing Chisel generators. Such changes might introduce 7 | bugs. This section aims to run through a typical debugging flow 8 | using Chipyard. We assume the user has a custom SoC configuration, 9 | and is trying to verify functionality by running some software test. 10 | We also assume the software has already been verified on a functional 11 | simulator, such as Spike or QEMU. This section will focus on debugging 12 | hardware. 13 | 14 | Waveforms 15 | --------------------------- 16 | 17 | The default software RTL simulators do not dump waveforms during execution. 18 | To build simulators with wave dump capabilities use must use the ``debug`` 19 | make target. For example: 20 | 21 | .. code-block:: shell 22 | 23 | make CONFIG=CustomConfig debug 24 | 25 | The ``run-binary-debug`` rule will also automatically build a simulator, 26 | run it on a custom binary, and generate a waveform. For example, to run a 27 | test on ``helloworld.riscv``, use 28 | 29 | .. code-block:: shell 30 | 31 | make CONFIG=CustomConfig run-binary-debug BINARY=helloworld.riscv 32 | 33 | VCS and Verilator also support many additional flags. For example, specifying 34 | the ``+vpdfilesize`` flag in VCS will treat the output file as a circular 35 | buffer, saving disk space for long-running simulations. Refer to the VCS 36 | and Verilator manuals for more information You may use the ``SIM_FLAGS`` 37 | make variable to set additional simulator flags: 38 | 39 | .. code-block:: shell 40 | 41 | make CONFIG=CustomConfig run-binary-debug BINARY=linux.riscv SIM_FLAGS=+vpdfilesize=1024 42 | 43 | .. note:: 44 | In some cases where there is multiple simulator flags, you can write the ``SIM_FLAGS`` 45 | like the following: ``SIM_FLAGS="+vpdfilesize=XYZ +some_other_flag=ABC"``. 46 | 47 | Print Output 48 | --------------------------- 49 | 50 | Both Rocket and BOOM can be configured with varying levels of print output. 51 | For information see the Rocket core source code, or the BOOM `documentation 52 | `__ website. In addition, developers 53 | may insert arbitrary printfs at arbitrary conditions within the Chisel generators. 54 | See the Chisel documentation for information on this. 55 | 56 | Once the cores have been configured with the desired print statements, the 57 | ``+verbose`` flag will cause the simulator to print the statements. The following 58 | commands will all generate desired print statements: 59 | 60 | .. code-block:: shell 61 | 62 | make CONFIG=CustomConfig run-binary-debug BINARY=helloworld.riscv 63 | 64 | # The below command does the same thing 65 | ./simv-CustomConfig-debug +verbose helloworld.riscv 66 | 67 | Both cores can be configured to print out commit logs, which can then be compared 68 | against a Spike commit log to verify correctness. 69 | 70 | Basic tests 71 | --------------------------- 72 | ``riscv-tests`` includes basic ISA-level tests and basic benchmarks. These 73 | are used in Chipyard CI, and should be the first step in verifying a chip's 74 | functionality. The make rule is 75 | 76 | .. code-block:: shell 77 | 78 | make CONFIG=CustomConfig run-asm-tests run-bmark-tests 79 | 80 | 81 | Torture tests 82 | --------------------------- 83 | The RISC-V torture utility generates random RISC-V assembly streams, compiles them, 84 | runs them on both the Spike functional model and the SW simulator, and verifies 85 | identical program behavior. The torture utility can also be configured to run 86 | continuously for stress-testing. The torture utility exists within the ``utilities`` 87 | directory. 88 | 89 | Firesim Debugging 90 | --------------------------- 91 | Chisel printfs, asserts, and waveform generation are also available in FireSim 92 | FPGA-accelerated simulation. See the FireSim 93 | `documentation `__ for more detail. 94 | 95 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/Resources.rst: -------------------------------------------------------------------------------- 1 | Accessing Scala Resources 2 | =============================== 3 | 4 | A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL. 5 | An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala `_. 6 | Here is the example inlined: 7 | 8 | .. code-block:: scala 9 | 10 | class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource { 11 | val io = IO(new Bundle { 12 | val clock = Input(Clock()) 13 | val reset = Input(Bool()) 14 | val serial = Flipped(new SerialIO(w)) 15 | val exit = Output(Bool()) 16 | }) 17 | 18 | addResource("/testchipip/vsrc/SimSerial.v") 19 | addResource("/testchipip/csrc/SimSerial.cc") 20 | } 21 | 22 | In this example, the ``SimSerial`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder. 23 | The ``addResource`` path retrieves resources from the ``src/main/resources`` directory. 24 | So to get an item at ``src/main/resources/fileA.v`` you can use ``addResource("/fileA.v")``. 25 | However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath. 26 | Thus, you need to add the SBT project as a dependency to the FIRRTL compiler in the Chipyard ``build.sbt``, which in Chipyards case is the ``tapeout`` project. 27 | For example, you added a new project called ``myAwesomeAccel`` in the Chipyard ``build.sbt``. 28 | Then you can add it as a ``dependsOn`` dependency to the ``tapeout`` project. 29 | For example: 30 | 31 | .. code-block:: scala 32 | 33 | lazy val myAwesomeAccel = (project in file("generators/myAwesomeAccelFolder")) 34 | .dependsOn(rocketchip) 35 | .settings(commonSettings) 36 | 37 | lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) 38 | .dependsOn(myAwesomeAccel) 39 | .settings(commonSettings) 40 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/Top-Testharness.rst: -------------------------------------------------------------------------------- 1 | Tops, Test-Harnesses, and the Test-Driver 2 | =========================================== 3 | 4 | The three highest levels of hierarchy in a Chipyard 5 | SoC are the Top (DUT), ``TestHarness``, and the ``TestDriver``. 6 | The Top and ``TestHarness`` are both emitted by Chisel generators. 7 | The ``TestDriver`` serves as our testbench, and is a Verilog 8 | file in Rocket Chip. 9 | 10 | 11 | Top/DUT 12 | ------------------------- 13 | 14 | The top-level module of a Rocket Chip SoC is composed via cake-pattern. 15 | Specifically, "Tops" extend a ``System``, which extends a ``Subsystem``, which extends a ``BaseSubsystem``. 16 | 17 | 18 | BaseSubsystem 19 | ^^^^^^^^^^^^^^^^^^^^^^^^^ 20 | 21 | The ``BaseSubsystem`` is defined in ``generators/rocketchip/src/main/scala/subsystem/BaseSubsystem.scala``. 22 | Looking at the ``BaseSubsystem`` abstract class, we see that this class instantiates the top-level buses 23 | (frontbus, systembus, peripherybus, etc.), but does not specify a topology. 24 | We also see this class define several ``ElaborationArtefacts``, files emitted after Chisel elaboration 25 | (e.g. the device tree string, and the diplomacy graph visualization GraphML file). 26 | 27 | Subsystem 28 | ^^^^^^^^^^^^^^^^^^^^^^^^^ 29 | 30 | Looking in `generators/chipyard/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` 31 | extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that 32 | defines and instantiates BOOM or Rocket tiles, depending on the parameters specified. 33 | We also connect some basic IOs for each tile here, specifically the hartids and the reset vector. 34 | 35 | System 36 | ^^^^^^^^^^^^^^^^^^^^^^^^^ 37 | 38 | ``generators/chipyard/src/main/scala/System.scala`` completes the definition of the ``System``. 39 | 40 | - ``HasHierarchicalBusTopology`` is defined in Rocket Chip, and specifies connections between the top-level buses 41 | - ``HasAsyncExtInterrupts`` and ``HasExtInterruptsModuleImp`` adds IOs for external interrupts and wires them appropriately to tiles 42 | - ``CanHave...AXI4Port`` adds various Master and Slave AXI4 ports, adds TL-to-AXI4 converters, and connects them to the appropriate buses 43 | - ``HasPeripheryBootROM`` adds a BootROM device 44 | 45 | Tops 46 | ^^^^^^^^^^^^^^^^^^^^^^^^^ 47 | 48 | A SoC Top then extends the ``System`` class with traits for custom components. 49 | In Chipyard, this includes things like adding a NIC, UART, and GPIO as well as setting up the hardware for the bringup method. 50 | Please refer to :ref:`Communicating with the DUT` for more information on these bringup methods. 51 | 52 | TestHarness 53 | ------------------------- 54 | 55 | The wiring between the ``TestHarness`` and the Top are performed in methods defined in traits added to the Top. 56 | When these methods are called from the ``TestHarness``, they may instantiate modules within the scope of the harness, 57 | and then connect them to the DUT. For example, the ``connectSimAXIMem`` method defined in the 58 | ``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMems`` 59 | and connect them to the correct IOs of the top. 60 | 61 | While this roundabout way of attaching to the IOs of the top may seem to be unnecessarily complex, it allows the designer to compose 62 | custom traits together without having to worry about the details of the implementation of any particular trait. 63 | 64 | TestDriver 65 | ------------------------- 66 | 67 | The ``TestDriver`` is defined in ``generators/rocketchip/src/main/resources/vsrc/TestDriver.v``. 68 | This Verilog file executes a simulation by instantiating the ``TestHarness``, driving the clock and reset signals, and interpreting the success output. 69 | This file is compiled with the generated Verilog for the ``TestHarness`` and the ``Top`` to produce a simulator. 70 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/index.rst: -------------------------------------------------------------------------------- 1 | Advanced Concepts 2 | ================================ 3 | 4 | The following sections are advanced topics about how to Chipyard works, how to use Chipyard, and special features of the framework. 5 | They expect you to know about Chisel, Parameters, configs, etc. 6 | 7 | .. toctree:: 8 | :maxdepth: 2 9 | :caption: Advanced Concepts: 10 | 11 | Top-Testharness 12 | Chip-Communication 13 | Debugging-RTL 14 | Resources 15 | CDEs 16 | 17 | -------------------------------------------------------------------------------- /docs/Chipyard-Basics/Development-Ecosystem.rst: -------------------------------------------------------------------------------- 1 | Development Ecosystem 2 | =============================== 3 | 4 | Chipyard Approach 5 | ------------------------------------------- 6 | 7 | The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts. 8 | Chipyard hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research `__ can coexist and be used together. 9 | Chipyard aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC). 10 | 11 | Chisel/FIRRTL 12 | ------------------------------------------- 13 | 14 | One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language `__ and the `FIRRTL Compiler `__. 15 | Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL. 16 | FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more! 17 | These two tools in combination allow quick design space exploration and development of new RTL. 18 | 19 | RTL Generators 20 | ------------------------------------------- 21 | 22 | Within this repository, all of the Chisel RTL is written as generators. 23 | Generators are parametrized programs designed to generate RTL code based on configuration specifications. 24 | Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. 25 | Generators allow you to create a family of SoC designs instead of a single instance of a design! 26 | -------------------------------------------------------------------------------- /docs/Chipyard-Basics/Initial-Repo-Setup.rst: -------------------------------------------------------------------------------- 1 | Initial Repository Setup 2 | ======================================================== 3 | 4 | Requirements 5 | ------------------------------------------- 6 | 7 | Chipyard is developed and tested on Linux-based systems. 8 | 9 | .. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. 10 | 11 | .. Warning:: Working under Windows is not recommended. 12 | 13 | 14 | In CentOS-based platforms, we recommend installing the following dependencies: 15 | 16 | .. include:: /../scripts/centos-req.sh 17 | :code: bash 18 | 19 | In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following dependencies: 20 | 21 | .. include:: /../scripts/ubuntu-req.sh 22 | :code: bash 23 | 24 | .. Note:: When running on an Amazon Web Services EC2 FPGA-development instance (for FireSim), FireSim includes a machine setup script that will install all of the aforementioned dependencies (and some additional ones). 25 | 26 | Checking out the sources 27 | ------------------------ 28 | 29 | After cloning this repo, you will need to initialize all of the submodules. 30 | 31 | .. code-block:: shell 32 | 33 | git clone https://github.com/ucb-bar/chipyard.git 34 | cd chipyard 35 | ./scripts/init-submodules-no-riscv-tools.sh 36 | 37 | When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. 38 | Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. 39 | 40 | .. _build-toolchains: 41 | 42 | Building a Toolchain 43 | ------------------------ 44 | 45 | The `toolchains` directory contains toolchains that include a cross-compiler toolchain, frontend server, and proxy kernel, which you will need in order to compile code to RISC-V instructions and run them on your design. 46 | Currently there are two toolchains, one for normal RISC-V programs, and another for Hwacha (``esp-tools``). 47 | For custom installations, Each tool within the toolchains contains individual installation procedures within its README file. 48 | To get a basic installation (which is the only thing needed for most Chipyard use-cases), just the following steps are necessary. 49 | 50 | .. code-block:: shell 51 | 52 | ./scripts/build-toolchains.sh riscv-tools # for a normal risc-v toolchain 53 | 54 | # OR 55 | 56 | ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions 57 | 58 | Once the script is run, a ``env.sh`` file is emitted that sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables. 59 | You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables. 60 | These variables need to be set for the ``make`` system to work properly. 61 | -------------------------------------------------------------------------------- /docs/Chipyard-Basics/index.rst: -------------------------------------------------------------------------------- 1 | Chipyard Basics 2 | ================================ 3 | 4 | These sections will walk you through the basics of the Chipyard framework: 5 | 6 | - First, we will go over the components of the framework. 7 | 8 | - Next, we will go over how to understand how Chipyard configures its designs. 9 | 10 | - Then, we will go over initial framework setup. 11 | 12 | Hit next to get started! 13 | 14 | .. toctree:: 15 | :maxdepth: 2 16 | :caption: Chipyard Basics: 17 | 18 | Chipyard-Components 19 | Development-Ecosystem 20 | Configs-Parameters-Mixins 21 | Initial-Repo-Setup 22 | 23 | 24 | -------------------------------------------------------------------------------- /docs/Customization/Boot-Process.rst: -------------------------------------------------------------------------------- 1 | Chipyard Boot Process 2 | ======================= 3 | 4 | This section will describe in detail the process by which a Chipyard-based 5 | SoC boots a Linux kernel and the changes you can make to customize this process. 6 | 7 | BootROM and RISC-V Frontend Server 8 | ---------------------------------- 9 | 10 | The BootROM contains both the first instructions to run when the SoC is powered on as well as the 11 | Device Tree Binary (dtb) which details the components of the system. 12 | The assembly for the BootROM code is located in 13 | `generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S `_. 14 | The BootROM address space starts at ``0x10000`` (determined by the ``BootROMParams`` key in the configuration) and execution starts at address 15 | ``0x10040`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly. 16 | 17 | The Chisel generator encodes the assembled instructions into the BootROM 18 | hardware at elaboration time, so if you want to change the BootROM code, you 19 | will need to run ``make`` in the bootrom directory and then regenerate the 20 | Verilog. If you don't want to overwrite the existing ``bootrom.S``, you can 21 | also point the generator to a different bootrom image by overriding the 22 | ``BootROMParams`` key in the configuration. 23 | 24 | .. code-block:: scala 25 | 26 | class WithMyBootROM extends Config((site, here, up) => { 27 | case BootROMParams => 28 | BootROMParams(contentFileName = "/path/to/your/bootrom.img") 29 | }) 30 | 31 | The default bootloader simply loops on a wait-for-interrupt (WFI) instruction 32 | as the RISC-V frontend-server (FESVR) loads the actual program. 33 | FESVR is a program that runs on the host CPU and can read/write arbitrary 34 | parts of the target system memory using the Tethered Serial Interface (TSI). 35 | 36 | FESVR uses TSI to load a baremetal executable or second-stage bootloader into 37 | the SoC memory. In :ref:`Software RTL Simulation`, this will be the binary you 38 | pass to the simulator. Once it is finished loading the program, FESVR will 39 | write to the software interrupt register for CPU 0, which will bring CPU 0 40 | out of its WFI loop. Once it receives the interrupt, CPU 0 will write to 41 | the software interrupt registers for the other CPUs in the system and then 42 | jump to the beginning of DRAM to execute the first instruction of the loaded 43 | executable. The other CPUs will be woken up by the first CPU and also jump 44 | to the beginning of DRAM. 45 | 46 | The executable loaded by FESVR should have memory locations designated 47 | as *tohost* and *fromhost*. FESVR uses these memory locations to communicate 48 | with the executable once it is running. The executable uses *tohost* to send 49 | commands to FESVR for things like printing to the console, 50 | proxying system calls, and shutting down the SoC. The *fromhost* register is 51 | used to send back responses for *tohost* commands and for sending console 52 | input. 53 | 54 | The Berkeley Boot Loader and RISC-V Linux 55 | ----------------------------------------- 56 | 57 | For baremetal programs, the story ends here. The loaded executable will run in 58 | machine mode until it sends a command through the *tohost* register telling the 59 | FESVR to power off the SoC. 60 | 61 | However, for booting the Linux Kernel, you will need to use a second-stage 62 | bootloader called the Berkeley Boot Loader, or BBL. This program reads the 63 | device tree encoded in the boot ROM and transforms it into a format compatible 64 | with the Linux kernel. It then sets up virtual memory and the interrupt 65 | controller, loads the kernel, which is embedded in the bootloader binary as a 66 | payload, and starts executing the kernel in supervisor mode. The bootloader is 67 | also responsible for servicing machine-mode traps from the kernel and 68 | proxying them over FESVR. 69 | 70 | Once BBL jumps into supervisor mode, the Linux kernel takes over and begins 71 | its process. It eventually loads the ``init`` program and runs it in user 72 | mode, thus starting userspace execution. 73 | 74 | The easiest way to build a BBL image that boots Linux is to use the FireMarshal 75 | tool that lives in the `firesim-software `_ 76 | repository. Directions on how to use FireMarshal can be found in the 77 | `FireSim documentation `_. 78 | Using FireMarshal, you can add custom kernel configurations and userspace software 79 | to your workload. 80 | -------------------------------------------------------------------------------- /docs/Customization/Custom-Chisel.rst: -------------------------------------------------------------------------------- 1 | .. _custom_chisel: 2 | 3 | Integrating Custom Chisel Projects into the Generator Build System 4 | ================================================================== 5 | 6 | .. warning:: 7 | This section assumes integration of custom Chisel through git submodules. 8 | While it is possible to directly commit custom Chisel into the Chipyard framework, 9 | we heavily recommend managing custom code through git submodules. Using submodules decouples 10 | development of custom features from development on the Chipyard framework. 11 | 12 | 13 | While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. 14 | To add a submodule to the Chipyard framework, make sure that your project is organized as follows. 15 | 16 | .. code-block:: none 17 | 18 | yourproject/ 19 | build.sbt 20 | src/main/scala/ 21 | YourFile.scala 22 | 23 | Put this in a git repository and make it accessible. 24 | Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``. 25 | 26 | The ``build.sbt`` is a minimal file which describes metadata for a Chisel project. 27 | For a simple project, the ``build.sbt`` can even be empty, but below we provide an example 28 | build.sbt. 29 | 30 | .. code-block:: scala 31 | 32 | organization := "edu.berkeley.cs" 33 | 34 | version := "1.0" 35 | 36 | name := "yourproject" 37 | 38 | scalaVersion := "2.12.4" 39 | 40 | 41 | 42 | .. code-block:: shell 43 | 44 | cd generators/ 45 | git submodule add https://git-repository.com/yourproject.git 46 | 47 | Then add ``yourproject`` to the Chipyard top-level build.sbt file. 48 | 49 | .. code-block:: scala 50 | 51 | lazy val yourproject = (project in file("generators/yourproject")).settings(commonSettings).dependsOn(rocketchip) 52 | 53 | You can then import the classes defined in the submodule in a new project if 54 | you add it as a dependency. For instance, if you want to use this code in 55 | the ``chipyard`` project, change the final line in build.sbt to the following. 56 | 57 | .. code-block:: scala 58 | 59 | lazy val chipyard = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) 60 | -------------------------------------------------------------------------------- /docs/Customization/DMA-Devices.rst: -------------------------------------------------------------------------------- 1 | .. _dma-devices: 2 | 3 | Adding a DMA Device 4 | =================== 5 | 6 | DMA devices are Tilelink widgets which act as masters. In other words, 7 | DMA devices can send their own read and write requests to the chip's memory 8 | system. 9 | 10 | For IO devices or accelerators (like a disk or network driver), instead of 11 | having the CPU poll data from the device, we may want to have the device write 12 | directly to the coherent memory system instead. For example, here is a device 13 | that writes zeros to the memory at a configured address. 14 | 15 | .. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala 16 | :language: scala 17 | 18 | .. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala 19 | :language: scala 20 | :start-after: DOC include start: Top 21 | :end-before: DOC include end: Top 22 | 23 | We use ``TLHelper.makeClientNode`` to create a TileLink client node for us. 24 | We then connect the client node to the memory system through the front bus (fbus). 25 | For more info on creating TileLink client nodes, take a look at :ref:`Client Node`. 26 | 27 | Once we've created our top-level module including the DMA widget, we can create a configuration for it as we did before. 28 | 29 | .. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala 30 | :language: scala 31 | :start-after: DOC include start: WithInitZero 32 | :end-before: DOC include end: WithInitZero 33 | 34 | .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala 35 | :language: scala 36 | :start-after: DOC include start: InitZeroRocketConfig 37 | :end-before: DOC include end: InitZeroRocketConfig 38 | 39 | 40 | -------------------------------------------------------------------------------- /docs/Customization/IOBinders.rst: -------------------------------------------------------------------------------- 1 | IOBinders 2 | ========= 3 | 4 | In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what modules to bind to the IOs of a ``Top`` in the ``TestHarness``. 5 | 6 | .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala 7 | :language: scala 8 | :start-after: DOC include start: IOBinders 9 | :end-before: DOC include end: IOBinders 10 | 11 | 12 | This special key solves the problem of duplicating test-harnesses for each different ``Top`` type. 13 | 14 | You could just as well create a custom harness module that attaches IOs explicitly. Instead, the IOBinders key provides a map from Scala traits to attachment behaviors. 15 | 16 | For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected. 17 | 18 | .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala 19 | :language: scala 20 | :start-after: DOC include start: WithSimAXIMem 21 | :end-before: DOC include end: WithSimAXIMem 22 | 23 | These classes are all ``Config`` objects, which can be mixed into the configs to specify IO connection behaviors. 24 | 25 | There are two macros for generating these ``Config``s. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. 26 | -------------------------------------------------------------------------------- /docs/Customization/Memory-Hierarchy.rst: -------------------------------------------------------------------------------- 1 | .. _memory-hierarchy: 2 | 3 | Memory Hierarchy 4 | =============================== 5 | 6 | The L1 Caches 7 | -------------- 8 | 9 | Each CPU tile has an L1 instruction cache and L1 data cache. The size and 10 | associativity of these caches can be configured. The default ``RocketConfig`` 11 | uses 16 KiB, 4-way set-associative instruction and data caches. However, 12 | if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can 13 | configure 4 KiB direct-mapped caches for L1I and L1D. 14 | 15 | If you only want to change the size or associativity, there are config 16 | fragments for those too. See :ref:`Config Fragments` for how to add these to a custom ``Config``. 17 | 18 | .. code-block:: scala 19 | 20 | new freechips.rocketchip.subsystem.WithL1ICacheSets(128) ++ // change rocket I$ 21 | new freechips.rocketchip.subsystem.WithL1ICacheWays(2) ++ // change rocket I$ 22 | new freechips.rocketchip.subsystem.WithL1DCacheSets(128) ++ // change rocket D$ 23 | new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++ // change rocket D$ 24 | 25 | 26 | You can also configure the L1 data cache as an data scratchpad instead. 27 | However, there are some limitations on this. If you are using a data scratchpad, 28 | you can only use a single core and you cannot give the design an external DRAM. 29 | Note that these configurations fully remove the L2 cache and mbus. 30 | 31 | 32 | .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala 33 | :language: scala 34 | :start-after: DOC include start: scratchpadrocket 35 | :end-before: DOC include end: scratchpadrocket 36 | 37 | 38 | This configuration fully removes the L2 cache and memory bus by setting the 39 | number of channels and number of banks to 0. 40 | 41 | The SiFive L2 Cache 42 | ------------------- 43 | 44 | The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's 45 | InclusiveCache generator to produce a shared L2 cache. In the default 46 | configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way 47 | set-associativity. However, you can change these parameters to obtain your 48 | desired cache configuration. The main restriction is that the number of ways 49 | and the number of banks must be powers of 2. 50 | 51 | Refer to the ``CacheParameters`` object defined in sifive-cache for 52 | customization options. 53 | 54 | The Broadcast Hub 55 | ----------------- 56 | 57 | If you do not want to use the L2 cache (say, for a resource-limited embedded 58 | design), you can create a configuration without it. Instead of using the L2 59 | cache, you will instead use RocketChip's TileLink broadcast hub. 60 | To make such a configuration, you can just copy the definition of 61 | ``RocketConfig`` but omit the ``WithInclusiveCache`` config fragment from the 62 | list of included mixims. 63 | 64 | If you want to reduce the resources used even further, you can configure 65 | the Broadcast Hub to use a bufferless design. This config fragment is 66 | ``freechips.rocketchip.subsystem.WithBufferlessBroadcastHub``. 67 | 68 | 69 | The Outer Memory System 70 | ----------------------- 71 | 72 | The L2 coherence agent (either L2 cache or Broadcast Hub) makes requests to 73 | an outer memory system consisting of an AXI4-compatible DRAM controller. 74 | 75 | The default configuration uses a single memory channel, but you can configure 76 | the system to use multiple channels. As with the number of L2 banks, the 77 | number of DRAM channels is restricted to powers of two. 78 | 79 | .. code-block:: scala 80 | 81 | new freechips.rocketchip.subsystem.WithNMemoryChannels(2) 82 | 83 | 84 | In VCS and Verilator simulation, the DRAM is simulated using the 85 | ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each 86 | memory channel. 87 | 88 | If you want a more realistic memory simulation, you can use FireSim, which 89 | can simulate the timing of DDR3 controllers. More documentation on FireSim 90 | memory models is available in the `FireSim docs `_. 91 | -------------------------------------------------------------------------------- /docs/Customization/RoCC-Accelerators.rst: -------------------------------------------------------------------------------- 1 | .. _rocc-accelerators: 2 | 3 | Adding a RoCC Accelerator 4 | ---------------------------- 5 | 6 | RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class. 7 | Their implementation should extends the ``LazyRoCCModule`` class. 8 | 9 | .. code-block:: scala 10 | 11 | class CustomAccelerator(opcodes: OpcodeSet) 12 | (implicit p: Parameters) extends LazyRoCC(opcodes) { 13 | override lazy val module = new CustomAcceleratorModule(this) 14 | } 15 | 16 | class CustomAcceleratorModule(outer: CustomAccelerator) 17 | extends LazyRoCCModuleImp(outer) { 18 | val cmd = Queue(io.cmd) 19 | // The parts of the command are as follows 20 | // inst - the parts of the instruction itself 21 | // opcode 22 | // rd - destination register number 23 | // rs1 - first source register number 24 | // rs2 - second source register number 25 | // funct 26 | // xd - is the destination register being used? 27 | // xs1 - is the first source register being used? 28 | // xs2 - is the second source register being used? 29 | // rs1 - the value of source register 1 30 | // rs2 - the value of source register 2 31 | ... 32 | } 33 | 34 | 35 | The ``opcodes`` parameter for ``LazyRoCC`` is the set of custom opcodes that will map to this accelerator. 36 | More on this in the next subsection. 37 | 38 | The ``LazyRoCC`` class contains two TLOutputNode instances, ``atlNode`` and ``tlNode``. 39 | The former connects into a tile-local arbiter along with the backside of the L1 instruction cache. 40 | The latter connects directly to the L1-L2 crossbar. 41 | The corresponding Tilelink ports in the module implementation's IO bundle are ``atl`` and ``tl``, respectively. 42 | 43 | The other interfaces available to the accelerator are ``mem``, which provides access to the L1 cache; 44 | ``ptw`` which provides access to the page-table walker; 45 | the ``busy`` signal, which indicates when the accelerator is still handling an instruction; 46 | and the ``interrupt`` signal, which can be used to interrupt the CPU. 47 | 48 | Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala`` for detailed information on the different IOs. 49 | 50 | Adding RoCC accelerator to Config 51 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 52 | 53 | RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter in the configuration. 54 | This takes a sequence of functions producing ``LazyRoCC`` objects, one for each accelerator you wish to add. 55 | 56 | For instance, if we wanted to add the previously defined accelerator and route custom0 and custom1 instructions to it, we could do the following. 57 | 58 | .. code-block:: scala 59 | 60 | class WithCustomAccelerator extends Config((site, here, up) => { 61 | case BuildRoCC => Seq((p: Parameters) => LazyModule( 62 | new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) 63 | }) 64 | 65 | class CustomAcceleratorConfig extends Config( 66 | new WithCustomAccelerator ++ 67 | new RocketConfig) 68 | 69 | To add RoCC instructions in your program, use the RoCC C macros provided in ``tests/rocc.h``. You can find examples in the files ``tests/accum.c`` and ``charcount.c``. 70 | 71 | -------------------------------------------------------------------------------- /docs/Customization/RoCC-or-MMIO.rst: -------------------------------------------------------------------------------- 1 | .. _rocc-vs-mmio: 2 | 3 | RoCC vs MMIO 4 | ------------ 5 | 6 | Accelerators or custom IO devices can be added to your SoC in several ways: 7 | 8 | * MMIO Peripheral (a.k.a TileLink-Attached Accelerator) 9 | * Tightly-Coupled RoCC Accelerator 10 | 11 | These approaches differ in the method of the communication between the processor and the custom block. 12 | 13 | With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. 14 | 15 | In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. 16 | Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. 17 | RoCC coprocessor instructions have the following form. 18 | 19 | .. code-block:: none 20 | 21 | customX rd, rs1, rs2, funct 22 | 23 | The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to. 24 | The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers. 25 | The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other. 26 | 27 | Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with appropriate driver support. 28 | -------------------------------------------------------------------------------- /docs/Customization/index.rst: -------------------------------------------------------------------------------- 1 | Customization 2 | ================================ 3 | 4 | These guides will walk you through customization of your system-on-chip: 5 | 6 | - Contructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system. 7 | 8 | - How to include your custom Chisel sources in the Chipyard build system 9 | 10 | - Adding custom RoCC accelerators to an existing Chipyard core (BOOM or Rocket) 11 | 12 | - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs 13 | 14 | - Standard practices for using keys, traits, and configs to parameterize your design 15 | 16 | - Customizing the memory hierarchy 17 | 18 | - Connect widgets which act as TileLink masters 19 | 20 | - Adding custom blackboxed Verilog to a Chipyard design 21 | 22 | We also provide information on: 23 | 24 | - The boot process for Chipyard SoCs 25 | 26 | - Examples of FIRRTL transforms used in Chipyard, and where they are specified 27 | 28 | We recommend reading all these pages in order. Hit next to get started! 29 | 30 | .. toctree:: 31 | :maxdepth: 2 32 | :caption: Customization: 33 | 34 | Heterogeneous-SoCs 35 | Custom-Chisel 36 | RoCC-or-MMIO 37 | RoCC-Accelerators 38 | MMIO-Peripherals 39 | Keys-Traits-Configs 40 | DMA-Devices 41 | Incorporating-Verilog-Blocks 42 | Memory-Hierarchy 43 | Boot-Process 44 | Firrtl-Transforms 45 | IOBinders 46 | -------------------------------------------------------------------------------- /docs/Generators/Ariane.rst: -------------------------------------------------------------------------------- 1 | Ariane Core 2 | ==================================== 3 | 4 | `Ariane `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. 5 | The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`. 6 | The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. 7 | 8 | .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface). 9 | 10 | While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters). 11 | 12 | .. Warning:: This target does not support Verilator simulation at this time. Please use VCS. 13 | 14 | For more information, please refer to the `GitHub repository `__. 15 | -------------------------------------------------------------------------------- /docs/Generators/BOOM.rst: -------------------------------------------------------------------------------- 1 | Berkeley Out-of-Order Machine (BOOM) 2 | ============================================== 3 | 4 | .. image:: ../_static/images/boom-pipeline-detailed.png 5 | 6 | The `Berkeley Out-of-Order Machine (BOOM) `__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. 7 | It serves as a drop-in replacement to the Rocket core given by Rocket Chip (replaces the RocketTile with a BoomTile). 8 | BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 out-of-order processors. 9 | Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). 10 | Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. 11 | However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). 12 | 13 | Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages `__. 14 | -------------------------------------------------------------------------------- /docs/Generators/Hwacha.rst: -------------------------------------------------------------------------------- 1 | Hwacha 2 | ==================================== 3 | 4 | The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption. 5 | The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven 6 | The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal. 7 | 8 | For more information on the Hwacha project, please visit the `Hwacha website `__. 9 | 10 | To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). 11 | 12 | To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala `__ to see the possible configuration parameters. 13 | 14 | Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions. 15 | To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it. 16 | -------------------------------------------------------------------------------- /docs/Generators/IceNet.rst: -------------------------------------------------------------------------------- 1 | IceNet 2 | ====== 3 | 4 | IceNet is a library of Chisel designs related to networking. The main component 5 | of IceNet is IceNIC, a network interface controller that is used primarily 6 | in `FireSim `_ for multi-node networked simulation. 7 | A diagram of IceNet's microarchitecture is shown below. 8 | 9 | .. image:: ../_static/images/nic-design.png 10 | 11 | There are four basic parts of the NIC: the :ref:`Controller`, which takes requests 12 | from and sends responses to the CPU; the :ref:`Send Path`, which reads data from 13 | memory and sends it out to the network; the :ref:`Receive Path`, which receives 14 | data from the network and writes it to memory; and, optionally, 15 | the :ref:`Pause Handler`, which generates Ethernet pause frames for the purpose 16 | of flow control. 17 | 18 | Controller 19 | ---------- 20 | 21 | The controller exposes a set of MMIO registers to the CPU. The device driver 22 | writes to registers to request that packets be sent or to provide memory 23 | locations to write received data to. Upon the completion of a send request or 24 | packet receive, the controller sends an interrupt to the CPU, which clears 25 | the completion by reading from another register. 26 | 27 | Send Path 28 | --------- 29 | 30 | The send path begins at the reader, which takes requests from the controller 31 | and reads the data from memory. 32 | 33 | Since TileLink responses can come back out-of-order, we use a reservation 34 | queue to reorder responses so that the packet data can be sent out in the 35 | proper order. 36 | 37 | The packet data then goes to an arbiter, which can arbitrate access to the 38 | outbound network interface between the NIC and one or more "tap in" interfaces, 39 | which come from other hardware modules that may want to send Ethernet packets. 40 | By default, there are no tap in interfaces, so the arbiter simply passes 41 | the output of the reservation buffer through. 42 | 43 | Receive Path 44 | ------------ 45 | 46 | The receive path begins with the packet buffer, which buffers data coming 47 | in from the network. If there is insufficient space in the buffer, it will 48 | drop data at packet granularity to ensure that the NIC does not deliver 49 | incomplete packets. 50 | 51 | From the packet buffer, the data can optionally go to a network tap, which 52 | examines the Ethernet header and select packets to be redirected from the NIC 53 | to external modules through one or more "tap out" interfaces. By default, there 54 | are no tap out interfaces, so the data will instead go directly to the writer, 55 | which writes the data to memory and then sends a completion to the controller. 56 | 57 | Pause Handler 58 | ------------- 59 | 60 | IceNIC can be configured to have pause handler, which sits between the 61 | send and receive paths and the Ethernet interface. This module tracks the 62 | occupancy of the receive packet buffer. If it sees the buffer filling up, it 63 | will send an `Ethernet pause frame `_ 64 | out to the network to block further packets from being sent. If the NIC receives 65 | an Ethernet pause frame, the pause handler will block sending from the NIC. 66 | 67 | Linux Driver 68 | ------------ 69 | 70 | The default Linux configuration provided by `firesim-software `_ 71 | contains an IceNet driver. If you launch a FireSim image that has IceNIC on it, 72 | the driver will automatically detect the device, and you will be able to use 73 | the full Linux networking stack in userspace. 74 | 75 | Configuration 76 | ------------- 77 | 78 | To add IceNIC to your design, add ``HasPeripheryIceNIC`` to your lazy module 79 | and ``HasPeripheryIceNICModuleImp`` to the module implementation. If you 80 | are confused about the distinction between lazy module and module 81 | implementation, refer to :ref:`Cake Pattern`. 82 | 83 | Then add the ``WithIceNIC`` config fragment to your configuration. This will 84 | define ``NICKey``, which IceNIC uses to determine its parameters. The config fragment 85 | takes two arguments. The ``inBufFlits`` argument is the number of 64-bit flits 86 | that the input packet buffer can hold and the ``usePauser`` argument determines 87 | whether or not the NIC will have a pause handler. 88 | -------------------------------------------------------------------------------- /docs/Generators/Rocket-Chip.rst: -------------------------------------------------------------------------------- 1 | Rocket Chip 2 | =========== 3 | 4 | Rocket Chip generator is an SoC generator developed at Berkeley and now supported by 5 | `SiFive `__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC. 6 | 7 | `Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator. 8 | Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip 9 | uses Rocket core CPUs by default, it can also be configured to use the BOOM 10 | out-of-order core generator or some other custom CPU generator instead. 11 | 12 | A detailed diagram of a typical Rocket Chip system is shown below. 13 | 14 | .. image:: ../_static/images/rocketchip-diagram.png 15 | 16 | Tiles 17 | ----- 18 | 19 | The diagram shows a dual-core ``Rocket`` system. Each ``Rocket`` core is 20 | grouped with a page-table walker, L1 instruction cache, and L1 data cache into 21 | a ``RocketTile``. 22 | 23 | The ``Rocket`` core can also be swapped for a ``BOOM`` core. Each tile can 24 | also be configured with a RoCC accelerator that connects to the core as a 25 | coprocessor. 26 | 27 | Memory System 28 | ------------- 29 | The tiles connect to the ``SystemBus``, which connect it to the L2 cache banks. 30 | The L2 cache banks then connect to the ``MemoryBus``, which connects to the 31 | DRAM controller through a TileLink to AXI converter. 32 | 33 | To learn more about the memory hierarchy, see :ref:`Memory Hierarchy`. 34 | 35 | MMIO 36 | ---- 37 | 38 | For MMIO peripherals, the ``SystemBus`` connects to the ``ControlBus`` and ``PeripheryBus``. 39 | 40 | The ``ControlBus`` attaches standard peripherals like the BootROM, the 41 | Platform-Level Interrupt Controller (PLIC), the core-local interrupts (CLINT), 42 | and the Debug Unit. 43 | 44 | The BootROM contains the first stage bootloader, the first instructions to run 45 | when the system comes out of reset. It also contains the Device Tree, which is 46 | used by Linux to determine what other peripherals are attached. 47 | 48 | The PLIC aggregates and masks device interrupts and external interrupts. 49 | 50 | The core-local interrupts include software interrupts and timer interrupts for 51 | each CPU. 52 | 53 | The Debug Unit is used to control the chip externally. It can be used to load 54 | data and instructions to memory or pull data from memory. It can be controlled 55 | through a custom DMI or standard JTAG protocol. 56 | 57 | The ``PeripheryBus`` attaches additional peripherals like the NIC and Block Device. 58 | It can also optionally expose an external AXI4 port, which can be attached to 59 | vendor-supplied AXI4 IP. 60 | 61 | To learn more about adding MMIO peripherals, check out the :ref:`mmio-accelerators` 62 | section. 63 | 64 | DMA 65 | --- 66 | 67 | You can also add DMA devices that read and write directly from the memory 68 | system. These are attached to the ``FrontendBus``. The ``FrontendBus`` can also 69 | connect vendor-supplied AXI4 DMA devices through an AXI4 to TileLink converter. 70 | 71 | To learn more about adding DMA devices, see the :ref:`dma-devices` section. 72 | -------------------------------------------------------------------------------- /docs/Generators/Rocket.rst: -------------------------------------------------------------------------------- 1 | Rocket Core 2 | ==================================== 3 | 4 | `Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`. 5 | 6 | The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language. 7 | It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction. 8 | Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS). 9 | For floating-point, Rocket makes use of Berkeley’s Chisel implementations of floating-point units. 10 | Rocket also supports the RISC-V machine, supervisor, and user privilege levels. 11 | A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes. 12 | 13 | For more information, please refer to the `GitHub repository `__, `technical report `__ or to `this Chisel Community Conference video `__. 14 | -------------------------------------------------------------------------------- /docs/Generators/SiFive-Generators.rst: -------------------------------------------------------------------------------- 1 | SiFive Generators 2 | ================== 3 | 4 | Chipyard includes several open-source generators developed and maintained by `SiFive `__. 5 | These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``. 6 | 7 | Last-Level Cache Generator 8 | ----------------------------- 9 | 10 | ``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration. 11 | To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section. 12 | 13 | 14 | Peripheral Devices 15 | ------------------- 16 | ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. 17 | 18 | These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. 19 | To integrate one of these devices in your SoC, you will need to define a custom config fragment with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following config fragment to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. 20 | 21 | .. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigFragments.scala 22 | :language: scala 23 | :start-after: DOC include start: gpio config fragment 24 | :end-before: DOC include end: gpio config fragment 25 | 26 | Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC. 27 | When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. 28 | 29 | This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). 30 | 31 | 32 | Finally, you add the relevant config fragment to the SoC config. For example: 33 | 34 | .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala 35 | :language: scala 36 | :start-after: DOC include start: GPIORocketConfig 37 | :end-before: DOC include end: GPIORocketConfig 38 | 39 | Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined config fragments within the Chipyard example project. You may be able to use these config fragments directly, but you should be aware of their addresses within the SoC address map. 40 | -------------------------------------------------------------------------------- /docs/Generators/TestChipIP.rst: -------------------------------------------------------------------------------- 1 | Test Chip IP 2 | ============ 3 | 4 | Chipyard includes a Test Chip IP library which provides various hardware 5 | widgets that may be useful when designing SoCs. This includes a :ref:`Serial Adapter`, 6 | :ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, and :ref:`UART Adapter`. 7 | 8 | Serial Adapter 9 | -------------- 10 | 11 | The serial adapter is used by tethered test chips to communicate with the host 12 | processor. An instance of RISC-V frontend server running on the host CPU 13 | can send commands to the serial adapter to read and write data from the memory 14 | system. The frontend server uses this functionality to load the test program 15 | into memory and to poll for completion of the program. More information on 16 | this can be found in :ref:`Chipyard Boot Process`. 17 | 18 | Block Device Controller 19 | ----------------------- 20 | 21 | The block device controller provides a generic interface for secondary storage. 22 | This device is primarily used in FireSim to interface with a block device 23 | software simulation model. The default Linux configuration in `firesim-software `_ 24 | 25 | To add a block device to your design, add the ``WithBlockDevice`` config fragment to your configuration. 26 | 27 | 28 | TileLink SERDES 29 | --------------- 30 | 31 | The TileLink SERDES in the Test Chip IP library allow TileLink memory requests 32 | to be serialized so that they can be carried off chip through a serial link. 33 | The five TileLink channels are multiplexed over two SERDES channels, one in 34 | each direction. 35 | 36 | There are three different variants provided by the library, ``TLSerdes`` 37 | exposes a manager interface to the chip, tunnels A, C, and E channels on 38 | its outbound link, and tunnels B and D channels on its inbound link. ``TLDesser`` 39 | exposes a client interface to the chip, tunnels A, C, and E on its inbound link, 40 | and tunnels B and D on its outbound link. Finally, ``TLSerdesser`` exposes 41 | both client and manager interface to the chip and can tunnel all channels in 42 | both directions. 43 | 44 | For an example of how to use the SERDES classes, take a look at the 45 | ``SerdesTest`` unit test in `the Test Chip IP unit test suite 46 | `_. 47 | 48 | TileLink Switcher 49 | ----------------- 50 | 51 | The TileLink switcher is used when the chip has multiple possible memory 52 | interfaces and you would like to select which channels to map your memory 53 | requests to at boot time. It exposes a client node, multiple manager nodes, 54 | and a select signal. Depending on the setting of the select signal, requests 55 | from the client node will be directed to one of the manager nodes. 56 | The select signal must be set before any TileLink messages are sent and be 57 | kept stable throughout the remainder of operation. It is not safe to change 58 | the select signal once TileLink messages have begun sending. 59 | 60 | For an example of how to use the switcher, take a look at the ``SwitcherTest`` 61 | unit test in the `Test Chip IP unit tests `_. 62 | 63 | UART Adapter 64 | ------------ 65 | 66 | The UART Adapter is a device that lives in the TestHarness and connects to the 67 | UART port of the DUT to simulate communication over UART (ex. printing out to UART 68 | during Linux boot). In addition to working with ``stdin/stdout`` of the host, it is able to 69 | output a UART log to a particular file using ``+uartlog=`` during simulation. 70 | 71 | By default, this UART Adapter is added to all systems within Chipyard by adding the 72 | ``WithUART`` and ``WithUARTAdapter`` configs. 73 | -------------------------------------------------------------------------------- /docs/Generators/index.rst: -------------------------------------------------------------------------------- 1 | .. _generator-index: 2 | 3 | Included RTL Generators 4 | ============================ 5 | 6 | A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. 7 | This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`). 8 | A standard RTL design is essentially just a single instance of a design coming from a generator. 9 | However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. 10 | The following pages introduce the generators integrated with the Chipyard framework. 11 | 12 | Chipyard bundles the source code for the generators, under the ``generators/`` directory. 13 | It builds them from source each time (although the build system will cache results if they have not changed), 14 | so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows. 15 | 16 | 17 | .. toctree:: 18 | :maxdepth: 2 19 | :caption: Generators: 20 | 21 | Rocket-Chip 22 | Rocket 23 | BOOM 24 | Hwacha 25 | Gemmini 26 | IceNet 27 | TestChipIP 28 | SiFive-Generators 29 | SHA3 30 | Ariane 31 | 32 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line. 5 | SPHINXOPTS = -w warnings.txt 6 | SPHINXBUILD = python -msphinx 7 | SPHINXPROJ = Chipyard 8 | SOURCEDIR = . 9 | BUILDDIR = _build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | -------------------------------------------------------------------------------- /docs/Simulation/FPGA-Accelerated-Simulation.rst: -------------------------------------------------------------------------------- 1 | .. _firesim-sim-intro: 2 | 3 | FPGA-Accelerated Simulation 4 | ============================== 5 | 6 | FireSim 7 | ----------------------- 8 | 9 | `FireSim `__ is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). 10 | FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. 11 | FireSim also provides additional device models to allow full-system simulation, including memory models and network models. 12 | 13 | FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances. 14 | In order to simulate your Chipyard design using FireSim, if you have not 15 | already, follow the initial EC2 setup instructions as detailed in the `FireSim 16 | documentation `__. 17 | Then clone Chipyard onto your FireSim manager 18 | instance, and setup your Chipyard repository as you would normally. 19 | 20 | Next, initalize FireSim as a library in Chipyard by running: 21 | 22 | .. code-block:: shell 23 | 24 | # At the root of your chipyard repo 25 | ./scripts/firesim-setup.sh --fast 26 | 27 | ``firesim-setup.sh`` initializes additional submodules and then invokes 28 | firesim's ``build-setup.sh`` script adding ``--library`` to properly 29 | initialize FireSim as a library submodule in chipyard. You may run 30 | ``./sims/firesim/build-setup.sh --help`` to see more options. 31 | 32 | Finally, source the following environment at the root of the firesim directory: 33 | 34 | .. code-block:: shell 35 | 36 | cd sims/firesim 37 | # (Recommended) The default manager environment (includes env.sh) 38 | source sourceme-f1-manager.sh 39 | 40 | .. Note:: Every time you want to use FireSim with a fresh shell, you must source this ``sourceme-f1-manager.sh`` 41 | 42 | At this point you're ready to use FireSim with Chipyard. If you're not already 43 | familiar with FireSim, please return to the `FireSim Docs 44 | `__, 45 | and proceed with the rest of the tutorial. 46 | 47 | Running your Design in FireSim 48 | ------------------------------ 49 | Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. 50 | 51 | 52 | .. literalinclude:: ../../generators/firechip/src/main/scala/TargetConfigs.scala 53 | :language: scala 54 | :start-after: DOC include start: firesimconfig 55 | :end-before: DOC include end: firesimconfig 56 | 57 | 58 | Only 3 additional config fragments are needed. 59 | 60 | * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. 61 | * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. 62 | * ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSim documentation for details. 63 | -------------------------------------------------------------------------------- /docs/Simulation/index.rst: -------------------------------------------------------------------------------- 1 | Simulation 2 | ======================= 3 | 4 | Chipyard supports two classes of simulation: 5 | 6 | #. Software RTL simulation using commercial or open-source (Verilator) RTL simulators 7 | #. FPGA-accelerated full-system simulation using FireSim 8 | 9 | Software RTL simulators of Chipyard designs run at O(1 KHz), but compile 10 | quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run 11 | at O(100 MHz), making them appropriate for booting an operating system and 12 | running a complete workload, but have multi-hour compile times and poorer debug 13 | visability. 14 | 15 | Click next to see how to run a simulation. 16 | 17 | .. toctree:: 18 | :maxdepth: 2 19 | :caption: Simulation: 20 | 21 | Software-RTL-Simulation 22 | FPGA-Accelerated-Simulation 23 | 24 | -------------------------------------------------------------------------------- /docs/Software/FireMarshal.rst: -------------------------------------------------------------------------------- 1 | .. _fire-marshal: 2 | 3 | FireMarshal 4 | ================= 5 | 6 | FireMarshal is a workload generation tool for RISC-V based systems. It 7 | currently only supports the FireSim FPGA-accelerated simulation platform. 8 | 9 | **Workloads** in FireMarshal consist of a series of **Jobs** that are assigned 10 | to logical nodes in the target system. If no jobs are specified, then the 11 | workload is considered ``uniform`` and only a single image will be produced for 12 | all nodes in the system. Workloads are described by a ``json`` file and a 13 | corresponding workload directory and can inherit their definitions from 14 | existing workloads. Typically, workload configurations are kept in 15 | ``workloads/`` although you can use any directory you like. We provide a few 16 | basic workloads to start with including buildroot or Fedora-based linux 17 | distributions and bare-metal. 18 | 19 | Once you define a workload, the ``marshal`` command will produce a 20 | corresponding boot-binary and rootfs for each job in the workload. This binary 21 | and rootfs can then be launched on qemu or spike (for functional simulation), or 22 | installed to a platform for running on real RTL (currently only FireSim is 23 | automated). 24 | 25 | To get started, checkout the full `FireMarshal documentation `_. 26 | -------------------------------------------------------------------------------- /docs/Software/Spike.rst: -------------------------------------------------------------------------------- 1 | The RISC-V ISA Simulator (Spike) 2 | ================================= 3 | 4 | Spike is the golden reference functional RISC-V ISA C++ sofware simulator. 5 | It provides full system emulation or proxied emulation with `HTIF/FESVR `__. 6 | It serves as a starting point for running software on a RISC-V target. 7 | Here is a highlight of some of Spikes main features: 8 | 9 | * Multiple ISAs: RV32IMAFDQCV extensions 10 | * Multiple memory models: Weak Memory Ordering (WMO) and Total Store Ordering (TSO) 11 | * Privileged Spec: Machine, Supervisor, User modes (v1.11) 12 | * Debug Spec 13 | * Single-step debugging with support for viewing memory/register contents 14 | * Multiple CPU support 15 | * JTAG support 16 | * Highly extensible (add and test new instructions) 17 | 18 | In most cases, software development for a Chipyard target will begin with functional simulation using Spike 19 | (usually with the addition of custom Spike models for custom accelerator functions), and only later move on to 20 | full cycle-accurate simulation using software RTL simulators or FireSim. 21 | 22 | Spike comes pre-packaged in the RISC-V toolchain and is available on the path as ``spike``. 23 | More information can be found in the `Spike repository `__. 24 | -------------------------------------------------------------------------------- /docs/Software/index.rst: -------------------------------------------------------------------------------- 1 | Target Software 2 | ================================== 3 | 4 | Chipyard includes tools for developing target software workloads. The primary 5 | tool is FireMarshal, which manages workload descriptions and generates binaries 6 | and disk images to run on your target designs. Workloads can be bare-metal, or 7 | be based on standard Linux distributions. Users can customize every part of the 8 | build process, including providing custom kernels (if needed by the hardware). 9 | 10 | FireMarshal can also run your workloads on high-performance functional 11 | simulators like Spike and Qemu. Spike is easily customized and serves as the 12 | official RISC-V ISA reference implementation. Qemu is a high-performance 13 | functional simulator that can run nearly as fast as native code, but can be 14 | challenging to modify. 15 | 16 | .. toctree:: 17 | :maxdepth: 2 18 | :caption: Contents: 19 | 20 | FireMarshal 21 | Spike 22 | -------------------------------------------------------------------------------- /docs/TileLink-Diplomacy-Reference/Diplomacy-Connectors.rst: -------------------------------------------------------------------------------- 1 | Diplomacy Connectors 2 | ==================== 3 | 4 | Nodes in a Diplomacy graph are connected to each other with edges. The Diplomacy 5 | library provides four operators that can be used to form edges between nodes. 6 | 7 | := 8 | -- 9 | 10 | This is the basic connection operator. It is the same syntax as the Chisel 11 | uni-directional connector, but it is not equivalent. This operator connects 12 | Diplomacy nodes, not Chisel bundles. 13 | 14 | The basic connection operator always creates a single edge between the two 15 | nodes. 16 | 17 | :=\* 18 | ---- 19 | 20 | This is a "query" type connection operator. It can create multiple edges 21 | between nodes, with the number of edges determined by the client node 22 | (the node on the right side of the operator). This can be useful if you 23 | are connecting a multi-edge client to a nexus node or adapter node. 24 | 25 | :\*= 26 | ---- 27 | 28 | This is a "star" type connection operator. It also creates multiple edges, 29 | but the number of edges is determined by the manager (left side of operator), 30 | rather than the client. It's useful for connecting nexus nodes to multi-edge 31 | manager nodes. 32 | 33 | :\*=\* 34 | ------ 35 | 36 | This is a "flex" connection operator. It creates multiple edges based on 37 | whichever side of the operator has a known number of edges. This can be used 38 | in generators where the type of node on either side isn't known until runtime. 39 | -------------------------------------------------------------------------------- /docs/TileLink-Diplomacy-Reference/index.rst: -------------------------------------------------------------------------------- 1 | TileLink and Diplomacy Reference 2 | ================================ 3 | 4 | TileLink is the cache coherence and memory protocol used by RocketChip and 5 | other Chipyard generators. It is how different modules like caches, memories, 6 | peripherals, and DMA devices communicate with each other. 7 | 8 | RocketChip's TileLink implementation is built on top of Diplomacy, a framework 9 | for exchanging configuration information among Chisel generators in a two-phase 10 | elaboration scheme. For a detailed explanation of Diplomacy, see `the paper 11 | by Cook, Terpstra, and Lee `_. 12 | 13 | A brief overview of how to connect simple TileLink widgets can be found 14 | in the :ref:`mmio-accelerators` section. This section will provide a 15 | detailed reference for the TileLink and Diplomacy functionality provided by 16 | RocketChip. 17 | 18 | A detailed specification of the TileLink 1.7 protocol can be found on the 19 | `SiFive website `_. 20 | 21 | 22 | .. toctree:: 23 | :maxdepth: 2 24 | :caption: Reference 25 | 26 | NodeTypes 27 | Diplomacy-Connectors 28 | EdgeFunctions 29 | Register-Router 30 | Widgets 31 | -------------------------------------------------------------------------------- /docs/Tools/Chisel-Testers.rst: -------------------------------------------------------------------------------- 1 | Chisel Testers 2 | ============================== 3 | 4 | `Chisel Testers `__ is a library for writing tests for Chisel designs. 5 | It provides a Scala API for interacting with a DUT. 6 | It can use multiple backends, including things such as Treadle and Verilator. 7 | See :ref:`Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods. 8 | -------------------------------------------------------------------------------- /docs/Tools/Chisel.rst: -------------------------------------------------------------------------------- 1 | Chisel 2 | =========================== 3 | 4 | `Chisel `__ is an open-source hardware description language embedded in Scala. 5 | It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM. 6 | 7 | After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog. 8 | First is the compilation step. 9 | If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions. 10 | Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more. 11 | After the compilation is complete, elaboration begins. 12 | The Chisel generator starts elaboration using the module and configuration classes passed to it. 13 | This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code. 14 | If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library". 15 | However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral! 16 | See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog. 17 | 18 | For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. 19 | Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website `__. 20 | -------------------------------------------------------------------------------- /docs/Tools/Dsptools.rst: -------------------------------------------------------------------------------- 1 | Dsptools 2 | =============================== 3 | 4 | `Dsptools `__ is a Chisel library for writing custom signal processing hardware. 5 | Additionally, dsptools is useful for integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). 6 | 7 | Some features: 8 | 9 | * Complex type 10 | * Typeclasses for writing polymorphic hardware generators 11 | * For example, write one FIR filter generator that works for real or complex inputs 12 | * Extensions to Chisel testers for fixed point and floating point types 13 | * A diplomatic implementation of AXI4-Stream 14 | * Models for verifying APB, AXI-4, and TileLink interfaces with chisel-testers 15 | * DSP building blocks 16 | -------------------------------------------------------------------------------- /docs/Tools/FIRRTL.rst: -------------------------------------------------------------------------------- 1 | FIRRTL 2 | ================================ 3 | 4 | `FIRRTL `__ is an intermediate representation of your circuit. 5 | It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog. 6 | Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations. 7 | An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. 8 | Once the transformations are done, a Verilog file is emitted and the build process is done. 9 | 10 | For more information on please visit their `website `__. 11 | -------------------------------------------------------------------------------- /docs/Tools/Treadle.rst: -------------------------------------------------------------------------------- 1 | Treadle and FIRRTL Interpreter 2 | ============================== 3 | 4 | `Treadle `__ and 5 | `FIRRTL Interpreter `__ 6 | are circuit simulators that directly execute FIRRTL (specifically low-firrtl IR). 7 | Treadle is the replacement for FIRRTL Interpreter but FIRRTL Interpreter is still used within some 8 | projects. Treadle is useful for simulating modules in a larger SoC design. Many projects 9 | use Treadle for interactive debugging and a low-overhead simulator. 10 | -------------------------------------------------------------------------------- /docs/Tools/index.rst: -------------------------------------------------------------------------------- 1 | Development Tools 2 | ============================== 3 | 4 | The Chipyard framework relays heavily on a set of Scala-based tools. 5 | The following pages will introduce them, and how we can use them in order to generate flexible designs. 6 | 7 | .. toctree:: 8 | :maxdepth: 2 9 | :caption: Tools: 10 | 11 | Chisel 12 | FIRRTL 13 | Treadle 14 | Chisel-Testers 15 | Dsptools 16 | Barstools 17 | 18 | -------------------------------------------------------------------------------- /docs/VLSI/Advanced-Usage.rst: -------------------------------------------------------------------------------- 1 | .. _advanced-usage: 2 | 3 | Advanced Usage 4 | ============== 5 | 6 | Alternative RTL Flows 7 | --------------------- 8 | The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile). 9 | 10 | .. code-block:: shell 11 | 12 | CUSTOM_VLOG= 13 | VLSI_TOP= 14 | 15 | ``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files. 16 | 17 | Under the Hood 18 | -------------- 19 | To uncover what is happening under the hood, here are the commands that are executed: 20 | 21 | For ``make syn``: 22 | 23 | .. code-block:: shell 24 | 25 | ./example-vlsi -e /path/to/env.yml -p /path/to/example.yml -p /path/to/inputs.yml --obj_dir /path/to/build syn 26 | 27 | ``example-vlsi`` is the entry script as explained before, ``-e`` provides the environment yml, ``-p`` points to configuration yml/jsons, ``--obj_dir`` speficies the destination directory, and ``syn`` is the action. 28 | 29 | For ``make par``: 30 | 31 | .. code-block:: shell 32 | 33 | ./example-vlsi -e /path/to/env.yml -p /path/to/syn-output-full.json -o /path/to/par-input.json --obj_dir /path/to/build syn-to-par 34 | ./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json --obj_dir /path/to/build par 35 | 36 | A ``syn-to-par`` action translates the synthesis output configuration into an input configuration given by ``-o``. Then, this is passed to the ``par`` action. 37 | 38 | For more information about all the options that can be passed to the Hammer command-line driver, please see the Hammer documentation. 39 | 40 | Manual Step Execution & Dependency Tracking 41 | ------------------------------------------- 42 | It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed. 43 | 44 | Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command. 45 | 46 | Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings: 47 | 48 | .. code-block:: shell 49 | 50 | make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' 51 | 52 | RTL and Gate-level Simulation 53 | ----------------------------- 54 | With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. 55 | -------------------------------------------------------------------------------- /docs/VLSI/Building-A-Chip.rst: -------------------------------------------------------------------------------- 1 | .. _build-a-chip: 2 | 3 | Building A Chip 4 | =============== 5 | 6 | In this section, we will discuss many of the ASIC-specific transforms and methodologies within Chipyard. 7 | For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. 8 | 9 | Transforming the RTL 10 | -------------------- 11 | 12 | Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication. 13 | This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Barstools`. 14 | In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier. 15 | This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module. 16 | 17 | 18 | Modifying the logical hierarchy 19 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 20 | 21 | Building a large or complex chip often requires using hierarchical design to place and route sections of the chip separately. 22 | In addition, the design as written in Chipyard may not have a hierarchy that matches the physical hierarchy that would work best in the place and route tool. 23 | In order to reorganize the design to have its logical hierarchy match its physical hierarchy there are several FIRRTL transformations that can be run. 24 | These include grouping, which pull several modules into a larger one, and flattening, which dissolves a modules boundary leaving its components in its containing module. 25 | These transformations can be applied repeatedly to different parts of the design to arrange it as the physical designer sees fit. 26 | More details on how to use these transformations to reorganize the design hierarchy are forthcoming. 27 | 28 | 29 | Creating a floorplan 30 | -------------------- 31 | 32 | An ASIC floorplan is a specification that the place-and-route tools will follow when placing instances in the design. 33 | This includes the top-level chip dimensions, placement of SRAM macros, placement of custom (analog) circuits, IO cell placement, bump or wirebond pad placement, blockages, hierarchical boundaries, and pin placement. 34 | 35 | Much of the design effort that goes into building a chip involves developing optimal floorplans for the instance of the design that is being manufactured. 36 | Often this is a highly manual and iterative process which consumes much of the physical designer's time. 37 | This cost becomes increasingly apparent as the parameterization space grows rapidly when using tools like Chisel- cycle times are hampered by the human labor 38 | that is required to floorplan each instance of the design. 39 | The Hammer team is actively developing methods of improving the agility of floorplanning for generator-based designs, like those that use Chisel. 40 | The libraries we are developing will emit Hammer IR that can be passed directly to the Hammer tool without the need for human intervention. 41 | Stay tuned for more information. 42 | 43 | In the meantime, see the `Hammer Documentation `__ for information on the Hammer IR floorplan API. 44 | It is possible to write this IR directly, or to generate it using simple python scripts. 45 | While we certainly look forward to having a more featureful toolkit, we have built many chips to date in this way. 46 | 47 | 48 | Running the VLSI flow 49 | --------------------- 50 | 51 | For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. 52 | For an example of how to use the VLSI in the context of Chipyard, see :ref:`ASAP7 Tutorial`. 53 | 54 | 55 | -------------------------------------------------------------------------------- /docs/VLSI/index.rst: -------------------------------------------------------------------------------- 1 | VLSI Flow 2 | ================================ 3 | 4 | The Chipyard framework aims to provide wrappers for a general VLSI flow. 5 | In particular, we aim to support the Hammer physical design generator flow. 6 | 7 | .. toctree:: 8 | :maxdepth: 2 9 | :caption: VLSI Flow: 10 | 11 | Building-A-Chip 12 | Hammer 13 | Tutorial 14 | Advanced-Usage 15 | -------------------------------------------------------------------------------- /docs/_static/images/boom-pipeline-detailed.png: -------------------------------------------------------------------------------- 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input [WIDTH-1:0] x, 10 | input [WIDTH-1:0] y, 11 | input output_ready, 12 | output output_valid, 13 | output reg [WIDTH-1:0] gcd, 14 | output busy 15 | ); 16 | // DOC include end: GCD portlist 17 | 18 | localparam S_IDLE = 2'b00, S_RUN = 2'b01, S_DONE = 2'b10; 19 | 20 | reg [1:0] state; 21 | reg [WIDTH-1:0] tmp; 22 | 23 | assign input_ready = state == S_IDLE; 24 | assign output_valid = state == S_DONE; 25 | assign busy = state != S_IDLE; 26 | 27 | always @(posedge clock) begin 28 | if (reset) 29 | state <= S_IDLE; 30 | else if (state == S_IDLE && input_valid) 31 | state <= S_RUN; 32 | else if (state == S_RUN && tmp == 0) 33 | state <= S_DONE; 34 | else if (state == S_DONE && output_ready) 35 | state <= S_IDLE; 36 | end 37 | 38 | always @(posedge clock) begin 39 | if (state == S_IDLE && input_valid) begin 40 | gcd <= x; 41 | tmp <= y; 42 | end else if (state == S_RUN) begin 43 | if (gcd > tmp) 44 | gcd <= gcd - tmp; 45 | else 46 | tmp <= tmp - gcd; 47 | end 48 | end 49 | 50 | endmodule // GCDMMIOBlackBox 51 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/ArianeConfigs.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.config.{Config} 6 | 7 | // --------------------- 8 | // Ariane Configs 9 | // --------------------- 10 | 11 | class ArianeConfig extends Config( 12 | new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter 13 | new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts 14 | new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem 15 | new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) 16 | new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing 17 | new testchipip.WithTSI ++ // use testchipip serial offchip link 18 | new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) 19 | new chipyard.config.WithBootROM ++ // use default bootrom 20 | new chipyard.config.WithUART ++ // add a UART 21 | new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) 22 | new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) 23 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache 24 | new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts 25 | new ariane.WithNArianeCores(1) ++ // single Ariane core 26 | new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system 27 | 28 | class dmiArianeConfig extends Config( 29 | new chipyard.iobinders.WithUARTAdapter ++ 30 | new chipyard.iobinders.WithTieOffInterrupts ++ 31 | new chipyard.iobinders.WithSimAXIMem ++ 32 | new chipyard.iobinders.WithTiedOffSerial ++ 33 | new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation 34 | new chipyard.config.WithNoGPIO ++ 35 | new chipyard.config.WithBootROM ++ 36 | new chipyard.config.WithUART ++ 37 | new freechips.rocketchip.subsystem.WithNoMMIOPort ++ 38 | new freechips.rocketchip.subsystem.WithNoSlavePort ++ 39 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 40 | new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ 41 | new ariane.WithNArianeCores(1) ++ 42 | new freechips.rocketchip.system.BaseConfig) 43 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/Generator.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import scala.util.Try 4 | 5 | import chisel3._ 6 | 7 | import freechips.rocketchip.config.{Parameters} 8 | import freechips.rocketchip.util.{GeneratorApp} 9 | import freechips.rocketchip.system.{TestGeneration} 10 | 11 | object Generator extends GeneratorApp { 12 | // add unique test suites 13 | override def addTestSuites { 14 | implicit val p: Parameters = params 15 | TestSuiteHelper.addRocketTestSuites 16 | TestSuiteHelper.addBoomTestSuites 17 | TestSuiteHelper.addArianeTestSuites 18 | 19 | // if hwacha parameter exists then generate its tests 20 | // TODO: find a more elegant way to do this. either through 21 | // trying to disambiguate BuildRoCC, having a AccelParamsKey, 22 | // or having the Accelerator/Tile add its own tests 23 | import hwacha.HwachaTestSuites._ 24 | if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) { 25 | TestGeneration.addSuites(rv64uv.map(_("p"))) 26 | TestGeneration.addSuites(rv64uv.map(_("vp"))) 27 | TestGeneration.addSuite(rv64sv("p")) 28 | TestGeneration.addSuite(hwachaBmarks) 29 | } 30 | } 31 | 32 | // specify the name that the generator outputs files as 33 | override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs 34 | 35 | // generate files 36 | generateFirrtl 37 | generateAnno 38 | generateTestSuiteMakefrags 39 | generateArtefacts 40 | } 41 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/System.scala: -------------------------------------------------------------------------------- 1 | //****************************************************************************** 2 | // Copyright (c) 2019 - 2019, The Regents of the University of California (Regents). 3 | // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. 4 | //------------------------------------------------------------------------------ 5 | 6 | package chipyard 7 | 8 | import chisel3._ 9 | 10 | import freechips.rocketchip.config.{Parameters} 11 | import freechips.rocketchip.subsystem._ 12 | import freechips.rocketchip.tilelink._ 13 | import freechips.rocketchip.devices.tilelink._ 14 | import freechips.rocketchip.diplomacy._ 15 | import freechips.rocketchip.util.{DontTouch} 16 | 17 | // --------------------------------------------------------------------- 18 | // Base system that uses the debug test module (dtm) to bringup the core 19 | // --------------------------------------------------------------------- 20 | 21 | /** 22 | * Base top with periphery devices and ports, and a BOOM + Rocket subsystem 23 | */ 24 | class System(implicit p: Parameters) extends Subsystem 25 | with HasHierarchicalBusTopology 26 | with HasAsyncExtInterrupts 27 | with CanHaveMasterAXI4MemPort 28 | with CanHaveMasterAXI4MMIOPort 29 | with CanHaveSlaveAXI4Port 30 | with HasPeripheryBootROM 31 | { 32 | override lazy val module = new SystemModule(this) 33 | } 34 | 35 | /** 36 | * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem 37 | */ 38 | class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) 39 | with HasRTCModuleImp 40 | with HasExtInterruptsModuleImp 41 | with CanHaveMasterAXI4MemPortModuleImp 42 | with CanHaveMasterAXI4MMIOPortModuleImp 43 | with CanHaveSlaveAXI4PortModuleImp 44 | with HasPeripheryBootROMModuleImp 45 | with DontTouch 46 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/TestHarness.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import chisel3._ 4 | import chisel3.experimental._ 5 | 6 | import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} 7 | 8 | import freechips.rocketchip.diplomacy.LazyModule 9 | import freechips.rocketchip.config.{Field, Parameters} 10 | import freechips.rocketchip.util.GeneratorApp 11 | import freechips.rocketchip.devices.debug.{Debug} 12 | 13 | import chipyard.config.ConfigValName._ 14 | import chipyard.iobinders.{IOBinders} 15 | 16 | // ------------------------------- 17 | // BOOM and/or Rocket Test Harness 18 | // ------------------------------- 19 | 20 | case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module)) 21 | 22 | class TestHarness(implicit val p: Parameters) extends Module { 23 | val io = IO(new Bundle { 24 | val success = Output(Bool()) 25 | }) 26 | 27 | val dut = p(BuildTop)(p) 28 | io.success := false.B 29 | p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut)) 30 | } 31 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/Top.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.subsystem._ 6 | import freechips.rocketchip.system._ 7 | import freechips.rocketchip.config.Parameters 8 | import freechips.rocketchip.devices.tilelink._ 9 | 10 | // ------------------------------------ 11 | // BOOM and/or Rocket Top Level Systems 12 | // ------------------------------------ 13 | 14 | // DOC include start: Top 15 | class Top(implicit p: Parameters) extends System 16 | with testchipip.CanHaveTraceIO // Enables optionally adding trace IO 17 | with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad 18 | with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device 19 | with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port 20 | with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART 21 | with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs 22 | with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim 23 | with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget 24 | with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget 25 | { 26 | override lazy val module = new TopModule(this) 27 | } 28 | 29 | class TopModule[+L <: Top](l: L) extends SystemModule(l) 30 | with testchipip.CanHaveTraceIOModuleImp 31 | with testchipip.CanHavePeripheryBlockDeviceModuleImp 32 | with testchipip.CanHavePeripherySerialModuleImp 33 | with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp 34 | with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp 35 | with icenet.CanHavePeripheryIceNICModuleImp 36 | with chipyard.example.CanHavePeripheryGCDModuleImp 37 | with freechips.rocketchip.util.DontTouch 38 | // DOC include end: Top 39 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/TracegenConfigs.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import freechips.rocketchip.config.{Config} 4 | import freechips.rocketchip.rocket.{DCacheParams} 5 | 6 | class TraceGenConfig extends Config( 7 | new chipyard.iobinders.WithBlackBoxSimMem ++ 8 | new chipyard.iobinders.WithTraceGenSuccessBinder ++ 9 | new chipyard.config.WithTracegenTop ++ 10 | new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ 11 | new freechips.rocketchip.system.BaseConfig) 12 | 13 | class NonBlockingTraceGenConfig extends Config( 14 | new chipyard.iobinders.WithBlackBoxSimMem ++ 15 | new chipyard.iobinders.WithTraceGenSuccessBinder ++ 16 | new chipyard.config.WithTracegenTop ++ 17 | new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ 18 | new freechips.rocketchip.system.BaseConfig) 19 | 20 | class BoomTraceGenConfig extends Config( 21 | new chipyard.iobinders.WithBlackBoxSimMem ++ 22 | new chipyard.iobinders.WithTraceGenSuccessBinder ++ 23 | new chipyard.config.WithTracegenTop ++ 24 | new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ 25 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 26 | new freechips.rocketchip.system.BaseConfig) 27 | 28 | class NonBlockingTraceGenL2Config extends Config( 29 | new chipyard.iobinders.WithBlackBoxSimMem ++ 30 | new chipyard.iobinders.WithTraceGenSuccessBinder ++ 31 | new chipyard.config.WithTracegenTop ++ 32 | new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ 33 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 34 | new freechips.rocketchip.system.BaseConfig) 35 | 36 | class NonBlockingTraceGenL2RingConfig extends Config( 37 | new chipyard.iobinders.WithBlackBoxSimMem ++ 38 | new chipyard.iobinders.WithTraceGenSuccessBinder ++ 39 | new chipyard.config.WithTracegenTop ++ 40 | new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ 41 | new testchipip.WithRingSystemBus ++ 42 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 43 | new freechips.rocketchip.system.BaseConfig) 44 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/example/InitZero.scala: -------------------------------------------------------------------------------- 1 | package chipyard.example 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} 6 | import freechips.rocketchip.config.{Parameters, Field, Config} 7 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} 8 | import testchipip.TLHelper 9 | 10 | case class InitZeroConfig(base: BigInt, size: BigInt) 11 | case object InitZeroKey extends Field[Option[InitZeroConfig]](None) 12 | 13 | class InitZero(implicit p: Parameters) extends LazyModule { 14 | val node = TLHelper.makeClientNode( 15 | name = "init-zero", sourceId = IdRange(0, 1)) 16 | 17 | lazy val module = new InitZeroModuleImp(this) 18 | } 19 | 20 | class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) { 21 | val config = p(InitZeroKey).get 22 | 23 | val (mem, edge) = outer.node.out(0) 24 | val addrBits = edge.bundle.addressBits 25 | val blockBytes = p(CacheBlockBytes) 26 | 27 | require(config.size % blockBytes == 0) 28 | 29 | val s_init :: s_write :: s_resp :: s_done :: Nil = Enum(4) 30 | val state = RegInit(s_init) 31 | 32 | val addr = Reg(UInt(addrBits.W)) 33 | val bytesLeft = Reg(UInt(log2Ceil(config.size+1).W)) 34 | 35 | mem.a.valid := state === s_write 36 | mem.a.bits := edge.Put( 37 | fromSource = 0.U, 38 | toAddress = addr, 39 | lgSize = log2Ceil(blockBytes).U, 40 | data = 0.U)._2 41 | mem.d.ready := state === s_resp 42 | 43 | when (state === s_init) { 44 | addr := config.base.U 45 | bytesLeft := config.size.U 46 | state := s_write 47 | } 48 | 49 | when (edge.done(mem.a)) { 50 | addr := addr + blockBytes.U 51 | bytesLeft := bytesLeft - blockBytes.U 52 | state := s_resp 53 | } 54 | 55 | when (mem.d.fire()) { 56 | state := Mux(bytesLeft === 0.U, s_done, s_write) 57 | } 58 | } 59 | 60 | trait CanHavePeripheryInitZero { this: BaseSubsystem => 61 | implicit val p: Parameters 62 | 63 | p(InitZeroKey) .map { k => 64 | val initZero = LazyModule(new InitZero()(p)) 65 | fbus.fromPort(Some("init-zero"))() := initZero.node 66 | } 67 | } 68 | 69 | 70 | // DOC include start: WithInitZero 71 | class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { 72 | case InitZeroKey => Some(InitZeroConfig(base, size)) 73 | }) 74 | // DOC include end: WithInitZero 75 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/example/NodeTypes.scala: -------------------------------------------------------------------------------- 1 | package chipyard.example 2 | 3 | import freechips.rocketchip.config.Parameters 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.tilelink._ 6 | import testchipip.TLHelper 7 | 8 | // These modules are not meant to be synthesized. 9 | // They are used as examples in the documentation and are only here 10 | // to check that they compile. 11 | 12 | // DOC include start: MyClient 13 | class MyClient(implicit p: Parameters) extends LazyModule { 14 | val node = TLHelper.makeClientNode(TLClientParameters( 15 | name = "my-client", 16 | sourceId = IdRange(0, 4), 17 | requestFifo = true, 18 | visibility = Seq(AddressSet(0x10000, 0xffff)))) 19 | 20 | lazy val module = new LazyModuleImp(this) { 21 | val (tl, edge) = node.out(0) 22 | 23 | // Rest of code here 24 | } 25 | } 26 | // DOC include end: MyClient 27 | 28 | // DOC include start: MyManager 29 | class MyManager(implicit p: Parameters) extends LazyModule { 30 | val device = new SimpleDevice("my-device", Seq("tutorial,my-device0")) 31 | val beatBytes = 8 32 | val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( 33 | address = Seq(AddressSet(0x20000, 0xfff)), 34 | resources = device.reg, 35 | regionType = RegionType.UNCACHED, 36 | executable = true, 37 | supportsArithmetic = TransferSizes(1, beatBytes), 38 | supportsLogical = TransferSizes(1, beatBytes), 39 | supportsGet = TransferSizes(1, beatBytes), 40 | supportsPutFull = TransferSizes(1, beatBytes), 41 | supportsPutPartial = TransferSizes(1, beatBytes), 42 | supportsHint = TransferSizes(1, beatBytes), 43 | fifoId = Some(0))) 44 | 45 | lazy val module = new LazyModuleImp(this) { 46 | val (tl, edge) = node.in(0) 47 | } 48 | } 49 | // DOC include end: MyManager 50 | 51 | // DOC include start: MyClient1+MyClient2 52 | class MyClient1(implicit p: Parameters) extends LazyModule { 53 | val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1)) 54 | 55 | lazy val module = new LazyModuleImp(this) { 56 | // ... 57 | } 58 | } 59 | 60 | class MyClient2(implicit p: Parameters) extends LazyModule { 61 | val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1)) 62 | 63 | lazy val module = new LazyModuleImp(this) { 64 | // ... 65 | } 66 | } 67 | // DOC include end: MyClient1+MyClient2 68 | 69 | // DOC include start: MyClientGroup 70 | class MyClientGroup(implicit p: Parameters) extends LazyModule { 71 | val client1 = LazyModule(new MyClient1) 72 | val client2 = LazyModule(new MyClient2) 73 | val node = TLIdentityNode() 74 | 75 | node := client1.node 76 | node := client2.node 77 | 78 | lazy val module = new LazyModuleImp(this) { 79 | // Nothing to do here 80 | } 81 | } 82 | // DOC include end: MyClientGroup 83 | 84 | // DOC include start: MyManagerGroup 85 | class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { 86 | val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( 87 | address = Seq(AddressSet(0x0, 0xfff)))) 88 | 89 | lazy val module = new LazyModuleImp(this) { 90 | // ... 91 | } 92 | } 93 | 94 | class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule { 95 | val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( 96 | address = Seq(AddressSet(0x1000, 0xfff)))) 97 | 98 | lazy val module = new LazyModuleImp(this) { 99 | // ... 100 | } 101 | } 102 | 103 | class MyManagerGroup(beatBytes: Int)(implicit p: Parameters) extends LazyModule { 104 | val man1 = LazyModule(new MyManager1(beatBytes)) 105 | val man2 = LazyModule(new MyManager2(beatBytes)) 106 | val node = TLIdentityNode() 107 | 108 | man1.node := node 109 | man2.node := node 110 | 111 | lazy val module = new LazyModuleImp(this) { 112 | // Nothing to do here 113 | } 114 | } 115 | // DOC include end: MyManagerGroup 116 | 117 | // DOC include start: MyClientManagerComplex 118 | class MyClientManagerComplex(implicit p: Parameters) extends LazyModule { 119 | val client = LazyModule(new MyClientGroup) 120 | val manager = LazyModule(new MyManagerGroup(8)) 121 | 122 | manager.node :=* client.node 123 | 124 | lazy val module = new LazyModuleImp(this) { 125 | // Nothing to do here 126 | } 127 | } 128 | // DOC include end: MyClientManagerComplex 129 | -------------------------------------------------------------------------------- /generators/firechip/src/main/scala/BridgeBinders.scala: -------------------------------------------------------------------------------- 1 | //See LICENSE for license details. 2 | 3 | package firesim.firesim 4 | 5 | import chisel3._ 6 | import chisel3.experimental.annotate 7 | 8 | import freechips.rocketchip.config.{Field, Config, Parameters} 9 | import freechips.rocketchip.diplomacy.{LazyModule} 10 | import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp 11 | import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} 12 | import freechips.rocketchip.tile.{RocketTile} 13 | import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp 14 | 15 | import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} 16 | import icenet.CanHavePeripheryIceNICModuleImp 17 | 18 | import junctions.{NastiKey, NastiParameters} 19 | import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} 20 | import midas.targetutils.{MemModelAnnotation} 21 | import firesim.bridges._ 22 | import firesim.configs.MemModelKey 23 | import tracegen.HasTraceGenTilesModuleImp 24 | import ariane.ArianeTile 25 | 26 | import boom.common.{BoomTile} 27 | 28 | import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} 29 | import chipyard.HasChipyardTilesModuleImp 30 | 31 | class WithSerialBridge extends OverrideIOBinder({ 32 | (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq 33 | }) 34 | 35 | class WithNICBridge extends OverrideIOBinder({ 36 | (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq 37 | }) 38 | 39 | class WithUARTBridge extends OverrideIOBinder({ 40 | (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq 41 | }) 42 | 43 | class WithBlockDeviceBridge extends OverrideIOBinder({ 44 | (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq 45 | }) 46 | 47 | class WithFASEDBridge extends OverrideIOBinder({ 48 | (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { 49 | implicit val p = t.p 50 | (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => 51 | (io zip node.in).map({ case (axi4Bundle, (_, edge)) => 52 | val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, 53 | axi4Bundle.ar.bits.addr.getWidth, 54 | axi4Bundle.ar.bits.id.getWidth) 55 | FASEDBridge(axi4Bundle, t.reset.toBool, 56 | CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) 57 | }) 58 | }).toSeq 59 | } 60 | }) 61 | 62 | class WithTracerVBridge extends OverrideIOBinder({ 63 | (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq 64 | }) 65 | 66 | class WithTraceGenBridge extends OverrideIOBinder({ 67 | (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) 68 | }) 69 | 70 | class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ 71 | (c, r, s, target: HasChipyardTilesModuleImp) => { 72 | target.outer.tiles.map { 73 | case r: RocketTile => { 74 | annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) 75 | r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) 76 | } 77 | case b: BoomTile => { 78 | val core = b.module.core 79 | core.iregfile match { 80 | case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) 81 | case _ => Nil 82 | } 83 | if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { 84 | case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) 85 | case _ => Nil 86 | } 87 | } 88 | case a: ArianeTile => Nil 89 | } 90 | Nil 91 | } 92 | }) 93 | 94 | 95 | 96 | // Shorthand to register all of the provided bridges above 97 | class WithDefaultFireSimBridges extends Config( 98 | new chipyard.iobinders.WithGPIOTiedOff ++ 99 | new chipyard.iobinders.WithTiedOffDebug ++ 100 | new chipyard.iobinders.WithTieOffInterrupts ++ 101 | new WithSerialBridge ++ 102 | new WithNICBridge ++ 103 | new WithUARTBridge ++ 104 | new WithBlockDeviceBridge ++ 105 | new WithFASEDBridge ++ 106 | new WithFireSimMultiCycleRegfile ++ 107 | new WithTracerVBridge 108 | ) 109 | -------------------------------------------------------------------------------- /generators/firechip/src/main/scala/FireSim.scala: -------------------------------------------------------------------------------- 1 | //See LICENSE for license details. 2 | 3 | package firesim.firesim 4 | 5 | import chisel3._ 6 | 7 | import freechips.rocketchip.config.{Field, Config, Parameters} 8 | import freechips.rocketchip.diplomacy.{LazyModule} 9 | 10 | import midas.widgets.{Bridge, PeekPokeBridge} 11 | 12 | import chipyard.{BuildTop} 13 | import chipyard.iobinders.{IOBinders} 14 | 15 | // Determines the number of times to instantiate the DUT in the harness. 16 | // Subsumes legacy supernode support 17 | case object NumNodes extends Field[Int](1) 18 | 19 | class WithNumNodes(n: Int) extends Config((pname, site, here) => { 20 | case NumNodes => n 21 | }) 22 | 23 | class FireSim(implicit val p: Parameters) extends RawModule { 24 | val clock = IO(Input(Clock())) 25 | val reset = WireInit(false.B) 26 | withClockAndReset(clock, reset) { 27 | // Instantiate multiple instances of the DUT to implement supernode 28 | val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) 29 | val peekPokeBridge = PeekPokeBridge(reset) 30 | // A Seq of partial functions that will instantiate the right bridge only 31 | // if that Mixin trait is present in the target's class instance 32 | // 33 | // Apply each partial function to each DUT instance 34 | for ((target) <- targets) { 35 | p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) 36 | } 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /generators/firechip/src/main/scala/Generator.scala: -------------------------------------------------------------------------------- 1 | //See LICENSE for license details. 2 | 3 | package firesim.firesim 4 | 5 | import java.io.{File, FileWriter} 6 | 7 | import chisel3.RawModule 8 | import chisel3.internal.firrtl.{Circuit, Port} 9 | 10 | import freechips.rocketchip.diplomacy.{ValName, AutoBundle} 11 | import freechips.rocketchip.devices.debug.DebugIO 12 | import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} 13 | import freechips.rocketchip.system.DefaultTestSuites._ 14 | import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} 15 | import freechips.rocketchip.config.Parameters 16 | import freechips.rocketchip.subsystem.RocketTilesKey 17 | import freechips.rocketchip.tile.XLen 18 | 19 | import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities} 20 | 21 | import scala.util.Try 22 | 23 | import chipyard.TestSuiteHelper 24 | 25 | trait HasTestSuites { 26 | def addTestSuites(targetName: String, params: Parameters) { 27 | TestSuiteHelper.addRocketTestSuites(params) 28 | TestSuiteHelper.addBoomTestSuites(params) 29 | TestSuiteHelper.addArianeTestSuites(params) 30 | TestGeneration.addSuite(FastBlockdevTests) 31 | TestGeneration.addSuite(SlowBlockdevTests) 32 | if (!targetName.contains("NoNIC")) 33 | TestGeneration.addSuite(NICLoopbackTests) 34 | 35 | import hwacha.HwachaTestSuites._ 36 | if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) { 37 | TestGeneration.addSuites(rv64uv.map(_("p"))) 38 | TestGeneration.addSuites(rv64uv.map(_("vp"))) 39 | TestGeneration.addSuite(rv64sv("p")) 40 | TestGeneration.addSuite(hwachaBmarks) 41 | } 42 | } 43 | } 44 | 45 | // Mixed into an App or into a TestSuite 46 | trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites { 47 | /** Output software test Makefrags, which provide targets for integration testing. */ 48 | def generateTestSuiteMakefrags { 49 | addTestSuites(names.topModuleClass, targetParams) 50 | writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites 51 | } 52 | 53 | // Output miscellaneous files produced as a side-effect of elaboration 54 | def generateArtefacts { 55 | ElaborationArtefacts.files.foreach { case (extension, contents) => 56 | writeOutputFile(s"${longName}.${extension}", contents ()) 57 | } 58 | } 59 | } 60 | 61 | object FireSimGenerator extends App with IsFireSimGeneratorLike { 62 | override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs 63 | lazy val generatorArgs = GeneratorArgs(args) 64 | lazy val genDir = new File(names.targetDir) 65 | // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 66 | // JsonProtocol to properly write out the annotations. Fix once the generated are unified 67 | elaborate 68 | generateTestSuiteMakefrags 69 | generateArtefacts 70 | } 71 | 72 | // For now, provide a separate generator app when not specifically building for FireSim 73 | object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites { 74 | override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs 75 | generateFirrtl 76 | generateAnno 77 | generateTestSuiteMakefrags 78 | generateArtefacts 79 | } 80 | -------------------------------------------------------------------------------- /generators/firechip/src/main/scala/TargetLandTestSuites.scala: -------------------------------------------------------------------------------- 1 | //See LICENSE for license details. 2 | package firesim.firesim 3 | 4 | import scala.collection.mutable.LinkedHashSet 5 | 6 | import freechips.rocketchip.system.{TestGeneration, RocketTestSuite} 7 | 8 | /* This imports tests from FireChip to test devices that aren't natively 9 | * tested by the riscv assembly tests. 10 | * Firesim's target-specific makefrag gives the recipes for building the 11 | * binaries. 12 | */ 13 | 14 | class BlockdevTestSuite(prefix: String, val names: LinkedHashSet[String]) extends RocketTestSuite { 15 | val envName = "" 16 | // fc_test_dir is is defined in firesim's Makefrag 17 | val dir = "$(fc_test_dir)" 18 | val makeTargetName = prefix + "-blkdev-tests" 19 | def kind = "blockdev" 20 | // Blockdev tests need an image, which complicates this 21 | def additionalArgs = "+blkdev-in-mem0=128 +nic-loopback0" 22 | override def toString = s"$makeTargetName = \\\n" + 23 | // Make variable with the binaries of the suite 24 | names.map(n => s"\t$n.riscv").mkString(" \\\n") + "\n\n" + 25 | // Variables with binary specific arguments 26 | names.map(n => s"$n.riscv_ARGS=$additionalArgs").mkString(" \n") + 27 | postScript 28 | } 29 | 30 | object FastBlockdevTests extends BlockdevTestSuite("fast", LinkedHashSet("blkdev")) 31 | object SlowBlockdevTests extends BlockdevTestSuite("slow", LinkedHashSet("big-blkdev")) 32 | 33 | class NICTestSuite(prefix: String, val names: LinkedHashSet[String]) extends RocketTestSuite { 34 | val envName = "" 35 | val dir = "$(fc_test_dir)" 36 | val makeTargetName = prefix + "-nic-tests" 37 | def kind = "nic" 38 | def additionalArgs = "+netbw0=100 +linklatency0=6405 +netburst0=8 +slotid=0 +nic-loopback0" 39 | override def toString = s"$makeTargetName = \\\n" + 40 | names.map(n => s"\t$n.riscv").mkString(" \\\n") + "\n\n" + 41 | names.map(n => s"$n.riscv_ARGS=$additionalArgs").mkString(" \n") + 42 | postScript 43 | } 44 | 45 | object NICLoopbackTests extends NICTestSuite("loopback", LinkedHashSet("nic-loopback")) 46 | -------------------------------------------------------------------------------- /generators/tracegen/src/main/scala/Configs.scala: -------------------------------------------------------------------------------- 1 | package tracegen 2 | 3 | import chisel3._ 4 | import chisel3.util.log2Ceil 5 | import freechips.rocketchip.config.{Config, Parameters} 6 | import freechips.rocketchip.groundtest.{TraceGenParams} 7 | import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey} 8 | import freechips.rocketchip.system.BaseConfig 9 | import freechips.rocketchip.rocket.DCacheParams 10 | import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 11 | import scala.math.{max, min} 12 | 13 | class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) 14 | extends Config((site, here, up) => { 15 | case TraceGenKey => params.map { dcp => TraceGenParams( 16 | dcache = Some(dcp), 17 | wordBits = site(XLen), 18 | addrBits = 48, 19 | addrBag = { 20 | val nSets = dcp.nSets 21 | val nWays = dcp.nWays 22 | val blockOffset = site(SystemBusKey).blockOffset 23 | val nBeats = min(2, site(SystemBusKey).blockBeats) 24 | val beatBytes = site(SystemBusKey).beatBytes 25 | List.tabulate(2 * nWays) { i => 26 | Seq.tabulate(nBeats) { j => 27 | BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) 28 | } 29 | }.flatten 30 | }, 31 | maxRequests = nReqs, 32 | memStart = site(ExtMem).get.master.base, 33 | numGens = params.size) 34 | } 35 | case MaxHartIdBits => log2Ceil(params.size + up(BoomTraceGenKey, site).length) max 1 36 | }) 37 | 38 | class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) 39 | extends Config((site, here, up) => { 40 | case BoomTraceGenKey => params.map { dcp => TraceGenParams( 41 | dcache = Some(dcp), 42 | wordBits = site(XLen), 43 | addrBits = 48, 44 | addrBag = { 45 | val nSets = dcp.nSets 46 | val nWays = dcp.nWays 47 | val blockOffset = site(SystemBusKey).blockOffset 48 | val nBeats = min(2, site(SystemBusKey).blockBeats) 49 | val beatBytes = site(SystemBusKey).beatBytes 50 | List.tabulate(2 * nWays) { i => 51 | Seq.tabulate(nBeats) { j => 52 | BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) 53 | } 54 | }.flatten 55 | }, 56 | maxRequests = nReqs, 57 | memStart = site(ExtMem).get.master.base, 58 | numGens = params.size) 59 | } 60 | case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1 61 | }) 62 | 63 | class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) 64 | extends Config((site, here, up) => { 65 | case TraceGenKey => params.map { dcp => TraceGenParams( 66 | dcache = Some(dcp), 67 | wordBits = site(XLen), 68 | addrBits = 48, 69 | addrBag = { 70 | val sbp = site(SystemBusKey) 71 | val l2p = site(InclusiveCacheKey) 72 | val nSets = max(l2p.sets, dcp.nSets) 73 | val nWays = max(l2p.ways, dcp.nWays) 74 | val blockOffset = sbp.blockOffset 75 | val nBeats = min(2, sbp.blockBeats) 76 | val beatBytes = sbp.beatBytes 77 | List.tabulate(2 * nWays) { i => 78 | Seq.tabulate(nBeats) { j => 79 | BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) 80 | } 81 | }.flatten 82 | }, 83 | maxRequests = nReqs, 84 | memStart = site(ExtMem).get.master.base, 85 | numGens = params.size) 86 | } 87 | case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size) 88 | }) 89 | 90 | -------------------------------------------------------------------------------- /generators/tracegen/src/main/scala/System.scala: -------------------------------------------------------------------------------- 1 | package tracegen 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.config.{Field, Parameters} 5 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} 6 | import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams} 7 | import freechips.rocketchip.subsystem._ 8 | 9 | case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil) 10 | case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil) 11 | 12 | trait HasTraceGenTiles { this: BaseSubsystem => 13 | val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) => 14 | LazyModule(new TraceGenTile(i, params, p)) 15 | } 16 | val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) => 17 | LazyModule(new BoomTraceGenTile(i, params, p)) 18 | } 19 | 20 | val tiles = rocket_tiles ++ boom_tiles 21 | 22 | tiles.foreach { t => 23 | sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode } 24 | } 25 | } 26 | 27 | trait HasTraceGenTilesModuleImp extends LazyModuleImp { 28 | val outer: HasTraceGenTiles 29 | val success = IO(Output(Bool())) 30 | 31 | outer.tiles.zipWithIndex.map { case(t, i) => 32 | t.module.constants.hartid := i.U 33 | } 34 | 35 | val status = DebugCombiner( 36 | outer.rocket_tiles.map(_.module.status) ++ 37 | outer.boom_tiles.map(_.module.status) 38 | ) 39 | success := status.finished 40 | } 41 | 42 | class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem 43 | with HasTraceGenTiles 44 | with HasHierarchicalBusTopology 45 | with CanHaveMasterAXI4MemPort { 46 | override lazy val module = new TraceGenSystemModuleImp(this) 47 | } 48 | 49 | class TraceGenSystemModuleImp(outer: TraceGenSystem) 50 | extends BaseSubsystemModuleImp(outer) 51 | with HasTraceGenTilesModuleImp 52 | with CanHaveMasterAXI4MemPortModuleImp 53 | -------------------------------------------------------------------------------- /generators/utilities/src/main/resources/bootrom: -------------------------------------------------------------------------------- 1 | ../../../../rocket-chip/bootrom -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.2.8 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) 2 | resolvers += Classpaths.sbtPluginReleases 3 | resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven" 4 | 5 | addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") 6 | addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") 7 | addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") 8 | addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0") 9 | addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") 10 | addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") 11 | addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") 12 | addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") 13 | addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") 14 | addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") 15 | addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") 16 | addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") 17 | 18 | libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" 19 | -------------------------------------------------------------------------------- /scripts/add-githooks.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # adds githooks, expects to be run from base directory 4 | 5 | git config core.hooksPath .githooks 6 | -------------------------------------------------------------------------------- /scripts/build-openocd.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # exit script if any command fails 4 | set -e 5 | set -o pipefail 6 | 7 | RDIR=$(git rev-parse --show-toplevel) 8 | 9 | if [ -z "${RISCV}" ] ; then 10 | ! [ -r "${RDIR}/env.sh" ] || . "${RDIR}/env.sh" 11 | if [ -z "${RISCV}" ] ; then 12 | echo "${0}: set the RISCV environment variable to desired install path" 13 | exit 1 14 | fi 15 | fi 16 | 17 | SRCDIR="${RDIR}/toolchains/riscv-tools" 18 | . "${RDIR}/scripts/build-util.sh" 19 | 20 | git config --unset submodule.toolchains/riscv-tools/riscv-openocd.update || : 21 | module_prepare riscv-openocd 22 | module_run riscv-openocd ./bootstrap 23 | module_build riscv-openocd --prefix="${RISCV}" \ 24 | --enable-remote-bitbang --enable-jtag_vpi --disable-werror 25 | -------------------------------------------------------------------------------- /scripts/build-util.sh: -------------------------------------------------------------------------------- 1 | # Derived from 2 | # https://github.com/riscv/riscv-tools/blob/master/build.common 3 | 4 | [ -n "${SRCDIR}" ] || exit 1 5 | 6 | # Scale number of parallel make jobs by hardware thread count 7 | ncpu="${NPROC:-$(getconf _NPROCESSORS_ONLN || # GNU 8 | getconf NPROCESSORS_ONLN || # *BSD, Solaris 9 | nproc --all || # Linux 10 | sysctl -n hw.ncpu || # *BSD, OS X 11 | :)}" 2>/dev/null 12 | case ${ncpu} in 13 | ''|*[!0-9]*) ;; # Ignore non-integer values 14 | *) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;; 15 | esac 16 | 17 | # Allow user to override MAKE 18 | [ -n "${MAKE}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make) 19 | readonly MAKE 20 | 21 | 22 | module_prepare() ( # [ignored-submodule..] 23 | set -e 24 | name=$1 25 | shift 26 | 27 | dir="${SRCDIR}/${name}" 28 | echo "=> Starting ${name} build" 29 | echo "==> Initializing ${name} submodule" 30 | if [ $# -gt 0 ] ; then 31 | git submodule update --init "${dir}" 32 | while [ -n "$1" ] ; do 33 | git -C "${dir}" config submodule."${1}".update none 34 | shift 35 | done 36 | fi 37 | git submodule update --init --recursive "${dir}" 38 | ) 39 | 40 | module_run() ( # 41 | set -e 42 | cd "${SRCDIR}/${1}" 43 | shift 44 | "$@" 45 | ) 46 | 47 | module_make() ( # 48 | set -e -o pipefail 49 | cd "${SRCDIR}/${1}/build" 50 | shift 51 | "${MAKE}" "$@" | tee "build-${1:-make}.log" 52 | ) 53 | 54 | module_build() ( # [configure-arg..] 55 | set -e -o pipefail 56 | name=$1 57 | shift 58 | 59 | cd "${SRCDIR}/${name}" 60 | 61 | if [ -e build ] ; then 62 | echo "==> Removing existing ${name}/build directory" 63 | rm -rf build 64 | fi 65 | if ! [ -e configure ] ; then 66 | echo "==> Updating autoconf files for ${name}" 67 | find . -iname configure.ac -type f -print0 | 68 | while read -r -d '' file ; do 69 | mkdir -p -- "${file%/*}/m4" 70 | done 71 | autoreconf -i 72 | fi 73 | 74 | mkdir -p build 75 | cd build 76 | { 77 | export PATH="${RISCV:+${RISCV}/bin:}${PATH}" 78 | echo "==> Configuring ${name}" 79 | ../configure "$@" 80 | echo "==> Building ${name}" 81 | "${MAKE}" 82 | echo "==> Installing ${name}" 83 | "${MAKE}" install 84 | } 2>&1 | tee build.log 85 | ) 86 | 87 | module_all() { # [configure-arg..] 88 | module_prepare "$1" 89 | module_build "$@" 90 | } 91 | -------------------------------------------------------------------------------- /scripts/centos-req.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | sudo yum groupinstall -y "Development tools" 6 | sudo yum install -y gmp-devel mpfr-devel libmpc-devel zlib-devel vim git java java-devel 7 | curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm.repo 8 | sudo yum install -y sbt texinfo gengetopt 9 | sudo yum install -y expat-devel libusb1-devel ncurses-devel cmake "perl(ExtUtils::MakeMaker)" 10 | # deps for poky 11 | sudo yum install -y python36 patch diffstat texi2html texinfo subversion chrpath git wget 12 | # deps for qemu 13 | sudo yum install -y gtk3-devel 14 | # deps for firemarshal 15 | sudo yum install -y python36-pip python36-devel rsync libguestfs-tools makeinfo expat ctags 16 | # Install GNU make 4.x (needed to cross-compile glibc 2.28+) 17 | sudo yum install -y centos-release-scl 18 | sudo yum install -y devtoolset-8-make 19 | # install DTC 20 | sudo yum install -y dtc 21 | 22 | # install verilator 23 | git clone http://git.veripool.org/git/verilator 24 | cd verilator 25 | git checkout v4.028 26 | autoconf && ./configure && make -j16 && sudo make install 27 | -------------------------------------------------------------------------------- /scripts/check-tracegen.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | SCRIPT_DIR=$(dirname $0) 6 | AXE_DIR=$(realpath ${SCRIPT_DIR}/../tools/axe) 7 | ROCKET_DIR=$(realpath ${SCRIPT_DIR}/../generators/rocket-chip) 8 | 9 | TO_AXE=${ROCKET_DIR}/scripts/toaxe.py 10 | AXE=${AXE_DIR}/src/axe 11 | AXE_SHRINK=${AXE_DIR}/src/axe-shrink.py 12 | 13 | PATH=$PATH:${AXE_DIR}/src 14 | 15 | grep '.*:.*#.*@' $1 > /tmp/clean-trace.txt 16 | "$TO_AXE" /tmp/clean-trace.txt > /tmp/trace.axe 17 | result=$("$AXE" check wmo /tmp/trace.axe) 18 | 19 | if [ "$result" != OK ]; then 20 | "$AXE_SHRINK" wmo /tmp/trace.axe 21 | else 22 | echo OK 23 | fi 24 | -------------------------------------------------------------------------------- /scripts/firesim-setup.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Sets up FireSim for use as a library within REBAR 4 | 5 | set -e 6 | set -o pipefail 7 | 8 | RDIR=$(pwd) 9 | scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]:-${(%):-%x}}" )" >/dev/null 2>&1 && pwd )" 10 | 11 | cd "${scripts_dir}/.." 12 | 13 | # Reenable the FireSim submodule 14 | git config --unset submodule.sims/firesim.update || true 15 | git submodule update --init sims/firesim 16 | cd sims/firesim 17 | ./build-setup.sh "$@" --library 18 | cd "$RDIR" 19 | -------------------------------------------------------------------------------- /scripts/gen-tags.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # run this script in the main Chipyard directory to generate ctags for all relevant repos 4 | # note: this requires exuberant-ctags 5 | # tested with: Exuberant Ctags 5.8 6 | # instructions: 7 | # cd /path/to/chipyard/ 8 | # ./scripts/gen-tags.sh 9 | # 10 | # input: 11 | # * nothing 12 | # 13 | # output: 14 | # * tags file in the directory that this was called in 15 | 16 | # ctags wrapper 17 | ctags -R --exclude=@.ctagsignore --links=no --languages=scala,C,C++,python 18 | -------------------------------------------------------------------------------- /scripts/init-submodules-no-riscv-tools-nolog.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # exit script if any command fails 4 | set -e 5 | set -o pipefail 6 | 7 | # Check that git version is at least 1.7.8 8 | MYGIT=$(git --version) 9 | MYGIT=${MYGIT#'git version '} # Strip prefix 10 | case ${MYGIT} in 11 | [1-9]*) ;; 12 | *) echo 'warning: unknown git version' ;; 13 | esac 14 | MINGIT="1.7.8" 15 | if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then 16 | echo "This script requires git version $MINGIT or greater. Exiting." 17 | false 18 | fi 19 | 20 | RDIR=$(git rev-parse --show-toplevel) 21 | 22 | # Ignore toolchain submodules 23 | cd "$RDIR" 24 | for name in toolchains/*-tools/*/ ; do 25 | git config submodule."${name%/}".update none 26 | done 27 | git config submodule.toolchains/libgloss.update none 28 | git config submodule.toolchains/qemu.update none 29 | 30 | # Don't automatically initialize generators with big submodules (e.g. linux source) 31 | git config submodule.generators/sha3.update none 32 | 33 | # Disable updates to the FireSim submodule until explicitly requested 34 | git config submodule.sims/firesim.update none 35 | # Disable updates to the hammer tool plugins repos 36 | git config submodule.vlsi/hammer-cadence-plugins.update none 37 | git config submodule.vlsi/hammer-synopsys-plugins.update none 38 | git config submodule.vlsi/hammer-mentor-plugins.update none 39 | git config submodule.software/firemarshal.update none 40 | git submodule update --init --recursive #--jobs 8 41 | 42 | # Un-ignore toolchain submodules 43 | for name in toolchains/*-tools/*/ ; do 44 | git config --unset submodule."${name%/}".update 45 | done 46 | git config --unset submodule.toolchains/libgloss.update 47 | git config --unset submodule.toolchains/qemu.update 48 | 49 | git config --unset submodule.vlsi/hammer-cadence-plugins.update 50 | git config --unset submodule.vlsi/hammer-synopsys-plugins.update 51 | git config --unset submodule.vlsi/hammer-mentor-plugins.update 52 | 53 | git config --unset submodule.generators/sha3.update 54 | git config --unset submodule.software/firemarshal.update 55 | 56 | # Non-recursive clone to exclude riscv-linux 57 | git submodule update --init generators/sha3 58 | 59 | git config --unset submodule.sims/firesim.update 60 | # Minimal non-recursive clone to initialize sbt dependencies 61 | git submodule update --init sims/firesim 62 | ( 63 | cd sims/firesim 64 | # Initialize dependencies for MIDAS-level RTL simulation 65 | git submodule update --init sim/midas 66 | ) 67 | git config submodule.sims/firesim.update none 68 | 69 | # Only shallow clone needed for basic SW tests 70 | git submodule update --init software/firemarshal 71 | 72 | # Configure firemarshal to know where our firesim installation is 73 | if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then 74 | echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml 75 | fi 76 | echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh 77 | -------------------------------------------------------------------------------- /scripts/init-submodules-no-riscv-tools.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # wrapper to log output from init-submodules script 4 | 5 | set -e 6 | set -o pipefail 7 | 8 | RDIR=$(git rev-parse --show-toplevel) 9 | cd "$RDIR" 10 | 11 | ./scripts/init-submodules-no-riscv-tools-nolog.sh "$@" 2>&1 | tee init-submodules-no-riscv-tools.log 12 | -------------------------------------------------------------------------------- /scripts/init-vlsi.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # exit script if any command fails 3 | set -e 4 | set -o pipefail 5 | 6 | # Initialize HAMMER and CAD-plugins 7 | git submodule update --init --recursive vlsi/hammer 8 | git submodule update --init --recursive vlsi/hammer-cadence-plugins 9 | git submodule update --init --recursive vlsi/hammer-synopsys-plugins 10 | git submodule update --init --recursive vlsi/hammer-mentor-plugins 11 | 12 | # Initialize HAMMER tech plugin 13 | if [[ $1 != *asap7* ]]; then 14 | git submodule update --init --recursive vlsi/hammer-$1-plugin 15 | fi 16 | -------------------------------------------------------------------------------- /scripts/tutorial-patches/RocketConfigs.scala.patch: -------------------------------------------------------------------------------- 1 | diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala 2 | index bc1dab6..1d84129 100644 3 | --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala 4 | +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala 5 | @@ -293,7 +293,7 @@ class Sha3RocketConfig extends Config( 6 | new chipyard.config.WithBootROM ++ 7 | new chipyard.config.WithUART ++ 8 | new chipyard.config.WithL2TLBs(1024) ++ 9 | - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator 10 | +// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator 11 | new freechips.rocketchip.subsystem.WithNoMMIOPort ++ 12 | new freechips.rocketchip.subsystem.WithNoSlavePort ++ 13 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 14 | -------------------------------------------------------------------------------- /scripts/tutorial-patches/build.sbt.patch: -------------------------------------------------------------------------------- 1 | diff --git a/build.sbt b/build.sbt 2 | index a633066..3df8b74 100644 3 | --- a/build.sbt 4 | +++ b/build.sbt 5 | @@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) 6 | 7 | lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) 8 | .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, 9 | - sha3, // On separate line to allow for cleaner tutorial-setup patches 10 | +// sha3, // On separate line to allow for cleaner tutorial-setup patches 11 | gemmini, icenet, tracegen, ariane) 12 | .settings(commonSettings) 13 | 14 | @@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane")) 15 | .dependsOn(rocketchip) 16 | .settings(commonSettings) 17 | 18 | -lazy val sha3 = (project in file("generators/sha3")) 19 | - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) 20 | - .settings(commonSettings) 21 | +//lazy val sha3 = (project in file("generators/sha3")) 22 | +// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) 23 | +// .settings(commonSettings) 24 | 25 | lazy val gemmini = (project in file("generators/gemmini")) 26 | .dependsOn(rocketchip, chisel_testers, testchipip) 27 | -------------------------------------------------------------------------------- /scripts/tutorial-setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e -x 4 | 5 | rm -rf generators/sha3 6 | 7 | for p in scripts/tutorial-patches/*.patch 8 | do 9 | echo "Applying tutorial patch $p" 10 | git apply $p 11 | done 12 | -------------------------------------------------------------------------------- /scripts/ubuntu-req.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | sudo apt-get install -y build-essential bison flex 6 | sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre 7 | # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html 8 | echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list 9 | curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add 10 | sudo apt-get update 11 | sudo apt-get install -y sbt 12 | sudo apt-get install -y texinfo gengetopt 13 | sudo apt-get install -y libexpat1-dev libusb-dev libncurses5-dev cmake 14 | # deps for poky 15 | sudo apt-get install -y python3.6 patch diffstat texi2html texinfo subversion chrpath git wget 16 | # deps for qemu 17 | sudo apt-get install -y libgtk-3-dev 18 | # deps for firemarshal 19 | sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat ctags 20 | # install DTC 21 | sudo apt-get install -y device-tree-compiler 22 | 23 | # install verilator 24 | git clone http://git.veripool.org/git/verilator 25 | cd verilator 26 | git checkout v4.028 27 | autoconf && ./configure && make -j16 && sudo make install 28 | -------------------------------------------------------------------------------- /sims/vcs/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | !Makefile 4 | !dramsim2_ini 5 | -------------------------------------------------------------------------------- /sims/vcs/Makefile: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | # vcs makefile 3 | ######################################################################################### 4 | 5 | ######################################################################################### 6 | # general path variables 7 | ######################################################################################### 8 | base_dir=$(abspath ../..) 9 | sim_dir=$(abspath .) 10 | 11 | ######################################################################################### 12 | # include shared variables 13 | ######################################################################################### 14 | include $(base_dir)/variables.mk 15 | 16 | ######################################################################################### 17 | # name of simulator (used to generate *.f arguments file) 18 | ######################################################################################### 19 | sim_name = vcs 20 | 21 | ######################################################################################### 22 | # vcs simulator types and rules 23 | ######################################################################################### 24 | sim_prefix = simv 25 | sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) 26 | sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug 27 | 28 | PERMISSIVE_ON=+permissive 29 | PERMISSIVE_OFF=+permissive-off 30 | 31 | WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd 32 | 33 | .PHONY: default debug 34 | default: $(sim) 35 | debug: $(sim_debug) 36 | 37 | ######################################################################################### 38 | # import other necessary rules and variables 39 | ######################################################################################### 40 | include $(base_dir)/common.mk 41 | 42 | ######################################################################################### 43 | # vcs binary and arguments 44 | ######################################################################################### 45 | VCS = vcs -full64 46 | 47 | VCS_CC_OPTS = \ 48 | -CC "-I$(VCS_HOME)/include" \ 49 | -CC "-I$(RISCV)/include" \ 50 | -CC "-I$(dramsim_dir)" \ 51 | -CC "-std=c++11" \ 52 | $(dramsim_lib) \ 53 | $(RISCV)/lib/libfesvr.a 54 | 55 | VCS_NONCC_OPTS = \ 56 | +lint=all,noVCDE,noONGS,noUI \ 57 | -error=PCWM-L \ 58 | -timescale=1ns/10ps \ 59 | -quiet \ 60 | -q \ 61 | +rad \ 62 | +v2k \ 63 | +vcs+lic+wait \ 64 | +vc+list \ 65 | -error=noZMMCM \ 66 | -assert svaext \ 67 | -sverilog \ 68 | +libext+.v \ 69 | +incdir+$(build_dir) \ 70 | -f $(sim_common_files) \ 71 | $(sim_vsrcs) 72 | 73 | VCS_DEFINES = \ 74 | +define+VCS \ 75 | +define+CLOCK_PERIOD=1.0 \ 76 | +define+PRINTF_COND=$(TB).printf_cond \ 77 | +define+STOP_COND=!$(TB).reset \ 78 | +define+RANDOMIZE_MEM_INIT \ 79 | +define+RANDOMIZE_REG_INIT \ 80 | +define+RANDOMIZE_GARBAGE_ASSIGN \ 81 | +define+RANDOMIZE_INVALID_ASSIGN 82 | 83 | VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) 84 | 85 | ######################################################################################### 86 | # vcs simulator rules 87 | ######################################################################################### 88 | $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) 89 | rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ 90 | -debug_pp 91 | 92 | $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) 93 | rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ 94 | +define+DEBUG \ 95 | -debug_pp 96 | 97 | ######################################################################################### 98 | # create a vcs vpd rule 99 | ######################################################################################### 100 | .PRECIOUS: $(output_dir)/%.vpd %.vpd 101 | $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) 102 | (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) 103 | 104 | ######################################################################################### 105 | # general cleanup rule 106 | ######################################################################################### 107 | .PHONY: clean 108 | clean: 109 | rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h 110 | -------------------------------------------------------------------------------- /sims/vcs/dramsim2_ini: -------------------------------------------------------------------------------- 1 | ../../generators/testchipip/src/main/resources/dramsim2_ini -------------------------------------------------------------------------------- /sims/verilator/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | !Makefile 4 | !verilator.mk 5 | !dramsim2_ini 6 | -------------------------------------------------------------------------------- /sims/verilator/dramsim2_ini: -------------------------------------------------------------------------------- 1 | ../../generators/testchipip/src/main/resources/dramsim2_ini -------------------------------------------------------------------------------- /tests/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.riscv 3 | *.dump 4 | libgloss/ 5 | -------------------------------------------------------------------------------- /tests/Makefile: -------------------------------------------------------------------------------- 1 | GCC=riscv64-unknown-elf-gcc 2 | OBJDUMP=riscv64-unknown-elf-objdump 3 | CFLAGS= -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall 4 | LDFLAGS= -static 5 | 6 | include libgloss.mk 7 | 8 | PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd 9 | 10 | .DEFAULT_GOAL := default 11 | 12 | .PHONY: default 13 | default: $(addsuffix .riscv,$(PROGRAMS)) 14 | 15 | .PHONY: dumps 16 | dumps: $(addsuffix .dump,$(PROGRAMS)) 17 | 18 | %.o: %.S 19 | $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ 20 | 21 | %.o: %.c mmio.h 22 | $(GCC) $(CFLAGS) -c $< -o $@ 23 | 24 | %.riscv: %.o $(libgloss) 25 | $(GCC) $(LDFLAGS) $< -o $@ 26 | 27 | %.dump: %.riscv 28 | $(OBJDUMP) -D $< > $@ 29 | 30 | 31 | .PHONY: clean 32 | clean: 33 | rm -f *.riscv *.o *.dump 34 | $(if $(libgloss),rm -rf $(libgloss_builddir)/) 35 | -------------------------------------------------------------------------------- /tests/accum.c: -------------------------------------------------------------------------------- 1 | #include "rocc.h" 2 | 3 | static inline void accum_write(int idx, unsigned long data) 4 | { 5 | ROCC_INSTRUCTION_SS(0, data, idx, 0); 6 | } 7 | 8 | static inline unsigned long accum_read(int idx) 9 | { 10 | unsigned long value; 11 | ROCC_INSTRUCTION_DSS(0, value, 0, idx, 1); 12 | return value; 13 | } 14 | 15 | static inline void accum_load(int idx, void *ptr) 16 | { 17 | asm volatile ("fence"); 18 | ROCC_INSTRUCTION_SS(0, (uintptr_t) ptr, idx, 2); 19 | } 20 | 21 | static inline void accum_add(int idx, unsigned long addend) 22 | { 23 | ROCC_INSTRUCTION_SS(0, addend, idx, 3); 24 | } 25 | 26 | unsigned long data = 0x3421L; 27 | 28 | int main(void) 29 | { 30 | unsigned long result; 31 | 32 | accum_load(0, &data); 33 | accum_add(0, 2); 34 | result = accum_read(0); 35 | 36 | if (result != data + 2) 37 | return 1; 38 | 39 | accum_write(0, 3); 40 | accum_add(0, 1); 41 | result = accum_read(0); 42 | 43 | if (result != 4) 44 | return 2; 45 | 46 | return 0; 47 | } 48 | -------------------------------------------------------------------------------- /tests/big-blkdev.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "mmio.h" 5 | #include "blkdev.h" 6 | 7 | #define SECTOR_WORDS (BLKDEV_SECTOR_SIZE / sizeof(uint64_t)) 8 | #define TEST_SECTORS 16 9 | 10 | unsigned long sector_buf[SECTOR_WORDS]; 11 | 12 | void write_sector(unsigned int secnum) 13 | { 14 | int req_tag, resp_tag; 15 | 16 | for (int i = 0; i < SECTOR_WORDS; i++) 17 | sector_buf[i] = (secnum << 6) | i; 18 | 19 | while (reg_read8(BLKDEV_NREQUEST) == 0); 20 | req_tag = blkdev_send_request((unsigned long) sector_buf, secnum, 1, 1); 21 | while (reg_read8(BLKDEV_NCOMPLETE) == 0); 22 | resp_tag = reg_read8(BLKDEV_COMPLETE); 23 | 24 | if (req_tag != resp_tag) { 25 | printf("Response tag %d does not match request tag %d\n", 26 | req_tag, resp_tag); 27 | exit(EXIT_FAILURE); 28 | } 29 | } 30 | 31 | void check_sector(unsigned int secnum) 32 | { 33 | int req_tag, resp_tag; 34 | 35 | while (reg_read8(BLKDEV_NREQUEST) == 0); 36 | req_tag = blkdev_send_request((unsigned long) sector_buf, secnum, 1, 0); 37 | while (reg_read8(BLKDEV_NCOMPLETE) == 0); 38 | resp_tag = reg_read8(BLKDEV_COMPLETE); 39 | 40 | if (req_tag != resp_tag) { 41 | printf("Response tag %d does not match request tag %d\n", 42 | req_tag, resp_tag); 43 | exit(EXIT_FAILURE); 44 | } 45 | 46 | for (int i = 0; i < SECTOR_WORDS; i++) { 47 | unsigned long expected = (secnum << 6) | i; 48 | unsigned long actual = sector_buf[i]; 49 | if (actual != expected) { 50 | printf("Word %d in sector %x does not match expected\n", 51 | i, secnum); 52 | printf("Expected %lx, got %lx\n", 53 | expected, actual); 54 | exit(EXIT_FAILURE); 55 | } 56 | } 57 | } 58 | 59 | int main(void) 60 | { 61 | unsigned int nsectors = blkdev_nsectors(); 62 | unsigned int stride = nsectors / TEST_SECTORS; 63 | 64 | printf("Writing %u of %u sectors\n", TEST_SECTORS, nsectors); 65 | 66 | for (int i = 0; i < TEST_SECTORS; i++) { 67 | int sector = i * stride; 68 | write_sector(sector); 69 | } 70 | 71 | printf("Checking sectors\n", nsectors); 72 | 73 | for (int i = 0; i < TEST_SECTORS; i++) { 74 | int sector = i * stride; 75 | check_sector(sector); 76 | } 77 | 78 | return 0; 79 | } 80 | -------------------------------------------------------------------------------- /tests/blkdev.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "mmio.h" 5 | #include "blkdev.h" 6 | 7 | void blkdev_read(void *addr, unsigned long offset, size_t nsectors) 8 | { 9 | int req_tag, resp_tag, ntags, i; 10 | size_t nsectors_per_tag; 11 | 12 | ntags = reg_read8(BLKDEV_NREQUEST); 13 | nsectors_per_tag = nsectors / ntags; 14 | 15 | printf("sending %d reads\n", ntags); 16 | 17 | for (i = 0; i < ntags; i++) { 18 | req_tag = blkdev_send_request( 19 | (unsigned long) addr, offset, 20 | nsectors_per_tag, 0); 21 | addr += (nsectors_per_tag << BLKDEV_SECTOR_SHIFT); 22 | offset += nsectors_per_tag; 23 | } 24 | 25 | while (reg_read8(BLKDEV_NCOMPLETE) < ntags); 26 | 27 | for (i = 0; i < ntags; i++) { 28 | resp_tag = reg_read8(BLKDEV_COMPLETE); 29 | printf("completed read %d\n", resp_tag); 30 | } 31 | } 32 | 33 | void blkdev_write(unsigned long offset, void *addr, size_t nsectors) 34 | { 35 | int req_tag, resp_tag, ntags, i; 36 | size_t nsectors_per_tag; 37 | 38 | ntags = reg_read8(BLKDEV_NREQUEST); 39 | nsectors_per_tag = nsectors / ntags; 40 | 41 | printf("sending %d writes\n", ntags); 42 | 43 | for (i = 0; i < ntags; i++) { 44 | req_tag = blkdev_send_request( 45 | (unsigned long) addr, offset, 46 | nsectors_per_tag, 1); 47 | addr += (nsectors_per_tag << BLKDEV_SECTOR_SHIFT); 48 | offset += nsectors_per_tag; 49 | } 50 | 51 | while (reg_read8(BLKDEV_NCOMPLETE) < ntags); 52 | 53 | for (i = 0; i < ntags; i++) { 54 | resp_tag = reg_read8(BLKDEV_COMPLETE); 55 | printf("completed write %d\n", resp_tag); 56 | } 57 | } 58 | 59 | #define TEST_NSECTORS 4 60 | #define TEST_SIZE (TEST_NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int)) 61 | 62 | unsigned int test_data[TEST_SIZE]; 63 | unsigned int res_data[TEST_SIZE]; 64 | 65 | int main(void) 66 | { 67 | unsigned int nsectors = blkdev_nsectors(); 68 | unsigned int max_req_len = blkdev_max_req_len(); 69 | 70 | if (nsectors < TEST_NSECTORS) { 71 | printf("Error: blkdev nsectors not large enough: %u < %u\n", 72 | nsectors, TEST_NSECTORS); 73 | return 1; 74 | } 75 | 76 | if (max_req_len < TEST_NSECTORS) { 77 | printf("Error: blkdev max_req_len not large enough: %u < %u\n", 78 | max_req_len, TEST_NSECTORS); 79 | return 1; 80 | } 81 | 82 | printf("blkdev: %u sectors %u max request length\n", 83 | nsectors, max_req_len); 84 | 85 | for (int i = 0; i < TEST_SIZE; i++) { 86 | test_data[i] = i << 8; 87 | } 88 | 89 | asm volatile ("fence"); 90 | 91 | blkdev_write(0, (void *) test_data, TEST_NSECTORS); 92 | blkdev_read((void *) res_data, 0, TEST_NSECTORS); 93 | 94 | for (int i = 0; i < TEST_SIZE; i++) { 95 | if (test_data[i] != res_data[i]) { 96 | printf("data mismatch at %d: %x != %x\n", 97 | i, test_data[i], res_data[i]); 98 | return 1; 99 | } 100 | } 101 | 102 | printf("All correct\n"); 103 | 104 | return 0; 105 | } 106 | -------------------------------------------------------------------------------- /tests/blkdev.h: -------------------------------------------------------------------------------- 1 | #define BLKDEV_BASE 0x10015000 2 | #define BLKDEV_ADDR BLKDEV_BASE 3 | #define BLKDEV_OFFSET (BLKDEV_BASE + 8) 4 | #define BLKDEV_LEN (BLKDEV_BASE + 12) 5 | #define BLKDEV_WRITE (BLKDEV_BASE + 16) 6 | #define BLKDEV_REQUEST (BLKDEV_BASE + 17) 7 | #define BLKDEV_NREQUEST (BLKDEV_BASE + 18) 8 | #define BLKDEV_COMPLETE (BLKDEV_BASE + 19) 9 | #define BLKDEV_NCOMPLETE (BLKDEV_BASE + 20) 10 | #define BLKDEV_NSECTORS (BLKDEV_BASE + 24) 11 | #define BLKDEV_MAX_REQUEST_LENGTH (BLKDEV_BASE + 28) 12 | #define BLKDEV_SECTOR_SIZE 512 13 | #define BLKDEV_SECTOR_SHIFT 9 14 | 15 | static inline size_t blkdev_nsectors(void) 16 | { 17 | return reg_read32(BLKDEV_NSECTORS); 18 | } 19 | 20 | static inline size_t blkdev_max_req_len(void) 21 | { 22 | return reg_read32(BLKDEV_MAX_REQUEST_LENGTH); 23 | } 24 | 25 | static inline unsigned int blkdev_send_request( 26 | unsigned long addr, 27 | unsigned int offset, 28 | unsigned int len, 29 | unsigned char write) 30 | { 31 | reg_write64(BLKDEV_ADDR, addr); 32 | reg_write32(BLKDEV_OFFSET, offset); 33 | reg_write32(BLKDEV_LEN, len); 34 | reg_write8(BLKDEV_WRITE, write); 35 | 36 | asm volatile ("fence"); 37 | return reg_read8(BLKDEV_REQUEST); 38 | } 39 | -------------------------------------------------------------------------------- /tests/charcount.c: -------------------------------------------------------------------------------- 1 | #include "rocc.h" 2 | 3 | char string[64] = "The quick brown fox jumped over the lazy dog"; 4 | 5 | static inline unsigned long count_chars(char *start, char needle) 6 | { 7 | unsigned long count; 8 | asm volatile ("fence"); 9 | ROCC_INSTRUCTION_DSS(2, count, start, needle, 0); 10 | return count; 11 | } 12 | 13 | int main(void) 14 | { 15 | unsigned long count = count_chars(string + 14, 'o'); 16 | if (count != 3) 17 | return count + 1; 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /tests/gcd.c: -------------------------------------------------------------------------------- 1 | #include "mmio.h" 2 | 3 | #define GCD_STATUS 0x2000 4 | #define GCD_X 0x2004 5 | #define GCD_Y 0x2008 6 | #define GCD_GCD 0x200C 7 | 8 | unsigned int gcd_ref(unsigned int x, unsigned int y) { 9 | while (y != 0) { 10 | if (x > y) 11 | x = x - y; 12 | else 13 | y = y - x; 14 | } 15 | return x; 16 | } 17 | 18 | // DOC include start: GCD test 19 | int main(void) 20 | { 21 | uint32_t result, ref, x = 20, y = 15; 22 | 23 | // wait for peripheral to be ready 24 | while ((reg_read8(GCD_STATUS) & 0x2) == 0) ; 25 | 26 | reg_write32(GCD_X, x); 27 | reg_write32(GCD_Y, y); 28 | 29 | 30 | // wait for peripheral to complete 31 | while ((reg_read8(GCD_STATUS) & 0x1) == 0) ; 32 | 33 | result = reg_read32(GCD_GCD); 34 | ref = gcd_ref(x, y); 35 | 36 | if (result != ref) { 37 | printf("Hardware result %d does not match reference value %d\n", result, ref); 38 | return 1; 39 | } 40 | return 0; 41 | } 42 | // DOC include end: GCD test 43 | -------------------------------------------------------------------------------- /tests/htif.ld: -------------------------------------------------------------------------------- 1 | ../toolchains/libgloss/util/htif.ld -------------------------------------------------------------------------------- /tests/libgloss.mk: -------------------------------------------------------------------------------- 1 | # Handle libgloss-htif dependency 2 | ifndef libgloss 3 | 4 | ifndef GCC 5 | $(error GCC is not defined) 6 | endif 7 | 8 | libgloss_specs := htif_nano.specs 9 | 10 | # Test whether libgloss-htif is globally installed and usable 11 | # Define BUILD_LIBGLOSS=1 to unconditionally force a local build 12 | BUILD_LIBGLOSS ?= $(shell { echo 'int main(void) { return 0; }' | \ 13 | $(GCC) -xc -specs=$(libgloss_specs) -o /dev/null - 2> /dev/null ; } || \ 14 | echo "$$?") 15 | 16 | ifneq ($(BUILD_LIBGLOSS),) 17 | $(info libgloss-htif: Using local build) 18 | 19 | libgloss_srcdir := ../toolchains/libgloss 20 | libgloss_builddir := libgloss 21 | libgloss_specs := $(libgloss_srcdir)/util/$(libgloss_specs) 22 | libgloss_lib := $(libgloss_builddir)/libgloss_htif.a 23 | libgloss := $(libgloss_lib) $(libgloss_specs) htif.ld 24 | 25 | LDFLAGS += -L libgloss 26 | 27 | $(libgloss_builddir)/Makefile: $(libgloss_srcdir)/configure 28 | mkdir -p $(dir $@) 29 | cd $(dir $@) && $(realpath $<) \ 30 | --prefix=$(shell $(GCC) -print-sysroot) \ 31 | --host=$(TARGET) \ 32 | --disable-multilib 33 | 34 | $(libgloss_lib): $(libgloss_builddir)/Makefile 35 | $(MAKE) -C $(dir $^) 36 | 37 | .PHONY: libgloss 38 | libgloss: $(libgloss) 39 | 40 | else 41 | 42 | $(info libgloss-htif: Using global install) 43 | libgloss := # No additional prerequisites 44 | 45 | endif 46 | 47 | CFLAGS += -specs=$(libgloss_specs) 48 | LDFLAGS += -specs=$(libgloss_specs) 49 | 50 | endif # libgloss 51 | -------------------------------------------------------------------------------- /tests/mmio.h: -------------------------------------------------------------------------------- 1 | #ifndef __MMIO_H__ 2 | #define __MMIO_H__ 3 | 4 | #include 5 | 6 | static inline void reg_write8(uintptr_t addr, uint8_t data) 7 | { 8 | volatile uint8_t *ptr = (volatile uint8_t *) addr; 9 | *ptr = data; 10 | } 11 | 12 | static inline uint8_t reg_read8(uintptr_t addr) 13 | { 14 | volatile uint8_t *ptr = (volatile uint8_t *) addr; 15 | return *ptr; 16 | } 17 | 18 | static inline void reg_write16(uintptr_t addr, uint16_t data) 19 | { 20 | volatile uint16_t *ptr = (volatile uint16_t *) addr; 21 | *ptr = data; 22 | } 23 | 24 | static inline uint16_t reg_read16(uintptr_t addr) 25 | { 26 | volatile uint16_t *ptr = (volatile uint16_t *) addr; 27 | return *ptr; 28 | } 29 | 30 | static inline void reg_write32(uintptr_t addr, uint32_t data) 31 | { 32 | volatile uint32_t *ptr = (volatile uint32_t *) addr; 33 | *ptr = data; 34 | } 35 | 36 | static inline uint32_t reg_read32(uintptr_t addr) 37 | { 38 | volatile uint32_t *ptr = (volatile uint32_t *) addr; 39 | return *ptr; 40 | } 41 | 42 | static inline void reg_write64(unsigned long addr, uint64_t data) 43 | { 44 | volatile uint64_t *ptr = (volatile uint64_t *) addr; 45 | *ptr = data; 46 | } 47 | 48 | static inline uint64_t reg_read64(unsigned long addr) 49 | { 50 | volatile uint64_t *ptr = (volatile uint64_t *) addr; 51 | return *ptr; 52 | } 53 | 54 | #endif 55 | -------------------------------------------------------------------------------- /tests/nic-loopback.c: -------------------------------------------------------------------------------- 1 | #include "mmio.h" 2 | #include 3 | #include 4 | #include 5 | 6 | #include 7 | #include "nic.h" 8 | 9 | #define NPACKETS 10 10 | #define TEST_OFFSET 3 11 | #define TEST_LEN 356 12 | #define ARRAY_LEN 360 13 | #define NTRIALS 3 14 | 15 | uint32_t src[NPACKETS][ARRAY_LEN]; 16 | uint32_t dst[NPACKETS][ARRAY_LEN]; 17 | uint64_t lengths[NPACKETS]; 18 | 19 | static inline void send_recv() 20 | { 21 | uint64_t send_packet, recv_addr; 22 | int ncomps, send_comps_left = NPACKETS, recv_comps_left = NPACKETS; 23 | int recv_idx = 0; 24 | 25 | for (int i = 0; i < NPACKETS; i++) { 26 | uint64_t pkt_size = TEST_LEN * sizeof(uint32_t); 27 | uint64_t src_addr = (uint64_t) &src[i][TEST_OFFSET]; 28 | send_packet = (pkt_size << 48) | src_addr; 29 | recv_addr = (uint64_t) dst[i]; 30 | reg_write64(SIMPLENIC_SEND_REQ, send_packet); 31 | reg_write64(SIMPLENIC_RECV_REQ, recv_addr); 32 | } 33 | 34 | while (send_comps_left > 0 || recv_comps_left > 0) { 35 | ncomps = nic_send_comp_avail(); 36 | asm volatile ("fence"); 37 | for (int i = 0; i < ncomps; i++) 38 | reg_read16(SIMPLENIC_SEND_COMP); 39 | send_comps_left -= ncomps; 40 | 41 | ncomps = nic_recv_comp_avail(); 42 | asm volatile ("fence"); 43 | for (int i = 0; i < ncomps; i++) { 44 | lengths[recv_idx] = reg_read16(SIMPLENIC_RECV_COMP); 45 | recv_idx++; 46 | } 47 | recv_comps_left -= ncomps; 48 | } 49 | } 50 | 51 | void run_test(void) 52 | { 53 | unsigned long start, end; 54 | int i, j; 55 | 56 | memset(dst, 0, sizeof(dst)); 57 | asm volatile ("fence"); 58 | 59 | start = rdcycle(); 60 | send_recv(); 61 | end = rdcycle(); 62 | 63 | printf("send/recv %lu cycles\n", end - start); 64 | 65 | for (i = 0; i < NPACKETS; i++) { 66 | if (lengths[i] != TEST_LEN * sizeof(uint32_t)) { 67 | printf("recv got wrong # bytes\n"); 68 | exit(EXIT_FAILURE); 69 | } 70 | 71 | for (j = 0; j < TEST_LEN; j++) { 72 | if (dst[i][j] != src[i][j + TEST_OFFSET]) { 73 | printf("Data mismatch @ %d, %d: %x != %x\n", 74 | i, j, dst[i][j], src[i][j + TEST_OFFSET]); 75 | exit(EXIT_FAILURE); 76 | } 77 | } 78 | } 79 | } 80 | 81 | int main(void) 82 | { 83 | int i, j; 84 | 85 | for (i = 0; i < NPACKETS; i++) { 86 | for (j = 0; j < ARRAY_LEN; j++) 87 | src[i][j] = i * ARRAY_LEN + j; 88 | } 89 | 90 | for (i = 0; i < NTRIALS; i++) { 91 | printf("Trial %d\n", i); 92 | run_test(); 93 | } 94 | 95 | printf("All correct\n"); 96 | 97 | return 0; 98 | } 99 | -------------------------------------------------------------------------------- /tests/nic.h: -------------------------------------------------------------------------------- 1 | #define SIMPLENIC_BASE 0x10016000L 2 | #define SIMPLENIC_SEND_REQ (SIMPLENIC_BASE + 0) 3 | #define SIMPLENIC_RECV_REQ (SIMPLENIC_BASE + 8) 4 | #define SIMPLENIC_SEND_COMP (SIMPLENIC_BASE + 16) 5 | #define SIMPLENIC_RECV_COMP (SIMPLENIC_BASE + 18) 6 | #define SIMPLENIC_COUNTS (SIMPLENIC_BASE + 20) 7 | #define SIMPLENIC_MACADDR (SIMPLENIC_BASE + 24) 8 | 9 | static inline int nic_send_req_avail(void) 10 | { 11 | return reg_read32(SIMPLENIC_COUNTS) & 0xff; 12 | } 13 | 14 | static inline int nic_recv_req_avail(void) 15 | { 16 | return (reg_read32(SIMPLENIC_COUNTS) >> 8) & 0xff; 17 | } 18 | 19 | static inline int nic_send_comp_avail(void) 20 | { 21 | return (reg_read32(SIMPLENIC_COUNTS) >> 16) & 0xff; 22 | } 23 | 24 | static inline int nic_recv_comp_avail(void) 25 | { 26 | return (reg_read32(SIMPLENIC_COUNTS) >> 24) & 0xff; 27 | } 28 | 29 | static void nic_send(void *data, unsigned long len) 30 | { 31 | uintptr_t addr = ((uintptr_t) data) & ((1L << 48) - 1); 32 | unsigned long packet = (len << 48) | addr; 33 | 34 | while (nic_send_req_avail() == 0); 35 | reg_write64(SIMPLENIC_SEND_REQ, packet); 36 | 37 | while (nic_send_comp_avail() == 0); 38 | reg_read16(SIMPLENIC_SEND_COMP); 39 | } 40 | 41 | static int nic_recv(void *dest) 42 | { 43 | uintptr_t addr = (uintptr_t) dest; 44 | int len; 45 | 46 | while (nic_recv_req_avail() == 0); 47 | reg_write64(SIMPLENIC_RECV_REQ, addr); 48 | 49 | // Poll for completion 50 | while (nic_recv_comp_avail() == 0); 51 | len = reg_read16(SIMPLENIC_RECV_COMP); 52 | asm volatile ("fence"); 53 | 54 | return len; 55 | } 56 | 57 | static inline uint64_t nic_macaddr(void) 58 | { 59 | return reg_read64(SIMPLENIC_MACADDR); 60 | } 61 | -------------------------------------------------------------------------------- /tests/pwm.c: -------------------------------------------------------------------------------- 1 | #define PWM_PERIOD 0x2000 2 | #define PWM_DUTY 0x2004 3 | #define PWM_ENABLE 0x2008 4 | 5 | #include "mmio.h" 6 | 7 | int main(void) 8 | { 9 | reg_write32(PWM_PERIOD, 20); 10 | reg_write32(PWM_DUTY, 5); 11 | reg_write32(PWM_ENABLE, 1); 12 | 13 | return 0; 14 | } 15 | -------------------------------------------------------------------------------- /vlsi/.gitignore: -------------------------------------------------------------------------------- 1 | inputs.yml 2 | __pycache__ 3 | hammer*.log 4 | build 5 | src/test/output-*.json 6 | generated-src -------------------------------------------------------------------------------- /vlsi/env.yml: -------------------------------------------------------------------------------- 1 | # Base path to where Mentor tools are installed 2 | mentor.mentor_home: "" 3 | # Mentor license server/file 4 | mentor.MGLS_LICENSE_FILE: "" 5 | # Base path to where Cadence tools are installed 6 | cadence.cadence_home: "" 7 | # Cadence license server/file 8 | cadence.CDS_LIC_FILE: "" 9 | # Base path to where Synopsys tools are installed 10 | synopsys.synopsys_home: "" 11 | # Synopsys license server/files 12 | synopsys.SNPSLMD_LICENSE_FILE: "" 13 | synopsys.MGLS_LICENSE_FILE: "" 14 | -------------------------------------------------------------------------------- /vlsi/example-vlsi: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | 4 | import hammer_vlsi 5 | from hammer_vlsi import CLIDriver, HammerToolHookAction 6 | 7 | from typing import Dict, Callable, Optional, List 8 | 9 | def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: 10 | x.append(''' 11 | # TODO 12 | # Place custom TCL here 13 | ''') 14 | return True 15 | 16 | def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: 17 | x.append(''' 18 | # TODO 19 | # Place custom TCL here 20 | ''') 21 | return True 22 | 23 | def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: 24 | x.append(''' 25 | # TODO 26 | # Place custom TCL here 27 | set_db route_design_bottom_routing_layer 2 28 | set_db route_design_top_routing_layer 7 29 | ''') 30 | return True 31 | 32 | def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: 33 | """ 34 | Scale the final GDS by a factor of 4 35 | hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script 36 | """ 37 | x.append(''' 38 | # Write script out to a temporary file and execute it 39 | set fp [open "{script_file}" "w"] 40 | puts -nonewline $fp "{script_text}" 41 | close $fp 42 | 43 | # Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python 44 | set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"] 45 | python3 {script_file} 46 | '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) 47 | return True 48 | 49 | 50 | class ExampleDriver(CLIDriver): 51 | def get_extra_par_hooks(self) -> List[HammerToolHookAction]: 52 | extra_hooks = [ 53 | 54 | # Default set of steps can be found in the CAD tool plugin's __init__.py 55 | 56 | # make_pre_insertion_hook will execute the custom hook before the specified step 57 | # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) 58 | # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), 59 | 60 | # make_post_insertion_hook will execute the custom hook after the specified step 61 | hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), 62 | 63 | # make_replacement_hook will replace the specified step with a custom hook 64 | # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), 65 | 66 | # make_removal_hook will remove the specified step from the flow 67 | hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), 68 | 69 | # The target step in any of the above calls may be a default step or another one of your custom hooks 70 | 71 | # This is an example of a technology-supplied hook 72 | hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds) 73 | ] 74 | return extra_hooks 75 | 76 | if __name__ == '__main__': 77 | ExampleDriver().main() 78 | -------------------------------------------------------------------------------- /vlsi/example.v: -------------------------------------------------------------------------------- 1 | // Sha3Accel w/ a blackbox (a dummy DCO) included inside 2 | 3 | module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] 4 | input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4] 5 | input reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4] 6 | output io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 7 | input io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 8 | input [6:0] io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 9 | input [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 10 | input [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 11 | input io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 12 | output io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 13 | output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 14 | output [7:0] io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 15 | output [4:0] io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 16 | output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 17 | input io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 18 | input [7:0] io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 19 | input [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 20 | output io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] 21 | input [13:0] col_sel_b, 22 | input [15:0] row_sel_b, 23 | input [7:0] code_regulator, 24 | input dither, 25 | input sleep_b, 26 | output dco_clock 27 | ); 28 | Sha3Accel sha3 ( 29 | .clock(clock), 30 | .reset(reset), 31 | .io_cmd_ready(io_cmd_ready), 32 | .io_cmd_valid(io_cmd_valid), 33 | .io_cmd_bits_inst_funct(io_cmd_bits_inst_funct), 34 | .io_cmd_bits_rs1(io_cmd_bits_rs1), 35 | .io_cmd_bits_rs2(io_cmd_bits_rs2), 36 | .io_mem_req_ready(io_mem_req_ready), 37 | .io_mem_req_valid(io_mem_req_valid), 38 | .io_mem_req_bits_addr(io_mem_req_bits_addr), 39 | .io_mem_req_bits_tag(io_mem_req_bits_tag), 40 | .io_mem_req_bits_cmd(io_mem_req_bits_cmd), 41 | .io_mem_req_bits_data(io_mem_req_bits_data), 42 | .io_mem_resp_valid(io_mem_resp_valid), 43 | .io_mem_resp_bits_tag(io_mem_resp_bits_tag), 44 | .io_mem_resp_bits_data(io_mem_resp_bits_data), 45 | .io_busy(io_busy) 46 | ); 47 | ExampleDCO dco ( 48 | .col_sel_b(col_sel_b), 49 | .row_sel_b(row_sel_b), 50 | .code_regulator(code_regulator), 51 | .dither(dither), 52 | .sleep_b(sleep_b), 53 | .clock(dco_clock) 54 | ); 55 | endmodule 56 | 57 | module ExampleDCO ( 58 | input [13:0] col_sel_b, 59 | input [15:0] row_sel_b, 60 | input [7:0] code_regulator, 61 | input dither, 62 | input sleep_b, 63 | output clock 64 | ); 65 | endmodule 66 | -------------------------------------------------------------------------------- /vlsi/extra_libraries/example/ExampleDCO.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/l-nic/chipyard/2c0928cb9c7c7f56f2d362c0a57d05561a872fa9/vlsi/extra_libraries/example/ExampleDCO.gds -------------------------------------------------------------------------------- /vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib: -------------------------------------------------------------------------------- 1 | library (ExampleDCO_PVT_0P63V_100C) { 2 | technology (cmos); 3 | date : "Mon Sep 2 16:01:59 2019"; 4 | comment : "Generated by dotlibber.py"; 5 | revision : 0; 6 | delay_model : table_lookup; 7 | simulation : true; 8 | capacitive_load_unit (1,pf); 9 | voltage_unit : "1V"; 10 | current_unit : "1mA"; 11 | time_unit : "1ns"; 12 | pulling_resistance_unit : "1kohm"; 13 | nom_process : 1; 14 | nom_temperature : 100; 15 | nom_voltage : 0.630000; 16 | voltage_map(VDD, 0.630000); 17 | voltage_map(VSS, 0.000000); 18 | operating_conditions("PVT_0P63V_100C") { 19 | process : 1; 20 | temperature : 100; 21 | voltage : 0.630000; 22 | } 23 | default_operating_conditions : PVT_0P63V_100C; 24 | lu_table_template (constraint_template_3x3) { 25 | variable_1 : related_pin_transition; 26 | variable_2 : constrained_pin_transition; 27 | index_1 ("0.0002, 0.0004, 0.0006"); 28 | index_2 ("0.0002, 0.0004, 0.0006"); 29 | } 30 | lu_table_template (delay_template_8x8) { 31 | variable_1 : input_net_transition; 32 | variable_2 : total_output_net_capacitance; 33 | index_1 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008"); 34 | index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088"); 35 | } 36 | 37 | 38 | type (bus_13_to_0) { 39 | base_type : array ; 40 | data_type : bit ; 41 | bit_width : 14 ; 42 | bit_from : 13 ; 43 | bit_to : 0 ; 44 | downto : true ; 45 | } 46 | 47 | 48 | type (bus_15_to_0) { 49 | base_type : array ; 50 | data_type : bit ; 51 | bit_width : 16 ; 52 | bit_from : 15 ; 53 | bit_to : 0 ; 54 | downto : true ; 55 | } 56 | 57 | 58 | type (bus_7_to_0) { 59 | base_type : array ; 60 | data_type : bit ; 61 | bit_width : 8 ; 62 | bit_from : 7 ; 63 | bit_to : 0 ; 64 | downto : true ; 65 | } 66 | cell (ExampleDCO) { 67 | dont_use : true; 68 | dont_touch : true; 69 | is_macro_cell : true; 70 | 71 | pg_pin (VDD) { 72 | pg_type : primary_power; 73 | voltage_name : VDD; 74 | } 75 | 76 | pg_pin (VSS) { 77 | pg_type : primary_ground; 78 | voltage_name : VSS; 79 | } 80 | 81 | pin (clock) { 82 | direction : output; 83 | clock : true; 84 | max_capacitance : 0.02; 85 | related_power_pin : VDD; 86 | related_ground_pin : VSS; 87 | } 88 | 89 | bus ( col_sel_b ) { 90 | bus_type : bus_13_to_0; 91 | direction : input; 92 | capacitance : 0.006; 93 | max_transition : 0.04; 94 | 95 | pin ( col_sel_b[13:0] ) { 96 | related_power_pin : VDD; 97 | related_ground_pin : VSS; 98 | } 99 | } 100 | 101 | bus ( row_sel_b ) { 102 | bus_type : bus_15_to_0; 103 | direction : input; 104 | capacitance : 0.006; 105 | max_transition : 0.04; 106 | 107 | pin ( row_sel_b[15:0] ) { 108 | related_power_pin : VDD; 109 | related_ground_pin : VSS; 110 | } 111 | } 112 | 113 | bus ( code_regulator ) { 114 | bus_type : bus_7_to_0; 115 | direction : input; 116 | capacitance : 0.006; 117 | max_transition : 0.04; 118 | 119 | pin ( code_regulator[7:0] ) { 120 | related_power_pin : VDD; 121 | related_ground_pin : VSS; 122 | } 123 | } 124 | 125 | pin (dither) { 126 | direction : input; 127 | capacitance : 0.006; 128 | max_transition : 0.04; 129 | related_power_pin : VDD; 130 | related_ground_pin : VSS; 131 | } 132 | 133 | pin (sleep_b) { 134 | direction : input; 135 | capacitance : 0.006; 136 | max_transition : 0.04; 137 | related_power_pin : VDD; 138 | related_ground_pin : VSS; 139 | } 140 | } 141 | 142 | } 143 | -------------------------------------------------------------------------------- /vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib: -------------------------------------------------------------------------------- 1 | library (ExampleDCO_PVT_0P77V_0C) { 2 | technology (cmos); 3 | date : "Mon Sep 2 16:01:59 2019"; 4 | comment : "Generated by dotlibber.py"; 5 | revision : 0; 6 | delay_model : table_lookup; 7 | simulation : true; 8 | capacitive_load_unit (1,pf); 9 | voltage_unit : "1V"; 10 | current_unit : "1mA"; 11 | time_unit : "1ns"; 12 | pulling_resistance_unit : "1kohm"; 13 | nom_process : 1; 14 | nom_temperature : 0; 15 | nom_voltage : 0.770000; 16 | voltage_map(VDD, 0.770000); 17 | voltage_map(VSS, 0.000000); 18 | operating_conditions("PVT_0P77V_0C") { 19 | process : 1; 20 | temperature : 0; 21 | voltage : 0.770000; 22 | } 23 | default_operating_conditions : PVT_0P77V_0C; 24 | lu_table_template (constraint_template_3x3) { 25 | variable_1 : related_pin_transition; 26 | variable_2 : constrained_pin_transition; 27 | index_1 ("0.0001, 0.0002, 0.0003"); 28 | index_2 ("0.0001, 0.0002, 0.0003"); 29 | } 30 | lu_table_template (delay_template_8x8) { 31 | variable_1 : input_net_transition; 32 | variable_2 : total_output_net_capacitance; 33 | index_1 ("0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001"); 34 | index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088"); 35 | } 36 | 37 | 38 | type (bus_13_to_0) { 39 | base_type : array ; 40 | data_type : bit ; 41 | bit_width : 14 ; 42 | bit_from : 13 ; 43 | bit_to : 0 ; 44 | downto : true ; 45 | } 46 | 47 | 48 | type (bus_15_to_0) { 49 | base_type : array ; 50 | data_type : bit ; 51 | bit_width : 16 ; 52 | bit_from : 15 ; 53 | bit_to : 0 ; 54 | downto : true ; 55 | } 56 | 57 | 58 | type (bus_7_to_0) { 59 | base_type : array ; 60 | data_type : bit ; 61 | bit_width : 8 ; 62 | bit_from : 7 ; 63 | bit_to : 0 ; 64 | downto : true ; 65 | } 66 | cell (ExampleDCO) { 67 | dont_use : true; 68 | dont_touch : true; 69 | is_macro_cell : true; 70 | 71 | pg_pin (VDD) { 72 | pg_type : primary_power; 73 | voltage_name : VDD; 74 | } 75 | 76 | pg_pin (VSS) { 77 | pg_type : primary_ground; 78 | voltage_name : VSS; 79 | } 80 | 81 | pin (clock) { 82 | direction : output; 83 | clock : true; 84 | max_capacitance : 0.02; 85 | related_power_pin : VDD; 86 | related_ground_pin : VSS; 87 | } 88 | 89 | bus ( col_sel_b ) { 90 | bus_type : bus_13_to_0; 91 | direction : input; 92 | capacitance : 0.006; 93 | max_transition : 0.04; 94 | 95 | pin ( col_sel_b[13:0] ) { 96 | related_power_pin : VDD; 97 | related_ground_pin : VSS; 98 | } 99 | } 100 | 101 | bus ( row_sel_b ) { 102 | bus_type : bus_15_to_0; 103 | direction : input; 104 | capacitance : 0.006; 105 | max_transition : 0.04; 106 | 107 | pin ( row_sel_b[15:0] ) { 108 | related_power_pin : VDD; 109 | related_ground_pin : VSS; 110 | } 111 | } 112 | 113 | bus ( code_regulator ) { 114 | bus_type : bus_7_to_0; 115 | direction : input; 116 | capacitance : 0.006; 117 | max_transition : 0.04; 118 | 119 | pin ( code_regulator[7:0] ) { 120 | related_power_pin : VDD; 121 | related_ground_pin : VSS; 122 | } 123 | } 124 | 125 | pin (dither) { 126 | direction : input; 127 | capacitance : 0.006; 128 | max_transition : 0.04; 129 | related_power_pin : VDD; 130 | related_ground_pin : VSS; 131 | } 132 | 133 | pin (sleep_b) { 134 | direction : input; 135 | capacitance : 0.006; 136 | max_transition : 0.04; 137 | related_power_pin : VDD; 138 | related_ground_pin : VSS; 139 | } 140 | } 141 | 142 | } 143 | -------------------------------------------------------------------------------- /vlsi/view_gds.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | try: 4 | import gdspy 5 | except ImportError: 6 | print('Bad gdspy installation!') 7 | sys.exit() 8 | 9 | print('Loading GDS...') 10 | gds_lib = gdspy.GdsLibrary().read_gds(infile=str(sys.argv[1]), units='import') 11 | 12 | # Comment to show layer 13 | hidden=[ 14 | (1, 0), #well 15 | (1, 251), #well lbl 16 | (2, 0), #fin 17 | (3, 0), #psub 18 | (3, 251), #psub lbl 19 | (7, 0), #gate 20 | (8, 0), #dummy 21 | (10, 0), #gate cut 22 | (11, 0), #active 23 | (12, 0), #nselect 24 | (13, 0), #pselect 25 | (16, 0), #LIG 26 | (17, 0), #LISD 27 | (18, 0), #V0 28 | (19, 0), #M1 29 | (19, 251), #M1 lbl 30 | (21, 0), #V1 31 | #(20, 0), #M2 32 | (20, 251), #M2 lbl 33 | #(25, 0), #V2 34 | #(30, 0), #M3 35 | (30, 251), #M3 lbl 36 | #(35, 0), #V3 37 | #(40, 0), #M4 38 | (40, 251), #M4 lbl 39 | (45, 0), #V4 40 | (50, 0), #M5 41 | (50, 251), #M5 lbl 42 | (55, 0), #V5 43 | (60, 0), #M6 44 | (60, 251), #M6 lbl 45 | (65, 0), #V6 46 | (70, 0), #M7 47 | (70, 251), #M7 lbl 48 | (75, 0), #V7 49 | (80, 0), #M8 50 | (80, 251), #M8 lbl 51 | (85, 0), #V8 52 | (88, 0), #SDT 53 | (90, 0), #M9 54 | (90, 251), #M9 lbl 55 | (95, 0), #V9 56 | (96, 0), #Pad 57 | (97, 0), #SLVT 58 | (98, 0), #LVT 59 | (99, 0), #SRAMDRC 60 | (100, 0), #??? 61 | (101, 0), #??? 62 | (110, 0) #SRAMVT 63 | ] 64 | 65 | print('Opening layout...') 66 | gdspy.LayoutViewer(gds_lib, hidden_types=hidden, depth=1) 67 | --------------------------------------------------------------------------------