├── .gitignore ├── adder └── install_apio.bat ├── blinky ├── apio.ini ├── install_apio.bat ├── install_apio.sh ├── pins.pcf ├── top.v └── top_tb.v ├── brainfuck ├── apio.ini ├── assemble.py ├── brainfuck.v ├── brainfuck_tb.v ├── hello.bf ├── hello.hex ├── hello2.hex ├── helloshort.bf ├── install_apio.bat ├── install_apio.sh ├── pins.pcf ├── program.hex ├── simpleuart.v └── test1.hex ├── hello_world ├── apio.ini ├── install_apio.bat ├── install_apio.sh ├── pins.pcf ├── simpleuart.v └── top.v ├── hex7seg ├── PushButton_Debouncer.v ├── apio.ini ├── decoder_7_seg_hex.v ├── display_7_seg_hex.v ├── pins.pcf └── top.v ├── nunchuk ├── I2C_master.v ├── PushButton_Debouncer.v ├── apio.ini ├── decoder_7_seg_hex.v ├── display_7_seg_hex.v ├── pins.pcf └── top.v ├── pong ├── apio.ini ├── hvsync_generator.v ├── install_apio.bat ├── install_apio.sh ├── pins.pcf └── top.v ├── shiftout ├── apio.ini ├── pins.pcf └── top.v ├── tone ├── apio.ini ├── install_apio.bat ├── install_apio.sh ├── pins.pcf ├── tone.v └── top.v └── uart_test ├── apio.ini ├── install_apio.bat ├── install_apio.sh ├── pins.pcf ├── simpleuart.v └── top.v /.gitignore: -------------------------------------------------------------------------------- 1 | **/*.out 2 | **/*.vcd 3 | **/*.dblite 4 | **/*.bin 5 | **/*.asc 6 | **/*.blif 7 | **/*.history 8 | 9 | -------------------------------------------------------------------------------- /adder/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /blinky/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /blinky/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /blinky/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /blinky/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io -nowarn PIN_1 A2 42 | set_io -nowarn PIN_2 A1 43 | set_io -nowarn PIN_3 B1 44 | set_io -nowarn PIN_4 C2 45 | set_io -nowarn PIN_5 C1 46 | set_io -nowarn PIN_6 D2 47 | set_io -nowarn PIN_7 D1 48 | set_io -nowarn PIN_8 E2 49 | set_io -nowarn PIN_9 E1 50 | set_io -nowarn PIN_10 G2 51 | set_io -nowarn PIN_11 H1 52 | set_io -nowarn PIN_12 J1 53 | set_io -nowarn PIN_13 H2 54 | 55 | # Right side of board 56 | set_io -nowarn PIN_14 H9 57 | set_io -nowarn PIN_15 D9 58 | set_io -nowarn PIN_16 D8 59 | set_io -nowarn PIN_17 C9 60 | set_io -nowarn PIN_18 A9 61 | set_io -nowarn PIN_19 B8 62 | set_io -nowarn PIN_20 A8 63 | set_io -nowarn PIN_21 B7 64 | set_io -nowarn PIN_22 A7 65 | set_io -nowarn PIN_23 B6 66 | set_io -nowarn PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io -nowarn SPI_SS F7 70 | set_io -nowarn SPI_SCK G7 71 | set_io -nowarn SPI_IO0 G6 72 | set_io -nowarn SPI_IO1 H7 73 | set_io -nowarn SPI_IO2 H4 74 | set_io -nowarn SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io -nowarn PIN_25 G1 78 | set_io -nowarn PIN_26 J3 79 | set_io -nowarn PIN_27 J4 80 | set_io -nowarn PIN_28 G9 81 | set_io -nowarn PIN_29 J9 82 | set_io -nowarn PIN_30 E8 83 | set_io -nowarn PIN_31 J2 84 | 85 | # LED 86 | set_io -nowarn LED B3 87 | 88 | # USB 89 | set_io -nowarn USBP B4 90 | set_io -nowarn USBN A4 91 | set_io -nowarn USBPU A3 92 | 93 | # 16MHz clock 94 | set_io -nowarn CLK B2 # input 95 | -------------------------------------------------------------------------------- /blinky/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | output LED, // User/boot LED next to power LED 5 | output USBPU // USB pull-up resistor 6 | ); 7 | // drive USB pull-up resistor to '0' to disable USB 8 | assign USBPU = 0; 9 | 10 | //////// 11 | // make a simple blink circuit 12 | //////// 13 | 14 | // keep track of time and location in blink_pattern 15 | reg [25:0] blink_counter = 0; 16 | 17 | // pattern that will be flashed over the LED over time 18 | wire [31:0] blink_pattern = 32'b101010001110111011100010101; 19 | 20 | // increment the blink_counter every clock 21 | always @(posedge CLK) begin 22 | blink_counter <= blink_counter + 1; 23 | end 24 | 25 | // light up the LED according to the pattern 26 | assign LED = blink_pattern[blink_counter[25:21]]; 27 | endmodule 28 | -------------------------------------------------------------------------------- /blinky/top_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module tb (); 3 | initial begin 4 | $dumpfile("top_tb.vcd"); 5 | $dumpvars(0, t); 6 | end 7 | 8 | reg clk; 9 | wire led, usbpu; 10 | 11 | initial begin 12 | clk = 1'b0; 13 | end 14 | 15 | always begin 16 | #31 clk = !clk; 17 | end 18 | 19 | initial begin 20 | repeat(16000000) @(posedge clk); 21 | 22 | $finish; 23 | end 24 | 25 | top t (.CLK(clk), .LED(led), .USBPU(usbpu)); 26 | 27 | endmodule // tb 28 | -------------------------------------------------------------------------------- /brainfuck/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /brainfuck/assemble.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import string 3 | 4 | def assemble(ifile, ofile): 5 | with open(ifile) as i, open(ofile, "w", encoding="latin-1") as o: 6 | while True: 7 | c = i.read(1) 8 | if not c: 9 | break 10 | if c not in string.whitespace : 11 | o.write("{0:02x}".format(ord(c)) + '\n') 12 | o.write("ff\n") 13 | 14 | assemble("hello.bf", "hello.hex") 15 | -------------------------------------------------------------------------------- /brainfuck/brainfuck.v: -------------------------------------------------------------------------------- 1 | module brainfuck( 2 | input clk, 3 | output PIN_1, 4 | input PIN_2, 5 | output LED, 6 | output USBPU 7 | ); 8 | 9 | // program state data 10 | wire [7:0] i, d; 11 | 12 | reg [10:0] ptr = 0; 13 | reg [10:0] pc = 0; 14 | reg [3:0] state = WELCOME; 15 | reg [3:0] depth = 0; 16 | 17 | // Extra optional output 18 | reg print_program = 0; 19 | reg print_welcome = 0; 20 | reg print_code = 0; 21 | 22 | // Disable USB 23 | assign USBPU = 0; 24 | 25 | // Set LED when halted 26 | assign LED = state == HALTED; 27 | 28 | // uart control 29 | reg [7:0] reg_dat_di; 30 | wire [7:0] reg_dat_do; 31 | reg reg_dat_re, reg_dat_we; 32 | wire reg_dat_wait; 33 | 34 | // states 35 | localparam WELCOME=0, PRINT_PROGRAM=1, STARTING = 2, 36 | EXECUTING = 3, SKIPPING_FORWARDS=4, 37 | SKIPPING_BACKWARDS = 5, WAITING_FOR_INPUT = 6, 38 | WAITING_FOR_OUTPUT = 7, HALTED = 8; 39 | 40 | // Wire up new program state 41 | wire [10:0] new_ptr = (state == EXECUTING && (i == "<")) ? ptr-1 : 42 | (state == EXECUTING && (i == ">")) ? ptr+1 : 43 | ptr; 44 | 45 | wire [7:0] new_d = (state == EXECUTING && i == "+") ? d+1 : 46 | (state == EXECUTING && i == "-") ? d-1 : 47 | d; 48 | 49 | wire [10:0] new_pc = (state == PRINT_PROGRAM || state == STARTING) ? pc : 50 | (state == SKIPPING_BACKWARDS && (i != "[" || depth > 0)) ? pc-1 : 51 | (state == EXECUTING && i == "]" && d > 0) ? pc-1 : 52 | pc+1; 53 | 54 | // Generate reset signal 55 | reg [5:0] reset_cnt = 0; 56 | wire resetn = &reset_cnt; 57 | 58 | always @(posedge clk) begin 59 | reset_cnt <= reset_cnt + !resetn; 60 | end 61 | 62 | // Create the welcome message 63 | reg [7:0] text [0:9]; 64 | reg [3:0] char_count; 65 | 66 | initial begin 67 | text[0] <= "B"; 68 | text[1] <= "r"; 69 | text[2] <= "a"; 70 | text[3] <= "i"; 71 | text[4] <= "n"; 72 | text[5] <= "f"; 73 | text[6] <= "u"; 74 | text[7] <= "c"; 75 | text[8] <= "k"; 76 | text[9] <= ":"; 77 | end 78 | 79 | // More control of uart 80 | reg wait_for_send = 0; 81 | 82 | // Print the welcome message 83 | always @(posedge clk) begin 84 | if (resetn && state == WELCOME) begin 85 | if (print_welcome) begin 86 | if (!wait_for_send) begin 87 | if (char_count == 10) state <= PRINT_PROGRAM; 88 | else begin 89 | char_count <= char_count + 1; 90 | reg_dat_we <= 1; 91 | end 92 | reg_dat_di <= text[char_count]; 93 | wait_for_send <= 1; 94 | end else if (!reg_dat_wait) begin 95 | reg_dat_we <= 0; 96 | wait_for_send <= 0; 97 | end 98 | end else state <= PRINT_PROGRAM; 99 | end 100 | 101 | // Print the program 102 | if (state == PRINT_PROGRAM) begin 103 | if (print_program) begin 104 | if (!wait_for_send) begin 105 | if (i == 8'hff) begin // end of program 106 | pc <= 0; 107 | ptr <= 0; 108 | state <= STARTING; 109 | end else begin 110 | reg_dat_we <= 1; 111 | reg_dat_di <= i; 112 | wait_for_send <= 1; 113 | pc <= pc + 1; 114 | end 115 | end else if (!reg_dat_wait) begin 116 | reg_dat_we <= 0; 117 | wait_for_send <= 0; 118 | end 119 | end else begin 120 | state <= STARTING; 121 | end 122 | end 123 | 124 | if (state == STARTING) begin 125 | state <= EXECUTING; 126 | if (print_code) begin 127 | reg_dat_we <= 1; 128 | reg_dat_di <= i; 129 | wait_for_send <= 1; 130 | end 131 | end 132 | 133 | if (state == HALTED && !reg_dat_wait) begin 134 | reg_dat_we <= 0; 135 | wait_for_send <= 0; 136 | end 137 | 138 | // Print the executing program 139 | if ( state >= EXECUTING && state < HALTED) begin 140 | if (!wait_for_send) begin 141 | // Initiate print of instruction 142 | if (i != 8'hff && print_code) begin 143 | reg_dat_we <= 1; 144 | reg_dat_di <= i; 145 | wait_for_send <= 1; 146 | end 147 | 148 | // Execute the program 149 | if (state <= SKIPPING_BACKWARDS) begin 150 | pc <= new_pc; 151 | ptr <= new_ptr; 152 | end 153 | 154 | // State machine 155 | case (state) 156 | SKIPPING_FORWARDS: 157 | begin 158 | if (i == "[") depth <= depth + 1; 159 | else if (i == "]") begin 160 | if (depth == 0) state <= EXECUTING; 161 | else depth <= depth - 1; 162 | end 163 | end 164 | SKIPPING_BACKWARDS: 165 | begin 166 | if (i == "]") depth <= depth + 1; 167 | else if (i == "[") begin 168 | if (depth == 0) state <= EXECUTING; 169 | else depth <= depth -1; 170 | end 171 | end 172 | EXECUTING: 173 | begin 174 | if (i == 8'hff) begin 175 | state <= HALTED; 176 | ptr <= 0; 177 | pc <= 0; 178 | end else if (i == "[" && d == 0) begin 179 | depth <= 0; 180 | state <= SKIPPING_FORWARDS; 181 | end else if (i == "]" && d > 0) begin 182 | depth <= 0; 183 | state <= SKIPPING_BACKWARDS; 184 | end else if (i == ".") begin 185 | state <= WAITING_FOR_OUTPUT; 186 | reg_dat_we <= 1; 187 | reg_dat_di <= d; 188 | wait_for_send <= 1; 189 | end else if (i == ",") begin 190 | state <= WAITING_FOR_INPUT; 191 | reg_dat_re <= 1; 192 | end 193 | end 194 | WAITING_FOR_OUTPUT: 195 | if (!reg_dat_wait) begin 196 | state <= EXECUTING; 197 | reg_dat_we <= 0; 198 | wait_for_send <= 0; 199 | end 200 | WAITING_FOR_INPUT: 201 | state <= EXECUTING; 202 | endcase 203 | end else if (!reg_dat_wait) begin 204 | reg_dat_we <= 0; 205 | wait_for_send <= 0; 206 | end 207 | end 208 | end 209 | 210 | // Program code 211 | rom code (.clk(clk), .pc(new_pc), 212 | .en(state >= PRINT_PROGRAM && state <= SKIPPING_BACKWARDS), .i(i)); 213 | 214 | // RAM 215 | ram data (.clk(clk), .p_in(ptr), .d_in(new_d), 216 | .en(state >= STARTING && state <= SKIPPING_BACKWARDS), 217 | .we(state >= EXECUTING && state <= SKIPPING_BACKWARDS), 218 | .p_out(new_ptr), .d_out(d)); 219 | 220 | // uart from picosoc 221 | simpleuart uart ( 222 | .clk (clk), 223 | .resetn (resetn), 224 | 225 | .ser_tx (PIN_1), 226 | .ser_rx (PIN_2), 227 | 228 | .cfg_divider(139), // 115200 baud 229 | .reg_dat_we (reg_dat_we), 230 | .reg_dat_re (reg_dat_re), 231 | .reg_dat_di (reg_dat_di), 232 | .reg_dat_do (reg_dat_do), 233 | .reg_dat_wait(reg_dat_wait) 234 | ); 235 | 236 | endmodule 237 | 238 | module rom( 239 | input clk, 240 | input [10:0] pc, 241 | input en, 242 | output reg [7:0] i 243 | ); 244 | 245 | reg [7:0] code [0:2047]; 246 | 247 | initial $readmemh("program.hex", code); 248 | 249 | always @(posedge clk) if (en) begin 250 | i <= code[pc]; 251 | end 252 | endmodule 253 | 254 | module ram( 255 | input clk, 256 | input [10:0] p_in, 257 | input [10:0] p_out, 258 | input en, 259 | input we, 260 | input [7:0] d_in, 261 | output reg [7:0] d_out 262 | ); 263 | 264 | reg [7:0] mem [0:2047]; 265 | 266 | always @(posedge clk) if (en) begin 267 | if (we) mem[p_in] <= d_in; 268 | d_out <= mem[p_out]; 269 | end 270 | endmodule 271 | -------------------------------------------------------------------------------- /brainfuck/brainfuck_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module tb (); 3 | initial begin 4 | $dumpfile("brainfuck_tb.vcd"); 5 | $dumpvars(0, bf); 6 | end 7 | 8 | reg clk; 9 | wire led, usbpu, pin1, pin2; 10 | 11 | initial begin 12 | clk = 1'b0; 13 | end 14 | 15 | always begin 16 | #31 clk = !clk; 17 | end 18 | 19 | initial begin 20 | repeat(100000) @(posedge clk); 21 | 22 | $finish; 23 | end 24 | 25 | brainfuck bf (.clk(clk), .PIN_1(pin1), .PIN_2(pin2), .LED(led), .USBPU(usbpu)); 26 | 27 | endmodule // tb 28 | -------------------------------------------------------------------------------- /brainfuck/hello.bf: -------------------------------------------------------------------------------- 1 | [ This program prints "Hello World!" and a newline to the screen, its 2 | length is 106 active command characters. [It is not the shortest.] 3 | 4 | This loop is an "initial comment loop", a simple way of adding a comment 5 | to a BF program such that you don't have to worry about any command 6 | characters. Any ".", ",", "+", "-", "<" and ">" characters are simply 7 | ignored, the "[" and "]" characters just have to be balanced. This 8 | loop and the commands it contains are ignored because the current cell 9 | defaults to a value of 0; the 0 value causes this loop to be skipped. 10 | ] 11 | ++++++++ Set Cell #0 to 8 12 | [ 13 | >++++ Add 4 to Cell #1; this will always set Cell #1 to 4 14 | [ as the cell will be cleared by the loop 15 | >++ Add 2 to Cell #2 16 | >+++ Add 3 to Cell #3 17 | >+++ Add 3 to Cell #4 18 | >+ Add 1 to Cell #5 19 | <<<<- Decrement the loop counter in Cell #1 20 | ] Loop till Cell #1 is zero; number of iterations is 4 21 | >+ Add 1 to Cell #2 22 | >+ Add 1 to Cell #3 23 | >- Subtract 1 from Cell #4 24 | >>+ Add 1 to Cell #6 25 | [<] Move back to the first zero cell you find; this will 26 | be Cell #1 which was cleared by the previous loop 27 | <- Decrement the loop Counter in Cell #0 28 | ] Loop till Cell #0 is zero; number of iterations is 8 29 | 30 | The result of this is: 31 | Cell No : 0 1 2 3 4 5 6 32 | Contents: 0 0 72 104 88 32 8 33 | Pointer : ^ 34 | 35 | >>. Cell #2 has value 72 which is 'H' 36 | >---. Subtract 3 from Cell #3 to get 101 which is 'e' 37 | +++++++..+++. Likewise for 'llo' from Cell #3 38 | >>. Cell #5 is 32 for the space 39 | <-. Subtract 1 from Cell #4 for 87 to give a 'W' 40 | <. Cell #3 was set to 'o' from the end of 'Hello' 41 | +++.------.--------. Cell #3 for 'rl' and 'd' 42 | >>+. Add 1 to Cell #5 gives us an exclamation point 43 | >++. And finally a newline from Cell #6 44 | -------------------------------------------------------------------------------- /brainfuck/hello.hex: -------------------------------------------------------------------------------- 1 | 5b 2 | 54 3 | 68 4 | 69 5 | 73 6 | 70 7 | 72 8 | 6f 9 | 67 10 | 72 11 | 61 12 | 6d 13 | 70 14 | 72 15 | 69 16 | 6e 17 | 74 18 | 73 19 | 22 20 | 48 21 | 65 22 | 6c 23 | 6c 24 | 6f 25 | 57 26 | 6f 27 | 72 28 | 6c 29 | 64 30 | 21 31 | 22 32 | 61 33 | 6e 34 | 64 35 | 61 36 | 6e 37 | 65 38 | 77 39 | 6c 40 | 69 41 | 6e 42 | 65 43 | 74 44 | 6f 45 | 74 46 | 68 47 | 65 48 | 73 49 | 63 50 | 72 51 | 65 52 | 65 53 | 6e 54 | 2c 55 | 69 56 | 74 57 | 73 58 | 6c 59 | 65 60 | 6e 61 | 67 62 | 74 63 | 68 64 | 69 65 | 73 66 | 31 67 | 30 68 | 36 69 | 61 70 | 63 71 | 74 72 | 69 73 | 76 74 | 65 75 | 63 76 | 6f 77 | 6d 78 | 6d 79 | 61 80 | 6e 81 | 64 82 | 63 83 | 68 84 | 61 85 | 72 86 | 61 87 | 63 88 | 74 89 | 65 90 | 72 91 | 73 92 | 2e 93 | 5b 94 | 49 95 | 74 96 | 69 97 | 73 98 | 6e 99 | 6f 100 | 74 101 | 74 102 | 68 103 | 65 104 | 73 105 | 68 106 | 6f 107 | 72 108 | 74 109 | 65 110 | 73 111 | 74 112 | 2e 113 | 5d 114 | 54 115 | 68 116 | 69 117 | 73 118 | 6c 119 | 6f 120 | 6f 121 | 70 122 | 69 123 | 73 124 | 61 125 | 6e 126 | 22 127 | 69 128 | 6e 129 | 69 130 | 74 131 | 69 132 | 61 133 | 6c 134 | 63 135 | 6f 136 | 6d 137 | 6d 138 | 65 139 | 6e 140 | 74 141 | 6c 142 | 6f 143 | 6f 144 | 70 145 | 22 146 | 2c 147 | 61 148 | 73 149 | 69 150 | 6d 151 | 70 152 | 6c 153 | 65 154 | 77 155 | 61 156 | 79 157 | 6f 158 | 66 159 | 61 160 | 64 161 | 64 162 | 69 163 | 6e 164 | 67 165 | 61 166 | 63 167 | 6f 168 | 6d 169 | 6d 170 | 65 171 | 6e 172 | 74 173 | 74 174 | 6f 175 | 61 176 | 42 177 | 46 178 | 70 179 | 72 180 | 6f 181 | 67 182 | 72 183 | 61 184 | 6d 185 | 73 186 | 75 187 | 63 188 | 68 189 | 74 190 | 68 191 | 61 192 | 74 193 | 79 194 | 6f 195 | 75 196 | 64 197 | 6f 198 | 6e 199 | 27 200 | 74 201 | 68 202 | 61 203 | 76 204 | 65 205 | 74 206 | 6f 207 | 77 208 | 6f 209 | 72 210 | 72 211 | 79 212 | 61 213 | 62 214 | 6f 215 | 75 216 | 74 217 | 61 218 | 6e 219 | 79 220 | 63 221 | 6f 222 | 6d 223 | 6d 224 | 61 225 | 6e 226 | 64 227 | 63 228 | 68 229 | 61 230 | 72 231 | 61 232 | 63 233 | 74 234 | 65 235 | 72 236 | 73 237 | 2e 238 | 41 239 | 6e 240 | 79 241 | 22 242 | 2e 243 | 22 244 | 2c 245 | 22 246 | 2c 247 | 22 248 | 2c 249 | 22 250 | 2b 251 | 22 252 | 2c 253 | 22 254 | 2d 255 | 22 256 | 2c 257 | 22 258 | 3c 259 | 22 260 | 61 261 | 6e 262 | 64 263 | 22 264 | 3e 265 | 22 266 | 63 267 | 68 268 | 61 269 | 72 270 | 61 271 | 63 272 | 74 273 | 65 274 | 72 275 | 73 276 | 61 277 | 72 278 | 65 279 | 73 280 | 69 281 | 6d 282 | 70 283 | 6c 284 | 79 285 | 69 286 | 67 287 | 6e 288 | 6f 289 | 72 290 | 65 291 | 64 292 | 2c 293 | 74 294 | 68 295 | 65 296 | 22 297 | 5b 298 | 22 299 | 61 300 | 6e 301 | 64 302 | 22 303 | 5d 304 | 22 305 | 63 306 | 68 307 | 61 308 | 72 309 | 61 310 | 63 311 | 74 312 | 65 313 | 72 314 | 73 315 | 6a 316 | 75 317 | 73 318 | 74 319 | 68 320 | 61 321 | 76 322 | 65 323 | 74 324 | 6f 325 | 62 326 | 65 327 | 62 328 | 61 329 | 6c 330 | 61 331 | 6e 332 | 63 333 | 65 334 | 64 335 | 2e 336 | 54 337 | 68 338 | 69 339 | 73 340 | 6c 341 | 6f 342 | 6f 343 | 70 344 | 61 345 | 6e 346 | 64 347 | 74 348 | 68 349 | 65 350 | 63 351 | 6f 352 | 6d 353 | 6d 354 | 61 355 | 6e 356 | 64 357 | 73 358 | 69 359 | 74 360 | 63 361 | 6f 362 | 6e 363 | 74 364 | 61 365 | 69 366 | 6e 367 | 73 368 | 61 369 | 72 370 | 65 371 | 69 372 | 67 373 | 6e 374 | 6f 375 | 72 376 | 65 377 | 64 378 | 62 379 | 65 380 | 63 381 | 61 382 | 75 383 | 73 384 | 65 385 | 74 386 | 68 387 | 65 388 | 63 389 | 75 390 | 72 391 | 72 392 | 65 393 | 6e 394 | 74 395 | 63 396 | 65 397 | 6c 398 | 6c 399 | 64 400 | 65 401 | 66 402 | 61 403 | 75 404 | 6c 405 | 74 406 | 73 407 | 74 408 | 6f 409 | 61 410 | 76 411 | 61 412 | 6c 413 | 75 414 | 65 415 | 6f 416 | 66 417 | 30 418 | 3b 419 | 74 420 | 68 421 | 65 422 | 30 423 | 76 424 | 61 425 | 6c 426 | 75 427 | 65 428 | 63 429 | 61 430 | 75 431 | 73 432 | 65 433 | 73 434 | 74 435 | 68 436 | 69 437 | 73 438 | 6c 439 | 6f 440 | 6f 441 | 70 442 | 74 443 | 6f 444 | 62 445 | 65 446 | 73 447 | 6b 448 | 69 449 | 70 450 | 70 451 | 65 452 | 64 453 | 2e 454 | 5d 455 | 2b 456 | 2b 457 | 2b 458 | 2b 459 | 2b 460 | 2b 461 | 2b 462 | 2b 463 | 53 464 | 65 465 | 74 466 | 43 467 | 65 468 | 6c 469 | 6c 470 | 23 471 | 30 472 | 74 473 | 6f 474 | 38 475 | 5b 476 | 3e 477 | 2b 478 | 2b 479 | 2b 480 | 2b 481 | 41 482 | 64 483 | 64 484 | 34 485 | 74 486 | 6f 487 | 43 488 | 65 489 | 6c 490 | 6c 491 | 23 492 | 31 493 | 3b 494 | 74 495 | 68 496 | 69 497 | 73 498 | 77 499 | 69 500 | 6c 501 | 6c 502 | 61 503 | 6c 504 | 77 505 | 61 506 | 79 507 | 73 508 | 73 509 | 65 510 | 74 511 | 43 512 | 65 513 | 6c 514 | 6c 515 | 23 516 | 31 517 | 74 518 | 6f 519 | 34 520 | 5b 521 | 61 522 | 73 523 | 74 524 | 68 525 | 65 526 | 63 527 | 65 528 | 6c 529 | 6c 530 | 77 531 | 69 532 | 6c 533 | 6c 534 | 62 535 | 65 536 | 63 537 | 6c 538 | 65 539 | 61 540 | 72 541 | 65 542 | 64 543 | 62 544 | 79 545 | 74 546 | 68 547 | 65 548 | 6c 549 | 6f 550 | 6f 551 | 70 552 | 3e 553 | 2b 554 | 2b 555 | 41 556 | 64 557 | 64 558 | 32 559 | 74 560 | 6f 561 | 43 562 | 65 563 | 6c 564 | 6c 565 | 23 566 | 32 567 | 3e 568 | 2b 569 | 2b 570 | 2b 571 | 41 572 | 64 573 | 64 574 | 33 575 | 74 576 | 6f 577 | 43 578 | 65 579 | 6c 580 | 6c 581 | 23 582 | 33 583 | 3e 584 | 2b 585 | 2b 586 | 2b 587 | 41 588 | 64 589 | 64 590 | 33 591 | 74 592 | 6f 593 | 43 594 | 65 595 | 6c 596 | 6c 597 | 23 598 | 34 599 | 3e 600 | 2b 601 | 41 602 | 64 603 | 64 604 | 31 605 | 74 606 | 6f 607 | 43 608 | 65 609 | 6c 610 | 6c 611 | 23 612 | 35 613 | 3c 614 | 3c 615 | 3c 616 | 3c 617 | 2d 618 | 44 619 | 65 620 | 63 621 | 72 622 | 65 623 | 6d 624 | 65 625 | 6e 626 | 74 627 | 74 628 | 68 629 | 65 630 | 6c 631 | 6f 632 | 6f 633 | 70 634 | 63 635 | 6f 636 | 75 637 | 6e 638 | 74 639 | 65 640 | 72 641 | 69 642 | 6e 643 | 43 644 | 65 645 | 6c 646 | 6c 647 | 23 648 | 31 649 | 5d 650 | 4c 651 | 6f 652 | 6f 653 | 70 654 | 74 655 | 69 656 | 6c 657 | 6c 658 | 43 659 | 65 660 | 6c 661 | 6c 662 | 23 663 | 31 664 | 69 665 | 73 666 | 7a 667 | 65 668 | 72 669 | 6f 670 | 3b 671 | 6e 672 | 75 673 | 6d 674 | 62 675 | 65 676 | 72 677 | 6f 678 | 66 679 | 69 680 | 74 681 | 65 682 | 72 683 | 61 684 | 74 685 | 69 686 | 6f 687 | 6e 688 | 73 689 | 69 690 | 73 691 | 34 692 | 3e 693 | 2b 694 | 41 695 | 64 696 | 64 697 | 31 698 | 74 699 | 6f 700 | 43 701 | 65 702 | 6c 703 | 6c 704 | 23 705 | 32 706 | 3e 707 | 2b 708 | 41 709 | 64 710 | 64 711 | 31 712 | 74 713 | 6f 714 | 43 715 | 65 716 | 6c 717 | 6c 718 | 23 719 | 33 720 | 3e 721 | 2d 722 | 53 723 | 75 724 | 62 725 | 74 726 | 72 727 | 61 728 | 63 729 | 74 730 | 31 731 | 66 732 | 72 733 | 6f 734 | 6d 735 | 43 736 | 65 737 | 6c 738 | 6c 739 | 23 740 | 34 741 | 3e 742 | 3e 743 | 2b 744 | 41 745 | 64 746 | 64 747 | 31 748 | 74 749 | 6f 750 | 43 751 | 65 752 | 6c 753 | 6c 754 | 23 755 | 36 756 | 5b 757 | 3c 758 | 5d 759 | 4d 760 | 6f 761 | 76 762 | 65 763 | 62 764 | 61 765 | 63 766 | 6b 767 | 74 768 | 6f 769 | 74 770 | 68 771 | 65 772 | 66 773 | 69 774 | 72 775 | 73 776 | 74 777 | 7a 778 | 65 779 | 72 780 | 6f 781 | 63 782 | 65 783 | 6c 784 | 6c 785 | 79 786 | 6f 787 | 75 788 | 66 789 | 69 790 | 6e 791 | 64 792 | 3b 793 | 74 794 | 68 795 | 69 796 | 73 797 | 77 798 | 69 799 | 6c 800 | 6c 801 | 62 802 | 65 803 | 43 804 | 65 805 | 6c 806 | 6c 807 | 23 808 | 31 809 | 77 810 | 68 811 | 69 812 | 63 813 | 68 814 | 77 815 | 61 816 | 73 817 | 63 818 | 6c 819 | 65 820 | 61 821 | 72 822 | 65 823 | 64 824 | 62 825 | 79 826 | 74 827 | 68 828 | 65 829 | 70 830 | 72 831 | 65 832 | 76 833 | 69 834 | 6f 835 | 75 836 | 73 837 | 6c 838 | 6f 839 | 6f 840 | 70 841 | 3c 842 | 2d 843 | 44 844 | 65 845 | 63 846 | 72 847 | 65 848 | 6d 849 | 65 850 | 6e 851 | 74 852 | 74 853 | 68 854 | 65 855 | 6c 856 | 6f 857 | 6f 858 | 70 859 | 43 860 | 6f 861 | 75 862 | 6e 863 | 74 864 | 65 865 | 72 866 | 69 867 | 6e 868 | 43 869 | 65 870 | 6c 871 | 6c 872 | 23 873 | 30 874 | 5d 875 | 4c 876 | 6f 877 | 6f 878 | 70 879 | 74 880 | 69 881 | 6c 882 | 6c 883 | 43 884 | 65 885 | 6c 886 | 6c 887 | 23 888 | 30 889 | 69 890 | 73 891 | 7a 892 | 65 893 | 72 894 | 6f 895 | 3b 896 | 6e 897 | 75 898 | 6d 899 | 62 900 | 65 901 | 72 902 | 6f 903 | 66 904 | 69 905 | 74 906 | 65 907 | 72 908 | 61 909 | 74 910 | 69 911 | 6f 912 | 6e 913 | 73 914 | 69 915 | 73 916 | 38 917 | 54 918 | 68 919 | 65 920 | 72 921 | 65 922 | 73 923 | 75 924 | 6c 925 | 74 926 | 6f 927 | 66 928 | 74 929 | 68 930 | 69 931 | 73 932 | 69 933 | 73 934 | 3a 935 | 43 936 | 65 937 | 6c 938 | 6c 939 | 4e 940 | 6f 941 | 3a 942 | 30 943 | 31 944 | 32 945 | 33 946 | 34 947 | 35 948 | 36 949 | 43 950 | 6f 951 | 6e 952 | 74 953 | 65 954 | 6e 955 | 74 956 | 73 957 | 3a 958 | 30 959 | 30 960 | 37 961 | 32 962 | 31 963 | 30 964 | 34 965 | 38 966 | 38 967 | 33 968 | 32 969 | 38 970 | 50 971 | 6f 972 | 69 973 | 6e 974 | 74 975 | 65 976 | 72 977 | 3a 978 | 5e 979 | 3e 980 | 3e 981 | 2e 982 | 43 983 | 65 984 | 6c 985 | 6c 986 | 23 987 | 32 988 | 68 989 | 61 990 | 73 991 | 76 992 | 61 993 | 6c 994 | 75 995 | 65 996 | 37 997 | 32 998 | 77 999 | 68 1000 | 69 1001 | 63 1002 | 68 1003 | 69 1004 | 73 1005 | 27 1006 | 48 1007 | 27 1008 | 3e 1009 | 2d 1010 | 2d 1011 | 2d 1012 | 2e 1013 | 53 1014 | 75 1015 | 62 1016 | 74 1017 | 72 1018 | 61 1019 | 63 1020 | 74 1021 | 33 1022 | 66 1023 | 72 1024 | 6f 1025 | 6d 1026 | 43 1027 | 65 1028 | 6c 1029 | 6c 1030 | 23 1031 | 33 1032 | 74 1033 | 6f 1034 | 67 1035 | 65 1036 | 74 1037 | 31 1038 | 30 1039 | 31 1040 | 77 1041 | 68 1042 | 69 1043 | 63 1044 | 68 1045 | 69 1046 | 73 1047 | 27 1048 | 65 1049 | 27 1050 | 2b 1051 | 2b 1052 | 2b 1053 | 2b 1054 | 2b 1055 | 2b 1056 | 2b 1057 | 2e 1058 | 2e 1059 | 2b 1060 | 2b 1061 | 2b 1062 | 2e 1063 | 4c 1064 | 69 1065 | 6b 1066 | 65 1067 | 77 1068 | 69 1069 | 73 1070 | 65 1071 | 66 1072 | 6f 1073 | 72 1074 | 27 1075 | 6c 1076 | 6c 1077 | 6f 1078 | 27 1079 | 66 1080 | 72 1081 | 6f 1082 | 6d 1083 | 43 1084 | 65 1085 | 6c 1086 | 6c 1087 | 23 1088 | 33 1089 | 3e 1090 | 3e 1091 | 2e 1092 | 43 1093 | 65 1094 | 6c 1095 | 6c 1096 | 23 1097 | 35 1098 | 69 1099 | 73 1100 | 33 1101 | 32 1102 | 66 1103 | 6f 1104 | 72 1105 | 74 1106 | 68 1107 | 65 1108 | 73 1109 | 70 1110 | 61 1111 | 63 1112 | 65 1113 | 3c 1114 | 2d 1115 | 2e 1116 | 53 1117 | 75 1118 | 62 1119 | 74 1120 | 72 1121 | 61 1122 | 63 1123 | 74 1124 | 31 1125 | 66 1126 | 72 1127 | 6f 1128 | 6d 1129 | 43 1130 | 65 1131 | 6c 1132 | 6c 1133 | 23 1134 | 34 1135 | 66 1136 | 6f 1137 | 72 1138 | 38 1139 | 37 1140 | 74 1141 | 6f 1142 | 67 1143 | 69 1144 | 76 1145 | 65 1146 | 61 1147 | 27 1148 | 57 1149 | 27 1150 | 3c 1151 | 2e 1152 | 43 1153 | 65 1154 | 6c 1155 | 6c 1156 | 23 1157 | 33 1158 | 77 1159 | 61 1160 | 73 1161 | 73 1162 | 65 1163 | 74 1164 | 74 1165 | 6f 1166 | 27 1167 | 6f 1168 | 27 1169 | 66 1170 | 72 1171 | 6f 1172 | 6d 1173 | 74 1174 | 68 1175 | 65 1176 | 65 1177 | 6e 1178 | 64 1179 | 6f 1180 | 66 1181 | 27 1182 | 48 1183 | 65 1184 | 6c 1185 | 6c 1186 | 6f 1187 | 27 1188 | 2b 1189 | 2b 1190 | 2b 1191 | 2e 1192 | 2d 1193 | 2d 1194 | 2d 1195 | 2d 1196 | 2d 1197 | 2d 1198 | 2e 1199 | 2d 1200 | 2d 1201 | 2d 1202 | 2d 1203 | 2d 1204 | 2d 1205 | 2d 1206 | 2d 1207 | 2e 1208 | 43 1209 | 65 1210 | 6c 1211 | 6c 1212 | 23 1213 | 33 1214 | 66 1215 | 6f 1216 | 72 1217 | 27 1218 | 72 1219 | 6c 1220 | 27 1221 | 61 1222 | 6e 1223 | 64 1224 | 27 1225 | 64 1226 | 27 1227 | 3e 1228 | 3e 1229 | 2b 1230 | 2e 1231 | 41 1232 | 64 1233 | 64 1234 | 31 1235 | 74 1236 | 6f 1237 | 43 1238 | 65 1239 | 6c 1240 | 6c 1241 | 23 1242 | 35 1243 | 67 1244 | 69 1245 | 76 1246 | 65 1247 | 73 1248 | 75 1249 | 73 1250 | 61 1251 | 6e 1252 | 65 1253 | 78 1254 | 63 1255 | 6c 1256 | 61 1257 | 6d 1258 | 61 1259 | 74 1260 | 69 1261 | 6f 1262 | 6e 1263 | 70 1264 | 6f 1265 | 69 1266 | 6e 1267 | 74 1268 | 3e 1269 | 2b 1270 | 2b 1271 | 2e 1272 | 41 1273 | 6e 1274 | 64 1275 | 66 1276 | 69 1277 | 6e 1278 | 61 1279 | 6c 1280 | 6c 1281 | 79 1282 | 61 1283 | 6e 1284 | 65 1285 | 77 1286 | 6c 1287 | 69 1288 | 6e 1289 | 65 1290 | 66 1291 | 72 1292 | 6f 1293 | 6d 1294 | 43 1295 | 65 1296 | 6c 1297 | 6c 1298 | 23 1299 | 36 1300 | ff 1301 | -------------------------------------------------------------------------------- /brainfuck/hello2.hex: -------------------------------------------------------------------------------- 1 | 2b 2 | 2b 3 | 2b 4 | 2b 5 | 2b 6 | 2b 7 | 2b 8 | 2b 9 | 5b 10 | 3e 11 | 2b 12 | 2b 13 | 2b 14 | 2b 15 | 5b 16 | 3e 17 | 2b 18 | 2b 19 | 3e 20 | 2b 21 | 2b 22 | 2b 23 | 3e 24 | 2b 25 | 2b 26 | 2b 27 | 3e 28 | 2b 29 | 3e 30 | 3e 31 | 2b 32 | 3c 33 | 3c 34 | 3c 35 | 3c 36 | 3c 37 | 3c 38 | 2d 39 | 5d 40 | 3e 41 | 2b 42 | 3e 43 | 2b 44 | 3e 45 | 2d 46 | 3e 47 | 3e 48 | 2b 49 | 3c 50 | 3c 51 | 3c 52 | 3c 53 | 3c 54 | 3c 55 | 2d 56 | 5d 57 | 3e 58 | 3e 59 | 2e 60 | 3e 61 | 2d 62 | 2d 63 | 2d 64 | 2e 65 | 2b 66 | 2b 67 | 2b 68 | 2b 69 | 2b 70 | 2b 71 | 2b 72 | 2e 73 | 2e 74 | 2b 75 | 2b 76 | 2b 77 | 2e 78 | 3e 79 | 3e 80 | 2e 81 | 3c 82 | 2d 83 | 2e 84 | 3c 85 | 2e 86 | 2b 87 | 2b 88 | 2b 89 | 2e 90 | 2d 91 | 2d 92 | 2d 93 | 2d 94 | 2d 95 | 2d 96 | 2e 97 | 2d 98 | 2d 99 | 2d 100 | 2d 101 | 2d 102 | 2d 103 | 2d 104 | 2d 105 | 2e 106 | 3e 107 | 3e 108 | 2b 109 | 2e 110 | 3e 111 | 2b 112 | 2b 113 | 2e 114 | ff 115 | -------------------------------------------------------------------------------- /brainfuck/helloshort.bf: -------------------------------------------------------------------------------- 1 | ++++++++[>++++[>++>+++>+++>+<<<<-]>+>+>->>+[<]<-]>>.>---.+++++++..+++.>>.<-.<.+++.------.--------.>>+.>++. 2 | -------------------------------------------------------------------------------- /brainfuck/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /brainfuck/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /brainfuck/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io -nowarn PIN_1 A2 42 | set_io -nowarn PIN_2 A1 43 | set_io -nowarn PIN_3 B1 44 | set_io -nowarn PIN_4 C2 45 | set_io -nowarn PIN_5 C1 46 | set_io -nowarn PIN_6 D2 47 | set_io -nowarn PIN_7 D1 48 | set_io -nowarn PIN_8 E2 49 | set_io -nowarn PIN_9 E1 50 | set_io -nowarn PIN_10 G2 51 | set_io -nowarn PIN_11 H1 52 | set_io -nowarn PIN_12 J1 53 | set_io -nowarn PIN_13 H2 54 | 55 | # Right side of board 56 | set_io -nowarn PIN_14 H9 57 | set_io -nowarn PIN_15 D9 58 | set_io -nowarn PIN_16 D8 59 | set_io -nowarn PIN_17 C9 60 | set_io -nowarn PIN_18 A9 61 | set_io -nowarn PIN_19 B8 62 | set_io -nowarn PIN_20 A8 63 | set_io -nowarn PIN_21 B7 64 | set_io -nowarn PIN_22 A7 65 | set_io -nowarn PIN_23 B6 66 | set_io -nowarn PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io -nowarn SPI_SS F7 70 | set_io -nowarn SPI_SCK G7 71 | set_io -nowarn SPI_IO0 G6 72 | set_io -nowarn SPI_IO1 H7 73 | set_io -nowarn SPI_IO2 H4 74 | set_io -nowarn SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io -nowarn PIN_25 G1 78 | set_io -nowarn PIN_26 J3 79 | set_io -nowarn PIN_27 J4 80 | set_io -nowarn PIN_28 G9 81 | set_io -nowarn PIN_29 J9 82 | set_io -nowarn PIN_30 E8 83 | set_io -nowarn PIN_31 J2 84 | 85 | # LED 86 | set_io -nowarn LED B3 87 | 88 | # USB 89 | set_io -nowarn USBP B4 90 | set_io -nowarn USBN A4 91 | set_io -nowarn USBPU A3 92 | 93 | # 16MHz clock 94 | set_io -nowarn CLK B2 # input 95 | 96 | set_io clk B2 97 | -------------------------------------------------------------------------------- /brainfuck/program.hex: -------------------------------------------------------------------------------- 1 | 2b 2 | 2b 3 | 2b 4 | 2b 5 | 2b 6 | 2b 7 | 2b 8 | 2b 9 | 5b 10 | 3e 11 | 2b 12 | 2b 13 | 2b 14 | 2b 15 | 5b 16 | 3e 17 | 2b 18 | 2b 19 | 3e 20 | 2b 21 | 2b 22 | 2b 23 | 3e 24 | 2b 25 | 2b 26 | 2b 27 | 3e 28 | 2b 29 | 3c 30 | 3c 31 | 3c 32 | 3c 33 | 2d 34 | 5d 35 | 3e 36 | 2b 37 | 3e 38 | 2b 39 | 3e 40 | 2d 41 | 3e 42 | 3e 43 | 2b 44 | 5b 45 | 3c 46 | 5d 47 | 3c 48 | 2d 49 | 5d 50 | 3e 51 | 3e 52 | 2e 53 | 3e 54 | 2d 55 | 2d 56 | 2d 57 | 2e 58 | 2b 59 | 2b 60 | 2b 61 | 2b 62 | 2b 63 | 2b 64 | 2b 65 | 2e 66 | 2e 67 | 2b 68 | 2b 69 | 2b 70 | 2e 71 | 3e 72 | 3e 73 | 2e 74 | 3c 75 | 2d 76 | 2e 77 | 3c 78 | 2e 79 | 2b 80 | 2b 81 | 2b 82 | 2e 83 | 2d 84 | 2d 85 | 2d 86 | 2d 87 | 2d 88 | 2d 89 | 2e 90 | 2d 91 | 2d 92 | 2d 93 | 2d 94 | 2d 95 | 2d 96 | 2d 97 | 2d 98 | 2e 99 | 3e 100 | 3e 101 | 2b 102 | 2e 103 | 3e 104 | 2b 105 | 2b 106 | 2e 107 | ff 108 | -------------------------------------------------------------------------------- /brainfuck/simpleuart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module simpleuart ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | input ser_rx, 26 | 27 | input reg_dat_we, 28 | input reg_dat_re, 29 | input [7:0] reg_dat_di, 30 | output [7:0] reg_dat_do, 31 | output reg_dat_wait, 32 | input [31:0] cfg_divider 33 | ); 34 | 35 | reg [3:0] recv_state; 36 | reg [31:0] recv_divcnt; 37 | reg [7:0] recv_pattern; 38 | reg [7:0] recv_buf_data; 39 | reg recv_buf_valid; 40 | 41 | reg [9:0] send_pattern; 42 | reg [3:0] send_bitcnt; 43 | reg [31:0] send_divcnt; 44 | reg send_dummy; 45 | 46 | assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); 47 | assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; 48 | 49 | always @(posedge clk) begin 50 | if (!resetn) begin 51 | recv_state <= 0; 52 | recv_divcnt <= 0; 53 | recv_pattern <= 0; 54 | recv_buf_data <= 0; 55 | recv_buf_valid <= 0; 56 | end else begin 57 | recv_divcnt <= recv_divcnt + 1; 58 | if (reg_dat_re) 59 | recv_buf_valid <= 0; 60 | case (recv_state) 61 | 0: begin 62 | if (!ser_rx) 63 | recv_state <= 1; 64 | recv_divcnt <= 0; 65 | end 66 | 1: begin 67 | if (2*recv_divcnt > cfg_divider) begin 68 | recv_state <= 2; 69 | recv_divcnt <= 0; 70 | end 71 | end 72 | 10: begin 73 | if (recv_divcnt > cfg_divider) begin 74 | recv_buf_data <= recv_pattern; 75 | recv_buf_valid <= 1; 76 | recv_state <= 0; 77 | end 78 | end 79 | default: begin 80 | if (recv_divcnt > cfg_divider) begin 81 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 82 | recv_state <= recv_state + 1; 83 | recv_divcnt <= 0; 84 | end 85 | end 86 | endcase 87 | end 88 | end 89 | 90 | assign ser_tx = send_pattern[0]; 91 | 92 | always @(posedge clk) begin 93 | send_divcnt <= send_divcnt + 1; 94 | if (!resetn) begin 95 | send_pattern <= ~0; 96 | send_bitcnt <= 0; 97 | send_divcnt <= 0; 98 | send_dummy <= 1; 99 | end else begin 100 | if (send_dummy && !send_bitcnt) begin 101 | send_pattern <= ~0; 102 | send_bitcnt <= 15; 103 | send_divcnt <= 0; 104 | send_dummy <= 0; 105 | end else if (reg_dat_we && !send_bitcnt) begin 106 | send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; 107 | send_bitcnt <= 10; 108 | send_divcnt <= 0; 109 | end else if (send_divcnt > cfg_divider && send_bitcnt) begin 110 | send_pattern <= {1'b1, send_pattern[9:1]}; 111 | send_bitcnt <= send_bitcnt - 1; 112 | send_divcnt <= 0; 113 | end 114 | end 115 | end 116 | endmodule 117 | -------------------------------------------------------------------------------- /brainfuck/test1.hex: -------------------------------------------------------------------------------- 1 | 2B 2 | 2B 3 | 2B 4 | 2B 5 | 2B 6 | 2B 7 | 2B 8 | 2B 9 | 2E 10 | 3E 11 | 2E 12 | 3C 13 | 2E 14 | 5B 15 | 2E 16 | 3E 17 | 2B 18 | 2B 19 | 2B 20 | 2B 21 | 3C 22 | 2E 23 | 2D 24 | 2E 25 | 5D 26 | FF 27 | -------------------------------------------------------------------------------- /hello_world/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /hello_world/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /hello_world/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /hello_world/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io -nowarn PIN_1 A2 42 | set_io -nowarn PIN_2 A1 43 | set_io -nowarn PIN_3 B1 44 | set_io -nowarn PIN_4 C2 45 | set_io -nowarn PIN_5 C1 46 | set_io -nowarn PIN_6 D2 47 | set_io -nowarn PIN_7 D1 48 | set_io -nowarn PIN_8 E2 49 | set_io -nowarn PIN_9 E1 50 | set_io -nowarn PIN_10 G2 51 | set_io -nowarn PIN_11 H1 52 | set_io -nowarn PIN_12 J1 53 | set_io -nowarn PIN_13 H2 54 | 55 | # Right side of board 56 | set_io -nowarn PIN_14 H9 57 | set_io -nowarn PIN_15 D9 58 | set_io -nowarn PIN_16 D8 59 | set_io -nowarn PIN_17 C9 60 | set_io -nowarn PIN_18 A9 61 | set_io -nowarn PIN_19 B8 62 | set_io -nowarn PIN_20 A8 63 | set_io -nowarn PIN_21 B7 64 | set_io -nowarn PIN_22 A7 65 | set_io -nowarn PIN_23 B6 66 | set_io -nowarn PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io -nowarn SPI_SS F7 70 | set_io -nowarn SPI_SCK G7 71 | set_io -nowarn SPI_IO0 G6 72 | set_io -nowarn SPI_IO1 H7 73 | set_io -nowarn SPI_IO2 H4 74 | set_io -nowarn SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io -nowarn PIN_25 G1 78 | set_io -nowarn PIN_26 J3 79 | set_io -nowarn PIN_27 J4 80 | set_io -nowarn PIN_28 G9 81 | set_io -nowarn PIN_29 J9 82 | set_io -nowarn PIN_30 E8 83 | set_io -nowarn PIN_31 J2 84 | 85 | # LED 86 | set_io -nowarn LED B3 87 | 88 | # USB 89 | set_io -nowarn USBP B4 90 | set_io -nowarn USBN A4 91 | set_io -nowarn USBPU A3 92 | 93 | # 16MHz clock 94 | set_io -nowarn CLK B2 # input 95 | -------------------------------------------------------------------------------- /hello_world/simpleuart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module simpleuart ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | input ser_rx, 26 | 27 | input [3:0] reg_div_we, 28 | input [31:0] reg_div_di, 29 | output [31:0] reg_div_do, 30 | 31 | input reg_dat_we, 32 | input reg_dat_re, 33 | input [31:0] reg_dat_di, 34 | output [31:0] reg_dat_do, 35 | output reg_dat_wait 36 | ); 37 | reg [31:0] cfg_divider; 38 | 39 | reg [3:0] recv_state; 40 | reg [31:0] recv_divcnt; 41 | reg [7:0] recv_pattern; 42 | reg [7:0] recv_buf_data; 43 | reg recv_buf_valid; 44 | 45 | reg [9:0] send_pattern; 46 | reg [3:0] send_bitcnt; 47 | reg [31:0] send_divcnt; 48 | reg send_dummy; 49 | 50 | assign reg_div_do = cfg_divider; 51 | 52 | assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); 53 | assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; 54 | 55 | always @(posedge clk) begin 56 | if (!resetn) begin 57 | cfg_divider <= 1; 58 | end else begin 59 | if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0]; 60 | if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8]; 61 | if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16]; 62 | if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24]; 63 | end 64 | end 65 | 66 | always @(posedge clk) begin 67 | if (!resetn) begin 68 | recv_state <= 0; 69 | recv_divcnt <= 0; 70 | recv_pattern <= 0; 71 | recv_buf_data <= 0; 72 | recv_buf_valid <= 0; 73 | end else begin 74 | recv_divcnt <= recv_divcnt + 1; 75 | if (reg_dat_re) 76 | recv_buf_valid <= 0; 77 | case (recv_state) 78 | 0: begin 79 | if (!ser_rx) 80 | recv_state <= 1; 81 | recv_divcnt <= 0; 82 | end 83 | 1: begin 84 | if (2*recv_divcnt > cfg_divider) begin 85 | recv_state <= 2; 86 | recv_divcnt <= 0; 87 | end 88 | end 89 | 10: begin 90 | if (recv_divcnt > cfg_divider) begin 91 | recv_buf_data <= recv_pattern; 92 | recv_buf_valid <= 1; 93 | recv_state <= 0; 94 | end 95 | end 96 | default: begin 97 | if (recv_divcnt > cfg_divider) begin 98 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 99 | recv_state <= recv_state + 1; 100 | recv_divcnt <= 0; 101 | end 102 | end 103 | endcase 104 | end 105 | end 106 | 107 | assign ser_tx = send_pattern[0]; 108 | 109 | always @(posedge clk) begin 110 | if (reg_div_we) 111 | send_dummy <= 1; 112 | send_divcnt <= send_divcnt + 1; 113 | if (!resetn) begin 114 | send_pattern <= ~0; 115 | send_bitcnt <= 0; 116 | send_divcnt <= 0; 117 | send_dummy <= 1; 118 | end else begin 119 | if (send_dummy && !send_bitcnt) begin 120 | send_pattern <= ~0; 121 | send_bitcnt <= 15; 122 | send_divcnt <= 0; 123 | send_dummy <= 0; 124 | end else if (reg_dat_we && !send_bitcnt) begin 125 | send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; 126 | send_bitcnt <= 10; 127 | send_divcnt <= 0; 128 | end else if (send_divcnt > cfg_divider && send_bitcnt) begin 129 | send_pattern <= {1'b1, send_pattern[9:1]}; 130 | send_bitcnt <= send_bitcnt - 1; 131 | send_divcnt <= 0; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /hello_world/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | input PIN_2, 5 | output USBPU, 6 | output PIN_1 7 | ); 8 | 9 | // Disable USB 10 | assign USBPU = 0; 11 | 12 | wire clk = CLK; 13 | reg [3:0] reg_div_en; 14 | reg [31:0] reg_div_di; 15 | wire [31:0] reg_div_do; 16 | reg [31:0] reg_dat_di; 17 | wire [31:0] reg_dat_do; 18 | reg reg_dat_re, reg_dat_we; 19 | wire reg_dat_wait; 20 | reg speed_set = 0; 21 | reg wait_for_send; 22 | 23 | // Generate reset signal 24 | reg [5:0] reset_cnt = 0; 25 | wire resetn = &reset_cnt; 26 | 27 | always @(posedge clk) begin 28 | reset_cnt <= reset_cnt + !resetn; 29 | end 30 | 31 | // Set the uart speed to 115200 32 | always @(posedge clk) begin 33 | if (resetn && !speed_set) begin 34 | reg_div_en <= 4'b1111; 35 | reg_div_di <= 32'd139; // 16Mhz / 115200 36 | speed_set <= 1; 37 | end else reg_div_en <= 4'b0000; 38 | end 39 | 40 | // Create the text string 41 | reg [7:0] text [0:12]; 42 | 43 | initial begin 44 | text[0] <= "H"; 45 | text[1] <= "e"; 46 | text[2] <= "l"; 47 | text[3] <= "l"; 48 | text[4] <= "o"; 49 | text[5] <= " "; 50 | text[6] <= "W"; 51 | text[7] <= "o"; 52 | text[8] <= "r"; 53 | text[9] <= "l"; 54 | text[10] <= "d"; 55 | text[11] <= "!"; 56 | text[12] <= "\n"; 57 | end 58 | 59 | // Send characters about every second 60 | reg [22:0] delay_count; 61 | reg [3:0] char_count; 62 | 63 | always @(posedge clk) begin 64 | delay_count <= delay_count + 1; 65 | if (speed_set && !wait_for_send) begin 66 | if (&delay_count) begin 67 | if (char_count == 12) char_count <= 0; 68 | else char_count <= char_count + 1; 69 | reg_dat_di <= text[char_count]; 70 | reg_dat_we <= 1; 71 | wait_for_send <= 1; 72 | end 73 | end else if (!reg_dat_wait) begin 74 | reg_dat_we <= 0; 75 | wait_for_send <= 0; 76 | end 77 | end 78 | 79 | // uart from picosoc 80 | simpleuart uart ( 81 | .clk (clk), 82 | .resetn (resetn), 83 | 84 | .ser_tx (PIN_1), 85 | .ser_rx (PIN_2), 86 | 87 | .reg_div_we (reg_div_en), 88 | .reg_div_di (reg_div_di), 89 | .reg_div_do (reg_div_do), 90 | 91 | .reg_dat_we (reg_dat_we), 92 | .reg_dat_re (reg_dat_re), 93 | .reg_dat_di (reg_dat_di), 94 | .reg_dat_do (reg_dat_do), 95 | .reg_dat_wait(reg_dat_wait) 96 | ); 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /hex7seg/PushButton_Debouncer.v: -------------------------------------------------------------------------------- 1 | module PushButton_Debouncer( 2 | input clk, 3 | input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal 4 | 5 | // from which we make three outputs, all synchronous to the clock 6 | output reg PB_state, // 1 as long as the push-button is active (down) 7 | output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed) 8 | output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released) 9 | ); 10 | 11 | // First use two flip-flops to synchronize the PB signal the "clk" clock domain 12 | reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high 13 | reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0; 14 | 15 | // Next declare a 16-bits counter 16 | reg [15:0] PB_cnt; 17 | 18 | // When the push-button is pushed or released, we increment the counter 19 | // The counter has to be maxed out before we decide that the push-button state has changed 20 | 21 | wire PB_idle = (PB_state==PB_sync_1); 22 | wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's 23 | 24 | always @(posedge clk) 25 | if(PB_idle) 26 | PB_cnt <= 0; // nothing's going on 27 | else 28 | begin 29 | PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter 30 | if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed! 31 | end 32 | 33 | assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state; 34 | assign PB_up = ~PB_idle & PB_cnt_max & PB_state; 35 | endmodule 36 | -------------------------------------------------------------------------------- /hex7seg/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /hex7seg/decoder_7_seg_hex.v: -------------------------------------------------------------------------------- 1 | module decoder_7_seg_hex( 2 | input clk, 3 | input [3:0] data, 4 | output reg [6:0] seg 5 | ); 6 | 7 | always @(posedge clk) begin 8 | case(data) 9 | 'h0: seg <= 'b1111110; 10 | 'h1: seg <= 'b0000110; 11 | 'h2: seg <= 'b1101101; 12 | 'h3: seg <= 'b1001111; 13 | 'h4: seg <= 'b0010111; 14 | 'h5: seg <= 'b1011011; 15 | 'h6: seg <= 'b1111011; 16 | 'h7: seg <= 'b0001110; 17 | 'h8: seg <= 'b1111111; 18 | 'h9: seg <= 'b1011111; 19 | 'hA: seg <= 'b0111111; 20 | 'hB: seg <= 'b1110011; 21 | 'hC: seg <= 'b1111000; 22 | 'hD: seg <= 'b1100111; 23 | 'hE: seg <= 'b1111001; 24 | 'hF: seg <= 'b0111001; 25 | endcase 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /hex7seg/display_7_seg_hex.v: -------------------------------------------------------------------------------- 1 | module display_7_seg_hex( 2 | input clk, 3 | input [7:0] value, 4 | output [6:0] seg, 5 | output reg digit 6 | ); 7 | 8 | reg [3:0] data; 9 | reg posn; 10 | reg [23:0] prescaler; 11 | 12 | decoder_7_seg_hex decoder(.clk (clk), .seg(seg), .data(data)); 13 | 14 | always @(posedge clk) begin 15 | prescaler <= prescaler + 1; 16 | if (prescaler == 8000) begin // 1khz 17 | prescaler <= 0; 18 | posn <= posn + 1; 19 | if (posn == 1) begin 20 | data <= value[7:4]; 21 | digit <= 0; 22 | end else if (posn == 0) begin 23 | data <= value[3:0]; 24 | digit <= 1; 25 | end 26 | end 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /hex7seg/pins.pcf: -------------------------------------------------------------------------------- 1 | set_io digit C9 2 | set_io seg[0] A9 3 | set_io seg[1] B8 4 | set_io seg[2] A8 5 | set_io seg[3] B7 6 | set_io seg[4] A7 7 | set_io seg[5] B6 8 | set_io seg[6] A6 9 | 10 | set_io button H2 11 | 12 | set_io usbpu A3 13 | set_io clk B2 14 | -------------------------------------------------------------------------------- /hex7seg/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clk, 3 | output [6:0] seg, 4 | output digit, 5 | input button, 6 | output usbpu 7 | ); 8 | // Disable USB 9 | assign usbpu = 0; 10 | reg [7:0] v; 11 | wire PB, pressed; 12 | 13 | SB_IO #( 14 | .PIN_TYPE(6'b 1010_01), 15 | .PULLUP(1'b 1) 16 | ) pbin ( 17 | .PACKAGE_PIN(button), 18 | .D_IN_0(PB) 19 | ); 20 | 21 | PushButton_Debouncer pb1 (.clk(clk), .PB(PB), .PB_down(pressed)); 22 | 23 | always @(posedge clk) if (pressed) v <= v + 1; 24 | 25 | // Display value as hex 26 | display_7_seg_hex seghex (.clk(clk), .value(v), .seg(seg), .digit(digit)); 27 | endmodule 28 | -------------------------------------------------------------------------------- /nunchuk/I2C_master.v: -------------------------------------------------------------------------------- 1 | module I2C_master 2 | #( 3 | parameter freq = 20 4 | ) 5 | ( 6 | inout wire SDA, // I2C Serial data line, pulled high at board level 7 | inout wire SCL, // I2C Serial clock line, pulled high at board level 8 | input wire sys_clock, // System clock, wr_ctrl should be synchronous to this 9 | input wire reset, // power-on reset - puts I2C bus into idle state 10 | input wire [31:0] ctrl_data, // Data bus for writing the control register 11 | input wire wr_ctrl, // Write enable for control register, also starts I2C cycles 12 | input wire read, 13 | output reg [31:0] status // Status of I2C including most recently read data 14 | ); 15 | 16 | reg sda_out, sda_dir, scl_out, scl_dir; 17 | 18 | SB_IO #( 19 | .PIN_TYPE(6'b 1010_01), 20 | .PULLUP(1'b 1) 21 | ) sda_io ( 22 | .PACKAGE_PIN(SDA), 23 | .OUTPUT_ENABLE(sda_dir), 24 | .D_OUT_0(sda_out), 25 | .D_IN_0(sda_in) 26 | ); 27 | 28 | SB_IO #( 29 | .PIN_TYPE(6'b 1010_01), 30 | .PULLUP(1'b 1) 31 | ) scl_io ( 32 | .PACKAGE_PIN(SCL), 33 | .OUTPUT_ENABLE(scl_dir), 34 | .D_OUT_0(scl_out), 35 | .D_IN_0(scl_in) 36 | ); 37 | 38 | reg float_sda; // This is essentially SDA when we are sourcing it (open drain at pin) 39 | reg float_scl; // This is essentially SCL when we are sourcing it (open drain at pin) 40 | wire sda_in; // Feedback from the IOB pin for SDA 41 | wire scl_in; // Feedback from the IOB pin for SCL 42 | 43 | assign scl_dir = !float_scl; 44 | assign sda_dir = !float_sda; 45 | assign scl_out = float_scl; 46 | assign sda_out = float_sda; 47 | 48 | // I/O buffers for the I2C open-drain signals 49 | // Note that even if no slaves drive SCL, you need to use feedback 50 | // to sense the rising edge of SCL to be sure to meet hold time. 51 | 52 | localparam t_hd_sta = 4 * freq, // Hold time on START condition, 4.0us from spec 53 | t_low = 5 * freq, // SCL low time 4.7us from spec 54 | t_high = 5 * freq, // SCL high time 4.0us from spec, but cycle time must be 10us 55 | t_su_sta = 5 * freq, // SDA, SCL high before asserting start, 4.7us from spec 56 | t_su_dat = (freq >> 2) + 1, // Data valid to SCL rising, 250ns from spec 57 | t_hold = (freq >> 1) + 1, // SCL falling to SDA changing 0 from spec, 0.5us for AD9888 58 | t_su_sto = 4 * freq; // SCL high to SDA high for STOP condition, 4us from spec 59 | 60 | localparam time_width = clogb2(t_low + 1); // Declare enough bits to hold maximum delay (5 us) 61 | 62 | reg [time_width-1:0] timer; 63 | 64 | // Ceiling of log base 2 from the Verilog Language Reference Manual: 65 | function integer clogb2; 66 | input [31:0] value; 67 | begin 68 | value = value - 1; 69 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 70 | value = value >> 1; 71 | end 72 | endfunction 73 | 74 | reg [31:0] ctrl_reg; // I2C control register 75 | // Bit definitions: 76 | // 31 Short write. 77 | // 30:24 Reserved. 7-bit I2C address of slave. 78 | // 23:16 Register Subaddress 79 | // 15:8 First data byte. Don't care on read cycles 80 | // 7:0 Second data byte. Don't care on read cycles. 81 | 82 | //reg [31:0] status; // I2C status register 83 | // Bit definitions 84 | // 31 Busy. Not ready to accept new control register writes. 85 | // 30 Address NACK. Last address cycle resulted in no acknowledge from slave. 86 | // 29 Data NACK. Last data write cycle resulted in no acknowledge from slave. 87 | // 28 Read. Most recently completed cycle was a read. Data in bits 7:0 is valid. 88 | // 27 Overrun. An attempt was made to write the ctrl_reg while busy. Cleared 89 | // on successful write of ctrl_reg. 90 | // 26 Initializing - waiting for SDA to go high after module reset 91 | // 25:8 Reserved. Tied to zero. 92 | // 7:0 Read data. Valid after a read cycle when bit 28 is set. 93 | 94 | reg [35:0] shift_reg; // Data to shift out. Includes ack positions: 1 = NACK or slave ack. 95 | 96 | reg [5:0] bit_count; // Counts bits during shift states. 97 | 98 | reg [3:0] state; // Main state machine state variable 99 | reg [3:0] rtn_state; // Return state for "subroutines" 100 | 101 | reg sda, scl; // debounced, deglitched SDA and SCL inputs 102 | 103 | reg wr_cyc; // Every access starts with a write cycle for subaddress. 104 | 105 | reg [7:0] read_data; // Input shift register for reads 106 | 107 | reg [3:0] scl_startup_count; // Clock SCL at least 12 times after SDA is detected high 108 | 109 | // Debounce and deglitch input signals 110 | reg [3:0] sda_sr, scl_sr; 111 | always @ (posedge sys_clock or posedge reset) 112 | if (reset) 113 | begin 114 | sda_sr <= 4'b1111; // Start up assuming quiescent state of inputs 115 | sda <= 1; 116 | scl_sr <= 4'b1111; // Start up assuming quiescent state of inputs 117 | scl <= 1; 118 | end 119 | else 120 | begin 121 | sda_sr <= {sda_sr[2:0], sda_in}; 122 | if (sda_sr == 4'b0000) sda <= 0; 123 | else if (sda_sr == 4'b1111) sda <= 1; 124 | scl_sr <= {scl_sr[2:0], scl_in}; 125 | if (scl_sr == 4'b0000) scl <= 0; 126 | else if (scl_sr == 4'b1111) scl <= 1; 127 | end 128 | 129 | // Define states: 130 | localparam pre_start_up = 0, 131 | start_up = 1, 132 | idle = 2, 133 | start = 3, 134 | clock_low = 4, 135 | shift_data = 5, 136 | clock_high = 6, 137 | stop = 7, 138 | spin = 15; 139 | 140 | always @ (posedge sys_clock or posedge reset) 141 | if (reset) 142 | begin 143 | timer <= t_low; 144 | state <= pre_start_up; 145 | rtn_state <= pre_start_up; 146 | ctrl_reg <= 0; 147 | status <= 32'h84000000; // Busy, initializing 148 | shift_reg <= {27{1'b1}}; 149 | bit_count <= 0; 150 | float_sda <= 1; 151 | float_scl <= 1; 152 | wr_cyc <= 1; 153 | read_data <= 0; 154 | scl_startup_count <= 0; 155 | end 156 | else 157 | begin 158 | if (wr_ctrl) 159 | begin 160 | if (status[31]) // busy 161 | begin 162 | status[27] <= 1; // Set overrun flag on unsuccessful attempt to write ctrl_reg 163 | end 164 | else // not busy 165 | begin 166 | ctrl_reg <= ctrl_data; 167 | status[27] <= 0; // Clear overrun flag on successful write to ctrl_reg 168 | end 169 | end 170 | case (state) 171 | // In pre-start-up state wait for SDA to go high while clocking SCL as necessary 172 | pre_start_up: 173 | begin 174 | if (timer == 0) // every 5 us 175 | begin 176 | if (float_scl) 177 | begin 178 | if (sda && (scl_startup_count == 12)) // quiescent? 179 | begin 180 | scl_startup_count <= 0; 181 | state <= start_up; 182 | end 183 | else 184 | begin 185 | float_scl <= 0; // Start another SCL clock cycle if SDA is still low 186 | timer <= t_low; 187 | scl_startup_count <= scl_startup_count + 1; 188 | end 189 | end 190 | else // Currently driving SCL 191 | begin 192 | float_scl <= 1; // Release SCL 193 | timer <= t_low; 194 | end 195 | end 196 | else if (scl | !float_scl) // Start timing after rising edge of SCL if not driven 197 | begin 198 | timer <= timer - 1; 199 | end 200 | end 201 | // In start-up state, generate a start and stop with no clocks in between 202 | start_up: 203 | begin 204 | if (timer == 0) // every 5 us 205 | begin 206 | timer <= t_low; 207 | scl_startup_count <= scl_startup_count + 1; 208 | if (scl_startup_count == 2) float_sda <= 0; // Create a start condition 209 | if (scl_startup_count == 12) float_sda <= 1; // Create a stop condition 210 | if (scl_startup_count == 15) state <= idle; 211 | end 212 | else 213 | begin 214 | timer <= timer - 1; 215 | end 216 | end 217 | idle: 218 | begin 219 | float_sda <= 1; 220 | float_scl <= 1; 221 | wr_cyc <= ~ctrl_data[0]; 222 | status[31] <= 0; // Not busy 223 | status[26] <= 0; // Done initialization 224 | if (wr_ctrl & !status[31]) // successful write to ctrl_reg 225 | begin 226 | state <= start; 227 | status[31] <= 1; // go busy 228 | end 229 | end 230 | start: 231 | begin 232 | // Create high to low transition on SDA. 233 | // Both SDA and SCL were high at least 4.7us before entering this state 234 | float_sda <= 0; 235 | float_scl <= 1; 236 | if (!sda) // Continue when we see sda driven low 237 | begin 238 | // 7-bit ADDR, R/WN, Slave Ack, 8-bit Subaddr, Slave Ack, 8-bit Data, Slave Ack 239 | // Data byte and final Slave Ack do not apply for reads 240 | // For Stop then start, SDA must be low after last ack cycle. 241 | // For repeated start, SDA must be high after last ack cycle. 242 | // Read is currently broken 243 | if (read) // reading requires subaddr write then data read 244 | if (wr_cyc) 245 | shift_reg <= {ctrl_reg[23:17],1'b0,1'b1,ctrl_reg[15:8],1'b1,ctrl_reg[30],7'b0,1'b0,9'b0}; 246 | else 247 | shift_reg <= {ctrl_reg[23:17],1'b1,1'b1,8'hff,1'b1,8'b0,1'b0,9'b0}; 248 | else // Writing 249 | shift_reg <= {ctrl_reg[30:24], 1'b0, 1'b1, ctrl_reg[23:16],1'b1,ctrl_reg[15:8],1'b1,ctrl_reg[7:0],1'b1}; 250 | bit_count <= 0; 251 | timer <= t_hd_sta; // 4.0us from the spec 252 | rtn_state <= clock_low; 253 | state <= spin; 254 | end 255 | end 256 | clock_low: 257 | begin 258 | // Assert SCL low and when it is low, wait for t_hold before changing SDA 259 | float_scl <= 0; 260 | if (!scl) // Continue when SCL line has gone low 261 | begin 262 | timer <= t_hold; // extra 0.5 us for AD9888 263 | rtn_state <= shift_data; 264 | state <= spin; 265 | end 266 | end 267 | shift_data: 268 | begin 269 | // Shift data onto the SDA line 270 | float_sda <= shift_reg[35]; 271 | 272 | shift_reg <= {shift_reg[34:0],1'b0}; // shift left 273 | timer <= t_low; // 4.7us min from spec 274 | rtn_state <= clock_high; 275 | state <= spin; 276 | end 277 | clock_high: 278 | begin 279 | // Release low drive on SCL and when it goes high 280 | // sample SDA and move on 281 | float_scl <= 1; 282 | if (scl) 283 | begin 284 | bit_count <= bit_count + 1; 285 | if (bit_count == 8) // Address ACK cycle 286 | begin 287 | status[30] <= sda; // SDA should be driven low for slave ACK 288 | end 289 | else if ((bit_count == 17) & wr_cyc || (bit_count == 26) || (bit_count == 35)) // Data ACK cycles 290 | begin 291 | status[29] <= sda; // SDA should be driven low for slave ACK 292 | end 293 | if ((bit_count == 18) & read // Reading and past first data ack 294 | || (bit_count == 36) || (ctrl_reg[31] && bit_count == 27)) // Past first or second data ack 295 | begin 296 | timer <= t_su_sto; // 4.0us from spec 297 | rtn_state <= stop; 298 | state <= spin; 299 | end 300 | else 301 | begin 302 | if (bit_count != 17) read_data <= {read_data[6:0],sda}; // shift data in, MSB first 303 | timer <= t_high; // 4.0us from spec, but use 5.0 instead to meet cycle time 304 | rtn_state <= clock_low; 305 | state <= spin; 306 | end 307 | end 308 | end 309 | stop: 310 | begin 311 | // We get here twice for read cycles, once for writes. On reads if 312 | // using repeated start we don't need to wait as long before asserting SDA 313 | // for start since t_su_sto has already elapsed (4.0us) 314 | float_sda <= 1; // SDA will already be high in the case of repeated start 315 | if (sda) 316 | begin 317 | if (read) // reading 318 | begin 319 | if (wr_cyc) // just finished sending subaddress 320 | begin 321 | if (ctrl_reg[30]) // repeated start 322 | timer <= t_su_sta - t_su_sto; 323 | else 324 | timer <= t_su_sta; 325 | rtn_state <= start; 326 | end 327 | else 328 | begin 329 | status[7:0] <= read_data; 330 | status[28] <= 1; 331 | timer <= t_su_sta; // Setup to start is same as bus-free, 4.7us from spec 332 | rtn_state <= idle; // For writes we're all done 333 | end 334 | wr_cyc <= 0; 335 | state <= spin; 336 | end 337 | else // writing 338 | begin 339 | status[28] <= 0; 340 | timer <= t_su_sta; // Setup to start is same as bus-free, 4.7us from spec 341 | rtn_state <= idle; // For writes we're all done 342 | state <= spin; 343 | end 344 | end 345 | end 346 | spin: 347 | begin 348 | // stay in this state for requested time period then "return" 349 | if (timer > 0) 350 | begin 351 | timer <= timer - 1; 352 | end 353 | else 354 | begin 355 | state <= rtn_state; 356 | end 357 | end 358 | endcase 359 | end 360 | 361 | endmodule 362 | -------------------------------------------------------------------------------- /nunchuk/PushButton_Debouncer.v: -------------------------------------------------------------------------------- 1 | module PushButton_Debouncer( 2 | input clk, 3 | input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal 4 | 5 | // from which we make three outputs, all synchronous to the clock 6 | output reg PB_state, // 1 as long as the push-button is active (down) 7 | output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed) 8 | output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released) 9 | ); 10 | 11 | // First use two flip-flops to synchronize the PB signal the "clk" clock domain 12 | reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high 13 | reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0; 14 | 15 | // Next declare a 16-bits counter 16 | reg [15:0] PB_cnt; 17 | 18 | // When the push-button is pushed or released, we increment the counter 19 | // The counter has to be maxed out before we decide that the push-button state has changed 20 | 21 | wire PB_idle = (PB_state==PB_sync_1); 22 | wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's 23 | 24 | always @(posedge clk) 25 | if(PB_idle) 26 | PB_cnt <= 0; // nothing's going on 27 | else 28 | begin 29 | PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter 30 | if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed! 31 | end 32 | 33 | assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state; 34 | assign PB_up = ~PB_idle & PB_cnt_max & PB_state; 35 | endmodule 36 | -------------------------------------------------------------------------------- /nunchuk/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /nunchuk/decoder_7_seg_hex.v: -------------------------------------------------------------------------------- 1 | module decoder_7_seg_hex( 2 | input clk, 3 | input [3:0] data, 4 | output reg [6:0] seg 5 | ); 6 | 7 | always @(posedge clk) begin 8 | case(data) 9 | 'h0: seg <= 'b1111110; 10 | 'h1: seg <= 'b0000110; 11 | 'h2: seg <= 'b1101101; 12 | 'h3: seg <= 'b1001111; 13 | 'h4: seg <= 'b0010111; 14 | 'h5: seg <= 'b1011011; 15 | 'h6: seg <= 'b1111011; 16 | 'h7: seg <= 'b0001110; 17 | 'h8: seg <= 'b1111111; 18 | 'h9: seg <= 'b1011111; 19 | 'hA: seg <= 'b0111111; 20 | 'hB: seg <= 'b1110011; 21 | 'hC: seg <= 'b1111000; 22 | 'hD: seg <= 'b1100111; 23 | 'hE: seg <= 'b1111001; 24 | 'hF: seg <= 'b0111001; 25 | endcase 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /nunchuk/display_7_seg_hex.v: -------------------------------------------------------------------------------- 1 | module display_7_seg_hex( 2 | input clk, 3 | input [7:0] value, 4 | output [6:0] seg, 5 | output reg digit 6 | ); 7 | 8 | reg [3:0] data; 9 | reg posn; 10 | reg [23:0] prescaler; 11 | 12 | decoder_7_seg_hex decoder(.clk (clk), .seg(seg), .data(data)); 13 | 14 | always @(posedge clk) begin 15 | prescaler <= prescaler + 1; 16 | if (prescaler == 8000) begin // 1khz 17 | prescaler <= 0; 18 | posn <= posn + 1; 19 | if (posn == 1) begin 20 | data <= value[7:4]; 21 | digit <= 0; 22 | end else if (posn == 0) begin 23 | data <= value[3:0]; 24 | digit <= 1; 25 | end 26 | end 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /nunchuk/pins.pcf: -------------------------------------------------------------------------------- 1 | set_io digit C9 2 | set_io seg[0] A9 3 | set_io seg[1] B8 4 | set_io seg[2] A8 5 | set_io seg[3] B7 6 | set_io seg[4] A7 7 | set_io seg[5] B6 8 | set_io seg[6] A6 9 | 10 | set_io button H2 11 | 12 | set_io scl A2 13 | set_io sda A1 14 | 15 | set_io usbpu A3 16 | set_io clk B2 17 | -------------------------------------------------------------------------------- /nunchuk/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clk, 3 | output [6:0] seg, 4 | output digit, 5 | input button, 6 | inout sda, 7 | inout scl, 8 | output usbpu 9 | ); 10 | // Disable USB 11 | assign usbpu = 0; 12 | reg [7:0] v; 13 | wire PB, pressed; 14 | 15 | SB_IO #( 16 | .PIN_TYPE(6'b 1010_01), 17 | .PULLUP(1'b 1) 18 | ) pbin ( 19 | .PACKAGE_PIN(button), 20 | .D_IN_0(PB) 21 | ); 22 | 23 | PushButton_Debouncer pb1 (.clk(clk), .PB(PB), .PB_down(pressed)); 24 | 25 | always @(posedge clk) if (pressed) v <= v + 1; 26 | 27 | // Display value as hex 28 | display_7_seg_hex seghex (.clk(clk), .value(status[7:0]), .seg(seg), .digit(digit)); 29 | 30 | wire enable; 31 | reg read; 32 | reg [31:0] data = 0, status; 33 | reg started = 0; 34 | reg [23:0] reset_timer = 0; 35 | wire reset = !(&reset_timer); 36 | reg [23:0] counter; 37 | 38 | always @(posedge clk) begin 39 | if (reset) reset_timer <= reset_timer + 1; 40 | else begin 41 | enable <= 0; 42 | counter <= counter + 1; 43 | if (counter == {23{1'b1}}) begin 44 | data[31] <= 1'b1; 45 | data[30:24] <= 7'h52; 46 | data[23:16] <= (started ? 8'h00 : 8'h40); 47 | data[15:8] <= 8'h00; 48 | read <= 0; 49 | enable <= 1; 50 | if (!started) started <= 1; 51 | end else if (!status[31] && counter == 0) begin 52 | data <= 0; 53 | data[0] <= 1; 54 | data[23:17] <= 7'h52; 55 | enable <= 1; 56 | read <= 1; 57 | end 58 | end 59 | end 60 | 61 | I2C_master #(.freq(16)) nunchuk ( 62 | .sys_clock(clk), 63 | .SDA(sda), 64 | .SCL(scl), 65 | .reset(reset), 66 | .ctrl_data(data), 67 | .wr_ctrl(enable), 68 | .read(read), 69 | .status (status) 70 | ); 71 | endmodule 72 | -------------------------------------------------------------------------------- /pong/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /pong/hvsync_generator.v: -------------------------------------------------------------------------------- 1 | module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY); 2 | input clk; 3 | output vga_h_sync, vga_v_sync; 4 | output inDisplayArea; 5 | output [9:0] CounterX; 6 | output [8:0] CounterY; 7 | 8 | ////////////////////////////////////////////////// 9 | reg [9:0] CounterX; 10 | reg [8:0] CounterY; 11 | wire CounterXmaxed = (CounterX==10'h2FF); 12 | 13 | always @(posedge clk) 14 | if(CounterXmaxed) 15 | CounterX <= 0; 16 | else 17 | CounterX <= CounterX + 1; 18 | 19 | always @(posedge clk) 20 | if(CounterXmaxed) CounterY <= CounterY + 1; 21 | 22 | reg vga_HS, vga_VS; 23 | always @(posedge clk) 24 | begin 25 | vga_HS <= (CounterX[9:4]==6'h2D); // change this value to move the display horizontally 26 | vga_VS <= (CounterY==500); // change this value to move the display vertically 27 | end 28 | 29 | reg inDisplayArea; 30 | always @(posedge clk) 31 | if(inDisplayArea==0) 32 | inDisplayArea <= (CounterXmaxed) && (CounterY<480); 33 | else 34 | inDisplayArea <= !(CounterX==639); 35 | 36 | assign vga_h_sync = ~vga_HS; 37 | assign vga_v_sync = ~vga_VS; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /pong/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /pong/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /pong/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io -nowarn PIN_1 A2 42 | set_io -nowarn PIN_2 A1 43 | set_io -nowarn PIN_3 B1 44 | set_io -nowarn PIN_4 C2 45 | set_io -nowarn PIN_5 C1 46 | set_io -nowarn PIN_6 D2 47 | set_io -nowarn PIN_7 D1 48 | set_io -nowarn PIN_8 E2 49 | set_io -nowarn PIN_9 E1 50 | set_io -nowarn PIN_10 G2 51 | set_io -nowarn PIN_11 H1 52 | set_io -nowarn PIN_12 J1 53 | set_io -nowarn PIN_13 H2 54 | 55 | # Right side of board 56 | set_io -nowarn PIN_14 H9 57 | set_io -nowarn PIN_15 D9 58 | set_io -nowarn PIN_16 D8 59 | set_io -nowarn PIN_17 C9 60 | set_io -nowarn PIN_18 A9 61 | set_io -nowarn PIN_19 B8 62 | set_io -nowarn PIN_20 A8 63 | set_io -nowarn PIN_21 B7 64 | set_io -nowarn PIN_22 A7 65 | set_io -nowarn PIN_23 B6 66 | set_io -nowarn PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io -nowarn SPI_SS F7 70 | set_io -nowarn SPI_SCK G7 71 | set_io -nowarn SPI_IO0 G6 72 | set_io -nowarn SPI_IO1 H7 73 | set_io -nowarn SPI_IO2 H4 74 | set_io -nowarn SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io -nowarn PIN_25 G1 78 | set_io -nowarn PIN_26 J3 79 | set_io -nowarn PIN_27 J4 80 | set_io -nowarn PIN_28 G9 81 | set_io -nowarn PIN_29 J9 82 | set_io -nowarn PIN_30 E8 83 | set_io -nowarn PIN_31 J2 84 | 85 | # LED 86 | set_io -nowarn LED B3 87 | 88 | # USB 89 | set_io -nowarn USBP B4 90 | set_io -nowarn USBN A4 91 | set_io -nowarn USBPU A3 92 | 93 | # 16MHz clock 94 | set_io -nowarn CLK B2 # input 95 | 96 | set_io clk_16 B2 97 | set_io vga_R H1 98 | set_io vga_G J1 99 | set_io vga_B H2 100 | set_io vga_h_sync G2 101 | set_io vga_v_sync E1 102 | set_io quadA D1 103 | set_io quadB E2 104 | -------------------------------------------------------------------------------- /pong/top.v: -------------------------------------------------------------------------------- 1 | // Pong VGA game 2 | // (c) fpga4fun.com 3 | 4 | module pong(clk_16, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, quadA, quadB, USBPU); 5 | input clk_16; 6 | output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B; 7 | input quadA, quadB; 8 | output USBPU; 9 | 10 | wire inDisplayArea; 11 | wire [9:0] CounterX; 12 | wire [8:0] CounterY; 13 | wire locked, clk; 14 | 15 | assign USBPU = 0; 16 | 17 | SB_PLL40_CORE #( 18 | .FEEDBACK_PATH("SIMPLE"), 19 | .DIVR(4'b0000), // DIVR = 0 20 | .DIVF(7'b0110001), // DIVF = 49 21 | .DIVQ(3'b101), // DIVQ = 5 22 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 23 | ) uut ( 24 | .LOCK(locked), 25 | .RESETB(1'b1), 26 | .BYPASS(1'b0), 27 | .REFERENCECLK(clk_16), 28 | .PLLOUTCORE(clk) 29 | ); 30 | 31 | 32 | hvsync_generator syncgen(.clk(clk), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), 33 | .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY)); 34 | 35 | ///////////////////////////////////////////////////////////////// 36 | reg [8:0] PaddlePosition; 37 | reg [2:0] quadAr, quadBr; 38 | always @(posedge clk) quadAr <= {quadAr[1:0], quadA}; 39 | always @(posedge clk) quadBr <= {quadBr[1:0], quadB}; 40 | 41 | always @(posedge clk) 42 | if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1]) 43 | begin 44 | if(quadAr[2] ^ quadBr[1]) 45 | begin 46 | if(~&PaddlePosition) // make sure the value doesn't overflow 47 | PaddlePosition <= PaddlePosition + 1; 48 | end 49 | else 50 | begin 51 | if(|PaddlePosition) // make sure the value doesn't underflow 52 | PaddlePosition <= PaddlePosition - 1; 53 | end 54 | end 55 | 56 | ///////////////////////////////////////////////////////////////// 57 | reg [9:0] ballX; 58 | reg [8:0] ballY; 59 | reg ball_inX, ball_inY; 60 | 61 | always @(posedge clk) 62 | if(ball_inX==0) ball_inX <= (CounterX==ballX) & ball_inY; else ball_inX <= !(CounterX==ballX+16); 63 | 64 | always @(posedge clk) 65 | if(ball_inY==0) ball_inY <= (CounterY==ballY); else ball_inY <= !(CounterY==ballY+16); 66 | 67 | wire ball = ball_inX & ball_inY; 68 | 69 | ///////////////////////////////////////////////////////////////// 70 | wire border = (CounterX[9:3]==0) || (CounterX[9:3]==79) || (CounterY[8:3]==0) || (CounterY[8:3]==59); 71 | wire paddle = (CounterX>=PaddlePosition+8) && (CounterX<=PaddlePosition+120) && (CounterY[8:4]==27); 72 | wire BouncingObject = border | paddle; // active if the border or paddle is redrawing itself 73 | 74 | reg ResetCollision; 75 | always @(posedge clk) ResetCollision <= (CounterY==500) & (CounterX==0); // active only once for every video frame 76 | 77 | reg CollisionX1, CollisionX2, CollisionY1, CollisionY2; 78 | always @(posedge clk) if(ResetCollision) CollisionX1<=0; else if(BouncingObject & (CounterX==ballX ) & (CounterY==ballY+ 8)) CollisionX1<=1; 79 | always @(posedge clk) if(ResetCollision) CollisionX2<=0; else if(BouncingObject & (CounterX==ballX+16) & (CounterY==ballY+ 8)) CollisionX2<=1; 80 | always @(posedge clk) if(ResetCollision) CollisionY1<=0; else if(BouncingObject & (CounterX==ballX+ 8) & (CounterY==ballY )) CollisionY1<=1; 81 | always @(posedge clk) if(ResetCollision) CollisionY2<=0; else if(BouncingObject & (CounterX==ballX+ 8) & (CounterY==ballY+16)) CollisionY2<=1; 82 | 83 | ///////////////////////////////////////////////////////////////// 84 | wire UpdateBallPosition = ResetCollision; // update the ball position at the same time that we reset the collision detectors 85 | 86 | reg ball_dirX, ball_dirY; 87 | always @(posedge clk) 88 | if(UpdateBallPosition) 89 | begin 90 | if(~(CollisionX1 & CollisionX2)) // if collision on both X-sides, don't move in the X direction 91 | begin 92 | ballX <= ballX + (ball_dirX ? -1 : 1); 93 | if(CollisionX2) ball_dirX <= 1; else if(CollisionX1) ball_dirX <= 0; 94 | end 95 | 96 | if(~(CollisionY1 & CollisionY2)) // if collision on both Y-sides, don't move in the Y direction 97 | begin 98 | ballY <= ballY + (ball_dirY ? -1 : 1); 99 | if(CollisionY2) ball_dirY <= 1; else if(CollisionY1) ball_dirY <= 0; 100 | end 101 | end 102 | 103 | ///////////////////////////////////////////////////////////////// 104 | wire R = BouncingObject | ball | (CounterX[3] ^ CounterY[3]); 105 | wire G = BouncingObject | ball; 106 | wire B = BouncingObject | ball; 107 | 108 | reg vga_R, vga_G, vga_B; 109 | always @(posedge clk) 110 | begin 111 | vga_R <= R & inDisplayArea; 112 | vga_G <= G & inDisplayArea; 113 | vga_B <= B & inDisplayArea; 114 | end 115 | 116 | endmodule 117 | -------------------------------------------------------------------------------- /shiftout/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /shiftout/pins.pcf: -------------------------------------------------------------------------------- 1 | set_io shiftout_data A2 2 | set_io shiftout_clock A1 3 | set_io shiftout_latch B1 4 | 5 | set_io -nowarn USBPU A3 6 | 7 | # 16MHz clock 8 | set_io -nowarn clk_16Mhz B2 # input 9 | -------------------------------------------------------------------------------- /shiftout/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk_16Mhz, 3 | output USBPU, 4 | output shiftout_clock, 5 | output reg shiftout_latch, 6 | output shiftout_data); 7 | 8 | assign USBPU = 0; 9 | 10 | reg [7:0] shift_reg = 0; 11 | 12 | assign shiftout_data = shift_reg[7]; 13 | 14 | reg [1:0] divider; 15 | wire clk = divider[1]; 16 | 17 | always @(posedge clk_16Mhz) divider <= divider + 1; 18 | 19 | assign shiftout_clock = clk; 20 | 21 | reg [20:0] delay_counter; 22 | 23 | reg [2:0] bit_counter = 0; 24 | reg [7:0] data_out = 0; 25 | 26 | always @(negedge clk) begin 27 | // When delay counter is zero shift out the data 28 | if (delay_counter == 0) begin 29 | shift_reg <= shift_reg << 1; 30 | bit_counter <= bit_counter + 1; 31 | if (bit_counter == 7) begin 32 | // Show the value and restart the delay counter 33 | shiftout_latch <= 1; 34 | delay_counter <= 1; 35 | // Increment data out to show increasing numbers 36 | data_out <= data_out + 1; 37 | end 38 | end else begin 39 | delay_counter <= delay_counter + 1; 40 | // When delay counter is maxed out, prepare to shift out next value 41 | if (&delay_counter) begin 42 | shiftout_latch <= 0; 43 | shift_reg <= data_out; 44 | end 45 | end 46 | end 47 | endmodule 48 | -------------------------------------------------------------------------------- /tone/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /tone/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /tone/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /tone/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io -nowarn PIN_1 A2 42 | set_io -nowarn PIN_2 A1 43 | set_io -nowarn PIN_3 B1 44 | set_io -nowarn PIN_4 C2 45 | set_io -nowarn PIN_5 C1 46 | set_io -nowarn PIN_6 D2 47 | set_io -nowarn PIN_7 D1 48 | set_io -nowarn PIN_8 E2 49 | set_io -nowarn PIN_9 E1 50 | set_io -nowarn PIN_10 G2 51 | set_io -nowarn PIN_11 H1 52 | set_io -nowarn PIN_12 J1 53 | set_io -nowarn PIN_13 H2 54 | 55 | # Right side of board 56 | set_io -nowarn PIN_14 H9 57 | set_io -nowarn PIN_15 D9 58 | set_io -nowarn PIN_16 D8 59 | set_io -nowarn PIN_17 C9 60 | set_io -nowarn PIN_18 A9 61 | set_io -nowarn PIN_19 B8 62 | set_io -nowarn PIN_20 A8 63 | set_io -nowarn PIN_21 B7 64 | set_io -nowarn PIN_22 A7 65 | set_io -nowarn PIN_23 B6 66 | set_io -nowarn PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io -nowarn SPI_SS F7 70 | set_io -nowarn SPI_SCK G7 71 | set_io -nowarn SPI_IO0 G6 72 | set_io -nowarn SPI_IO1 H7 73 | set_io -nowarn SPI_IO2 H4 74 | set_io -nowarn SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io -nowarn PIN_25 G1 78 | set_io -nowarn PIN_26 J3 79 | set_io -nowarn PIN_27 J4 80 | set_io -nowarn PIN_28 G9 81 | set_io -nowarn PIN_29 J9 82 | set_io -nowarn PIN_30 E8 83 | set_io -nowarn PIN_31 J2 84 | 85 | # LED 86 | set_io -nowarn LED B3 87 | 88 | # USB 89 | set_io -nowarn USBP B4 90 | set_io -nowarn USBN A4 91 | set_io -nowarn USBPU A3 92 | 93 | # 16MHz clock 94 | set_io -nowarn CLK B2 # input 95 | -------------------------------------------------------------------------------- /tone/tone.v: -------------------------------------------------------------------------------- 1 | module tone( 2 | input clk, 3 | input [31:0] duration, // millis 4 | input [31:0] freq, //hz 5 | output reg tone_out, // pin 6 | output reg done 7 | ); 8 | 9 | parameter CLK_F = 16; // CLK freq in MHz 10 | 11 | reg [7:0] prescaler = 0; 12 | reg [31:0] tone_counter = 0; 13 | reg [31:0] time_counter = 0; 14 | reg [31:0] millis = 0; 15 | wire [31:0] period = 1000000 / freq; 16 | 17 | always @(posedge clk) if (duration > 0) begin 18 | if (time_counter == CLK_F * 1000 - 1) begin 19 | millis <= millis + 1; 20 | time_counter <= 0; 21 | end else time_counter <= time_counter + 1; 22 | 23 | if (millis < duration) begin 24 | prescaler <= prescaler + 1; 25 | if (prescaler == CLK_F / 2 - 1) begin 26 | prescaler <= 0; 27 | tone_counter <= tone_counter + 1; 28 | if (tone_counter >= period - 1) begin 29 | tone_counter <= 0; 30 | tone_out <= ~tone_out; 31 | end 32 | end 33 | end else begin 34 | tone_out <= 0; 35 | done = 1; 36 | end 37 | end else begin 38 | millis <= 0; 39 | done <= 0; 40 | prescaler <= 0; 41 | time_counter <= 0; 42 | tone_counter <= 0; 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /tone/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top( 3 | input CLK, 4 | output PIN_1, 5 | output USBPU 6 | ); 7 | 8 | assign USBPU = 0; 9 | 10 | localparam G = 440, Ef = 311, F = 349, D = 294; 11 | 12 | reg [31:0] frequency; 13 | reg [31:0] duration = 0; 14 | reg [21:0] beat_counter = 0; 15 | reg [2:0] note_counter = 0; 16 | reg bar_counter = 0; 17 | 18 | wire done; 19 | 20 | always @(posedge CLK) begin 21 | if (beat_counter == 0) begin 22 | note_counter <= note_counter + 1; 23 | if (note_counter == 7) bar_counter <= bar_counter + 1; 24 | if (note_counter == 4) begin 25 | duration <= 400; 26 | frequency = 1000; 27 | //frequency <= (bar_counter == 0 ? Ef : D); 28 | end else if (note_counter > 0 && note_counter < 4) begin 29 | duration <= 40; 30 | //frequency <= (bar_counter == 0 ? G : F); 31 | end else duration <= 0; 32 | end 33 | beat_counter <= beat_counter + 1; 34 | if (done) duration <= 0; 35 | end 36 | 37 | tone t(.clk (CLK), .duration(duration), .freq (frequency), .tone_out (PIN_1), .done(done)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /uart_test/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /uart_test/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /uart_test/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /uart_test/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io -nowarn PIN_1 A2 42 | set_io -nowarn PIN_2 A1 43 | set_io -nowarn PIN_3 B1 44 | set_io -nowarn PIN_4 C2 45 | set_io -nowarn PIN_5 C1 46 | set_io -nowarn PIN_6 D2 47 | set_io -nowarn PIN_7 D1 48 | set_io -nowarn PIN_8 E2 49 | set_io -nowarn PIN_9 E1 50 | set_io -nowarn PIN_10 G2 51 | set_io -nowarn PIN_11 H1 52 | set_io -nowarn PIN_12 J1 53 | set_io -nowarn PIN_13 H2 54 | 55 | # Right side of board 56 | set_io -nowarn PIN_14 H9 57 | set_io -nowarn PIN_15 D9 58 | set_io -nowarn PIN_16 D8 59 | set_io -nowarn PIN_17 C9 60 | set_io -nowarn PIN_18 A9 61 | set_io -nowarn PIN_19 B8 62 | set_io -nowarn PIN_20 A8 63 | set_io -nowarn PIN_21 B7 64 | set_io -nowarn PIN_22 A7 65 | set_io -nowarn PIN_23 B6 66 | set_io -nowarn PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io -nowarn SPI_SS F7 70 | set_io -nowarn SPI_SCK G7 71 | set_io -nowarn SPI_IO0 G6 72 | set_io -nowarn SPI_IO1 H7 73 | set_io -nowarn SPI_IO2 H4 74 | set_io -nowarn SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io -nowarn PIN_25 G1 78 | set_io -nowarn PIN_26 J3 79 | set_io -nowarn PIN_27 J4 80 | set_io -nowarn PIN_28 G9 81 | set_io -nowarn PIN_29 J9 82 | set_io -nowarn PIN_30 E8 83 | set_io -nowarn PIN_31 J2 84 | 85 | # LED 86 | set_io -nowarn LED B3 87 | 88 | # USB 89 | set_io -nowarn USBP B4 90 | set_io -nowarn USBN A4 91 | set_io -nowarn USBPU A3 92 | 93 | # 16MHz clock 94 | set_io -nowarn CLK B2 # input 95 | -------------------------------------------------------------------------------- /uart_test/simpleuart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module simpleuart ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | input ser_rx, 26 | 27 | input reg_dat_we, 28 | input reg_dat_re, 29 | input [7:0] reg_dat_di, 30 | output [7:0] reg_dat_do, 31 | output reg_dat_wait, 32 | input [31:0] cfg_divider 33 | ); 34 | 35 | reg [3:0] recv_state; 36 | reg [31:0] recv_divcnt; 37 | reg [7:0] recv_pattern; 38 | reg [7:0] recv_buf_data; 39 | reg recv_buf_valid; 40 | 41 | reg [9:0] send_pattern; 42 | reg [3:0] send_bitcnt; 43 | reg [31:0] send_divcnt; 44 | reg send_dummy; 45 | 46 | assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); 47 | assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; 48 | 49 | always @(posedge clk) begin 50 | if (!resetn) begin 51 | recv_state <= 0; 52 | recv_divcnt <= 0; 53 | recv_pattern <= 0; 54 | recv_buf_data <= 0; 55 | recv_buf_valid <= 0; 56 | end else begin 57 | recv_divcnt <= recv_divcnt + 1; 58 | if (reg_dat_re) 59 | recv_buf_valid <= 0; 60 | case (recv_state) 61 | 0: begin 62 | if (!ser_rx) 63 | recv_state <= 1; 64 | recv_divcnt <= 0; 65 | end 66 | 1: begin 67 | if (2*recv_divcnt > cfg_divider) begin 68 | recv_state <= 2; 69 | recv_divcnt <= 0; 70 | end 71 | end 72 | 10: begin 73 | if (recv_divcnt > cfg_divider) begin 74 | recv_buf_data <= recv_pattern; 75 | recv_buf_valid <= 1; 76 | recv_state <= 0; 77 | end 78 | end 79 | default: begin 80 | if (recv_divcnt > cfg_divider) begin 81 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 82 | recv_state <= recv_state + 1; 83 | recv_divcnt <= 0; 84 | end 85 | end 86 | endcase 87 | end 88 | end 89 | 90 | assign ser_tx = send_pattern[0]; 91 | 92 | always @(posedge clk) begin 93 | send_divcnt <= send_divcnt + 1; 94 | if (!resetn) begin 95 | send_pattern <= ~0; 96 | send_bitcnt <= 0; 97 | send_divcnt <= 0; 98 | send_dummy <= 1; 99 | end else begin 100 | if (send_dummy && !send_bitcnt) begin 101 | send_pattern <= ~0; 102 | send_bitcnt <= 15; 103 | send_divcnt <= 0; 104 | send_dummy <= 0; 105 | end else if (reg_dat_we && !send_bitcnt) begin 106 | send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; 107 | send_bitcnt <= 10; 108 | send_divcnt <= 0; 109 | end else if (send_divcnt > cfg_divider && send_bitcnt) begin 110 | send_pattern <= {1'b1, send_pattern[9:1]}; 111 | send_bitcnt <= send_bitcnt - 1; 112 | send_divcnt <= 0; 113 | end 114 | end 115 | end 116 | endmodule 117 | -------------------------------------------------------------------------------- /uart_test/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | input PIN_2, 5 | output USBPU, 6 | output PIN_1 7 | ); 8 | 9 | // Disable USB 10 | assign USBPU = 0; 11 | 12 | wire clk = CLK; 13 | reg [7:0] reg_dat_di; 14 | wire [7:0] reg_dat_do; 15 | reg reg_dat_re, reg_dat_we; 16 | wire reg_dat_wait; 17 | reg wait_for_send; 18 | 19 | // Generate reset signal 20 | reg [5:0] reset_cnt = 0; 21 | wire resetn = &reset_cnt; 22 | 23 | always @(posedge clk) begin 24 | reset_cnt <= reset_cnt + !resetn; 25 | end 26 | 27 | // Create the text string 28 | reg [7:0] text [0:12]; 29 | 30 | initial begin 31 | text[0] <= "H"; 32 | text[1] <= "e"; 33 | text[2] <= "l"; 34 | text[3] <= "l"; 35 | text[4] <= "o"; 36 | text[5] <= " "; 37 | text[6] <= "W"; 38 | text[7] <= "o"; 39 | text[8] <= "r"; 40 | text[9] <= "l"; 41 | text[10] <= "d"; 42 | text[11] <= "!"; 43 | text[12] <= "\n"; 44 | end 45 | 46 | // Send characters about every second 47 | reg [22:0] delay_count; 48 | reg [3:0] char_count; 49 | 50 | always @(posedge clk) begin 51 | delay_count <= delay_count + 1; 52 | if (resetn && !wait_for_send) begin 53 | if (&delay_count) begin 54 | if (char_count == 12) char_count <= 0; 55 | else char_count <= char_count + 1; 56 | reg_dat_di <= text[char_count]; 57 | reg_dat_we <= 1; 58 | wait_for_send <= 1; 59 | end 60 | end else if (!reg_dat_wait) begin 61 | reg_dat_we <= 0; 62 | wait_for_send <= 0; 63 | end 64 | end 65 | 66 | // uart from picosoc 67 | simpleuart uart ( 68 | .clk (clk), 69 | .resetn (resetn), 70 | 71 | .ser_tx (PIN_1), 72 | .ser_rx (PIN_2), 73 | 74 | .cfg_divider(139), 75 | 76 | .reg_dat_we (reg_dat_we), 77 | .reg_dat_re (reg_dat_re), 78 | .reg_dat_di (reg_dat_di), 79 | .reg_dat_do (reg_dat_do), 80 | .reg_dat_wait(reg_dat_wait) 81 | ); 82 | 83 | endmodule 84 | --------------------------------------------------------------------------------