├── README.md ├── basics ├── Makefile ├── led │ ├── Makefile │ └── top.v ├── sum │ ├── Makefile │ └── top.v ├── sum_vhdl │ ├── Makefile │ ├── ulx3s.mk │ └── top.vhd ├── button │ ├── Makefile │ └── top.v ├── counter │ ├── Makefile │ └── top.v ├── debounce │ ├── Makefile │ └── top.v ├── trigger │ ├── Makefile │ └── top.v └── top.v ├── .gitignore ├── ps2port ├── ps2_port.v ├── byte_to_hex.v ├── Makefile ├── debug.v ├── ps2_test.v └── uart_tx.v ├── riscv ├── console │ ├── firmware.elf │ ├── Makefile │ ├── sections.lds │ ├── firmware.s │ ├── makehex.py │ ├── start.s │ └── firmware.c ├── Makefile ├── top.v ├── blinky │ ├── Makefile │ ├── sections.lds │ ├── firmware.s │ └── makehex.py └── pll.v ├── sdram8 ├── Makefile └── ulx3s.mk ├── st7789 ├── README.md ├── Makefile ├── st7789_init.mem ├── top_checkered.v ├── top_hex_demo.v └── oled_font.mem ├── hdmi ├── menu │ ├── software │ │ ├── firmware.elf │ │ ├── delay.h │ │ ├── Makefile │ │ ├── sdcard.h │ │ ├── sections.lds │ │ ├── firmware.s │ │ ├── makehex.py │ │ ├── flash.h │ │ ├── start.s │ │ └── flash.c │ ├── font_rom.v │ ├── Makefile │ ├── makehex.py │ ├── sdcard.v │ ├── flash_write.v │ ├── PushButton_Debouncer.v │ └── spi_master.v ├── color │ ├── Makefile │ ├── top.v │ └── pll.v ├── checkers │ ├── Makefile │ ├── top.v │ └── pll.v ├── tricolor │ ├── Makefile │ ├── top.v │ └── pll.v ├── text │ ├── Makefile │ ├── font_rom.v │ ├── top.v │ └── pll.v ├── buffer │ ├── Makefile │ ├── font_rom.v │ ├── top.v │ └── pll.v ├── sprite │ ├── Makefile │ ├── sprite_rom.v │ ├── pll.v │ └── top.v ├── terminal │ ├── Makefile │ ├── font_rom.v │ ├── pll.v │ ├── uart_rx.v │ └── top.v ├── pll.v ├── clk_25_250_125_25.v ├── fake_differential.v ├── vga_video.v └── hdmi_video.v ├── audio ├── piano │ ├── Makefile │ └── audio.v └── sound │ ├── Makefile │ └── audio.v ├── test68 ├── Makefile └── ulx3s.mk ├── oled ├── Makefile ├── top_checkered.v ├── oled_init_16bit.mem └── oled_video.v ├── protocols ├── spidisplay │ ├── Makefile │ ├── pll.v │ ├── uart_tx.v │ └── uart_rx.v ├── serialtx │ ├── Makefile │ ├── top.v │ └── uart_tx.v └── echo │ ├── Makefile │ ├── top.v │ ├── uart_tx.v │ └── uart_rx.v ├── video ├── color │ ├── Makefile │ ├── top.v │ └── pll.v ├── checkers │ ├── Makefile │ ├── top.v │ └── pll.v ├── tricolor │ ├── Makefile │ ├── top.v │ └── pll.v ├── buffer │ ├── Makefile │ ├── font_rom.v │ ├── pll.v │ └── top.v ├── text │ ├── Makefile │ ├── font_rom.v │ ├── pll.v │ └── top.v ├── sprite │ ├── Makefile │ ├── sprite_rom.v │ ├── pll.v │ └── top.v └── terminal │ ├── Makefile │ ├── font_rom.v │ ├── pll.v │ ├── uart_rx.v │ └── top.v ├── pong ├── ball │ ├── Makefile │ └── pll.v ├── game │ ├── Makefile │ ├── pll.v │ └── numbers.list ├── move │ ├── Makefile │ ├── pll.v │ └── top.v ├── wall │ ├── Makefile │ └── pll.v └── pll.v ├── st7735 ├── Makefile ├── top_checkered.v ├── st7735_init.mem ├── top_hex_demo.v └── oled_font.mem ├── cpu ├── Makefile ├── grom_top.v ├── grom_computer_tb.v ├── grom_computer.v ├── ram_memory.v └── alu.v ├── ps2 ├── byte_to_hex.v ├── Makefile ├── debug.v ├── ps2_test.v └── uart_tx.v ├── computer ├── Makefile ├── rom_memory.v ├── top_altair.v ├── ram_memory.v ├── jmp_boot.v ├── mc6850.v └── turnmon.bin.mem ├── ledpanel ├── palette.raw └── sprite_rom.v ├── sdram16 ├── Makefile ├── ulx3s.mk └── spi_display │ ├── st7789_linit_xflip.mem │ └── hex_font.mem ├── pong-hdmi ├── ball │ └── Makefile ├── game │ ├── Makefile │ └── numbers.list ├── move │ ├── Makefile │ └── top.v ├── wall │ └── Makefile ├── pll.v ├── clk_25_250_125_25.v ├── fake_differential.v ├── vga_video.v └── hdmi_video.v ├── ps2send ├── Makefile ├── BaudTickGen.v ├── tb.v ├── PushButton_Debouncer.v └── ps2_send.v ├── usbhost ├── UsbHidTest.v_toplevel_coreArea_usbHostHid_C_setup_rom.bin ├── Makefile ├── st7789_init.mem ├── usbh_setup_rom.mem ├── usbh_crc5.v ├── ssd1331_linit_xflip_16bit.mem ├── usbh_crc16.v ├── hex_font.mem ├── clk_25_125_48_6_25.v └── usb_phy.v ├── usbemard ├── Makefile ├── st7789_init.mem ├── usbh_setup_rom.mem ├── ssd1331_linit_xflip_16bit.mem ├── hex_font.mem ├── clk_25_125_48_6_25.v └── usbh_crc5.v └── ulx3s.mk /README.md: -------------------------------------------------------------------------------- 1 | # ulx3s_examples 2 | Example Verilog code for Ulx3s 3 | -------------------------------------------------------------------------------- /basics/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | 3 | include ../ulx3s.mk 4 | 5 | 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bin/ 2 | *.vcd 3 | tb 4 | firmware.bin 5 | firmware.hex 6 | 7 | 8 | -------------------------------------------------------------------------------- /ps2port/ps2_port.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lawrie/ulx3s_examples/HEAD/ps2port/ps2_port.v -------------------------------------------------------------------------------- /basics/led/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | DEVICE = 85k 3 | 4 | include ../../ulx3s.mk 5 | 6 | 7 | -------------------------------------------------------------------------------- /basics/sum/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | DEVICE = 85k 3 | 4 | include ../../ulx3s.mk 5 | 6 | 7 | -------------------------------------------------------------------------------- /basics/sum_vhdl/Makefile: -------------------------------------------------------------------------------- 1 | VHDL = top.vhd 2 | DEVICE = 85k 3 | 4 | include ulx3s.mk 5 | 6 | 7 | -------------------------------------------------------------------------------- /basics/button/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | DEVICE = 12k 3 | 4 | include ../../ulx3s.mk 5 | 6 | 7 | -------------------------------------------------------------------------------- /basics/counter/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | DEVICE = 85k 3 | 4 | include ../../ulx3s.mk 5 | 6 | 7 | -------------------------------------------------------------------------------- /riscv/console/firmware.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lawrie/ulx3s_examples/HEAD/riscv/console/firmware.elf -------------------------------------------------------------------------------- /sdram8/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = testram.v ecp5pll.sv sdram.v 2 | DEVICE = 85k 3 | 4 | include ulx3s.mk 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /st7789/README.md: -------------------------------------------------------------------------------- 1 | # ST7789 Display driver 2 | 3 | Not yet working, but the similar ST7735 version does work. 4 | 5 | -------------------------------------------------------------------------------- /hdmi/menu/software/firmware.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lawrie/ulx3s_examples/HEAD/hdmi/menu/software/firmware.elf -------------------------------------------------------------------------------- /audio/piano/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = audio.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /audio/sound/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = audio.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /basics/debounce/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /basics/trigger/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /test68/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = test68.v fx68k.v fx68kAlu.v uaddrPla.v 2 | DEVICE = 85k 3 | 4 | include ulx3s.mk 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /riscv/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v attosoc.v picorv32.v simpleuart.v pll.v 2 | DEVICE = 85k 3 | 4 | include ../ulx3s.mk 5 | 6 | 7 | -------------------------------------------------------------------------------- /oled/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top_checkered.v oled_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /protocols/spidisplay/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /protocols/serialtx/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v uart_tx.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /video/color/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong/ball/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../pll.v ../spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong/game/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../pll.v ../spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong/move/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../pll.v ../spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong/wall/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../pll.v ../spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /protocols/echo/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v uart_tx.v uart_rx.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /video/checkers/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /video/tricolor/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /video/buffer/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v font_rom.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /video/text/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v font_rom.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /st7735/Makefile: -------------------------------------------------------------------------------- 1 | TOP ?= top_checkered.v 2 | VERILOG = ${TOP} oled_video.v 3 | DEVICE = 25k 4 | IDCODE = 0x21111043 5 | 6 | include ../ulx3s.mk 7 | 8 | 9 | -------------------------------------------------------------------------------- /st7789/Makefile: -------------------------------------------------------------------------------- 1 | TOP ?= top_checkered.v 2 | VERILOG = ${TOP} oled_video.v 3 | DEVICE = 25k 4 | IDCODE = 0x21111043 5 | 6 | include ../ulx3s.mk 7 | 8 | 9 | -------------------------------------------------------------------------------- /video/sprite/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v sprite_rom.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /cpu/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = grom_top.v grom_computer.v grom_cpu.v alu.v ram_memory.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /ps2/byte_to_hex.v: -------------------------------------------------------------------------------- 1 | module byte_to_hex ( 2 | input [3:0] b, 3 | output [7:0] h); 4 | 5 | assign h = (b < 10 ? "0" + b : "A" + (b-10)); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /ps2/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = ps2_test.v ps2.v debug.v uart_tx.v byte_to_hex.v 2 | IDCODE = 0x21111043 # 12f 3 | DEVICE = 25k 4 | 5 | include ../ulx3s.mk 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /ps2port/byte_to_hex.v: -------------------------------------------------------------------------------- 1 | module byte_to_hex ( 2 | input [3:0] b, 3 | output [7:0] h); 4 | 5 | assign h = (b < 10 ? "0" + b : "A" + (b-10)); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /video/terminal/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v pll.v spi_video.v font_rom.v uart_rx.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /hdmi/menu/software/delay.h: -------------------------------------------------------------------------------- 1 | #ifndef __TINYSOC_DELAY__ 2 | #define __TINYSOC_DELAY__ 3 | 4 | #include 5 | 6 | void delay(uint32_t millis); 7 | 8 | #endif 9 | -------------------------------------------------------------------------------- /ps2port/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = ps2_test.v ps2_port.v debug.v uart_tx.v byte_to_hex.v 2 | IDCODE = 0x21111043 # 12f 3 | DEVICE = 25k 4 | 5 | include ../ulx3s.mk 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /basics/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | output [7:0] led, 3 | output wifi_gpio0 4 | ); 5 | assign led = 8'b00000111; 6 | 7 | assign wifi_gpio0 = 1'b1; 8 | endmodule 9 | -------------------------------------------------------------------------------- /basics/led/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | output [7:0] led, 3 | output wifi_gpio0 4 | ); 5 | assign led = 8'b00000111; 6 | 7 | assign wifi_gpio0 = 1'b1; 8 | endmodule 9 | -------------------------------------------------------------------------------- /computer/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top_altair.v altair.v jmp_boot.v ram_memory.v rom_memory.v i8080.v mc6850.v simpleuart.v 2 | #DEVICE = 25k 3 | #IDCODE = 0x21111043 4 | 5 | include ../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /ledpanel/palette.raw: -------------------------------------------------------------------------------- 1 | edfdfb 2 | d0edee 3 | 79d5cd 4 | 02a59e 5 | 55b7b0 6 | 248b8f 7 | 12a5a1 8 | 0faba4 9 | 0b9d9a 10 | 029b98 11 | 299c9a 12 | 18b6aa 13 | 137e85 14 | 0d646c 15 | 0b8c89 16 | 02a09b 17 | -------------------------------------------------------------------------------- /sdram16/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = testram.v ecp5pll.sv sdram.v \ 2 | spi_display/lcd_video.v \ 3 | spi_display/hex_decoder_v.v 4 | 5 | DEVICE = 85k 6 | 7 | include ulx3s.mk 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /basics/button/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | output [7:0] led, 3 | input [6:0] btn, 4 | output wifi_gpio0 5 | ); 6 | assign led = { 1'b0, btn }; 7 | 8 | assign wifi_gpio0 = 1'b1; 9 | endmodule 10 | -------------------------------------------------------------------------------- /hdmi/color/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /hdmi/checkers/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /hdmi/tricolor/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong-hdmi/ball/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong-hdmi/game/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong-hdmi/move/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /pong-hdmi/wall/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /hdmi/text/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v font_rom.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /hdmi/buffer/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v font_rom.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /hdmi/sprite/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v sprite_rom.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /ps2send/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = uart_to_ps2.v ps2_send.v PushButton_Debouncer.v async_receiver.v BaudTickGen.v 2 | 3 | include ../ulx3s.mk 4 | 5 | tb: tb.v $(VERILOG) 6 | iverilog -o tb tb.v ps2_send.v 7 | 8 | sim: tb 9 | ./tb 10 | 11 | -------------------------------------------------------------------------------- /hdmi/terminal/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v font_rom.v uart_rx.v ../clk_25_250_125_25.v ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v 2 | DEVICE = 25k 3 | IDCODE = 0x21111043 4 | 5 | include ../../ulx3s.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /usbhost/UsbHidTest.v_toplevel_coreArea_usbHostHid_C_setup_rom.bin: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000101 3 | 00000001 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00001001 11 | 00000001 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | -------------------------------------------------------------------------------- /usbemard/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = ulx3s_usbhost_test.v usb_phy.v usb_rx_phy.v usb_tx_phy.v \ 2 | hex_decoder_v.v usbh_sie.v usbh_crc5.v usbh_crc16.v \ 3 | lcd_video.v usbh_host_hid.v clk_25_125_48_6_25.v 4 | IDCODE = 0x41113043 # 85 5 | DEVICE = 85k 6 | 7 | include ../ulx3s.mk 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /usbhost/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = ulx3s_usbhost_test.v usb_phy.v usb_rx_phy.v usb_tx_phy.v \ 2 | hex_decoder_v.v usbh_sie.v usbh_crc5.v usbh_crc16.v \ 3 | lcd_video.v usbh_host_hid.v clk_25_125_48_6_25.v 4 | IDCODE = 0x41113043 # 85 5 | DEVICE = 85k 6 | 7 | include ../ulx3s.mk 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /hdmi/buffer/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /hdmi/menu/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /hdmi/terminal/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /hdmi/text/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /video/buffer/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /video/text/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /hdmi/menu/Makefile: -------------------------------------------------------------------------------- 1 | VERILOG = top.v font_rom.v PushButton_Debouncer.v ../clk_25_250_125_25.v \ 2 | ../fake_differential.v ../hdmi_video.v ..//tmds_encoder.v ../vga2dvid.v ../vga_video.v \ 3 | attosoc.v picorv32.v simpleuart.v spi_master.v flash_write.v sdcard.v 4 | 5 | DEVICE = 85k 6 | 7 | include ../../ulx3s.mk 8 | 9 | 10 | -------------------------------------------------------------------------------- /video/terminal/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /basics/counter/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk_25mhz, 3 | output [7:0] led, 4 | output wifi_gpio0 5 | ); 6 | reg [31:0] cnt = 0; 7 | 8 | always @(posedge clk_25mhz) 9 | begin 10 | cnt <= cnt + 1; 11 | end 12 | 13 | assign led = cnt[31:24]; 14 | assign wifi_gpio0 = 1'b1; 15 | endmodule 16 | -------------------------------------------------------------------------------- /basics/trigger/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk_25mhz, 3 | output [7:0] led, 4 | input [6:0] btn, 5 | output wifi_gpio0 6 | ); 7 | reg [7:0] cnt = 0; 8 | 9 | always @(posedge btn[1]) 10 | begin 11 | cnt <= cnt + 1; 12 | end 13 | 14 | assign led = cnt; 15 | assign wifi_gpio0 = 1'b1; 16 | endmodule 17 | -------------------------------------------------------------------------------- /hdmi/color/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | output wifi_gpio0 6 | ); 7 | assign wifi_gpio0 = 1'b1; 8 | 9 | hdmi_video hdmi_video 10 | ( 11 | .clk_25mhz(clk_25mhz), 12 | .color(24'h000080), 13 | .gpdi_dp(gpdi_dp), 14 | .gpdi_dn(gpdi_dn) 15 | ); 16 | endmodule 17 | -------------------------------------------------------------------------------- /cpu/grom_top.v: -------------------------------------------------------------------------------- 1 | module grom_top( 2 | input clk_25mhz, 3 | output [7:0] led, 4 | input [6:0] btn, 5 | output wifi_gpio0 6 | ); 7 | 8 | wire [7:0] display_out; 9 | wire hlt; 10 | 11 | grom_computer computer(.clk(clk_25mhz),.reset(btn[1]),.hlt(hlt),.display_out(display_out)); 12 | 13 | assign led = display_out; 14 | assign wifi_gpio0 = 1'b1; 15 | endmodule 16 | -------------------------------------------------------------------------------- /protocols/serialtx/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk_25mhz, 3 | output ftdi_rxd, 4 | input [6:0] btn, 5 | output wifi_gpio0); 6 | 7 | uart_tx uart_transmit( 8 | .clk(clk_25mhz), 9 | .resetn(1'b1), 10 | .ser_tx(ftdi_rxd), 11 | .cfg_divider(25000000/115200), 12 | .data(8'd65), 13 | .data_we(btn[1]) 14 | ); 15 | 16 | assign wifi_gpio0 = 1'b1; 17 | 18 | endmodule -------------------------------------------------------------------------------- /riscv/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clk_25mhz, 3 | output [7:0] led, 4 | output ftdi_rxd, 5 | input ftdi_txd, 6 | output wifi_gpio0 7 | ); 8 | 9 | assign wifi_gpio0 = 1'b1; 10 | 11 | wire clk; 12 | pll pll( 13 | .clki(clk_25mhz), 14 | .clko(clk) 15 | ); 16 | attosoc soc( 17 | .clk(clk), 18 | .led(led), 19 | .uart_tx(ftdi_rxd), 20 | .uart_rx(ftdi_txd) 21 | ); 22 | endmodule 23 | -------------------------------------------------------------------------------- /riscv/blinky/Makefile: -------------------------------------------------------------------------------- 1 | all: firmware.hex 2 | 3 | clean: 4 | rm -f firmware.hex firmware.elf firmware.bin 5 | 6 | firmware.elf: sections.lds firmware.s 7 | riscv-none-embed-gcc -mabi=ilp32 -march=rv32i -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf firmware.s 8 | 9 | firmware.bin: firmware.elf 10 | riscv-none-embed-objcopy -O binary firmware.elf firmware.bin 11 | 12 | firmware.hex: firmware.bin 13 | python3 makehex.py $^ 8192 > $@ 14 | 15 | -------------------------------------------------------------------------------- /hdmi/checkers/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | output wifi_gpio0 6 | ); 7 | assign wifi_gpio0 = 1'b1; 8 | 9 | wire [23:0] color; 10 | wire [9:0] x; 11 | wire [9:0] y; 12 | 13 | assign color = x[4] ^ y[4] ? 24'hffffff : 24'h000000; 14 | 15 | hdmi_video hdmi_video 16 | ( 17 | .clk_25mhz(clk_25mhz), 18 | .x(x), 19 | .y(y), 20 | .color(color), 21 | .gpdi_dp(gpdi_dp), 22 | .gpdi_dn(gpdi_dn) 23 | ); 24 | endmodule 25 | -------------------------------------------------------------------------------- /cpu/grom_computer_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module grom_computer_tb(); 3 | reg clk = 0; 4 | reg reset; 5 | wire [7:0] display_out; 6 | wire hlt; 7 | 8 | grom_computer computer(.clk(clk),.reset(reset),.hlt(hlt),.display_out(display_out)); 9 | 10 | always 11 | #(5) clk <= !clk; 12 | 13 | initial 14 | begin 15 | $dumpfile("grom_computer_tb.vcd"); 16 | $dumpvars(0,grom_computer_tb); 17 | reset = 1; 18 | #20 19 | reset = 0; 20 | #900 21 | $finish; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /riscv/console/Makefile: -------------------------------------------------------------------------------- 1 | all: firmware.hex 2 | 3 | clean: 4 | rm -f firmware.hex firmware.elf firmware.bin 5 | 6 | firmware.elf: sections.lds start.s firmware.c 7 | riscv-none-embed-gcc -mabi=ilp32 -march=rv32i -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.s firmware.c 8 | 9 | firmware.bin: firmware.elf 10 | riscv-none-embed-objcopy -O binary firmware.elf firmware.bin 11 | 12 | firmware.hex: firmware.bin 13 | python3 makehex.py $^ 8192 > $@ 14 | 15 | -------------------------------------------------------------------------------- /hdmi/tricolor/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | output wifi_gpio0 6 | ); 7 | assign wifi_gpio0 = 1'b1; 8 | 9 | wire [23:0] color; 10 | wire [9:0] x; 11 | wire [9:0] y; 12 | 13 | assign color = (x<213) ? 24'hff0000 : (x<426) ? 24'hffffff : 24'h0000ff; 14 | 15 | hdmi_video hdmi_video 16 | ( 17 | .clk_25mhz(clk_25mhz), 18 | .x(x), 19 | .y(y), 20 | .color(color), 21 | .gpdi_dp(gpdi_dp), 22 | .gpdi_dn(gpdi_dn) 23 | ); 24 | endmodule 25 | -------------------------------------------------------------------------------- /st7789/st7789_init.mem: -------------------------------------------------------------------------------- 1 | // SWRESET, delay 150 2 | 01 3 | 80 4 | 96 5 | // SLPOUT, delay 10 6 | 11 7 | 80 8 | 0A 9 | // COLMOD, 16-bit color, delay 10 10 | 3A 11 | 81 12 | 55 13 | 0A 14 | // MADCTL 15 | 36 16 | 01 17 | 08 18 | // CASET 19 | 2A 20 | 04 21 | 00 22 | 00 23 | 00 24 | E0 25 | // RASET 26 | 2B 27 | 04 28 | 00 29 | 00 30 | 01 31 | 40 32 | // INVON, delay 10 33 | 21 34 | 80 35 | 0A 36 | // NORON, delay 10 37 | 13 38 | 80 39 | 0A 40 | // DISPON, delay 10 41 | 29 42 | 80 43 | 0A 44 | // RAMWR 2C 00 45 | 2C 46 | 00 47 | 48 | -------------------------------------------------------------------------------- /basics/sum/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | output [7:0] led, 3 | ); 4 | 5 | localparam N = 8; 6 | integer i; 7 | 8 | reg [7:0] arr [0:N-1]; 9 | reg [7:0] ps [0:N-1]; 10 | 11 | initial begin 12 | for(i = 0; i < N; i=i+1) 13 | arr[i] = i; 14 | end 15 | 16 | always @* begin 17 | ps[0] = arr[0]; 18 | 19 | for(i = 1; i < N; i=i+1) 20 | ps[i] = ps[i-1] + arr[i]; 21 | end 22 | 23 | assign led = ps[N-1]; 24 | 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /computer/rom_memory.v: -------------------------------------------------------------------------------- 1 | module rom_memory( 2 | input clk, 3 | input [ADDR_WIDTH-1:0] addr, 4 | input rd, 5 | output reg [7:0] data_out 6 | ); 7 | parameter FILENAME = ""; 8 | 9 | parameter integer ADDR_WIDTH = 8; 10 | 11 | reg [7:0] rom[0:(2 ** ADDR_WIDTH)-1] /* verilator public_flat */; 12 | 13 | initial 14 | begin 15 | if (FILENAME!="") 16 | $readmemh(FILENAME, rom); 17 | end 18 | 19 | always @(posedge clk) 20 | begin 21 | if (rd) 22 | data_out <= rom[addr]; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /computer/top_altair.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | input ftdi_txd, 5 | output ftdi_rxd, 6 | output [7:0] led, 7 | output wifi_gpio0 8 | ); 9 | 10 | reg [5:0] reset_cnt; 11 | wire resetn = &reset_cnt; 12 | 13 | always @(posedge clk_25mhz) begin 14 | reset_cnt <= reset_cnt + !resetn; 15 | end 16 | 17 | altair machine( 18 | .clk(clk_25mhz), 19 | .reset(~resetn), 20 | .rx(ftdi_txd), 21 | .tx(ftdi_rxd), 22 | .led(led) 23 | ); 24 | 25 | assign wifi_gpio0 = 1'b1; 26 | endmodule 27 | -------------------------------------------------------------------------------- /hdmi/menu/software/Makefile: -------------------------------------------------------------------------------- 1 | all: firmware.hex 2 | 3 | clean: 4 | rm -f firmware.hex firmware.elf firmware.bin 5 | 6 | firmware.elf: sections.lds start.s firmware.c sdcard.c flash.c 7 | /opt/riscv/bin/riscv64-unknown-elf-gcc -mabi=ilp32 -march=rv32i -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.s firmware.c sdcard.c flash.c 8 | 9 | firmware.bin: firmware.elf 10 | /opt/riscv/bin/riscv64-unknown-elf-objcopy -O binary firmware.elf firmware.bin 11 | 12 | firmware.hex: firmware.bin 13 | python3 makehex.py $^ 8192 > $@ 14 | 15 | -------------------------------------------------------------------------------- /hdmi/menu/software/sdcard.h: -------------------------------------------------------------------------------- 1 | #ifndef __TINYSOC_SDCARD__ 2 | #define __TINYSOC_SDCARD__ 3 | 4 | #include 5 | 6 | #define reg_sdcard_prescale (*(volatile uint32_t*)0x06000000) 7 | #define reg_sdcard_cs (*(volatile uint32_t*)0x06000004) 8 | #define reg_sdcard_xfer (*(volatile uint32_t*)0x06000008) 9 | #define reg_sdcard_mode (*(volatile uint32_t*)0x0600000c) 10 | 11 | void sdcard_read(uint8_t *data, uint32_t blockaddr); 12 | 13 | void sdcard_init(void); 14 | 15 | void sdcard_error(char *msg, uint32_t r); 16 | 17 | void sdcard_error2(char *msg, uint32_t r1, uint32_t r2); 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /basics/debounce/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk_25mhz, 3 | output [7:0] led, 4 | input [6:0] btn, 5 | output wifi_gpio0 6 | ); 7 | reg [7:0] cnt = 0; 8 | reg [23:0] clk_cnt = 0; 9 | reg prev_btn = 0; 10 | 11 | always @(posedge clk_25mhz) 12 | begin 13 | clk_cnt <= clk_cnt + 1; 14 | end 15 | 16 | always @(posedge clk_cnt[20]) 17 | begin 18 | prev_btn <= btn[1]; 19 | if (prev_btn== 1'b0 && btn[1]==1'b1) 20 | cnt <= cnt + 1; 21 | end 22 | 23 | assign led = cnt; 24 | assign wifi_gpio0 = 1'b1; 25 | endmodule 26 | -------------------------------------------------------------------------------- /computer/ram_memory.v: -------------------------------------------------------------------------------- 1 | module ram_memory( 2 | input clk, 3 | input [ADDR_WIDTH-1:0] addr, 4 | input [7:0] data_in, 5 | input rd, 6 | input we, 7 | output reg [7:0] data_out 8 | ); 9 | parameter integer ADDR_WIDTH = 8; 10 | 11 | reg [7:0] ram[0:(2 ** ADDR_WIDTH)-1] /* verilator public_flat */; 12 | 13 | parameter FILENAME = ""; 14 | 15 | initial 16 | begin 17 | if (FILENAME!="") 18 | $readmemh(FILENAME, ram); 19 | end 20 | 21 | always @(posedge clk) 22 | begin 23 | if (we) 24 | ram[addr] <= data_in; 25 | if (rd) 26 | data_out <= ram[addr]; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /hdmi/text/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | output wifi_gpio0 6 | ); 7 | assign wifi_gpio0 = 1'b1; 8 | 9 | wire [23:0] color; 10 | wire [9:0] x; 11 | wire [9:0] y; 12 | 13 | wire [7:0] data_out; 14 | 15 | font_rom vga_font( 16 | .clk(clk_25mhz), 17 | .addr({ 8'd77, y[3:0] }), 18 | .data_out(data_out) 19 | ); 20 | 21 | assign color = data_out[7-x[2:0]+1] ? 24'hffffff : 24'h000000; // +1 for sync 22 | 23 | hdmi_video hdmi_video 24 | ( 25 | .clk_25mhz(clk_25mhz), 26 | .x(x), 27 | .y(y), 28 | .color(color), 29 | .gpdi_dp(gpdi_dp), 30 | .gpdi_dn(gpdi_dn) 31 | ); 32 | endmodule 33 | -------------------------------------------------------------------------------- /protocols/echo/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk_25mhz, 3 | input ftdi_txd, 4 | output ftdi_rxd, 5 | output wifi_gpio0); 6 | 7 | wire rx_valid; 8 | wire [7:0] uart_out; 9 | 10 | uart_rx uart_receive( 11 | .clk(clk_25mhz), 12 | .resetn(1'b1), 13 | .ser_rx(ftdi_txd), 14 | .cfg_divider(25000000/115200), 15 | .data(uart_out), 16 | .valid(rx_valid) 17 | ); 18 | 19 | uart_tx uart_transmit( 20 | .clk(clk_25mhz), 21 | .resetn(1'b1), 22 | .ser_tx(ftdi_rxd), 23 | .cfg_divider(25000000/115200), 24 | .data(uart_out), 25 | .data_we(rx_valid) 26 | ); 27 | 28 | assign wifi_gpio0 = 1'b1; 29 | 30 | endmodule -------------------------------------------------------------------------------- /riscv/blinky/sections.lds: -------------------------------------------------------------------------------- 1 | /* 2 | This is free and unencumbered software released into the public domain. 3 | 4 | Anyone is free to copy, modify, publish, use, compile, sell, or 5 | distribute this software, either in source code form or as a compiled 6 | binary, for any purpose, commercial or non-commercial, and by any 7 | means. 8 | */ 9 | 10 | MEMORY { 11 | /* the memory in the testbench is 64k in size; 12 | * set LENGTH=48k and leave at least 16k for stack */ 13 | mem : ORIGIN = 0x00000000, LENGTH = 0x0000c000 14 | } 15 | 16 | SECTIONS { 17 | .memory : { 18 | . = 0x000000; 19 | start*(.text); 20 | *(.text); 21 | *(*); 22 | end = .; 23 | } > mem 24 | } 25 | -------------------------------------------------------------------------------- /riscv/console/sections.lds: -------------------------------------------------------------------------------- 1 | /* 2 | This is free and unencumbered software released into the public domain. 3 | 4 | Anyone is free to copy, modify, publish, use, compile, sell, or 5 | distribute this software, either in source code form or as a compiled 6 | binary, for any purpose, commercial or non-commercial, and by any 7 | means. 8 | */ 9 | 10 | MEMORY { 11 | /* the memory in the testbench is 64k in size; 12 | * set LENGTH=48k and leave at least 16k for stack */ 13 | mem : ORIGIN = 0x00000000, LENGTH = 0x0000c000 14 | } 15 | 16 | SECTIONS { 17 | .memory : { 18 | . = 0x000000; 19 | start*(.text); 20 | *(.text); 21 | *(*); 22 | end = .; 23 | } > mem 24 | } 25 | -------------------------------------------------------------------------------- /ulx3s.mk: -------------------------------------------------------------------------------- 1 | DEVICE ?= 85k 2 | PIN_DEF ?= ulx3s_v20.lpf 3 | 4 | BUILDDIR = bin 5 | 6 | compile: $(BUILDDIR)/toplevel.bit 7 | 8 | prog: $(BUILDDIR)/toplevel.bit 9 | ujprog $^ 10 | 11 | $(BUILDDIR)/toplevel.json: $(VERILOG) 12 | mkdir -p $(BUILDDIR) 13 | yosys -p "synth_ecp5 -abc9 -top top -json $@" $^ 14 | 15 | $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json 16 | nextpnr-ecp5 --${DEVICE} --package CABGA381 --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $< 17 | 18 | $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config 19 | ecppack --compress $^ $@ 20 | 21 | clean: 22 | rm -rf ${BUILDDIR} 23 | 24 | .SECONDARY: 25 | .PHONY: compile clean prog 26 | -------------------------------------------------------------------------------- /hdmi/menu/software/sections.lds: -------------------------------------------------------------------------------- 1 | /* 2 | This is free and unencumbered software released into the public domain. 3 | 4 | Anyone is free to copy, modify, publish, use, compile, sell, or 5 | distribute this software, either in source code form or as a compiled 6 | binary, for any purpose, commercial or non-commercial, and by any 7 | means. 8 | */ 9 | 10 | MEMORY { 11 | /* the memory in the testbench is 64k in size; 12 | * set LENGTH=48k and leave at least 16k for stack */ 13 | mem : ORIGIN = 0x00000000, LENGTH = 0x0000c000 14 | } 15 | 16 | SECTIONS { 17 | .memory : { 18 | . = 0x000000; 19 | start*(.text); 20 | *(.text); 21 | *(*); 22 | end = .; 23 | } > mem 24 | } 25 | -------------------------------------------------------------------------------- /riscv/blinky/firmware.s: -------------------------------------------------------------------------------- 1 | start: 2 | li s0, 2 3 | li s1, 0x02000000 4 | li s3, 256 5 | outerloop: 6 | addi s0, s0, 1 7 | blt s0, s3, inrange 8 | li s0, 2 9 | inrange: 10 | li s2, 2 11 | innerloop: 12 | bge s2, s0, prime 13 | add a0, s0, 0 14 | add a1, s2, 0 15 | jal ra, divtest 16 | beq a0, x0, notprime 17 | addi s2, s2, 1 18 | j innerloop 19 | prime: 20 | sw s0, 0(s1) 21 | jal ra, delay 22 | notprime: 23 | j outerloop 24 | 25 | divtest: 26 | li t0, 1 27 | divloop: 28 | sub a0, a0, a1 29 | bge a0, t0, divloop 30 | jr ra 31 | 32 | delay: 33 | li t0, 360000 34 | delayloop: 35 | addi t0, t0, -1 36 | bnez t0, delayloop 37 | jr ra 38 | -------------------------------------------------------------------------------- /riscv/console/firmware.s: -------------------------------------------------------------------------------- 1 | start: 2 | li s0, 2 3 | li s1, 0x02000000 4 | li s3, 256 5 | outerloop: 6 | addi s0, s0, 1 7 | blt s0, s3, inrange 8 | li s0, 2 9 | inrange: 10 | li s2, 2 11 | innerloop: 12 | bge s2, s0, prime 13 | add a0, s0, 0 14 | add a1, s2, 0 15 | jal ra, divtest 16 | beq a0, x0, notprime 17 | addi s2, s2, 1 18 | j innerloop 19 | prime: 20 | sw s0, 0(s1) 21 | jal ra, delay 22 | notprime: 23 | j outerloop 24 | 25 | divtest: 26 | li t0, 1 27 | divloop: 28 | sub a0, a0, a1 29 | bge a0, t0, divloop 30 | jr ra 31 | 32 | delay: 33 | li t0, 360000 34 | delayloop: 35 | addi t0, t0, -1 36 | bnez t0, delayloop 37 | jr ra 38 | -------------------------------------------------------------------------------- /hdmi/menu/software/firmware.s: -------------------------------------------------------------------------------- 1 | start: 2 | li s0, 2 3 | li s1, 0x02000000 4 | li s3, 256 5 | outerloop: 6 | addi s0, s0, 1 7 | blt s0, s3, inrange 8 | li s0, 2 9 | inrange: 10 | li s2, 2 11 | innerloop: 12 | bge s2, s0, prime 13 | add a0, s0, 0 14 | add a1, s2, 0 15 | jal ra, divtest 16 | beq a0, x0, notprime 17 | addi s2, s2, 1 18 | j innerloop 19 | prime: 20 | sw s0, 0(s1) 21 | jal ra, delay 22 | notprime: 23 | j outerloop 24 | 25 | divtest: 26 | li t0, 1 27 | divloop: 28 | sub a0, a0, a1 29 | bge a0, t0, divloop 30 | jr ra 31 | 32 | delay: 33 | li t0, 360000 34 | delayloop: 35 | addi t0, t0, -1 36 | bnez t0, delayloop 37 | jr ra 38 | -------------------------------------------------------------------------------- /basics/sum_vhdl/ulx3s.mk: -------------------------------------------------------------------------------- 1 | DEVICE ?= 85k 2 | PIN_DEF ?= ulx3s_v20.lpf 3 | 4 | BUILDDIR = bin 5 | 6 | compile: $(BUILDDIR)/toplevel.bit 7 | 8 | prog: $(BUILDDIR)/toplevel.bit 9 | ujprog $^ 10 | 11 | $(BUILDDIR)/toplevel.json: ${VHDL} 12 | mkdir -p $(BUILDDIR) 13 | yosys -m ghdl \ 14 | -p "ghdl --std=08 --ieee=synopsys ${VHDL} -e top" \ 15 | -p "hierarchy -top top" \ 16 | -p "synth_ecp5 -json $@" 17 | 18 | $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json 19 | nextpnr-ecp5 --${DEVICE} --package CABGA381 --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $< 20 | 21 | $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config 22 | ecppack --compress $^ $@ 23 | 24 | clean: 25 | rm -rf ${BUILDDIR} 26 | 27 | .SECONDARY: 28 | .PHONY: compile clean prog 29 | -------------------------------------------------------------------------------- /hdmi/menu/makehex.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # This is free and unencumbered software released into the public domain. 4 | # 5 | # Anyone is free to copy, modify, publish, use, compile, sell, or 6 | # distribute this software, either in source code form or as a compiled 7 | # binary, for any purpose, commercial or non-commercial, and by any 8 | # means. 9 | 10 | from sys import argv 11 | 12 | binfile = argv[1] 13 | nwords = int(argv[2]) 14 | 15 | with open(binfile, "rb") as f: 16 | bindata = f.read() 17 | 18 | assert len(bindata) < 4*nwords 19 | #assert len(bindata) % 4 == 0 20 | 21 | for i in range(nwords): 22 | if i < len(bindata) // 4: 23 | w = bindata[4*i : 4*i+4] 24 | print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0])) 25 | else: 26 | print("0") 27 | 28 | -------------------------------------------------------------------------------- /basics/sum_vhdl/top.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | library std; 3 | 4 | use IEEE.std_logic_1164.all; 5 | use IEEE.std_logic_arith.all; 6 | 7 | entity top is 8 | port( 9 | led : out std_logic_vector(7 downto 0); 10 | btn : in std_logic_vector(6 downto 0) 11 | ); 12 | end top; 13 | 14 | architecture rtl of top is 15 | type byte_array is array (0 to 7) of std_logic_vector(7 downto 0); 16 | signal arr : byte_array := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07"); 17 | begin 18 | main: process(btn) 19 | variable sum : std_logic_vector(7 downto 0); 20 | begin 21 | sum := (others => '0'); 22 | 23 | for n in arr'range loop 24 | sum := unsigned(sum) + unsigned(arr(n)); 25 | end loop; 26 | 27 | led <= sum; 28 | end process; 29 | end; 30 | 31 | -------------------------------------------------------------------------------- /riscv/blinky/makehex.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # This is free and unencumbered software released into the public domain. 4 | # 5 | # Anyone is free to copy, modify, publish, use, compile, sell, or 6 | # distribute this software, either in source code form or as a compiled 7 | # binary, for any purpose, commercial or non-commercial, and by any 8 | # means. 9 | 10 | from sys import argv 11 | 12 | binfile = argv[1] 13 | nwords = int(argv[2]) 14 | 15 | with open(binfile, "rb") as f: 16 | bindata = f.read() 17 | 18 | assert len(bindata) < 4*nwords 19 | #assert len(bindata) % 4 == 0 20 | 21 | for i in range(nwords): 22 | if i < len(bindata) // 4: 23 | w = bindata[4*i : 4*i+4] 24 | print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0])) 25 | else: 26 | print("0") 27 | 28 | -------------------------------------------------------------------------------- /riscv/console/makehex.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # This is free and unencumbered software released into the public domain. 4 | # 5 | # Anyone is free to copy, modify, publish, use, compile, sell, or 6 | # distribute this software, either in source code form or as a compiled 7 | # binary, for any purpose, commercial or non-commercial, and by any 8 | # means. 9 | 10 | from sys import argv 11 | 12 | binfile = argv[1] 13 | nwords = int(argv[2]) 14 | 15 | with open(binfile, "rb") as f: 16 | bindata = f.read() 17 | 18 | assert len(bindata) < 4*nwords 19 | #assert len(bindata) % 4 == 0 20 | 21 | for i in range(nwords): 22 | if i < len(bindata) // 4: 23 | w = bindata[4*i : 4*i+4] 24 | print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0])) 25 | else: 26 | print("0") 27 | 28 | -------------------------------------------------------------------------------- /hdmi/menu/software/makehex.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # This is free and unencumbered software released into the public domain. 4 | # 5 | # Anyone is free to copy, modify, publish, use, compile, sell, or 6 | # distribute this software, either in source code form or as a compiled 7 | # binary, for any purpose, commercial or non-commercial, and by any 8 | # means. 9 | 10 | from sys import argv 11 | 12 | binfile = argv[1] 13 | nwords = int(argv[2]) 14 | 15 | with open(binfile, "rb") as f: 16 | bindata = f.read() 17 | 18 | assert len(bindata) < 4*nwords 19 | #assert len(bindata) % 4 == 0 20 | 21 | for i in range(nwords): 22 | if i < len(bindata) // 4: 23 | w = bindata[4*i : 4*i+4] 24 | print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0])) 25 | else: 26 | print("0") 27 | 28 | -------------------------------------------------------------------------------- /sdram8/ulx3s.mk: -------------------------------------------------------------------------------- 1 | DEVICE ?= 85k 2 | PIN_DEF ?= ulx3s_v20.lpf 3 | #IDCODE ?= 0x41113043 # 85f 4 | 5 | BUILDDIR = bin 6 | 7 | compile: $(BUILDDIR)/toplevel.bit 8 | 9 | prog: $(BUILDDIR)/toplevel.bit 10 | ujprog $^ 11 | 12 | $(BUILDDIR)/toplevel.json: $(VERILOG) 13 | mkdir -p $(BUILDDIR) 14 | yosys -p "synth_ecp5 -abc9 -top testram -json $@" $^ 15 | 16 | $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json 17 | nextpnr-ecp5 --${DEVICE} --package CABGA381 --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $< 18 | 19 | $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config 20 | ecppack --compress $^ $@ 21 | 22 | tb: test68.v $(VERILOG) 23 | iverilog -o tb tb.v $(VERILOG) 24 | 25 | sim: tb 26 | ./tb 27 | 28 | clean: 29 | rm -rf ${BUILDDIR} 30 | 31 | .SECONDARY: 32 | .PHONY: compile clean prog 33 | -------------------------------------------------------------------------------- /ledpanel/sprite_rom.v: -------------------------------------------------------------------------------- 1 | module sprite_rom( 2 | input clk, 3 | input [6:0] addrx, 4 | input [4:0] addry, 5 | output [23:0] data0, 6 | output [23:0] data1 7 | ); 8 | 9 | // reg [4:0] store[0:4095]; 10 | reg [4:0] store[0:8191]; 11 | reg [23:0] palette[0:15]; 12 | 13 | initial 14 | begin 15 | $readmemh("sprite.mem", store); 16 | $readmemh("palette.raw",palette); 17 | end 18 | 19 | wire [23:0] data0, data1; 20 | 21 | wire [6:0] ax; 22 | wire [4:0] ay; 23 | 24 | assign ax = addrx; 25 | assign ay = addry + 1; 26 | 27 | reg [3:0] pixel0, pixel1; 28 | 29 | always @(posedge clk) pixel0 <= store[ {1'b0, ay, ax } ]; 30 | always @(posedge clk) pixel1 <= store[ {1'b1, ay, ax } ]; 31 | 32 | assign data0 = palette[pixel0]; 33 | assign data1 = palette[pixel1]; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /audio/sound/audio.v: -------------------------------------------------------------------------------- 1 | module audio( 2 | input clk_25mhz, 3 | output wifi_gpio0, 4 | input [6:0] btn, 5 | output reg [3:0] audio_l, 6 | output reg [3:0] audio_r); 7 | 8 | parameter TONE_A4 = 25000000/440/2; 9 | parameter TONE_A5 = 25000000/880/2; 10 | 11 | reg [25:0] counter; 12 | initial 13 | begin 14 | audio_l = 0; 15 | audio_r = 0; 16 | counter = 0; 17 | end 18 | 19 | reg [23:0] tone; 20 | always @(posedge clk_25mhz) 21 | tone <= tone+1; 22 | 23 | always @(posedge clk_25mhz) 24 | if(counter==26'b0) 25 | begin 26 | counter <= (tone[23] ? TONE_A4-1 : TONE_A5-1 ); 27 | audio_l <= ~audio_l; 28 | audio_r <= ~audio_r; 29 | end 30 | else 31 | counter <= counter-1; 32 | 33 | assign wifi_gpio0 = 1'b1; 34 | endmodule 35 | -------------------------------------------------------------------------------- /hdmi/menu/software/flash.h: -------------------------------------------------------------------------------- 1 | #ifndef __TINYSOC_FLASH 2 | #define __TINYSOC_FLASH 3 | 4 | #include 5 | 6 | #define reg_flash_prescale (*(volatile uint32_t*)0x08000000) 7 | #define reg_flash_cs (*(volatile uint32_t*)0x08000004) 8 | #define reg_flash_xfer (*(volatile uint32_t*)0x08000008) 9 | #define reg_flash_mode (*(volatile uint32_t*)0x0800000C) 10 | 11 | void flash_begin(void); 12 | 13 | void flash_end(void); 14 | 15 | uint8_t flash_xfer(uint8_t d); 16 | 17 | void flash_write_enable(void); 18 | 19 | void flash_bulk_erase(void); 20 | 21 | void flash_erase_64kB(uint32_t addr); 22 | 23 | void flash_erase_32kB(uint32_t addr); 24 | 25 | void flash_write(uint32_t addr, uint8_t *data, int n); 26 | 27 | void flash_read(uint32_t addr, uint8_t *data, int n); 28 | 29 | void flash_wait(); 30 | 31 | #endif 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /sdram16/ulx3s.mk: -------------------------------------------------------------------------------- 1 | DEVICE ?= 85k 2 | PIN_DEF ?= ulx3s_v20.lpf 3 | #IDCODE ?= 0x41113043 # 85f 4 | 5 | BUILDDIR = bin 6 | 7 | compile: $(BUILDDIR)/toplevel.bit 8 | 9 | prog: $(BUILDDIR)/toplevel.bit 10 | ujprog $^ 11 | 12 | $(BUILDDIR)/toplevel.json: $(VERILOG) 13 | mkdir -p $(BUILDDIR) 14 | yosys -p "synth_ecp5 -abc9 -top testram -json $@" $^ 15 | 16 | $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json 17 | nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $< 18 | 19 | $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config 20 | ecppack --compress $^ $@ 21 | 22 | tb: test68.v $(VERILOG) 23 | iverilog -o tb tb.v $(VERILOG) 24 | 25 | sim: tb 26 | ./tb 27 | 28 | clean: 29 | rm -rf ${BUILDDIR} 30 | 31 | .SECONDARY: 32 | .PHONY: compile clean prog 33 | -------------------------------------------------------------------------------- /test68/ulx3s.mk: -------------------------------------------------------------------------------- 1 | DEVICE ?= 85k 2 | PIN_DEF ?= ulx3s_v20.lpf 3 | #IDCODE ?= 0x41113043 # 85f 4 | 5 | BUILDDIR = bin 6 | 7 | compile: $(BUILDDIR)/toplevel.bit 8 | 9 | prog: $(BUILDDIR)/toplevel.bit 10 | ujprog $^ 11 | 12 | $(BUILDDIR)/toplevel.json: $(VERILOG) 13 | mkdir -p $(BUILDDIR) 14 | yosys -p "synth_ecp5 -abc9 -top test68 -json $@" $^ 15 | 16 | $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json 17 | nextpnr-ecp5 --${DEVICE} --debug --log nextpnr.log --package CABGA381 --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $< 18 | 19 | $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config 20 | ecppack --compress $^ $@ 21 | 22 | tb: test68.v $(VERILOG) 23 | iverilog -o tb tb.v $(VERILOG) 24 | 25 | sim: tb 26 | ./tb 27 | 28 | clean: 29 | rm -rf ${BUILDDIR} 30 | 31 | .SECONDARY: 32 | .PHONY: compile clean prog 33 | -------------------------------------------------------------------------------- /cpu/grom_computer.v: -------------------------------------------------------------------------------- 1 | module grom_computer 2 | (input clk, // Main Clock 3 | input reset, // reset 4 | output hlt, 5 | output reg[7:0] display_out 6 | ); 7 | 8 | wire [11:0] addr; 9 | wire [7:0] memory_out; 10 | wire [7:0] memory_in; 11 | wire mem_enable; 12 | wire we; 13 | wire ioreq; 14 | 15 | grom_cpu cpu(.clk(clk),.reset(reset),.addr(addr),.data_in(memory_out),.data_out(memory_in),.we(we),.ioreq(ioreq),.hlt(hlt)); 16 | 17 | assign mem_enable = we & ~ioreq; 18 | 19 | ram_memory memory(.clk(clk),.addr(addr),.data_in(memory_in),.we(mem_enable),.data_out(memory_out)); 20 | 21 | always @(posedge clk) 22 | begin 23 | if(ioreq==1 && we==1) 24 | begin 25 | display_out <= memory_in; 26 | `ifdef DISASSEMBLY 27 | $display("Display output : %h", memory_in); 28 | `endif 29 | end 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /oled/top_checkered.v: -------------------------------------------------------------------------------- 1 | module top_checkered ( 2 | input wire clk_25mhz, 3 | output wire oled_csn, 4 | output wire oled_clk, 5 | output wire oled_mosi, 6 | output wire oled_dc, 7 | output wire oled_resn 8 | ); 9 | // checkered red green blue red green blue 10 | wire [15:0] color = x[3] ^ y[3] ? {5'd0, x[6:1], 5'd0} : {y[5:1], 6'd0, 5'd0}; 11 | wire [6:0] x, y; 12 | 13 | oled_video #( 14 | .C_init_file("oled_init_16bit.mem"), 15 | .C_init_size(44) 16 | ) oled_video_inst ( 17 | .clk(clk_25mhz), 18 | .x(x), 19 | .y(y), 20 | .color(color), 21 | .oled_csn(oled_csn), 22 | .oled_clk(oled_clk), 23 | .oled_mosi(oled_mosi), 24 | .oled_dc(oled_dc), 25 | .oled_resn(oled_resn) 26 | ); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /usbemard/st7789_init.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image X-flip 3 | // 38 bytes 4 | // after reset, delay 2^13 us = 8ms before sending commands 5 | 80 6 | 0D 7 | // SWRESET, delay 2^17 us = 131us 8 | 01 9 | 80 10 | 11 11 | // SLPOUT, delay 2^14 us = 16ms 12 | 11 13 | 80 14 | 0E 15 | // COLMOD, 16-bit color, delay 2^14 us = 16ms 16 | 3A 17 | 81 18 | 55 19 | 0E 20 | // MADCTL 21 | 36 22 | 01 23 | 80 24 | // CASET X 25 | 2A 26 | 04 27 | // X start MSB,LSB 28 | 00 29 | 00 30 | // X end MSB,LSB 31 | 00 32 | EF 33 | // RASET Y 34 | 2B 35 | 04 36 | // Y start MSB,LSB 37 | 00 38 | 50 39 | // Y end MSB,LSB 40 | 01 41 | 3F 42 | // INVON, delay 2^14 us = 16ms 43 | 21 44 | 80 45 | 0E 46 | // NORON, delay 2^14 us = 16ms 47 | 13 48 | 80 49 | 0E 50 | // DISPON, delay 2^14 us = 16ms 51 | 29 52 | 80 53 | 0E 54 | // RAMWR 2C 00 55 | 2C 56 | 00 57 | -------------------------------------------------------------------------------- /usbhost/st7789_init.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image X-flip 3 | // 38 bytes 4 | // after reset, delay 2^13 us = 8ms before sending commands 5 | 80 6 | 0D 7 | // SWRESET, delay 2^17 us = 131us 8 | 01 9 | 80 10 | 11 11 | // SLPOUT, delay 2^14 us = 16ms 12 | 11 13 | 80 14 | 0E 15 | // COLMOD, 16-bit color, delay 2^14 us = 16ms 16 | 3A 17 | 81 18 | 55 19 | 0E 20 | // MADCTL 21 | 36 22 | 01 23 | 80 24 | // CASET X 25 | 2A 26 | 04 27 | // X start MSB,LSB 28 | 00 29 | 00 30 | // X end MSB,LSB 31 | 00 32 | EF 33 | // RASET Y 34 | 2B 35 | 04 36 | // Y start MSB,LSB 37 | 00 38 | 50 39 | // Y end MSB,LSB 40 | 01 41 | 3F 42 | // INVON, delay 2^14 us = 16ms 43 | 21 44 | 80 45 | 0E 46 | // NORON, delay 2^14 us = 16ms 47 | 13 48 | 80 49 | 0E 50 | // DISPON, delay 2^14 us = 16ms 51 | 29 52 | 80 53 | 0E 54 | // RAMWR 2C 00 55 | 2C 56 | 00 57 | -------------------------------------------------------------------------------- /sdram16/spi_display/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image X-flip 3 | // 38 bytes 4 | // after reset, delay 2^13 us = 8ms before sending commands 5 | 80 6 | 0D 7 | // SWRESET, delay 2^17 us = 131us 8 | 01 9 | 80 10 | 11 11 | // SLPOUT, delay 2^14 us = 16ms 12 | 11 13 | 80 14 | 0E 15 | // COLMOD, 16-bit color, delay 2^14 us = 16ms 16 | 3A 17 | 81 18 | 55 19 | 0E 20 | // MADCTL 21 | 36 22 | 01 23 | 80 24 | // CASET X 25 | 2A 26 | 04 27 | // X start MSB,LSB 28 | 00 29 | 00 30 | // X end MSB,LSB 31 | 00 32 | EF 33 | // RASET Y 34 | 2B 35 | 04 36 | // Y start MSB,LSB 37 | 00 38 | 50 39 | // Y end MSB,LSB 40 | 01 41 | 3F 42 | // INVON, delay 2^14 us = 16ms 43 | 21 44 | 80 45 | 0E 46 | // NORON, delay 2^14 us = 16ms 47 | 13 48 | 80 49 | 0E 50 | // DISPON, delay 2^14 us = 16ms 51 | 29 52 | 80 53 | 0E 54 | // RAMWR 2C 00 55 | 2C 56 | 00 57 | -------------------------------------------------------------------------------- /ps2send/BaudTickGen.v: -------------------------------------------------------------------------------- 1 | module BaudTickGen( 2 | input clk, enable, 3 | output tick // generate a tick at the specified baud rate * oversampling 4 | ); 5 | parameter ClkFrequency = 25000000; 6 | parameter Baud = 115200; 7 | parameter Oversampling = 1; 8 | 9 | function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction 10 | localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte 11 | reg [AccWidth:0] Acc = 0; 12 | localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow 13 | localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter); 14 | always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0]; 15 | assign tick = Acc[AccWidth]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /st7735/top_checkered.v: -------------------------------------------------------------------------------- 1 | module top_checkered ( 2 | input wire clk_25mhz, 3 | output wire oled_csn, 4 | output wire oled_clk, 5 | output wire oled_mosi, 6 | output wire oled_dc, 7 | output wire oled_resn 8 | ); 9 | // checkered red green blue red green blue 10 | wire [15:0] color = x[3] ^ y[3] ? {5'd0, 6'b111111, 5'd0} : {5'b11111, 6'd0, 5'd0}; 11 | wire [6:0] x; 12 | wire [7:0] y; 13 | 14 | oled_video #( 15 | .C_init_file("st7735_init.mem"), 16 | .C_init_size(110) 17 | ) oled_video_inst ( 18 | .clk(clk_25mhz), 19 | .x(x), 20 | .y(y), 21 | .color(color), 22 | .oled_csn(oled_csn), 23 | .oled_clk(oled_clk), 24 | .oled_mosi(oled_mosi), 25 | .oled_dc(oled_dc), 26 | .oled_resn(oled_resn) 27 | ); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /st7789/top_checkered.v: -------------------------------------------------------------------------------- 1 | module top_checkered ( 2 | input wire clk_25mhz, 3 | output wire oled_csn, 4 | output wire oled_clk, 5 | output wire oled_mosi, 6 | output wire oled_dc, 7 | output wire oled_resn 8 | ); 9 | // checkered red green blue red green blue 10 | wire [15:0] color = x[3] ^ y[3] ? {5'd0, 6'b111111, 5'd0} : {5'b11111, 6'd0, 5'd0}; 11 | wire [6:0] x; 12 | wire [7:0] y; 13 | 14 | oled_video #( 15 | .C_init_file("st7789_init.mem"), 16 | .C_init_size(36) 17 | ) oled_video_inst ( 18 | .clk(clk_25mhz), 19 | .x(x), 20 | .y(y), 21 | .color(color), 22 | .oled_csn(oled_csn), 23 | .oled_clk(oled_clk), 24 | .oled_mosi(oled_mosi), 25 | .oled_dc(oled_dc), 26 | .oled_resn(oled_resn) 27 | ); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /ps2send/tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/100ps 2 | 3 | module tb(); 4 | 5 | initial begin 6 | $dumpfile("waves.vcd"); 7 | $dumpvars(0, u_ps2); 8 | end 9 | 10 | reg clk; 11 | wire ps2_clk, ps2_data; 12 | wire busy; 13 | reg req; 14 | wire [7:0] data = 8'h21; 15 | wire extended = 0; 16 | wire shift = 0; 17 | wire [7:0] led; 18 | 19 | initial begin 20 | clk = 1'b0; 21 | end 22 | 23 | initial begin 24 | repeat(5) @(posedge clk); 25 | req <= 1; 26 | repeat(1) @(posedge clk); 27 | req <= 0; 28 | 29 | repeat(100000) @(posedge clk); 30 | 31 | $finish; 32 | end 33 | 34 | always begin 35 | #5 clk = !clk; 36 | end 37 | 38 | 39 | ps2_send u_ps2 ( 40 | .clk_25mhz(clk), 41 | .ps2_data(ps2_data), 42 | .ps2_clk(ps2_clk), 43 | .req(req), 44 | .busy(busy), 45 | .data(data), 46 | .extended(extended), 47 | .shift(shift), 48 | .led(led) 49 | ); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /video/sprite/sprite_rom.v: -------------------------------------------------------------------------------- 1 | module sprite_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [3:0] store[0:4095]; 8 | wire [7:0] palette[0:15]; 9 | 10 | assign palette[0] = 8'h00; 11 | assign palette[1] = 8'h20; 12 | assign palette[2] = 8'h20; 13 | assign palette[3] = 8'h20; 14 | assign palette[4] = 8'h40; 15 | assign palette[5] = 8'h40; 16 | assign palette[6] = 8'h40; 17 | assign palette[7] = 8'h80; 18 | assign palette[8] = 8'h80; 19 | assign palette[9] = 8'h80; 20 | assign palette[10] = 8'h80; 21 | assign palette[11] = 8'h80; 22 | assign palette[12] = 8'h80; 23 | assign palette[13] = 8'hff; 24 | assign palette[14] = 8'hff; 25 | assign palette[15] = 8'hff; 26 | 27 | initial 28 | begin 29 | $readmemh("sprite.mem", store); 30 | end 31 | 32 | always @(posedge clk) 33 | data_out <= palette[store[addr]]; 34 | endmodule 35 | -------------------------------------------------------------------------------- /video/color/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | output wifi_gpio0 12 | ); 13 | assign wifi_gpio0 = 1'b1; 14 | 15 | wire clk; 16 | pll pll( 17 | .clki(clk_25mhz), 18 | .clko(clk), 19 | .locked() 20 | ); 21 | 22 | wire [7:0] x; 23 | wire [5:0] y; 24 | wire [7:0] color; 25 | 26 | spi_video video( 27 | .clk(clk), 28 | .oled_csn(oled_csn), 29 | .oled_clk(oled_clk), 30 | .oled_mosi(oled_mosi), 31 | .oled_dc(oled_dc), 32 | .oled_resn(oled_resn), 33 | .x(x), 34 | .y(y), 35 | .color(color) 36 | ); 37 | // Color encoding 38 | // RRR GGG BB 39 | assign color = 8'h02; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /computer/jmp_boot.v: -------------------------------------------------------------------------------- 1 | module jmp_boot( 2 | input clk, 3 | input reset, 4 | input rd, 5 | output reg [7:0] data_out, 6 | output reg valid 7 | ); 8 | reg [1:0] state = 0; 9 | reg prev_rd = 0; 10 | always @(posedge clk) 11 | begin 12 | if (reset) 13 | begin 14 | state <= 0; 15 | valid <= 1; 16 | prev_rd <= 0; 17 | end 18 | else 19 | begin 20 | if (rd && prev_rd==0) 21 | begin 22 | case (state) 23 | 2'b00 : begin 24 | data_out <= 8'b11000011; // JMP 0xfd00 25 | state <= 2'b01; 26 | end 27 | 2'b01 : begin 28 | data_out <= 8'h00; 29 | state <= 2'b10; 30 | end 31 | 2'b10 : begin 32 | data_out <= 8'hFD; 33 | state <= 2'b11; 34 | end 35 | 2'b11 : begin 36 | state <= 2'b11; 37 | valid <= 0; 38 | end 39 | endcase 40 | end 41 | prev_rd = rd; 42 | end 43 | end 44 | endmodule -------------------------------------------------------------------------------- /riscv/console/start.s: -------------------------------------------------------------------------------- 1 | .section .text 2 | 3 | start: 4 | 5 | # zero-initialize register file 6 | addi x1, zero, 0 7 | # x2 (sp) is initialized by reset 8 | addi x3, zero, 0 9 | addi x4, zero, 0 10 | addi x5, zero, 0 11 | addi x6, zero, 0 12 | addi x7, zero, 0 13 | addi x8, zero, 0 14 | addi x9, zero, 0 15 | addi x10, zero, 0 16 | addi x11, zero, 0 17 | addi x12, zero, 0 18 | addi x13, zero, 0 19 | addi x14, zero, 0 20 | addi x15, zero, 0 21 | addi x16, zero, 0 22 | addi x17, zero, 0 23 | addi x18, zero, 0 24 | addi x19, zero, 0 25 | addi x20, zero, 0 26 | addi x21, zero, 0 27 | addi x22, zero, 0 28 | addi x23, zero, 0 29 | addi x24, zero, 0 30 | addi x25, zero, 0 31 | addi x26, zero, 0 32 | addi x27, zero, 0 33 | addi x28, zero, 0 34 | addi x29, zero, 0 35 | addi x30, zero, 0 36 | addi x31, zero, 0 37 | 38 | # Update LEDs 39 | li a0, 0x02000000 40 | li a1, 0xAA 41 | sw a1, 0(a0) 42 | 43 | call main 44 | 45 | loop: 46 | j loop 47 | 48 | -------------------------------------------------------------------------------- /hdmi/menu/software/start.s: -------------------------------------------------------------------------------- 1 | .section .text 2 | 3 | start: 4 | 5 | # zero-initialize register file 6 | addi x1, zero, 0 7 | # x2 (sp) is initialized by reset 8 | addi x3, zero, 0 9 | addi x4, zero, 0 10 | addi x5, zero, 0 11 | addi x6, zero, 0 12 | addi x7, zero, 0 13 | addi x8, zero, 0 14 | addi x9, zero, 0 15 | addi x10, zero, 0 16 | addi x11, zero, 0 17 | addi x12, zero, 0 18 | addi x13, zero, 0 19 | addi x14, zero, 0 20 | addi x15, zero, 0 21 | addi x16, zero, 0 22 | addi x17, zero, 0 23 | addi x18, zero, 0 24 | addi x19, zero, 0 25 | addi x20, zero, 0 26 | addi x21, zero, 0 27 | addi x22, zero, 0 28 | addi x23, zero, 0 29 | addi x24, zero, 0 30 | addi x25, zero, 0 31 | addi x26, zero, 0 32 | addi x27, zero, 0 33 | addi x28, zero, 0 34 | addi x29, zero, 0 35 | addi x30, zero, 0 36 | addi x31, zero, 0 37 | 38 | # Update LEDs 39 | li a0, 0x02000000 40 | li a1, 0xAA 41 | sw a1, 0(a0) 42 | 43 | call main 44 | 45 | loop: 46 | j loop 47 | 48 | -------------------------------------------------------------------------------- /video/checkers/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | output wifi_gpio0 12 | ); 13 | assign wifi_gpio0 = 1'b1; 14 | 15 | wire clk; 16 | pll pll( 17 | .clki(clk_25mhz), 18 | .clko(clk), 19 | .locked() 20 | ); 21 | 22 | wire [7:0] x; 23 | wire [5:0] y; 24 | wire [7:0] color; 25 | 26 | spi_video video( 27 | .clk(clk), 28 | .oled_csn(oled_csn), 29 | .oled_clk(oled_clk), 30 | .oled_mosi(oled_mosi), 31 | .oled_dc(oled_dc), 32 | .oled_resn(oled_resn), 33 | .x(x), 34 | .y(y), 35 | .color(color) 36 | ); 37 | // Color encoding 38 | // RRR GGG BB 39 | assign color = x[3] ^ y[3] ? 8'hff : 8'h00; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /video/tricolor/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | output wifi_gpio0 12 | ); 13 | assign wifi_gpio0 = 1'b1; 14 | 15 | wire clk; 16 | pll pll( 17 | .clki(clk_25mhz), 18 | .clko(clk), 19 | .locked() 20 | ); 21 | 22 | wire [7:0] x; 23 | wire [5:0] y; 24 | wire [7:0] color; 25 | 26 | spi_video video( 27 | .clk(clk), 28 | .oled_csn(oled_csn), 29 | .oled_clk(oled_clk), 30 | .oled_mosi(oled_mosi), 31 | .oled_dc(oled_dc), 32 | .oled_resn(oled_resn), 33 | .x(x), 34 | .y(y), 35 | .color(color) 36 | ); 37 | // Color encoding 38 | // RRR GGG BB 39 | assign color = (x<32) ? 8'h02 : (x<64) ? 8'hff : 8'he0; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /hdmi/buffer/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | output wifi_gpio0 6 | ); 7 | assign wifi_gpio0 = 1'b1; 8 | 9 | wire [23:0] color; 10 | wire [9:0] x; 11 | wire [9:0] y; 12 | 13 | reg [7:0] mem [0:2400]; 14 | 15 | integer k; 16 | 17 | initial 18 | begin 19 | for (k = 0; k < 2400; k = k + 1) 20 | mem[k] <= 32; 21 | mem[0] <= 8'd65; 22 | mem[1] <= 8'd66; 23 | mem[2] <= 8'd67; 24 | end 25 | 26 | wire [7:0] data_out; 27 | 28 | font_rom vga_font( 29 | .clk(clk_25mhz), 30 | .addr({ mem[(y >> 4) * 80 + (x>>3)], y[3:0] }), 31 | .data_out(data_out) 32 | ); 33 | 34 | assign color = data_out[7-x[2:0]+1] ? 24'hffffff : 24'h000000; // +1 for sync 35 | 36 | hdmi_video hdmi_video 37 | ( 38 | .clk_25mhz(clk_25mhz), 39 | .x(x), 40 | .y(y), 41 | .color(color), 42 | .gpdi_dp(gpdi_dp), 43 | .gpdi_dn(gpdi_dn) 44 | ); 45 | endmodule 46 | -------------------------------------------------------------------------------- /hdmi/sprite/sprite_rom.v: -------------------------------------------------------------------------------- 1 | module sprite_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [23:0] data_out 5 | ); 6 | 7 | reg [3:0] store[0:4095]; 8 | wire [23:0] palette[0:15]; 9 | 10 | assign palette[0] = 24'h000000; 11 | assign palette[1] = 24'h180002; 12 | assign palette[2] = 24'h240001; 13 | assign palette[3] = 24'h390100; 14 | assign palette[4] = 24'h530000; 15 | assign palette[5] = 24'h710000; 16 | assign palette[6] = 24'h8a0000; 17 | assign palette[7] = 24'ha20000; 18 | assign palette[8] = 24'hba0000; 19 | assign palette[9] = 24'hdd0002; 20 | assign palette[10] = 24'hff0000; 21 | assign palette[11] = 24'hff3031; 22 | assign palette[12] = 24'hff5f62; 23 | assign palette[13] = 24'hff8d8b; 24 | assign palette[14] = 24'hffcccb; 25 | assign palette[15] = 24'hffffff; 26 | 27 | initial 28 | begin 29 | $readmemh("sprite.mem", store); 30 | end 31 | 32 | always @(posedge clk) 33 | data_out <= palette[store[addr]]; 34 | endmodule 35 | -------------------------------------------------------------------------------- /computer/mc6850.v: -------------------------------------------------------------------------------- 1 | module mc6850( 2 | input clk, 3 | input reset, 4 | input addr, 5 | input [7:0] data_in, 6 | input rd, 7 | input we, 8 | output reg [7:0] data_out, 9 | input ce, 10 | input rx, 11 | output tx 12 | ); 13 | wire valid; 14 | wire tdre; 15 | wire [7:0] uart_out; 16 | wire dat_wait; 17 | 18 | simpleuart uart( 19 | .clk(clk), 20 | .resetn(~reset), 21 | 22 | .ser_tx(tx), 23 | .ser_rx(rx), 24 | 25 | .cfg_divider(25000000/9600), 26 | 27 | .reg_dat_we(we && (addr==1'b1)), 28 | .reg_dat_re(rd && (addr==1'b1)), 29 | .reg_dat_di(data_in & 8'h7f), 30 | .reg_dat_do(uart_out), 31 | .reg_dat_wait(dat_wait), 32 | .recv_buf_valid(valid), 33 | .tdre(tdre) 34 | ); 35 | 36 | always @(posedge clk) 37 | begin 38 | if (rd) 39 | begin 40 | if (addr==1'b0) 41 | data_out <= { 2'b00,valid, 1'b0, 2'b00, tdre, valid }; 42 | else 43 | data_out <= uart_out; 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /ps2/debug.v: -------------------------------------------------------------------------------- 1 | module debug #(parameter text_len = 20) ( 2 | input clk, 3 | input reset, 4 | input text_req, 5 | output reg text_done, 6 | input [8*text_len-1:0] debug_text, 7 | output uart_tx); 8 | 9 | reg [3:0] text_cntr; 10 | 11 | reg tx_req; 12 | reg [7:0] tx_data; 13 | wire tx_ready; 14 | 15 | uart_tx u_uart_tx ( 16 | .clk (clk), 17 | .reset (reset), 18 | .tx_req(tx_req), 19 | .tx_ready(tx_ready), 20 | .tx_data(tx_data), 21 | .uart_tx(uart_tx) 22 | ); 23 | 24 | // Output the text 25 | always @(posedge clk) begin 26 | if (text_req && text_cntr == 0 && !tx_req) begin 27 | text_cntr <= text_len; 28 | text_done <= 1'b1; 29 | end 30 | 31 | if (text_cntr == text_len || (text_cntr > 0 && tx_ready)) begin 32 | tx_data = debug_text[(text_cntr-1)*8 +: 8]; 33 | text_cntr <= text_cntr - 1; 34 | tx_req <= 1'b1; 35 | end else if (tx_ready) tx_req <= 1'b0; 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /ps2port/debug.v: -------------------------------------------------------------------------------- 1 | module debug #(parameter text_len = 20) ( 2 | input clk, 3 | input reset, 4 | input text_req, 5 | output reg text_done, 6 | input [8*text_len-1:0] debug_text, 7 | output uart_tx); 8 | 9 | reg [3:0] text_cntr; 10 | 11 | reg tx_req; 12 | reg [7:0] tx_data; 13 | wire tx_ready; 14 | 15 | uart_tx u_uart_tx ( 16 | .clk (clk), 17 | .reset (reset), 18 | .tx_req(tx_req), 19 | .tx_ready(tx_ready), 20 | .tx_data(tx_data), 21 | .uart_tx(uart_tx) 22 | ); 23 | 24 | // Output the text 25 | always @(posedge clk) begin 26 | if (text_req && text_cntr == 0 && !tx_req) begin 27 | text_cntr <= text_len; 28 | text_done <= 1'b1; 29 | end 30 | 31 | if (text_cntr == text_len || (text_cntr > 0 && tx_ready)) begin 32 | tx_data = debug_text[(text_cntr-1)*8 +: 8]; 33 | text_cntr <= text_cntr - 1; 34 | tx_req <= 1'b1; 35 | end else if (tx_ready) tx_req <= 1'b0; 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /usbemard/usbh_setup_rom.mem: -------------------------------------------------------------------------------- 1 | // minimal setup sequence is usually the most compatible 2 | // byte length of this sequence should be equal to 3 | // parameter "C_setup_rom_len" in file "usbh_host_hid.v" 4 | 5 | // set_address 1, Microsoft IntelliMouse needs address > 0 to activate reports 6 | 00 05 01 00 00 00 00 00 7 | // set_configuration 1, most devices need configuration = 1 to activate reports 8 | 00 09 01 00 00 00 00 00 9 | 10 | // transmission example 11 | // 00 09 01 00 00 00 00 00 12 | // HOST: < SYNC >EP0 CRC5 13 | // D+ ___-_-_-_---___--_-_-_-_-_-_-_--_-_____ 14 | // D- ---_-_-_-___---__-_-_-_-_-_-_-__-_-__-- 15 | // HOST: < SYNC >< 00 >< 09 >< 01 >< 00 >< 00 >< 00 >< 00 >< 00 >< CRC16 > 16 | // D+ ___-_-_-_----_-_---_-_-_-_--_--_-_--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-____-__-__--_--_-____ 17 | // D- ---_-_-_-____-_-___-_-_-_-__-__-_-__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_----_--_--__-__-___-- 18 | // MOUSE: < SYNC >< ACK > 19 | // D+ ___-_-_-_--__-__---_____ 20 | // D- ---_-_-_-__--_--_____--- 21 | -------------------------------------------------------------------------------- /usbhost/usbh_setup_rom.mem: -------------------------------------------------------------------------------- 1 | // minimal setup sequence is usually the most compatible 2 | // byte length of this sequence should be equal to 3 | // parameter "C_setup_rom_len" in file "usbh_host_hid.v" 4 | 5 | // set_address 1, Microsoft IntelliMouse needs address > 0 to activate reports 6 | 00 05 01 00 00 00 00 00 7 | // set_configuration 1, most devices need configuration = 1 to activate reports 8 | 00 09 01 00 00 00 00 00 9 | 10 | // transmission example 11 | // 00 09 01 00 00 00 00 00 12 | // HOST: < SYNC >EP0 CRC5 13 | // D+ ___-_-_-_---___--_-_-_-_-_-_-_--_-_____ 14 | // D- ---_-_-_-___---__-_-_-_-_-_-_-__-_-__-- 15 | // HOST: < SYNC >< 00 >< 09 >< 01 >< 00 >< 00 >< 00 >< 00 >< 00 >< CRC16 > 16 | // D+ ___-_-_-_----_-_---_-_-_-_--_--_-_--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-____-__-__--_--_-____ 17 | // D- ---_-_-_-____-_-___-_-_-_-__-__-_-__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_----_--_--__-__-___-- 18 | // MOUSE: < SYNC >< ACK > 19 | // D+ ___-_-_-_--__-__---_____ 20 | // D- ---_-_-_-__--_--_____--- 21 | -------------------------------------------------------------------------------- /cpu/ram_memory.v: -------------------------------------------------------------------------------- 1 | module ram_memory( 2 | input clk, 3 | input [11:0] addr, 4 | input [7:0] data_in, 5 | input we, 6 | output reg [7:0] data_out 7 | ); 8 | 9 | reg [7:0] store[0:4095] /* verilator public_flat */; 10 | 11 | initial 12 | begin 13 | $readmemh("boot.mem", store); 14 | `ifndef VERILATOR 15 | store[0] <= 8'b11100001; // MOV DS,2 16 | store[1] <= 8'b00000010; // 17 | store[2] <= 8'b01010100; // LOAD R1,[R0] 18 | store[3] <= 8'b00110001; // INC R1 19 | store[4] <= 8'b00110001; // INC R1 20 | store[5] <= 8'b01100001; // STORE [R0],R1 21 | store[6] <= 8'b11010001; // OUT [0],R1 22 | store[7] <= 8'b00000000; // 23 | store[8] <= 8'b00110001; // INC R1 24 | store[9] <= 8'b10100001; // CALL 0x100 25 | store[10] <= 8'b00000000; // 26 | store[11] <= 8'b01111111; // HLT 27 | 28 | 29 | store[256] <= 8'b11010001; // OUT [0],R1 30 | store[257] <= 8'b00000000; // 31 | store[258] <= 8'b01111110; // RET 32 | `endif 33 | end 34 | 35 | always @(posedge clk) 36 | if (we) 37 | store[addr] <= data_in; 38 | else 39 | data_out <= store[addr]; 40 | endmodule 41 | -------------------------------------------------------------------------------- /hdmi/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /pong/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/text/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /pong-hdmi/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /pong/ball/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /pong/game/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /pong/move/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /pong/wall/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /riscv/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/buffer/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/checkers/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/color/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/sprite/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/terminal/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /hdmi/tricolor/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/buffer/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/checkers/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/color/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/sprite/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/terminal/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/text/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /video/text/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | output wifi_gpio0 12 | ); 13 | assign wifi_gpio0 = 1'b1; 14 | 15 | wire clk; 16 | pll pll( 17 | .clki(clk_25mhz), 18 | .clko(clk), 19 | .locked() 20 | ); 21 | 22 | wire [7:0] x; 23 | wire [5:0] y; 24 | wire [7:0] color; 25 | 26 | spi_video video( 27 | .clk(clk), 28 | .oled_csn(oled_csn), 29 | .oled_clk(oled_clk), 30 | .oled_mosi(oled_mosi), 31 | .oled_dc(oled_dc), 32 | .oled_resn(oled_resn), 33 | .x(x), 34 | .y(y), 35 | .color(color) 36 | ); 37 | 38 | 39 | wire [7:0] data_out; 40 | 41 | font_rom vga_font( 42 | .clk(clk), 43 | .addr({ 8'd77, y[3:0] }), 44 | .data_out(data_out) 45 | ); 46 | 47 | assign color = data_out[7-x[2:0]+1] ? 8'hff : 8'h00; // +1 for sync 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /video/tricolor/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /protocols/spidisplay/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /usbhost/usbh_crc5.v: -------------------------------------------------------------------------------- 1 | module UsbCrc5 ( 2 | input [4:0] io_crc_i, 3 | input [10:0] io_data_i, 4 | output reg [4:0] io_crc_o); 5 | always @ (*) begin 6 | io_crc_o[0] = ((((((((io_data_i[10] ^ io_data_i[9]) ^ io_data_i[6]) ^ io_data_i[5]) ^ io_data_i[3]) ^ io_data_i[0]) ^ io_crc_i[0]) ^ io_crc_i[3]) ^ io_crc_i[4]); 7 | io_crc_o[1] = (((((((io_data_i[10] ^ io_data_i[7]) ^ io_data_i[6]) ^ io_data_i[4]) ^ io_data_i[1]) ^ io_crc_i[0]) ^ io_crc_i[1]) ^ io_crc_i[4]); 8 | io_crc_o[2] = ((((((((((((io_data_i[10] ^ io_data_i[9]) ^ io_data_i[8]) ^ io_data_i[7]) ^ io_data_i[6]) ^ io_data_i[3]) ^ io_data_i[2]) ^ io_data_i[0]) ^ io_crc_i[0]) ^ io_crc_i[1]) ^ io_crc_i[2]) ^ io_crc_i[3]) ^ io_crc_i[4]); 9 | io_crc_o[3] = ((((((((((io_data_i[10] ^ io_data_i[9]) ^ io_data_i[8]) ^ io_data_i[7]) ^ io_data_i[4]) ^ io_data_i[3]) ^ io_data_i[1]) ^ io_crc_i[1]) ^ io_crc_i[2]) ^ io_crc_i[3]) ^ io_crc_i[4]); 10 | io_crc_o[4] = ((((((((io_data_i[10] ^ io_data_i[9]) ^ io_data_i[8]) ^ io_data_i[5]) ^ io_data_i[4]) ^ io_data_i[2]) ^ io_crc_i[2]) ^ io_crc_i[3]) ^ io_crc_i[4]); 11 | end 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hdmi/menu/sdcard.v: -------------------------------------------------------------------------------- 1 | 2 | module sdcard 3 | ( 4 | input resetn, 5 | input clk, 6 | input iomem_valid, 7 | output reg iomem_ready, 8 | input [3:0] iomem_wstrb, 9 | input [31:0] iomem_addr, 10 | input [31:0] iomem_wdata, 11 | output reg [31:0] iomem_rdata, 12 | inout SD_MOSI, 13 | inout SD_MISO, 14 | inout SD_SCK, 15 | inout SD_CS); 16 | 17 | reg spi_wr, spi_rd; 18 | reg [31:0] spi_rdata; 19 | reg spi_ready; 20 | spi_master #(.CLOCK_FREQ_HZ(25000000), .CS_LENGTH(1)) sd ( 21 | .clk(clk), 22 | .resetn(resetn), 23 | .ctrl_wr(spi_wr), 24 | .ctrl_rd(spi_rd), 25 | .ctrl_addr(iomem_addr[7:0]), 26 | .ctrl_wdat(iomem_wdata), 27 | .ctrl_rdat(spi_rdata), 28 | .ctrl_done(spi_ready), 29 | .mosi(SD_MOSI), 30 | .miso(SD_MISO), 31 | .sclk(SD_SCK), 32 | .CS(SD_CS)); 33 | 34 | 35 | always @(posedge clk) begin 36 | spi_wr <= 0; 37 | spi_rd <= 0; 38 | iomem_ready <= 0; 39 | if (iomem_valid && !iomem_ready) begin 40 | iomem_ready <= spi_ready; 41 | iomem_rdata <= spi_rdata; 42 | spi_wr <= spi_ready ? 0 : |iomem_wstrb; 43 | spi_rd <= !iomem_wstrb && !spi_ready; 44 | end 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /hdmi/menu/flash_write.v: -------------------------------------------------------------------------------- 1 | 2 | module flash_write 3 | ( 4 | input resetn, 5 | input clk, 6 | input iomem_valid, 7 | output reg iomem_ready, 8 | input [3:0] iomem_wstrb, 9 | input [31:0] iomem_addr, 10 | input [31:0] iomem_wdata, 11 | output reg [31:0] iomem_rdata, 12 | inout SPI_MOSI, 13 | inout SPI_MISO, 14 | inout SPI_SCK, 15 | inout SPI_CS); 16 | 17 | reg spi_wr, spi_rd; 18 | reg [31:0] spi_rdata; 19 | reg spi_ready; 20 | spi_master #(.CLOCK_FREQ_HZ(25000000), .CS_LENGTH(1)) sd ( 21 | .clk(clk), 22 | .resetn(resetn), 23 | .ctrl_wr(spi_wr), 24 | .ctrl_rd(spi_rd), 25 | .ctrl_addr(iomem_addr[7:0]), 26 | .ctrl_wdat(iomem_wdata), 27 | .ctrl_rdat(spi_rdata), 28 | .ctrl_done(spi_ready), 29 | .mosi(SPI_MOSI), 30 | .miso(SPI_MISO), 31 | .sclk(SPI_SCK), 32 | .CS(SPI_CS)); 33 | 34 | 35 | always @(posedge clk) begin 36 | spi_wr <= 0; 37 | spi_rd <= 0; 38 | iomem_ready <= 0; 39 | if (iomem_valid && !iomem_ready) begin 40 | iomem_ready <= spi_ready; 41 | iomem_rdata <= spi_rdata; 42 | spi_wr <= spi_ready ? 0 : iomem_wstrb; 43 | spi_rd <= !iomem_wstrb && !spi_ready; 44 | end 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /audio/piano/audio.v: -------------------------------------------------------------------------------- 1 | module audio( 2 | input clk_25mhz, 3 | output wifi_gpio0, 4 | input [6:0] btn, 5 | output reg [3:0] audio_l, 6 | output reg [3:0] audio_r); 7 | 8 | parameter TONE_A4 = 25000000/440/2; 9 | parameter TONE_B4 = 25000000/494/2; 10 | parameter TONE_C5 = 25000000/523/2; 11 | parameter TONE_D5 = 25000000/587/2; 12 | parameter TONE_E5 = 25000000/659/2; 13 | parameter TONE_F5 = 25000000/698/2; 14 | parameter TONE_G5 = 25000000/783/2; 15 | 16 | reg [25:0] counter; 17 | initial 18 | begin 19 | audio_l = 0; 20 | audio_r = 0; 21 | counter = 0; 22 | end 23 | 24 | always @(posedge clk_25mhz) 25 | if(counter==26'b0) counter <= (btn[6] ? TONE_A4-1 : 26 | btn[5] ? TONE_B4-1 : 27 | btn[4] ? TONE_C5-1 : 28 | btn[3] ? TONE_D5-1 : 29 | btn[2] ? TONE_E5-1 : 30 | btn[1] ? TONE_F5-1 : 31 | 0); else counter <= counter-1; 32 | 33 | always @(posedge clk_25mhz) 34 | if(counter==0) 35 | begin 36 | audio_l <= ~audio_l; 37 | audio_r <= ~audio_r; 38 | end 39 | 40 | assign wifi_gpio0 = 1'b1; 41 | endmodule 42 | -------------------------------------------------------------------------------- /st7735/st7735_init.mem: -------------------------------------------------------------------------------- 1 | // SWRESET, delay 180 2 | 01 3 | 80 4 | B4 5 | // SLPOUT, delay 180 6 | 11 7 | 80 8 | B4 9 | // FRMCTR1 10 | B1 11 | 03 12 | 01 13 | 2C 14 | 2D 15 | // FRMCTR2 16 | B2 17 | 03 18 | 01 19 | 2C 20 | 2D 21 | // FRMCTR3 22 | B3 23 | 06 24 | 01 25 | 2C 26 | 2D 27 | 01 28 | 2C 29 | 2D 30 | // PWCTR1 31 | C0 32 | 03 33 | A2 34 | 02 35 | 84 36 | // PWCTR2 37 | C1 38 | 01 39 | C5 40 | // PWCTR3 41 | C2 42 | 02 43 | 0A 44 | 00 45 | // PWCTR4 46 | C3 47 | 02 48 | 8A 49 | 2A 50 | // PWCTR5 51 | C4 52 | 02 53 | 8A 54 | EE 55 | // VMCTR1 56 | C5 57 | 01 58 | 0E 59 | // INVOFF 60 | 20 61 | 00 62 | // MADCTL 63 | 36 64 | 01 65 | 44 66 | // COLMOD 67 | 3A 68 | 01 69 | 05 70 | // GMCTRP1 71 | E0 72 | 10 73 | 02 74 | 1C 75 | 07 76 | 12 77 | 37 78 | 32 79 | 29 80 | 2D 81 | 29 82 | 25 83 | 2B 84 | 39 85 | 00 86 | 01 87 | 03 88 | 10 89 | // GMCTRN1 90 | E1 91 | 10 92 | 03 93 | 1D 94 | 07 95 | 06 96 | 2E 97 | 2C 98 | 29 99 | 2D 100 | 2E 101 | 2E 102 | 37 103 | 3F 104 | 00 105 | 00 106 | 02 107 | 10 108 | // NORON 109 | 13 110 | 00 111 | // DISPON, delay 180 112 | 29 113 | 80 114 | B4 115 | // CASET 116 | 2A 117 | 04 118 | 00 119 | 02 120 | 00 121 | 81 122 | // RASET 123 | 2B 124 | 04 125 | 00 126 | 01 127 | 00 128 | A0 129 | // RAMWR 130 | 2C 131 | 00 132 | 133 | -------------------------------------------------------------------------------- /video/buffer/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | output wifi_gpio0 12 | ); 13 | assign wifi_gpio0 = 1'b1; 14 | 15 | wire clk; 16 | pll pll( 17 | .clki(clk_25mhz), 18 | .clko(clk), 19 | .locked() 20 | ); 21 | 22 | wire [7:0] x; 23 | wire [5:0] y; 24 | wire [7:0] color; 25 | 26 | spi_video video( 27 | .clk(clk), 28 | .oled_csn(oled_csn), 29 | .oled_clk(oled_clk), 30 | .oled_mosi(oled_mosi), 31 | .oled_dc(oled_dc), 32 | .oled_resn(oled_resn), 33 | .x(x), 34 | .y(y), 35 | .color(color) 36 | ); 37 | 38 | reg [7:0] mem [0:47]; 39 | 40 | integer k; 41 | 42 | initial 43 | begin 44 | for (k = 0; k < 48; k = k + 1) 45 | mem[k] <= 32; 46 | mem[0] <= 8'd65; 47 | mem[1] <= 8'd66; 48 | mem[2] <= 8'd67; 49 | end 50 | 51 | wire [7:0] data_out; 52 | 53 | font_rom vga_font( 54 | .clk(clk), 55 | .addr({ mem[(y >> 4) * 12 + (x>>3)], y[3:0] }), 56 | .data_out(data_out) 57 | ); 58 | 59 | assign color = data_out[7-x[2:0]+1] ? 8'hff : 8'h00; // +1 for sync 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /hdmi/clk_25_250_125_25.v: -------------------------------------------------------------------------------- 1 | module clk_25_250_125_25(input clki, 2 | output clks1, 3 | output clks2, 4 | output locked, 5 | output clko 6 | ); 7 | wire clkfb; 8 | wire clkos; 9 | wire clkop; 10 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 11 | EHXPLLL #( 12 | .PLLRST_ENA("DISABLED"), 13 | .INTFB_WAKE("DISABLED"), 14 | .STDBY_ENABLE("DISABLED"), 15 | .DPHASE_SOURCE("DISABLED"), 16 | .CLKOP_FPHASE(0), 17 | .CLKOP_CPHASE(0), 18 | .OUTDIVIDER_MUXA("DIVA"), 19 | .CLKOP_ENABLE("ENABLED"), 20 | .CLKOP_DIV(2), 21 | .CLKOS_ENABLE("ENABLED"), 22 | .CLKOS_DIV(4), 23 | .CLKOS_CPHASE(0), 24 | .CLKOS_FPHASE(0), 25 | .CLKOS2_ENABLE("ENABLED"), 26 | .CLKOS2_DIV(20), 27 | .CLKOS2_CPHASE(0), 28 | .CLKOS2_FPHASE(0), 29 | .CLKFB_DIV(10), 30 | .CLKI_DIV(1), 31 | .FEEDBK_PATH("INT_OP") 32 | ) pll_i ( 33 | .CLKI(clki), 34 | .CLKFB(clkfb), 35 | .CLKINTFB(clkfb), 36 | .CLKOP(clkop), 37 | .CLKOS(clks1), 38 | .CLKOS2(clks2), 39 | .RST(1'b0), 40 | .STDBY(1'b0), 41 | .PHASESEL0(1'b0), 42 | .PHASESEL1(1'b0), 43 | .PHASEDIR(1'b0), 44 | .PHASESTEP(1'b0), 45 | .PLLWAKESYNC(1'b0), 46 | .ENCLKOP(1'b0), 47 | .LOCK(locked) 48 | ); 49 | assign clko = clkop; 50 | endmodule 51 | -------------------------------------------------------------------------------- /pong-hdmi/clk_25_250_125_25.v: -------------------------------------------------------------------------------- 1 | module clk_25_250_125_25(input clki, 2 | output clks1, 3 | output clks2, 4 | output locked, 5 | output clko 6 | ); 7 | wire clkfb; 8 | wire clkos; 9 | wire clkop; 10 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 11 | EHXPLLL #( 12 | .PLLRST_ENA("DISABLED"), 13 | .INTFB_WAKE("DISABLED"), 14 | .STDBY_ENABLE("DISABLED"), 15 | .DPHASE_SOURCE("DISABLED"), 16 | .CLKOP_FPHASE(0), 17 | .CLKOP_CPHASE(0), 18 | .OUTDIVIDER_MUXA("DIVA"), 19 | .CLKOP_ENABLE("ENABLED"), 20 | .CLKOP_DIV(2), 21 | .CLKOS_ENABLE("ENABLED"), 22 | .CLKOS_DIV(4), 23 | .CLKOS_CPHASE(0), 24 | .CLKOS_FPHASE(0), 25 | .CLKOS2_ENABLE("ENABLED"), 26 | .CLKOS2_DIV(20), 27 | .CLKOS2_CPHASE(0), 28 | .CLKOS2_FPHASE(0), 29 | .CLKFB_DIV(10), 30 | .CLKI_DIV(1), 31 | .FEEDBK_PATH("INT_OP") 32 | ) pll_i ( 33 | .CLKI(clki), 34 | .CLKFB(clkfb), 35 | .CLKINTFB(clkfb), 36 | .CLKOP(clkop), 37 | .CLKOS(clks1), 38 | .CLKOS2(clks2), 39 | .RST(1'b0), 40 | .STDBY(1'b0), 41 | .PHASESEL0(1'b0), 42 | .PHASESEL1(1'b0), 43 | .PHASEDIR(1'b0), 44 | .PHASESTEP(1'b0), 45 | .PLLWAKESYNC(1'b0), 46 | .ENCLKOP(1'b0), 47 | .LOCK(locked) 48 | ); 49 | assign clko = clkop; 50 | endmodule 51 | -------------------------------------------------------------------------------- /oled/oled_init_16bit.mem: -------------------------------------------------------------------------------- 1 | // This file must be in the directory from where 2 | // the verilog compiler is running. 3 | // The path to this file is not relative to the 4 | // verilog source that needs to include this file. 5 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 6 | // 44 bytes follow: 7 | // 0: NOP 8 | BC 9 | // 1: Set display off 10 | AE 11 | // 2: Set data format 12 | // A0 20 normal 8bpp 13 | // A0 22 X-flip 8bpp 14 | // A0 30 Y-flip 8bpp 15 | // A0 32 XY-flip 8bpp 16 | // A0 60 normal 16bpp 17 | // A0 62 X-flip 16bpp 18 | // A0 70 Y-flip 16bpp 19 | // A0 72 XY-flip 16bpp 20 | A0 21 | 60 22 | // 4: Set display start line 23 | A1 24 | 00 25 | // 6: Set display offset 26 | A2 27 | 00 28 | // 8: Set display mode normal 29 | A4 30 | // 9: Set multiplex ratio 31 | A8 32 | 3F 33 | // 11: Set master configuration 34 | AD 35 | 8E 36 | // 13: Set power save mode 37 | B0 38 | 00 39 | // 15: Phase 1/2 period adjustment 40 | B1 41 | 74 42 | // 17: Set display clock divider 43 | F0 44 | F0 45 | // 19: Set precharge A 46 | 8A 47 | 64 48 | // 21: Set precharge B 49 | 8B 50 | 78 51 | // 23: Set precharge C 52 | 8C 53 | 64 54 | // 25: Set precharge voltage 55 | BB 56 | 31 57 | // 27: Set contrast A 58 | 81 59 | FF 60 | // 29: Set contrast B 61 | 82 62 | FF 63 | // 31: Set contrast C 64 | 83 65 | FF 66 | // 33: Set Vcomh voltage 67 | BE 68 | 3E 69 | // 35: Master current control 70 | 87 71 | 06 72 | // 37: Set column address 73 | 15 74 | 00 75 | 5F 76 | // 40: Set row address 77 | 75 78 | 00 79 | 3F 80 | // 43: Set display on 81 | AF 82 | -------------------------------------------------------------------------------- /ps2send/PushButton_Debouncer.v: -------------------------------------------------------------------------------- 1 | module PushButton_Debouncer( 2 | input clk, 3 | input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal 4 | 5 | // from which we make three outputs, all synchronous to the clock 6 | output reg PB_state, // 1 as long as the push-button is active (down) 7 | output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed) 8 | output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released) 9 | ); 10 | 11 | // First use two flip-flops to synchronize the PB signal the "clk" clock domain 12 | reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high 13 | reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0; 14 | 15 | // Next declare a 16-bits counter 16 | reg [15:0] PB_cnt; 17 | 18 | // When the push-button is pushed or released, we increment the counter 19 | // The counter has to be maxed out before we decide that the push-button state has changed 20 | 21 | wire PB_idle = (PB_state==PB_sync_1); 22 | wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's 23 | 24 | always @(posedge clk) 25 | if(PB_idle) 26 | PB_cnt <= 0; // nothing's going on 27 | else 28 | begin 29 | PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter 30 | if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed! 31 | end 32 | 33 | assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state; 34 | assign PB_up = ~PB_idle & PB_cnt_max & PB_state; 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /hdmi/menu/PushButton_Debouncer.v: -------------------------------------------------------------------------------- 1 | module PushButton_Debouncer( 2 | input clk, 3 | input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal 4 | 5 | // from which we make three outputs, all synchronous to the clock 6 | output reg PB_state = 1, // 1 as long as the push-button is active (down) 7 | output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed) 8 | output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released) 9 | ); 10 | 11 | // First use two flip-flops to synchronize the PB signal the "clk" clock domain 12 | reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high 13 | reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0; 14 | 15 | // Next declare a 16-bits counter 16 | reg [15:0] PB_cnt; 17 | 18 | // When the push-button is pushed or released, we increment the counter 19 | // The counter has to be maxed out before we decide that the push-button state has changed 20 | 21 | wire PB_idle = (PB_state==PB_sync_1); 22 | wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's 23 | 24 | always @(posedge clk) 25 | if(PB_idle) 26 | PB_cnt <= 0; // nothing's going on 27 | else 28 | begin 29 | PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter 30 | if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed! 31 | end 32 | 33 | assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state; 34 | assign PB_up = ~PB_idle & PB_cnt_max & PB_state; 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /hdmi/fake_differential.v: -------------------------------------------------------------------------------- 1 | // DDR mode uses Lattice ECP5 vendor-specific module ODDRX1F 2 | 3 | module fake_differential 4 | ( 5 | input clk_shift, // used only in DDR mode 6 | // [1:0]:DDR [0]:SDR TMDS 7 | input [1:0] in_clock, in_red, in_green, in_blue, 8 | // [3]:clock [2]:red [1]:green [0]:blue 9 | output [3:0] out_p, out_n 10 | ); 11 | wire [1:0] tmds[3:0]; 12 | assign tmds[3] = in_clock; 13 | assign tmds[2] = in_red; 14 | assign tmds[1] = in_green; 15 | assign tmds[0] = in_blue; 16 | 17 | // register stage to improve timing of the fake differential 18 | reg [1:0] R_tmds_p[3:0], R_tmds_n[3:0]; 19 | generate 20 | genvar i; 21 | for(i = 0; i < 4; i++) 22 | begin : TMDS_pn_registers 23 | always @(posedge clk_shift) R_tmds_p[i] <= tmds[i]; 24 | always @(posedge clk_shift) R_tmds_n[i] <= ~tmds[i]; 25 | end 26 | endgenerate 27 | 28 | // output SDR/DDR to fake differential 29 | generate 30 | genvar i; 31 | for(i = 0; i < 4; i++) 32 | begin : DDR_output_mode 33 | ODDRX1F 34 | ddr_p_instance 35 | ( 36 | .D0(R_tmds_p[i][0]), 37 | .D1(R_tmds_p[i][1]), 38 | .Q(out_p[i]), 39 | .SCLK(clk_shift), 40 | .RST(0) 41 | ); 42 | ODDRX1F 43 | ddr_n_instance 44 | ( 45 | .D0(R_tmds_n[i][0]), 46 | .D1(R_tmds_n[i][1]), 47 | .Q(out_n[i]), 48 | .SCLK(clk_shift), 49 | .RST(0) 50 | ); 51 | end 52 | endgenerate 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /pong-hdmi/fake_differential.v: -------------------------------------------------------------------------------- 1 | // DDR mode uses Lattice ECP5 vendor-specific module ODDRX1F 2 | 3 | module fake_differential 4 | ( 5 | input clk_shift, // used only in DDR mode 6 | // [1:0]:DDR [0]:SDR TMDS 7 | input [1:0] in_clock, in_red, in_green, in_blue, 8 | // [3]:clock [2]:red [1]:green [0]:blue 9 | output [3:0] out_p, out_n 10 | ); 11 | wire [1:0] tmds[3:0]; 12 | assign tmds[3] = in_clock; 13 | assign tmds[2] = in_red; 14 | assign tmds[1] = in_green; 15 | assign tmds[0] = in_blue; 16 | 17 | // register stage to improve timing of the fake differential 18 | reg [1:0] R_tmds_p[3:0], R_tmds_n[3:0]; 19 | generate 20 | genvar i; 21 | for(i = 0; i < 4; i++) 22 | begin : TMDS_pn_registers 23 | always @(posedge clk_shift) R_tmds_p[i] <= tmds[i]; 24 | always @(posedge clk_shift) R_tmds_n[i] <= ~tmds[i]; 25 | end 26 | endgenerate 27 | 28 | // output SDR/DDR to fake differential 29 | generate 30 | genvar i; 31 | for(i = 0; i < 4; i++) 32 | begin : DDR_output_mode 33 | ODDRX1F 34 | ddr_p_instance 35 | ( 36 | .D0(R_tmds_p[i][0]), 37 | .D1(R_tmds_p[i][1]), 38 | .Q(out_p[i]), 39 | .SCLK(clk_shift), 40 | .RST(0) 41 | ); 42 | ODDRX1F 43 | ddr_n_instance 44 | ( 45 | .D0(R_tmds_n[i][0]), 46 | .D1(R_tmds_n[i][1]), 47 | .Q(out_n[i]), 48 | .SCLK(clk_shift), 49 | .RST(0) 50 | ); 51 | end 52 | endgenerate 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /hdmi/vga_video.v: -------------------------------------------------------------------------------- 1 | module vga_video (input clk, 2 | input resetn, 3 | output reg vga_hsync, 4 | output reg vga_vsync, 5 | output reg vga_blank, 6 | output reg [9:0] h_pos, 7 | output reg [9:0] v_pos 8 | ); 9 | 10 | 11 | parameter h_visible = 10'd640; 12 | parameter h_front = 10'd16; 13 | parameter h_sync = 10'd96; 14 | parameter h_back = 10'd44; 15 | parameter h_total = h_visible + h_front + h_sync + h_back; 16 | 17 | parameter v_visible = 10'd480; 18 | parameter v_front = 10'd10; 19 | parameter v_sync = 10'd2; 20 | parameter v_back = 10'd31; 21 | parameter v_total = v_visible + v_front + v_sync + v_back; 22 | 23 | wire h_active, v_active, visible; 24 | 25 | always @(posedge clk) 26 | begin 27 | if (resetn == 0) begin 28 | h_pos <= 10'b0; 29 | v_pos <= 10'b0; 30 | 31 | end else begin 32 | //Pixel counters 33 | if (h_pos == h_total - 1) begin 34 | h_pos <= 0; 35 | if (v_pos == v_total - 1) begin 36 | v_pos <= 0; 37 | end else begin 38 | v_pos <= v_pos + 1; 39 | end 40 | end else begin 41 | h_pos <= h_pos + 1; 42 | end 43 | vga_blank <= !visible; 44 | vga_hsync <= !((h_pos >= (h_visible + h_front)) && (h_pos < (h_visible + h_front + h_sync))); 45 | vga_vsync <= !((v_pos >= (v_visible + v_front)) && (v_pos < (v_visible + v_front + v_sync))); 46 | end 47 | end 48 | 49 | assign h_active = (h_pos < h_visible); 50 | assign v_active = (v_pos < v_visible); 51 | assign visible = h_active && v_active; 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /pong-hdmi/vga_video.v: -------------------------------------------------------------------------------- 1 | module vga_video (input clk, 2 | input resetn, 3 | output reg vga_hsync, 4 | output reg vga_vsync, 5 | output reg vga_blank, 6 | output reg [9:0] h_pos, 7 | output reg [9:0] v_pos 8 | ); 9 | 10 | 11 | parameter h_visible = 10'd640; 12 | parameter h_front = 10'd16; 13 | parameter h_sync = 10'd96; 14 | parameter h_back = 10'd44; 15 | parameter h_total = h_visible + h_front + h_sync + h_back; 16 | 17 | parameter v_visible = 10'd480; 18 | parameter v_front = 10'd10; 19 | parameter v_sync = 10'd2; 20 | parameter v_back = 10'd31; 21 | parameter v_total = v_visible + v_front + v_sync + v_back; 22 | 23 | wire h_active, v_active, visible; 24 | 25 | always @(posedge clk) 26 | begin 27 | if (resetn == 0) begin 28 | h_pos <= 10'b0; 29 | v_pos <= 10'b0; 30 | 31 | end else begin 32 | //Pixel counters 33 | if (h_pos == h_total - 1) begin 34 | h_pos <= 0; 35 | if (v_pos == v_total - 1) begin 36 | v_pos <= 0; 37 | end else begin 38 | v_pos <= v_pos + 1; 39 | end 40 | end else begin 41 | h_pos <= h_pos + 1; 42 | end 43 | vga_blank <= !visible; 44 | vga_hsync <= !((h_pos >= (h_visible + h_front)) && (h_pos < (h_visible + h_front + h_sync))); 45 | vga_vsync <= !((v_pos >= (v_visible + v_front)) && (v_pos < (v_visible + v_front + v_sync))); 46 | end 47 | end 48 | 49 | assign h_active = (h_pos < h_visible); 50 | assign v_active = (v_pos < v_visible); 51 | assign visible = h_active && v_active; 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdmi/hdmi_video.v: -------------------------------------------------------------------------------- 1 | module hdmi_video( 2 | input clk_25mhz, 3 | output [9:0] x, 4 | output [9:0] y, 5 | input [23:0] color, 6 | output [3:0] gpdi_dp, gpdi_dn, 7 | output vga_vsync, 8 | output vga_hsync, 9 | output vga_blank, 10 | output clk_locked 11 | ); 12 | // clock generator 13 | wire clk_250MHz, clk_125MHz, clk_25MHz; 14 | clk_25_250_125_25 15 | clock_instance 16 | ( 17 | .clki(clk_25mhz), 18 | .clko(clk_250MHz), 19 | .clks1(clk_125MHz), 20 | .clks2(clk_25MHz), 21 | .locked(clk_locked) 22 | ); 23 | 24 | vga_video vga_instance 25 | ( 26 | .clk(clk_25MHz), 27 | .resetn(clk_locked), 28 | .vga_hsync(vga_hsync), 29 | .vga_vsync(vga_vsync), 30 | .vga_blank(vga_blank), 31 | .h_pos(x), 32 | .v_pos(y) 33 | ); 34 | 35 | // VGA to digital video converter 36 | wire [1:0] tmds[3:0]; 37 | vga2dvid vga2dvid_instance 38 | ( 39 | .clk_pixel(clk_25MHz), 40 | .clk_shift(clk_125MHz), 41 | .in_color(color), 42 | .in_hsync(vga_hsync), 43 | .in_vsync(vga_vsync), 44 | .in_blank(vga_blank), 45 | .out_clock(tmds[3]), 46 | .out_red(tmds[2]), 47 | .out_green(tmds[1]), 48 | .out_blue(tmds[0]), 49 | .resetn(clk_locked), 50 | ); 51 | 52 | // output TMDS SDR/DDR data to fake differential lanes 53 | fake_differential fake_differential_instance 54 | ( 55 | .clk_shift(clk_125MHz), 56 | .in_clock(tmds[3]), 57 | .in_red(tmds[2]), 58 | .in_green(tmds[1]), 59 | .in_blue(tmds[0]), 60 | .out_p(gpdi_dp), 61 | .out_n(gpdi_dn) 62 | ); 63 | endmodule 64 | -------------------------------------------------------------------------------- /pong-hdmi/hdmi_video.v: -------------------------------------------------------------------------------- 1 | module hdmi_video( 2 | input clk_25mhz, 3 | output [9:0] x, 4 | output [9:0] y, 5 | input [23:0] color, 6 | output [3:0] gpdi_dp, gpdi_dn, 7 | output vga_vsync, 8 | output vga_hsync, 9 | output vga_blank, 10 | output clk_locked 11 | ); 12 | // clock generator 13 | wire clk_250MHz, clk_125MHz, clk_25MHz; 14 | clk_25_250_125_25 15 | clock_instance 16 | ( 17 | .clki(clk_25mhz), 18 | .clko(clk_250MHz), 19 | .clks1(clk_125MHz), 20 | .clks2(clk_25MHz), 21 | .locked(clk_locked) 22 | ); 23 | 24 | vga_video vga_instance 25 | ( 26 | .clk(clk_25MHz), 27 | .resetn(clk_locked), 28 | .vga_hsync(vga_hsync), 29 | .vga_vsync(vga_vsync), 30 | .vga_blank(vga_blank), 31 | .h_pos(x), 32 | .v_pos(y) 33 | ); 34 | 35 | // VGA to digital video converter 36 | wire [1:0] tmds[3:0]; 37 | vga2dvid vga2dvid_instance 38 | ( 39 | .clk_pixel(clk_25MHz), 40 | .clk_shift(clk_125MHz), 41 | .in_color(color), 42 | .in_hsync(vga_hsync), 43 | .in_vsync(vga_vsync), 44 | .in_blank(vga_blank), 45 | .out_clock(tmds[3]), 46 | .out_red(tmds[2]), 47 | .out_green(tmds[1]), 48 | .out_blue(tmds[0]), 49 | .resetn(clk_locked), 50 | ); 51 | 52 | // output TMDS SDR/DDR data to fake differential lanes 53 | fake_differential fake_differential_instance 54 | ( 55 | .clk_shift(clk_125MHz), 56 | .in_clock(tmds[3]), 57 | .in_red(tmds[2]), 58 | .in_green(tmds[1]), 59 | .in_blue(tmds[0]), 60 | .out_p(gpdi_dp), 61 | .out_n(gpdi_dn) 62 | ); 63 | endmodule 64 | -------------------------------------------------------------------------------- /hdmi/sprite/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | input [6:0] btn, 6 | output wifi_gpio0 7 | ); 8 | assign wifi_gpio0 = 1'b1; 9 | 10 | wire locked; 11 | wire [23:0] color; 12 | wire [9:0] x; 13 | wire [9:0] y; 14 | 15 | reg [9:0] pos_x; 16 | reg [9:0] pos_y; 17 | 18 | wire [23:0] sprite_rgb; 19 | 20 | wire [9:0] sprite_x; 21 | wire [9:0] sprite_y; 22 | 23 | assign sprite_x = x - pos_x; 24 | assign sprite_y = y - pos_y; 25 | 26 | sprite_rom sprite( 27 | .clk(clk_25mhz), 28 | .addr({ sprite_y[5:0], sprite_x[5:0] }), 29 | .data_out(sprite_rgb)); 30 | 31 | assign color = (x > pos_x && x < pos_x + 64 && y > pos_y && y < pos_y + 64) ? sprite_rgb : 24'hffffff; 32 | 33 | reg [15:0] counter; 34 | 35 | always @(posedge clk_25mhz) begin 36 | counter <= counter + 1; 37 | end 38 | 39 | always @(posedge counter[15]) 40 | begin 41 | if (!locked) 42 | begin 43 | pos_x <= 0; 44 | pos_y <= 0; 45 | end 46 | if (btn[5]==1'b1) 47 | pos_x <= (pos_x > 0) ? pos_x - 1 : pos_x; 48 | if (btn[6]==1'b1) 49 | pos_x <= (pos_x < 640-64) ? pos_x +1 : pos_x; 50 | if (btn[3]==1'b1) 51 | pos_y <= (pos_y > 0) ? pos_y - 1 : pos_y; 52 | if (btn[4]==1'b1) 53 | pos_y <= (pos_y < 480-64) ? pos_y +1 : pos_y; 54 | end 55 | 56 | hdmi_video hdmi_video 57 | ( 58 | .clk_25mhz(clk_25mhz), 59 | .x(x), 60 | .y(y), 61 | .color(color), 62 | .gpdi_dp(gpdi_dp), 63 | .gpdi_dn(gpdi_dn), 64 | .clk_locked(locked) 65 | ); 66 | endmodule 67 | -------------------------------------------------------------------------------- /riscv/console/firmware.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define LED (*(volatile uint32_t*)0x02000000) 4 | 5 | #define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004) 6 | #define reg_uart_data (*(volatile uint32_t*)0x02000008) 7 | 8 | void putchar(char c) 9 | { 10 | if (c == '\n') 11 | putchar('\r'); 12 | reg_uart_data = c; 13 | } 14 | 15 | void print(const char *p) 16 | { 17 | while (*p) 18 | putchar(*(p++)); 19 | } 20 | 21 | void delay() { 22 | for (volatile int i = 0; i < 25000; i++) 23 | ; 24 | } 25 | 26 | char getchar_prompt(char *prompt) 27 | { 28 | int32_t c = -1; 29 | 30 | uint32_t cycles_begin, cycles_now, cycles; 31 | __asm__ volatile ("rdcycle %0" : "=r"(cycles_begin)); 32 | 33 | if (prompt) 34 | print(prompt); 35 | 36 | while (c == -1) { 37 | __asm__ volatile ("rdcycle %0" : "=r"(cycles_now)); 38 | cycles = cycles_now - cycles_begin; 39 | if (cycles > 12000000) { 40 | if (prompt) 41 | print(prompt); 42 | cycles_begin = cycles_now; 43 | } 44 | c = reg_uart_data; 45 | } 46 | return c; 47 | } 48 | 49 | int main() { 50 | // 9600 baud at 50MHz 51 | reg_uart_clkdiv = 1302; 52 | while (getchar_prompt("Press ENTER to continue..\n") != '\r') { /* wait */ } 53 | 54 | print("\n"); 55 | print(" ____ _ ____ ____\n"); 56 | print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n"); 57 | print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n"); 58 | print(" | __/| | (_| (_) |__) | (_) | |___\n"); 59 | print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n"); 60 | print("\n"); 61 | print("Blinking leds demo....\n"); 62 | while (1) { 63 | LED = 0xFF; 64 | delay(); 65 | delay(); 66 | delay(); 67 | LED = 0x00; 68 | delay(); 69 | delay(); 70 | delay(); 71 | } 72 | } 73 | -------------------------------------------------------------------------------- /video/sprite/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | input [6:0] btn, 12 | output wifi_gpio0 13 | ); 14 | assign wifi_gpio0 = 1'b1; 15 | 16 | wire clk; 17 | pll pll( 18 | .clki(clk_25mhz), 19 | .clko(clk), 20 | .locked() 21 | ); 22 | 23 | wire [7:0] x; 24 | wire [5:0] y; 25 | wire [7:0] color; 26 | 27 | spi_video video( 28 | .clk(clk), 29 | .oled_csn(oled_csn), 30 | .oled_clk(oled_clk), 31 | .oled_mosi(oled_mosi), 32 | .oled_dc(oled_dc), 33 | .oled_resn(oled_resn), 34 | .x(x), 35 | .y(y), 36 | .color(color) 37 | ); 38 | 39 | reg [7:0] pos_x; 40 | reg [5:0] pos_y; 41 | 42 | initial 43 | begin 44 | pos_x <= 0; 45 | pos_y <= 0; 46 | end 47 | 48 | wire [7:0] sprite_rgb; 49 | 50 | wire [7:0] sprite_x; 51 | wire [5:0] sprite_y; 52 | 53 | assign sprite_x = x - pos_x; 54 | assign sprite_y = y - pos_y; 55 | 56 | sprite_rom sprite( 57 | .clk(clk), 58 | .addr({ sprite_y[5:0], sprite_x[5:0] }), 59 | .data_out(sprite_rgb)); 60 | 61 | assign color = (x > pos_x && x < pos_x + 64 && y > pos_y && y < pos_y + 64) ? sprite_rgb : 8'hff; 62 | 63 | reg [15:0] counter; 64 | 65 | always @(posedge clk) begin 66 | counter <= counter + 1; 67 | end 68 | 69 | always @(posedge counter[15]) 70 | begin 71 | if (btn[5]==1'b1) 72 | pos_x <= (pos_x > 0) ? pos_x - 1 : pos_x; 73 | if (btn[6]==1'b1) 74 | pos_x <= (pos_x < 32) ? pos_x +1 : pos_x; 75 | end 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /st7735/top_hex_demo.v: -------------------------------------------------------------------------------- 1 | module top_hex_demo 2 | ( 3 | input wire clk_25mhz, 4 | input wire [6:0] btn, 5 | output wire [7:0] led, 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn 11 | ); 12 | parameter C_color_bits = 16; 13 | 14 | assign led = 0; 15 | 16 | reg [127:0] R_display; // something to display 17 | always @(posedge clk_25mhz) 18 | begin 19 | R_display[0] <= btn[0]; 20 | R_display[4] <= btn[1]; 21 | R_display[8] <= btn[2]; 22 | R_display[12] <= btn[3]; 23 | R_display[16] <= btn[4]; 24 | R_display[20] <= btn[5]; 25 | R_display[24] <= btn[6]; 26 | R_display[127:64] <= R_display[127:64] + 1; // shown in next OLED row 27 | end 28 | 29 | wire [6:0] x; 30 | wire [7:0] y; 31 | wire next_pixel; 32 | wire [C_color_bits-1:0] color; 33 | 34 | hex_decoder 35 | #( 36 | .C_data_len(128), 37 | .C_font_file("oled_font.mem"), 38 | .C_color_bits(C_color_bits) 39 | ) 40 | hex_decoder_inst 41 | ( 42 | .clk(clk_25mhz), 43 | .en(1'b1), 44 | .data(R_display), 45 | .x(x), 46 | .y(y), 47 | .next_pixel(next_pixel), 48 | .color(color) 49 | ); 50 | 51 | localparam C_init_file = "st7735_init.mem"; 52 | 53 | oled_video 54 | #( 55 | .C_init_file(C_init_file), 56 | .C_init_size(110) 57 | ) 58 | oled_video_inst 59 | ( 60 | .clk(clk_25mhz), 61 | .x(x), 62 | .y(y), 63 | .next_pixel(next_pixel), 64 | .color(color), 65 | .oled_csn(oled_csn), 66 | .oled_clk(oled_clk), 67 | .oled_mosi(oled_mosi), 68 | .oled_dc(oled_dc), 69 | .oled_resn(oled_resn) 70 | ); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /st7789/top_hex_demo.v: -------------------------------------------------------------------------------- 1 | module top_hex_demo 2 | ( 3 | input wire clk_25mhz, 4 | input wire [6:0] btn, 5 | output wire [7:0] led, 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn 11 | ); 12 | parameter C_color_bits = 16; 13 | 14 | assign led = 0; 15 | 16 | reg [127:0] R_display; // something to display 17 | always @(posedge clk_25mhz) 18 | begin 19 | R_display[0] <= btn[0]; 20 | R_display[4] <= btn[1]; 21 | R_display[8] <= btn[2]; 22 | R_display[12] <= btn[3]; 23 | R_display[16] <= btn[4]; 24 | R_display[20] <= btn[5]; 25 | R_display[24] <= btn[6]; 26 | R_display[127:64] <= R_display[127:64] + 1; // shown in next OLED row 27 | end 28 | 29 | wire [6:0] x; 30 | wire [7:0] y; 31 | wire next_pixel; 32 | wire [C_color_bits-1:0] color; 33 | 34 | hex_decoder 35 | #( 36 | .C_data_len(128), 37 | .C_font_file("oled_font.mem"), 38 | .C_color_bits(C_color_bits) 39 | ) 40 | hex_decoder_inst 41 | ( 42 | .clk(clk_25mhz), 43 | .en(1'b1), 44 | .data(R_display), 45 | .x(x), 46 | .y(y), 47 | .next_pixel(next_pixel), 48 | .color(color) 49 | ); 50 | 51 | localparam C_init_file = "st7789_init.mem"; 52 | 53 | oled_video 54 | #( 55 | .C_init_file(C_init_file), 56 | .C_init_size(36) 57 | ) 58 | oled_video_inst 59 | ( 60 | .clk(clk_25mhz), 61 | .x(x), 62 | .y(y), 63 | .next_pixel(next_pixel), 64 | .color(color), 65 | .oled_csn(oled_csn), 66 | .oled_clk(oled_clk), 67 | .oled_mosi(oled_mosi), 68 | .oled_dc(oled_dc), 69 | .oled_resn(oled_resn) 70 | ); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /ps2/ps2_test.v: -------------------------------------------------------------------------------- 1 | module ps2_test ( 2 | input clk_25mhz, 3 | input ps2_clk, 4 | input ps2_data, 5 | output ftdi_rxd, 6 | output [3:0] led, 7 | output usb_fpga_pu_dp, 8 | output usb_fpga_pu_dn 9 | ); 10 | 11 | assign usb_fpga_pu_dp = 1; 12 | assign usb_fpga_pu_dn = 1; 13 | 14 | wire reset_n = &reset_counter; 15 | reg [9:0] reset_counter = 0; 16 | 17 | // reset_n will be held low for 1ms, then stay high 18 | always @(posedge clk_25mhz) 19 | begin 20 | if (!reset_n) 21 | begin 22 | reset_counter = reset_counter + 1; 23 | end 24 | end 25 | 26 | // =============================================================== 27 | // PS/2 keyboard interface 28 | // =============================================================== 29 | 30 | wire [7:0] keyb_data; 31 | wire keyb_valid; 32 | wire keyb_error; 33 | 34 | ps2_intf ps2 35 | ( 36 | .CLK (clk_25mhz), 37 | .nRESET (reset_n), 38 | .PS2_CLK (ps2_clk), 39 | .PS2_DATA (ps2_data), 40 | .DATA (keyb_data), 41 | .VALID (keyb_valid), 42 | .ERROR (keyb_error) 43 | ); 44 | 45 | assign led = {keyb_valid, keyb_error, keyb_data[1:0]}; 46 | 47 | wire [7:0] hex1, hex2; // Ascii hex chars to print 48 | 49 | // Convert ascii code tp hex 50 | byte_to_hex h1(keyb_data[3:0], hex1); 51 | byte_to_hex h2(keyb_data[7:4], hex2); 52 | 53 | // Send the key to the UART 54 | wire [15:0] text = {hex2, hex1}; 55 | reg text_req, text_done; 56 | 57 | debug #(.text_len(2)) db ( 58 | .clk(clk_25mhz), 59 | .reset(~reset_n), 60 | .text_req(text_req), 61 | .text_done(text_done), 62 | .debug_text(text), 63 | .uart_tx(ftdi_rxd)); 64 | 65 | always @(posedge clk_25mhz) begin 66 | if (text_done) text_req = 1'b0; 67 | if (keyb_valid) text_req = 1'b1; 68 | end 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /protocols/echo/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_tx ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | input data_we, 29 | input [7:0] data, 30 | output data_wait 31 | ); 32 | reg [9:0] send_pattern; 33 | reg [3:0] send_bitcnt; 34 | reg [31:0] send_divcnt; 35 | 36 | assign data_wait = data_we && (send_bitcnt); 37 | 38 | assign ser_tx = send_pattern[0]; 39 | 40 | always @(posedge clk) begin 41 | send_divcnt <= send_divcnt + 1; 42 | if (!resetn) begin 43 | send_pattern <= ~0; 44 | send_bitcnt <= 0; 45 | send_divcnt <= 0; 46 | end else begin 47 | if (data_we && !send_bitcnt) begin 48 | send_pattern <= {1'b1, data, 1'b0}; 49 | send_bitcnt <= 10; 50 | send_divcnt <= 0; 51 | end else 52 | if (send_divcnt > cfg_divider && send_bitcnt) begin 53 | send_pattern <= {1'b1, send_pattern[9:1]}; 54 | send_bitcnt <= send_bitcnt - 1; 55 | send_divcnt <= 0; 56 | end 57 | end 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /protocols/serialtx/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_tx ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | input data_we, 29 | input [7:0] data, 30 | output data_wait 31 | ); 32 | reg [9:0] send_pattern; 33 | reg [3:0] send_bitcnt; 34 | reg [31:0] send_divcnt; 35 | 36 | assign data_wait = data_we && (send_bitcnt); 37 | 38 | assign ser_tx = send_pattern[0]; 39 | 40 | always @(posedge clk) begin 41 | send_divcnt <= send_divcnt + 1; 42 | if (!resetn) begin 43 | send_pattern <= ~0; 44 | send_bitcnt <= 0; 45 | send_divcnt <= 0; 46 | end else begin 47 | if (data_we && !send_bitcnt) begin 48 | send_pattern <= {1'b1, data, 1'b0}; 49 | send_bitcnt <= 10; 50 | send_divcnt <= 0; 51 | end else 52 | if (send_divcnt > cfg_divider && send_bitcnt) begin 53 | send_pattern <= {1'b1, send_pattern[9:1]}; 54 | send_bitcnt <= send_bitcnt - 1; 55 | send_divcnt <= 0; 56 | end 57 | end 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /protocols/spidisplay/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_tx ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | input data_we, 29 | input [7:0] data, 30 | output data_wait 31 | ); 32 | reg [9:0] send_pattern; 33 | reg [3:0] send_bitcnt; 34 | reg [31:0] send_divcnt; 35 | 36 | assign data_wait = data_we && (send_bitcnt); 37 | 38 | assign ser_tx = send_pattern[0]; 39 | 40 | always @(posedge clk) begin 41 | send_divcnt <= send_divcnt + 1; 42 | if (!resetn) begin 43 | send_pattern <= ~0; 44 | send_bitcnt <= 0; 45 | send_divcnt <= 0; 46 | end else begin 47 | if (data_we && !send_bitcnt) begin 48 | send_pattern <= {1'b1, data, 1'b0}; 49 | send_bitcnt <= 10; 50 | send_divcnt <= 0; 51 | end else 52 | if (send_divcnt > cfg_divider && send_bitcnt) begin 53 | send_pattern <= {1'b1, send_pattern[9:1]}; 54 | send_bitcnt <= send_bitcnt - 1; 55 | send_divcnt <= 0; 56 | end 57 | end 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /usbemard/ssd1331_linit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | // init for SSD1331 OLED and lcd_video.v 2 | // This file must be in the directory from where 3 | // the verilog compiler is running. 4 | // The path to this file is not relative to the 5 | // verilog source that needs to include this file. 6 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 7 | // 90 bytes follow: 8 | // after reset, delay 2^10 us = 1ms before sending commands 9 | 80 10 | 0A 11 | // NOP 12 | BC 13 | 00 14 | // Set display off 15 | AE 16 | 00 17 | // Set data format 18 | // A0 20 normal 8bpp 19 | // A0 60 normal 16bpp 20 | // A0 22 X-flip 8bpp 21 | // A0 62 X-flip 16bpp 22 | // A0 32 Y-flip 8bpp 23 | A0 24 | 00 25 | 62 26 | 00 27 | // Set display start line 28 | A1 29 | 00 30 | 00 31 | 00 32 | // Set display offset 33 | A2 34 | 00 35 | 00 36 | 00 37 | // Set display mode normal 38 | A4 39 | 00 40 | // Set multiplex ratio 41 | A8 42 | 00 43 | 3F 44 | 00 45 | // Set master configuration 46 | AD 47 | 00 48 | 8E 49 | 00 50 | // Set power save mode 51 | B0 52 | 00 53 | 00 54 | 00 55 | // Phase 1/2 period adjustment 56 | B1 57 | 00 58 | 74 59 | 00 60 | // Set display clock divider 61 | B3 62 | 00 63 | F0 64 | 00 65 | // Set precharge A 66 | 8A 67 | 00 68 | 64 69 | 00 70 | // Set precharge B 71 | 8B 72 | 00 73 | 78 74 | 00 75 | // Set precharge C 76 | 8C 77 | 00 78 | 64 79 | 00 80 | // Set precharge voltage 81 | BB 82 | 00 83 | 31 84 | 00 85 | // Set contrast A 86 | 81 87 | 00 88 | FF 89 | 00 90 | // Set contrast B 91 | 82 92 | 00 93 | FF 94 | 00 95 | // Set contrast C 96 | 83 97 | 00 98 | FF 99 | 00 100 | // Set Vcomh voltage 101 | BE 102 | 00 103 | 3E 104 | 00 105 | // Master current control 106 | 87 107 | 00 108 | 06 109 | 00 110 | // Set column address 111 | 15 112 | 00 113 | 00 114 | 00 115 | 5F 116 | 00 117 | // Set row address 118 | 75 119 | 00 120 | 00 121 | 00 122 | 3F 123 | 00 124 | // Set display on 125 | AF 126 | 00 127 | -------------------------------------------------------------------------------- /usbhost/ssd1331_linit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | // init for SSD1331 OLED and lcd_video.v 2 | // This file must be in the directory from where 3 | // the verilog compiler is running. 4 | // The path to this file is not relative to the 5 | // verilog source that needs to include this file. 6 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 7 | // 90 bytes follow: 8 | // after reset, delay 2^10 us = 1ms before sending commands 9 | 80 10 | 0A 11 | // NOP 12 | BC 13 | 00 14 | // Set display off 15 | AE 16 | 00 17 | // Set data format 18 | // A0 20 normal 8bpp 19 | // A0 60 normal 16bpp 20 | // A0 22 X-flip 8bpp 21 | // A0 62 X-flip 16bpp 22 | // A0 32 Y-flip 8bpp 23 | A0 24 | 00 25 | 62 26 | 00 27 | // Set display start line 28 | A1 29 | 00 30 | 00 31 | 00 32 | // Set display offset 33 | A2 34 | 00 35 | 00 36 | 00 37 | // Set display mode normal 38 | A4 39 | 00 40 | // Set multiplex ratio 41 | A8 42 | 00 43 | 3F 44 | 00 45 | // Set master configuration 46 | AD 47 | 00 48 | 8E 49 | 00 50 | // Set power save mode 51 | B0 52 | 00 53 | 00 54 | 00 55 | // Phase 1/2 period adjustment 56 | B1 57 | 00 58 | 74 59 | 00 60 | // Set display clock divider 61 | B3 62 | 00 63 | F0 64 | 00 65 | // Set precharge A 66 | 8A 67 | 00 68 | 64 69 | 00 70 | // Set precharge B 71 | 8B 72 | 00 73 | 78 74 | 00 75 | // Set precharge C 76 | 8C 77 | 00 78 | 64 79 | 00 80 | // Set precharge voltage 81 | BB 82 | 00 83 | 31 84 | 00 85 | // Set contrast A 86 | 81 87 | 00 88 | FF 89 | 00 90 | // Set contrast B 91 | 82 92 | 00 93 | FF 94 | 00 95 | // Set contrast C 96 | 83 97 | 00 98 | FF 99 | 00 100 | // Set Vcomh voltage 101 | BE 102 | 00 103 | 3E 104 | 00 105 | // Master current control 106 | 87 107 | 00 108 | 06 109 | 00 110 | // Set column address 111 | 15 112 | 00 113 | 00 114 | 00 115 | 5F 116 | 00 117 | // Set row address 118 | 75 119 | 00 120 | 00 121 | 00 122 | 3F 123 | 00 124 | // Set display on 125 | AF 126 | 00 127 | -------------------------------------------------------------------------------- /usbhost/usbh_crc16.v: -------------------------------------------------------------------------------- 1 | module UsbCrc16 ( 2 | input [15:0] io_crc_i, 3 | input [7:0] io_data_i, 4 | output reg [15:0] io_crc_o); 5 | wire _zz_1_; 6 | wire _zz_2_; 7 | assign _zz_1_ = io_data_i[0]; 8 | assign _zz_2_ = io_data_i[1]; 9 | always @ (*) begin 10 | io_crc_o[15] = (((((((((((((((io_data_i[0] ^ io_data_i[1]) ^ io_data_i[2]) ^ io_data_i[3]) ^ io_data_i[4]) ^ io_data_i[5]) ^ io_data_i[6]) ^ io_data_i[7]) ^ io_crc_i[7]) ^ io_crc_i[6]) ^ io_crc_i[5]) ^ io_crc_i[4]) ^ io_crc_i[3]) ^ io_crc_i[2]) ^ io_crc_i[1]) ^ io_crc_i[0]); 11 | io_crc_o[14] = (((((((((((((io_data_i[0] ^ io_data_i[1]) ^ io_data_i[2]) ^ io_data_i[3]) ^ io_data_i[4]) ^ io_data_i[5]) ^ io_data_i[6]) ^ io_crc_i[6]) ^ io_crc_i[5]) ^ io_crc_i[4]) ^ io_crc_i[3]) ^ io_crc_i[2]) ^ io_crc_i[1]) ^ io_crc_i[0]); 12 | io_crc_o[13] = (((io_data_i[6] ^ io_data_i[7]) ^ io_crc_i[7]) ^ io_crc_i[6]); 13 | io_crc_o[12] = (((io_data_i[5] ^ io_data_i[6]) ^ io_crc_i[6]) ^ io_crc_i[5]); 14 | io_crc_o[11] = (((io_data_i[4] ^ io_data_i[5]) ^ io_crc_i[5]) ^ io_crc_i[4]); 15 | io_crc_o[10] = (((io_data_i[3] ^ io_data_i[4]) ^ io_crc_i[4]) ^ io_crc_i[3]); 16 | io_crc_o[9] = (((io_data_i[2] ^ io_data_i[3]) ^ io_crc_i[3]) ^ io_crc_i[2]); 17 | io_crc_o[8] = (((io_data_i[1] ^ io_data_i[2]) ^ io_crc_i[2]) ^ io_crc_i[1]); 18 | io_crc_o[7] = ((((io_data_i[0] ^ io_data_i[1]) ^ io_crc_i[15]) ^ io_crc_i[1]) ^ io_crc_i[0]); 19 | io_crc_o[6] = ((io_data_i[0] ^ io_crc_i[14]) ^ io_crc_i[0]); 20 | io_crc_o[5] = io_crc_i[13]; 21 | io_crc_o[4] = io_crc_i[12]; 22 | io_crc_o[3] = io_crc_i[11]; 23 | io_crc_o[2] = io_crc_i[10]; 24 | io_crc_o[1] = io_crc_i[9]; 25 | io_crc_o[0] = ((((((((((((((((_zz_1_ ^ _zz_2_) ^ io_data_i[2]) ^ io_data_i[3]) ^ io_data_i[4]) ^ io_data_i[5]) ^ io_data_i[6]) ^ io_data_i[7]) ^ io_crc_i[8]) ^ io_crc_i[7]) ^ io_crc_i[6]) ^ io_crc_i[5]) ^ io_crc_i[4]) ^ io_crc_i[3]) ^ io_crc_i[2]) ^ io_crc_i[1]) ^ io_crc_i[0]); 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /hdmi/menu/software/flash.c: -------------------------------------------------------------------------------- 1 | #include "flash.h" 2 | #include "delay.h" 3 | 4 | void flash_begin() { 5 | reg_flash_cs = 0; 6 | } 7 | 8 | void flash_end() { 9 | reg_flash_cs = 1; 10 | } 11 | 12 | uint8_t flash_xfer(uint8_t d) { 13 | reg_flash_xfer = d; 14 | return reg_flash_xfer; 15 | } 16 | 17 | void flash_write_enable() { 18 | flash_begin(); 19 | flash_xfer(0x06); 20 | flash_end(); 21 | } 22 | 23 | void flash_bulk_erase() { 24 | flash_begin(); 25 | flash_xfer(0xc7); 26 | flash_end(); 27 | } 28 | 29 | void flash_erase_64kB(uint32_t addr) { 30 | flash_begin(); 31 | flash_xfer(0xd8); 32 | flash_xfer(addr >> 16); 33 | flash_xfer(addr >> 8); 34 | flash_xfer(addr); 35 | flash_end(); 36 | } 37 | 38 | void flash_erase_32kB(uint32_t addr) { 39 | flash_begin(); 40 | flash_xfer(0x52); 41 | flash_xfer(addr >> 16); 42 | flash_xfer(addr >> 8); 43 | flash_xfer(addr); 44 | flash_end(); 45 | } 46 | 47 | void flash_write(uint32_t addr, uint8_t *data, int n) { 48 | flash_begin(); 49 | flash_xfer(0x02); 50 | flash_xfer(addr >> 16); 51 | flash_xfer(addr >> 8); 52 | flash_xfer(addr); 53 | while (n--) 54 | flash_xfer(*(data++)); 55 | flash_end(); 56 | } 57 | 58 | void flash_read(uint32_t addr, uint8_t *data, int n) { 59 | flash_begin(); 60 | flash_xfer(0x03); 61 | flash_xfer(addr >> 16); 62 | flash_xfer(addr >> 8); 63 | flash_xfer(addr); 64 | while (n--) 65 | *(data++) = flash_xfer(0); 66 | flash_end(); 67 | } 68 | 69 | void flash_wait() { 70 | while (1) 71 | { 72 | flash_begin(); 73 | flash_xfer(0x05); 74 | int status = flash_xfer(0); 75 | flash_end(); 76 | 77 | if ((status & 0x01) == 0) 78 | break; 79 | 80 | delay(1); 81 | } 82 | } 83 | 84 | -------------------------------------------------------------------------------- /ps2port/ps2_test.v: -------------------------------------------------------------------------------- 1 | module ps2_test ( 2 | input clk_25mhz, 3 | input ps2_clk, 4 | input ps2_data, 5 | output ftdi_rxd, 6 | output [3:0] led, 7 | output usb_fpga_pu_dp, 8 | output usb_fpga_pu_dn 9 | ); 10 | 11 | assign usb_fpga_pu_dp = 1; 12 | assign usb_fpga_pu_dn = 1; 13 | 14 | wire reset_n = &reset_counter; 15 | reg [9:0] reset_counter = 0; 16 | 17 | // reset_n will be held low for 1ms, then stay high 18 | always @(posedge clk_25mhz) 19 | begin 20 | if (!reset_n) 21 | begin 22 | reset_counter = reset_counter + 1; 23 | end 24 | end 25 | 26 | // =============================================================== 27 | // PS/2 keyboard interface 28 | // =============================================================== 29 | 30 | wire [7:0] keyb_data; 31 | wire keyb_valid; 32 | wire keyb_error; 33 | wire extended; 34 | wire released; 35 | 36 | ps2_port ps2 37 | ( 38 | .clk (clk_25mhz), 39 | .ps2clk_ext (ps2_clk), 40 | .ps2data_ext (ps2_data), 41 | .scancode (keyb_data), 42 | .enable_rcv(1), 43 | .kb_interrupt (keyb_valid), 44 | .extended(extended), 45 | .released(released) 46 | ); 47 | 48 | assign led = {keyb_valid, keyb_error, keyb_data[1:0]}; 49 | 50 | wire [7:0] hex1, hex2; // Ascii hex chars to print 51 | 52 | // Convert ascii code tp hex 53 | byte_to_hex h1(keyb_data[3:0], hex1); 54 | byte_to_hex h2(keyb_data[7:4], hex2); 55 | 56 | // Send the key to the UART 57 | wire [15:0] text = {hex2, hex1}; 58 | reg text_req, text_done; 59 | 60 | debug #(.text_len(2)) db ( 61 | .clk(clk_25mhz), 62 | .reset(~reset_n), 63 | .text_req(text_req), 64 | .text_done(text_done), 65 | .debug_text(text), 66 | .uart_tx(ftdi_rxd)); 67 | 68 | always @(posedge clk_25mhz) begin 69 | if (text_done) text_req = 1'b0; 70 | if (keyb_valid) text_req = 1'b1; 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /pong-hdmi/move/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | input [6:0] btn, 6 | output wifi_gpio0 7 | ); 8 | assign wifi_gpio0 = 1'b1; 9 | 10 | wire locked; 11 | wire [23:0] color; 12 | wire [9:0] x; 13 | wire [9:0] y; 14 | 15 | localparam SCREEN_WIDTH = 640; 16 | localparam SCREEN_HEIGHT = 480; 17 | localparam PADDLE_SIZE = 64; 18 | localparam PADDLE_WIDTH = 16; 19 | localparam NET_WIDTH = 8; 20 | 21 | reg [9:0] paddle1_y; 22 | reg [9:0] paddle2_y; 23 | 24 | assign color = 25 | (x > 0 && x < PADDLE_WIDTH && y > paddle1_y && y < paddle1_y + PADDLE_SIZE) ? 24'hffffff : 26 | (x > (SCREEN_WIDTH-PADDLE_WIDTH) && x < SCREEN_WIDTH && y > paddle2_y && y < paddle2_y + PADDLE_SIZE) ? 24'hffffff : 27 | (x > (SCREEN_WIDTH/2) - NET_WIDTH && x < (SCREEN_WIDTH/2) + NET_WIDTH && y[4]==0) ? 24'hffffff : 28 | 24'h000000; 29 | 30 | 31 | reg [31:0] cnt; 32 | always @(posedge clk_25mhz) 33 | begin 34 | cnt <= cnt + 1; 35 | end 36 | 37 | always @(posedge cnt[16]) 38 | begin 39 | if(!locked) 40 | begin 41 | paddle1_y <= (SCREEN_HEIGHT-PADDLE_SIZE)/2; 42 | paddle2_y <= (SCREEN_HEIGHT-PADDLE_SIZE)/2; 43 | end 44 | else 45 | begin 46 | if (btn[1]==1'b1) 47 | paddle1_y <= (paddle1_y > 0) ? paddle1_y - 1 : paddle1_y; 48 | if (btn[2]==1'b1) 49 | paddle1_y <= (paddle1_y < (SCREEN_HEIGHT-PADDLE_SIZE)) ? paddle1_y +1 : paddle1_y; 50 | if (btn[3]==1'b1) 51 | paddle2_y <= (paddle2_y > 0) ? paddle2_y - 1 : paddle2_y; 52 | if (btn[4]==1'b1) 53 | paddle2_y <= (paddle2_y < (SCREEN_HEIGHT-PADDLE_SIZE)) ? paddle2_y +1 : paddle2_y; 54 | end 55 | end 56 | 57 | 58 | hdmi_video hdmi_video 59 | ( 60 | .clk_25mhz(clk_25mhz), 61 | .x(x), 62 | .y(y), 63 | .color(color), 64 | .gpdi_dp(gpdi_dp), 65 | .gpdi_dn(gpdi_dn), 66 | .clk_locked(locked) 67 | ); 68 | endmodule 69 | -------------------------------------------------------------------------------- /st7735/oled_font.mem: -------------------------------------------------------------------------------- 1 | // This file must be in the directory from where 2 | // the verilog compiler is running. 3 | // The path to this file is not relative to the 4 | // verilog source that needs to include this file. 5 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 6 | // 136 words follow (each word is 5-bit) 7 | // 0 8 | 01110 9 | 10001 10 | 10011 11 | 10101 12 | 11001 13 | 10001 14 | 01110 15 | 00000 16 | // 1 17 | 00100 18 | 01100 19 | 00100 20 | 00100 21 | 00100 22 | 00100 23 | 01110 24 | 00000 25 | // 2 26 | 01110 27 | 10001 28 | 00001 29 | 00010 30 | 00100 31 | 01000 32 | 11111 33 | 00000 34 | // 3 35 | 01110 36 | 10001 37 | 00001 38 | 01110 39 | 00001 40 | 10001 41 | 01110 42 | 00000 43 | // 4 44 | 00010 45 | 00110 46 | 01010 47 | 10010 48 | 11111 49 | 00010 50 | 00010 51 | 00000 52 | // 5 53 | 11111 54 | 10000 55 | 11110 56 | 00001 57 | 00001 58 | 10001 59 | 01110 60 | 00000 61 | // 6 62 | 01111 63 | 10000 64 | 11110 65 | 10001 66 | 10001 67 | 10001 68 | 01110 69 | 00000 70 | // 7 71 | 11111 72 | 10001 73 | 00001 74 | 00010 75 | 00100 76 | 01000 77 | 01000 78 | 00000 79 | // 8 80 | 01110 81 | 10001 82 | 10001 83 | 01110 84 | 10001 85 | 10001 86 | 01110 87 | 00000 88 | // 9 89 | 01110 90 | 10001 91 | 10001 92 | 01111 93 | 00001 94 | 10001 95 | 01110 96 | 00000 97 | // 10: A 98 | 01110 99 | 10001 100 | 10001 101 | 11111 102 | 10001 103 | 10001 104 | 10001 105 | 00000 106 | // 11: B 107 | 11110 108 | 10001 109 | 10001 110 | 11110 111 | 10001 112 | 10001 113 | 11110 114 | 00000 115 | // 12: C 116 | 01110 117 | 10001 118 | 10000 119 | 10000 120 | 10000 121 | 10001 122 | 01110 123 | 00000 124 | // 13: D 125 | 11110 126 | 10001 127 | 10001 128 | 10001 129 | 10001 130 | 10001 131 | 11110 132 | 00000 133 | // 14: E 134 | 11111 135 | 10000 136 | 10000 137 | 11110 138 | 10000 139 | 10000 140 | 11111 141 | 00000 142 | // 15: F 143 | 11111 144 | 10000 145 | 10000 146 | 11110 147 | 10000 148 | 10000 149 | 10000 150 | 00000 151 | // 16: SPACE 152 | 00000 153 | 00000 154 | 00000 155 | 00000 156 | 00000 157 | 00000 158 | 00000 159 | 00000 160 | -------------------------------------------------------------------------------- /st7789/oled_font.mem: -------------------------------------------------------------------------------- 1 | // This file must be in the directory from where 2 | // the verilog compiler is running. 3 | // The path to this file is not relative to the 4 | // verilog source that needs to include this file. 5 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 6 | // 136 words follow (each word is 5-bit) 7 | // 0 8 | 01110 9 | 10001 10 | 10011 11 | 10101 12 | 11001 13 | 10001 14 | 01110 15 | 00000 16 | // 1 17 | 00100 18 | 01100 19 | 00100 20 | 00100 21 | 00100 22 | 00100 23 | 01110 24 | 00000 25 | // 2 26 | 01110 27 | 10001 28 | 00001 29 | 00010 30 | 00100 31 | 01000 32 | 11111 33 | 00000 34 | // 3 35 | 01110 36 | 10001 37 | 00001 38 | 01110 39 | 00001 40 | 10001 41 | 01110 42 | 00000 43 | // 4 44 | 00010 45 | 00110 46 | 01010 47 | 10010 48 | 11111 49 | 00010 50 | 00010 51 | 00000 52 | // 5 53 | 11111 54 | 10000 55 | 11110 56 | 00001 57 | 00001 58 | 10001 59 | 01110 60 | 00000 61 | // 6 62 | 01111 63 | 10000 64 | 11110 65 | 10001 66 | 10001 67 | 10001 68 | 01110 69 | 00000 70 | // 7 71 | 11111 72 | 10001 73 | 00001 74 | 00010 75 | 00100 76 | 01000 77 | 01000 78 | 00000 79 | // 8 80 | 01110 81 | 10001 82 | 10001 83 | 01110 84 | 10001 85 | 10001 86 | 01110 87 | 00000 88 | // 9 89 | 01110 90 | 10001 91 | 10001 92 | 01111 93 | 00001 94 | 10001 95 | 01110 96 | 00000 97 | // 10: A 98 | 01110 99 | 10001 100 | 10001 101 | 11111 102 | 10001 103 | 10001 104 | 10001 105 | 00000 106 | // 11: B 107 | 11110 108 | 10001 109 | 10001 110 | 11110 111 | 10001 112 | 10001 113 | 11110 114 | 00000 115 | // 12: C 116 | 01110 117 | 10001 118 | 10000 119 | 10000 120 | 10000 121 | 10001 122 | 01110 123 | 00000 124 | // 13: D 125 | 11110 126 | 10001 127 | 10001 128 | 10001 129 | 10001 130 | 10001 131 | 11110 132 | 00000 133 | // 14: E 134 | 11111 135 | 10000 136 | 10000 137 | 11110 138 | 10000 139 | 10000 140 | 11111 141 | 00000 142 | // 15: F 143 | 11111 144 | 10000 145 | 10000 146 | 11110 147 | 10000 148 | 10000 149 | 10000 150 | 00000 151 | // 16: SPACE 152 | 00000 153 | 00000 154 | 00000 155 | 00000 156 | 00000 157 | 00000 158 | 00000 159 | 00000 160 | -------------------------------------------------------------------------------- /usbemard/hex_font.mem: -------------------------------------------------------------------------------- 1 | // This file must be in the directory from where 2 | // the verilog compiler is running. 3 | // The path to this file is not relative to the 4 | // verilog source that needs to include this file. 5 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 6 | // 136 words follow (each word is 5-bit) 7 | // 0 8 | 01110 9 | 10001 10 | 10011 11 | 10101 12 | 11001 13 | 10001 14 | 01110 15 | 00000 16 | // 1 17 | 00100 18 | 01100 19 | 00100 20 | 00100 21 | 00100 22 | 00100 23 | 01110 24 | 00000 25 | // 2 26 | 01110 27 | 10001 28 | 00001 29 | 00010 30 | 00100 31 | 01000 32 | 11111 33 | 00000 34 | // 3 35 | 01110 36 | 10001 37 | 00001 38 | 01110 39 | 00001 40 | 10001 41 | 01110 42 | 00000 43 | // 4 44 | 00010 45 | 00110 46 | 01010 47 | 10010 48 | 11111 49 | 00010 50 | 00010 51 | 00000 52 | // 5 53 | 11111 54 | 10000 55 | 11110 56 | 00001 57 | 00001 58 | 10001 59 | 01110 60 | 00000 61 | // 6 62 | 00111 63 | 01000 64 | 10000 65 | 11110 66 | 10001 67 | 10001 68 | 01110 69 | 00000 70 | // 7 71 | 11111 72 | 00001 73 | 00010 74 | 00100 75 | 01000 76 | 01000 77 | 01000 78 | 00000 79 | // 8 80 | 01110 81 | 10001 82 | 10001 83 | 01110 84 | 10001 85 | 10001 86 | 01110 87 | 00000 88 | // 9 89 | 01110 90 | 10001 91 | 10001 92 | 01111 93 | 00001 94 | 10001 95 | 01110 96 | 00000 97 | // 10: A 98 | 01110 99 | 10001 100 | 10001 101 | 11111 102 | 10001 103 | 10001 104 | 10001 105 | 00000 106 | // 11: B 107 | 11110 108 | 10001 109 | 10001 110 | 11110 111 | 10001 112 | 10001 113 | 11110 114 | 00000 115 | // 12: C 116 | 01110 117 | 10001 118 | 10000 119 | 10000 120 | 10000 121 | 10001 122 | 01110 123 | 00000 124 | // 13: D 125 | 11110 126 | 10001 127 | 10001 128 | 10001 129 | 10001 130 | 10001 131 | 11110 132 | 00000 133 | // 14: E 134 | 11111 135 | 10000 136 | 10000 137 | 11110 138 | 10000 139 | 10000 140 | 11111 141 | 00000 142 | // 15: F 143 | 11111 144 | 10000 145 | 10000 146 | 11110 147 | 10000 148 | 10000 149 | 10000 150 | 00000 151 | // 16: SPACE 152 | 00000 153 | 00000 154 | 00000 155 | 00000 156 | 00000 157 | 00000 158 | 00000 159 | 00000 160 | -------------------------------------------------------------------------------- /usbhost/hex_font.mem: -------------------------------------------------------------------------------- 1 | // This file must be in the directory from where 2 | // the verilog compiler is running. 3 | // The path to this file is not relative to the 4 | // verilog source that needs to include this file. 5 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 6 | // 136 words follow (each word is 5-bit) 7 | // 0 8 | 01110 9 | 10001 10 | 10011 11 | 10101 12 | 11001 13 | 10001 14 | 01110 15 | 00000 16 | // 1 17 | 00100 18 | 01100 19 | 00100 20 | 00100 21 | 00100 22 | 00100 23 | 01110 24 | 00000 25 | // 2 26 | 01110 27 | 10001 28 | 00001 29 | 00010 30 | 00100 31 | 01000 32 | 11111 33 | 00000 34 | // 3 35 | 01110 36 | 10001 37 | 00001 38 | 01110 39 | 00001 40 | 10001 41 | 01110 42 | 00000 43 | // 4 44 | 00010 45 | 00110 46 | 01010 47 | 10010 48 | 11111 49 | 00010 50 | 00010 51 | 00000 52 | // 5 53 | 11111 54 | 10000 55 | 11110 56 | 00001 57 | 00001 58 | 10001 59 | 01110 60 | 00000 61 | // 6 62 | 00111 63 | 01000 64 | 10000 65 | 11110 66 | 10001 67 | 10001 68 | 01110 69 | 00000 70 | // 7 71 | 11111 72 | 00001 73 | 00010 74 | 00100 75 | 01000 76 | 01000 77 | 01000 78 | 00000 79 | // 8 80 | 01110 81 | 10001 82 | 10001 83 | 01110 84 | 10001 85 | 10001 86 | 01110 87 | 00000 88 | // 9 89 | 01110 90 | 10001 91 | 10001 92 | 01111 93 | 00001 94 | 10001 95 | 01110 96 | 00000 97 | // 10: A 98 | 01110 99 | 10001 100 | 10001 101 | 11111 102 | 10001 103 | 10001 104 | 10001 105 | 00000 106 | // 11: B 107 | 11110 108 | 10001 109 | 10001 110 | 11110 111 | 10001 112 | 10001 113 | 11110 114 | 00000 115 | // 12: C 116 | 01110 117 | 10001 118 | 10000 119 | 10000 120 | 10000 121 | 10001 122 | 01110 123 | 00000 124 | // 13: D 125 | 11110 126 | 10001 127 | 10001 128 | 10001 129 | 10001 130 | 10001 131 | 11110 132 | 00000 133 | // 14: E 134 | 11111 135 | 10000 136 | 10000 137 | 11110 138 | 10000 139 | 10000 140 | 11111 141 | 00000 142 | // 15: F 143 | 11111 144 | 10000 145 | 10000 146 | 11110 147 | 10000 148 | 10000 149 | 10000 150 | 00000 151 | // 16: SPACE 152 | 00000 153 | 00000 154 | 00000 155 | 00000 156 | 00000 157 | 00000 158 | 00000 159 | 00000 160 | -------------------------------------------------------------------------------- /sdram16/spi_display/hex_font.mem: -------------------------------------------------------------------------------- 1 | // This file must be in the directory from where 2 | // the verilog compiler is running. 3 | // The path to this file is not relative to the 4 | // verilog source that needs to include this file. 5 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 6 | // 136 words follow (each word is 5-bit) 7 | // 0 8 | 01110 9 | 10001 10 | 10011 11 | 10101 12 | 11001 13 | 10001 14 | 01110 15 | 00000 16 | // 1 17 | 00100 18 | 01100 19 | 00100 20 | 00100 21 | 00100 22 | 00100 23 | 01110 24 | 00000 25 | // 2 26 | 01110 27 | 10001 28 | 00001 29 | 00010 30 | 00100 31 | 01000 32 | 11111 33 | 00000 34 | // 3 35 | 01110 36 | 10001 37 | 00001 38 | 01110 39 | 00001 40 | 10001 41 | 01110 42 | 00000 43 | // 4 44 | 00010 45 | 00110 46 | 01010 47 | 10010 48 | 11111 49 | 00010 50 | 00010 51 | 00000 52 | // 5 53 | 11111 54 | 10000 55 | 11110 56 | 00001 57 | 00001 58 | 10001 59 | 01110 60 | 00000 61 | // 6 62 | 00111 63 | 01000 64 | 10000 65 | 11110 66 | 10001 67 | 10001 68 | 01110 69 | 00000 70 | // 7 71 | 11111 72 | 00001 73 | 00010 74 | 00100 75 | 01000 76 | 01000 77 | 01000 78 | 00000 79 | // 8 80 | 01110 81 | 10001 82 | 10001 83 | 01110 84 | 10001 85 | 10001 86 | 01110 87 | 00000 88 | // 9 89 | 01110 90 | 10001 91 | 10001 92 | 01111 93 | 00001 94 | 10001 95 | 01110 96 | 00000 97 | // 10: A 98 | 01110 99 | 10001 100 | 10001 101 | 11111 102 | 10001 103 | 10001 104 | 10001 105 | 00000 106 | // 11: B 107 | 11110 108 | 10001 109 | 10001 110 | 11110 111 | 10001 112 | 10001 113 | 11110 114 | 00000 115 | // 12: C 116 | 01110 117 | 10001 118 | 10000 119 | 10000 120 | 10000 121 | 10001 122 | 01110 123 | 00000 124 | // 13: D 125 | 11110 126 | 10001 127 | 10001 128 | 10001 129 | 10001 130 | 10001 131 | 11110 132 | 00000 133 | // 14: E 134 | 11111 135 | 10000 136 | 10000 137 | 11110 138 | 10000 139 | 10000 140 | 11111 141 | 00000 142 | // 15: F 143 | 11111 144 | 10000 145 | 10000 146 | 11110 147 | 10000 148 | 10000 149 | 10000 150 | 00000 151 | // 16: SPACE 152 | 00000 153 | 00000 154 | 00000 155 | 00000 156 | 00000 157 | 00000 158 | 00000 159 | 00000 160 | -------------------------------------------------------------------------------- /ps2/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * uart_tx 3 | * 4 | * Copyright 2018 Tom Verbeure 5 | * 6 | * Copyright and related rights are licensed under the Solderpad Hardware License, 7 | * Version 0.51 (the “License”); you may not use this file except in compliance with 8 | * the License. 9 | * You may obtain a copy of the License at * http://solderpad.org/licenses/SHL-0.51. 10 | * Unless required by applicable law or agreed to in writing, software, hardware and 11 | * materials distributed under this License is distributed on an “AS IS” BASIS, WITHOUT 12 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and limitations under the License. 14 | * 15 | */ 16 | 17 | module uart_tx 18 | ( 19 | input clk, 20 | input reset, 21 | input tx_req, 22 | output tx_ready, 23 | input [7:0] tx_data, 24 | output uart_tx 25 | ); 26 | 27 | parameter MAIN_CLK = 26000000; 28 | parameter BAUD = 115200; 29 | 30 | localparam BAUD_DIVIDE = MAIN_CLK/BAUD; 31 | 32 | reg [$clog2(BAUD_DIVIDE)-1:0] baud_cntr; 33 | reg baud_tick; 34 | 35 | always @(posedge clk) begin 36 | baud_tick <= 1'b0; 37 | 38 | if (reset) begin 39 | baud_cntr <= 0; 40 | end 41 | else if (baud_cntr == 0) begin 42 | baud_cntr <= BAUD_DIVIDE-1; 43 | baud_tick <= 1'b1; 44 | end 45 | else begin 46 | baud_cntr <= baud_cntr - 1; 47 | end 48 | end 49 | 50 | reg uart_tx; 51 | reg tx_ready; 52 | 53 | reg [3:0] tx_bit_cntr; 54 | reg [8:0] tx_shift_reg; 55 | always @(posedge clk) begin 56 | tx_ready <= 1'b0; 57 | 58 | if (reset) begin 59 | tx_bit_cntr <= 0; 60 | uart_tx <= 1'b1; 61 | end 62 | else if (baud_tick) begin 63 | if (tx_bit_cntr == 0) begin 64 | if (tx_req) begin 65 | `ifndef SYNTHESIS 66 | $display("Send Character '%c'", tx_data); 67 | `endif 68 | tx_shift_reg <= { 1'b1, tx_data }; 69 | uart_tx <= 1'b0; // Start bit 70 | tx_bit_cntr <= 9; 71 | tx_ready <= 1'b1; 72 | end 73 | end 74 | else begin 75 | uart_tx <= tx_shift_reg[0]; 76 | tx_shift_reg <= { 1'b0, tx_shift_reg[8:1] }; 77 | tx_bit_cntr <= tx_bit_cntr - 1; 78 | end 79 | end 80 | end 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /ps2port/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * uart_tx 3 | * 4 | * Copyright 2018 Tom Verbeure 5 | * 6 | * Copyright and related rights are licensed under the Solderpad Hardware License, 7 | * Version 0.51 (the “License”); you may not use this file except in compliance with 8 | * the License. 9 | * You may obtain a copy of the License at * http://solderpad.org/licenses/SHL-0.51. 10 | * Unless required by applicable law or agreed to in writing, software, hardware and 11 | * materials distributed under this License is distributed on an “AS IS” BASIS, WITHOUT 12 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and limitations under the License. 14 | * 15 | */ 16 | 17 | module uart_tx 18 | ( 19 | input clk, 20 | input reset, 21 | input tx_req, 22 | output tx_ready, 23 | input [7:0] tx_data, 24 | output uart_tx 25 | ); 26 | 27 | parameter MAIN_CLK = 26000000; 28 | parameter BAUD = 115200; 29 | 30 | localparam BAUD_DIVIDE = MAIN_CLK/BAUD; 31 | 32 | reg [$clog2(BAUD_DIVIDE)-1:0] baud_cntr; 33 | reg baud_tick; 34 | 35 | always @(posedge clk) begin 36 | baud_tick <= 1'b0; 37 | 38 | if (reset) begin 39 | baud_cntr <= 0; 40 | end 41 | else if (baud_cntr == 0) begin 42 | baud_cntr <= BAUD_DIVIDE-1; 43 | baud_tick <= 1'b1; 44 | end 45 | else begin 46 | baud_cntr <= baud_cntr - 1; 47 | end 48 | end 49 | 50 | reg uart_tx; 51 | reg tx_ready; 52 | 53 | reg [3:0] tx_bit_cntr; 54 | reg [8:0] tx_shift_reg; 55 | always @(posedge clk) begin 56 | tx_ready <= 1'b0; 57 | 58 | if (reset) begin 59 | tx_bit_cntr <= 0; 60 | uart_tx <= 1'b1; 61 | end 62 | else if (baud_tick) begin 63 | if (tx_bit_cntr == 0) begin 64 | if (tx_req) begin 65 | `ifndef SYNTHESIS 66 | $display("Send Character '%c'", tx_data); 67 | `endif 68 | tx_shift_reg <= { 1'b1, tx_data }; 69 | uart_tx <= 1'b0; // Start bit 70 | tx_bit_cntr <= 9; 71 | tx_ready <= 1'b1; 72 | end 73 | end 74 | else begin 75 | uart_tx <= tx_shift_reg[0]; 76 | tx_shift_reg <= { 1'b0, tx_shift_reg[8:1] }; 77 | tx_bit_cntr <= tx_bit_cntr - 1; 78 | end 79 | end 80 | end 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /computer/turnmon.bin.mem: -------------------------------------------------------------------------------- 1 | 3e 2 | 03 3 | d3 4 | 10 5 | 3e 6 | 11 7 | d3 8 | 10 9 | 31 10 | 00 11 | fc 12 | cd 13 | 9d 14 | fd 15 | 3e 16 | 2e 17 | cd 18 | f2 19 | fd 20 | cd 21 | e8 22 | fd 23 | fe 24 | 4d 25 | ca 26 | 29 27 | fd 28 | fe 29 | 44 30 | cc 31 | 4f 32 | fd 33 | fe 34 | 4a 35 | c2 36 | 08 37 | fd 38 | cd 39 | a7 40 | fd 41 | e9 42 | cd 43 | a7 44 | fd 45 | 3e 46 | 23 47 | cd 48 | 9d 49 | fd 50 | 54 51 | 5d 52 | cd 53 | c9 54 | fd 55 | 1a 56 | 67 57 | cd 58 | cf 59 | fd 60 | cd 61 | a8 62 | fd 63 | eb 64 | da 65 | 2d 66 | fd 67 | 77 68 | be 69 | ca 70 | 2d 71 | fd 72 | 3e 73 | 3f 74 | cd 75 | f2 76 | fd 77 | c3 78 | 08 79 | fd 80 | cd 81 | a7 82 | fd 83 | eb 84 | d4 85 | e3 86 | fd 87 | cd 88 | a7 89 | fd 90 | 3e 91 | 0d 92 | 06 93 | 3c 94 | cd 95 | f2 96 | fd 97 | 05 98 | c2 99 | 5d 100 | fd 101 | b8 102 | 78 103 | c2 104 | 5b 105 | fd 106 | 7d 107 | 93 108 | 6f 109 | 7c 110 | 9a 111 | 67 112 | 23 113 | 05 114 | 7c 115 | b7 116 | c2 117 | 77 118 | fd 119 | 45 120 | 3e 121 | 3c 122 | cd 123 | f2 124 | fd 125 | 78 126 | cd 127 | f2 128 | fd 129 | 0e 130 | 00 131 | 7b 132 | cd 133 | f2 134 | fd 135 | 7a 136 | cd 137 | f2 138 | fd 139 | 1a 140 | cd 141 | f2 142 | fd 143 | 13 144 | 2b 145 | 05 146 | c2 147 | 8a 148 | fd 149 | 79 150 | cd 151 | f2 152 | fd 153 | 7c 154 | b5 155 | c2 156 | 70 157 | fd 158 | 3e 159 | 0d 160 | cd 161 | f2 162 | fd 163 | 3e 164 | 0a 165 | c3 166 | f2 167 | fd 168 | 06 169 | 06 170 | 03 171 | 21 172 | 00 173 | 00 174 | cd 175 | e8 176 | fd 177 | 4f 178 | fe 179 | 20 180 | 37 181 | c8 182 | e6 183 | b8 184 | ee 185 | 30 186 | c2 187 | 47 188 | fd 189 | 79 190 | e6 191 | 07 192 | 29 193 | 29 194 | 29 195 | 85 196 | 6f 197 | 05 198 | c2 199 | ad 200 | fd 201 | c9 202 | 06 203 | 06 204 | af 205 | c3 206 | d6 207 | fd 208 | 06 209 | 03 210 | e6 211 | 29 212 | 17 213 | 29 214 | 17 215 | 29 216 | 17 217 | e6 218 | 07 219 | f6 220 | 30 221 | cd 222 | f2 223 | fd 224 | 05 225 | c2 226 | d2 227 | fd 228 | 3e 229 | 20 230 | c3 231 | f2 232 | fd 233 | db 234 | 10 235 | 0f 236 | d2 237 | e8 238 | fd 239 | db 240 | 11 241 | e6 242 | 7f 243 | f5 244 | 81 245 | 4f 246 | db 247 | 10 248 | 0f 249 | 0f 250 | d2 251 | f5 252 | fd 253 | f1 254 | d3 255 | 11 256 | c9 257 | -------------------------------------------------------------------------------- /usbemard/clk_25_125_48_6_25.v: -------------------------------------------------------------------------------- 1 | // diamond 3.7 accepts this PLL 2 | // diamond 3.8-3.9 is untested 3 | // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal 4 | // cause of this could be from wrong CPHASE/FPHASE parameters 5 | module clk_25_125_48_6_25 6 | ( 7 | input clk25_i, // 25 MHz, 0 deg 8 | output clk125_o, // 125 MHz, 0 deg 9 | output clk48_o, // 48.0769 MHz, 0 deg 10 | output clk6_o, // 6.00962 MHz, 0 deg 11 | output clk25_o, // 25 MHz, 0 deg 12 | output locked 13 | ); 14 | (* FREQUENCY_PIN_CLKI="25" *) 15 | (* FREQUENCY_PIN_CLKOP="125" *) 16 | (* FREQUENCY_PIN_CLKOS="48.0769" *) 17 | (* FREQUENCY_PIN_CLKOS2="6.00962" *) 18 | (* FREQUENCY_PIN_CLKOS3="25" *) 19 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 20 | EHXPLLL #( 21 | .PLLRST_ENA("DISABLED"), 22 | .INTFB_WAKE("DISABLED"), 23 | .STDBY_ENABLE("DISABLED"), 24 | .DPHASE_SOURCE("DISABLED"), 25 | .OUTDIVIDER_MUXA("DIVA"), 26 | .OUTDIVIDER_MUXB("DIVB"), 27 | .OUTDIVIDER_MUXC("DIVC"), 28 | .OUTDIVIDER_MUXD("DIVD"), 29 | .CLKI_DIV(1), 30 | .CLKOP_ENABLE("ENABLED"), 31 | .CLKOP_DIV(5), 32 | .CLKOP_CPHASE(2), 33 | .CLKOP_FPHASE(0), 34 | .CLKOS_ENABLE("ENABLED"), 35 | .CLKOS_DIV(13), 36 | .CLKOS_CPHASE(2), 37 | .CLKOS_FPHASE(0), 38 | .CLKOS2_ENABLE("ENABLED"), 39 | .CLKOS2_DIV(104), 40 | .CLKOS2_CPHASE(2), 41 | .CLKOS2_FPHASE(0), 42 | .CLKOS3_ENABLE("ENABLED"), 43 | .CLKOS3_DIV(25), 44 | .CLKOS3_CPHASE(2), 45 | .CLKOS3_FPHASE(0), 46 | .FEEDBK_PATH("CLKOP"), 47 | .CLKFB_DIV(5) 48 | ) pll_i ( 49 | .RST(1'b0), 50 | .STDBY(1'b0), 51 | .CLKI(clk25_i), 52 | .CLKOP(clk125_o), 53 | .CLKOS(clk48_o), 54 | .CLKOS2(clk6_o), 55 | .CLKOS3(clk25_o), 56 | .CLKFB(clk125_o), 57 | .CLKINTFB(), 58 | .PHASESEL0(1'b0), 59 | .PHASESEL1(1'b0), 60 | .PHASEDIR(1'b1), 61 | .PHASESTEP(1'b1), 62 | .PHASELOADREG(1'b1), 63 | .PLLWAKESYNC(1'b0), 64 | .ENCLKOP(1'b0), 65 | .LOCK(locked) 66 | ); 67 | endmodule 68 | -------------------------------------------------------------------------------- /usbhost/clk_25_125_48_6_25.v: -------------------------------------------------------------------------------- 1 | // diamond 3.7 accepts this PLL 2 | // diamond 3.8-3.9 is untested 3 | // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal 4 | // cause of this could be from wrong CPHASE/FPHASE parameters 5 | module clk_25_125_48_6_25 6 | ( 7 | input clk25_i, // 25 MHz, 0 deg 8 | output clk125_o, // 125 MHz, 0 deg 9 | output clk48_o, // 48.0769 MHz, 0 deg 10 | output clk6_o, // 6.00962 MHz, 0 deg 11 | output clk25_o, // 25 MHz, 0 deg 12 | output locked 13 | ); 14 | (* FREQUENCY_PIN_CLKI="25" *) 15 | (* FREQUENCY_PIN_CLKOP="125" *) 16 | (* FREQUENCY_PIN_CLKOS="48.0769" *) 17 | (* FREQUENCY_PIN_CLKOS2="6.00962" *) 18 | (* FREQUENCY_PIN_CLKOS3="25" *) 19 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 20 | EHXPLLL #( 21 | .PLLRST_ENA("DISABLED"), 22 | .INTFB_WAKE("DISABLED"), 23 | .STDBY_ENABLE("DISABLED"), 24 | .DPHASE_SOURCE("DISABLED"), 25 | .OUTDIVIDER_MUXA("DIVA"), 26 | .OUTDIVIDER_MUXB("DIVB"), 27 | .OUTDIVIDER_MUXC("DIVC"), 28 | .OUTDIVIDER_MUXD("DIVD"), 29 | .CLKI_DIV(1), 30 | .CLKOP_ENABLE("ENABLED"), 31 | .CLKOP_DIV(5), 32 | .CLKOP_CPHASE(2), 33 | .CLKOP_FPHASE(0), 34 | .CLKOS_ENABLE("ENABLED"), 35 | .CLKOS_DIV(13), 36 | .CLKOS_CPHASE(2), 37 | .CLKOS_FPHASE(0), 38 | .CLKOS2_ENABLE("ENABLED"), 39 | .CLKOS2_DIV(104), 40 | .CLKOS2_CPHASE(2), 41 | .CLKOS2_FPHASE(0), 42 | .CLKOS3_ENABLE("ENABLED"), 43 | .CLKOS3_DIV(25), 44 | .CLKOS3_CPHASE(2), 45 | .CLKOS3_FPHASE(0), 46 | .FEEDBK_PATH("CLKOP"), 47 | .CLKFB_DIV(5) 48 | ) pll_i ( 49 | .RST(1'b0), 50 | .STDBY(1'b0), 51 | .CLKI(clk25_i), 52 | .CLKOP(clk125_o), 53 | .CLKOS(clk48_o), 54 | .CLKOS2(clk6_o), 55 | .CLKOS3(clk25_o), 56 | .CLKFB(clk125_o), 57 | .CLKINTFB(), 58 | .PHASESEL0(1'b0), 59 | .PHASESEL1(1'b0), 60 | .PHASEDIR(1'b1), 61 | .PHASESTEP(1'b1), 62 | .PHASELOADREG(1'b1), 63 | .PLLWAKESYNC(1'b0), 64 | .ENCLKOP(1'b0), 65 | .LOCK(locked) 66 | ); 67 | endmodule 68 | -------------------------------------------------------------------------------- /hdmi/terminal/uart_rx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_rx ( 21 | input clk, 22 | input resetn, 23 | 24 | input ser_rx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | output [7:0] data, 29 | output reg valid 30 | ); 31 | 32 | reg [3:0] recv_state; 33 | reg [31:0] recv_divcnt; 34 | reg [7:0] recv_pattern; 35 | reg [7:0] recv_buf_data; 36 | 37 | assign data = valid ? recv_buf_data : ~0; 38 | 39 | always @(posedge clk) begin 40 | if (!resetn) begin 41 | recv_state <= 0; 42 | recv_divcnt <= 0; 43 | recv_pattern <= 0; 44 | recv_buf_data <= 0; 45 | valid <= 0; 46 | end else begin 47 | recv_divcnt <= recv_divcnt + 1; 48 | 49 | valid <= 0; 50 | 51 | case (recv_state) 52 | 0: begin 53 | if (!ser_rx) 54 | recv_state <= 1; 55 | recv_divcnt <= 0; 56 | end 57 | 1: begin 58 | if (2*recv_divcnt > cfg_divider) begin 59 | recv_state <= 2; 60 | recv_divcnt <= 0; 61 | end 62 | end 63 | 10: begin 64 | if (recv_divcnt > cfg_divider) begin 65 | recv_buf_data <= recv_pattern; 66 | valid <= 1; 67 | recv_state <= 0; 68 | end 69 | end 70 | default: begin 71 | if (recv_divcnt > cfg_divider) begin 72 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 73 | recv_state <= recv_state + 1; 74 | recv_divcnt <= 0; 75 | end 76 | end 77 | endcase 78 | end 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /protocols/echo/uart_rx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_rx ( 21 | input clk, 22 | input resetn, 23 | 24 | input ser_rx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | output [7:0] data, 29 | output reg valid 30 | ); 31 | 32 | reg [3:0] recv_state; 33 | reg [31:0] recv_divcnt; 34 | reg [7:0] recv_pattern; 35 | reg [7:0] recv_buf_data; 36 | 37 | assign data = valid ? recv_buf_data : ~0; 38 | 39 | always @(posedge clk) begin 40 | if (!resetn) begin 41 | recv_state <= 0; 42 | recv_divcnt <= 0; 43 | recv_pattern <= 0; 44 | recv_buf_data <= 0; 45 | valid <= 0; 46 | end else begin 47 | recv_divcnt <= recv_divcnt + 1; 48 | 49 | valid <= 0; 50 | 51 | case (recv_state) 52 | 0: begin 53 | if (!ser_rx) 54 | recv_state <= 1; 55 | recv_divcnt <= 0; 56 | end 57 | 1: begin 58 | if (2*recv_divcnt > cfg_divider) begin 59 | recv_state <= 2; 60 | recv_divcnt <= 0; 61 | end 62 | end 63 | 10: begin 64 | if (recv_divcnt > cfg_divider) begin 65 | recv_buf_data <= recv_pattern; 66 | valid <= 1; 67 | recv_state <= 0; 68 | end 69 | end 70 | default: begin 71 | if (recv_divcnt > cfg_divider) begin 72 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 73 | recv_state <= recv_state + 1; 74 | recv_divcnt <= 0; 75 | end 76 | end 77 | endcase 78 | end 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /video/terminal/uart_rx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_rx ( 21 | input clk, 22 | input resetn, 23 | 24 | input ser_rx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | output [7:0] data, 29 | output reg valid 30 | ); 31 | 32 | reg [3:0] recv_state; 33 | reg [31:0] recv_divcnt; 34 | reg [7:0] recv_pattern; 35 | reg [7:0] recv_buf_data; 36 | 37 | assign data = valid ? recv_buf_data : ~0; 38 | 39 | always @(posedge clk) begin 40 | if (!resetn) begin 41 | recv_state <= 0; 42 | recv_divcnt <= 0; 43 | recv_pattern <= 0; 44 | recv_buf_data <= 0; 45 | valid <= 0; 46 | end else begin 47 | recv_divcnt <= recv_divcnt + 1; 48 | 49 | valid <= 0; 50 | 51 | case (recv_state) 52 | 0: begin 53 | if (!ser_rx) 54 | recv_state <= 1; 55 | recv_divcnt <= 0; 56 | end 57 | 1: begin 58 | if (2*recv_divcnt > cfg_divider) begin 59 | recv_state <= 2; 60 | recv_divcnt <= 0; 61 | end 62 | end 63 | 10: begin 64 | if (recv_divcnt > cfg_divider) begin 65 | recv_buf_data <= recv_pattern; 66 | valid <= 1; 67 | recv_state <= 0; 68 | end 69 | end 70 | default: begin 71 | if (recv_divcnt > cfg_divider) begin 72 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 73 | recv_state <= recv_state + 1; 74 | recv_divcnt <= 0; 75 | end 76 | end 77 | endcase 78 | end 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /protocols/spidisplay/uart_rx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_rx ( 21 | input clk, 22 | input resetn, 23 | 24 | input ser_rx, 25 | 26 | input [31:0] cfg_divider, 27 | 28 | output [7:0] data, 29 | output reg valid 30 | ); 31 | 32 | reg [3:0] recv_state; 33 | reg [31:0] recv_divcnt; 34 | reg [7:0] recv_pattern; 35 | reg [7:0] recv_buf_data; 36 | 37 | assign data = valid ? recv_buf_data : ~0; 38 | 39 | always @(posedge clk) begin 40 | if (!resetn) begin 41 | recv_state <= 0; 42 | recv_divcnt <= 0; 43 | recv_pattern <= 0; 44 | recv_buf_data <= 0; 45 | valid <= 0; 46 | end else begin 47 | recv_divcnt <= recv_divcnt + 1; 48 | 49 | valid <= 0; 50 | 51 | case (recv_state) 52 | 0: begin 53 | if (!ser_rx) 54 | recv_state <= 1; 55 | recv_divcnt <= 0; 56 | end 57 | 1: begin 58 | if (2*recv_divcnt > cfg_divider) begin 59 | recv_state <= 2; 60 | recv_divcnt <= 0; 61 | end 62 | end 63 | 10: begin 64 | if (recv_divcnt > cfg_divider) begin 65 | recv_buf_data <= recv_pattern; 66 | valid <= 1; 67 | recv_state <= 0; 68 | end 69 | end 70 | default: begin 71 | if (recv_divcnt > cfg_divider) begin 72 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 73 | recv_state <= recv_state + 1; 74 | recv_divcnt <= 0; 75 | end 76 | end 77 | endcase 78 | end 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /cpu/alu.v: -------------------------------------------------------------------------------- 1 | module alu( 2 | input clk, 3 | input [7:0] A, 4 | input [7:0] B, 5 | input [3:0] operation, 6 | output reg [7:0] result, 7 | output reg CF, 8 | output reg ZF, 9 | output reg SF 10 | ); 11 | 12 | localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000; 13 | localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001; 14 | localparam ALU_OP_ADC /* verilator public_flat */ = 4'b0010; 15 | localparam ALU_OP_SBC /* verilator public_flat */ = 4'b0011; 16 | 17 | localparam ALU_OP_AND /* verilator public_flat */ = 4'b0100; 18 | localparam ALU_OP_OR /* verilator public_flat */ = 4'b0101; 19 | localparam ALU_OP_NOT /* verilator public_flat */ = 4'b0110; 20 | localparam ALU_OP_XOR /* verilator public_flat */ = 4'b0111; 21 | 22 | localparam ALU_OP_SHL /* verilator public_flat */ = 4'b1000; 23 | localparam ALU_OP_SHR /* verilator public_flat */ = 4'b1001; 24 | localparam ALU_OP_SAL /* verilator public_flat */ = 4'b1010; 25 | localparam ALU_OP_SAR /* verilator public_flat */ = 4'b1011; 26 | 27 | localparam ALU_OP_ROL /* verilator public_flat */ = 4'b1100; 28 | localparam ALU_OP_ROR /* verilator public_flat */ = 4'b1101; 29 | localparam ALU_OP_RCL /* verilator public_flat */ = 4'b1110; 30 | localparam ALU_OP_RCR /* verilator public_flat */ = 4'b1111; 31 | 32 | reg [8:0] tmp; 33 | 34 | always @(posedge clk) 35 | begin 36 | case (operation) 37 | ALU_OP_ADD : 38 | tmp = A + B; 39 | ALU_OP_SUB : 40 | tmp = A - B; 41 | ALU_OP_ADC : 42 | tmp = A + B + { 7'b0000000, CF }; 43 | ALU_OP_SBC : 44 | tmp = A - B - { 7'b0000000, CF }; 45 | ALU_OP_AND : 46 | tmp = {1'b0, A & B }; 47 | ALU_OP_OR : 48 | tmp = {1'b0, A | B }; 49 | ALU_OP_NOT : 50 | tmp = {1'b0, ~B }; 51 | ALU_OP_XOR : 52 | tmp = {1'b0, A ^ B}; 53 | ALU_OP_SHL : 54 | tmp = { A[7], A[6:0], 1'b0}; 55 | ALU_OP_SHR : 56 | tmp = { A[0], 1'b0, A[7:1]}; 57 | ALU_OP_SAL : 58 | // Same as SHL 59 | tmp = { A[7], A[6:0], 1'b0}; 60 | ALU_OP_SAR : 61 | tmp = { A[0], A[7], A[7:1]}; 62 | ALU_OP_ROL : 63 | tmp = { A[7], A[6:0], A[7]}; 64 | ALU_OP_ROR : 65 | tmp = { A[0], A[0], A[7:1]}; 66 | ALU_OP_RCL : 67 | tmp = { A[7], A[6:0], CF}; 68 | ALU_OP_RCR : 69 | tmp = { A[0], CF, A[7:1]}; 70 | endcase 71 | 72 | CF <= tmp[8]; 73 | ZF <= tmp[7:0] == 0; 74 | SF <= tmp[7]; 75 | 76 | result <= tmp[7:0]; 77 | end 78 | endmodule 79 | 80 | -------------------------------------------------------------------------------- /pong/move/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | input [6:0] btn, 12 | output wifi_gpio0 13 | ); 14 | assign wifi_gpio0 = 1'b1; 15 | 16 | wire clk; 17 | wire locked; 18 | pll pll( 19 | .clki(clk_25mhz), 20 | .clko(clk), 21 | .locked(locked) 22 | ); 23 | 24 | wire [7:0] x; 25 | wire [5:0] y; 26 | wire [7:0] color; 27 | 28 | spi_video video( 29 | .clk(clk), 30 | .oled_csn(oled_csn), 31 | .oled_clk(oled_clk), 32 | .oled_mosi(oled_mosi), 33 | .oled_dc(oled_dc), 34 | .oled_resn(oled_resn), 35 | .x(x), 36 | .y(y), 37 | .color(color) 38 | ); 39 | 40 | localparam SCREEN_WIDTH = 96; 41 | localparam SCREEN_HEIGHT = 64; 42 | localparam PADDLE_SIZE = 16; 43 | localparam PADDLE_WIDTH = 4; 44 | localparam NET_WIDTH = 2; 45 | 46 | reg [5:0] paddle1_y; 47 | reg [5:0] paddle2_y; 48 | 49 | assign color = 50 | (x > 0 && x < PADDLE_WIDTH && y > paddle1_y && y < paddle1_y + PADDLE_SIZE) ? 8'hff : 51 | (x > (SCREEN_WIDTH-PADDLE_WIDTH) && x < SCREEN_WIDTH && y > paddle2_y && y < paddle2_y + PADDLE_SIZE) ? 8'hff : 52 | (x > (SCREEN_WIDTH/2) - NET_WIDTH && x < (SCREEN_WIDTH/2) + NET_WIDTH && y[2]==0) ? 8'hff : 53 | 8'h00; 54 | 55 | 56 | reg [31:0] cnt; 57 | always @(posedge clk) 58 | begin 59 | cnt <= cnt + 1; 60 | end 61 | 62 | always @(posedge cnt[16]) 63 | begin 64 | if(!locked) 65 | begin 66 | paddle1_y <= (SCREEN_HEIGHT-PADDLE_SIZE)/2; 67 | paddle2_y <= (SCREEN_HEIGHT-PADDLE_SIZE)/2; 68 | end 69 | else 70 | begin 71 | if (btn[1]==1'b1) 72 | paddle1_y <= (paddle1_y > 0) ? paddle1_y - 1 : paddle1_y; 73 | if (btn[2]==1'b1) 74 | paddle1_y <= (paddle1_y < (SCREEN_HEIGHT-PADDLE_SIZE)) ? paddle1_y +1 : paddle1_y; 75 | if (btn[3]==1'b1) 76 | paddle2_y <= (paddle2_y > 0) ? paddle2_y - 1 : paddle2_y; 77 | if (btn[4]==1'b1) 78 | paddle2_y <= (paddle2_y < (SCREEN_HEIGHT-PADDLE_SIZE)) ? paddle2_y +1 : paddle2_y; 79 | end 80 | end 81 | endmodule 82 | -------------------------------------------------------------------------------- /ps2send/ps2_send.v: -------------------------------------------------------------------------------- 1 | module ps2_send ( 2 | input clk_25mhz, 3 | output reg ps2_data, 4 | output reg ps2_clk = 1, 5 | input req, 6 | output reg busy, 7 | input [7:0] data, 8 | input extended, 9 | input shift, 10 | output reg [7:0] led 11 | ); 12 | 13 | reg [3:0] bit_count = 0; 14 | reg [10:0] prescaler = 0; 15 | reg parity = 0; 16 | reg [2:0] byte_count = 0; 17 | reg [11:0] delay = 0; 18 | 19 | wire [7:0] break_code = 8'hf0; 20 | wire [7:0] extend_code = 8'he0; 21 | wire [7:0] shift_code = 8'h12; 22 | 23 | wire data_bit = data[bit_count]; 24 | wire break_bit = break_code[bit_count]; 25 | wire extend_bit = extend_code[bit_count]; 26 | wire shift_bit = shift_code[bit_count]; 27 | 28 | wire send_bit = (shift ? ((byte_count == 0 || byte_count == 5) ? shift_bit 29 | : ((byte_count == 2 || byte_count == 4) ? break_bit : data_bit)) : 30 | (extended ? (byte_count == 3 ? break_bit : 31 | ((byte_count == 0 || byte_count == 2) ? extend_bit : data_bit)) 32 | : (byte_count == 1 ? break_bit : data_bit))); 33 | 34 | always @(posedge clk_25mhz) begin 35 | if (req) begin 36 | ps2_data <= 0; // Start bit 37 | busy <= 1; 38 | prescaler <= 0; 39 | end 40 | 41 | if (busy) begin 42 | prescaler <= prescaler + 1; 43 | 44 | if (prescaler == 1023) begin 45 | prescaler <= 0; 46 | if (delay > 0) delay <= delay - 1; 47 | else begin 48 | ps2_clk <= ~ps2_clk; 49 | 50 | if (!ps2_clk) begin // Rising edge 51 | bit_count <= bit_count + 1; 52 | 53 | if (bit_count < 8) begin 54 | ps2_data <= send_bit; 55 | parity = parity ^ send_bit; 56 | if (byte_count == 0) led[bit_count] <= send_bit; 57 | end else if (bit_count == 8) begin 58 | ps2_data <= ~parity; 59 | end else if (bit_count == 9) begin 60 | ps2_data <= 1; // Stop bit 61 | end else begin // End of byte 62 | bit_count <= 0; 63 | parity <= 0; 64 | if (byte_count < 2 + extended + extended + shift + shift + shift) begin // More bytes 65 | byte_count <= byte_count + 1; 66 | if (byte_count == 1 + shift + extended) delay <= 12'h3ff; 67 | ps2_data <= 0; // Start bit 68 | end else begin 69 | busy <= 0; 70 | byte_count <= 0; 71 | end 72 | end 73 | end 74 | end 75 | end 76 | end 77 | end 78 | 79 | endmodule 80 | 81 | -------------------------------------------------------------------------------- /oled/oled_video.v: -------------------------------------------------------------------------------- 1 | // SPI OLED SSD1331 display video XY scan core 2 | // AUTHORS=EMARD,MMICKO 3 | // LICENSE=BSD 4 | 5 | module oled_video #( 6 | // file name is relative to directory path in which verilog compiler is running 7 | // screen can be also XY flipped and/or rotated from this init file 8 | parameter C_init_file = "oled_init_16bit.mem", 9 | parameter C_init_size = 0, // bytes in init file 10 | ) ( 11 | input wire clk, // SPI display clock rate will be half of this clock rate 12 | 13 | output reg [C_x_bits-1:0] x, 14 | output reg [C_y_bits-1:0] y, 15 | output reg next_pixel, // 1 when x/y changes 16 | input wire [C_color_bits-1:0] color, 17 | 18 | output wire oled_csn, 19 | output wire oled_clk, 20 | output wire oled_mosi, 21 | output wire oled_dc, 22 | output wire oled_resn 23 | ); 24 | localparam C_color_bits = 16; 25 | localparam C_x_size = 96; // pixel X screen size 26 | localparam C_y_size = 64; // pixel Y screen size 27 | localparam C_x_bits = $clog2(C_x_size); 28 | localparam C_y_bits = $clog2(C_y_size); 29 | 30 | reg [7:0] C_oled_init[0:C_init_size-1]; 31 | initial begin 32 | $readmemh(C_init_file, C_oled_init); 33 | end 34 | 35 | reg [1:0] reset_cnt; 36 | reg [9:0] init_cnt; 37 | reg [7:0] data; 38 | reg dc; 39 | reg byte; // alternates data byte for 16-bit mode 40 | 41 | assign oled_resn = ~reset_cnt[0]; 42 | assign oled_csn = reset_cnt[0]; 43 | assign oled_dc = dc; 44 | assign oled_clk = ~init_cnt[0]; 45 | assign oled_mosi = data[7]; 46 | 47 | always @(posedge clk) begin 48 | if (reset_cnt != 2) begin 49 | reset_cnt <= reset_cnt+1; 50 | data <= C_oled_init[0]; 51 | end else if (init_cnt[9:4] != C_init_size) begin 52 | init_cnt <= init_cnt + 1; 53 | if (init_cnt[3:0] == 0) begin 54 | if (dc == 0) data <= C_oled_init[init_cnt[9:4]]; 55 | else begin 56 | byte <= ~byte; 57 | data <= byte ? color[7:0] : color[15:8]; 58 | if(byte == 0) begin 59 | next_pixel <= 1; 60 | if (x == C_x_size-1) begin 61 | x <= 0; 62 | y <= y + 1; 63 | end else x <= x + 1; 64 | end 65 | end 66 | end else begin 67 | next_pixel <= 0; 68 | if (init_cnt[0] == 0) data <= { data[6:0], 1'b0 }; 69 | end 70 | end else begin 71 | dc <= 1; 72 | init_cnt[9:4] <= C_init_size - 1; 73 | end 74 | end 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /pong/game/numbers.list: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11000011 3 | 11000011 4 | 11000011 5 | 11000011 6 | 11000011 7 | 11000011 8 | 11111111 9 | 10 | 00000011 11 | 00000011 12 | 00000011 13 | 00000011 14 | 00000011 15 | 00000011 16 | 00000011 17 | 00000000 18 | 19 | 11111111 20 | 00000011 21 | 00000011 22 | 11111111 23 | 11000000 24 | 11000000 25 | 11111111 26 | 00000000 27 | 28 | 11111111 29 | 00000011 30 | 00000011 31 | 11111111 32 | 00000011 33 | 00000011 34 | 11111111 35 | 00000000 36 | 37 | 11000011 38 | 11000011 39 | 11000011 40 | 11111111 41 | 00000011 42 | 00000011 43 | 00000011 44 | 00000000 45 | 46 | 11111111 47 | 11000000 48 | 11000000 49 | 11111111 50 | 00000011 51 | 00000011 52 | 11111111 53 | 00000000 54 | 55 | 11111111 56 | 11000000 57 | 11000000 58 | 11111111 59 | 11000011 60 | 11000011 61 | 11111111 62 | 00000000 63 | 64 | 11111111 65 | 11111111 66 | 00000011 67 | 00000011 68 | 00000011 69 | 00000011 70 | 00000011 71 | 00000000 72 | 73 | 11111111 74 | 11000011 75 | 11000011 76 | 11111111 77 | 11000011 78 | 11000011 79 | 11111111 80 | 00000000 81 | 82 | 11111111 83 | 11000011 84 | 11000011 85 | 11111111 86 | 00000011 87 | 00000011 88 | 11111111 89 | 00000000 90 | 91 | //////// 92 | 93 | 00111100 94 | 01000010 95 | 01000010 96 | 01000010 97 | 01000010 98 | 01000010 99 | 01000010 100 | 00111100 101 | 102 | 00111100 103 | 01000010 104 | 01000010 105 | 01000010 106 | 01000010 107 | 01000010 108 | 01000010 109 | 00111100 110 | 111 | 00001000 112 | 00011000 113 | 00101000 114 | 00001000 115 | 00001000 116 | 00001000 117 | 00001000 118 | 01111110 119 | 120 | 00111000 121 | 01000100 122 | 00000100 123 | 00000100 124 | 00111000 125 | 01000000 126 | 01000000 127 | 01111100 128 | 129 | 00011110 130 | 00100010 131 | 00000010 132 | 00001100 133 | 00000010 134 | 00000010 135 | 00100010 136 | 00011100 137 | 138 | 01000000 139 | 01000000 140 | 01000000 141 | 01001000 142 | 01001000 143 | 01111110 144 | 00001000 145 | 00001000 146 | 147 | 01111100 148 | 01000000 149 | 01000000 150 | 01111000 151 | 00000100 152 | 00000100 153 | 00000100 154 | 01111000 155 | 156 | 00111100 157 | 01000000 158 | 10000000 159 | 10111000 160 | 11000100 161 | 10000100 162 | 10000100 163 | 01111000 164 | 165 | 01111110 166 | 00000010 167 | 00000100 168 | 00001000 169 | 00010000 170 | 00010000 171 | 00100000 172 | 00100000 173 | 174 | 00111100 175 | 01000010 176 | 01000010 177 | 00111100 178 | 01000010 179 | 01000010 180 | 01000010 181 | 00111100 182 | 183 | 00111100 184 | 01000010 185 | 01000010 186 | 01000110 187 | 00111010 188 | 00000010 189 | 00000010 190 | 00000010 191 | 192 | 193 | 194 | -------------------------------------------------------------------------------- /pong-hdmi/game/numbers.list: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11000011 3 | 11000011 4 | 11000011 5 | 11000011 6 | 11000011 7 | 11000011 8 | 11111111 9 | 10 | 00000011 11 | 00000011 12 | 00000011 13 | 00000011 14 | 00000011 15 | 00000011 16 | 00000011 17 | 00000000 18 | 19 | 11111111 20 | 00000011 21 | 00000011 22 | 11111111 23 | 11000000 24 | 11000000 25 | 11111111 26 | 00000000 27 | 28 | 11111111 29 | 00000011 30 | 00000011 31 | 11111111 32 | 00000011 33 | 00000011 34 | 11111111 35 | 00000000 36 | 37 | 11000011 38 | 11000011 39 | 11000011 40 | 11111111 41 | 00000011 42 | 00000011 43 | 00000011 44 | 00000000 45 | 46 | 11111111 47 | 11000000 48 | 11000000 49 | 11111111 50 | 00000011 51 | 00000011 52 | 11111111 53 | 00000000 54 | 55 | 11111111 56 | 11000000 57 | 11000000 58 | 11111111 59 | 11000011 60 | 11000011 61 | 11111111 62 | 00000000 63 | 64 | 11111111 65 | 11111111 66 | 00000011 67 | 00000011 68 | 00000011 69 | 00000011 70 | 00000011 71 | 00000000 72 | 73 | 11111111 74 | 11000011 75 | 11000011 76 | 11111111 77 | 11000011 78 | 11000011 79 | 11111111 80 | 00000000 81 | 82 | 11111111 83 | 11000011 84 | 11000011 85 | 11111111 86 | 00000011 87 | 00000011 88 | 11111111 89 | 00000000 90 | 91 | //////// 92 | 93 | 00111100 94 | 01000010 95 | 01000010 96 | 01000010 97 | 01000010 98 | 01000010 99 | 01000010 100 | 00111100 101 | 102 | 00111100 103 | 01000010 104 | 01000010 105 | 01000010 106 | 01000010 107 | 01000010 108 | 01000010 109 | 00111100 110 | 111 | 00001000 112 | 00011000 113 | 00101000 114 | 00001000 115 | 00001000 116 | 00001000 117 | 00001000 118 | 01111110 119 | 120 | 00111000 121 | 01000100 122 | 00000100 123 | 00000100 124 | 00111000 125 | 01000000 126 | 01000000 127 | 01111100 128 | 129 | 00011110 130 | 00100010 131 | 00000010 132 | 00001100 133 | 00000010 134 | 00000010 135 | 00100010 136 | 00011100 137 | 138 | 01000000 139 | 01000000 140 | 01000000 141 | 01001000 142 | 01001000 143 | 01111110 144 | 00001000 145 | 00001000 146 | 147 | 01111100 148 | 01000000 149 | 01000000 150 | 01111000 151 | 00000100 152 | 00000100 153 | 00000100 154 | 01111000 155 | 156 | 00111100 157 | 01000000 158 | 10000000 159 | 10111000 160 | 11000100 161 | 10000100 162 | 10000100 163 | 01111000 164 | 165 | 01111110 166 | 00000010 167 | 00000100 168 | 00001000 169 | 00010000 170 | 00010000 171 | 00100000 172 | 00100000 173 | 174 | 00111100 175 | 01000010 176 | 01000010 177 | 00111100 178 | 01000010 179 | 01000010 180 | 01000010 181 | 00111100 182 | 183 | 00111100 184 | 01000010 185 | 01000010 186 | 01000110 187 | 00111010 188 | 00000010 189 | 00000010 190 | 00000010 191 | 192 | 193 | 194 | -------------------------------------------------------------------------------- /hdmi/menu/spi_master.v: -------------------------------------------------------------------------------- 1 | module spi_master #( 2 | parameter integer CLOCK_FREQ_HZ = 0, 3 | parameter integer CS_LENGTH = 32 4 | ) ( 5 | input clk, 6 | input resetn, 7 | 8 | input ctrl_wr, 9 | input ctrl_rd, 10 | input [ 7:0] ctrl_addr, 11 | input [31:0] ctrl_wdat, 12 | output reg [31:0] ctrl_rdat, 13 | output reg ctrl_done, 14 | 15 | inout [CS_LENGTH-1:0] CS, 16 | inout mosi, miso, sclk 17 | ); 18 | wire spi_miso; 19 | reg spi_mosi, spi_sclk; 20 | reg [CS_LENGTH-1:0] spi_cs; 21 | 22 | reg mode_cpol; 23 | reg mode_cpha; 24 | 25 | reg [7:0] prescale_cnt; 26 | reg [7:0] prescale_cfg; 27 | reg [7:0] spi_data; 28 | reg [4:0] spi_state; 29 | 30 | assign spi_miso = miso; 31 | 32 | assign mosi = spi_mosi; 33 | 34 | assign sclk = spi_sclk ^ ~mode_cpol; 35 | 36 | assign CS = spi_cs; 37 | 38 | always @(posedge clk) begin 39 | ctrl_rdat <= 'bx; 40 | ctrl_done <= 0; 41 | if (!resetn) begin 42 | spi_mosi <= 0; 43 | spi_sclk <= 1; 44 | spi_cs <= ~0; 45 | 46 | mode_cpol <= 1; 47 | mode_cpha <= 1; 48 | prescale_cnt <= 0; 49 | prescale_cfg <= 0; 50 | spi_state <= 0; 51 | end else 52 | if (!ctrl_done) begin 53 | if (ctrl_wr) begin 54 | ctrl_done <= 1; 55 | if (ctrl_addr == 'h00) prescale_cfg <= ctrl_wdat; 56 | if (ctrl_addr == 'h04) begin 57 | spi_cs <= ctrl_wdat; 58 | ctrl_done <= prescale_cnt == prescale_cfg; 59 | prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1; 60 | end 61 | if (ctrl_addr == 'h08) begin 62 | if (!prescale_cnt) begin 63 | if (spi_state == 0) begin 64 | spi_data <= ctrl_wdat; 65 | spi_mosi <= ctrl_wdat[7]; 66 | end else begin 67 | if (spi_state[0]) 68 | spi_data <= {spi_data, spi_miso}; 69 | else if (spi_state < 16) 70 | spi_mosi <= spi_data[7]; 71 | end 72 | end 73 | spi_sclk <= spi_state[0] ^ ~mode_cpha; 74 | ctrl_done <= spi_state == (mode_cpha ? 15 : 16) && prescale_cnt == prescale_cfg; 75 | spi_state <= prescale_cnt == prescale_cfg ? (spi_state[4] ? 0 : spi_state + 1) : spi_state; 76 | if (mode_cpha) spi_state[4] <= 0; 77 | prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1; 78 | end 79 | if (ctrl_addr == 'h0c) begin 80 | {mode_cpol, mode_cpha} <= ctrl_wdat; 81 | ctrl_done <= prescale_cnt == prescale_cfg; 82 | prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1; 83 | end 84 | end 85 | if (ctrl_rd) begin 86 | ctrl_done <= 1; 87 | if (ctrl_addr == 'h00) ctrl_rdat <= prescale_cfg; 88 | if (ctrl_addr == 'h04) ctrl_rdat <= spi_cs; 89 | if (ctrl_addr == 'h08) ctrl_rdat <= spi_data; 90 | if (ctrl_addr == 'h0c) ctrl_rdat <= {mode_cpol, mode_cpha}; 91 | end 92 | end 93 | end 94 | endmodule 95 | 96 | -------------------------------------------------------------------------------- /hdmi/terminal/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk_25mhz, 4 | output [3:0] gpdi_dp, gpdi_dn, 5 | output wifi_gpio0, 6 | input wire ftdi_txd 7 | ); 8 | assign wifi_gpio0 = 1'b1; 9 | 10 | wire [23:0] color; 11 | wire [9:0] x; 12 | wire [9:0] y; 13 | 14 | reg [7:0] mem [0:2400]; 15 | 16 | integer k; 17 | 18 | initial 19 | begin 20 | for (k = 0; k < 2400; k = k + 1) 21 | mem[k] <= 32; 22 | end 23 | 24 | 25 | wire rx_valid; 26 | wire locked; 27 | 28 | wire [7:0] uart_out; 29 | 30 | uart_rx uart( 31 | .clk(clk_25mhz), 32 | .resetn(locked), 33 | 34 | .ser_rx(ftdi_txd), 35 | 36 | .cfg_divider(25000000/115200), 37 | 38 | .data(uart_out), 39 | .valid(rx_valid) 40 | ); 41 | 42 | wire [11:0] pos; 43 | reg [6:0] p_x; 44 | reg [4:0] p_y; 45 | 46 | reg valid; 47 | reg [7:0] display_char; 48 | reg [7:0] display_data; 49 | 50 | assign pos = p_x + p_y*80; 51 | always @(posedge clk_25mhz) begin 52 | if (valid) begin 53 | mem[pos] <= display_char; 54 | end 55 | display_data <= mem[(y >> 4) * 80 + (x>>3)]; 56 | end 57 | 58 | 59 | reg state; 60 | 61 | always @(posedge clk_25mhz) 62 | begin 63 | if (!locked) 64 | begin 65 | state <= 0; 66 | p_x <= 0; 67 | p_y <= 0; 68 | valid <= 0; 69 | end 70 | else 71 | begin 72 | case (state) 73 | 0: begin // receiving char 74 | if (rx_valid) 75 | begin 76 | valid <= 1; 77 | display_char <= uart_out; 78 | state <= 1; 79 | end 80 | end 81 | 1: begin // display char 82 | if (p_x < 79) 83 | p_x <= p_x + 1; 84 | else 85 | begin 86 | if (p_y < 29) 87 | p_y <= p_y + 1; 88 | else 89 | p_y <= 0; 90 | p_x <= 0; 91 | end 92 | valid <= 0; 93 | state <= 0; 94 | end 95 | endcase 96 | end 97 | end 98 | 99 | wire [7:0] data_out; 100 | 101 | font_rom vga_font( 102 | .clk(clk_25mhz), 103 | .addr({display_data, y[3:0] }), 104 | .data_out(data_out) 105 | ); 106 | 107 | assign color = data_out[7-x[2:0]+1] ? 24'hffffff : 24'h000000; // +1 for sync 108 | 109 | hdmi_video hdmi_video 110 | ( 111 | .clk_25mhz(clk_25mhz), 112 | .x(x), 113 | .y(y), 114 | .color(color), 115 | .gpdi_dp(gpdi_dp), 116 | .gpdi_dn(gpdi_dn), 117 | .clk_locked(locked) 118 | ); 119 | endmodule 120 | -------------------------------------------------------------------------------- /usbemard/usbh_crc5.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------- 2 | // USB Full Speed Host 3 | // V0.5 4 | // Ultra-Embedded.com 5 | // Copyright 2015-2019 6 | // 7 | // Email: admin@ultra-embedded.com 8 | // 9 | // License: GPL 10 | // If you would like a version with a more permissive license for 11 | // use in closed source commercial applications please contact me 12 | // for details. 13 | //----------------------------------------------------------------- 14 | // 15 | // This file is open source HDL; you can redistribute it and/or 16 | // modify it under the terms of the GNU General Public License as 17 | // published by the Free Software Foundation; either version 2 of 18 | // the License, or (at your option) any later version. 19 | // 20 | // This file is distributed in the hope that it will be useful, 21 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 22 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 | // GNU General Public License for more details. 24 | // 25 | // You should have received a copy of the GNU General Public 26 | // License along with this file; if not, write to the Free Software 27 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 28 | // USA 29 | //----------------------------------------------------------------- 30 | 31 | //----------------------------------------------------------------- 32 | // Generated File 33 | //----------------------------------------------------------------- 34 | //----------------------------------------------------------------- 35 | // Module: 5-bit CRC used by USB tokens 36 | //----------------------------------------------------------------- 37 | module usbh_crc5 38 | ( 39 | input [4:0] crc_i, 40 | input [10:0] data_i, 41 | output [4:0] crc_o 42 | ); 43 | 44 | //----------------------------------------------------------------- 45 | // Implementation 46 | //----------------------------------------------------------------- 47 | assign crc_o[0] = data_i[10] ^ data_i[9] ^ data_i[6] ^ data_i[5] ^ data_i[3] ^ data_i[0] ^ 48 | crc_i[0] ^ crc_i[3] ^ crc_i[4]; 49 | 50 | assign crc_o[1] = data_i[10] ^ data_i[7] ^ data_i[6] ^ data_i[4] ^ data_i[1] ^ 51 | crc_i[0] ^ crc_i[1] ^ crc_i[4]; 52 | 53 | assign crc_o[2] = data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[7] ^ data_i[6] ^ data_i[3] ^ data_i[2] ^ data_i[0] ^ 54 | crc_i[0] ^ crc_i[1] ^ crc_i[2] ^ crc_i[3] ^ crc_i[4]; 55 | 56 | assign crc_o[3] = data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[7] ^ data_i[4] ^ data_i[3] ^ data_i[1] ^ 57 | crc_i[1] ^ crc_i[2] ^ crc_i[3] ^ crc_i[4]; 58 | 59 | assign crc_o[4] = data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[5] ^ data_i[4] ^ data_i[2] ^ 60 | crc_i[2] ^ crc_i[3] ^ crc_i[4]; 61 | 62 | endmodule 63 | 64 | -------------------------------------------------------------------------------- /usbhost/usb_phy.v: -------------------------------------------------------------------------------- 1 | module UsbPhy ( 2 | input io_phyTxMode, 3 | output io_usbRst, 4 | input io_rxd, 5 | input io_rxdp, 6 | input io_rxdn, 7 | output io_txdp, 8 | output io_txdn, 9 | output io_txoe, 10 | output io_ceO, 11 | input io_lineCtrlI, 12 | input [7:0] io_dataOutI, 13 | input io_txValidI, 14 | output io_txReadyO, 15 | output [7:0] io_dataInO, 16 | output io_rxValidO, 17 | output io_rxActiveO, 18 | output io_rxErrorO, 19 | output [1:0] io_lineStateO, 20 | input clkout2, 21 | input reset); 22 | wire [1:0] usbRxPhy_1__io_lineState; 23 | wire usbRxPhy_1__io_clkRecovered; 24 | wire usbRxPhy_1__io_clkRecoveredEdge; 25 | wire usbRxPhy_1__io_rawData; 26 | wire usbRxPhy_1__io_rxActive; 27 | wire usbRxPhy_1__io_rxError; 28 | wire usbRxPhy_1__io_valid; 29 | wire [7:0] usbRxPhy_1__io_data; 30 | wire usbTxPhy_1__io_txdp; 31 | wire usbTxPhy_1__io_txdn; 32 | wire usbTxPhy_1__io_txoe; 33 | wire usbTxPhy_1__io_txReadyO; 34 | reg [4:0] rRstCnt; 35 | wire rUsbRstOut; 36 | wire sTxoe; 37 | UsbRxPhy usbRxPhy_1_ ( 38 | .io_usbDif(io_rxd), 39 | .io_usbDp(io_rxdp), 40 | .io_usbDn(io_rxdn), 41 | .io_lineState(usbRxPhy_1__io_lineState), 42 | .io_clkRecovered(usbRxPhy_1__io_clkRecovered), 43 | .io_clkRecoveredEdge(usbRxPhy_1__io_clkRecoveredEdge), 44 | .io_rawData(usbRxPhy_1__io_rawData), 45 | .io_rxEn(sTxoe), 46 | .io_rxActive(usbRxPhy_1__io_rxActive), 47 | .io_rxError(usbRxPhy_1__io_rxError), 48 | .io_valid(usbRxPhy_1__io_valid), 49 | .io_data(usbRxPhy_1__io_data), 50 | .clkout2(clkout2), 51 | .reset(reset) 52 | ); 53 | UsbTxPhy usbTxPhy_1_ ( 54 | .io_fsCe(usbRxPhy_1__io_clkRecoveredEdge), 55 | .io_phyMode(io_phyTxMode), 56 | .io_txdp(usbTxPhy_1__io_txdp), 57 | .io_txdn(usbTxPhy_1__io_txdn), 58 | .io_txoe(usbTxPhy_1__io_txoe), 59 | .io_lineCtrlI(io_lineCtrlI), 60 | .io_dataOutI(io_dataOutI), 61 | .io_txValidI(io_txValidI), 62 | .io_txReadyO(usbTxPhy_1__io_txReadyO), 63 | .clkout2(clkout2), 64 | .reset(reset) 65 | ); 66 | assign rUsbRstOut = 1'b0; 67 | assign sTxoe = usbTxPhy_1__io_txoe; 68 | assign io_usbRst = (rRstCnt == (5'b11111)); 69 | assign io_rxErrorO = 1'b0; 70 | assign io_ceO = usbRxPhy_1__io_clkRecoveredEdge; 71 | assign io_txdp = usbTxPhy_1__io_txdp; 72 | assign io_txdn = usbTxPhy_1__io_txdn; 73 | assign io_txoe = usbTxPhy_1__io_txoe; 74 | assign io_txReadyO = usbTxPhy_1__io_txReadyO; 75 | assign io_dataInO = usbRxPhy_1__io_data; 76 | assign io_lineStateO = usbRxPhy_1__io_lineState; 77 | assign io_rxValidO = usbRxPhy_1__io_valid; 78 | assign io_rxActiveO = usbRxPhy_1__io_rxActive; 79 | always @ (posedge clkout2 or posedge reset) begin 80 | if (reset) begin 81 | rRstCnt <= (5'b00000); 82 | end else begin 83 | if((usbRxPhy_1__io_lineState != (2'b00)))begin 84 | rRstCnt <= (5'b00000); 85 | end else begin 86 | rRstCnt <= (rRstCnt + (5'b00001)); 87 | end 88 | end 89 | end 90 | 91 | endmodule 92 | 93 | -------------------------------------------------------------------------------- /video/terminal/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input wire clk_25mhz, 5 | 6 | output wire oled_csn, 7 | output wire oled_clk, 8 | output wire oled_mosi, 9 | output wire oled_dc, 10 | output wire oled_resn, 11 | output wifi_gpio0, 12 | input wire ftdi_txd 13 | ); 14 | assign wifi_gpio0 = 1'b1; 15 | 16 | wire clk; 17 | wire locked; 18 | pll pll( 19 | .clki(clk_25mhz), 20 | .clko(clk), 21 | .locked(locked) 22 | ); 23 | 24 | wire [7:0] x; 25 | wire [5:0] y; 26 | wire [7:0] color; 27 | 28 | spi_video video( 29 | .clk(clk), 30 | .oled_csn(oled_csn), 31 | .oled_clk(oled_clk), 32 | .oled_mosi(oled_mosi), 33 | .oled_dc(oled_dc), 34 | .oled_resn(oled_resn), 35 | .x(x), 36 | .y(y), 37 | .color(color) 38 | ); 39 | 40 | reg [7:0] mem [0:47]; 41 | 42 | integer k; 43 | 44 | initial 45 | begin 46 | for (k = 0; k < 48; k = k + 1) 47 | mem[k] <= 32; 48 | end 49 | 50 | wire rx_valid; 51 | wire [7:0] uart_out; 52 | 53 | uart_rx uart( 54 | .clk(clk), 55 | .resetn(locked), 56 | 57 | .ser_rx(ftdi_txd), 58 | 59 | .cfg_divider(12500000/115200), 60 | 61 | .data(uart_out), 62 | .valid(rx_valid) 63 | ); 64 | 65 | wire [5:0] pos; 66 | reg [3:0] p_x; 67 | reg [1:0] p_y; 68 | 69 | reg valid; 70 | reg [7:0] display_char; 71 | 72 | assign pos = p_x + p_y*12; 73 | always @(posedge clk) begin 74 | if (valid) begin 75 | mem[pos] <= display_char; 76 | 77 | end 78 | end 79 | 80 | 81 | reg state; 82 | 83 | always @(posedge clk) 84 | begin 85 | if (!locked) 86 | begin 87 | state <= 0; 88 | p_x <= 0; 89 | p_y <= 0; 90 | valid <= 0; 91 | end 92 | else 93 | begin 94 | case (state) 95 | 0: begin // receiving char 96 | if (rx_valid) 97 | begin 98 | valid <= 1; 99 | display_char <= uart_out; 100 | state <= 1; 101 | end 102 | end 103 | 1: begin // display char 104 | if (p_x < 11) 105 | p_x <= p_x + 1; 106 | else 107 | begin 108 | p_y <= p_y + 1; 109 | p_x <= 0; 110 | end 111 | valid <= 0; 112 | state <= 0; 113 | end 114 | endcase 115 | end 116 | end 117 | 118 | wire [7:0] data_out; 119 | 120 | font_rom vga_font( 121 | .clk(clk), 122 | .addr({ mem[(y >> 4) * 12 + (x>>3)], y[3:0] }), 123 | .data_out(data_out) 124 | ); 125 | 126 | assign color = data_out[7-x[2:0]+1] ? 8'hff : 8'h00; // +1 for sync 127 | 128 | endmodule 129 | --------------------------------------------------------------------------------