├── .gitignore ├── .mxproject ├── Core ├── Inc │ ├── gpio.h │ ├── main.h │ ├── quadspi.h │ ├── stm32h7xx_hal_conf.h │ ├── stm32h7xx_it.h │ ├── usart.h │ └── w25qxx.h └── Src │ ├── gpio.c │ ├── main.c │ ├── quadspi.c │ ├── stm32h7xx_hal_msp.c │ ├── stm32h7xx_it.c │ ├── system_stm32h7xx.c │ ├── usart.c │ └── w25qxx.c ├── Dev_Inf.c ├── Dev_Inf.h ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32H7xx │ │ │ ├── Include │ │ │ ├── stm32h750xx.h │ │ │ ├── stm32h7xx.h │ │ │ └── system_stm32h7xx.h │ │ │ └── LICENSE.txt │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_armclang_ltm.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv81mml.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm35p.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── LICENSE.txt └── STM32H7xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32h7xx_hal.h │ ├── stm32h7xx_hal_cortex.h │ ├── stm32h7xx_hal_def.h │ ├── stm32h7xx_hal_dma.h │ ├── stm32h7xx_hal_dma_ex.h │ ├── stm32h7xx_hal_exti.h │ ├── stm32h7xx_hal_flash.h │ ├── stm32h7xx_hal_flash_ex.h │ ├── stm32h7xx_hal_gpio.h │ ├── stm32h7xx_hal_gpio_ex.h │ ├── stm32h7xx_hal_hsem.h │ ├── stm32h7xx_hal_i2c.h │ ├── stm32h7xx_hal_i2c_ex.h │ ├── stm32h7xx_hal_mdma.h │ ├── stm32h7xx_hal_pwr.h │ ├── stm32h7xx_hal_pwr_ex.h │ ├── stm32h7xx_hal_qspi.h │ ├── stm32h7xx_hal_rcc.h │ ├── stm32h7xx_hal_rcc_ex.h │ ├── stm32h7xx_hal_tim.h │ ├── stm32h7xx_hal_tim_ex.h │ ├── stm32h7xx_hal_uart.h │ ├── stm32h7xx_hal_uart_ex.h │ ├── stm32h7xx_hal_usart.h │ ├── stm32h7xx_hal_usart_ex.h │ ├── stm32h7xx_ll_bus.h │ ├── stm32h7xx_ll_cortex.h │ ├── stm32h7xx_ll_crs.h │ ├── stm32h7xx_ll_dma.h │ ├── stm32h7xx_ll_dmamux.h │ ├── stm32h7xx_ll_exti.h │ ├── stm32h7xx_ll_gpio.h │ ├── stm32h7xx_ll_hsem.h │ ├── stm32h7xx_ll_pwr.h │ ├── stm32h7xx_ll_rcc.h │ ├── stm32h7xx_ll_system.h │ └── stm32h7xx_ll_utils.h │ ├── LICENSE.txt │ └── Src │ ├── stm32h7xx_hal.c │ ├── stm32h7xx_hal_cortex.c │ ├── stm32h7xx_hal_dma.c │ ├── stm32h7xx_hal_dma_ex.c │ ├── stm32h7xx_hal_exti.c │ ├── stm32h7xx_hal_flash.c │ ├── stm32h7xx_hal_flash_ex.c │ ├── stm32h7xx_hal_gpio.c │ ├── stm32h7xx_hal_hsem.c │ ├── stm32h7xx_hal_i2c.c │ ├── stm32h7xx_hal_i2c_ex.c │ ├── stm32h7xx_hal_mdma.c │ ├── stm32h7xx_hal_pwr.c │ ├── stm32h7xx_hal_pwr_ex.c │ ├── stm32h7xx_hal_qspi.c │ ├── stm32h7xx_hal_rcc.c │ ├── stm32h7xx_hal_rcc_ex.c │ ├── stm32h7xx_hal_tim.c │ ├── stm32h7xx_hal_tim_ex.c │ ├── stm32h7xx_hal_uart.c │ ├── stm32h7xx_hal_uart_ex.c │ ├── stm32h7xx_hal_usart.c │ └── stm32h7xx_hal_usart_ex.c ├── Loader_Src.c ├── MDK-ARM ├── RTE │ ├── _STM32H750XBH_ARTPIQSPI_W25Q64JV │ │ └── RTE_Components.h │ └── _flashalgo │ │ └── RTE_Components.h ├── STM32H750XBH_ARTPIQSPI_W25Q64JV.uvoptx ├── STM32H750XBH_ARTPIQSPI_W25Q64JV.uvprojx └── startup_stm32h750xx.s ├── README.assets ├── image-20230601115223608.png ├── image-20230601115440178.png ├── image-20230601115533935.png ├── image-20230601115618557.png ├── image-20230601115823597.png ├── image-20230601115857964.png ├── image-20230601120011779.png ├── image-20230601120129867.png ├── image-20230601120333767.png ├── image-20230601120341498.png ├── image-20230601120511564.png ├── image-20230601121518862.png └── image-20230601121558481.png ├── README.md ├── Reference ├── apnt_333.pdf └── en.DM00403500.pdf ├── STM32H750XBH_ARTPIQSPI_W25Q64JV.ioc ├── STM32H750XBH_ARTPIQSPI_W25Q64JV.stldr └── loader.sct /.gitignore: -------------------------------------------------------------------------------- 1 | *.bak 2 | *.ddk 3 | *.edk 4 | *.lst 5 | *.lnp 6 | *.mpf 7 | *.mpj 8 | *.obj 9 | *.omf 10 | *.plg 11 | *.rpt 12 | *.tmp 13 | *.__i 14 | *.crf 15 | *.o 16 | *.d 17 | *.axf 18 | *.hex 19 | *.tra 20 | *.dep 21 | *.iex 22 | *.map 23 | *.swp 24 | .DS_Store 25 | MDK-ARM/*/*.htm 26 | MDK-ARM/*/*.build_log.htm 27 | MDK-ARM/DebugConfig/* 28 | MDK-ARM/*/*.uvguix.* 29 | MDK-ARM/STM32H750XBH_ARTPIQSPI_W25Q64JV.uvguix.Li Chuang 30 | -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousGenFiles] 2 | AdvancedFolderStructure=true 3 | HeaderFileListSize=5 4 | HeaderFiles#0=..\Core\Inc\gpio.h 5 | HeaderFiles#1=..\Core\Inc\quadspi.h 6 | HeaderFiles#2=..\Core\Inc\stm32h7xx_it.h 7 | HeaderFiles#3=..\Core\Inc\stm32h7xx_hal_conf.h 8 | HeaderFiles#4=..\Core\Inc\main.h 9 | HeaderFolderListSize=1 10 | HeaderPath#0=..\Core\Inc 11 | HeaderFiles=; 12 | SourceFileListSize=5 13 | SourceFiles#0=..\Core\Src\gpio.c 14 | SourceFiles#1=..\Core\Src\quadspi.c 15 | SourceFiles#2=..\Core\Src\stm32h7xx_it.c 16 | SourceFiles#3=..\Core\Src\stm32h7xx_hal_msp.c 17 | SourceFiles#4=..\Core\Src\main.c 18 | SourceFolderListSize=1 19 | SourcePath#0=..\Core\Src 20 | SourceFiles=; 21 | 22 | [PreviousLibFiles] 23 | LibFiles=Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h750xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; 24 | 25 | [PreviousUsedKeilFiles] 26 | SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\quadspi.c;..\Core\Src\stm32h7xx_it.c;..\Core\Src\stm32h7xx_hal_msp.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;..\Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;..\Core\Src\system_stm32h7xx.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;..\Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;..\Core\Src\system_stm32h7xx.c;;; 27 | HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; 28 | CDefines=USE_HAL_DRIVER;STM32H750xx;USE_HAL_DRIVER;USE_HAL_DRIVER; 29 | 30 | -------------------------------------------------------------------------------- /Core/Inc/gpio.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file gpio.h 5 | * @brief This file contains all the function prototypes for 6 | * the gpio.c file 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __GPIO_H__ 22 | #define __GPIO_H__ 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "main.h" 30 | 31 | /* USER CODE BEGIN Includes */ 32 | 33 | /* USER CODE END Includes */ 34 | 35 | /* USER CODE BEGIN Private defines */ 36 | 37 | /* USER CODE END Private defines */ 38 | 39 | void MX_GPIO_Init(void); 40 | 41 | /* USER CODE BEGIN Prototypes */ 42 | 43 | /* USER CODE END Prototypes */ 44 | 45 | #ifdef __cplusplus 46 | } 47 | #endif 48 | #endif /*__ GPIO_H__ */ 49 | 50 | -------------------------------------------------------------------------------- /Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __MAIN_H 23 | #define __MAIN_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32h7xx_hal.h" 31 | 32 | /* Private includes ----------------------------------------------------------*/ 33 | /* USER CODE BEGIN Includes */ 34 | 35 | /* USER CODE END Includes */ 36 | 37 | /* Exported types ------------------------------------------------------------*/ 38 | /* USER CODE BEGIN ET */ 39 | 40 | /* USER CODE END ET */ 41 | 42 | /* Exported constants --------------------------------------------------------*/ 43 | /* USER CODE BEGIN EC */ 44 | 45 | /* USER CODE END EC */ 46 | 47 | /* Exported macro ------------------------------------------------------------*/ 48 | /* USER CODE BEGIN EM */ 49 | #define DEBUG_WITH_UART 50 | #define W25QXX_WRITE_DIFF 51 | //#define W25QXX_READ_BY_MEMORY_MAP 52 | /* USER CODE END EM */ 53 | 54 | /* Exported functions prototypes ---------------------------------------------*/ 55 | void Error_Handler(void); 56 | 57 | /* USER CODE BEGIN EFP */ 58 | 59 | /* USER CODE END EFP */ 60 | 61 | /* Private defines -----------------------------------------------------------*/ 62 | 63 | /* USER CODE BEGIN Private defines */ 64 | 65 | /* USER CODE END Private defines */ 66 | 67 | #ifdef __cplusplus 68 | } 69 | #endif 70 | 71 | #endif /* __MAIN_H */ 72 | -------------------------------------------------------------------------------- /Core/Inc/quadspi.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file quadspi.h 5 | * @brief This file contains all the function prototypes for 6 | * the quadspi.c file 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __QUADSPI_H__ 22 | #define __QUADSPI_H__ 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "main.h" 30 | 31 | /* USER CODE BEGIN Includes */ 32 | 33 | /* USER CODE END Includes */ 34 | 35 | extern QSPI_HandleTypeDef hqspi; 36 | 37 | /* USER CODE BEGIN Private defines */ 38 | 39 | /* USER CODE END Private defines */ 40 | 41 | void MX_QUADSPI_Init(void); 42 | 43 | /* USER CODE BEGIN Prototypes */ 44 | 45 | /* USER CODE END Prototypes */ 46 | 47 | #ifdef __cplusplus 48 | } 49 | #endif 50 | 51 | #endif /* __QUADSPI_H__ */ 52 | 53 | -------------------------------------------------------------------------------- /Core/Inc/stm32h7xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2023 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32H7xx_IT_H 22 | #define __STM32H7xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void NMI_Handler(void); 50 | void HardFault_Handler(void); 51 | void MemManage_Handler(void); 52 | void BusFault_Handler(void); 53 | void UsageFault_Handler(void); 54 | void SVC_Handler(void); 55 | void DebugMon_Handler(void); 56 | void PendSV_Handler(void); 57 | void SysTick_Handler(void); 58 | /* USER CODE BEGIN EFP */ 59 | 60 | /* USER CODE END EFP */ 61 | 62 | #ifdef __cplusplus 63 | } 64 | #endif 65 | 66 | #endif /* __STM32H7xx_IT_H */ 67 | -------------------------------------------------------------------------------- /Core/Inc/usart.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file usart.h 5 | * @brief This file contains all the function prototypes for 6 | * the usart.c file 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __USART_H__ 22 | #define __USART_H__ 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "main.h" 30 | 31 | /* USER CODE BEGIN Includes */ 32 | 33 | /* USER CODE END Includes */ 34 | 35 | extern UART_HandleTypeDef huart4; 36 | 37 | /* USER CODE BEGIN Private defines */ 38 | 39 | /* USER CODE END Private defines */ 40 | 41 | void MX_UART4_Init(void); 42 | 43 | /* USER CODE BEGIN Prototypes */ 44 | 45 | /* USER CODE END Prototypes */ 46 | 47 | #ifdef __cplusplus 48 | } 49 | #endif 50 | 51 | #endif /* __USART_H__ */ 52 | 53 | -------------------------------------------------------------------------------- /Core/Inc/w25qxx.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2006-2018, RT-Thread Development Team 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Change Logs: 7 | * Date Author Notes 8 | * 2020-09-15 whj4674672 first version 9 | */ 10 | 11 | #ifndef __W25QXX_H 12 | #define __W25QXX_H 13 | 14 | typedef unsigned char uint8_t; 15 | typedef unsigned short uint16_t; 16 | typedef unsigned int uint32_t; 17 | typedef unsigned long long uint64_t; 18 | 19 | #include "quadspi.h" 20 | /*----------------------------------------------------------------------------*/ 21 | #define W25Q80 0xEF13 22 | #define W25Q16 0xEF14 23 | #define W25Q32 0xEF15 24 | #define W25Q64 0xEF16 25 | #define W25Q128 0xEF17 26 | #define W25Q256 0xEF18 27 | 28 | #define W25X_WriteEnable 0x06 29 | #define W25X_VolatileSRWriteEnable 0x50 30 | #define W25X_WriteDisable 0x04 31 | 32 | #define W25X_ReleasePowerDownID 0xAB 33 | #define W25X_ManufacturerDeviceID 0x90 34 | #define W25X_JedecID 0x9F 35 | #define W25X_ReadUniqueID 0x4B //SPI 36 | #define W25X_SetReadParameters 0xC0 //QPI 37 | 38 | #define W25X_ReadData 0x03 //SPI 39 | #define W25X_FastRead 0x0B 40 | #define W25X_BurstReadWithWrap 0x0C //QPI 41 | #define W25X_FastReadQuadIO 0xEB //QPI 42 | 43 | #define W25X_PageProgram 0x02 44 | #define W25X_SectorErase 0x20 //4KB 45 | #define W25X_BlockErase32 0x52 //32KB 46 | #define W25X_BlockErase64 0xD8 //64KB 47 | #define W25X_ChipErase 0xC7 //0x60 48 | 49 | #define W25X_ReadStatusReg1 0x05 50 | #define W25X_ReadStatusReg2 0x35 51 | #define W25X_ReadStatusReg3 0x15 52 | #define W25X_WriteStatusReg1 0x01 // Reg1 Reg2 53 | #define W25X_WriteStatusReg2 0x01 //0x31 54 | #define W25X_WriteStatusReg3 0x01 //0x11 55 | 56 | #define W25X_ReadSFDPReg 0x5A //SPI 57 | #define W25X_EraseSecurityReg 0x44 //SPI 58 | #define W25X_ProgSecurityReg 0x42 //SPI 59 | #define W25X_ReadSecurityReg 0x48 //SPI 60 | 61 | #define W25X_GlobalBlockLock 0x7E 62 | #define W25X_GlobalBlockUnlock 0x98 63 | #define W25X_ReadBlockLock 0x3D 64 | #define W25X_IndividualBlockLock 0x36 65 | #define W25X_IndividualBlockUnlock 0x39 66 | 67 | #define W25X_EraseProgramSuspend 0x75 68 | #define W25X_EraseProgramResume 0x7A 69 | 70 | #define W25X_PowerDown 0xB9 71 | 72 | #define W25X_EnterQPIMode 0x38 //SPI 73 | #define W25X_EnableReset 0x66 74 | #define W25X_ResetDevice 0x99 75 | #define W25X_ExitQPIMode 0xFF //QPI 76 | 77 | /*----------------------------------------------------------------------------*/ 78 | extern uint16_t w25qxx_mid; 79 | /*----------------------------------------------------------------------------*/ 80 | void W25QXX_Init(void); 81 | int W25QXX_ExitQPIMode(void); 82 | void W25QXX_EnterQPIMode(void); 83 | uint8_t W25QXX_ReadSR(uint8_t srx); 84 | void W25QXX_WriteSR(uint8_t srx, uint8_t dat); 85 | void W25QXX_WriteEnable(uint8_t en); 86 | 87 | uint16_t W25QXX_MftrDeviceID(void); 88 | uint8_t W25QXX_UniqueID(void); 89 | 90 | void W25QXX_Write_NoCheck(uint8_t *pbuf, uint32_t addr, uint32_t size); 91 | void W25QXX_Read(uint8_t *pbuf, uint32_t addr, uint32_t size); 92 | void W25QXX_PageProgram(uint8_t *pbuf, uint32_t addr, uint16_t size); 93 | void W25QXX_Write(uint8_t *pbuf, uint32_t addr, uint32_t size); 94 | void W25QXX_ChipErase(void); 95 | void W25QXX_SectorErase(uint32_t addr); 96 | void W25QXX_WaitBusy(void); 97 | void W25QXX_Reset(void); 98 | 99 | void W25Q_Memory_Mapped_Enable(void); 100 | void MX_QUADSPI_Init(void); 101 | 102 | void W25QXX_Block32K_Erase(uint32_t addr); 103 | void W25QXX_Block64K_Erase(uint32_t addr); 104 | #endif 105 | -------------------------------------------------------------------------------- /Core/Src/gpio.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file gpio.c 5 | * @brief This file provides code for the configuration 6 | * of all used GPIO pins. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "gpio.h" 23 | 24 | /* USER CODE BEGIN 0 */ 25 | 26 | /* USER CODE END 0 */ 27 | 28 | /*----------------------------------------------------------------------------*/ 29 | /* Configure GPIO */ 30 | /*----------------------------------------------------------------------------*/ 31 | /* USER CODE BEGIN 1 */ 32 | 33 | /* USER CODE END 1 */ 34 | 35 | /** Pinout Configuration 36 | */ 37 | void MX_GPIO_Init(void) 38 | { 39 | 40 | /* GPIO Ports Clock Enable */ 41 | __HAL_RCC_GPIOE_CLK_ENABLE(); 42 | __HAL_RCC_GPIOB_CLK_ENABLE(); 43 | __HAL_RCC_GPIOD_CLK_ENABLE(); 44 | __HAL_RCC_GPIOC_CLK_ENABLE(); 45 | 46 | } 47 | 48 | /* USER CODE BEGIN 2 */ 49 | 50 | /* USER CODE END 2 */ 51 | -------------------------------------------------------------------------------- /Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2023 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "main.h" 21 | #include "quadspi.h" 22 | #include "gpio.h" 23 | 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | 27 | /* USER CODE END Includes */ 28 | 29 | /* Private typedef -----------------------------------------------------------*/ 30 | /* USER CODE BEGIN PTD */ 31 | 32 | /* USER CODE END PTD */ 33 | 34 | /* Private define ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN PD */ 36 | 37 | /* USER CODE END PD */ 38 | 39 | /* Private macro -------------------------------------------------------------*/ 40 | /* USER CODE BEGIN PM */ 41 | 42 | /* USER CODE END PM */ 43 | 44 | /* Private variables ---------------------------------------------------------*/ 45 | 46 | /* USER CODE BEGIN PV */ 47 | 48 | /* USER CODE END PV */ 49 | 50 | /* Private function prototypes -----------------------------------------------*/ 51 | void SystemClock_Config(void); 52 | /* USER CODE BEGIN PFP */ 53 | 54 | /* USER CODE END PFP */ 55 | 56 | /* Private user code ---------------------------------------------------------*/ 57 | /* USER CODE BEGIN 0 */ 58 | 59 | /* USER CODE END 0 */ 60 | 61 | /** 62 | * @brief System Clock Configuration 63 | * @retval None 64 | */ 65 | void SystemClock_Config(void) 66 | { 67 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 68 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 69 | // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 70 | 71 | /** Supply configuration update enable 72 | */ 73 | HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 74 | /** Configure the main internal regulator output voltage 75 | */ 76 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 77 | 78 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 79 | /** Initializes the RCC Oscillators according to the specified parameters 80 | * in the RCC_OscInitTypeDef structure. 81 | */ 82 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 83 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; 84 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 85 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 86 | RCC_OscInitStruct.PLL.PLLM = 5; 87 | RCC_OscInitStruct.PLL.PLLN = 192; 88 | RCC_OscInitStruct.PLL.PLLP = 2; 89 | RCC_OscInitStruct.PLL.PLLQ = 2; 90 | RCC_OscInitStruct.PLL.PLLR = 2; 91 | RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 92 | RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 93 | RCC_OscInitStruct.PLL.PLLFRACN = 0; 94 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 95 | { 96 | Error_Handler(); 97 | } 98 | /** Initializes the CPU, AHB and APB buses clocks 99 | */ 100 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 101 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 102 | |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; 103 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 104 | RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 105 | RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 106 | RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 107 | RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 108 | RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 109 | RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 110 | 111 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 112 | { 113 | Error_Handler(); 114 | } 115 | // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_QSPI; 116 | // PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; 117 | // PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 118 | // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 119 | // { 120 | // Error_Handler(); 121 | // } 122 | } 123 | 124 | /* USER CODE BEGIN 4 */ 125 | 126 | /* USER CODE END 4 */ 127 | 128 | /** 129 | * @brief This function is executed in case of error occurrence. 130 | * @retval None 131 | */ 132 | void Error_Handler(void) 133 | { 134 | /* USER CODE BEGIN Error_Handler_Debug */ 135 | /* User can add his own implementation to report the HAL error return state */ 136 | __disable_irq(); 137 | while (1) 138 | { 139 | } 140 | /* USER CODE END Error_Handler_Debug */ 141 | } 142 | 143 | #ifdef USE_FULL_ASSERT 144 | /** 145 | * @brief Reports the name of the source file and the source line number 146 | * where the assert_param error has occurred. 147 | * @param file: pointer to the source file name 148 | * @param line: assert_param error line source number 149 | * @retval None 150 | */ 151 | void assert_failed(uint8_t *file, uint32_t line) 152 | { 153 | /* USER CODE BEGIN 6 */ 154 | /* User can add his own implementation to report the file name and line number, 155 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 156 | /* USER CODE END 6 */ 157 | } 158 | #endif /* USE_FULL_ASSERT */ 159 | -------------------------------------------------------------------------------- /Core/Src/quadspi.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file quadspi.c 5 | * @brief This file provides code for the configuration 6 | * of the QUADSPI instances. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "quadspi.h" 22 | #include 23 | /* USER CODE BEGIN 0 */ 24 | 25 | /* USER CODE END 0 */ 26 | 27 | 28 | //QSPI_HandleTypeDef hqspi; 29 | 30 | ///* QUADSPI init function */ 31 | //void MX_QUADSPI_Init(void) 32 | //{ 33 | 34 | // /* USER CODE BEGIN QUADSPI_Init 0 */ 35 | 36 | // /* USER CODE END QUADSPI_Init 0 */ 37 | 38 | // /* USER CODE BEGIN QUADSPI_Init 1 */ 39 | 40 | // /* USER CODE END QUADSPI_Init 1 */ 41 | // hqspi.Instance = QUADSPI; 42 | // hqspi.Init.ClockPrescaler = 1; 43 | // hqspi.Init.FifoThreshold = 32; 44 | // hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; 45 | // hqspi.Init.FlashSize = 22; 46 | // hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE; 47 | // hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; 48 | // hqspi.Init.FlashID = QSPI_FLASH_ID_1; 49 | // hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; 50 | // if (HAL_QSPI_Init(&hqspi) != HAL_OK) 51 | // { 52 | // Error_Handler(); 53 | // } 54 | // /* USER CODE BEGIN QUADSPI_Init 2 */ 55 | 56 | // /* USER CODE END QUADSPI_Init 2 */ 57 | 58 | //} 59 | 60 | //void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle) 61 | //{ 62 | 63 | // GPIO_InitTypeDef GPIO_InitStruct = {0}; 64 | // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 65 | // if(qspiHandle->Instance==QUADSPI) 66 | // { 67 | // /* USER CODE BEGIN QUADSPI_MspInit 0 */ 68 | 69 | // /* USER CODE END QUADSPI_MspInit 0 */ 70 | 71 | // /** Initializes the peripherals clock 72 | // */ 73 | // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI; 74 | // PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; 75 | // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 76 | // { 77 | // Error_Handler(); 78 | // } 79 | 80 | // /* QUADSPI clock enable */ 81 | // __HAL_RCC_QSPI_CLK_ENABLE(); 82 | 83 | // __HAL_RCC_GPIOG_CLK_ENABLE(); 84 | // __HAL_RCC_GPIOF_CLK_ENABLE(); 85 | // /**QUADSPI GPIO Configuration 86 | // PG6 ------> QUADSPI_BK1_NCS 87 | // PF6 ------> QUADSPI_BK1_IO3 88 | // PF7 ------> QUADSPI_BK1_IO2 89 | // PF8 ------> QUADSPI_BK1_IO0 90 | // PF10 ------> QUADSPI_CLK 91 | // PF9 ------> QUADSPI_BK1_IO1 92 | // */ 93 | // GPIO_InitStruct.Pin = GPIO_PIN_6; 94 | // GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 95 | // GPIO_InitStruct.Pull = GPIO_NOPULL; 96 | // GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 97 | // GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; 98 | // HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 99 | 100 | // GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10; 101 | // GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 102 | // GPIO_InitStruct.Pull = GPIO_NOPULL; 103 | // GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 104 | // GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; 105 | // HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 106 | 107 | // GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 108 | // GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 109 | // GPIO_InitStruct.Pull = GPIO_NOPULL; 110 | // GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 111 | // GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; 112 | // HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 113 | 114 | // /* USER CODE BEGIN QUADSPI_MspInit 1 */ 115 | 116 | // /* USER CODE END QUADSPI_MspInit 1 */ 117 | // } 118 | //} 119 | 120 | //void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle) 121 | //{ 122 | 123 | // if(qspiHandle->Instance==QUADSPI) 124 | // { 125 | // /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ 126 | 127 | // /* USER CODE END QUADSPI_MspDeInit 0 */ 128 | // /* Peripheral clock disable */ 129 | // __HAL_RCC_QSPI_CLK_DISABLE(); 130 | 131 | // /**QUADSPI GPIO Configuration 132 | // PG6 ------> QUADSPI_BK1_NCS 133 | // PF6 ------> QUADSPI_BK1_IO3 134 | // PF7 ------> QUADSPI_BK1_IO2 135 | // PF8 ------> QUADSPI_BK1_IO0 136 | // PF10 ------> QUADSPI_CLK 137 | // PF9 ------> QUADSPI_BK1_IO1 138 | // */ 139 | // HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6); 140 | 141 | // HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_10 142 | // |GPIO_PIN_9); 143 | 144 | // /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ 145 | 146 | // /* USER CODE END QUADSPI_MspDeInit 1 */ 147 | // } 148 | //} 149 | 150 | /* USER CODE BEGIN 1 */ 151 | 152 | /* USER CODE END 1 */ 153 | -------------------------------------------------------------------------------- /Core/Src/stm32h7xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | /* USER CODE BEGIN Includes */ 24 | 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN Define */ 34 | 35 | /* USER CODE END Define */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN Macro */ 39 | 40 | /* USER CODE END Macro */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* External functions --------------------------------------------------------*/ 53 | /* USER CODE BEGIN ExternalFunctions */ 54 | 55 | /* USER CODE END ExternalFunctions */ 56 | 57 | /* USER CODE BEGIN 0 */ 58 | 59 | /* USER CODE END 0 */ 60 | /** 61 | * Initializes the Global MSP. 62 | */ 63 | void HAL_MspInit(void) 64 | { 65 | /* USER CODE BEGIN MspInit 0 */ 66 | 67 | /* USER CODE END MspInit 0 */ 68 | 69 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 70 | 71 | /* System interrupt init*/ 72 | 73 | /* USER CODE BEGIN MspInit 1 */ 74 | 75 | /* USER CODE END MspInit 1 */ 76 | } 77 | 78 | /* USER CODE BEGIN 1 */ 79 | void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle) 80 | { 81 | 82 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 83 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 84 | if(qspiHandle->Instance==QUADSPI) 85 | { 86 | /* USER CODE BEGIN QUADSPI_MspInit 0 */ 87 | 88 | /* USER CODE END QUADSPI_MspInit 0 */ 89 | 90 | /** Initializes the peripherals clock 91 | */ 92 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI; 93 | PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; 94 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 95 | { 96 | Error_Handler(); 97 | } 98 | 99 | /* QUADSPI clock enable */ 100 | __HAL_RCC_QSPI_CLK_ENABLE(); 101 | 102 | __HAL_RCC_GPIOG_CLK_ENABLE(); 103 | __HAL_RCC_GPIOF_CLK_ENABLE(); 104 | /**QUADSPI GPIO Configuration 105 | PG6 ------> QUADSPI_BK1_NCS 106 | PF6 ------> QUADSPI_BK1_IO3 107 | PF7 ------> QUADSPI_BK1_IO2 108 | PF8 ------> QUADSPI_BK1_IO0 109 | PF10 ------> QUADSPI_CLK 110 | PF9 ------> QUADSPI_BK1_IO1 111 | */ 112 | GPIO_InitStruct.Pin = GPIO_PIN_6; 113 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 114 | GPIO_InitStruct.Pull = GPIO_NOPULL; 115 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 116 | GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; 117 | HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 118 | 119 | GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10; 120 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 121 | GPIO_InitStruct.Pull = GPIO_NOPULL; 122 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 123 | GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; 124 | HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 125 | 126 | GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 127 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 128 | GPIO_InitStruct.Pull = GPIO_NOPULL; 129 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 130 | GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; 131 | HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 132 | 133 | /* USER CODE BEGIN QUADSPI_MspInit 1 */ 134 | 135 | /* USER CODE END QUADSPI_MspInit 1 */ 136 | } 137 | } 138 | 139 | void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle) 140 | { 141 | 142 | if(qspiHandle->Instance==QUADSPI) 143 | { 144 | /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ 145 | 146 | /* USER CODE END QUADSPI_MspDeInit 0 */ 147 | /* Peripheral clock disable */ 148 | __HAL_RCC_QSPI_CLK_DISABLE(); 149 | 150 | /**QUADSPI GPIO Configuration 151 | PG6 ------> QUADSPI_BK1_NCS 152 | PF6 ------> QUADSPI_BK1_IO3 153 | PF7 ------> QUADSPI_BK1_IO2 154 | PF8 ------> QUADSPI_BK1_IO0 155 | PF10 ------> QUADSPI_CLK 156 | PF9 ------> QUADSPI_BK1_IO1 157 | */ 158 | HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6); 159 | 160 | HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_10 161 | |GPIO_PIN_9); 162 | 163 | /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ 164 | 165 | /* USER CODE END QUADSPI_MspDeInit 1 */ 166 | } 167 | } 168 | 169 | 170 | 171 | 172 | 173 | /* USER CODE BEGIN 1 */ 174 | void HAL_UART_MspInit(UART_HandleTypeDef* huart) 175 | { 176 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 177 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 178 | if(huart->Instance==UART4) 179 | { 180 | /* USER CODE BEGIN UART4_MspInit 0 */ 181 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4; 182 | PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 183 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 184 | { 185 | Error_Handler(); 186 | } 187 | /* USER CODE END UART4_MspInit 0 */ 188 | /* Peripheral clock enable */ 189 | __HAL_RCC_UART4_CLK_ENABLE(); 190 | 191 | __HAL_RCC_GPIOI_CLK_ENABLE(); 192 | __HAL_RCC_GPIOA_CLK_ENABLE(); 193 | /**UART4 GPIO Configuration 194 | PI9 ------> UART4_RX 195 | PA0 ------> UART4_TX 196 | */ 197 | GPIO_InitStruct.Pin = GPIO_PIN_9; 198 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 199 | GPIO_InitStruct.Pull = GPIO_NOPULL; 200 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 201 | GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 202 | HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); 203 | 204 | GPIO_InitStruct.Pin = GPIO_PIN_0; 205 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 206 | GPIO_InitStruct.Pull = GPIO_NOPULL; 207 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 208 | GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 209 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 210 | 211 | /* USER CODE BEGIN UART4_MspInit 1 */ 212 | 213 | /* USER CODE END UART4_MspInit 1 */ 214 | } 215 | 216 | } 217 | 218 | /** 219 | * @brief UART MSP De-Initialization 220 | * This function freeze the hardware resources used in this example 221 | * @param huart: UART handle pointer 222 | * @retval None 223 | */ 224 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) 225 | { 226 | if(huart->Instance==UART4) 227 | { 228 | /* USER CODE BEGIN UART4_MspDeInit 0 */ 229 | 230 | /* USER CODE END UART4_MspDeInit 0 */ 231 | /* Peripheral clock disable */ 232 | __HAL_RCC_UART4_CLK_DISABLE(); 233 | 234 | /**UART4 GPIO Configuration 235 | PI9 ------> UART4_RX 236 | PA0 ------> UART4_TX 237 | */ 238 | HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9); 239 | 240 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); 241 | 242 | /* USER CODE BEGIN UART4_MspDeInit 1 */ 243 | 244 | /* USER CODE END UART4_MspDeInit 1 */ 245 | } 246 | 247 | } 248 | /* USER CODE END 1 */ 249 | -------------------------------------------------------------------------------- /Core/Src/stm32h7xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2023 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "stm32h7xx_it.h" 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN PD */ 34 | 35 | /* USER CODE END PD */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN PM */ 39 | 40 | /* USER CODE END PM */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* Private user code ---------------------------------------------------------*/ 53 | /* USER CODE BEGIN 0 */ 54 | 55 | /* USER CODE END 0 */ 56 | 57 | /* External variables --------------------------------------------------------*/ 58 | 59 | /* USER CODE BEGIN EV */ 60 | 61 | /* USER CODE END EV */ 62 | 63 | /******************************************************************************/ 64 | /* Cortex Processor Interruption and Exception Handlers */ 65 | /******************************************************************************/ 66 | /** 67 | * @brief This function handles Non maskable interrupt. 68 | */ 69 | void NMI_Handler(void) 70 | { 71 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 72 | 73 | /* USER CODE END NonMaskableInt_IRQn 0 */ 74 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 75 | while (1) 76 | { 77 | } 78 | /* USER CODE END NonMaskableInt_IRQn 1 */ 79 | } 80 | 81 | /** 82 | * @brief This function handles Hard fault interrupt. 83 | */ 84 | void HardFault_Handler(void) 85 | { 86 | /* USER CODE BEGIN HardFault_IRQn 0 */ 87 | 88 | /* USER CODE END HardFault_IRQn 0 */ 89 | while (1) 90 | { 91 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 92 | /* USER CODE END W1_HardFault_IRQn 0 */ 93 | } 94 | } 95 | 96 | /** 97 | * @brief This function handles Memory management fault. 98 | */ 99 | void MemManage_Handler(void) 100 | { 101 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 102 | 103 | /* USER CODE END MemoryManagement_IRQn 0 */ 104 | while (1) 105 | { 106 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 107 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 108 | } 109 | } 110 | 111 | /** 112 | * @brief This function handles Pre-fetch fault, memory access fault. 113 | */ 114 | void BusFault_Handler(void) 115 | { 116 | /* USER CODE BEGIN BusFault_IRQn 0 */ 117 | 118 | /* USER CODE END BusFault_IRQn 0 */ 119 | while (1) 120 | { 121 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 122 | /* USER CODE END W1_BusFault_IRQn 0 */ 123 | } 124 | } 125 | 126 | /** 127 | * @brief This function handles Undefined instruction or illegal state. 128 | */ 129 | void UsageFault_Handler(void) 130 | { 131 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 132 | 133 | /* USER CODE END UsageFault_IRQn 0 */ 134 | while (1) 135 | { 136 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 137 | /* USER CODE END W1_UsageFault_IRQn 0 */ 138 | } 139 | } 140 | 141 | /** 142 | * @brief This function handles System service call via SWI instruction. 143 | */ 144 | void SVC_Handler(void) 145 | { 146 | /* USER CODE BEGIN SVCall_IRQn 0 */ 147 | 148 | /* USER CODE END SVCall_IRQn 0 */ 149 | /* USER CODE BEGIN SVCall_IRQn 1 */ 150 | 151 | /* USER CODE END SVCall_IRQn 1 */ 152 | } 153 | 154 | /** 155 | * @brief This function handles Debug monitor. 156 | */ 157 | void DebugMon_Handler(void) 158 | { 159 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 160 | 161 | /* USER CODE END DebugMonitor_IRQn 0 */ 162 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 163 | 164 | /* USER CODE END DebugMonitor_IRQn 1 */ 165 | } 166 | 167 | /** 168 | * @brief This function handles Pendable request for system service. 169 | */ 170 | void PendSV_Handler(void) 171 | { 172 | /* USER CODE BEGIN PendSV_IRQn 0 */ 173 | 174 | /* USER CODE END PendSV_IRQn 0 */ 175 | /* USER CODE BEGIN PendSV_IRQn 1 */ 176 | 177 | /* USER CODE END PendSV_IRQn 1 */ 178 | } 179 | 180 | /** 181 | * @brief This function handles System tick timer. 182 | */ 183 | void SysTick_Handler(void) 184 | { 185 | /* USER CODE BEGIN SysTick_IRQn 0 */ 186 | 187 | /* USER CODE END SysTick_IRQn 0 */ 188 | HAL_IncTick(); 189 | /* USER CODE BEGIN SysTick_IRQn 1 */ 190 | 191 | /* USER CODE END SysTick_IRQn 1 */ 192 | } 193 | 194 | /******************************************************************************/ 195 | /* STM32H7xx Peripheral Interrupt Handlers */ 196 | /* Add here the Interrupt Handlers for the used peripherals. */ 197 | /* For the available peripheral interrupt handler names, */ 198 | /* please refer to the startup file (startup_stm32h7xx.s). */ 199 | /******************************************************************************/ 200 | 201 | /* USER CODE BEGIN 1 */ 202 | 203 | /* USER CODE END 1 */ 204 | -------------------------------------------------------------------------------- /Core/Src/usart.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file usart.c 5 | * @brief This file provides code for the configuration 6 | * of the USART instances. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "usart.h" 22 | 23 | /* USER CODE BEGIN 0 */ 24 | 25 | /* USER CODE END 0 */ 26 | 27 | UART_HandleTypeDef huart4; 28 | 29 | /* UART4 init function */ 30 | void MX_UART4_Init(void) 31 | { 32 | 33 | /* USER CODE BEGIN UART4_Init 0 */ 34 | 35 | /* USER CODE END UART4_Init 0 */ 36 | 37 | /* USER CODE BEGIN UART4_Init 1 */ 38 | 39 | /* USER CODE END UART4_Init 1 */ 40 | huart4.Instance = UART4; 41 | huart4.Init.BaudRate = 115200; 42 | huart4.Init.WordLength = UART_WORDLENGTH_8B; 43 | huart4.Init.StopBits = UART_STOPBITS_1; 44 | huart4.Init.Parity = UART_PARITY_NONE; 45 | huart4.Init.Mode = UART_MODE_TX; 46 | huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 47 | huart4.Init.OverSampling = UART_OVERSAMPLING_16; 48 | // huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 49 | huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; 50 | huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 51 | if (HAL_UART_Init(&huart4) != HAL_OK) 52 | { 53 | Error_Handler(); 54 | } 55 | /* USER CODE BEGIN UART4_Init 2 */ 56 | 57 | /* USER CODE END UART4_Init 2 */ 58 | 59 | } 60 | /* USER CODE BEGIN 1 */ 61 | 62 | /* USER CODE END 1 */ 63 | -------------------------------------------------------------------------------- /Dev_Inf.c: -------------------------------------------------------------------------------- 1 | #include "Dev_Inf.h" 2 | 3 | /* This structure containes information used by ST-LINK Utility to program and erase the device */ 4 | #if defined(__ICCARM__) 5 | __root struct StorageInfo const StorageInfo = { 6 | #else 7 | struct StorageInfo const StorageInfo = { 8 | #endif 9 | "STM32H750XBH_ARTPI_W25Q64JV", // Device Name + EVAL Borad name 10 | SPI_FLASH, // Device Type 11 | 0x90000000, // Device Start Address 12 | 0x00800000, // Device Size in Bytes (8MBytes) 13 | 0x1000, // Programming Page Size 256Bytes 14 | 0xFF, // Initial Content of Erased Memory 15 | // Specify Size and Address of Sectors (view example below) 16 | {{0x00000800, 0x00001000,}, // Sector Num : 2048 ,Sector Size: 4KBytes 17 | {0x00000000, 0x00000000,}} 18 | }; 19 | 20 | -------------------------------------------------------------------------------- /Dev_Inf.h: -------------------------------------------------------------------------------- 1 | #define MCU_FLASH 1 2 | #define NAND_FLASH 2 3 | #define NOR_FLASH 3 4 | #define SRAM 4 5 | #define PSRAM 5 6 | #define PC_CARD 6 7 | #define SPI_FLASH 7 8 | #define I2C_FLASH 8 9 | #define SDRAM 9 10 | #define I2C_EEPROM 10 11 | 12 | #define SECTOR_NUM 10 // Max Number of Sector types 13 | 14 | struct DeviceSectors 15 | { 16 | unsigned long SectorNum; // Number of Sectors 17 | unsigned long SectorSize; // Sector Size in Bytes 18 | }; 19 | 20 | struct StorageInfo 21 | { 22 | char DeviceName[100]; // Device Name and Description 23 | unsigned short DeviceType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... 24 | unsigned long DeviceStartAddress; // Default Device Start Address 25 | unsigned long DeviceSize; // Total Size of Device 26 | unsigned long PageSize; // Programming Page Size 27 | unsigned char EraseValue; // Content of Erased Memory 28 | struct DeviceSectors sectors[SECTOR_NUM]; 29 | }; 30 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32H7xx device used in the target application 11 | * - To use or not the peripheral's drivers in application code(i.e. 12 | * code will be based on direct access to peripheral's registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | * Copyright (c) 2017 STMicroelectronics. 20 | * All rights reserved. 21 | * 22 | * This software is licensed under terms that can be found in the LICENSE file 23 | * in the root directory of this software component. 24 | * If no LICENSE file comes with this software, it is provided AS-IS. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /** @addtogroup CMSIS 30 | * @{ 31 | */ 32 | 33 | /** @addtogroup stm32h7xx 34 | * @{ 35 | */ 36 | 37 | #ifndef STM32H7xx_H 38 | #define STM32H7xx_H 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif /* __cplusplus */ 43 | 44 | /** @addtogroup Library_configuration_section 45 | * @{ 46 | */ 47 | 48 | /** 49 | * @brief STM32 Family 50 | */ 51 | #if !defined (STM32H7) 52 | #define STM32H7 53 | #endif /* STM32H7 */ 54 | 55 | 56 | /* Uncomment the line below according to the target STM32H7 device used in your 57 | application 58 | */ 59 | 60 | #if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \ 61 | !defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \ 62 | !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \ 63 | !defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx) 64 | /* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */ 65 | /* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */ 66 | /* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */ 67 | /* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */ 68 | /* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */ 69 | /* #define STM32H747xG */ /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */ 70 | /* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */ 71 | /* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */ 72 | /* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */ 73 | /* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */ 74 | /* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */ 75 | /* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */ 76 | /* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */ 77 | /* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */ 78 | /* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */ 79 | /* #define STM32H735xx */ /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */ 80 | /* #define STM32H733xx */ /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */ 81 | /* #define STM32H730xx */ /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */ 82 | /* #define STM32H730xxQ */ /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */ 83 | /* #define STM32H725xx */ /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices */ 84 | /* #define STM32H723xx */ /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */ 85 | #endif 86 | 87 | /* Tip: To avoid modifying this file each time you need to switch between these 88 | devices, you can define the device in your toolchain compiler preprocessor. 89 | */ 90 | 91 | #if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7) 92 | #error "Dual core device, please select CORE_CM4 or CORE_CM7" 93 | #endif 94 | 95 | #if !defined (USE_HAL_DRIVER) 96 | /** 97 | * @brief Comment the line below if you will not use the peripherals drivers. 98 | In this case, these drivers will not be included and the application code will 99 | be based on direct access to peripherals registers 100 | */ 101 | /*#define USE_HAL_DRIVER */ 102 | #endif /* USE_HAL_DRIVER */ 103 | 104 | /** 105 | * @brief CMSIS Device version number V1.10.3 106 | */ 107 | #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ 108 | #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ 109 | #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ 110 | #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ 111 | #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ 112 | |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ 113 | |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ 114 | |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC)) 115 | 116 | /** 117 | * @} 118 | */ 119 | 120 | /** @addtogroup Device_Included 121 | * @{ 122 | */ 123 | 124 | #if defined(STM32H743xx) 125 | #include "stm32h743xx.h" 126 | #elif defined(STM32H753xx) 127 | #include "stm32h753xx.h" 128 | #elif defined(STM32H750xx) 129 | #include "stm32h750xx.h" 130 | #elif defined(STM32H742xx) 131 | #include "stm32h742xx.h" 132 | #elif defined(STM32H745xx) 133 | #include "stm32h745xx.h" 134 | #elif defined(STM32H745xG) 135 | #include "stm32h745xg.h" 136 | #elif defined(STM32H755xx) 137 | #include "stm32h755xx.h" 138 | #elif defined(STM32H747xx) 139 | #include "stm32h747xx.h" 140 | #elif defined(STM32H747xG) 141 | #include "stm32h747xg.h" 142 | #elif defined(STM32H757xx) 143 | #include "stm32h757xx.h" 144 | #elif defined(STM32H7B0xx) 145 | #include "stm32h7b0xx.h" 146 | #elif defined(STM32H7B0xxQ) 147 | #include "stm32h7b0xxq.h" 148 | #elif defined(STM32H7A3xx) 149 | #include "stm32h7a3xx.h" 150 | #elif defined(STM32H7B3xx) 151 | #include "stm32h7b3xx.h" 152 | #elif defined(STM32H7A3xxQ) 153 | #include "stm32h7a3xxq.h" 154 | #elif defined(STM32H7B3xxQ) 155 | #include "stm32h7b3xxq.h" 156 | #elif defined(STM32H735xx) 157 | #include "stm32h735xx.h" 158 | #elif defined(STM32H733xx) 159 | #include "stm32h733xx.h" 160 | #elif defined(STM32H730xx) 161 | #include "stm32h730xx.h" 162 | #elif defined(STM32H730xxQ) 163 | #include "stm32h730xxq.h" 164 | #elif defined(STM32H725xx) 165 | #include "stm32h725xx.h" 166 | #elif defined(STM32H723xx) 167 | #include "stm32h723xx.h" 168 | #else 169 | #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)" 170 | #endif 171 | 172 | /** 173 | * @} 174 | */ 175 | 176 | /** @addtogroup Exported_types 177 | * @{ 178 | */ 179 | typedef enum 180 | { 181 | RESET = 0, 182 | SET = !RESET 183 | } FlagStatus, ITStatus; 184 | 185 | typedef enum 186 | { 187 | DISABLE = 0, 188 | ENABLE = !DISABLE 189 | } FunctionalState; 190 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 191 | 192 | typedef enum 193 | { 194 | SUCCESS = 0, 195 | ERROR = !SUCCESS 196 | } ErrorStatus; 197 | 198 | /** 199 | * @} 200 | */ 201 | 202 | 203 | /** @addtogroup Exported_macros 204 | * @{ 205 | */ 206 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 207 | 208 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 209 | 210 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 211 | 212 | #define CLEAR_REG(REG) ((REG) = (0x0)) 213 | 214 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 215 | 216 | #define READ_REG(REG) ((REG)) 217 | 218 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 219 | 220 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 221 | 222 | /* Use of CMSIS compiler intrinsics for register exclusive access */ 223 | /* Atomic 32-bit register access macro to set one or several bits */ 224 | #define ATOMIC_SET_BIT(REG, BIT) \ 225 | do { \ 226 | uint32_t val; \ 227 | do { \ 228 | val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ 229 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 230 | } while(0) 231 | 232 | /* Atomic 32-bit register access macro to clear one or several bits */ 233 | #define ATOMIC_CLEAR_BIT(REG, BIT) \ 234 | do { \ 235 | uint32_t val; \ 236 | do { \ 237 | val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ 238 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 239 | } while(0) 240 | 241 | /* Atomic 32-bit register access macro to clear and set one or several bits */ 242 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 243 | do { \ 244 | uint32_t val; \ 245 | do { \ 246 | val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 247 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 248 | } while(0) 249 | 250 | /* Atomic 16-bit register access macro to set one or several bits */ 251 | #define ATOMIC_SETH_BIT(REG, BIT) \ 252 | do { \ 253 | uint16_t val; \ 254 | do { \ 255 | val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ 256 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 257 | } while(0) 258 | 259 | /* Atomic 16-bit register access macro to clear one or several bits */ 260 | #define ATOMIC_CLEARH_BIT(REG, BIT) \ 261 | do { \ 262 | uint16_t val; \ 263 | do { \ 264 | val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ 265 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 266 | } while(0) 267 | 268 | /* Atomic 16-bit register access macro to clear and set one or several bits */ 269 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ 270 | do { \ 271 | uint16_t val; \ 272 | do { \ 273 | val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 274 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 275 | } while(0) 276 | 277 | /** 278 | * @} 279 | */ 280 | 281 | #if defined (USE_HAL_DRIVER) 282 | #include "stm32h7xx_hal.h" 283 | #endif /* USE_HAL_DRIVER */ 284 | 285 | 286 | #ifdef __cplusplus 287 | } 288 | #endif /* __cplusplus */ 289 | 290 | #endif /* STM32H7xx_H */ 291 | /** 292 | * @} 293 | */ 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | 300 | 301 | 302 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32h7xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /** @addtogroup CMSIS 20 | * @{ 21 | */ 22 | 23 | /** @addtogroup stm32h7xx_system 24 | * @{ 25 | */ 26 | 27 | /** 28 | * @brief Define to prevent recursive inclusion 29 | */ 30 | #ifndef SYSTEM_STM32H7XX_H 31 | #define SYSTEM_STM32H7XX_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /** @addtogroup STM32H7xx_System_Includes 38 | * @{ 39 | */ 40 | 41 | /** 42 | * @} 43 | */ 44 | 45 | 46 | /** @addtogroup STM32H7xx_System_Exported_types 47 | * @{ 48 | */ 49 | /* This variable is updated in three ways: 50 | 1) by calling CMSIS function SystemCoreClockUpdate() 51 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 52 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 53 | Note: If you use this function to configure the system clock; then there 54 | is no need to call the 2 first functions listed above, since SystemCoreClock 55 | variable is updated automatically. 56 | */ 57 | extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */ 58 | extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */ 59 | extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32H7xx_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32H7xx_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32H7xx_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /* SYSTEM_STM32H7XX_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32H7xx/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the Apache-2.0 license shall apply. 5 | You may obtain a copy of the Apache-2.0 at: 6 | https://opensource.org/licenses/Apache-2.0 7 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ 109 | (((MPU_RASR_ENABLE_Msk)))) 110 | 111 | /** 112 | * MPU Region Attribute and Size Register Value 113 | * 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 117 | * \param IsShareable Region is shareable between multiple bus masters. 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 120 | * \param SubRegionDisable Sub-region disable field. 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. 122 | */ 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 125 | 126 | /** 127 | * MPU Memory Access Attribute for strongly ordered memory. 128 | * - TEX: 000b 129 | * - Shareable 130 | * - Non-cacheable 131 | * - Non-bufferable 132 | */ 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 134 | 135 | /** 136 | * MPU Memory Access Attribute for device memory. 137 | * - TEX: 000b (if shareable) or 010b (if non-shareable) 138 | * - Shareable or non-shareable 139 | * - Non-cacheable 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 141 | * 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. 143 | */ 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 145 | 146 | /** 147 | * MPU Memory Access Attribute for normal memory. 148 | * - TEX: 1BBb (reflecting outer cacheability rules) 149 | * - Shareable or non-shareable 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 152 | * 153 | * \param OuterCp Configures the outer cache policy. 154 | * \param InnerCp Configures the inner cache policy. 155 | * \param IsShareable Configures the memory as shareable or non-shareable. 156 | */ 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute non-cacheable policy. 161 | */ 162 | #define ARM_MPU_CACHEP_NOCACHE 0U 163 | 164 | /** 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. 166 | */ 167 | #define ARM_MPU_CACHEP_WB_WRA 1U 168 | 169 | /** 170 | * MPU Memory Access Attribute write-through, no write allocate policy. 171 | */ 172 | #define ARM_MPU_CACHEP_WT_NWA 2U 173 | 174 | /** 175 | * MPU Memory Access Attribute write-back, no write allocate policy. 176 | */ 177 | #define ARM_MPU_CACHEP_WB_NWA 3U 178 | 179 | 180 | /** 181 | * Struct for a single MPU Region 182 | */ 183 | typedef struct { 184 | uint32_t RBAR; //!< The region base address register value (RBAR) 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 186 | } ARM_MPU_Region_t; 187 | 188 | /** Enable the MPU. 189 | * \param MPU_Control Default access permissions for unconfigured regions. 190 | */ 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 192 | { 193 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 194 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 195 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 196 | #endif 197 | __DSB(); 198 | __ISB(); 199 | } 200 | 201 | /** Disable the MPU. 202 | */ 203 | __STATIC_INLINE void ARM_MPU_Disable(void) 204 | { 205 | __DMB(); 206 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 207 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 208 | #endif 209 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | MPU->RNR = rnr; 218 | MPU->RASR = 0U; 219 | } 220 | 221 | /** Configure an MPU region. 222 | * \param rbar Value for RBAR register. 223 | * \param rsar Value for RSAR register. 224 | */ 225 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 226 | { 227 | MPU->RBAR = rbar; 228 | MPU->RASR = rasr; 229 | } 230 | 231 | /** Configure the given MPU region. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rsar Value for RSAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 237 | { 238 | MPU->RNR = rnr; 239 | MPU->RBAR = rbar; 240 | MPU->RASR = rasr; 241 | } 242 | 243 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 244 | * \param dst Destination data is copied to. 245 | * \param src Source data is copied from. 246 | * \param len Amount of data words to be copied. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 249 | { 250 | uint32_t i; 251 | for (i = 0U; i < len; ++i) 252 | { 253 | dst[i] = src[i]; 254 | } 255 | } 256 | 257 | /** Load the given number of MPU regions from a table. 258 | * \param table Pointer to the MPU configuration table. 259 | * \param cnt Amount of regions to be configured. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 262 | { 263 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 264 | while (cnt > MPU_TYPE_RALIASES) { 265 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 266 | table += MPU_TYPE_RALIASES; 267 | cnt -= MPU_TYPE_RALIASES; 268 | } 269 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 270 | } 271 | 272 | #endif 273 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | #if defined(MPU_RLAR_PXN_Pos) 105 | 106 | /** \brief Region Limit Address Register with PXN value 107 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 108 | * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. 109 | * \param IDX The attribute index to be associated with this memory region. 110 | */ 111 | #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ 112 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 113 | ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ 114 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 115 | (MPU_RLAR_EN_Msk)) 116 | 117 | #endif 118 | 119 | /** 120 | * Struct for a single MPU Region 121 | */ 122 | typedef struct { 123 | uint32_t RBAR; /*!< Region Base Address Register value */ 124 | uint32_t RLAR; /*!< Region Limit Address Register value */ 125 | } ARM_MPU_Region_t; 126 | 127 | /** Enable the MPU. 128 | * \param MPU_Control Default access permissions for unconfigured regions. 129 | */ 130 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 131 | { 132 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 133 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 134 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 135 | #endif 136 | __DSB(); 137 | __ISB(); 138 | } 139 | 140 | /** Disable the MPU. 141 | */ 142 | __STATIC_INLINE void ARM_MPU_Disable(void) 143 | { 144 | __DMB(); 145 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 146 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 147 | #endif 148 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 149 | } 150 | 151 | #ifdef MPU_NS 152 | /** Enable the Non-secure MPU. 153 | * \param MPU_Control Default access permissions for unconfigured regions. 154 | */ 155 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 156 | { 157 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 158 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 160 | #endif 161 | __DSB(); 162 | __ISB(); 163 | } 164 | 165 | /** Disable the Non-secure MPU. 166 | */ 167 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 168 | { 169 | __DMB(); 170 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 171 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 172 | #endif 173 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 174 | } 175 | #endif 176 | 177 | /** Set the memory attribute encoding to the given MPU. 178 | * \param mpu Pointer to the MPU to be configured. 179 | * \param idx The attribute index to be set [0-7] 180 | * \param attr The attribute value to be set. 181 | */ 182 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 183 | { 184 | const uint8_t reg = idx / 4U; 185 | const uint32_t pos = ((idx % 4U) * 8U); 186 | const uint32_t mask = 0xFFU << pos; 187 | 188 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 189 | return; // invalid index 190 | } 191 | 192 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 193 | } 194 | 195 | /** Set the memory attribute encoding. 196 | * \param idx The attribute index to be set [0-7] 197 | * \param attr The attribute value to be set. 198 | */ 199 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 200 | { 201 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 202 | } 203 | 204 | #ifdef MPU_NS 205 | /** Set the memory attribute encoding to the Non-secure MPU. 206 | * \param idx The attribute index to be set [0-7] 207 | * \param attr The attribute value to be set. 208 | */ 209 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 210 | { 211 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 212 | } 213 | #endif 214 | 215 | /** Clear and disable the given MPU region of the given MPU. 216 | * \param mpu Pointer to MPU to be used. 217 | * \param rnr Region number to be cleared. 218 | */ 219 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 220 | { 221 | mpu->RNR = rnr; 222 | mpu->RLAR = 0U; 223 | } 224 | 225 | /** Clear and disable the given MPU region. 226 | * \param rnr Region number to be cleared. 227 | */ 228 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 229 | { 230 | ARM_MPU_ClrRegionEx(MPU, rnr); 231 | } 232 | 233 | #ifdef MPU_NS 234 | /** Clear and disable the given Non-secure MPU region. 235 | * \param rnr Region number to be cleared. 236 | */ 237 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 238 | { 239 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 240 | } 241 | #endif 242 | 243 | /** Configure the given MPU region of the given MPU. 244 | * \param mpu Pointer to MPU to be used. 245 | * \param rnr Region number to be configured. 246 | * \param rbar Value for RBAR register. 247 | * \param rlar Value for RLAR register. 248 | */ 249 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 250 | { 251 | mpu->RNR = rnr; 252 | mpu->RBAR = rbar; 253 | mpu->RLAR = rlar; 254 | } 255 | 256 | /** Configure the given MPU region. 257 | * \param rnr Region number to be configured. 258 | * \param rbar Value for RBAR register. 259 | * \param rlar Value for RLAR register. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 262 | { 263 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 264 | } 265 | 266 | #ifdef MPU_NS 267 | /** Configure the given Non-secure MPU region. 268 | * \param rnr Region number to be configured. 269 | * \param rbar Value for RBAR register. 270 | * \param rlar Value for RLAR register. 271 | */ 272 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 273 | { 274 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 275 | } 276 | #endif 277 | 278 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 279 | * \param dst Destination data is copied to. 280 | * \param src Source data is copied from. 281 | * \param len Amount of data words to be copied. 282 | */ 283 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 284 | { 285 | uint32_t i; 286 | for (i = 0U; i < len; ++i) 287 | { 288 | dst[i] = src[i]; 289 | } 290 | } 291 | 292 | /** Load the given number of MPU regions from a table to the given MPU. 293 | * \param mpu Pointer to the MPU registers to be used. 294 | * \param rnr First region number to be configured. 295 | * \param table Pointer to the MPU configuration table. 296 | * \param cnt Amount of regions to be configured. 297 | */ 298 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 299 | { 300 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 301 | if (cnt == 1U) { 302 | mpu->RNR = rnr; 303 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 304 | } else { 305 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 306 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 307 | 308 | mpu->RNR = rnrBase; 309 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 310 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 311 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 312 | table += c; 313 | cnt -= c; 314 | rnrOffset = 0U; 315 | rnrBase += MPU_TYPE_RALIASES; 316 | mpu->RNR = rnrBase; 317 | } 318 | 319 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 320 | } 321 | } 322 | 323 | /** Load the given number of MPU regions from a table. 324 | * \param rnr First region number to be configured. 325 | * \param table Pointer to the MPU configuration table. 326 | * \param cnt Amount of regions to be configured. 327 | */ 328 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 329 | { 330 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 331 | } 332 | 333 | #ifdef MPU_NS 334 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 335 | * \param rnr First region number to be configured. 336 | * \param table Pointer to the MPU configuration table. 337 | * \param cnt Amount of regions to be configured. 338 | */ 339 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 340 | { 341 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 342 | } 343 | #endif 344 | 345 | #endif 346 | 347 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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-------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32H7xx_HAL_DEF 22 | #define STM32H7xx_HAL_DEF 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32h7xx.h" 30 | #include "Legacy/stm32_hal_legacy.h" 31 | #include 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00, 42 | HAL_ERROR = 0x01, 43 | HAL_BUSY = 0x02, 44 | HAL_TIMEOUT = 0x03 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00, 53 | HAL_LOCKED = 0x01 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macro ------------------------------------------------------------*/ 57 | 58 | #define HAL_MAX_DELAY 0xFFFFFFFFU 59 | 60 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) 61 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 62 | 63 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 64 | do{ \ 65 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 66 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 67 | } while(0) 68 | 69 | #define UNUSED(x) ((void)(x)) 70 | 71 | /** @brief Reset the Handle's State field. 72 | * @param __HANDLE__: specifies the Peripheral Handle. 73 | * @note This macro can be used for the following purpose: 74 | * - When the Handle is declared as local variable; before passing it as parameter 75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 76 | * to set to 0 the Handle's "State" field. 77 | * Otherwise, "State" field may have any random value and the first time the function 78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 79 | * (i.e. HAL_PPP_MspInit() will not be executed). 80 | * - When there is a need to reconfigure the low level hardware: instead of calling 81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 84 | * @retval None 85 | */ 86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) 87 | 88 | #if (USE_RTOS == 1) 89 | #error " USE_RTOS should be 0 in the current HAL release " 90 | #else 91 | #define __HAL_LOCK(__HANDLE__) \ 92 | do{ \ 93 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 94 | { \ 95 | return HAL_BUSY; \ 96 | } \ 97 | else \ 98 | { \ 99 | (__HANDLE__)->Lock = HAL_LOCKED; \ 100 | } \ 101 | }while (0) 102 | 103 | #define __HAL_UNLOCK(__HANDLE__) \ 104 | do{ \ 105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 106 | }while (0) 107 | #endif /* USE_RTOS */ 108 | 109 | 110 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 111 | #ifndef __weak 112 | #define __weak __attribute__((weak)) 113 | #endif 114 | #ifndef __packed 115 | #define __packed __attribute__((packed)) 116 | #endif 117 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 118 | #ifndef __weak 119 | #define __weak __attribute__((weak)) 120 | #endif /* __weak */ 121 | #ifndef __packed 122 | #define __packed __attribute__((__packed__)) 123 | #endif /* __packed */ 124 | #endif /* __GNUC__ */ 125 | 126 | 127 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 128 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 129 | #ifndef __ALIGN_BEGIN 130 | #define __ALIGN_BEGIN 131 | #endif 132 | #ifndef __ALIGN_END 133 | #define __ALIGN_END __attribute__ ((aligned (4))) 134 | #endif 135 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 136 | #ifndef __ALIGN_END 137 | #define __ALIGN_END __attribute__ ((aligned (4))) 138 | #endif /* __ALIGN_END */ 139 | #ifndef __ALIGN_BEGIN 140 | #define __ALIGN_BEGIN 141 | #endif /* __ALIGN_BEGIN */ 142 | #else 143 | #ifndef __ALIGN_END 144 | #define __ALIGN_END 145 | #endif /* __ALIGN_END */ 146 | #ifndef __ALIGN_BEGIN 147 | #if defined (__CC_ARM) /* ARM Compiler V5 */ 148 | #define __ALIGN_BEGIN __align(4) 149 | #elif defined (__ICCARM__) /* IAR Compiler */ 150 | #define __ALIGN_BEGIN 151 | #endif /* __CC_ARM */ 152 | #endif /* __ALIGN_BEGIN */ 153 | #endif /* __GNUC__ */ 154 | 155 | /* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ 156 | #if defined (__GNUC__) /* GNU Compiler */ 157 | #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) 158 | #elif defined (__ICCARM__) /* IAR Compiler */ 159 | #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf 160 | #elif defined (__CC_ARM) /* ARM Compiler */ 161 | #define ALIGN_32BYTES(buf) __align(32) buf 162 | #endif 163 | 164 | /** 165 | * @brief __RAM_FUNC definition 166 | */ 167 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 168 | /* ARM Compiler V4/V5 and V6 169 | -------------------------- 170 | RAM functions are defined using the toolchain options. 171 | Functions that are executed in RAM should reside in a separate source module. 172 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 173 | area of a module to a memory space in physical RAM. 174 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 175 | dialog. 176 | */ 177 | #define __RAM_FUNC 178 | 179 | #elif defined ( __ICCARM__ ) 180 | /* ICCARM Compiler 181 | --------------- 182 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 183 | */ 184 | #define __RAM_FUNC __ramfunc 185 | 186 | #elif defined ( __GNUC__ ) 187 | /* GNU Compiler 188 | ------------ 189 | RAM functions are defined using a specific toolchain attribute 190 | "__attribute__((section(".RamFunc")))". 191 | */ 192 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 193 | 194 | #endif 195 | 196 | /** 197 | * @brief __NOINLINE definition 198 | */ 199 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 200 | /* ARM V4/V5 and V6 & GNU Compiler 201 | ------------------------------- 202 | */ 203 | #define __NOINLINE __attribute__ ( (noinline) ) 204 | 205 | #elif defined ( __ICCARM__ ) 206 | /* ICCARM Compiler 207 | --------------- 208 | */ 209 | #define __NOINLINE _Pragma("optimize = no_inline") 210 | 211 | #endif 212 | 213 | 214 | #ifdef __cplusplus 215 | } 216 | #endif 217 | 218 | #endif /* STM32H7xx_HAL_DEF */ 219 | 220 | 221 | -------------------------------------------------------------------------------- /Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_gpio.h 4 | * @author MCD Application Team 5 | * @brief Header file of GPIO HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32H7xx_HAL_GPIO_H 21 | #define STM32H7xx_HAL_GPIO_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32h7xx_hal_def.h" 29 | 30 | /** @addtogroup STM32H7xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup GPIO 35 | * @{ 36 | */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /** @defgroup GPIO_Exported_Types GPIO Exported Types 40 | * @{ 41 | */ 42 | 43 | /** 44 | * @brief GPIO Init structure definition 45 | */ 46 | typedef struct 47 | { 48 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 49 | This parameter can be any value of @ref GPIO_pins_define */ 50 | 51 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 52 | This parameter can be a value of @ref GPIO_mode_define */ 53 | 54 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. 55 | This parameter can be a value of @ref GPIO_pull_define */ 56 | 57 | uint32_t Speed; /*!< Specifies the speed for the selected pins. 58 | This parameter can be a value of @ref GPIO_speed_define */ 59 | 60 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. 61 | This parameter can be a value of @ref GPIO_Alternate_function_selection */ 62 | } GPIO_InitTypeDef; 63 | 64 | /** 65 | * @brief GPIO Bit SET and Bit RESET enumeration 66 | */ 67 | typedef enum 68 | { 69 | GPIO_PIN_RESET = 0U, 70 | GPIO_PIN_SET 71 | } GPIO_PinState; 72 | /** 73 | * @} 74 | */ 75 | 76 | /* Exported constants --------------------------------------------------------*/ 77 | 78 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants 79 | * @{ 80 | */ 81 | 82 | /** @defgroup GPIO_pins_define GPIO pins define 83 | * @{ 84 | */ 85 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ 86 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ 87 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ 88 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ 89 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ 90 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ 91 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ 92 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ 93 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ 94 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ 95 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ 96 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ 97 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ 98 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ 99 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ 100 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ 101 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ 102 | 103 | #define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ 104 | /** 105 | * @} 106 | */ 107 | 108 | /** @defgroup GPIO_mode_define GPIO mode define 109 | * @brief GPIO Configuration Mode 110 | * Elements values convention: 0x00WX00YZ 111 | * - W : EXTI trigger detection on 3 bits 112 | * - X : EXTI mode (IT or Event) on 2 bits 113 | * - Y : Output type (Push Pull or Open Drain) on 1 bit 114 | * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits 115 | * @{ 116 | */ 117 | #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ 118 | #define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ 119 | #define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ 120 | #define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ 121 | #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ 122 | #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ 123 | #define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ 124 | #define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ 125 | #define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 126 | 127 | #define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ 128 | #define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ 129 | #define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ 130 | /** 131 | * @} 132 | */ 133 | 134 | /** @defgroup GPIO_speed_define GPIO speed define 135 | * @brief GPIO Output Maximum frequency 136 | * @{ 137 | */ 138 | #define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ 139 | #define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ 140 | #define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< Fast speed */ 141 | #define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< High speed */ 142 | /** 143 | * @} 144 | */ 145 | 146 | /** @defgroup GPIO_pull_define GPIO pull define 147 | * @brief GPIO Pull-Up or Pull-Down Activation 148 | * @{ 149 | */ 150 | #define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ 151 | #define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ 152 | #define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ 153 | /** 154 | * @} 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /* Exported macro ------------------------------------------------------------*/ 162 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros 163 | * @{ 164 | */ 165 | 166 | /** 167 | * @brief Checks whether the specified EXTI line flag is set or not. 168 | * @param __EXTI_LINE__: specifies the EXTI line flag to check. 169 | * This parameter can be GPIO_PIN_x where x can be(0..15) 170 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 171 | */ 172 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) 173 | 174 | /** 175 | * @brief Clears the EXTI's line pending flags. 176 | * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. 177 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 178 | * @retval None 179 | */ 180 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) 181 | 182 | /** 183 | * @brief Checks whether the specified EXTI line is asserted or not. 184 | * @param __EXTI_LINE__: specifies the EXTI line to check. 185 | * This parameter can be GPIO_PIN_x where x can be(0..15) 186 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 187 | */ 188 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) 189 | 190 | /** 191 | * @brief Clears the EXTI's line pending bits. 192 | * @param __EXTI_LINE__: specifies the EXTI lines to clear. 193 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 194 | * @retval None 195 | */ 196 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) 197 | 198 | #if defined(DUAL_CORE) 199 | /** 200 | * @brief Checks whether the specified EXTI line flag is set or not. 201 | * @param __EXTI_LINE__: specifies the EXTI line flag to check. 202 | * This parameter can be GPIO_PIN_x where x can be(0..15) 203 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 204 | */ 205 | #define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) 206 | 207 | /** 208 | * @brief Clears the EXTI's line pending flags. 209 | * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. 210 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 211 | * @retval None 212 | */ 213 | #define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) 214 | 215 | /** 216 | * @brief Checks whether the specified EXTI line is asserted or not. 217 | * @param __EXTI_LINE__: specifies the EXTI line to check. 218 | * This parameter can be GPIO_PIN_x where x can be(0..15) 219 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 220 | */ 221 | #define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) 222 | 223 | /** 224 | * @brief Clears the EXTI's line pending bits. 225 | * @param __EXTI_LINE__: specifies the EXTI lines to clear. 226 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 227 | * @retval None 228 | */ 229 | #define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) 230 | #endif 231 | 232 | /** 233 | * @brief Generates a Software interrupt on selected EXTI line. 234 | * @param __EXTI_LINE__: specifies the EXTI line to check. 235 | * This parameter can be GPIO_PIN_x where x can be(0..15) 236 | * @retval None 237 | */ 238 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) 239 | /** 240 | * @} 241 | */ 242 | 243 | /* Include GPIO HAL Extension module */ 244 | #include "stm32h7xx_hal_gpio_ex.h" 245 | 246 | /* Exported functions --------------------------------------------------------*/ 247 | /** @addtogroup GPIO_Exported_Functions 248 | * @{ 249 | */ 250 | 251 | /** @addtogroup GPIO_Exported_Functions_Group1 252 | * @{ 253 | */ 254 | /* Initialization and de-initialization functions *****************************/ 255 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); 256 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); 257 | /** 258 | * @} 259 | */ 260 | 261 | /** @addtogroup GPIO_Exported_Functions_Group2 262 | * @{ 263 | */ 264 | /* IO operation functions *****************************************************/ 265 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 266 | void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); 267 | void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 268 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 269 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); 270 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); 271 | 272 | /** 273 | * @} 274 | */ 275 | 276 | /** 277 | * @} 278 | */ 279 | /* Private types -------------------------------------------------------------*/ 280 | /* Private variables ---------------------------------------------------------*/ 281 | /* Private constants ---------------------------------------------------------*/ 282 | /** @defgroup GPIO_Private_Constants GPIO Private Constants 283 | * @{ 284 | */ 285 | #define GPIO_MODE_Pos 0u 286 | #define GPIO_MODE (0x3uL << GPIO_MODE_Pos) 287 | #define MODE_INPUT (0x0uL << GPIO_MODE_Pos) 288 | #define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) 289 | #define MODE_AF (0x2uL << GPIO_MODE_Pos) 290 | #define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) 291 | #define OUTPUT_TYPE_Pos 4u 292 | #define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) 293 | #define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) 294 | #define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) 295 | #define EXTI_MODE_Pos 16u 296 | #define EXTI_MODE (0x3uL << EXTI_MODE_Pos) 297 | #define EXTI_IT (0x1uL << EXTI_MODE_Pos) 298 | #define EXTI_EVT (0x2uL << EXTI_MODE_Pos) 299 | #define TRIGGER_MODE_Pos 20u 300 | #define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) 301 | #define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) 302 | #define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) 303 | #define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) 304 | /** 305 | * @} 306 | */ 307 | 308 | /* Private macros ------------------------------------------------------------*/ 309 | /** @defgroup GPIO_Private_Macros GPIO Private Macros 310 | * @{ 311 | */ 312 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) 313 | #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ 314 | (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) 315 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ 316 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ 317 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ 318 | ((MODE) == GPIO_MODE_AF_PP) ||\ 319 | ((MODE) == GPIO_MODE_AF_OD) ||\ 320 | ((MODE) == GPIO_MODE_IT_RISING) ||\ 321 | ((MODE) == GPIO_MODE_IT_FALLING) ||\ 322 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ 323 | ((MODE) == GPIO_MODE_EVT_RISING) ||\ 324 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\ 325 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ 326 | ((MODE) == GPIO_MODE_ANALOG)) 327 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ 328 | ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) 329 | 330 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ 331 | ((PULL) == GPIO_PULLDOWN)) 332 | 333 | /** 334 | * @} 335 | */ 336 | 337 | /* Private functions ---------------------------------------------------------*/ 338 | /** @defgroup GPIO_Private_Functions GPIO Private Functions 339 | * @{ 340 | */ 341 | 342 | /** 343 | * @} 344 | */ 345 | 346 | /** 347 | * @} 348 | */ 349 | 350 | /** 351 | * @} 352 | */ 353 | 354 | #ifdef __cplusplus 355 | } 356 | #endif 357 | 358 | #endif /* STM32H7xx_HAL_GPIO_H */ 359 | 360 | -------------------------------------------------------------------------------- /Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_hsem.h 4 | * @author MCD Application Team 5 | * @brief Header file of HSEM HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32H7xx_HAL_HSEM_H 21 | #define STM32H7xx_HAL_HSEM_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32h7xx_hal_def.h" 29 | 30 | /** @addtogroup STM32H7xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup HSEM 35 | * @{ 36 | */ 37 | 38 | /* Exported macro ------------------------------------------------------------*/ 39 | /** @defgroup HSEM_Exported_Macros HSEM Exported Macros 40 | * @{ 41 | */ 42 | 43 | /** 44 | * @brief SemID to mask helper Macro. 45 | * @param __SEMID__: semaphore ID from 0 to 31 46 | * @retval Semaphore Mask. 47 | */ 48 | #define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) 49 | 50 | /** 51 | * @brief Enables the specified HSEM interrupts. 52 | * @param __SEM_MASK__: semaphores Mask 53 | * @retval None. 54 | */ 55 | #if defined(DUAL_CORE) 56 | #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 57 | (HSEM->C1IER |= (__SEM_MASK__)) : \ 58 | (HSEM->C2IER |= (__SEM_MASK__))) 59 | #else 60 | #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) 61 | #endif /* DUAL_CORE */ 62 | /** 63 | * @brief Disables the specified HSEM interrupts. 64 | * @param __SEM_MASK__: semaphores Mask 65 | * @retval None. 66 | */ 67 | #if defined(DUAL_CORE) 68 | #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 69 | (HSEM->C1IER &= ~(__SEM_MASK__)) : \ 70 | (HSEM->C2IER &= ~(__SEM_MASK__))) 71 | #else 72 | #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) 73 | #endif /* DUAL_CORE */ 74 | 75 | /** 76 | * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask. 77 | * @param __SEM_MASK__: semaphores Mask 78 | * @retval semaphores Mask : Semaphores where an interrupt occurred. 79 | */ 80 | #if defined(DUAL_CORE) 81 | #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 82 | ((__SEM_MASK__) & HSEM->C1MISR) : \ 83 | ((__SEM_MASK__) & HSEM->C2MISR1)) 84 | #else 85 | #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) 86 | #endif /* DUAL_CORE */ 87 | 88 | /** 89 | * @brief Get the semaphores release status flags. 90 | * @param __SEM_MASK__: semaphores Mask 91 | * @retval semaphores Mask : Semaphores where Release flags rise. 92 | */ 93 | #if defined(DUAL_CORE) 94 | #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 95 | (__SEM_MASK__) & HSEM->C1ISR : \ 96 | (__SEM_MASK__) & HSEM->C2ISR) 97 | #else 98 | #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) 99 | #endif /* DUAL_CORE */ 100 | 101 | /** 102 | * @brief Clears the HSEM Interrupt flags. 103 | * @param __SEM_MASK__: semaphores Mask 104 | * @retval None. 105 | */ 106 | #if defined(DUAL_CORE) 107 | #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 108 | (HSEM->C1ICR |= (__SEM_MASK__)) : \ 109 | (HSEM->C2ICR |= (__SEM_MASK__))) 110 | #else 111 | #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) 112 | #endif /* DUAL_CORE */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /* Exported functions --------------------------------------------------------*/ 119 | /** @defgroup HSEM_Exported_Functions HSEM Exported Functions 120 | * @{ 121 | */ 122 | 123 | /** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions 124 | * @brief HSEM Take and Release functions 125 | * @{ 126 | */ 127 | 128 | /* HSEM semaphore take (lock) using 2-Step method ****************************/ 129 | HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); 130 | /* HSEM semaphore fast take (lock) using 1-Step method ***********************/ 131 | HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); 132 | /* HSEM Release **************************************************************/ 133 | void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); 134 | /* HSEM Release All************************************************************/ 135 | void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); 136 | /* HSEM Check semaphore state Taken or not **********************************/ 137 | uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); 138 | 139 | /** 140 | * @} 141 | */ 142 | 143 | /** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions 144 | * @brief HSEM Set and Get Key functions. 145 | * @{ 146 | */ 147 | /* HSEM Set Clear Key *********************************************************/ 148 | void HAL_HSEM_SetClearKey(uint32_t Key); 149 | /* HSEM Get Clear Key *********************************************************/ 150 | uint32_t HAL_HSEM_GetClearKey(void); 151 | /** 152 | * @} 153 | */ 154 | 155 | /** @addtogroup HSEM_Exported_Functions_Group3 156 | * @brief HSEM Notification functions 157 | * @{ 158 | */ 159 | /* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/ 160 | void HAL_HSEM_ActivateNotification(uint32_t SemMask); 161 | /* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/ 162 | void HAL_HSEM_DeactivateNotification(uint32_t SemMask); 163 | /* HSEM Free Callback (When a semaphore is released) *******************************/ 164 | void HAL_HSEM_FreeCallback(uint32_t SemMask); 165 | /* HSEM IRQ Handler **********************************************************/ 166 | void HAL_HSEM_IRQHandler(void); 167 | 168 | /** 169 | * @} 170 | */ 171 | 172 | /** 173 | * @} 174 | */ 175 | 176 | /* Private macros ------------------------------------------------------------*/ 177 | /** @defgroup HSEM_Private_Macros HSEM Private Macros 178 | * @{ 179 | */ 180 | 181 | #define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) 182 | 183 | #define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) 184 | 185 | #define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) 186 | 187 | #if defined(DUAL_CORE) 188 | #define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \ 189 | ((__COREID__) == HSEM_CPU2_COREID)) 190 | #else 191 | #define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID) 192 | #endif 193 | 194 | 195 | /** 196 | * @} 197 | */ 198 | 199 | /** 200 | * @} 201 | */ 202 | 203 | /** 204 | * @} 205 | */ 206 | 207 | #ifdef __cplusplus 208 | } 209 | #endif 210 | 211 | #endif /* STM32H7xx_HAL_HSEM_H */ 212 | -------------------------------------------------------------------------------- /Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_i2c_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of I2C HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32H7xx_HAL_I2C_EX_H 21 | #define STM32H7xx_HAL_I2C_EX_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32h7xx_hal_def.h" 29 | 30 | /** @addtogroup STM32H7xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup I2CEx 35 | * @{ 36 | */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* Exported constants --------------------------------------------------------*/ 40 | /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants 41 | * @{ 42 | */ 43 | 44 | /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter 45 | * @{ 46 | */ 47 | #define I2C_ANALOGFILTER_ENABLE 0x00000000U 48 | #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 49 | /** 50 | * @} 51 | */ 52 | 53 | /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus 54 | * @{ 55 | */ 56 | #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ 57 | #define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 58 | #define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 59 | #define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 60 | #define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 61 | #define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ 62 | #define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ 63 | #define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ 64 | #define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ 65 | #if defined(SYSCFG_PMCR_I2C5_FMP) 66 | #define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ 67 | #else 68 | #define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ 69 | #endif /* SYSCFG_PMCR_I2C5_FMP */ 70 | /** 71 | * @} 72 | */ 73 | 74 | /** 75 | * @} 76 | */ 77 | 78 | /* Exported macro ------------------------------------------------------------*/ 79 | /** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /* Exported functions --------------------------------------------------------*/ 88 | /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions 89 | * @{ 90 | */ 91 | 92 | /** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions 93 | * @{ 94 | */ 95 | /* Peripheral Control functions ************************************************/ 96 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); 97 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); 98 | /** 99 | * @} 100 | */ 101 | 102 | /** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions 103 | * @{ 104 | */ 105 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); 106 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions 112 | * @{ 113 | */ 114 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); 115 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); 116 | /** 117 | * @} 118 | */ 119 | 120 | /** 121 | * @} 122 | */ 123 | 124 | /* Private constants ---------------------------------------------------------*/ 125 | /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants 126 | * @{ 127 | */ 128 | 129 | /** 130 | * @} 131 | */ 132 | 133 | /* Private macros ------------------------------------------------------------*/ 134 | /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros 135 | * @{ 136 | */ 137 | #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ 138 | ((FILTER) == I2C_ANALOGFILTER_DISABLE)) 139 | 140 | #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 141 | 142 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ 143 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ 144 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ 145 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ 146 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ 147 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ 148 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ 149 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) 150 | /** 151 | * @} 152 | */ 153 | 154 | /* Private Functions ---------------------------------------------------------*/ 155 | /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions 156 | * @{ 157 | */ 158 | /* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */ 159 | /** 160 | * @} 161 | */ 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /** 168 | * @} 169 | */ 170 | 171 | #ifdef __cplusplus 172 | } 173 | #endif 174 | 175 | #endif /* STM32H7xx_HAL_I2C_EX_H */ 176 | -------------------------------------------------------------------------------- /Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_usart_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of USART HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32H7xx_HAL_USART_EX_H 22 | #define STM32H7xx_HAL_USART_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32h7xx_hal_def.h" 30 | 31 | /** @addtogroup STM32H7xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup USARTEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup USARTEx_Word_Length USARTEx Word Length 46 | * @{ 47 | */ 48 | #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ 49 | #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ 50 | #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ 51 | /** 52 | * @} 53 | */ 54 | 55 | /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management 56 | * @{ 57 | */ 58 | #define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ 59 | #define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ 60 | /** 61 | * @} 62 | */ 63 | 64 | 65 | /** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable 66 | * @brief USART SLAVE mode 67 | * @{ 68 | */ 69 | #define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ 70 | #define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode 76 | * @brief USART FIFO mode 77 | * @{ 78 | */ 79 | #define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 80 | #define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level 86 | * @brief USART TXFIFO level 87 | * @{ 88 | */ 89 | #define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ 90 | #define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ 91 | #define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ 92 | #define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ 93 | #define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ 94 | #define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level 100 | * @brief USART RXFIFO level 101 | * @{ 102 | */ 103 | #define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ 104 | #define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ 105 | #define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ 106 | #define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ 107 | #define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ 108 | #define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /* Private macros ------------------------------------------------------------*/ 118 | /** @defgroup USARTEx_Private_Macros USARTEx Private Macros 119 | * @{ 120 | */ 121 | 122 | /** @brief Compute the USART mask to apply to retrieve the received data 123 | * according to the word length and to the parity bits activation. 124 | * @note If PCE = 1, the parity bit is not included in the data extracted 125 | * by the reception API(). 126 | * This masking operation is not carried out in the case of 127 | * DMA transfers. 128 | * @param __HANDLE__ specifies the USART Handle. 129 | * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. 130 | */ 131 | #define USART_MASK_COMPUTATION(__HANDLE__) \ 132 | do { \ 133 | if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ 134 | { \ 135 | if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ 136 | { \ 137 | (__HANDLE__)->Mask = 0x01FFU; \ 138 | } \ 139 | else \ 140 | { \ 141 | (__HANDLE__)->Mask = 0x00FFU; \ 142 | } \ 143 | } \ 144 | else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ 145 | { \ 146 | if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ 147 | { \ 148 | (__HANDLE__)->Mask = 0x00FFU; \ 149 | } \ 150 | else \ 151 | { \ 152 | (__HANDLE__)->Mask = 0x007FU; \ 153 | } \ 154 | } \ 155 | else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ 156 | { \ 157 | if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ 158 | { \ 159 | (__HANDLE__)->Mask = 0x007FU; \ 160 | } \ 161 | else \ 162 | { \ 163 | (__HANDLE__)->Mask = 0x003FU; \ 164 | } \ 165 | } \ 166 | else \ 167 | { \ 168 | (__HANDLE__)->Mask = 0x0000U; \ 169 | } \ 170 | } while(0U) 171 | 172 | /** 173 | * @brief Ensure that USART frame length is valid. 174 | * @param __LENGTH__ USART frame length. 175 | * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) 176 | */ 177 | #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ 178 | ((__LENGTH__) == USART_WORDLENGTH_8B) || \ 179 | ((__LENGTH__) == USART_WORDLENGTH_9B)) 180 | 181 | /** 182 | * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. 183 | * @param __NSS__ USART Negative Slave Select pin management. 184 | * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) 185 | */ 186 | #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ 187 | ((__NSS__) == USART_NSS_SOFT)) 188 | 189 | /** 190 | * @brief Ensure that USART Slave Mode is valid. 191 | * @param __STATE__ USART Slave Mode. 192 | * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) 193 | */ 194 | #define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ 195 | ((__STATE__) == USART_SLAVEMODE_ENABLE)) 196 | 197 | /** 198 | * @brief Ensure that USART FIFO mode is valid. 199 | * @param __STATE__ USART FIFO mode. 200 | * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) 201 | */ 202 | #define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ 203 | ((__STATE__) == USART_FIFOMODE_ENABLE)) 204 | 205 | /** 206 | * @brief Ensure that USART TXFIFO threshold level is valid. 207 | * @param __THRESHOLD__ USART TXFIFO threshold level. 208 | * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) 209 | */ 210 | #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ 211 | ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ 212 | ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ 213 | ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ 214 | ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ 215 | ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) 216 | 217 | /** 218 | * @brief Ensure that USART RXFIFO threshold level is valid. 219 | * @param __THRESHOLD__ USART RXFIFO threshold level. 220 | * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) 221 | */ 222 | #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ 223 | ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ 224 | ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ 225 | ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ 226 | ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ 227 | ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) 228 | /** 229 | * @} 230 | */ 231 | 232 | /* Exported functions --------------------------------------------------------*/ 233 | /** @addtogroup USARTEx_Exported_Functions 234 | * @{ 235 | */ 236 | 237 | /** @addtogroup USARTEx_Exported_Functions_Group1 238 | * @{ 239 | */ 240 | 241 | /* IO operation functions *****************************************************/ 242 | void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); 243 | void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); 244 | 245 | /** 246 | * @} 247 | */ 248 | 249 | /** @addtogroup USARTEx_Exported_Functions_Group2 250 | * @{ 251 | */ 252 | 253 | /* Peripheral Control functions ***********************************************/ 254 | HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); 255 | HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); 256 | HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); 257 | HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); 258 | HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); 259 | HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); 260 | HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); 261 | 262 | /** 263 | * @} 264 | */ 265 | 266 | /** 267 | * @} 268 | */ 269 | 270 | /** 271 | * @} 272 | */ 273 | 274 | /** 275 | * @} 276 | */ 277 | 278 | #ifdef __cplusplus 279 | } 280 | #endif 281 | 282 | #endif /* STM32H7xx_HAL_USART_EX_H */ 283 | 284 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 285 | -------------------------------------------------------------------------------- /Drivers/STM32H7xx_HAL_Driver/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the BSD-3-Clause license shall apply. 5 | You may obtain a copy of the BSD-3-Clause at: 6 | https://opensource.org/licenses/BSD-3-Clause 7 | -------------------------------------------------------------------------------- /Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_i2c_ex.c 4 | * @author MCD Application Team 5 | * @brief I2C Extended HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of I2C Extended peripheral: 8 | * + Filter Mode Functions 9 | * + WakeUp Mode Functions 10 | * + FastModePlus Functions 11 | * 12 | ****************************************************************************** 13 | * @attention 14 | * 15 | * Copyright (c) 2017 STMicroelectronics. 16 | * All rights reserved. 17 | * 18 | * This software is licensed under terms that can be found in the LICENSE file 19 | * in the root directory of this software component. 20 | * If no LICENSE file comes with this software, it is provided AS-IS. 21 | * 22 | ****************************************************************************** 23 | @verbatim 24 | ============================================================================== 25 | ##### I2C peripheral Extended features ##### 26 | ============================================================================== 27 | 28 | [..] Comparing to other previous devices, the I2C interface for STM32H7xx 29 | devices contains the following additional features 30 | 31 | (+) Possibility to disable or enable Analog Noise Filter 32 | (+) Use of a configured Digital Noise Filter 33 | (+) Disable or enable wakeup from Stop mode(s) 34 | (+) Disable or enable Fast Mode Plus 35 | 36 | ##### How to use this driver ##### 37 | ============================================================================== 38 | [..] This driver provides functions to configure Noise Filter and Wake Up Feature 39 | (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() 40 | (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() 41 | (#) Configure the enable or disable of I2C Wake Up Mode using the functions : 42 | (++) HAL_I2CEx_EnableWakeUp() 43 | (++) HAL_I2CEx_DisableWakeUp() 44 | (#) Configure the enable or disable of fast mode plus driving capability using the functions : 45 | (++) HAL_I2CEx_EnableFastModePlus() 46 | (++) HAL_I2CEx_DisableFastModePlus() 47 | @endverbatim 48 | */ 49 | 50 | /* Includes ------------------------------------------------------------------*/ 51 | #include "stm32h7xx_hal.h" 52 | 53 | /** @addtogroup STM32H7xx_HAL_Driver 54 | * @{ 55 | */ 56 | 57 | /** @defgroup I2CEx I2CEx 58 | * @brief I2C Extended HAL module driver 59 | * @{ 60 | */ 61 | 62 | #ifdef HAL_I2C_MODULE_ENABLED 63 | 64 | /* Private typedef -----------------------------------------------------------*/ 65 | /* Private define ------------------------------------------------------------*/ 66 | /* Private macro -------------------------------------------------------------*/ 67 | /* Private variables ---------------------------------------------------------*/ 68 | /* Private function prototypes -----------------------------------------------*/ 69 | /* Private functions ---------------------------------------------------------*/ 70 | 71 | /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions 72 | * @{ 73 | */ 74 | 75 | /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions 76 | * @brief Filter Mode Functions 77 | * 78 | @verbatim 79 | =============================================================================== 80 | ##### Filter Mode Functions ##### 81 | =============================================================================== 82 | [..] This section provides functions allowing to: 83 | (+) Configure Noise Filters 84 | 85 | @endverbatim 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @brief Configure I2C Analog noise filter. 91 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 92 | * the configuration information for the specified I2Cx peripheral. 93 | * @param AnalogFilter New state of the Analog filter. 94 | * @retval HAL status 95 | */ 96 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) 97 | { 98 | /* Check the parameters */ 99 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 100 | assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); 101 | 102 | if (hi2c->State == HAL_I2C_STATE_READY) 103 | { 104 | /* Process Locked */ 105 | __HAL_LOCK(hi2c); 106 | 107 | hi2c->State = HAL_I2C_STATE_BUSY; 108 | 109 | /* Disable the selected I2C peripheral */ 110 | __HAL_I2C_DISABLE(hi2c); 111 | 112 | /* Reset I2Cx ANOFF bit */ 113 | hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 114 | 115 | /* Set analog filter bit*/ 116 | hi2c->Instance->CR1 |= AnalogFilter; 117 | 118 | __HAL_I2C_ENABLE(hi2c); 119 | 120 | hi2c->State = HAL_I2C_STATE_READY; 121 | 122 | /* Process Unlocked */ 123 | __HAL_UNLOCK(hi2c); 124 | 125 | return HAL_OK; 126 | } 127 | else 128 | { 129 | return HAL_BUSY; 130 | } 131 | } 132 | 133 | /** 134 | * @brief Configure I2C Digital noise filter. 135 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 136 | * the configuration information for the specified I2Cx peripheral. 137 | * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. 138 | * @retval HAL status 139 | */ 140 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) 141 | { 142 | uint32_t tmpreg; 143 | 144 | /* Check the parameters */ 145 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 146 | assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); 147 | 148 | if (hi2c->State == HAL_I2C_STATE_READY) 149 | { 150 | /* Process Locked */ 151 | __HAL_LOCK(hi2c); 152 | 153 | hi2c->State = HAL_I2C_STATE_BUSY; 154 | 155 | /* Disable the selected I2C peripheral */ 156 | __HAL_I2C_DISABLE(hi2c); 157 | 158 | /* Get the old register value */ 159 | tmpreg = hi2c->Instance->CR1; 160 | 161 | /* Reset I2Cx DNF bits [11:8] */ 162 | tmpreg &= ~(I2C_CR1_DNF); 163 | 164 | /* Set I2Cx DNF coefficient */ 165 | tmpreg |= DigitalFilter << 8U; 166 | 167 | /* Store the new register value */ 168 | hi2c->Instance->CR1 = tmpreg; 169 | 170 | __HAL_I2C_ENABLE(hi2c); 171 | 172 | hi2c->State = HAL_I2C_STATE_READY; 173 | 174 | /* Process Unlocked */ 175 | __HAL_UNLOCK(hi2c); 176 | 177 | return HAL_OK; 178 | } 179 | else 180 | { 181 | return HAL_BUSY; 182 | } 183 | } 184 | /** 185 | * @} 186 | */ 187 | 188 | /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions 189 | * @brief WakeUp Mode Functions 190 | * 191 | @verbatim 192 | =============================================================================== 193 | ##### WakeUp Mode Functions ##### 194 | =============================================================================== 195 | [..] This section provides functions allowing to: 196 | (+) Configure Wake Up Feature 197 | 198 | @endverbatim 199 | * @{ 200 | */ 201 | 202 | /** 203 | * @brief Enable I2C wakeup from Stop mode(s). 204 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 205 | * the configuration information for the specified I2Cx peripheral. 206 | * @retval HAL status 207 | */ 208 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) 209 | { 210 | /* Check the parameters */ 211 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 212 | 213 | if (hi2c->State == HAL_I2C_STATE_READY) 214 | { 215 | /* Process Locked */ 216 | __HAL_LOCK(hi2c); 217 | 218 | hi2c->State = HAL_I2C_STATE_BUSY; 219 | 220 | /* Disable the selected I2C peripheral */ 221 | __HAL_I2C_DISABLE(hi2c); 222 | 223 | /* Enable wakeup from stop mode */ 224 | hi2c->Instance->CR1 |= I2C_CR1_WUPEN; 225 | 226 | __HAL_I2C_ENABLE(hi2c); 227 | 228 | hi2c->State = HAL_I2C_STATE_READY; 229 | 230 | /* Process Unlocked */ 231 | __HAL_UNLOCK(hi2c); 232 | 233 | return HAL_OK; 234 | } 235 | else 236 | { 237 | return HAL_BUSY; 238 | } 239 | } 240 | 241 | /** 242 | * @brief Disable I2C wakeup from Stop mode(s). 243 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 244 | * the configuration information for the specified I2Cx peripheral. 245 | * @retval HAL status 246 | */ 247 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) 248 | { 249 | /* Check the parameters */ 250 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 251 | 252 | if (hi2c->State == HAL_I2C_STATE_READY) 253 | { 254 | /* Process Locked */ 255 | __HAL_LOCK(hi2c); 256 | 257 | hi2c->State = HAL_I2C_STATE_BUSY; 258 | 259 | /* Disable the selected I2C peripheral */ 260 | __HAL_I2C_DISABLE(hi2c); 261 | 262 | /* Enable wakeup from stop mode */ 263 | hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); 264 | 265 | __HAL_I2C_ENABLE(hi2c); 266 | 267 | hi2c->State = HAL_I2C_STATE_READY; 268 | 269 | /* Process Unlocked */ 270 | __HAL_UNLOCK(hi2c); 271 | 272 | return HAL_OK; 273 | } 274 | else 275 | { 276 | return HAL_BUSY; 277 | } 278 | } 279 | /** 280 | * @} 281 | */ 282 | 283 | /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions 284 | * @brief Fast Mode Plus Functions 285 | * 286 | @verbatim 287 | =============================================================================== 288 | ##### Fast Mode Plus Functions ##### 289 | =============================================================================== 290 | [..] This section provides functions allowing to: 291 | (+) Configure Fast Mode Plus 292 | 293 | @endverbatim 294 | * @{ 295 | */ 296 | 297 | /** 298 | * @brief Enable the I2C fast mode plus driving capability. 299 | * @param ConfigFastModePlus Selects the pin. 300 | * This parameter can be one of the @ref I2CEx_FastModePlus values 301 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected 302 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 303 | * on each one of the following pins PB6, PB7, PB8 and PB9. 304 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 305 | * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 306 | * @note For all I2C2 pins fast mode plus driving capability can be enabled 307 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 308 | * @note For all I2C3 pins fast mode plus driving capability can be enabled 309 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 310 | * @note For all I2C4 pins fast mode plus driving capability can be enabled 311 | * only by using I2C_FASTMODEPLUS_I2C4 parameter. 312 | * @note For all I2C5 pins fast mode plus driving capability can be enabled 313 | * only by using I2C_FASTMODEPLUS_I2C5 parameter. 314 | * @retval None 315 | */ 316 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) 317 | { 318 | /* Check the parameter */ 319 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 320 | 321 | /* Enable SYSCFG clock */ 322 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 323 | 324 | /* Enable fast mode plus driving capability for selected pin */ 325 | SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); 326 | } 327 | 328 | /** 329 | * @brief Disable the I2C fast mode plus driving capability. 330 | * @param ConfigFastModePlus Selects the pin. 331 | * This parameter can be one of the @ref I2CEx_FastModePlus values 332 | * @note For I2C1, fast mode plus driving capability can be disabled on all selected 333 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 334 | * on each one of the following pins PB6, PB7, PB8 and PB9. 335 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 336 | * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 337 | * @note For all I2C2 pins fast mode plus driving capability can be disabled 338 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 339 | * @note For all I2C3 pins fast mode plus driving capability can be disabled 340 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 341 | * @note For all I2C4 pins fast mode plus driving capability can be disabled 342 | * only by using I2C_FASTMODEPLUS_I2C4 parameter. 343 | * @note For all I2C5 pins fast mode plus driving capability can be disabled 344 | * only by using I2C_FASTMODEPLUS_I2C5 parameter. 345 | * @retval None 346 | */ 347 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) 348 | { 349 | /* Check the parameter */ 350 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 351 | 352 | /* Enable SYSCFG clock */ 353 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 354 | 355 | /* Disable fast mode plus driving capability for selected pin */ 356 | CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); 357 | } 358 | /** 359 | * @} 360 | */ 361 | /** 362 | * @} 363 | */ 364 | 365 | #endif /* HAL_I2C_MODULE_ENABLED */ 366 | /** 367 | * @} 368 | */ 369 | 370 | /** 371 | * @} 372 | */ 373 | -------------------------------------------------------------------------------- /MDK-ARM/RTE/_STM32H750XBH_ARTPIQSPI_W25Q64JV/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'STM32H750XBH_ARTPIQSPI_W25Q64JV' 7 | * Target: 'STM32H750XBH_ARTPIQSPI_W25Q64JV' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "stm32h7xx.h" 18 | 19 | 20 | 21 | #endif /* RTE_COMPONENTS_H */ 22 | -------------------------------------------------------------------------------- /MDK-ARM/RTE/_flashalgo/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'flashalgo' 7 | * Target: 'flashalgo' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "stm32h7xx.h" 18 | 19 | 20 | 21 | #endif /* RTE_COMPONENTS_H */ 22 | -------------------------------------------------------------------------------- /MDK-ARM/STM32H750XBH_ARTPIQSPI_W25Q64JV.uvoptx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | *.c 10 | *.s*; *.src; *.a* 11 | *.obj; *.o 12 | *.lib 13 | *.txt; *.h; *.inc; *.md 14 | *.plm 15 | *.cpp; *.cc; *.cxx 16 | 0 17 | 18 | 19 | 20 | 0 21 | 0 22 | 23 | 24 | 25 | STM32H750XBH_ARTPIQSPI_W25Q64JV 26 | 0x4 27 | ARM-ADS 28 | 29 | 12000000 30 | 31 | 1 32 | 1 33 | 0 34 | 1 35 | 0 36 | 37 | 38 | 1 39 | 65535 40 | 0 41 | 0 42 | 0 43 | 44 | 45 | 79 46 | 66 47 | 8 48 | 49 | 50 | 51 | 1 52 | 1 53 | 1 54 | 0 55 | 1 56 | 1 57 | 0 58 | 1 59 | 0 60 | 0 61 | 0 62 | 0 63 | 64 | 65 | 1 66 | 1 67 | 1 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 75 | 76 | 1 77 | 0 78 | 1 79 | 80 | 18 81 | 82 | 0 83 | 1 84 | 1 85 | 1 86 | 1 87 | 1 88 | 1 89 | 1 90 | 1 91 | 1 92 | 1 93 | 1 94 | 1 95 | 1 96 | 0 97 | 1 98 | 1 99 | 1 100 | 1 101 | 0 102 | 0 103 | 1 104 | 0 105 | 0 106 | 0 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | BIN\UL2CM3.DLL 118 | 119 | 120 | 121 | 0 122 | UL2CM3 123 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_128k -FS08000000 -FL020000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM)) 124 | 125 | 126 | 127 | 128 | 0 129 | 130 | 131 | 0 132 | 0 133 | 0 134 | 0 135 | 0 136 | 0 137 | 0 138 | 0 139 | 0 140 | 0 141 | 0 142 | 0 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 0 151 | 0 152 | 0 153 | 0 154 | 0 155 | 156 | 157 | 158 | 0 159 | 0 160 | 0 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 1 171 | 1 172 | 0 173 | 2 174 | 10000000 175 | 176 | 177 | 178 | 179 | 180 | Application/MDK-ARM 181 | 0 182 | 0 183 | 0 184 | 0 185 | 186 | 187 | 188 | Application/User/Core 189 | 1 190 | 0 191 | 0 192 | 0 193 | 194 | 2 195 | 1 196 | 1 197 | 0 198 | 0 199 | 0 200 | ../Core/Src/main.c 201 | main.c 202 | 0 203 | 0 204 | 205 | 206 | 2 207 | 2 208 | 1 209 | 0 210 | 0 211 | 0 212 | ../Core/Src/quadspi.c 213 | quadspi.c 214 | 0 215 | 0 216 | 217 | 218 | 2 219 | 3 220 | 1 221 | 0 222 | 0 223 | 0 224 | ../Core/Src/stm32h7xx_it.c 225 | stm32h7xx_it.c 226 | 0 227 | 0 228 | 229 | 230 | 2 231 | 4 232 | 1 233 | 0 234 | 0 235 | 0 236 | ../Core/Src/stm32h7xx_hal_msp.c 237 | stm32h7xx_hal_msp.c 238 | 0 239 | 0 240 | 241 | 242 | 2 243 | 5 244 | 1 245 | 0 246 | 0 247 | 0 248 | ..\Dev_Inf.c 249 | Dev_Inf.c 250 | 0 251 | 0 252 | 253 | 254 | 2 255 | 6 256 | 1 257 | 0 258 | 0 259 | 0 260 | ..\Loader_Src.c 261 | Loader_Src.c 262 | 0 263 | 0 264 | 265 | 266 | 2 267 | 7 268 | 1 269 | 0 270 | 0 271 | 0 272 | ..\Core\Src\w25qxx.c 273 | w25qxx.c 274 | 0 275 | 0 276 | 277 | 278 | 2 279 | 8 280 | 1 281 | 0 282 | 0 283 | 0 284 | ..\Core\Src\usart.c 285 | usart.c 286 | 0 287 | 0 288 | 289 | 290 | 291 | 292 | Drivers/STM32H7xx_HAL_Driver 293 | 1 294 | 0 295 | 0 296 | 0 297 | 298 | 3 299 | 9 300 | 1 301 | 0 302 | 0 303 | 0 304 | ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c 305 | stm32h7xx_hal_cortex.c 306 | 0 307 | 0 308 | 309 | 310 | 3 311 | 10 312 | 1 313 | 0 314 | 0 315 | 0 316 | ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c 317 | stm32h7xx_hal_qspi.c 318 | 0 319 | 0 320 | 321 | 322 | 3 323 | 11 324 | 1 325 | 0 326 | 0 327 | 0 328 | ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c 329 | stm32h7xx_hal_rcc.c 330 | 0 331 | 0 332 | 333 | 334 | 3 335 | 12 336 | 1 337 | 0 338 | 0 339 | 0 340 | ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c 341 | stm32h7xx_hal_rcc_ex.c 342 | 0 343 | 0 344 | 345 | 346 | 3 347 | 13 348 | 1 349 | 0 350 | 0 351 | 0 352 | ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c 353 | stm32h7xx_hal_gpio.c 354 | 0 355 | 0 356 | 357 | 358 | 3 359 | 14 360 | 1 361 | 0 362 | 0 363 | 0 364 | ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c 365 | stm32h7xx_hal.c 366 | 0 367 | 0 368 | 369 | 370 | 3 371 | 15 372 | 1 373 | 0 374 | 0 375 | 0 376 | ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c 377 | stm32h7xx_hal_pwr.c 378 | 0 379 | 0 380 | 381 | 382 | 3 383 | 16 384 | 1 385 | 0 386 | 0 387 | 0 388 | ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c 389 | stm32h7xx_hal_pwr_ex.c 390 | 0 391 | 0 392 | 393 | 394 | 3 395 | 17 396 | 1 397 | 0 398 | 0 399 | 0 400 | ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c 401 | stm32h7xx_hal_uart.c 402 | 0 403 | 0 404 | 405 | 406 | 3 407 | 18 408 | 1 409 | 0 410 | 0 411 | 0 412 | ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c 413 | stm32h7xx_hal_uart_ex.c 414 | 0 415 | 0 416 | 417 | 418 | 3 419 | 19 420 | 1 421 | 0 422 | 0 423 | 0 424 | ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c 425 | stm32h7xx_hal_dma.c 426 | 0 427 | 0 428 | 429 | 430 | 3 431 | 20 432 | 1 433 | 0 434 | 0 435 | 0 436 | ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c 437 | stm32h7xx_hal_mdma.c 438 | 0 439 | 0 440 | 441 | 442 | 443 | 444 | Drivers/CMSIS 445 | 1 446 | 0 447 | 0 448 | 0 449 | 450 | 4 451 | 21 452 | 1 453 | 0 454 | 0 455 | 0 456 | ../Core/Src/system_stm32h7xx.c 457 | system_stm32h7xx.c 458 | 0 459 | 0 460 | 461 | 462 | 463 | 464 | ::CMSIS 465 | 0 466 | 0 467 | 0 468 | 1 469 | 470 | 471 | 472 | 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https://raw.githubusercontent.com/lchnu/STM32H750XBH_ARTPIQSPI_W25Q64JV/4d47c2612435d34a8467fd740540f9461bf2110f/README.assets/image-20230601121558481.png -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32H750XBH_ARTPIQSPI_W25Q64JV 2 | ARTPI STLDR - QSPI Flash W25Q64JV Download Algorithm for STM32CubeProgrammer & RT-Thread Studio 3 | 4 | 本程序适用于ART-PI开发板，基于STM32H750XBH6和W25Q64JV制作，支持串口输出打印Init、Read、Write过程。暂时未做Verfiy程序。 5 | 6 | 测试环境： 7 | 8 | ST CubeProgrammer 2.10.0 9 | 10 | RT-Thread Studio 2.2.6 11 | 12 | > 注意，为了个人测试方便，默认在两个文件夹中生成STLDR文件。用户可以删除或修改User自定义命令 13 | 14 | ![image-20230601115223608](README.assets/image-20230601115223608.png) 15 | 16 | 17 | 18 | 在下载算法程序中，main.h中有三个宏 19 | 20 | ```c 21 | #define DEBUG_WITH_UART 22 | #define W25QXX_WRITE_DIFF 23 | #define W25QXX_READ_BY_MEMORY_MAP 24 | ``` 25 | 26 | 分别对应： 27 | 28 | 1. 使用串口4输出进行下载过程打印 29 | 2. W25Q64使用差分方式下载 30 | 3. W25Q64使用内存映射模式读取 31 | 32 | 三个宏可以任意组合使用。 33 | 34 | 目前上传到Github的版本中，默认开启了串口和差分下载。 35 | 36 | 如果取消串口打印，则下载时间会有2秒左右提升。 37 | 38 | ## ST CubeProgrammer中测试 39 | 40 | **Step 1**. 选中算法 41 | 42 | ![image-20230601115440178](README.assets/image-20230601115440178.png) 43 | 44 | **Step 2**. 全片擦除 45 | 46 | ![image-20230601115533935](README.assets/image-20230601115533935.png) 47 | 48 | **Step 3**. 读取0x90000000，确认已擦除 49 | 50 | ![image-20230601115618557](README.assets/image-20230601115618557.png) 51 | 52 | **Step 4**. 下载程序 53 | 54 | 由于默认用差分方式下载，所以每个扇区的内容与待写入的程序不同，耗时约10S左右。 55 | 56 | ![image-20230601115823597](README.assets/image-20230601115823597.png) 57 | 58 | **Step 5**. 复位开发板，程序成功运行 59 | 60 | ![image-20230601115857964](README.assets/image-20230601115857964.png) 61 | 62 | ## RT-Thread Studio中测试 63 | 64 | **Step 1**.在Studio中选中算法 65 | 66 | ![image-20230601120011779](README.assets/image-20230601120011779.png) 67 | 68 | 69 | 70 | **Step 2**. 在完成上述步骤后，在Studio中不修改程序，直接下载 71 | 72 | 由于程序没有任何变化，所以下载过程会提示扇区内容与待写入数据相同，并没有对扇区有任何擦除和写入操作。 73 | 74 | ![image-20230601120129867](README.assets/image-20230601120129867.png) 75 | 76 | **Step 3**. 修改程序的LOG，编译后再次下载。 77 | 78 | 如，修改如下LOG的最后一个字符 79 | 80 | ```c 81 | LOG_I("Hello RT-Thread----------xyz2"); 82 | ``` 83 | 84 | 将2修改为3 85 | 86 | ```c 87 | LOG_I("Hello RT-Thread----------xyz3"); 88 | ``` 89 | 90 | 此时只有某一个扇区有不同的数据，程序下载后，成功运行，且下载过程中串口输出结果表示，在扇区34处有数据不同，因此进行该扇区的擦除和写入。 91 | 92 | ![image-20230601120333767](README.assets/image-20230601120333767.png) 93 | 94 | ![image-20230601120341498](README.assets/image-20230601120341498.png) 95 | 96 | **Step 4.** 确认在Studio中通过命令行调用STM32 CubeProg下载所花费的时间 97 | 98 | 在串口输出打印的情况下，差分下载约4秒。若关闭串口输出打印，时间约1-2秒。 99 | 100 | ![image-20230601120511564](README.assets/image-20230601120511564.png) 101 | 102 | **Step 5.** 关闭串口输出，简单修改log字符，下载时间约2秒 103 | 104 | ![image-20230601121518862](README.assets/image-20230601121518862.png) 105 | -------------------------------------------------------------------------------- /Reference/apnt_333.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lchnu/STM32H750XBH_ARTPIQSPI_W25Q64JV/4d47c2612435d34a8467fd740540f9461bf2110f/Reference/apnt_333.pdf -------------------------------------------------------------------------------- /Reference/en.DM00403500.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lchnu/STM32H750XBH_ARTPIQSPI_W25Q64JV/4d47c2612435d34a8467fd740540f9461bf2110f/Reference/en.DM00403500.pdf -------------------------------------------------------------------------------- /STM32H750XBH_ARTPIQSPI_W25Q64JV.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | CAD.formats= 3 | CAD.pinconfig= 4 | CAD.provider= 5 | CORTEX_M7.CPU_DCache=Enabled 6 | CORTEX_M7.CPU_ICache=Enabled 7 | CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache 8 | CORTEX_M7.default_mode_Activation=0 9 | File.Version=6 10 | GPIO.groupedBy=Group By Peripherals 11 | KeepUserPlacement=false 12 | Mcu.CPN=STM32H750XBH6 13 | Mcu.Family=STM32H7 14 | Mcu.IP0=CORTEX_M7 15 | Mcu.IP1=NVIC 16 | Mcu.IP2=QUADSPI 17 | Mcu.IP3=RCC 18 | Mcu.IP4=SYS 19 | Mcu.IP5=UART4 20 | Mcu.IPNb=6 21 | Mcu.Name=STM32H750XBHx 22 | Mcu.Package=TFBGA240 23 | Mcu.Pin0=PC10 24 | Mcu.Pin1=PC15-OSC32_OUT (OSC32_OUT) 25 | Mcu.Pin10=PF8 26 | Mcu.Pin11=PF10 27 | Mcu.Pin12=PF9 28 | Mcu.Pin13=VP_SYS_VS_Systick 29 | Mcu.Pin2=PA10 30 | Mcu.Pin3=PI9 31 | Mcu.Pin4=PI8 32 | Mcu.Pin5=PG6 33 | Mcu.Pin6=PH1-OSC_OUT (PH1) 34 | Mcu.Pin7=PH0-OSC_IN (PH0) 35 | Mcu.Pin8=PF6 36 | Mcu.Pin9=PF7 37 | Mcu.PinsNb=14 38 | Mcu.ThirdPartyNb=0 39 | Mcu.UserConstants= 40 | Mcu.UserName=STM32H750XBHx 41 | MxCube.Version=6.7.0 42 | MxDb.Version=DB.6.0.70 43 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 44 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 45 | NVIC.ForceEnableDMAVector=true 46 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 47 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 48 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 49 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 50 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 51 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 52 | NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false 53 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 54 | PA10.Locked=true 55 | PA10.Signal=USART1_RX 56 | PC10.Mode=Asynchronous 57 | PC10.Signal=UART4_TX 58 | PC15-OSC32_OUT\ (OSC32_OUT).GPIOParameters=PinState,GPIO_PuPd 59 | PC15-OSC32_OUT\ (OSC32_OUT).GPIO_PuPd=GPIO_PULLUP 60 | PC15-OSC32_OUT\ (OSC32_OUT).Locked=true 61 | PC15-OSC32_OUT\ (OSC32_OUT).PinState=GPIO_PIN_SET 62 | PC15-OSC32_OUT\ (OSC32_OUT).Signal=GPIO_Output 63 | PF10.GPIOParameters=GPIO_Speed 64 | PF10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 65 | PF10.Locked=true 66 | PF10.Mode=Single Bank 1 67 | PF10.Signal=QUADSPI_CLK 68 | PF6.GPIOParameters=GPIO_Speed 69 | PF6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 70 | PF6.Locked=true 71 | PF6.Mode=Single Bank 1 72 | PF6.Signal=QUADSPI_BK1_IO3 73 | PF7.GPIOParameters=GPIO_Speed 74 | PF7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 75 | PF7.Locked=true 76 | PF7.Mode=Single Bank 1 77 | PF7.Signal=QUADSPI_BK1_IO2 78 | PF8.GPIOParameters=GPIO_Speed 79 | PF8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 80 | PF8.Locked=true 81 | PF8.Mode=Single Bank 1 82 | PF8.Signal=QUADSPI_BK1_IO0 83 | PF9.GPIOParameters=GPIO_Speed 84 | PF9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 85 | PF9.Locked=true 86 | PF9.Mode=Single Bank 1 87 | PF9.Signal=QUADSPI_BK1_IO1 88 | PG6.GPIOParameters=GPIO_Speed 89 | PG6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 90 | PG6.Locked=true 91 | PG6.Mode=Single Bank 1 92 | PG6.Signal=QUADSPI_BK1_NCS 93 | PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator 94 | PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN 95 | PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator 96 | PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT 97 | PI8.GPIOParameters=PinState,GPIO_PuPd 98 | PI8.GPIO_PuPd=GPIO_PULLUP 99 | PI8.Locked=true 100 | PI8.PinState=GPIO_PIN_SET 101 | PI8.Signal=GPIO_Output 102 | PI9.Locked=true 103 | PI9.Mode=Asynchronous 104 | PI9.Signal=UART4_RX 105 | PinOutPanel.CurrentBGAView=Top 106 | PinOutPanel.RotationAngle=0 107 | ProjectManager.AskForMigrate=true 108 | ProjectManager.BackupPrevious=false 109 | ProjectManager.CompilerOptimize=6 110 | ProjectManager.ComputerToolchain=false 111 | ProjectManager.CoupleFile=true 112 | ProjectManager.CustomerFirmwarePackage=..\\..\\STM32Cube\\Repository\\STM32Cube_FW_H7_V1.9.1 113 | ProjectManager.DefaultFWLocation=false 114 | ProjectManager.DeletePrevious=true 115 | ProjectManager.DeviceId=STM32H750XBHx 116 | ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0 117 | ProjectManager.FreePins=false 118 | ProjectManager.HalAssertFull=false 119 | ProjectManager.HeapSize=0x200 120 | ProjectManager.KeepUserCode=true 121 | ProjectManager.LastFirmware=true 122 | ProjectManager.LibraryCopy=1 123 | ProjectManager.MainLocation=Core/Src 124 | ProjectManager.NoMain=true 125 | ProjectManager.PreviousToolchain= 126 | ProjectManager.ProjectBuild=false 127 | ProjectManager.ProjectFileName=STM32H750XBH6_ArtPi_QSPI_W25Q64JV_STLDR.ioc 128 | ProjectManager.ProjectName=STM32H750XBH6_ArtPi_QSPI_W25Q64JV_STLDR 129 | ProjectManager.ProjectStructure= 130 | ProjectManager.RegisterCallBack= 131 | ProjectManager.StackSize=0x400 132 | ProjectManager.TargetToolchain=MDK-ARM V5 133 | ProjectManager.ToolChainLocation= 134 | ProjectManager.UnderRoot=false 135 | ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_QUADSPI_Init-QUADSPI-false-HAL-true,4-MX_UART4_Init-UART4-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true 136 | QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_5_CYCLE 137 | QUADSPI.ClockMode=QSPI_CLOCK_MODE_0 138 | QUADSPI.ClockPrescaler=1 139 | QUADSPI.FifoThreshold=32 140 | QUADSPI.FlashSize=22 141 | QUADSPI.IPParameters=ClockPrescaler,FifoThreshold,SampleShifting,FlashSize,ChipSelectHighTime,ClockMode 142 | QUADSPI.SampleShifting=QSPI_SAMPLE_SHIFTING_HALFCYCLE 143 | RCC.ADCFreq_Value=50390625 144 | RCC.AHB12Freq_Value=240000000 145 | RCC.AHB4Freq_Value=240000000 146 | RCC.APB1Freq_Value=120000000 147 | RCC.APB2Freq_Value=120000000 148 | RCC.APB3Freq_Value=120000000 149 | RCC.APB4Freq_Value=120000000 150 | RCC.AXIClockFreq_Value=240000000 151 | RCC.CECFreq_Value=32000 152 | RCC.CKPERFreq_Value=64000000 153 | RCC.CortexFreq_Value=480000000 154 | RCC.CpuClockFreq_Value=480000000 155 | RCC.D1CPREFreq_Value=480000000 156 | RCC.D1PPRE=RCC_APB3_DIV2 157 | RCC.D2PPRE1=RCC_APB1_DIV2 158 | RCC.D2PPRE2=RCC_APB2_DIV2 159 | RCC.D3PPRE=RCC_APB4_DIV2 160 | RCC.DFSDMACLkFreq_Value=480000000 161 | RCC.DFSDMFreq_Value=120000000 162 | RCC.DIVM1=5 163 | RCC.DIVN1=192 164 | RCC.DIVP1Freq_Value=480000000 165 | RCC.DIVP2Freq_Value=50390625 166 | RCC.DIVP3Freq_Value=50390625 167 | RCC.DIVQ1Freq_Value=480000000 168 | RCC.DIVQ2Freq_Value=50390625 169 | RCC.DIVQ3Freq_Value=50390625 170 | RCC.DIVR1Freq_Value=480000000 171 | RCC.DIVR2Freq_Value=50390625 172 | RCC.DIVR3Freq_Value=50390625 173 | RCC.FDCANFreq_Value=480000000 174 | RCC.FMCFreq_Value=240000000 175 | RCC.FamilyName=M 176 | RCC.HCLK3ClockFreq_Value=240000000 177 | RCC.HCLKFreq_Value=240000000 178 | RCC.HPRE=RCC_HCLK_DIV2 179 | RCC.HRTIMFreq_Value=240000000 180 | RCC.I2C123Freq_Value=120000000 181 | RCC.I2C4Freq_Value=120000000 182 | RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,ProductRev,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value 183 | RCC.LPTIM1Freq_Value=120000000 184 | RCC.LPTIM2Freq_Value=120000000 185 | RCC.LPTIM345Freq_Value=120000000 186 | RCC.LPUART1Freq_Value=120000000 187 | RCC.LTDCFreq_Value=50390625 188 | RCC.MCO1PinFreq_Value=64000000 189 | RCC.MCO2PinFreq_Value=480000000 190 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE 191 | RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE0 192 | RCC.ProductRev=revV 193 | RCC.QSPIFreq_Value=240000000 194 | RCC.RNGFreq_Value=48000000 195 | RCC.RTCFreq_Value=32000 196 | RCC.SAI1Freq_Value=480000000 197 | RCC.SAI23Freq_Value=480000000 198 | RCC.SAI4AFreq_Value=480000000 199 | RCC.SAI4BFreq_Value=480000000 200 | RCC.SDMMCFreq_Value=480000000 201 | RCC.SPDIFRXFreq_Value=480000000 202 | RCC.SPI123Freq_Value=480000000 203 | RCC.SPI45Freq_Value=120000000 204 | RCC.SPI6Freq_Value=120000000 205 | RCC.SWPMI1Freq_Value=120000000 206 | RCC.SYSCLKFreq_VALUE=480000000 207 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 208 | RCC.Tim1OutputFreq_Value=240000000 209 | RCC.Tim2OutputFreq_Value=240000000 210 | RCC.TraceFreq_Value=64000000 211 | RCC.USART16Freq_Value=120000000 212 | RCC.USART234578Freq_Value=120000000 213 | RCC.USBFreq_Value=480000000 214 | RCC.VCO1OutputFreq_Value=960000000 215 | RCC.VCO2OutputFreq_Value=100781250 216 | RCC.VCO3OutputFreq_Value=100781250 217 | RCC.VCOInput1Freq_Value=5000000 218 | RCC.VCOInput2Freq_Value=781250 219 | RCC.VCOInput3Freq_Value=781250 220 | VP_SYS_VS_Systick.Mode=SysTick 221 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 222 | board=custom 223 | -------------------------------------------------------------------------------- /STM32H750XBH_ARTPIQSPI_W25Q64JV.stldr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lchnu/STM32H750XBH_ARTPIQSPI_W25Q64JV/4d47c2612435d34a8467fd740540f9461bf2110f/STM32H750XBH_ARTPIQSPI_W25Q64JV.stldr -------------------------------------------------------------------------------- /loader.sct: -------------------------------------------------------------------------------- 1 | ;FLASH_LOADER 0x24040004 PI ; FlashLoader Functions 2 | ;FLASH_LOADER 0x20000004 PI 3 | FLASH_LOADER 0x24000004 PI 4 | { 5 | PrgCode +0 ; Code 6 | { 7 | * (+RO) 8 | } 9 | PrgData +0 ; Data 10 | { 11 | * (+RW,+ZI) 12 | } 13 | } 14 | 15 | DEVICE_INFO +0 ; Device Info 16 | { 17 | DevInfo +0 ; Info structure 18 | { 19 | dev_inf.o 20 | } 21 | } 22 | 23 | --------------------------------------------------------------------------------