├── .gitignore ├── LICENSE ├── README.md ├── riscv.py └── tests ├── Makefile ├── riscv32 ├── Makefile ├── test_RV32A.s ├── test_RV32F_RV32D.s ├── test_RV32I.s └── test_RV32M.s └── riscv64 └── Makefile /.gitignore: -------------------------------------------------------------------------------- 1 | # Byte-compiled / optimized / DLL files 2 | __pycache__/ 3 | *.py[cod] 4 | *$py.class 5 | 6 | *.o 7 | *.bin 8 | *.elf 9 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. By contrast, 15 | the GNU General Public License is intended to guarantee your freedom to 16 | share and change all versions of a program--to make sure it remains free 17 | software for all its users. We, the Free Software Foundation, use the 18 | GNU General Public License for most of our software; it applies also to 19 | any other work released this way by its authors. You can apply it to 20 | your programs, too. 21 | 22 | When we speak of free software, we are referring to freedom, not 23 | price. Our General Public Licenses are designed to make sure that you 24 | have the freedom to distribute copies of free software (and charge for 25 | them if you wish), that you receive source code or can get it if you 26 | want it, that you can change the software or use pieces of it in new 27 | free programs, and that you know you can do these things. 28 | 29 | To protect your rights, we need to prevent others from denying you 30 | these rights or asking you to surrender the rights. Therefore, you have 31 | certain responsibilities if you distribute copies of the software, or if 32 | you modify it: responsibilities to respect the freedom of others. 33 | 34 | For example, if you distribute copies of such a program, whether 35 | gratis or for a fee, you must pass on to the recipients the same 36 | freedoms that you received. You must make sure that they, too, receive 37 | or can get the source code. And you must show them these terms so they 38 | know their rights. 39 | 40 | Developers that use the GNU GPL protect your rights with two steps: 41 | (1) assert copyright on the software, and (2) offer you this License 42 | giving you legal permission to copy, distribute and/or modify it. 43 | 44 | For the developers' and authors' protection, the GPL clearly explains 45 | that there is no warranty for this free software. For both users' and 46 | authors' sake, the GPL requires that modified versions be marked as 47 | changed, so that their problems will not be attributed erroneously to 48 | authors of previous versions. 49 | 50 | Some devices are designed to deny users access to install or run 51 | modified versions of the software inside them, although the manufacturer 52 | can do so. This is fundamentally incompatible with the aim of 53 | protecting users' freedom to change the software. The systematic 54 | pattern of such abuse occurs in the area of products for individuals to 55 | use, which is precisely where it is most unacceptable. Therefore, we 56 | have designed this version of the GPL to prohibit the practice for those 57 | products. If such problems arise substantially in other domains, we 58 | stand ready to extend this provision to those domains in future versions 59 | of the GPL, as needed to protect the freedom of users. 60 | 61 | Finally, every program is threatened constantly by software patents. 62 | States should not allow patents to restrict development and use of 63 | software on general-purpose computers, but in those that do, we wish to 64 | avoid the special danger that patents applied to a free program could 65 | make it effectively proprietary. To prevent this, the GPL assures that 66 | patents cannot be used to render the program non-free. 67 | 68 | The precise terms and conditions for copying, distribution and 69 | modification follow. 70 | 71 | TERMS AND CONDITIONS 72 | 73 | 0. Definitions. 74 | 75 | "This License" refers to version 3 of the GNU General Public License. 76 | 77 | "Copyright" also means copyright-like laws that apply to other kinds of 78 | works, such as semiconductor masks. 79 | 80 | "The Program" refers to any copyrightable work licensed under this 81 | License. Each licensee is addressed as "you". "Licensees" and 82 | "recipients" may be individuals or organizations. 83 | 84 | To "modify" a work means to copy from or adapt all or part of the work 85 | in a fashion requiring copyright permission, other than the making of an 86 | exact copy. The resulting work is called a "modified version" of the 87 | earlier work or a work "based on" the earlier work. 88 | 89 | A "covered work" means either the unmodified Program or a work based 90 | on the Program. 91 | 92 | To "propagate" a work means to do anything with it that, without 93 | permission, would make you directly or secondarily liable for 94 | infringement under applicable copyright law, except executing it on a 95 | computer or modifying a private copy. Propagation includes copying, 96 | distribution (with or without modification), making available to the 97 | public, and in some countries other activities as well. 98 | 99 | To "convey" a work means any kind of propagation that enables other 100 | parties to make or receive copies. Mere interaction with a user through 101 | a computer network, with no transfer of a copy, is not conveying. 102 | 103 | An interactive user interface displays "Appropriate Legal Notices" 104 | to the extent that it includes a convenient and prominently visible 105 | feature that (1) displays an appropriate copyright notice, and (2) 106 | tells the user that there is no warranty for the work (except to the 107 | extent that warranties are provided), that licensees may convey the 108 | work under this License, and how to view a copy of this License. If 109 | the interface presents a list of user commands or options, such as a 110 | menu, a prominent item in the list meets this criterion. 111 | 112 | 1. Source Code. 113 | 114 | The "source code" for a work means the preferred form of the work 115 | for making modifications to it. "Object code" means any non-source 116 | form of a work. 117 | 118 | A "Standard Interface" means an interface that either is an official 119 | standard defined by a recognized standards body, or, in the case of 120 | interfaces specified for a particular programming language, one that 121 | is widely used among developers working in that language. 122 | 123 | The "System Libraries" of an executable work include anything, other 124 | than the work as a whole, that (a) is included in the normal form of 125 | packaging a Major Component, but which is not part of that Major 126 | Component, and (b) serves only to enable use of the work with that 127 | Major Component, or to implement a Standard Interface for which an 128 | implementation is available to the public in source code form. A 129 | "Major Component", in this context, means a major essential component 130 | (kernel, window system, and so on) of the specific operating system 131 | (if any) on which the executable work runs, or a compiler used to 132 | produce the work, or an object code interpreter used to run it. 133 | 134 | The "Corresponding Source" for a work in object code form means all 135 | the source code needed to generate, install, and (for an executable 136 | work) run the object code and to modify the work, including scripts to 137 | control those activities. However, it does not include the work's 138 | System Libraries, or general-purpose tools or generally available free 139 | programs which are used unmodified in performing those activities but 140 | which are not part of the work. For example, Corresponding Source 141 | includes interface definition files associated with source files for 142 | the work, and the source code for shared libraries and dynamically 143 | linked subprograms that the work is specifically designed to require, 144 | such as by intimate data communication or control flow between those 145 | subprograms and other parts of the work. 146 | 147 | The Corresponding Source need not include anything that users 148 | can regenerate automatically from other parts of the Corresponding 149 | Source. 150 | 151 | The Corresponding Source for a work in source code form is that 152 | same work. 153 | 154 | 2. Basic Permissions. 155 | 156 | All rights granted under this License are granted for the term of 157 | copyright on the Program, and are irrevocable provided the stated 158 | conditions are met. This License explicitly affirms your unlimited 159 | permission to run the unmodified Program. The output from running a 160 | covered work is covered by this License only if the output, given its 161 | content, constitutes a covered work. This License acknowledges your 162 | rights of fair use or other equivalent, as provided by copyright law. 163 | 164 | You may make, run and propagate covered works that you do not 165 | convey, without conditions so long as your license otherwise remains 166 | in force. You may convey covered works to others for the sole purpose 167 | of having them make modifications exclusively for you, or provide you 168 | with facilities for running those works, provided that you comply with 169 | the terms of this License in conveying all material for which you do 170 | not control copyright. Those thus making or running the covered works 171 | for you must do so exclusively on your behalf, under your direction 172 | and control, on terms that prohibit them from making any copies of 173 | your copyrighted material outside their relationship with you. 174 | 175 | Conveying under any other circumstances is permitted solely under 176 | the conditions stated below. Sublicensing is not allowed; section 10 177 | makes it unnecessary. 178 | 179 | 3. Protecting Users' Legal Rights From Anti-Circumvention Law. 180 | 181 | No covered work shall be deemed part of an effective technological 182 | measure under any applicable law fulfilling obligations under article 183 | 11 of the WIPO copyright treaty adopted on 20 December 1996, or 184 | similar laws prohibiting or restricting circumvention of such 185 | measures. 186 | 187 | When you convey a covered work, you waive any legal power to forbid 188 | circumvention of technological measures to the extent such circumvention 189 | is effected by exercising rights under this License with respect to 190 | the covered work, and you disclaim any intention to limit operation or 191 | modification of the work as a means of enforcing, against the work's 192 | users, your or third parties' legal rights to forbid circumvention of 193 | technological measures. 194 | 195 | 4. Conveying Verbatim Copies. 196 | 197 | You may convey verbatim copies of the Program's source code as you 198 | receive it, in any medium, provided that you conspicuously and 199 | appropriately publish on each copy an appropriate copyright notice; 200 | keep intact all notices stating that this License and any 201 | non-permissive terms added in accord with section 7 apply to the code; 202 | keep intact all notices of the absence of any warranty; and give all 203 | recipients a copy of this License along with the Program. 204 | 205 | You may charge any price or no price for each copy that you convey, 206 | and you may offer support or warranty protection for a fee. 207 | 208 | 5. Conveying Modified Source Versions. 209 | 210 | You may convey a work based on the Program, or the modifications to 211 | produce it from the Program, in the form of source code under the 212 | terms of section 4, provided that you also meet all of these conditions: 213 | 214 | a) The work must carry prominent notices stating that you modified 215 | it, and giving a relevant date. 216 | 217 | b) The work must carry prominent notices stating that it is 218 | released under this License and any conditions added under section 219 | 7. This requirement modifies the requirement in section 4 to 220 | "keep intact all notices". 221 | 222 | c) You must license the entire work, as a whole, under this 223 | License to anyone who comes into possession of a copy. This 224 | License will therefore apply, along with any applicable section 7 225 | additional terms, to the whole of the work, and all its parts, 226 | regardless of how they are packaged. This License gives no 227 | permission to license the work in any other way, but it does not 228 | invalidate such permission if you have separately received it. 229 | 230 | d) If the work has interactive user interfaces, each must display 231 | Appropriate Legal Notices; however, if the Program has interactive 232 | interfaces that do not display Appropriate Legal Notices, your 233 | work need not make them do so. 234 | 235 | A compilation of a covered work with other separate and independent 236 | works, which are not by their nature extensions of the covered work, 237 | and which are not combined with it such as to form a larger program, 238 | in or on a volume of a storage or distribution medium, is called an 239 | "aggregate" if the compilation and its resulting copyright are not 240 | used to limit the access or legal rights of the compilation's users 241 | beyond what the individual works permit. Inclusion of a covered work 242 | in an aggregate does not cause this License to apply to the other 243 | parts of the aggregate. 244 | 245 | 6. Conveying Non-Source Forms. 246 | 247 | You may convey a covered work in object code form under the terms 248 | of sections 4 and 5, provided that you also convey the 249 | machine-readable Corresponding Source under the terms of this License, 250 | in one of these ways: 251 | 252 | a) Convey the object code in, or embodied in, a physical product 253 | (including a physical distribution medium), accompanied by the 254 | Corresponding Source fixed on a durable physical medium 255 | customarily used for software interchange. 256 | 257 | b) Convey the object code in, or embodied in, a physical product 258 | (including a physical distribution medium), accompanied by a 259 | written offer, valid for at least three years and valid for as 260 | long as you offer spare parts or customer support for that product 261 | model, to give anyone who possesses the object code either (1) a 262 | copy of the Corresponding Source for all the software in the 263 | product that is covered by this License, on a durable physical 264 | medium customarily used for software interchange, for a price no 265 | more than your reasonable cost of physically performing this 266 | conveying of source, or (2) access to copy the 267 | Corresponding Source from a network server at no charge. 268 | 269 | c) Convey individual copies of the object code with a copy of the 270 | written offer to provide the Corresponding Source. This 271 | alternative is allowed only occasionally and noncommercially, and 272 | only if you received the object code with such an offer, in accord 273 | with subsection 6b. 274 | 275 | d) Convey the object code by offering access from a designated 276 | place (gratis or for a charge), and offer equivalent access to the 277 | Corresponding Source in the same way through the same place at no 278 | further charge. You need not require recipients to copy the 279 | Corresponding Source along with the object code. If the place to 280 | copy the object code is a network server, the Corresponding Source 281 | may be on a different server (operated by you or a third party) 282 | that supports equivalent copying facilities, provided you maintain 283 | clear directions next to the object code saying where to find the 284 | Corresponding Source. Regardless of what server hosts the 285 | Corresponding Source, you remain obligated to ensure that it is 286 | available for as long as needed to satisfy these requirements. 287 | 288 | e) Convey the object code using peer-to-peer transmission, provided 289 | you inform other peers where the object code and Corresponding 290 | Source of the work are being offered to the general public at no 291 | charge under subsection 6d. 292 | 293 | A separable portion of the object code, whose source code is excluded 294 | from the Corresponding Source as a System Library, need not be 295 | included in conveying the object code work. 296 | 297 | A "User Product" is either (1) a "consumer product", which means any 298 | tangible personal property which is normally used for personal, family, 299 | or household purposes, or (2) anything designed or sold for incorporation 300 | into a dwelling. In determining whether a product is a consumer product, 301 | doubtful cases shall be resolved in favor of coverage. For a particular 302 | product received by a particular user, "normally used" refers to a 303 | typical or common use of that class of product, regardless of the status 304 | of the particular user or of the way in which the particular user 305 | actually uses, or expects or is expected to use, the product. A product 306 | is a consumer product regardless of whether the product has substantial 307 | commercial, industrial or non-consumer uses, unless such uses represent 308 | the only significant mode of use of the product. 309 | 310 | "Installation Information" for a User Product means any methods, 311 | procedures, authorization keys, or other information required to install 312 | and execute modified versions of a covered work in that User Product from 313 | a modified version of its Corresponding Source. The information must 314 | suffice to ensure that the continued functioning of the modified object 315 | code is in no case prevented or interfered with solely because 316 | modification has been made. 317 | 318 | If you convey an object code work under this section in, or with, or 319 | specifically for use in, a User Product, and the conveying occurs as 320 | part of a transaction in which the right of possession and use of the 321 | User Product is transferred to the recipient in perpetuity or for a 322 | fixed term (regardless of how the transaction is characterized), the 323 | Corresponding Source conveyed under this section must be accompanied 324 | by the Installation Information. But this requirement does not apply 325 | if neither you nor any third party retains the ability to install 326 | modified object code on the User Product (for example, the work has 327 | been installed in ROM). 328 | 329 | The requirement to provide Installation Information does not include a 330 | requirement to continue to provide support service, warranty, or updates 331 | for a work that has been modified or installed by the recipient, or for 332 | the User Product in which it has been modified or installed. Access to a 333 | network may be denied when the modification itself materially and 334 | adversely affects the operation of the network or violates the rules and 335 | protocols for communication across the network. 336 | 337 | Corresponding Source conveyed, and Installation Information provided, 338 | in accord with this section must be in a format that is publicly 339 | documented (and with an implementation available to the public in 340 | source code form), and must require no special password or key for 341 | unpacking, reading or copying. 342 | 343 | 7. Additional Terms. 344 | 345 | "Additional permissions" are terms that supplement the terms of this 346 | License by making exceptions from one or more of its conditions. 347 | Additional permissions that are applicable to the entire Program shall 348 | be treated as though they were included in this License, to the extent 349 | that they are valid under applicable law. If additional permissions 350 | apply only to part of the Program, that part may be used separately 351 | under those permissions, but the entire Program remains governed by 352 | this License without regard to the additional permissions. 353 | 354 | When you convey a copy of a covered work, you may at your option 355 | remove any additional permissions from that copy, or from any part of 356 | it. (Additional permissions may be written to require their own 357 | removal in certain cases when you modify the work.) You may place 358 | additional permissions on material, added by you to a covered work, 359 | for which you have or can give appropriate copyright permission. 360 | 361 | Notwithstanding any other provision of this License, for material you 362 | add to a covered work, you may (if authorized by the copyright holders of 363 | that material) supplement the terms of this License with terms: 364 | 365 | a) Disclaiming warranty or limiting liability differently from the 366 | terms of sections 15 and 16 of this License; or 367 | 368 | b) Requiring preservation of specified reasonable legal notices or 369 | author attributions in that material or in the Appropriate Legal 370 | Notices displayed by works containing it; or 371 | 372 | c) Prohibiting misrepresentation of the origin of that material, or 373 | requiring that modified versions of such material be marked in 374 | reasonable ways as different from the original version; or 375 | 376 | d) Limiting the use for publicity purposes of names of licensors or 377 | authors of the material; or 378 | 379 | e) Declining to grant rights under trademark law for use of some 380 | trade names, trademarks, or service marks; or 381 | 382 | f) Requiring indemnification of licensors and authors of that 383 | material by anyone who conveys the material (or modified versions of 384 | it) with contractual assumptions of liability to the recipient, for 385 | any liability that these contractual assumptions directly impose on 386 | those licensors and authors. 387 | 388 | All other non-permissive additional terms are considered "further 389 | restrictions" within the meaning of section 10. If the Program as you 390 | received it, or any part of it, contains a notice stating that it is 391 | governed by this License along with a term that is a further 392 | restriction, you may remove that term. If a license document contains 393 | a further restriction but permits relicensing or conveying under this 394 | License, you may add to a covered work material governed by the terms 395 | of that license document, provided that the further restriction does 396 | not survive such relicensing or conveying. 397 | 398 | If you add terms to a covered work in accord with this section, you 399 | must place, in the relevant source files, a statement of the 400 | additional terms that apply to those files, or a notice indicating 401 | where to find the applicable terms. 402 | 403 | Additional terms, permissive or non-permissive, may be stated in the 404 | form of a separately written license, or stated as exceptions; 405 | the above requirements apply either way. 406 | 407 | 8. Termination. 408 | 409 | You may not propagate or modify a covered work except as expressly 410 | provided under this License. Any attempt otherwise to propagate or 411 | modify it is void, and will automatically terminate your rights under 412 | this License (including any patent licenses granted under the third 413 | paragraph of section 11). 414 | 415 | However, if you cease all violation of this License, then your 416 | license from a particular copyright holder is reinstated (a) 417 | provisionally, unless and until the copyright holder explicitly and 418 | finally terminates your license, and (b) permanently, if the copyright 419 | holder fails to notify you of the violation by some reasonable means 420 | prior to 60 days after the cessation. 421 | 422 | Moreover, your license from a particular copyright holder is 423 | reinstated permanently if the copyright holder notifies you of the 424 | violation by some reasonable means, this is the first time you have 425 | received notice of violation of this License (for any work) from that 426 | copyright holder, and you cure the violation prior to 30 days after 427 | your receipt of the notice. 428 | 429 | Termination of your rights under this section does not terminate the 430 | licenses of parties who have received copies or rights from you under 431 | this License. If your rights have been terminated and not permanently 432 | reinstated, you do not qualify to receive new licenses for the same 433 | material under section 10. 434 | 435 | 9. Acceptance Not Required for Having Copies. 436 | 437 | You are not required to accept this License in order to receive or 438 | run a copy of the Program. Ancillary propagation of a covered work 439 | occurring solely as a consequence of using peer-to-peer transmission 440 | to receive a copy likewise does not require acceptance. However, 441 | nothing other than this License grants you permission to propagate or 442 | modify any covered work. These actions infringe copyright if you do 443 | not accept this License. Therefore, by modifying or propagating a 444 | covered work, you indicate your acceptance of this License to do so. 445 | 446 | 10. Automatic Licensing of Downstream Recipients. 447 | 448 | Each time you convey a covered work, the recipient automatically 449 | receives a license from the original licensors, to run, modify and 450 | propagate that work, subject to this License. You are not responsible 451 | for enforcing compliance by third parties with this License. 452 | 453 | An "entity transaction" is a transaction transferring control of an 454 | organization, or substantially all assets of one, or subdividing an 455 | organization, or merging organizations. If propagation of a covered 456 | work results from an entity transaction, each party to that 457 | transaction who receives a copy of the work also receives whatever 458 | licenses to the work the party's predecessor in interest had or could 459 | give under the previous paragraph, plus a right to possession of the 460 | Corresponding Source of the work from the predecessor in interest, if 461 | the predecessor has it or can get it with reasonable efforts. 462 | 463 | You may not impose any further restrictions on the exercise of the 464 | rights granted or affirmed under this License. For example, you may 465 | not impose a license fee, royalty, or other charge for exercise of 466 | rights granted under this License, and you may not initiate litigation 467 | (including a cross-claim or counterclaim in a lawsuit) alleging that 468 | any patent claim is infringed by making, using, selling, offering for 469 | sale, or importing the Program or any portion of it. 470 | 471 | 11. Patents. 472 | 473 | A "contributor" is a copyright holder who authorizes use under this 474 | License of the Program or a work on which the Program is based. The 475 | work thus licensed is called the contributor's "contributor version". 476 | 477 | A contributor's "essential patent claims" are all patent claims 478 | owned or controlled by the contributor, whether already acquired or 479 | hereafter acquired, that would be infringed by some manner, permitted 480 | by this License, of making, using, or selling its contributor version, 481 | but do not include claims that would be infringed only as a 482 | consequence of further modification of the contributor version. For 483 | purposes of this definition, "control" includes the right to grant 484 | patent sublicenses in a manner consistent with the requirements of 485 | this License. 486 | 487 | Each contributor grants you a non-exclusive, worldwide, royalty-free 488 | patent license under the contributor's essential patent claims, to 489 | make, use, sell, offer for sale, import and otherwise run, modify and 490 | propagate the contents of its contributor version. 491 | 492 | In the following three paragraphs, a "patent license" is any express 493 | agreement or commitment, however denominated, not to enforce a patent 494 | (such as an express permission to practice a patent or covenant not to 495 | sue for patent infringement). To "grant" such a patent license to a 496 | party means to make such an agreement or commitment not to enforce a 497 | patent against the party. 498 | 499 | If you convey a covered work, knowingly relying on a patent license, 500 | and the Corresponding Source of the work is not available for anyone 501 | to copy, free of charge and under the terms of this License, through a 502 | publicly available network server or other readily accessible means, 503 | then you must either (1) cause the Corresponding Source to be so 504 | available, or (2) arrange to deprive yourself of the benefit of the 505 | patent license for this particular work, or (3) arrange, in a manner 506 | consistent with the requirements of this License, to extend the patent 507 | license to downstream recipients. "Knowingly relying" means you have 508 | actual knowledge that, but for the patent license, your conveying the 509 | covered work in a country, or your recipient's use of the covered work 510 | in a country, would infringe one or more identifiable patents in that 511 | country that you have reason to believe are valid. 512 | 513 | If, pursuant to or in connection with a single transaction or 514 | arrangement, you convey, or propagate by procuring conveyance of, a 515 | covered work, and grant a patent license to some of the parties 516 | receiving the covered work authorizing them to use, propagate, modify 517 | or convey a specific copy of the covered work, then the patent license 518 | you grant is automatically extended to all recipients of the covered 519 | work and works based on it. 520 | 521 | A patent license is "discriminatory" if it does not include within 522 | the scope of its coverage, prohibits the exercise of, or is 523 | conditioned on the non-exercise of one or more of the rights that are 524 | specifically granted under this License. You may not convey a covered 525 | work if you are a party to an arrangement with a third party that is 526 | in the business of distributing software, under which you make payment 527 | to the third party based on the extent of your activity of conveying 528 | the work, and under which the third party grants, to any of the 529 | parties who would receive the covered work from you, a discriminatory 530 | patent license (a) in connection with copies of the covered work 531 | conveyed by you (or copies made from those copies), or (b) primarily 532 | for and in connection with specific products or compilations that 533 | contain the covered work, unless you entered into that arrangement, 534 | or that patent license was granted, prior to 28 March 2007. 535 | 536 | Nothing in this License shall be construed as excluding or limiting 537 | any implied license or other defenses to infringement that may 538 | otherwise be available to you under applicable patent law. 539 | 540 | 12. No Surrender of Others' Freedom. 541 | 542 | If conditions are imposed on you (whether by court order, agreement or 543 | otherwise) that contradict the conditions of this License, they do not 544 | excuse you from the conditions of this License. If you cannot convey a 545 | covered work so as to satisfy simultaneously your obligations under this 546 | License and any other pertinent obligations, then as a consequence you may 547 | not convey it at all. For example, if you agree to terms that obligate you 548 | to collect a royalty for further conveying from those to whom you convey 549 | the Program, the only way you could satisfy both those terms and this 550 | License would be to refrain entirely from conveying the Program. 551 | 552 | 13. Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V for IDA 2 | RISC-V ISA processor module for IDA 7.x written in Python. 3 | 4 | ## Overview 5 | **riscv-ida** is just a simple RISC-V processor module for IDA, written in Python for best compatibility across platforms and to ease the development process. 6 | Albeit very simple in nature, the plugin is already quite useful, allowing for instruction simplification, basic emulation and cross-references. 7 | 8 | The main reason I decided to write a RISC-V module for IDA is that I'm working on a RISC-V emulator/virtual-machine project, and since I'm new to RISC-V, the best way to start is writing a disassembler, to get a feeling of the architecture. 9 | 10 | 11 | ## Install 12 | Just copy riscv.py into *procs* folder of IDA. Start ida.exe and not ida64.exe, 64bit support is still missing (coming soon). 13 | 14 | ## Use 15 | You need to manually choose RISC-V in the cpu selector when you load a binary. ELF loader support coming soon... 16 | 17 | ## Missing 18 | Too much... :D 19 | 20 | Soon to come: 21 | - 64bit support in IDA 22 | - Data cross reference 23 | - Better emu 24 | - Better integration with ELF loader (no more Unrecognized cpu blabla) 25 | 26 | Someday: 27 | - Stack tracing (very nice to have...) 28 | - 128bit? 29 | 30 | # License 31 | GPLv3 32 | -------------------------------------------------------------------------------- /riscv.py: -------------------------------------------------------------------------------- 1 | from idaapi import * 2 | 3 | # keeping __EA64__ name for historical reasons 4 | __EA64__ = BADADDR == 0xFFFFFFFFFFFFFFFF 5 | 6 | 7 | def fix_sign_32(l): 8 | l &= 0xFFFFFFFF 9 | if l & 0x80000000: 10 | l -= 0x100000000 11 | return l 12 | 13 | 14 | def BITS(val, low, high): 15 | return (val >> low) & ((1 << (high - low + 1)) - 1) 16 | 17 | 18 | def BIT(val, bit): 19 | return (val >> bit) & 1 20 | 21 | 22 | def SIGNEXT(x, b): 23 | m = 1 << (b - 1) 24 | x = x & ((1 << b) - 1) 25 | return (x ^ m) - m 26 | 27 | 28 | def is_reg(op, regNo): 29 | return op.reg == regNo 30 | 31 | 32 | class UnknownInstruction(Exception): 33 | pass 34 | 35 | 36 | # RISC-V major opcodes 37 | RV_LUI = 0b0110111 38 | RV_AUIPC = 0b0010111 39 | RV_JAL = 0b1101111 40 | RV_JALR = 0b1100111 41 | RV_BRANCH = 0b1100011 42 | RV_LOAD = 0b0000011 43 | RV_STORE = 0b0100011 44 | RV_IMM = 0b0010011 45 | RV_OP = 0b0110011 46 | RV_MISC_MEM = 0b0001111 47 | RV_SYSTEM = 0b1110011 48 | RV_AMO = 0b0101111 49 | RV_LOAD_FP = 0b0000111 50 | RV_STORE_FP = 0b0100111 51 | RV_FMADD = 0b1000011 52 | RV_FMSUB = 0b1000111 53 | RV_FNMSUB = 0b1001011 54 | RV_FNMADD = 0b1001111 55 | RV_OP_FP = 0b1010011 56 | 57 | RV_MAJ_OPCODE_MASK = 0b01111111 58 | RV_C_MASK = 0b11 59 | 60 | RV_U_IMM_31_12_MASK = 0b11111111111111111111000000000000 61 | RV_IMM_SIGN_BIT = 0x80000000 62 | RV_C_IMM_SIGN_BIT = 0x1000 63 | 64 | RV_OP_FLAG_SIGNED = 1 << 0 65 | 66 | RV_AUX_NOPOST = 0 # no postfix, default for most instructions 67 | 68 | RV_AUX_RL = 0x1 # .rl for atomic 69 | RV_AUX_AQ = 0x2 # .aq for atomic 70 | 71 | RV_AUX_W = 1 72 | RV_AUX_WU = 2 73 | RV_AUX_D = 3 74 | RV_AUX_S = 4 75 | RV_AUX_X = 5 76 | RV_AUX_L = 6 77 | RV_AUX_LU = 7 78 | 79 | # csr instruction (some special handling required) 80 | RV_INSN_CSR = 0x1 81 | 82 | 83 | class riscv_processor_t(processor_t): 84 | id = 0x8000 + 0x100 85 | flag = PR_ASSEMBLE | PR_SEGS | PR_DEFSEG32 | PR_USE32 | PRN_HEX | PR_RNAMESOK | PR_NO_SEGMOVE 86 | cnbits = 8 87 | dnbits = 8 88 | psnames = ['riscv'] 89 | plnames = ['RISC-V ISA'] 90 | segreg_size = 0 91 | tbyte_size = 0 92 | retcodes = ['\x82\x80'] 93 | 94 | instruc = [ 95 | {'name': '', 'feature': 0}, # "not an instruction" 96 | 97 | # RV32I 98 | {'name': 'lui', 'feature': CF_CHG1 | CF_USE2}, 99 | {'name': 'auipc', 'feature': CF_CHG1 | CF_USE2}, 100 | {'name': 'jal', 'feature': CF_CHG1 | CF_USE1 | CF_USE2 | CF_CALL}, 101 | {'name': 'jalr', 'feature': CF_CHG1 | CF_USE2 | CF_CALL}, 102 | {'name': 'beq', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_JUMP}, 103 | {'name': 'bne', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_JUMP}, 104 | {'name': 'blt', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_JUMP}, 105 | {'name': 'bge', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_JUMP}, 106 | {'name': 'bltu', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_JUMP}, 107 | {'name': 'bgeu', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_JUMP}, 108 | {'name': 'lb', 'feature': CF_CHG1 | CF_USE2}, 109 | {'name': 'lh', 'feature': CF_CHG1 | CF_USE2}, 110 | {'name': 'lw', 'feature': CF_CHG1 | CF_USE2}, 111 | {'name': 'lbu', 'feature': CF_CHG1 | CF_USE2}, 112 | {'name': 'lhu', 'feature': CF_CHG1 | CF_USE2}, 113 | {'name': 'sb', 'feature': CF_USE1 | CF_CHG2}, 114 | {'name': 'sh', 'feature': CF_USE1 | CF_CHG2}, 115 | {'name': 'sw', 'feature': CF_USE1 | CF_CHG2}, 116 | {'name': 'addi', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 117 | {'name': 'slti', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 118 | {'name': 'sltiu', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 119 | {'name': 'xori', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 120 | {'name': 'ori', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 121 | {'name': 'andi', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 122 | {'name': 'slli', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 123 | {'name': 'srli', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 124 | {'name': 'srai', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 125 | {'name': 'add', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 126 | {'name': 'sub', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 127 | {'name': 'sll', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 128 | {'name': 'slt', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 129 | {'name': 'sltu', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 130 | {'name': 'xor', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 131 | {'name': 'slr', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 132 | {'name': 'sra', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 133 | {'name': 'or', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 134 | {'name': 'and', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 135 | {'name': 'fence', 'feature': CF_USE1}, 136 | {'name': 'fence.i', 'feature': 0}, 137 | {'name': 'ecall', 'feature': CF_CALL}, 138 | {'name': 'ebreak', 'feature': 0}, 139 | {'name': 'csrrw', 'feature': CF_USE1 | CF_USE2 | CF_USE3}, 140 | {'name': 'csrrs', 'feature': CF_USE1 | CF_USE2 | CF_USE3}, 141 | {'name': 'csrrc', 'feature': CF_USE1 | CF_USE2 | CF_USE3}, 142 | {'name': 'csrrwi', 'feature': CF_USE1 | CF_USE2 | CF_USE3}, 143 | {'name': 'csrrsi', 'feature': CF_USE1 | CF_USE2 | CF_USE3}, 144 | {'name': 'csrrci', 'feature': CF_USE1 | CF_USE2 | CF_USE3}, 145 | 146 | # RV64I 147 | {'name': 'lwu', 'feature': CF_CHG1 | CF_USE2}, 148 | {'name': 'ld', 'feature': CF_CHG1 | CF_USE2}, 149 | {'name': 'sd', 'feature': CF_USE1 | CF_CHG2}, 150 | {'name': 'addiw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 151 | {'name': 'slliw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 152 | {'name': 'srliw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 153 | {'name': 'sraiw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 154 | {'name': 'addw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 155 | {'name': 'subw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 156 | {'name': 'sllw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 157 | {'name': 'srlw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 158 | {'name': 'sraw', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 159 | 160 | # RV32M 161 | {'name': 'mul', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 162 | {'name': 'mulh', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 163 | {'name': 'mulhsu', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 164 | {'name': 'mulhu', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 165 | {'name': 'div', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 166 | {'name': 'divu', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 167 | {'name': 'rem', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 168 | {'name': 'remu', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 169 | 170 | # RV32A / RV64A 171 | {'name': 'lr', 'feature': CF_CHG1 | CF_USE2}, 172 | {'name': 'sc', 'feature': CF_CHG1 | CF_USE2}, 173 | {'name': 'amoswap', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 174 | {'name': 'amoadd', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 175 | {'name': 'amoxor', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 176 | {'name': 'amoand', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 177 | {'name': 'amoor', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 178 | {'name': 'amomin', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 179 | {'name': 'amomax', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 180 | {'name': 'amominu', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 181 | {'name': 'amomaxu', 'feature': CF_CHG1 | CF_USE1 | CF_USE2}, 182 | 183 | # RV32F/RV64F/FV32D/RV64D 184 | {'name': 'flw', 'feature': CF_CHG1 | CF_USE2}, 185 | {'name': 'fld', 'feature': CF_CHG1 | CF_USE2}, 186 | {'name': 'fsw', 'feature': CF_USE1 | CF_CHG2}, 187 | {'name': 'fsd', 'feature': CF_USE1 | CF_CHG2}, 188 | {'name': 'fmadd', 'feature': CF_CHG1 | CF_USE2 | CF_USE3 | CF_USE4}, 189 | {'name': 'fmsub', 'feature': CF_CHG1 | CF_USE2 | CF_USE3 | CF_USE4}, 190 | {'name': 'fnmsub', 'feature': CF_CHG1 | CF_USE2 | CF_USE3 | CF_USE4}, 191 | {'name': 'fnmadd', 'feature': CF_CHG1 | CF_USE2 | CF_USE3 | CF_USE4}, 192 | {'name': 'fadd', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 193 | {'name': 'fsub', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 194 | {'name': 'fmul', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 195 | {'name': 'fdiv', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 196 | {'name': 'fsqrt', 'feature': CF_CHG1 | CF_USE2}, 197 | {'name': 'fsgnj', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 198 | {'name': 'fsgnjn', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 199 | {'name': 'fsgnjx', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 200 | {'name': 'fmin', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 201 | {'name': 'fmax', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 202 | {'name': 'fcvt', 'feature': CF_CHG1 | CF_USE2}, 203 | {'name': 'fmv', 'feature': CF_CHG1 | CF_USE2}, 204 | {'name': 'feq', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 205 | {'name': 'flt', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 206 | {'name': 'fle', 'feature': CF_CHG1 | CF_USE2 | CF_USE3}, 207 | {'name': 'fclass', 'feature': CF_CHG1 | CF_USE2}, 208 | 209 | # pseudo-instructions 210 | {'name': 'nop', 'feature': 0}, 211 | {'name': 'li', 'feature': CF_CHG1 | CF_USE2}, 212 | {'name': 'mv', 'feature': CF_CHG1 | CF_USE2}, 213 | {'name': 'not', 'feature': CF_CHG1 | CF_USE2}, 214 | {'name': 'neg', 'feature': CF_CHG1 | CF_USE2}, 215 | {'name': 'negw', 'feature': CF_CHG1 | CF_USE2}, 216 | {'name': 'sext.w', 'feature': CF_CHG1 | CF_USE2}, 217 | {'name': 'seqz', 'feature': CF_CHG1 | CF_USE2}, 218 | {'name': 'snez', 'feature': CF_CHG1 | CF_USE2}, 219 | {'name': 'sltz', 'feature': CF_CHG1 | CF_USE2}, 220 | {'name': 'sgtz', 'feature': CF_CHG1 | CF_USE2}, 221 | 222 | # branch pseudo-instructions 223 | {'name': 'beqz', 'feature': CF_USE1 | CF_USE2 | CF_JUMP}, 224 | {'name': 'bnez', 'feature': CF_USE1 | CF_USE2 | CF_JUMP}, 225 | {'name': 'blez', 'feature': CF_USE1 | CF_USE2 | CF_JUMP}, 226 | {'name': 'bgez', 'feature': CF_USE1 | CF_USE2 | CF_JUMP}, 227 | {'name': 'bltz', 'feature': CF_USE1 | CF_USE2 | CF_JUMP}, 228 | {'name': 'bgtz', 'feature': CF_USE1 | CF_USE2 | CF_JUMP}, 229 | 230 | # jump/call pseudo-instructions 231 | {'name': 'j', 'feature': CF_USE1 | CF_JUMP}, 232 | {'name': 'jr', 'feature': CF_USE1 | CF_JUMP}, 233 | {'name': 'ret', 'feature': CF_STOP}, 234 | {'name': 'call', 'feature': CF_USE1 | CF_CALL}, 235 | {'name': 'tail', 'feature': CF_USE1 | CF_CALL}, 236 | 237 | # csr pseudo-instructions 238 | {'name': 'rdinstret', 'feature': CF_CHG1}, 239 | {'name': 'rdinstreth', 'feature': CF_CHG1}, 240 | {'name': 'rdcycle', 'feature': CF_CHG1}, 241 | {'name': 'rdcycleh', 'feature': CF_CHG1}, 242 | {'name': 'rdtime', 'feature': CF_CHG1}, 243 | {'name': 'rdtimeh', 'feature': CF_CHG1}, 244 | {'name': 'csrr', 'feature': CF_CHG1 | CF_USE2}, 245 | {'name': 'csrw', 'feature': CF_CHG1 | CF_USE2}, 246 | {'name': 'csrs', 'feature': CF_CHG1 | CF_USE2}, 247 | {'name': 'csrc', 'feature': CF_CHG1 | CF_USE2}, 248 | {'name': 'csrwi', 'feature': CF_CHG1 | CF_USE2}, 249 | {'name': 'csrsi', 'feature': CF_CHG1 | CF_USE2}, 250 | {'name': 'csrci', 'feature': CF_CHG1 | CF_USE2} 251 | ] 252 | instruc_start = 0 253 | instruc_end = len(instruc) - 1 254 | 255 | real_width = (0, 0, 0, 0) 256 | 257 | assembler = { 258 | 'flag': ASH_HEXF0 | ASD_DECF0 | ASO_OCTF5 | ASB_BINF0 | AS_N2CHR, 259 | 'uflag': 0, 260 | 'name': "RISC-V assembler", 261 | 'header': ['.riscv'], 262 | 'origin': '.org', 263 | 'end': '.end', 264 | 'cmnt': ';', 265 | 'ascsep': '"', 266 | 'accsep': "'", 267 | 'esccodes': "\"'", 268 | 'a_ascii': '.char', 269 | 'a_byte': '.byte', 270 | 'a_word': '.short', 271 | 'a_dword': '.long', 272 | 'a_bss': '.space %s', 273 | 'a_equ': '.equ', 274 | 'a_seg': 'seg', 275 | 'a_curip': '$', 276 | 'a_public': '.def', 277 | 'a_weak': '', 278 | 'a_extrn': '.ref', 279 | 'a_comdef': '', 280 | 'a_align': '.align', 281 | 'lbrace': '(', 282 | 'rbrace': ')', 283 | 'a_mod': '%', 284 | 'a_band': '&', 285 | 'a_bor': '|', 286 | 'a_xor': '^', 287 | 'a_bnot': '~', 288 | 'a_shl': '<<', 289 | 'a_shr': '>>', 290 | 'a_sizeof_fmt': 'size %s', 291 | 'flag2': 0, 292 | 'a_include_fmt': '.include "%s"' 293 | } 294 | 295 | def __init__(self): 296 | processor_t.__init__(self) 297 | self.PTRSZ = 4 298 | self.init_instructions() 299 | self.init_registers() 300 | self.init_tables() 301 | if __EA64__: 302 | print "64bit\n" 303 | else: 304 | print "32bit" 305 | 306 | # available postfixes 307 | self.postfixs = ['.w', '.wu', '.d', '.s', '.x', '.l', '.lu'] 308 | 309 | # CSRs number:name dict, some entries will be added during initialization 310 | # to avoid endless repetition 311 | self.csr_names = { 312 | # User Trap Setup 313 | 0x000: 'ustatus', 314 | 0x004: 'uie', 315 | 0x005: 'utvec', 316 | 317 | # User Trap Handling 318 | 0x040: 'uscratch', 319 | 0x041: 'uepc', 320 | 0x042: 'ucause', 321 | 0x043: 'utval', 322 | 0x044: 'uip', 323 | 324 | # User Floating-Point CSRs 325 | 0x001: 'fflags', 326 | 0x002: 'frm', 327 | 0x003: 'fcsr', 328 | 329 | # User Counter/Timers 330 | 0xC00: 'cycle', 331 | 0xC01: 'time', 332 | 0xC02: 'instret', 333 | 334 | # 0xC03-0xC1F: Performance-monitoring counters (see init_csrs) 335 | 0xC80: 'cycleh', 336 | 0xC81: 'timeh', 337 | 0xC82: 'instreth', 338 | 339 | # 0xC83-0xC9F: Upper 32 bits of hpmcounter[xx], RV32I only 340 | 341 | # Machine Trap Setup 342 | 0x300: 'mstatus', 343 | 0x301: 'misa', 344 | 0x302: 'medeleg', 345 | 0x303: 'mideleg', 346 | 0x304: 'mie', 347 | 0x305: 'mtvec', 348 | 0x306: 'mcounteren', 349 | 350 | # Machine Trap Handling 351 | 0x340: 'mscratch', 352 | 0x341: 'mepc', 353 | 0x342: 'mcause', 354 | 0x343: 'mtval', 355 | 0x344: 'mip', 356 | 357 | # Machine Counters / Timers 358 | 0xB00: 'mcycle', 359 | 0xB02: 'minstret', 360 | 361 | # Machine Information Registers 362 | 0xF11: 'mvendorid', 363 | 0xF12: 'marchid', 364 | 0xF13: 'mimpid', 365 | 0xF14: 'mhartid', 366 | 367 | } 368 | self.init_csrs() 369 | 370 | def imm_sign_extend(self, opcode, imm, bits): 371 | if opcode & RV_IMM_SIGN_BIT == RV_IMM_SIGN_BIT: 372 | return SIGNEXT(imm, bits) 373 | return imm 374 | 375 | def decode_u_imm(self, opcode): 376 | return opcode & RV_U_IMM_31_12_MASK 377 | 378 | def decode_j_imm(self, opcode): 379 | imm = (BITS(opcode, 21, 30) << 1) | \ 380 | (BIT(opcode, 20) << 11) | \ 381 | (BITS(opcode, 12, 19) << 12) | \ 382 | (BIT(opcode, 31) << 20) 383 | return self.imm_sign_extend(opcode, imm, 20) 384 | 385 | def decode_i_imm(self, opcode, sign_extend=True): 386 | imm = BITS(opcode, 20, 31) 387 | if opcode & 0x80000000 == 0x80000000 and sign_extend: 388 | return SIGNEXT(imm, 12) 389 | return imm 390 | 391 | def decode_b_imm(self, opcode): 392 | imm = (BITS(opcode, 8, 11) << 1) | \ 393 | (BITS(opcode, 25, 30) << 5) | \ 394 | (BIT(opcode, 7) << 11) | \ 395 | (BIT(opcode, 31) << 12) 396 | return self.imm_sign_extend(opcode, imm, 12) 397 | 398 | def decode_s_imm(self, opcode): 399 | imm = (BITS(opcode, 7, 11)) | \ 400 | (BITS(opcode, 25, 27) << 5) 401 | return self.imm_sign_extend(opcode, imm, 12) 402 | 403 | def decode_rd(self, opcode): 404 | regNo = BITS(opcode, 7, 11) 405 | return regNo 406 | 407 | def decode_rs1(self, opcode): 408 | regNo = BITS(opcode, 15, 19) 409 | return regNo 410 | 411 | def decode_rs2(self, opcode): 412 | regNo = BITS(opcode, 20, 24) 413 | return regNo 414 | 415 | def decode_funct3(self, opcode): 416 | funct3 = BITS(opcode, 12, 14) 417 | return funct3 418 | 419 | def decode_funct7(self, opcode): 420 | funct7 = BITS(opcode, 25, 31) 421 | return funct7 422 | 423 | def op_reg(self, op, regNo, dtype=dt_dword): 424 | op.type = o_reg 425 | op.reg = regNo 426 | op.dtype = dtype 427 | 428 | def op_imm(self, op, imm, signed=True): 429 | op.type = o_imm 430 | op.value = imm 431 | op.dtype = dt_dword 432 | op.specflag1 = 0 433 | if signed: 434 | op.specflag1 |= RV_OP_FLAG_SIGNED 435 | 436 | def op_addr(self, op, addr): 437 | op.type = o_near 438 | op.addr = addr 439 | op.dtype = dt_code 440 | 441 | def op_displ(self, op, base, displ, dtype=dt_dword): 442 | op.type = o_displ 443 | op.reg = base 444 | op.value = displ 445 | op.dtype = dtype 446 | 447 | def set_postfix1(self, insn, value): 448 | insn.auxpref |= (value << 2) 449 | 450 | def set_postfix2(self, insn, value): 451 | insn.auxpref |= (value << 6) 452 | 453 | def decode_LUI(self, insn, opcode): 454 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 455 | self.op_imm(insn.Op2, self.decode_u_imm(opcode), signed=False) 456 | insn.itype = self.itype_lui 457 | 458 | def decode_AUIPC(self, insn, opcode): 459 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 460 | self.op_imm(insn.Op2, insn.ip + self.decode_u_imm(opcode), signed=False) 461 | insn.itype = self.itype_auipc 462 | 463 | def decode_JAL(self, insn, opcode): 464 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 465 | jimm = self.decode_j_imm(opcode) 466 | self.op_addr(insn.Op2, insn.ip + jimm) 467 | insn.itype = self.itype_jal 468 | 469 | def decode_JALR(self, insn, opcode): 470 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 471 | self.op_displ(insn.Op2, self.decode_rs1(opcode), self.decode_i_imm(opcode)) 472 | insn.itype = self.itype_jalr 473 | 474 | def decode_BRANCH(self, insn, opcode): 475 | self.op_reg(insn.Op1, self.decode_rs1(opcode)) 476 | self.op_reg(insn.Op2, self.decode_rs2(opcode)) 477 | self.op_addr(insn.Op3, insn.ip + self.decode_b_imm(opcode)) 478 | insn.itype = [ 479 | self.itype_beq, self.itype_bne, 480 | 0, 0, 481 | self.itype_blt, self.itype_bge, 482 | self.itype_bltu, self.itype_bgeu 483 | ][self.decode_funct3(opcode)] 484 | 485 | 486 | def decode_LOAD(self, insn, opcode): 487 | funct3 = self.decode_funct3(opcode) 488 | optbl = [ 489 | [self.itype_lb, dt_byte], [self.itype_lh, dt_word], 490 | [self.itype_lw, dt_dword], [self.itype_ld, dt_qword], 491 | [self.itype_lbu, dt_byte], [self.itype_lhu, dt_word], [self.itype_lwu, dt_dword] 492 | ] 493 | insn.itype = optbl[funct3][0] 494 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 495 | self.op_displ(insn.Op2, self.decode_rs1(opcode), self.decode_i_imm(opcode), optbl[funct3][1]) 496 | 497 | def decode_STORE(self, insn, opcode): 498 | funct3 = self.decode_funct3(opcode) 499 | optbl = [ 500 | [self.itype_sb, dt_byte], [self.itype_sh, dt_word], [self.itype_sw, dt_dword], 501 | [self.itype_sd, dt_qword] 502 | ] 503 | self.op_reg(insn.Op1, self.decode_rs2(opcode)) 504 | self.op_displ(insn.Op2, self.decode_rs1(opcode), self.decode_s_imm(opcode), optbl[funct3][1]) 505 | insn.itype = optbl[funct3][0] 506 | 507 | def decode_IMM(self, insn, opcode): 508 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 509 | self.op_reg(insn.Op2, self.decode_rs1(opcode)) 510 | funct3 = self.decode_funct3(opcode) 511 | imm = self.decode_i_imm(opcode) 512 | if funct3 == 0b001: 513 | self.op_imm(insn.Op3, imm & 0b11111) 514 | insn.itype = self.itype_slli 515 | elif funct3 == 0b101: 516 | self.op_imm(insn.Op3, imm & 0b11111) 517 | insn.itype = self.itype_srai if imm & 0x400 == 0x400 else self.itype_srli 518 | else: 519 | self.op_imm(insn.Op3, imm) 520 | insn.itype = [ 521 | self.itype_addi, 0, self.itype_slti, 522 | self.itype_sltiu, self.itype_xori, 0, 523 | self.itype_ori, self.itype_andi 524 | ][funct3] 525 | 526 | def decode_OP(self, insn, opcode): 527 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 528 | self.op_reg(insn.Op2, self.decode_rs1(opcode)) 529 | self.op_reg(insn.Op3, self.decode_rs2(opcode)) 530 | funct7 = self.decode_funct7(opcode) 531 | insn.itype = [ 532 | [ 533 | self.itype_add, self.itype_sll, self.itype_slt, self.itype_sltu, 534 | self.itype_xor, self.itype_slr, self.itype_or, self.itype_and 535 | ], 536 | [ 537 | self.itype_mul, self.itype_mulh, self.itype_mulhsu, self.itype_mulhu, 538 | self.itype_div, self.itype_divu, self.itype_rem, self.itype_remu 539 | ] 540 | ][funct7 & 0b1][self.decode_funct3(opcode)] 541 | if funct7 & 0b0100001 == 0b0100000: 542 | if insn.itype == self.itype_add: 543 | insn.itype = self.itype_sub 544 | elif insn.itype == self.itype_slr: 545 | insn.itype = self.itype_sra 546 | 547 | def decode_MISC_MEM(self, insn, opcode): 548 | funct3 = self.decode_funct3(opcode) 549 | if funct3 == 0: 550 | self.op_imm(insn.Op1, self.decode_i_imm(opcode, False)) 551 | insn.itype = self.itype_fence 552 | else: 553 | insn.itype = self.itype_fencei 554 | 555 | def decode_SYSTEM(self, insn, opcode): 556 | rd = self.decode_rd(opcode) 557 | imm = self.decode_i_imm(opcode, sign_extend=False) 558 | rs1_zimm = self.decode_rs1(opcode) 559 | 560 | funct3 = self.decode_funct3(opcode) 561 | if funct3 == 0: 562 | if imm & 0b1 == 0b1: 563 | insn.itype = self.itype_ebreak 564 | else: 565 | insn.itype = self.itype_ecall 566 | else: 567 | insn.itype = [ 568 | self.itype_csrrw, self.itype_csrrs, self.itype_csrrc, 569 | self.itype_csrrwi, self.itype_csrrsi, self.itype_csrrci 570 | ][funct3-1] 571 | i = ord(insn.insnpref) | RV_INSN_CSR 572 | insn.insnpref = chr(i) 573 | self.op_reg(insn.Op1, self.decode_rd(opcode)) 574 | if funct3 < 3: 575 | self.op_reg(insn.Op3, rs1_zimm) 576 | else: 577 | self.op_imm(insn.Op3, rs1_zimm, signed=False) 578 | self.op_imm(insn.Op2, imm, signed=False) 579 | 580 | 581 | def decode_AMO(self, insn, opcode): 582 | rd = self.decode_rd(opcode) 583 | rs1 = self.decode_rs1(opcode) 584 | rs2 = self.decode_rs2(opcode) 585 | funct3 = self.decode_funct3(opcode) 586 | funct7 = self.decode_funct7(opcode) 587 | 588 | # funct3 = 0b010 for RV32A 589 | # funct3 = 0b011 for RV64A 590 | # else invalid? not specified in the ISA, assume invalid... 591 | if funct3 not in [0b010, 0b011]: 592 | return 593 | 594 | # propagate aq/rl suffix to auxpref 595 | insn.auxpref |= (funct7 & 0b11) 596 | 597 | # set 32/64 flag 598 | self.set_postfix1(insn, RV_AUX_W if funct3 & 1 == 0 else RV_AUX_D) 599 | 600 | # extract AMO opcode 601 | a_opcode = BITS(funct7, 2, 7) 602 | insn.itype = { 603 | 0b00010: self.itype_lr, 604 | 0b00011: self.itype_sc, 605 | 0b00001: self.itype_amoswap, 606 | 0b00000: self.itype_amoadd, 607 | 0b00100: self.itype_amoxor, 608 | 0b01100: self.itype_amoand, 609 | 0b01000: self.itype_amoor, 610 | 0b10000: self.itype_amomin, 611 | 0b10100: self.itype_amomax, 612 | 0b11000: self.itype_amominu, 613 | 0b11100: self.itype_amomaxu 614 | }[a_opcode] 615 | self.op_reg(insn.Op1, rd) 616 | if insn.itype == self.itype_lr: 617 | self.op_displ(insn.Op2, rs1, 0) 618 | else: 619 | self.op_reg(insn.Op2, rs2) 620 | self.op_displ(insn.Op3, rs1, 0) 621 | 622 | def decode_LOAD_FP(self, insn, opcode): 623 | rd = self.decode_rd(opcode) 624 | rs1 = self.decode_rs1(opcode) 625 | imm = self.decode_i_imm(opcode) 626 | funct3 = self.decode_funct3(opcode) 627 | 628 | # fp-regs start at +32 into reg_names array 629 | self.op_reg(insn.Op1, rd+32) 630 | self.op_displ(insn.Op2, rs1, imm) 631 | insn.itype = self.itype_flw if funct3 & 0b1 == 0 else self.itype_fld 632 | 633 | def decode_STORE_FP(self, insn, opcode): 634 | rs1 = self.decode_rs1(opcode) 635 | rs2 = self.decode_rs2(opcode) 636 | imm = self.decode_s_imm(opcode) 637 | funct3 = self.decode_funct3(opcode) 638 | isfloat = (funct3 & 0b1) == 0 639 | dtype = dt_float if isfloat else dt_double 640 | 641 | self.op_reg(insn.Op1, rs2+32, dtype) 642 | self.op_displ(insn.Op2, rs1, imm, dtype) 643 | insn.itype = self.itype_fsw if isfloat else self.itype_fsd 644 | 645 | def decode_fmadd(self, insn, opcode): 646 | rd = self.decode_rd(opcode) 647 | rs1 = self.decode_rs1(opcode) 648 | rs2 = self.decode_rs2(opcode) 649 | rm = self.decode_funct3(opcode) # rounding mode 650 | rs3 = BITS(opcode, 27, 31) 651 | funct2 = BITS(opcode, 25, 26) 652 | 653 | insn.itype = [ 654 | self.itype_fmadd, self.itype_fmsub, \ 655 | self.itype_fnmsub, self.itype_fnmadd 656 | ][BITS(opcode, 2, 3)] 657 | self.set_postfix1(insn, RV_AUX_S if funct2 == 0 else RV_AUX_D) 658 | 659 | self.op_reg(insn.Op1, rd+32) 660 | self.op_reg(insn.Op2, rs1+32) 661 | self.op_reg(insn.Op3, rs2+32) 662 | self.op_reg(insn.Op4, rs3+32) 663 | 664 | def decode_OP_FP(self, insn, opcode): 665 | rd = self.decode_rd(opcode) 666 | rs1 = self.decode_rs1(opcode) 667 | rs2 = self.decode_rs2(opcode) 668 | funct3 = self.decode_funct3(opcode) 669 | funct7 = self.decode_funct7(opcode) 670 | isfloat = (funct7 & 0b11) == 0 671 | dtype = dt_float if isfloat else dt_double 672 | 673 | sz_postfix = RV_AUX_S if isfloat else RV_AUX_D 674 | 675 | sel = funct7 >> 2 676 | postfix1 = sz_postfix 677 | postfix2 = 0 678 | 679 | if sel < 4: 680 | # fadd, fsub, fmul, fdiv 681 | insn.itype = [self.itype_fadd, self.itype_fsub, self.itype_fmul, self.itype_fdiv][sel] 682 | self.op_reg(insn.Op1, rd + 32, dtype) 683 | self.op_reg(insn.Op2, rs1 + 32, dtype) 684 | self.op_reg(insn.Op3, rs2 + 32, dtype) 685 | elif sel == 0b01011: 686 | # fsqrt 687 | insn.itype = self.itype_fsqrt 688 | self.op_reg(insn.Op1, rd + 32, dtype) 689 | self.op_reg(insn.Op2, rs1 + 32, dtype) 690 | elif sel == 0b00100: 691 | # fsgnj, fsgnjn, fsgnjx 692 | insn.itype = [self.itype_fsgnj, self.itype_fsgnjn, self.itype_fsgnjx][funct3] 693 | self.op_reg(insn.Op1, rd + 32, dtype) 694 | self.op_reg(insn.Op2, rs1 + 32, dtype) 695 | self.op_reg(insn.Op3, rs2 + 32, dtype) 696 | elif sel == 0b10100: 697 | # feq, flt, fle 698 | insn.itype = [self.itype_fle, self.itype_flt, self.itype_feq][funct3] 699 | self.op_reg(insn.Op1, rd, dt_qword if __EA64__ else dt_dword) 700 | self.op_reg(insn.Op2, rs1 + 32, dtype) 701 | self.op_reg(insn.Op3, rs2 + 32, dtype) 702 | elif sel == 0b01000: 703 | # fcvt[.s|.d][.d|.s] 704 | if rs2 == 0 or rs2 == 1: 705 | optbl = [[RV_AUX_S, dt_float], [RV_AUX_D, dt_double]] 706 | insn.itype = self.itype_fcvt 707 | postfix2 = optbl[rs2][0] 708 | self.op_reg(insn.Op1, rd + 32, dtype) 709 | self.op_reg(insn.Op2, rs1 + 32, optbl[rs2][1]) 710 | elif sel == 0b00101: 711 | # fmin, fmax 712 | insn.itype = [self.itype_fmin, self.itype_fmax][funct3] 713 | self.op_reg(insn.Op1, rd + 32, dtype) 714 | self.op_reg(insn.Op2, rs1 + 32, dtype) 715 | self.op_reg(insn.Op3, rs2 + 32, dtype) 716 | elif sel == 0b11010 or sel == 0b11000: 717 | cvtsel = BIT(sel, 1) 718 | # fcvt[.w|.wu|.l|.lu][.s] or fcvt[.s][.w|.wu|.l|.lu] 719 | optbl = [[RV_AUX_W, dt_dword], [RV_AUX_WU, dt_dword], [RV_AUX_L, dt_qword], [RV_AUX_LU, dt_qword]] 720 | cvttbl = [ 721 | [rd, rs1+32, optbl[rs2][1], dtype, optbl[rs2][0], sz_postfix], 722 | [rd+32, rs1, dtype, optbl[rs2][1], sz_postfix, optbl[rs2][0]] 723 | ] 724 | insn.itype = self.itype_fcvt 725 | self.op_reg(insn.Op1, cvttbl[cvtsel][0], cvttbl[cvtsel][2]) 726 | self.op_reg(insn.Op2, cvttbl[cvtsel][1], cvttbl[cvtsel][3]) 727 | postfix1 = cvttbl[cvtsel][4] 728 | postfix2 = cvttbl[cvtsel][5] 729 | elif sel == 0b11110 or sel == 0b11100: 730 | cvtsel = BIT(sel, 1) 731 | if funct3 == 1: 732 | if cvtsel == 0: 733 | # fclass 734 | insn.itype = self.itype_fclass 735 | self.op_reg(insn.Op1, rd, dt_qword if __EA64__ else dt_dword) 736 | self.op_reg(insn.Op2, rs1 + 32, dtype) 737 | else: 738 | # fmv[.w|.d][.x] or fmv[.x][.w|.d] 739 | insn.itype = self.itype_fmv 740 | if cvtsel == 0: 741 | self.op_reg(insn.Op1, rd, dt_qword if __EA64__ else dt_dword) 742 | self.op_reg(insn.Op2, rs1+32, dtype) 743 | postfix1 = RV_AUX_X 744 | postfix2 = RV_AUX_W if dtype == dt_float else RV_AUX_D 745 | else: 746 | self.op_reg(insn.Op1, rd+32, dtype) 747 | self.op_reg(insn.Op2, rs1, dt_qword if __EA64__ else dt_dword) 748 | postfix1 = RV_AUX_W if dtype == dt_float else RV_AUX_D 749 | postfix2 = RV_AUX_X 750 | 751 | self.set_postfix1(insn, postfix1) 752 | self.set_postfix2(insn, postfix2) 753 | 754 | def decode_compressed(self, insn): 755 | opcode = insn.get_next_word() 756 | # some quick exists 757 | if opcode == 0: 758 | # invalid instruction 759 | insn.itype = self.itype_null 760 | return insn.size 761 | if opcode == 1: 762 | # nop 763 | insn.itype = self.itype_addi 764 | self.op_reg(insn.Op1, self.ireg_zero) 765 | self.op_reg(insn.Op2, self.ireg_zero) 766 | self.op_imm(insn.Op3, 0) 767 | return insn.size 768 | 769 | # default to invalid instruction 770 | insn.itype = self.itype_null 771 | 772 | copcode = BITS(opcode, 13, 15) 773 | 774 | q = opcode & 0b11 775 | is_signed = (opcode & RV_C_IMM_SIGN_BIT) == RV_C_IMM_SIGN_BIT 776 | # quadrant 0 777 | if q == 0: 778 | rs1 = BITS(opcode, 7, 9) 779 | rd_rs2 = BITS(opcode, 2, 4) 780 | if copcode != 0: 781 | # a lookup table is used for compressed load/store 782 | # they make up most of compressed instructions in an average executable 783 | decoder = self.c_q0[copcode-1] 784 | if decoder[0] != self.itype_null: 785 | insn.itype = decoder[0] 786 | self.op_reg(insn.Op1, decoder[2][rd_rs2]) 787 | self.op_displ(insn.Op2, self.ciregs[rs1], decoder[1](opcode)) 788 | else: 789 | insn.itype = self.itype_addi 790 | imm = (BIT(opcode, 5) << 3) | (BIT(opcode, 6) << 2) | \ 791 | (BITS(opcode, 7, 10) << 6) | (BITS(opcode, 11, 12) << 4) 792 | self.op_reg(insn.Op1, self.ciregs[rd_rs2]) 793 | self.op_reg(insn.Op2, self.ireg_sp) 794 | self.op_imm(insn.Op3, imm) 795 | elif q == 1: 796 | rs1_rd = BITS(opcode, 7, 9) 797 | rs2 = BITS(opcode, 2, 4) 798 | if copcode == 0: 799 | imm = (BITS(opcode, 2, 6)) | (BIT(opcode, 12) << 5) 800 | if is_signed: 801 | imm = SIGNEXT(imm, 6) 802 | rd = BITS(opcode, 7, 11) 803 | self.op_reg(insn.Op1, rd) 804 | self.op_reg(insn.Op2, rd) 805 | self.op_imm(insn.Op3, imm) 806 | insn.itype = self.itype_addi 807 | elif copcode == 0b001: 808 | # RV32 only 809 | imm = (BIT(opcode, 2) << 5) | (BITS(opcode, 3, 5) << 1) | \ 810 | (BIT(opcode, 6) << 7) | (BIT(opcode, 7) << 6) | \ 811 | (BIT(opcode, 8) << 10) | (BITS(opcode, 9, 10) << 8) | \ 812 | (BIT(opcode, 11) << 4) | (BIT(opcode, 12) << 11) 813 | if is_signed: 814 | imm = SIGNEXT(imm, 12) 815 | self.op_reg(insn.Op1, self.ireg_ra) 816 | self.op_addr(insn.Op2, insn.ip + imm) 817 | insn.itype = self.itype_jal 818 | elif copcode == 0b010: 819 | imm = (BITS(opcode, 2, 6)) | (BIT(opcode, 12) << 5) 820 | if is_signed: 821 | imm = SIGNEXT(imm, 6) 822 | self.op_reg(insn.Op1, BITS(opcode, 7, 11)) 823 | self.op_reg(insn.Op2, self.ireg_zero) 824 | self.op_imm(insn.Op3, imm) 825 | insn.itype = self.itype_addi 826 | elif copcode == 0b011: 827 | rs1_rd = BITS(opcode, 7, 11) 828 | # C.ADDI16SP variant 829 | if rs1_rd == 2: 830 | imm = (BIT(opcode, 2) << 5) | (BITS(opcode, 3, 4) << 7) | \ 831 | (BIT(opcode, 5) << 6) | (BIT(opcode, 6) << 4) | (BIT(opcode, 12) << 9) 832 | if is_signed: 833 | imm = SIGNEXT(imm, 10) 834 | self.op_reg(insn.Op1, self.ireg_sp) 835 | self.op_reg(insn.Op2, self.ireg_sp) 836 | self.op_imm(insn.Op3, imm) 837 | insn.itype = self.itype_addi 838 | else: 839 | imm = (BITS(opcode, 2, 6) << 12) | (BIT(opcode, 12) << 17) 840 | if is_signed: 841 | imm = SIGNEXT(imm, 18) 842 | self.op_reg(insn.Op1, rs1_rd) 843 | self.op_imm(insn.Op2, imm) 844 | insn.itype = self.itype_lui 845 | elif copcode == 0b100: 846 | imm = (BITS(opcode, 2, 6)) | (BIT(opcode, 12) << 5) 847 | if is_signed: 848 | imm = SIGNEXT(imm, 6) 849 | sel1 = BITS(opcode, 10, 11) 850 | sel2 = BITS(opcode, 5, 6) 851 | self.op_reg(insn.Op1, self.ciregs[rs1_rd]) 852 | self.op_reg(insn.Op2, self.ciregs[rs1_rd]) 853 | if sel1 < 3: 854 | insn.itype = [self.itype_srli, self.itype_srai, self.itype_andi][sel1] 855 | if sel1 < 2: 856 | imm = imm & 0b11111 if imm != 0 else 64 857 | self.op_imm(insn.Op3, imm) 858 | elif sel1 == 0b11: 859 | insn.itype =[self.itype_sub, self.itype_xor, self.itype_or, self.itype_and][sel2] 860 | self.op_reg(insn.Op3, self.ciregs[rs2]) 861 | if BIT(opcode, 12) == 1: 862 | if insn.itype == self.itype_sub: 863 | insn.itype = self.itype_subw 864 | elif insn.itype == self.itype_xor: 865 | insn.itype = self.itype_addw 866 | elif copcode == 0b101: 867 | imm = (BIT(opcode, 2) << 5) | (BITS(opcode, 3, 5) << 1) | \ 868 | (BIT(opcode, 6) << 7) | (BIT(opcode, 7) << 6) | \ 869 | (BIT(opcode, 8) << 10) | (BITS(opcode, 9, 10) << 8) | \ 870 | (BIT(opcode, 11) << 4) | (BIT(opcode, 12) << 11) 871 | if is_signed: 872 | imm = SIGNEXT(imm, 12) 873 | self.op_reg(insn.Op1, self.ireg_zero) 874 | self.op_addr(insn.Op2, insn.ip + imm) 875 | insn.itype = self.itype_jal 876 | elif copcode > 0b101: 877 | insn.itype = [self.itype_beq, self.itype_bne][copcode - 0b110] 878 | imm = (BIT(opcode, 2) << 5) | (BITS(opcode, 3,4) << 1) | (BITS(opcode, 5, 6) << 6) | \ 879 | (BITS(opcode, 10, 11) << 3) | (BIT(opcode, 12) << 8) 880 | if is_signed: 881 | imm = SIGNEXT(imm, 9) 882 | self.op_reg(insn.Op1, self.ciregs[rs1_rd]) 883 | self.op_reg(insn.Op2, self.ireg_zero) 884 | self.op_addr(insn.Op3, insn.ip + imm) 885 | elif q == 2: 886 | rs1_rd = BITS(opcode, 7, 11) 887 | rs2 = BITS(opcode, 2, 6) 888 | if copcode == 0b000: 889 | imm = (BITS(opcode, 2, 6)) | (BIT(opcode, 12)) 890 | self.op_reg(insn.Op1, rs1_rd) 891 | self.op_reg(insn.Op2, rs1_rd) 892 | self.op_imm(insn.Op3, imm if imm != 0 else 64) 893 | insn.itype = self.itype_slli 894 | elif copcode == 0b001: 895 | imm = (BITS(opcode, 2, 4) << 6) | (BITS(opcode, 5, 6) << 3) 896 | self.op_reg(insn.Op1, rs1_rd+32) 897 | self.op_displ(insn.Op2, self.ireg_sp, imm) 898 | insn.itype = self.itype_fld 899 | elif copcode == 0b010: 900 | imm = (BITS(opcode, 2, 3) << 6) | (BITS(opcode, 4, 6) << 2) | (BIT(opcode, 12) << 5) 901 | self.op_reg(insn.Op1, rs1_rd) 902 | self.op_displ(insn.Op2, self.ireg_sp, imm) 903 | insn.itype = self.itype_lw 904 | elif copcode == 0b011: 905 | imm = (BITS(opcode, 2, 4) << 6) | (BITS(opcode, 3, 4) << 3) | (BIT(opcode, 12) << 5) 906 | self.op_reg(insn.Op1, rs1_rd+32) 907 | self.op_displ(insn.Op2, self.ireg_sp, imm) 908 | insn.itype = self.itype_flw 909 | elif copcode == 0b100: 910 | sel1 = BIT(opcode, 12) 911 | if sel1 == 0: 912 | if rs2 == 0: 913 | self.op_reg(insn.Op1, self.ireg_zero) 914 | self.op_reg(insn.Op2, rs1_rd) 915 | self.op_imm(insn.Op3, 0) 916 | insn.itype = self.itype_jalr 917 | else: 918 | self.op_reg(insn.Op1, rs1_rd) 919 | self.op_reg(insn.Op2, self.ireg_zero) 920 | self.op_reg(insn.Op3, rs2) 921 | insn.itype = self.itype_add 922 | else: 923 | if rs2 == 0: 924 | if rs1_rd == 0: 925 | insn.itype = self.itype_ebreak 926 | else: 927 | self.op_reg(insn.Op1, self.ireg_ra) 928 | self.op_reg(insn.Op2, rs1_rd) 929 | self.op_imm(insn.Op3, 0) 930 | insn.itype = self.itype_jalr 931 | else: 932 | self.op_reg(insn.Op1, rs1_rd) 933 | self.op_reg(insn.Op2, rs1_rd) 934 | self.op_reg(insn.Op3, rs2) 935 | insn.itype = self.itype_add 936 | elif copcode == 0b101: 937 | imm = (BITS(opcode, 7, 9) << 6) | (BITS(opcode, 10, 12) << 3) 938 | self.op_reg(insn.Op1, rs2) 939 | self.op_displ(insn.Op2, self.ireg_sp, imm) 940 | insn.itype = self.itype_fsd 941 | elif copcode == 0b110: 942 | imm = (BITS(opcode, 7, 8) << 6) | (BITS(opcode, 9, 12) << 2) 943 | self.op_reg(insn.Op1, rs2) 944 | self.op_displ(insn.Op2, self.ireg_sp, imm) 945 | insn.itype = self.itype_sw 946 | 947 | if insn.itype != self.itype_null: 948 | return insn.size 949 | print "returning unknown for 0x%08x" % (insn.ea) 950 | return 0 951 | 952 | def decode_normal(self, insn): 953 | # normal instructions are 32bit aligned 954 | opcode = insn.get_next_dword() 955 | maj_opcode = BITS(opcode, 0, 6) 956 | try: 957 | self.maj_opcodes[maj_opcode](insn, opcode) 958 | if insn.size == 0: 959 | raise UnknownInstruction() 960 | return insn.size 961 | except (KeyError, UnknownInstruction) as e: 962 | print "error: 0x%08x - %s" % (insn.ea, str(e)) 963 | return 0 964 | 965 | # rewrite one instruction into a simpler form 966 | def simplify(self, insn): 967 | # addi rd, zero, imm -> [li rd, imm] | [nop] 968 | # addi rd, rs, 0 -> [mv rd, rs] 969 | if insn.itype == self.itype_addi: 970 | if insn.Op2.reg == self.ireg_zero: 971 | if insn.Op1.reg != self.ireg_zero: 972 | insn.itype = self.itype_li 973 | insn.Op2.assign(insn.Op3) 974 | insn.Op3.type = o_void 975 | elif insn.Op3.value == 0: 976 | insn.itype = self.itype_nop 977 | insn.Op1.type = o_void 978 | insn.Op2.type = o_void 979 | insn.Op3.type = o_void 980 | elif insn.Op3.value == 0: 981 | insn.itype = self.itype_mv 982 | insn.Op3.type = o_void 983 | elif insn.itype == self.itype_add: 984 | # add rd, zero, rs2 -> [mv rd, rs2] 985 | if insn.Op2.reg == self.ireg_zero: 986 | insn.itype = self.itype_mv 987 | insn.Op2.assign(insn.Op3) 988 | insn.Op3.type = o_void 989 | elif insn.itype == self.itype_xori: 990 | if fix_sign_32(insn.Op3.value) == -1: 991 | insn.itype = self.itype_not 992 | insn.Op3.type = o_void 993 | elif insn.itype == self.itype_sub: 994 | if insn.Op2.reg == self.ireg_zero: 995 | insn.itype = self.itype_neg 996 | insn.Op2.assign(insn.Op3) 997 | insn.Op3.type = o_void 998 | elif insn.itype == self.itype_jal: 999 | if insn.Op1.reg == self.ireg_zero: 1000 | insn.itype = self.itype_j 1001 | insn.Op1.assign(insn.Op2) 1002 | insn.Op2.type = o_void 1003 | elif insn.Op1.reg == self.ireg_ra: 1004 | insn.Op1.assign(insn.Op2) 1005 | insn.Op2.type = o_void 1006 | elif insn.itype == self.itype_jalr: 1007 | if insn.Op1.reg == self.ireg_zero: 1008 | if insn.Op2.reg == self.ireg_ra: 1009 | insn.itype = self.itype_ret 1010 | insn.Op1.type = o_void 1011 | insn.Op2.type = o_void 1012 | insn.Op3.type = o_void 1013 | else: 1014 | insn.itype = self.itype_jr 1015 | insn.Op1.assign(insn.Op2) 1016 | insn.Op2.type = o_void 1017 | elif insn.Op1.reg == self.ireg_ra: 1018 | insn.Op1.assign(insn.Op2) 1019 | insn.Op2.type = o_void 1020 | elif insn.itype == self.itype_beq and insn.Op2.reg == self.ireg_zero: 1021 | insn.itype = self.itype_beqz 1022 | insn.Op2.assign(insn.Op3) 1023 | insn.Op3.type = o_void 1024 | elif insn.itype == self.itype_bne and insn.Op2.reg == self.ireg_zero: 1025 | insn.itype = self.itype_bnez 1026 | insn.Op2.assign(insn.Op3) 1027 | insn.Op3.type = o_void 1028 | elif insn.itype == self.itype_bge and insn.Op1.reg == self.ireg_zero: 1029 | insn.itype = self.itype_blez 1030 | insn.Op1.assign(insn.Op2) 1031 | insn.Op2.assign(insn.Op3) 1032 | insn.Op3.type = o_void 1033 | elif insn.itype == self.itype_bge and insn.Op2.reg == self.ireg_zero: 1034 | insn.itype = self.itype_bgez 1035 | insn.Op2.assign(insn.Op3) 1036 | insn.Op3.type = o_void 1037 | elif insn.itype == self.itype_blt and insn.Op2.reg == self.ireg_zero: 1038 | insn.itype = self.itype_bltz 1039 | insn.Op2.assign(insn.Op3) 1040 | insn.Op3.type = o_void 1041 | elif insn.itype == self.itype_blt and insn.Op1.reg == self.ireg_zero: 1042 | insn.itype = self.itype_bgtz 1043 | insn.Op1.assign(insn.Op2) 1044 | insn.Op2.assign(insn.Op3) 1045 | insn.Op3.type = o_void 1046 | elif ord(insn.insnpref) & RV_INSN_CSR == RV_INSN_CSR: 1047 | csr = insn.Op2.value 1048 | 1049 | # these CSRs produce a pseudo-instruction rdXXX 1050 | if 0xC00 <= csr <= 0xC02 or 0xC80 <= csr <= 0xC82: 1051 | instrs = ['rdinstret', 'rdcycle', 'rdtime'] 1052 | iname = "itype_" + instrs[csr & 0x00F] 1053 | if csr & 0x080 == 0x080: 1054 | iname += 'h' 1055 | insn.itype = getattr(self, iname) 1056 | insn.Op2.type = o_void 1057 | insn.Op3.type = o_void 1058 | else: 1059 | insn.itype = { 1060 | self.itype_csrrw: self.itype_csrw, 1061 | self.itype_csrrs: self.itype_csrs, 1062 | self.itype_csrrc: self.itype_csrc, 1063 | self.itype_csrrwi: self.itype_csrwi, 1064 | self.itype_csrrsi: self.itype_csrsi, 1065 | self.itype_csrrci: self.itype_csrci 1066 | }[insn.itype] 1067 | 1068 | if insn.Op3.reg == self.ireg_zero: 1069 | insn.Op3.type = o_void 1070 | elif insn.Op1.reg == self.ireg_zero: 1071 | insn.Op1.assign(insn.Op2) 1072 | insn.Op2.assign(insn.Op3) 1073 | insn.Op3.type = o_void 1074 | 1075 | def handle_operand(self, insn, op, r): 1076 | flags = get_flags(insn.ea) 1077 | is_offs = is_off(flags, op.n) 1078 | optype = op.type 1079 | feats = insn.get_canon_feature() 1080 | 1081 | itype = insn.itype 1082 | if optype == o_near: 1083 | if feats & CF_CALL: 1084 | insn.add_cref(op.addr, op.offb, fl_CN) 1085 | elif feats & CF_JUMP: 1086 | insn.add_cref(op.addr, op.offb, fl_JN) 1087 | 1088 | def init_instructions(self): 1089 | i = 0 1090 | for x in self.instruc: 1091 | if x['name'] != '': 1092 | setattr(self, 'itype_' + x['name'].replace('.', '_'), i) 1093 | else: 1094 | setattr(self, 'itype_null', i) 1095 | i += 1 1096 | 1097 | def init_registers(self): 1098 | # using ABI names by default 1099 | self.reg_names = [ 1100 | # integer registers 1101 | 'zero', # hard-wired zero 1102 | 'ra', # return address 1103 | 'sp', # stack pointer 1104 | 'gp', # global pointer 1105 | 'tp', # thread pointer 1106 | 't0', # temporary/alternate link register 1107 | 't1', 't2', # temporaries 1108 | 's0', # saved register/frame pointer 1109 | 's1', # saved register 1110 | 'a0', 'a1', # function arguments/return values 1111 | 'a2', 'a3', 'a4', 'a5', 'a6', 'a7', # function arguments 1112 | 's2', 's3', 's4', 's5', 's6', 's7', 's8', 's9', 's10', 's11', # saved registers 1113 | 't3', 't4', 't5', 't6', # temporaries 1114 | 1115 | # floating point registers 1116 | 'ft0', 'ft1', 'ft2', 'ft3', 'ft4', 'ft5', 'ft6', 'ft7', 1117 | 'fs0', 'fs1', 1118 | 'fa0', 'fa1', 1119 | 'fa2', 'fa3', 'fa4', 'fa5', 'fa6', 'fa7', 1120 | 'fs2', 'fs3', 'fs4', 'fs5', 'fs6', 'fs7', 'fs8', 'fs9', 'fs10', 'fs11', 1121 | 'ft8', 'ft9', 'ft10', 'ft11', 1122 | 'vCS', # fake cs 1123 | 'vDS' # fake ds 1124 | ] 1125 | 1126 | for i in xrange(len(self.reg_names)): 1127 | setattr(self, 'ireg_' + self.reg_names[i], i) 1128 | 1129 | self.reg_first_sreg = self.ireg_vCS 1130 | self.reg_last_sreg = self.ireg_vDS 1131 | self.reg_code_sreg = self.ireg_vCS 1132 | self.reg_data_sreg = self.ireg_vDS 1133 | 1134 | # compressed integer registers 1135 | self.ciregs = [ 1136 | self.ireg_s0, self.ireg_s1, 1137 | self.ireg_a0, self.ireg_a1, 1138 | self.ireg_a2, self.ireg_a3, 1139 | self.ireg_a4, self.ireg_a5 1140 | ] 1141 | 1142 | # compressed floating point registers 1143 | self.cfregs = [ 1144 | self.ireg_fs0, self.ireg_fs1, 1145 | self.ireg_fa0, self.ireg_fa1, 1146 | self.ireg_fa2, self.ireg_fa3, 1147 | self.ireg_fa4, self.ireg_fa5 1148 | ] 1149 | 1150 | def init_csrs(self): 1151 | for i in xrange(3, 32): 1152 | self.csr_names[0xC00+i] = "hpmcounter%d" % (i) 1153 | self.csr_names[0xC80+i] = "hpmcounter%dh" % (i) 1154 | 1155 | # initializes some decoding tables to speedup decoding a bit (only for some frequent instructions) 1156 | def init_tables(self): 1157 | 1158 | # main decoder, dispatches decoding depending on major opcode 1159 | self.maj_opcodes = { 1160 | RV_LUI: self.decode_LUI, 1161 | RV_AUIPC: self.decode_AUIPC, 1162 | RV_JAL: self.decode_JAL, 1163 | RV_JALR: self.decode_JALR, 1164 | RV_BRANCH: self.decode_BRANCH, 1165 | RV_LOAD: self.decode_LOAD, 1166 | RV_STORE: self.decode_STORE, 1167 | RV_IMM: self.decode_IMM, 1168 | RV_OP: self.decode_OP, 1169 | RV_MISC_MEM: self.decode_MISC_MEM, 1170 | RV_SYSTEM: self.decode_SYSTEM, 1171 | RV_AMO: self.decode_AMO, 1172 | RV_STORE_FP: self.decode_STORE_FP, 1173 | RV_LOAD_FP: self.decode_LOAD_FP, 1174 | RV_FMADD: self.decode_fmadd, 1175 | RV_FMSUB: self.decode_fmadd, 1176 | RV_FNMADD: self.decode_fmadd, 1177 | RV_FNMSUB: self.decode_fmadd, 1178 | RV_OP_FP: self.decode_OP_FP 1179 | } 1180 | 1181 | # compressed instructions for load and store, quadrant 0 1182 | # format: [itype, decode_immediate(..), reg_list] 1183 | # these are the most common compressed instructions 1184 | self.c_q0 = [ 1185 | # 001 1186 | [self.itype_fld, lambda opcode: (BITS(opcode, 10, 12) << 3) | (BITS(opcode, 5, 6) << 6), 1187 | self.cfregs], 1188 | # 010 1189 | [self.itype_lw, lambda opcode: (BIT(opcode, 6) << 2) | (BITS(opcode, 10, 12) << 3) | (BIT(opcode, 5) << 6), 1190 | self.ciregs], 1191 | # 011 1192 | [self.itype_flw, lambda opcode: (BIT(opcode, 6) << 2) | (BITS(opcode, 10, 12) << 3) | (BIT(opcode, 5) << 6), 1193 | self.cfregs], 1194 | # 100 1195 | [self.itype_null, None, None], 1196 | # 101 1197 | [self.itype_fsd, lambda opcode: (BITS(opcode, 10, 12) << 3) | (BITS(opcode, 5, 6) << 6), 1198 | self.cfregs], 1199 | # 110 1200 | [self.itype_sw, lambda opcode: (BIT(opcode, 5) << 6) | (BIT(opcode, 6) << 2) | (BITS(opcode, 10, 12) << 3), 1201 | self.ciregs], 1202 | # 111 1203 | [self.itype_fsw, lambda opcode: (BIT(opcode, 6) << 2) | (BITS(opcode, 10, 12) << 3) | (BIT(opcode, 5) << 6), 1204 | self.cfregs] 1205 | ] 1206 | 1207 | # TODO: setup loader hooks and inject correct ELF type 1208 | #def notify_init(self, idp_file): 1209 | 1210 | #def notify_get_frame_retsize(self, func_ea): 1211 | # return 4 1212 | 1213 | # auto-comments are disabled 1214 | def notify_get_autocmt(self, insn): 1215 | pass 1216 | 1217 | # verify if this instruction is acceptable 1218 | def notify_is_sane_insn(self, insn, no_crefs): 1219 | opcode = get_byte(insn.ea) & RV_MAJ_OPCODE_MASK 1220 | if opcode in self.maj_opcodes or (opcode & RV_C_MASK != RV_C_MASK): 1221 | return 1 1222 | return -1 1223 | 1224 | # emulate one instruction, used mainly to crefs and drefs 1225 | # and to establish general program flow 1226 | # TODO: add stack tracing 1227 | def notify_emu(self, insn): 1228 | feats = insn.get_canon_feature() 1229 | 1230 | if feats & CF_USE1: 1231 | self.handle_operand(insn, insn.Op1, 1) 1232 | elif feats & CF_CHG1: 1233 | self.handle_operand(insn, insn.Op1, 0) 1234 | 1235 | if feats & CF_USE2: 1236 | self.handle_operand(insn, insn.Op2, 1) 1237 | elif feats & CF_CHG2: 1238 | self.handle_operand(insn, insn.Op2, 0) 1239 | 1240 | if feats & CF_USE3: 1241 | self.handle_operand(insn, insn.Op3, 1) 1242 | 1243 | if feats & CF_JUMP or feats & CF_CALL: 1244 | remember_problem(PR_JUMP, insn.ea) 1245 | 1246 | # flow, best part in IDAPro :D 1247 | if feats & CF_STOP == 0: 1248 | add_cref(insn.ea, insn.ea + insn.size, fl_F) 1249 | return 1 1250 | 1251 | def notify_out_operand(self, ctx, op): 1252 | optype = op.type 1253 | if optype == o_reg: 1254 | ctx.out_register(self.reg_names[op.reg]) 1255 | elif optype == o_imm: 1256 | if ord(ctx.insn.insnpref) & RV_INSN_CSR == RV_INSN_CSR: 1257 | ctx.out_register(self.csr_names[op.value]) 1258 | else: 1259 | opflag = OOFW_IMM | OOFW_32 | OOF_NUMBER 1260 | if op.specflag1 & RV_OP_FLAG_SIGNED == RV_OP_FLAG_SIGNED: 1261 | opflag |= OOF_SIGNED 1262 | ctx.out_value(op, opflag) 1263 | elif optype == o_near: 1264 | ctx.out_name_expr(op, op.addr, BADADDR) 1265 | elif optype == o_displ: 1266 | if op.value != 0: 1267 | ctx.out_value(op, OOF_OUTER | OOFW_32 | OOF_SIGNED) 1268 | ctx.out_symbol('(') 1269 | ctx.out_register(self.reg_names[op.reg]) 1270 | ctx.out_symbol(')') 1271 | else: 1272 | return False 1273 | return True 1274 | 1275 | def out_mnem(self, ctx): 1276 | auxpref = ctx.insn.auxpref 1277 | postfix = "" 1278 | 1279 | if auxpref != 0: 1280 | aqrl = BITS(auxpref, 0, 1) # extract aq/rl pattern (if present) 1281 | postfix1 = BITS(auxpref, 2, 5) # extract first postfix 1282 | postfix2 = BITS(auxpref, 6, 9) # extract second postfix 1283 | if postfix1 != 0: 1284 | postfix = self.postfixs[postfix1-1] 1285 | if postfix2 != 0: 1286 | postfix += self.postfixs[postfix2-1] 1287 | if aqrl & 0b10 == 0b10: 1288 | postfix += ".aq" 1289 | if aqrl & 0b01 == 0b01: 1290 | postfix += ".rl" 1291 | 1292 | ctx.out_mnem(14, postfix) 1293 | 1294 | def notify_out_insn(self, ctx): 1295 | # nothing special to be done here 1296 | ctx.out_mnemonic() 1297 | 1298 | # output all operands 1299 | # number are HEX by default, ugly for negative numbers... 1300 | if ctx.insn.Op1.type != o_void: 1301 | ctx.out_one_operand(0) 1302 | 1303 | for i in xrange(1,4): 1304 | if ctx.insn[i].type == o_void: 1305 | break 1306 | ctx.out_symbol(',') 1307 | ctx.out_char(' ') 1308 | ctx.out_one_operand(i) 1309 | ctx.flush_outbuf() 1310 | 1311 | def notify_ana(self, insn): 1312 | # instructions must be aligned 1313 | # TODO: check for eventual CPU features in cfg? 1314 | if (insn.ea & 1) != 0: 1315 | return 0 1316 | 1317 | # some default values 1318 | insn.auxpref = RV_AUX_NOPOST 1319 | insn.insnpref = '' 1320 | insn.itype = self.itype_null 1321 | 1322 | # determine if this is a compressed instruction 1323 | # TODO: add support for extended format 1324 | b = get_byte(insn.ea) 1325 | if b & RV_C_MASK != RV_C_MASK: 1326 | retval = self.decode_compressed(insn) 1327 | else: 1328 | retval = self.decode_normal(insn) 1329 | 1330 | # if we got a valid instruction, simplify it 1331 | if insn.itype != self.itype_null: 1332 | self.simplify(insn) 1333 | 1334 | return retval 1335 | 1336 | 1337 | def PROCESSOR_ENTRY(): 1338 | return riscv_processor_t() -------------------------------------------------------------------------------- /tests/Makefile: -------------------------------------------------------------------------------- 1 | SUBDIRS = riscv32 #\ 2 | riscv64 3 | 4 | all: $(SUBDIRS) 5 | $(SUBDIRS): 6 | $(MAKE) -C $@ 7 | 8 | .PHONY: all $(SUBDIRS) 9 | 10 | clean: 11 | $(MAKE) -C $(SUBDIRS) clean 12 | -------------------------------------------------------------------------------- /tests/riscv32/Makefile: -------------------------------------------------------------------------------- 1 | AS=riscv32-unknown-elf-as 2 | CC=riscv32-unknown-elf-gcc 3 | OBJCOPY=riscv32-unknown-elf-objcopy 4 | OBJ=test_RV32I.o test_RV32M.o test_RV32A.o test_RV32F_RV32D.o 5 | BIN=test_RV32A.bin test_RV32M.bin test_RV32F_RV32D.bin 6 | ELF=test_RV32I.elf 7 | 8 | %.o: %.s 9 | $(AS) -o $@ $< 10 | 11 | %.bin: %.o 12 | $(OBJCOPY) -O binary $< $@ 13 | 14 | %.elf: %.o 15 | $(CC) -nostdlib -o $@ $< 16 | chmod -x $@ 17 | 18 | test: $(BIN) $(ELF) 19 | 20 | .PHONY: clean 21 | 22 | clean: 23 | rm -f *.bin *.o *.elf 24 | -------------------------------------------------------------------------------- /tests/riscv32/test_RV32A.s: -------------------------------------------------------------------------------- 1 | .section .text 2 | .global _start 3 | _start: 4 | li a0, 1 5 | mv a1, a0 6 | lr.w t0, 0(a0) 7 | lr.w.aq t0, 0(a0) 8 | lr.w.rl t0, 0(a0) 9 | sc.w a0, a2, (a0) 10 | sc.w.aq a0, a2, (a0) 11 | sc.w.rl a0, a2, (a0) 12 | amoswap.w a0, a3, (a1) 13 | amoadd.w a0, a3, (a1) 14 | amoand.w a0, a3, (a1) 15 | amoor.w a0, a3, (a1) 16 | amoxor.w a0, a3, (a1) 17 | amomax.w a0, a3, (a1) 18 | amomin.w a0, a3, (a1) 19 | amomaxu.w a0, a3, (a1) 20 | amominu.w a0, a3, (a1) 21 | -------------------------------------------------------------------------------- /tests/riscv32/test_RV32F_RV32D.s: -------------------------------------------------------------------------------- 1 | .section .text 2 | .global _start 3 | _start: 4 | ## float 5 | # load/store 6 | flw ft0, 8(a0) 7 | fsw ft0, 8(a0) 8 | 9 | # multiply-add 10 | fmadd.s ft0, ft1, ft2, ft4 11 | fmsub.s ft1, ft2, ft3, ft5 12 | fnmadd.s ft0, ft1, ft2, ft4 13 | fnmsub.s ft1, ft2, ft3, ft5 14 | 15 | # op 16 | fadd.s ft0, ft1, ft2 17 | fsub.s ft0, ft1, ft2 18 | fmul.s ft0, ft1, ft2 19 | fdiv.s ft0, ft1, ft2 20 | 21 | # sqrt 22 | fsqrt.s ft0, ft1 23 | 24 | # fsgnj 25 | fsgnj.s ft0, ft1, ft2 26 | fsgnjn.s ft0, ft1, ft2 27 | fsgnjx.s ft0, ft1, ft2 28 | 29 | # fmin/fmax 30 | fmin.s ft0, ft1, ft2 31 | fmax.s ft0, ft1, ft2 32 | 33 | # fcvt.s 34 | fcvt.w.s a0, ft0 35 | fcvt.wu.s a0, ft0 36 | 37 | # fmv 38 | fmv.x.w a0, ft0 39 | 40 | # feq/flt/fle 41 | feq.s a0, ft0, ft1 42 | flt.s a0, ft0, ft1 43 | fle.s a0, ft0, ft1 44 | 45 | # fclass 46 | fclass.s a0, ft0 47 | 48 | # fcvt.s 49 | fcvt.s.w ft0, a0 50 | fcvt.s.wu ft0, a0 51 | 52 | # fmv 53 | fmv.w.x ft0, a0 54 | 55 | ## double 56 | fld ft0, 8(a0) 57 | fsd ft0, 8(a0) 58 | 59 | # multiply-add 60 | fmadd.d ft0, ft1, ft2, ft4 61 | fmsub.d ft1, ft2, ft3, ft5 62 | fnmadd.d ft0, ft1, ft2, ft4 63 | fnmsub.d ft1, ft2, ft3, ft5 64 | 65 | # op 66 | fadd.d ft0, ft1, ft2 67 | fsub.d ft0, ft1, ft2 68 | fmul.d ft0, ft1, ft2 69 | fdiv.d ft0, ft1, ft2 70 | 71 | # sqrt 72 | fsqrt.d ft0, ft1 73 | 74 | # fsgnj 75 | fsgnj.d ft0, ft1, ft2 76 | fsgnjn.d ft0, ft1, ft2 77 | fsgnjx.d ft0, ft1, ft2 78 | 79 | # fmin/fmax 80 | fmin.d ft0, ft1, ft2 81 | fmax.d ft0, ft1, ft2 82 | 83 | fcvt.s.d ft0, ft1 84 | fcvt.d.s ft2, ft3 85 | fcvt.s.d fa0, fa1 86 | fcvt.d.s fa1, fa2 87 | 88 | # fcvt.s 89 | fcvt.w.d a0, ft0 90 | fcvt.wu.d a0, ft0 91 | 92 | # feq/flt/fle 93 | feq.d a0, ft0, ft1 94 | flt.d a0, ft0, ft1 95 | fle.d a0, ft0, ft1 96 | 97 | # fclass 98 | fclass.d a0, ft0 99 | 100 | # fcvt 101 | fcvt.d.w ft0, a0 102 | fcvt.d.wu ft0, a0 103 | -------------------------------------------------------------------------------- /tests/riscv32/test_RV32I.s: -------------------------------------------------------------------------------- 1 | .section .text 2 | .global _start 3 | _start: 4 | lui a0, %hi(0x40010000) 5 | addi a0, a0, %lo(0x40010000) 6 | 1: auipc a0, %pcrel_hi(bogus) 7 | addi a0, a0, %pcrel_lo(1b) 8 | 1: 9 | li a0, 0x12345678 10 | li a1, 0xabcdef12 11 | li a2, 0x34abcdef 12 | nop 13 | jal 1b 14 | jalr t0 15 | beq a0, a1, 2f 16 | bne a0, a1, 2f 17 | blt a0, a1, 2f 18 | bge a0, a1, 2f 19 | bltu a0, a1, 2f 20 | bgeu a0, a1, 2f 21 | 2: 22 | lb t0, 8(a0) 23 | lh t0, 8(a1) 24 | lw t0, 8(a2) 25 | lbu t0, 8(a3) 26 | lhu t0, 8(a4) 27 | sb t0, 8(a0) 28 | sh t0, 8(a1) 29 | sw t0, 8(a2) 30 | 31 | 3: 32 | addi a0, a1, -5 33 | addi a2, a3, 5 34 | addi t0, t1, -578 35 | addi a0, a1, 542 36 | 37 | andi a0, a1, 0x23 38 | andi a2, a3, 0x11 39 | 40 | slti a0, a1, 4 41 | sltiu a1, a2, 5 42 | 43 | xori t2, t3, 0x23 44 | xori a0, a1, 0x11 45 | 46 | ori s0, s1, 0x32 47 | ori s1, a1, 0x11 48 | 49 | slli s0, s1, 8 50 | srli a1, a4, 30 51 | srai a1, a5, 30 52 | 53 | add a0, a1, a2 54 | sub a3, a4, a5 55 | sll s0, s1, s2 56 | slt s1, a2, a1 57 | sltu a0, a1, a2 58 | xor a0, a1, a2 59 | srl a0, a1, a2 60 | sra s0, s1, s2 61 | or a1, a2, a3 62 | and s0, a1, t0 63 | bogus: 64 | .long 0xDEADDEAD 65 | -------------------------------------------------------------------------------- /tests/riscv32/test_RV32M.s: -------------------------------------------------------------------------------- 1 | .section .text 2 | .global _start 3 | _start: 4 | mul a0, a1, s2 5 | mul a2, a3, s1 6 | mul s0, s1, a0 7 | mul t0, t1, t1 8 | mulh a0, a2, a3 9 | mulhsu t0, s2, t4 10 | mulhu t1, t2, s4 11 | div a0, a1, a4 12 | divu a2, a3, a0 13 | rem a0, a1, a1 14 | remu a2, a3, a4 15 | -------------------------------------------------------------------------------- /tests/riscv64/Makefile: -------------------------------------------------------------------------------- 1 | AS=riscv64-unknown-elf-as 2 | OBJCOPY=riscv64-unknown-elf-objcopy 3 | OBJ= 4 | BIN= 5 | 6 | %.o: %.s 7 | $(AS) -o $@ $< 8 | 9 | %.bin: %.o 10 | $(OBJCOPY) -O binary $< $@ 11 | 12 | test: $(BIN) 13 | 14 | .PHONY: clean 15 | 16 | clean: 17 | rm -f *.bin *.o 18 | --------------------------------------------------------------------------------