├── .github └── workflows │ └── test.yml ├── .gitignore ├── CHANGELOG.md ├── LICENSE ├── Makefile ├── README.md ├── examples ├── Makefile ├── Scientific.vhd ├── based.vhd ├── bigfile.vhd ├── clk.vhd ├── concat.vhd ├── counters.vhd ├── dsp.vhd ├── exclude ├── expr.vhd ├── fifo.vhd ├── forgen.vhd ├── forloop.vhd ├── genericmap.vhd ├── ifchain.vhd ├── ifchain2.vhd ├── mem.vhd ├── operators.vhd ├── partselect.vhd ├── signextend.vhd ├── test.vhd ├── todo.vhd ├── wbit1.vhd ├── whileloop.vhd └── withselect.vhd ├── src ├── def.h ├── makefile ├── vhd2vl.l └── vhd2vl.y └── translated_examples ├── Makefile ├── Scientific.v ├── based.v ├── bigfile.v ├── clk.v ├── concat.v ├── counters.v ├── dsp.v ├── expr.v ├── fifo.v ├── forgen.v ├── forloop.v ├── genericmap.v ├── ifchain.v ├── ifchain2.v ├── mem.v ├── operators.v ├── partselect.v ├── signextend.v ├── test.v ├── wbit1.v ├── whileloop.v └── withselect.v /.github/workflows/test.yml: -------------------------------------------------------------------------------- 1 | name: vhd2vl 2 | 3 | on: [push] 4 | 5 | jobs: 6 | test: 7 | runs-on: ${{ matrix.os }} 8 | strategy: 9 | matrix: 10 | os: [ubuntu-24.04, ubuntu-22.04, ubuntu-20.04] 11 | steps: 12 | - name: Checkout code 13 | uses: actions/checkout@v2 14 | - name: Install dependencies 15 | run: sudo apt-get update && sudo apt-get install -y build-essential flex bison iverilog 16 | - name: Build 17 | run: make 18 | - name: Install and print version 19 | run: sudo make install && vhd2vl --version 20 | - name: Test 21 | run: make test 22 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | temp 2 | ignore 3 | 4 | src/*.c 5 | src/*.h 6 | src/*.output 7 | src/vhd2vl 8 | 9 | examples/*.o 10 | examples/*.cf 11 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | Changes 3.0 to (unreleased): 2 | * Clean up examples to yield better Verilog output 3 | * Fewer stupid parentheses in Verilog output 4 | * Emit indexed part select Verilog syntax (+: or -:) when possible 5 | * Improved WARNING messages 6 | * Use ',' to separate sensitivity list in Verilog 2001 output 7 | * Support ** as exponentiation operator 8 | * Partial support for while and assert, contributed by jeinstei 9 | * Minor build system improvements, now might work on macOS 10 | 11 | 12 | Changes 2.5 to 3.0 (Rodrigo A. Melo, February 2017): 13 | * Github-ization, including converting text to markdown 14 | * Better Verilog standard selection, and make 2001 the default 15 | * New --quiet option 16 | * Support scientific notation for floats 17 | * Use GHDL to test example VHDL input, corrected problems discovered 18 | * Yosys-compatible whitespace in \'\\ notation output 19 | 20 | 21 | Changes 2.4 to 2.5 (Larry Doolittle, September 2015) 22 | 23 | Coding: 24 | * Use $(CC) in makefile 25 | * Trivial fix to yacc grammar, was causing FTBFS with recent bison 26 | * Eliminate a couple of unused variables 27 | 28 | 29 | Changes 2.3 to 2.4 (Larry Doolittle, November 2010) 30 | 31 | Grammar: 32 | * drop DOS-style returns at end of comments 33 | * allow FLOAT in expressions (maybe a mistake) 34 | * fixed regression in "others" handling since 2.1 35 | * don't crash with "others" in instantiation (Verilog result is still broken) 36 | 37 | Grammar submitted by Shankar Giri: 38 | * Verilog 2001 module declaration (runtime selectable, use -g2001) 39 | * named generate block support for XST compatibility 40 | * support for array of vectors 41 | * some generic enhancements on architecture body 42 | 43 | Coding: 44 | * CLI enhancement (added more switches) 45 | * factor out push_clkedge(), pull_clkedge() 46 | * fully const-correct 47 | * minor whitespace and coding style cleanup 48 | 49 | 50 | Changes 2.2 to 2.3 (Larry Doolittle, May 2010) 51 | 52 | Grammar: 53 | * add array type (not well tested) 54 | * add octal strings (O"777") 55 | * add one more "rem" 56 | * accept octal and hex strings as "when" values 57 | * accept constants, bit ranges, and "open" in port mappings 58 | * accept a single un-named generic map item 59 | * accept conv_integer function, treated as a no-op 60 | * accept ports with default values, but ignore default and give a warning 61 | * accept integer ranges, but ignore the range and give a warning 62 | 63 | Coding: 64 | * list def.h properly in makefile 65 | * factor out new_vrange(), addnest(), setup_port() 66 | 67 | 68 | Changes 1.2 to 2.2 (Larry Doolittle, February 2009) 69 | 70 | Merge extensive changes from Mark Gonzales' version 2.0. Thanks, Mark! 71 | 72 | Grammar: 73 | * add XNOR 74 | * add hex strings (X"f0f0") 75 | * remove UNIT reserved words, and actually emit timescale directive 76 | * case statements without "when others" 77 | * add a few more "rem"s to the grammar 78 | * add resize to the CONVFUNC_2 list 79 | * handle one-bit enumeration bit range correctly (no more [0]) 80 | * some gratuitous changes in output whitespace 81 | 82 | Coding: 83 | * clean up GENERIC pattern 84 | * debug and clean up slist routines and their usage 85 | * wrap malloc with xmalloc to exit if out of memory 86 | * update Free Software Foundation address 87 | 88 | 89 | Changes 2.0 to 2.1 (Steve Haynal, unreleased?) 90 | 91 | Presumably useful to Steve, but everything is too strange or scary 92 | for me (Larry Doolittle) to understand and incorporate. Sorry, Steve, 93 | maybe I'll get something from your work on my next iteration. People 94 | interested in the following features (incomplete list) should contact 95 | the developers directly: 96 | * lower-cased identifiers in translated Verilog 97 | * parses VHDL packages 98 | * parses many VHDL functions and macros 99 | * floating-point "after" construct parsed but ignored 100 | 101 | 102 | Changes 1.0 to 2.0 (Mark Gonzales, June 2006) 103 | 104 | Grammar: 105 | * FOR LOOP 106 | * FOR GENERATE and IF GENERATE 107 | * natural, integer, time types 108 | * based numbers (16#55aa#) 109 | * expressions can now include VHDL type conversion functions, mod operator, numbers 110 | * now can tolerate comments in the middle of expressions 111 | * expressions can now be used in subscripts and vector range definitions 112 | * width on (others => 'x') can now be an expression 113 | * uses always @(*) when creating some combinational always blocks 114 | * variable initialization support 115 | * constant can be initialized by an expression 116 | * GENERIC definitions for entity are now translated into Verilog 117 | parameter definitions, and GENERIC MAPs on instances are translated 118 | into Verilog in-line explicit parameter definitions. 119 | * allow entity declarations and architectures in separate files 120 | 121 | Operation: 122 | * new -d option for trace parse - to debug grammar errors 123 | 124 | Coding: 125 | * introduce slist data structure to build resulting Verilog 126 | 127 | 128 | Changes 1.0 to 1.2 (Larry Doolittle, May 2005) 129 | 130 | Grammar: 131 | * allow NATURAL as an expression terminal symbol 132 | * allow (name'event and exprc) as process sensitivity 133 | * allow IS syntactic sugar in COMPONENT declaration 134 | * add a bunch of "rem"s to the grammar 135 | * handle inout better 136 | * treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector" 137 | 138 | Operation: 139 | * more complete handling of argc/argv 140 | * if error happened, return 1 from main and remove incorrect/incomplete output files 141 | * avoid insinuating that output Verilog is covered by GPL 142 | 143 | Coding: 144 | * increase gcc warning level 145 | * add required #includes 146 | * remove spurious commas in bison token lists 147 | * drop worthless malloc() casts; see C-faq/q7.7 148 | * prototype yylex and yyerror 149 | * add braces around confusing if/else chain 150 | 151 | Original 1.0 (Vincenzo Liguori, February 2001) 152 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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It is safest 289 | to attach them to the start of each source file to most effectively 290 | convey the exclusion of warranty; and each file should have at least 291 | the "copyright" line and a pointer to where the full notice is found. 292 | 293 | 294 | Copyright (C) 295 | 296 | This program is free software; you can redistribute it and/or modify 297 | it under the terms of the GNU General Public License as published by 298 | the Free Software Foundation; either version 2 of the License, or 299 | (at your option) any later version. 300 | 301 | This program is distributed in the hope that it will be useful, 302 | but WITHOUT ANY WARRANTY; without even the implied warranty of 303 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 304 | GNU General Public License for more details. 305 | 306 | You should have received a copy of the GNU General Public License along 307 | with this program; if not, write to the Free Software Foundation, Inc., 308 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this 313 | when it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author 316 | Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 317 | This is free software, and you are welcome to redistribute it 318 | under certain conditions; type `show c' for details. 319 | 320 | The hypothetical commands `show w' and `show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | , 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | TEMP = temp 4 | 5 | EXCLUDE = $(shell cat examples/exclude) 6 | EXCLUDE := $(basename $(EXCLUDE)) 7 | EXCLUDE := $(addsuffix .vhd,$(EXCLUDE)) 8 | 9 | VHDLS = $(sort $(wildcard examples/*.vhd)) 10 | VHDLS := $(notdir $(VHDLS)) 11 | 12 | DIFFOPT = --exclude=Makefile 13 | 14 | ifndef WIP 15 | VHDLS := $(filter-out $(EXCLUDE),$(VHDLS)) 16 | DIFFOPT := $(DIFFOPT) --exclude-from=examples/exclude 17 | endif 18 | 19 | PREFIX ?= /usr/local 20 | BINDIR ?= $(PREFIX)/bin 21 | BINARY = src/vhd2vl 22 | 23 | all: $(BINARY) 24 | 25 | build $(BINARY): 26 | make -C src 27 | 28 | install: $(BINARY) 29 | cp $< $(BINDIR) 30 | 31 | test: $(BINARY) 32 | @make -C examples 33 | @rm -fr $(TEMP)/verilog && mkdir -p $(TEMP)/verilog 34 | @echo "##### Translating Examples #####################################" 35 | @cd examples; $(foreach VHDL,$(VHDLS), echo "Translating: $(VHDL)";\ 36 | ../$(BINARY) --quiet $(VHDL) ../$(TEMP)/verilog/$(basename $(VHDL)).v;) 37 | @make -C translated_examples 38 | @echo "##### Diff #####################################################" 39 | diff -u $(DIFFOPT) translated_examples $(TEMP)/verilog 40 | @echo "PASS" 41 | 42 | clean: 43 | make -C src clean 44 | rm -fr $(TEMP) 45 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # VHD2VL v3.0 2 | 3 | Vhd2vl is designed to translate synthesizable VHDL into Verilog 1995 or 2001. 4 | It does not support the full VHDL grammar - most of the testbench 5 | related features have been left out. See the examples and 6 | translated_examples directories for examples of what vhd2vl can do. 7 | 8 | Vhd2vl does a pretty good job of translating, but you should ALWAYS 9 | test the generated Verilog, ideally by using a formal verification 10 | tool to compare it to the original VHDL! 11 | 12 | A similar but more sophisticated effort is embedded in Icarus Verilog 13 | as vhdlpp, mostly by Maciej Suminski. If hands-free use of VHDL in a 14 | (Icarus) Verilog environment is the goal, that's probably a better tool. 15 | If you want to convert a bit of VHDL to Verilog, and will then maintain 16 | that Verilog as source, vhd2vl probably makes more sense, if for no other 17 | reason than it conserves comments. It's good that both options exist! 18 | You may find that your VHDL style is better accepted by one tool or the other. 19 | 20 | The home page for (at least this version of) vhd2vl is 21 | http://doolittle.icarus.com/~larry/vhd2vl/ 22 | 23 | ## 1.0 HOW TO BUILD AND INSTALL vhd2vl: 24 | 25 | Install the required dependencies for building and testing: 26 | ``` 27 | sudo apt install build-essential flex bison iverilog 28 | ``` 29 | 30 | To build, just type `make` in the src directory. 31 | 32 | This version of vhd2vl has been tested with 33 | * Debian 7 (Wheezy): gcc-4.7.2, bison-2.5, flex-2.5.35, glibc-2.13 34 | * Debian 8 (Jessie): gcc-4.9.2 or clang-3.5.0, bison-3.0.2, flex-2.5.39, glibc-2.19 35 | * Debian 9 (Stretch): gcc-6.3.0 or clang-3.8.1, bison-3.0.4, flex-2.6.1, glibc-2.24 36 | 37 | It is also verified to work with recent tinycc from its git mob. 38 | This is portable C89/C99 code. It can be expected to work with any 39 | fairly recent version of the required tools. 40 | 41 | To install, you can either type `make install` to copy the resulting src/vhd2vl 42 | file to */usr/local/bin*, or copy it manually to someplace in your *$PATH*, like 43 | *$HOME/bin*. 44 | 45 | ## 2.0 HOW TO USE vhd2vl: 46 | 47 | ``` 48 | vhd2vl VHDL_file.vhd > translated_file.v 49 | ``` 50 | or 51 | ``` 52 | vhd2vl VHDL_file.vhd translated_file.v 53 | ``` 54 | The two are equivalent when everything works. The latter has some 55 | advantages when handling errors within a Makefile. 56 | 57 | There are a few options available on the command line: 58 | * `--debug` turn ON debugging within the yacc (bison) parser 59 | * `--src 1995|2001` to specify module declaration style 60 | * `--quiet` to avoid print vhd2vl header in translated_file.v 61 | * `--version` to print vhd2vl version and info from git, if available 62 | 63 | ## 3.0 TROUBLESHOOTING: 64 | 65 | If vhd2vl complains about a syntax error, this is usually due to a 66 | VHDL construct that vhd2vl cannot translate. Try commenting out the 67 | offending line, and running vhd2vl again. You can then edit the 68 | Verilog output file and manually translate the offending line of VHDL. 69 | 70 | Comments in the middle of statements sometimes confuse vhd2vl. This 71 | is a "feature" of the logic that copies comments from VHDL to Verilog. 72 | If vhd2vl complains about a syntax error caused by a comment, just 73 | move that comment out of the middle of the statement and try again. 74 | 75 | The grammar has rules that recognize common ways of writing clocked 76 | processes. Your code might contain clocked processes that do not match 77 | any of the templates in the grammar. This usually causes vhd2vl to 78 | complain about a clock'event expression in a process. If this 79 | happens, a minor rewrite of that process will let you work around the 80 | problem. 81 | 82 | To test a copy of vhd2vl for regressions against the example code shipped, 83 | run `make` from this directory using a Bourne-style shell. If you have 84 | GHDL and/or iverilog installed, the example VHDL and Verilog code will be 85 | compiled -- and therefore syntax-checked -- with those tools. 86 | 87 | ## 4.0 VHDL PACKAGES 88 | 89 | Vhd2vl does not understand VHDL package files. You might be able to work 90 | around that limitation with the following strategy: 91 | 92 | * Either by hand, or with a stupid script (I wrote mine in awk), break the 93 | package file into individual VHDL files, each named after the entity. 94 | * Use vhd2vl to convert each of those to Verilog. 95 | Test to make sure the conversions went OK. 96 | * Use iverilog's -y switch (or the eqivalent in your tool) to "find" those 97 | files as needed. 98 | 99 | ## 5.0 MISSING FEATURES AND KNOWN INCORRECT OUTPUT: 100 | 101 | String types: awkward, because Verilog strings need predefined length. 102 | 103 | Attribute: easy to parse, but I'm not sure what Verilog construct 104 | to turn it into. It smells like a parameter, not an (* attribute *). 105 | 106 | Multiple actions in one process, as used in DDR logic? 107 | 108 | Exit statement incompletely converted to disable statement. 109 | 110 | Detection of indexed part select is limited. While it can correctly convert 111 | `data(index*8+WIDTH-1 downto index*8)` to `data[index*8+WIDTH-1 -: WIDTH-1+1]` 112 | it gets tripped on slightly more complex cases. The rule is that the 113 | larger expression must take the form `smaller + offset` or `offset + smaller`. 114 | Otherwise the output will be a direct transcription of the VHDL, which is not 115 | standard-conforming unless both ends of the range are constant. 116 | 117 | Conversion functions (resize, to_unsigned, conv_integer) are parsed, but 118 | their semantics are ignored: resize(foo,n), to_unsigned(foo,n), and 119 | conv_integer(foo) are treated as equivalent to foo. 120 | 121 | VHDL is case insensitive, vhd2vl is case retentive, and Verilog is case 122 | sensitive. If you're sloppy with case in the original VHDL, the 123 | resulting Verilog will have compile-time warnings or errors. See 124 | the comments about vhd2vl-2.1 in the changelog file. 125 | 126 | Doesn't handle functions, procedures, or packages. See above for a possible 127 | way to handle packages. 128 | 129 | Doesn't necessarily get clock edge sensitivities right if there is more 130 | than one clock in the list. 131 | 132 | Totally broken handling of text in generic mappings, as Xilinx is wont to 133 | use for their primitives and wrappers. 134 | 135 | Broken (invalid Verilog syntax for) initialization of process-scope variables. 136 | -------------------------------------------------------------------------------- /examples/Makefile: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | TEMP = ../temp/vhdl 4 | 5 | all: 6 | ifneq ($(shell which ghdl),) 7 | @mkdir -p $(TEMP) 8 | @echo "##### Checking examples with GHDL ##############################" 9 | ghdl -a --workdir=$(TEMP) signextend.vhd 10 | ghdl -a --workdir=$(TEMP) *.vhd 11 | endif 12 | 13 | clean: 14 | rm -fr $(TEMP) 15 | -------------------------------------------------------------------------------- /examples/Scientific.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | 4 | entity Scientific is 5 | generic ( 6 | exp1: integer := 25e6; 7 | exp2: integer := 25E6; 8 | exp3: real := 25.0e6; 9 | exp4: real := 50.0e+3; 10 | exp5: real := 50.0e-3 11 | ); 12 | port( 13 | clk : in std_logic 14 | ); 15 | end Scientific; 16 | -------------------------------------------------------------------------------- /examples/based.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all; 3 | 4 | entity based is port( sysclk : in std_logic); 5 | end based; 6 | architecture rtl of based is 7 | signal foo,foo1,foo2,foo8,foo10,foo11,foo16 : integer; 8 | begin 9 | foo <= 123; 10 | foo1 <= 123_456; 11 | foo2 <= 2#00101101110111#; 12 | foo8 <= 8#0177362#; 13 | foo10<= 10#01234#; 14 | --foo11<= 11#01234#; 15 | foo16<= 16#12af#; 16 | end rtl; 17 | -------------------------------------------------------------------------------- /examples/bigfile.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | -- CONNECTIVITY DEFINITION 6 | entity bigfile is 7 | port ( 8 | -- from external pins 9 | sysclk : in std_logic; 10 | g_zaq_in : in std_logic_vector(31 downto 0); 11 | g_aux : in std_logic_vector(31 downto 0); 12 | scanb : in std_logic; 13 | g_wrb : in std_logic; 14 | g_rdb : in std_logic; 15 | g_noop_clr : in std_logic_vector(31 downto 0); 16 | swe_ed : in std_logic; 17 | swe_lv : in std_logic; 18 | din : in std_logic_vector(63 downto 0); 19 | g_dout_w0x0f : in std_logic_vector(4 downto 0); 20 | n9_bit_write : in std_logic; 21 | -- from reset_gen block 22 | reset : in std_logic; 23 | alu_u : in std_logic_vector(31 downto 0); 24 | debct_ping : in std_logic; 25 | g_sys_in : out std_logic_vector(31 downto 0); 26 | g_zaq_in_rst_hold : out std_logic_vector(31 downto 0); 27 | g_zaq_hhh_enb : out std_logic_vector(31 downto 0); 28 | g_zaq_out : out std_logic_vector(31 downto 0); 29 | g_dout : out std_logic_vector(31 downto 0); 30 | g_zaq_ctl : out std_logic_vector(31 downto 0); 31 | g_zaq_qaz_hb : out std_logic_vector(31 downto 0); 32 | g_zaq_qaz_lb : out std_logic_vector(31 downto 0); 33 | gwerth : out std_logic_vector(31 downto 0); 34 | g_noop : out std_logic_vector(31 downto 0); 35 | g_vector : out std_logic_vector(8*32-1 downto 0); 36 | swe_qaz1 : out std_logic_vector(31 downto 0) 37 | ); 38 | end bigfile; 39 | 40 | 41 | -- IMPLEMENTATION 42 | architecture rtl of bigfile is 43 | 44 | -- constants 45 | constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000"; 46 | constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001"; 47 | constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010"; 48 | constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011"; 49 | constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100"; 50 | constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101"; 51 | constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110"; 52 | constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111"; 53 | constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000"; 54 | constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001"; 55 | constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010"; 56 | constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011"; 57 | constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100"; 58 | constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101"; 59 | constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110"; 60 | constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111"; 61 | constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000"; 62 | constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001"; 63 | constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010"; 64 | constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011"; 65 | constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100"; 66 | constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101"; 67 | constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110"; 68 | constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111"; 69 | 70 | -- comment 71 | signal g_t_klim_dout : std_logic_vector(31 downto 0); 72 | signal g_t_u_dout : std_logic_vector(31 downto 0); 73 | signal g_t_l_dout : std_logic_vector(31 downto 0); 74 | signal g_t_hhh_l_dout : std_logic_vector(31 downto 0); 75 | signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0); 76 | signal g_secondary_t_l_dout : std_logic_vector(31 downto 0); 77 | signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used 78 | signal g_e_z_dout : std_logic_vector(31 downto 0); 79 | signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0); 80 | signal g_style_vfr_dout : std_logic_vector(31 downto 0); 81 | signal g_style_klim_dout : std_logic_vector(31 downto 0); 82 | signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0); 83 | signal g_style_t_y_dout : std_logic_vector(31 downto 0); 84 | signal g_n_l_dout : std_logic_vector(31 downto 0); 85 | signal g_n_vfr_dout : std_logic_vector(31 downto 0); 86 | signal g_e_n_r_dout : std_logic_vector(31 downto 0); 87 | signal g_n_r_bne_dout : std_logic; 88 | signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0); 89 | signal g_alu_l_dout : std_logic_vector(31 downto 0); 90 | signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0); 91 | signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0); 92 | signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0); 93 | signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0); 94 | signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0); 95 | 96 | -- other 97 | signal q_g_zaq_in : std_logic_vector(31 downto 0); 98 | signal q2_g_zaq_in : std_logic_vector(31 downto 0); 99 | signal q3_g_zaq_in : std_logic_vector(31 downto 0); 100 | signal q_g_zaq_in_cd : std_logic_vector(3 downto 0); 101 | signal q_g_style_vfr_dout : std_logic_vector(31 downto 0); 102 | signal q_g_unzq : std_logic_vector(3 downto 0); 103 | signal g_n_active : std_logic_vector(31 downto 0); 104 | 105 | -- inter 106 | signal g_zaq_in_y : std_logic_vector(31 downto 0); 107 | signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0); 108 | signal g_zaq_out_i : std_logic_vector(31 downto 0); 109 | signal g_zaq_ctl_i : std_logic_vector(31 downto 0); 110 | signal g_sys_in_i : std_logic_vector(31 downto 0); 111 | signal g_sys_in_ii : std_logic_vector(31 downto 0); 112 | signal g_dout_i : std_logic_vector(31 downto 0); 113 | 114 | begin 115 | 116 | -- qaz out 117 | g_zaq_out_i <= 118 | -- if secondary 119 | (g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or 120 | -- if alu 121 | (g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or 122 | -- otherwise 123 | (not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout); 124 | -- Changed 125 | g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout; 126 | 127 | -- qaz 128 | -- JLB 129 | g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or 130 | (g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i)); 131 | -- mux 132 | --vnavigatoroff 133 | g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000"; 134 | --vnavigatoron 135 | 136 | g_zaq_hhh_enb <= not(g_t_hhh_l_dout); 137 | 138 | g_zaq_qaz_hb <= g_t_qaz_mult_high_dout; 139 | g_zaq_qaz_lb <= g_t_qaz_mult_low_dout; 140 | 141 | 142 | -- Dout 143 | g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else 144 | g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else 145 | g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else 146 | g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else 147 | g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else 148 | g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else 149 | ("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else 150 | g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else 151 | g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else 152 | g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else 153 | g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else 154 | g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else 155 | g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else 156 | g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else 157 | g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else 158 | g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else 159 | ("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else 160 | g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else 161 | g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else 162 | g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else 163 | g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else 164 | gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else 165 | g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else 166 | gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else 167 | "00000000000000000000000000000000"; 168 | g_dout <= g_dout_i when g_rdb = '0' else (others => '1'); 169 | 170 | 171 | -- this can be used to use zzz1 172 | g_style_main_reset_hold_dout_proc : 173 | process(sysclk) 174 | begin 175 | if( sysclk'event and sysclk = '1' ) then 176 | if( scanb = '1' ) then 177 | if( reset = '1' ) then 178 | g_style_main_reset_hold_dout <= g_zaq_in; 179 | end if; 180 | --vnavigatoroff 181 | else 182 | g_style_main_reset_hold_dout <= q2_g_zaq_in; 183 | end if; 184 | --vnavigatoron 185 | end if; 186 | end process; 187 | -- qaz 188 | g_zaq_in_rst_hold <= g_style_main_reset_hold_dout; 189 | 190 | -- Din 191 | g_doutister_proc : 192 | process(reset, sysclk) 193 | variable g_dout_w0x0f_v : std_logic_vector(4 downto 0); 194 | variable i : integer; 195 | variable j : integer; 196 | begin 197 | if( reset /= '0' ) then 198 | g_t_klim_dout <= (others => '0'); 199 | g_t_u_dout <= (others => '0'); 200 | g_t_l_dout <= (others => '0'); 201 | g_t_hhh_l_dout <= (others => '0'); 202 | g_t_jkl_sink_l_dout <= (others => '0'); 203 | g_secondary_t_l_dout <= (others => '0'); 204 | g_style_c_l_dout <= (others => '0'); 205 | g_e_z_dout <= (others => '0'); 206 | g_n_both_qbars_l_dout <= (others => '0'); 207 | g_style_klim_dout <= (others => '0'); 208 | g_style_t_y_dout <= (others => '0'); 209 | g_n_l_dout <= (others => '0'); 210 | g_e_n_r_dout <= (others => '0'); 211 | g_n_r_bne_dout <= '0'; 212 | g_n_div_rebeq_dout <= (others => '1'); 213 | g_alu_l_dout <= (others => '0'); 214 | g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low 215 | g_t_qaz_mult_high_dout <= (others => '0'); 216 | gwerthernal_style_u_dout <= (others => '0'); 217 | gwerthernal_style_l_dout <= (others => '0'); 218 | elsif( sysclk'event and sysclk = '1' ) then 219 | -- clear 220 | g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr; 221 | if( g_wrb = '0' ) then 222 | -- because we now... 223 | for i in 0 to 1 loop 224 | if( i = 0 ) then 225 | g_dout_w0x0f_v := g_dout_w0x0f; 226 | elsif( i = 1 ) then 227 | if( n9_bit_write = '1' ) then 228 | -- set 229 | g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1'; 230 | end if; 231 | --vnavigatoroff 232 | else 233 | -- not possible but added for code coverage's sake 234 | end if; 235 | --vnavigatoron 236 | case g_dout_w0x0f_v is 237 | when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32); 238 | when g_t_u_w0x0f => 239 | -- output klim 240 | for j in 0 to 31 loop 241 | if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then 242 | g_t_u_dout(j) <= din(32*i+j); 243 | end if; 244 | end loop; 245 | when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32); 246 | when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32); 247 | when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32); 248 | when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32); 249 | when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32); 250 | when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32); 251 | when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32); 252 | when g_style_vfr_w0x0f => null; -- read-only register 253 | when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32); 254 | when g_unklimed_style_vfr_w0x0f => null; -- read-only register 255 | when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32); 256 | when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32); 257 | when g_n_vfr_w0x0f => null; -- writes 258 | when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32); 259 | when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32); 260 | when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or 261 | g_n_div_rebeq_dout; -- a '1' writes 262 | when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32); 263 | when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32); 264 | when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32); 265 | when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32); 266 | when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32); 267 | --vnavigatoroff 268 | when others => null; 269 | --vnavigatoron 270 | end case; 271 | end loop; 272 | 273 | end if; 274 | end if; 275 | end process; 276 | 277 | -- sample 278 | g_zaq_in_sample_proc : 279 | process(reset, sysclk) 280 | begin 281 | if( reset /= '0' ) then 282 | q_g_zaq_in <= (others => '0'); 283 | q2_g_zaq_in <= (others => '0'); 284 | q3_g_zaq_in <= (others => '0'); 285 | elsif( sysclk'event and sysclk = '1' ) then 286 | q_g_zaq_in <= g_zaq_in; 287 | q2_g_zaq_in <= q_g_zaq_in; 288 | q3_g_zaq_in <= g_zaq_in_y; 289 | end if; 290 | end process; 291 | 292 | -- vfr register 293 | g_unklimed_style_vfr_dout <= q2_g_zaq_in; 294 | 295 | -- switch 296 | g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in; 297 | 298 | -- qaz 299 | g_style_vfr_dout <= -- top 2 300 | (g_zaq_in_y(31 downto 4) & 301 | -- FSM 302 | (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or 303 | -- otherwise just use 304 | (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0)))); 305 | 306 | -- in scan mode 307 | g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1' 308 | --vnavigatoroff 309 | else g_style_t_y_dout; 310 | --vnavigatoron 311 | 312 | g_sys_in_i <= (-- top 28 313 | (g_zaq_in_y_no_dout(31 downto 4) & 314 | -- is enabled 315 | (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or 316 | -- otherwise just use 317 | (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0))))); 318 | 319 | g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout ); 320 | 321 | g_sys_in <= g_sys_in_ii; 322 | 323 | lpq_proc : 324 | process(reset, sysclk) 325 | variable i : integer; 326 | begin 327 | if( reset /= '0' ) then 328 | q_g_zaq_in_cd <= (others => '0'); 329 | q_g_unzq <= (others => '1'); 330 | elsif( sysclk'event and sysclk = '1' ) then 331 | -- sample 332 | if( debct_ping = '1') then 333 | -- taken 334 | for i in 0 to 3 loop 335 | if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then 336 | q_g_unzq(i) <= '1'; 337 | else 338 | if( q_g_unzq(i) = '0' ) then 339 | q_g_zaq_in_cd(i) <= g_zaq_in_y(i); 340 | else 341 | q_g_unzq(i) <= '0'; 342 | end if; 343 | end if; 344 | end loop; 345 | else 346 | for i in 0 to 3 loop 347 | if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then 348 | q_g_unzq(i) <= '1'; 349 | end if; 350 | end loop; 351 | end if; 352 | end if; 353 | end process; 354 | 355 | -- generate lqqs 356 | sample_forwerth_proc : 357 | process(reset, sysclk) 358 | begin 359 | if( reset /= '0' ) then 360 | q_g_style_vfr_dout <= (others => '0'); 361 | elsif( sysclk'event and sysclk = '1' ) then 362 | if( scanb = '1' ) then 363 | q_g_style_vfr_dout <= g_style_vfr_dout; 364 | --vnavigatoroff 365 | else 366 | -- in scan 367 | q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii; 368 | end if; 369 | --vnavigatoron 370 | end if; 371 | end process; 372 | 373 | -- generate 374 | g_n_active <= -- 1 to 0 375 | (((q_g_style_vfr_dout and not g_style_vfr_dout) or 376 | -- get this 377 | (not q_g_style_vfr_dout and g_style_vfr_dout and 378 | g_n_both_qbars_l_dout))) and 379 | -- must be 380 | g_n_l_dout; 381 | 382 | -- check for lqq active and set lqq vfr register 383 | -- also clear 384 | n_proc : 385 | process(reset, sysclk) 386 | variable i : integer; 387 | begin 388 | if( reset /= '0' ) then 389 | g_n_vfr_dout <= (others => '0'); 390 | gwerth <= (others => '0'); 391 | elsif( sysclk'event and sysclk = '1' ) then 392 | for i in 0 to 31 loop 393 | -- lqq 394 | -- vfr matches 395 | if( g_n_active(i) = '1' ) then 396 | gwerth(i) <= '1'; 397 | if( g_e_z_dout(i) = '1' ) then 398 | -- lqq 399 | g_n_vfr_dout(i) <= '1'; 400 | else 401 | g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); 402 | end if; 403 | else 404 | -- clear 405 | if( g_e_z_dout(i) = '0' ) then 406 | g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign 407 | -- in both 408 | if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then 409 | gwerth(i) <= '0'; 410 | end if; 411 | else 412 | -- write 413 | if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then 414 | gwerth(i) <= '0'; 415 | g_n_vfr_dout(i) <= '0'; 416 | end if; 417 | end if; 418 | end if; 419 | end loop; 420 | end if; 421 | end process; 422 | 423 | ---- 424 | -- Create the Lqq 425 | createwerth_vec_proc : 426 | process( g_n_r_bne_dout, g_e_n_r_dout) 427 | variable imod8, idiv8 : integer; 428 | variable i : integer; 429 | begin 430 | for i in 0 to 31 loop 431 | imod8 := i mod 8; 432 | idiv8 := i / 8; 433 | 434 | if( g_n_r_bne_dout = '0' ) then 435 | -- non-unique 436 | g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); 437 | else 438 | -- unique 439 | if( imod8 = 0 ) then 440 | g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); 441 | else 442 | g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) + 443 | to_unsigned(imod8, 8)); 444 | end if; 445 | end if; 446 | end loop; 447 | end process; 448 | 449 | ---- 450 | -- Qaz 451 | g_noop <= g_n_div_rebeq_dout; 452 | 453 | 454 | create_g_ack_bne_proc : 455 | process( swe_ed,swe_lv,g_e_z_dout) 456 | variable i : integer; 457 | begin 458 | for i in 0 to 31 loop 459 | if( g_e_z_dout(i) = '1') then 460 | swe_qaz1(i) <= swe_ed; 461 | else 462 | swe_qaz1(i) <= swe_lv; 463 | end if; 464 | end loop; 465 | end process; 466 | 467 | end rtl; 468 | -------------------------------------------------------------------------------- /examples/clk.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all; 3 | entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic; 4 | ival : in std_logic_vector(31 downto 0) 5 | ); 6 | end clk; 7 | architecture rtl of clk is 8 | signal foo : std_logic_vector(10+3 downto 0); 9 | signal baz : std_logic_vector(2 downto 0); 10 | signal egg : std_logic_vector(4 to 7-1); 11 | begin 12 | pfoo: process(reset, sysclk) 13 | begin 14 | if( reset /= '0' ) then 15 | foo <= (others => '1'); 16 | elsif( sysclk'event and sysclk = '1' ) then 17 | foo <= ival(31 downto 31-(10+3)); 18 | end if; 19 | end process; 20 | pbaz: process(preset, dsysclk) 21 | begin 22 | if( preset /= '1' ) then 23 | baz <= (others => '0'); 24 | elsif( dsysclk'event and dsysclk = '0' ) then 25 | baz <= ival(2 downto 0); 26 | end if; 27 | end process; 28 | pegg: process(qreset, esysclk) 29 | begin 30 | if( qreset /= '1' ) then 31 | egg <= (others => '0'); 32 | elsif( esysclk'event and esysclk = '0' ) then 33 | egg <= ival(6 downto 4); 34 | end if; 35 | end process; 36 | end rtl; 37 | -------------------------------------------------------------------------------- /examples/concat.vhd: -------------------------------------------------------------------------------- 1 | entity concat_demo is 2 | generic( abc : std_logic_vector(26 downto 0) := "010" & x"aaa"; 3 | xyz : std_logic_vector(31 downto 0) := x"ff" 4 | ); 5 | port(reset : in std_logic 6 | ); 7 | 8 | end entity concat_demo; 9 | -------------------------------------------------------------------------------- /examples/counters.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity counters is 7 | port( 8 | sysclk : in std_logic; 9 | foo_card : in std_logic; 10 | wfoo0_baz : in std_logic; 11 | wfoo0_blrb : in std_logic; 12 | wfoo0_zz1pb : in std_logic; 13 | wfoo0_turn : in std_logic_vector(31 downto 0); 14 | debct_baz : in std_logic; 15 | debct_blrb : in std_logic; 16 | debct_zz1pb : in std_logic; 17 | debct_bar : in std_logic; 18 | debct_turn : in std_logic_vector(31 downto 0); 19 | Z0_bar : in std_logic; 20 | Z0_baz : in std_logic; 21 | Z0_blrb : in std_logic; 22 | Z0_zz1pb : in std_logic; 23 | Z0_turn : in std_logic_vector(31 downto 0); 24 | Y1_bar : in std_logic; 25 | Y1_baz : in std_logic; 26 | Y1_blrb : in std_logic; 27 | Y1_zz1pb : in std_logic; 28 | Y1_turn : in std_logic_vector(31 downto 0); 29 | X2_bar : in std_logic; 30 | X2_baz : in std_logic; 31 | X2_blrb : in std_logic; 32 | X2_zz1pb : in std_logic; 33 | X2_turn : in std_logic_vector(31 downto 0); 34 | W3_bar : in std_logic; 35 | W3_baz : in std_logic; 36 | W3_blrb : in std_logic; 37 | W3_zz1pb : in std_logic; 38 | W3_turn : in std_logic_vector(31 downto 0); 39 | -- to engine block 40 | Z0_cwm : out std_logic; 41 | Z0 : out std_logic_vector(31 downto 0); 42 | Y1_cwm : out std_logic; 43 | Y1 : out std_logic_vector(31 downto 0); 44 | X2_cwm : out std_logic; 45 | X2 : out std_logic_vector(31 downto 0); 46 | W3_cwm : out std_logic; 47 | W3 : out std_logic_vector(31 downto 0); 48 | wfoo0_cwm : out std_logic; 49 | wfoo0_llwln : out std_logic_vector(31 downto 0); 50 | debct_cwm : out std_logic; 51 | debct_pull : out std_logic; 52 | debct : out std_logic_vector(31 downto 0); 53 | wdfilecardA2P : out std_logic 54 | ); 55 | end counters; 56 | 57 | architecture rtl of counters is 58 | 59 | signal wfoo0_llwln_var : unsigned(31 downto 0); 60 | signal debct_var : unsigned(31 downto 0); 61 | signal Z0_var : unsigned(31 downto 0); 62 | signal Y1_var : unsigned(31 downto 0); 63 | signal X2_var : unsigned(31 downto 0); 64 | signal W3_var : unsigned(31 downto 0); 65 | signal main_wfoo0_cwm : std_logic; 66 | signal do_q3p_Z0 : std_logic; 67 | signal do_q3p_Y1 : std_logic; 68 | signal do_q3p_X2 : std_logic; 69 | signal do_q3p_W3 : std_logic; 70 | signal do_q3p_wfoo0 : std_logic; 71 | signal do_q3p_debct : std_logic; 72 | 73 | signal Z0_cwm_i : std_logic; 74 | signal Y1_cwm_i : std_logic; 75 | signal X2_cwm_i : std_logic; 76 | signal W3_cwm_i : std_logic; 77 | signal debct_cwm_i : std_logic; 78 | 79 | signal file_card_i : std_logic; 80 | signal do_file_card_i : std_logic; 81 | signal prev_do_file_card : std_logic; 82 | 83 | begin 84 | 85 | ----- 86 | -- form the outputs 87 | wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var); 88 | debct <= std_logic_vector(debct_var); 89 | Z0 <= std_logic_vector(Z0_var); 90 | Y1 <= std_logic_vector(Y1_var); 91 | X2 <= std_logic_vector(X2_var); 92 | W3 <= std_logic_vector(W3_var); 93 | Z0_cwm <= Z0_cwm_i; 94 | Y1_cwm <= Y1_cwm_i; 95 | X2_cwm <= X2_cwm_i; 96 | W3_cwm <= W3_cwm_i; 97 | debct_cwm <= debct_cwm_i; 98 | 99 | wdfilecardA2P <= do_file_card_i; 100 | 101 | LLWLNS : 102 | process(foo_card, sysclk) 103 | begin 104 | if foo_card = '1' then 105 | wfoo0_llwln_var <= (others => '0'); 106 | debct_var <= (others => '0'); 107 | Z0_var <= (others => '0'); 108 | Y1_var <= (others => '0'); 109 | X2_var <= (others => '0'); 110 | W3_var <= (others => '0'); 111 | 112 | wfoo0_cwm <= '0'; 113 | debct_cwm_i <= '0'; 114 | debct_pull <= '0'; 115 | Z0_cwm_i <= '0'; 116 | Y1_cwm_i <= '0'; 117 | X2_cwm_i <= '0'; 118 | W3_cwm_i <= '0'; 119 | main_wfoo0_cwm <= '0'; 120 | file_card_i <= '0'; 121 | 122 | do_q3p_wfoo0 <= '0'; 123 | do_file_card_i <= '0'; 124 | prev_do_file_card <= '0'; 125 | 126 | do_q3p_Z0 <= '0'; 127 | do_q3p_Y1 <= '0'; 128 | do_q3p_X2 <= '0'; 129 | do_q3p_W3 <= '0'; 130 | do_q3p_debct <= '0'; 131 | 132 | else 133 | if sysclk'event and sysclk = '1' then 134 | 135 | -- pull 136 | debct_pull <= '0'; 137 | do_file_card_i <= '0'; 138 | 139 | ---- 140 | -- wfoo0 141 | 142 | if wfoo0_baz = '1' then 143 | wfoo0_llwln_var <= unsigned(wfoo0_turn); 144 | main_wfoo0_cwm <= '0'; 145 | if wfoo0_llwln_var = "00000000000000000000000000000000" then 146 | do_q3p_wfoo0 <= '0'; 147 | else 148 | do_q3p_wfoo0 <= '1'; 149 | end if; 150 | else 151 | if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then 152 | wfoo0_llwln_var <= wfoo0_llwln_var - 1; 153 | if (wfoo0_llwln_var = "00000000000000000000000000000000") then 154 | wfoo0_llwln_var <= unsigned(wfoo0_turn); 155 | if main_wfoo0_cwm = '0' then 156 | wfoo0_cwm <= '1'; 157 | main_wfoo0_cwm <= '1'; 158 | else 159 | do_file_card_i <= '1'; 160 | do_q3p_wfoo0 <= '0'; 161 | end if; 162 | end if; 163 | end if; 164 | end if; 165 | 166 | if wfoo0_zz1pb = '0' then 167 | wfoo0_cwm <= '0'; 168 | end if; 169 | 170 | if Z0_baz = '1' then -- counter Baz 171 | Z0_var <= unsigned(Z0_turn); 172 | if Z0_turn = "00000000000000000000000000000000" then 173 | do_q3p_Z0 <= '0'; 174 | else 175 | do_q3p_Z0 <= '1'; 176 | end if; 177 | else 178 | if do_q3p_Z0 = '1' and Z0_blrb = '1' then 179 | if Z0_bar = '0' then 180 | if Z0_cwm_i = '0' then 181 | if do_q3p_Z0 = '1' then 182 | Z0_var <= Z0_var - 1; 183 | if (Z0_var = "00000000000000000000000000000001") then 184 | Z0_cwm_i <= '1'; 185 | do_q3p_Z0 <= '0'; 186 | end if; 187 | end if; 188 | end if; 189 | else 190 | Z0_var <= Z0_var - 1; 191 | if (Z0_var = "00000000000000000000000000000000") then 192 | Z0_cwm_i <= '1'; 193 | Z0_var <= unsigned(Z0_turn); 194 | end if; 195 | end if; -- Z0_bar 196 | end if; 197 | end if; -- Z0_blrb 198 | 199 | if Z0_zz1pb = '0' then 200 | Z0_cwm_i <= '0'; 201 | end if; 202 | 203 | if Y1_baz = '1' then -- counter Baz 204 | Y1_var <= unsigned(Y1_turn); 205 | if Y1_turn = "00000000000000000000000000000000" then 206 | do_q3p_Y1 <= '0'; 207 | else 208 | do_q3p_Y1 <= '1'; 209 | end if; 210 | elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then 211 | if Y1_bar = '0' then 212 | if Y1_cwm_i = '0' then 213 | if do_q3p_Y1 = '1' then 214 | Y1_var <= Y1_var - 1; 215 | if (Y1_var = "00000000000000000000000000000001") then 216 | Y1_cwm_i <= '1'; 217 | do_q3p_Y1 <= '0'; 218 | end if; 219 | end if; 220 | end if; 221 | else 222 | Y1_var <= Y1_var - 1; 223 | 224 | if (Y1_var = "00000000000000000000000000000000") then 225 | Y1_cwm_i <= '1'; 226 | Y1_var <= unsigned(Y1_turn); 227 | end if; 228 | end if; -- Y1_bar 229 | 230 | end if; -- Y1_blrb 231 | 232 | if Y1_zz1pb = '0' then 233 | Y1_cwm_i <= '0'; 234 | end if; 235 | 236 | if X2_baz = '1' then -- counter Baz 237 | X2_var <= unsigned(X2_turn); 238 | if X2_turn = "00000000000000000000000000000000" then 239 | do_q3p_X2 <= '0'; 240 | else 241 | do_q3p_X2 <= '1'; 242 | end if; 243 | elsif do_q3p_X2 = '1' and X2_blrb = '1' then 244 | if X2_bar = '0' then 245 | if X2_cwm_i = '0' then 246 | if do_q3p_X2 = '1' then 247 | X2_var <= X2_var - 1; 248 | if (X2_var = "00000000000000000000000000000001") then 249 | X2_cwm_i <= '1'; 250 | do_q3p_X2 <= '0'; 251 | end if; 252 | end if; 253 | end if; 254 | else 255 | X2_var <= X2_var - 1; 256 | 257 | if (X2_var = "00000000000000000000000000000000") then --{ 258 | X2_cwm_i <= '1'; 259 | X2_var <= unsigned(X2_turn); 260 | end if; 261 | end if; --X2_bar 262 | end if; -- X2_blrb 263 | 264 | if X2_zz1pb = '0' then 265 | X2_cwm_i <= '0'; 266 | end if; 267 | 268 | if W3_baz = '1' then -- counter Baz 269 | W3_var <= unsigned(W3_turn); 270 | if W3_turn = "00000000000000000000000000000000" then 271 | do_q3p_W3 <= '0'; 272 | else 273 | do_q3p_W3 <= '1'; 274 | end if; 275 | elsif do_q3p_W3 = '1' and W3_blrb = '1' then 276 | if W3_bar = '0' then 277 | if W3_cwm_i = '0'then 278 | if do_q3p_W3 = '1' then 279 | W3_var <= W3_var - 1; 280 | if (W3_var = "00000000000000000000000000000001") then 281 | W3_cwm_i <= '1'; 282 | do_q3p_W3 <= '0'; 283 | end if; 284 | end if; 285 | end if; 286 | else 287 | W3_var <= W3_var - 1; 288 | 289 | if (W3_var = "00000000000000000000000000000000") then --{ 290 | W3_cwm_i <= '1'; 291 | W3_var <= unsigned(W3_turn); 292 | end if; 293 | end if; -- W3_bar 294 | 295 | end if; -- W3_blrb 296 | 297 | if W3_zz1pb = '0' then 298 | W3_cwm_i <= '0'; 299 | end if; 300 | 301 | if debct_baz = '1' then -- counter Baz 302 | debct_var <= unsigned(debct_turn); 303 | if debct_turn = "00000000000000000000000000000000" then 304 | do_q3p_debct <= '0'; 305 | else 306 | do_q3p_debct <= '1'; 307 | end if; 308 | elsif do_q3p_debct = '1' and debct_blrb = '1' then 309 | if debct_bar = '0' then 310 | if debct_cwm_i = '0'then 311 | if do_q3p_debct = '1' then 312 | debct_var <= debct_var - 1; 313 | if (debct_var = "00000000000000000000000000000001") then 314 | debct_cwm_i <= '1'; 315 | debct_pull <= '1'; 316 | do_q3p_debct <= '0'; 317 | end if; 318 | end if; 319 | end if; 320 | else 321 | ---- T 322 | -- Continue 323 | debct_var <= debct_var - 1; 324 | 325 | -- ending 326 | if (debct_var = "00000000000000000000000000000000") then --{ 327 | debct_cwm_i <= '1'; 328 | debct_pull <= '1'; 329 | debct_var <= unsigned(debct_turn); 330 | end if; 331 | end if; -- debct_bar 332 | 333 | end if; -- debct_blrb 334 | 335 | -- comment 336 | if debct_zz1pb = '0' then 337 | debct_cwm_i <= '0'; 338 | end if; 339 | 340 | end if; 341 | end if; 342 | end process; 343 | 344 | end rtl; 345 | -------------------------------------------------------------------------------- /examples/dsp.vhd: -------------------------------------------------------------------------------- 1 | -- Nearly useless stub, it's here to support genericmap.vhd 2 | LIBRARY IEEE; 3 | USE IEEE.std_logic_1164.all; 4 | USE IEEE.numeric_std.all; 5 | 6 | entity dsp is generic( 7 | rst_val : std_logic := '0'; 8 | thing_size: integer := 51; 9 | bus_width : integer := 24); 10 | port( 11 | -- Inputs 12 | clk, rstn : in std_logic; 13 | en, start : in std_logic; 14 | param : in std_logic_vector(7 downto 0); 15 | addr : in std_logic_vector(2 downto 0); 16 | din : in std_logic_vector(bus_width-1 downto 0); 17 | we : in std_logic; 18 | memdin : out std_logic_vector(13 downto 0); 19 | -- Outputs 20 | dout : out std_logic_vector(bus_width-1 downto 0); 21 | memaddr : out std_logic_vector(5 downto 0); 22 | memdout : out std_logic_vector(13 downto 0) 23 | ); 24 | end; 25 | 26 | architecture rtl of dsp is 27 | signal foo : std_logic; 28 | signal sr : std_logic_vector(63 downto 0); 29 | signal iparam : integer; 30 | begin 31 | iparam <= to_integer(unsigned(param)); 32 | process(clk) begin 33 | -- dout <= std_logic_vector(to_unsigned(1,bus_width)); 34 | if rising_edge(clk) then 35 | if we = '1' then 36 | sr <= sr(thing_size-bus_width-1 downto 0) & din; 37 | end if; 38 | dout <= sr(iparam*bus_width+bus_width-1 downto iparam*bus_width); 39 | end if; 40 | end process; 41 | end rtl; 42 | -------------------------------------------------------------------------------- /examples/exclude: -------------------------------------------------------------------------------- 1 | todo.* 2 | -------------------------------------------------------------------------------- /examples/expr.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity expr is 6 | generic(SIZE: positive:=2**8-1); 7 | port(reset, sysclk, ival : in std_logic); 8 | end expr; 9 | 10 | architecture rtl of expr is 11 | constant SIZE_OF : positive:=2**8-1; 12 | signal foo : std_logic_vector(13 downto 0); 13 | signal baz : std_logic_vector(2 downto 0); 14 | signal bam : std_logic_vector(22 downto 0); 15 | signal out_i : std_logic_vector(5 downto 3); 16 | signal input_status : std_logic_vector(8 downto 0); 17 | signal enable, debug, aux, outy, dv, value : std_logic; 18 | signal expo : std_logic_vector(2**3-1 downto 0); 19 | begin 20 | -- drive input status 21 | input_status <= -- top bits 22 | (foo(9 downto 4) & 23 | (( (baz(2 downto 0) and foo(3 downto 0)) or 24 | (not baz(2 downto 0) and bam(3 downto 0))))); 25 | -- drive based on foo 26 | out_i(4) <= 27 | -- if secondary enabl is set then drive aux out 28 | (enable and (aux xor outy)) or 29 | -- if debug is enabled 30 | (debug and dv and not enable) or 31 | -- otherwise we drive reg 32 | (not debug and not enable and value); 33 | -- not drive 34 | 35 | pfoo: process(reset, sysclk) 36 | begin 37 | if( reset /= '0' ) then 38 | foo <= (others => '0'); 39 | elsif( sysclk'event and sysclk = '0' ) then 40 | foo(3*(2-1)) <= baz(1*(1+2)-2); 41 | bam(foo'range) <= foo; 42 | end if; 43 | end process; 44 | 45 | expo <= std_logic_vector(to_unsigned(2**4, 2**8)); 46 | end rtl; 47 | -------------------------------------------------------------------------------- /examples/fifo.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------- 2 | -- Filename: gh_fifo_async16_sr.vhd 3 | -- 4 | -- Description: 5 | -- an Asynchronous FIFO 6 | -- 7 | -- Copyright (c) 2006 by George Huber 8 | -- an OpenCores.org Project 9 | -- free to use, but see documentation for conditions 10 | -- 11 | -- Revision History: 12 | -- Revision Date Author Comment 13 | -- -------- ---------- --------- ----------- 14 | -- 1.0 12/17/06 h lefevre Initial revision 15 | -- 16 | -------------------------------------------------------- 17 | 18 | library IEEE; 19 | use IEEE.std_logic_1164.all; 20 | USE ieee.numeric_std.all; 21 | 22 | entity fifo is 23 | GENERIC (data_width: INTEGER :=8 ); -- size of data bus 24 | port ( 25 | clk_WR : in STD_LOGIC; -- write clock 26 | clk_RD : in STD_LOGIC; -- read clock 27 | rst : in STD_LOGIC; -- resets counters 28 | srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR) 29 | WR : in STD_LOGIC; -- write control 30 | RD : in STD_LOGIC; -- read control 31 | D : in STD_LOGIC_VECTOR (data_width-1 downto 0); 32 | Q : out STD_LOGIC_VECTOR (data_width-1 downto 0); 33 | empty : out STD_LOGIC; 34 | full : out STD_LOGIC); 35 | end entity; 36 | 37 | architecture rtl of fifo is 38 | 39 | type ram_mem_type is array (15 downto 0) 40 | of STD_LOGIC_VECTOR (data_width-1 downto 0); 41 | signal ram_mem : ram_mem_type; 42 | signal iempty : STD_LOGIC; 43 | signal ifull : STD_LOGIC; 44 | signal add_WR_CE : std_logic; 45 | signal add_WR : std_logic_vector(4 downto 0); -- 4 bits are used to address MEM 46 | signal add_WR_GC : std_logic_vector(4 downto 0); -- 5 bits are used to compare 47 | signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags 48 | signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk 49 | signal add_RD_CE : std_logic; 50 | signal add_RD : std_logic_vector(4 downto 0); 51 | signal add_RD_GC : std_logic_vector(4 downto 0); 52 | signal add_RD_GCwc : std_logic_vector(4 downto 0); 53 | signal n_add_RD : std_logic_vector(4 downto 0); 54 | signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk 55 | signal srst_w : STD_LOGIC; 56 | signal isrst_w : STD_LOGIC; 57 | signal srst_r : STD_LOGIC; 58 | signal isrst_r : STD_LOGIC; 59 | 60 | begin 61 | 62 | -------------------------------------------- 63 | ------- memory ----------------------------- 64 | -------------------------------------------- 65 | 66 | process (clk_WR) 67 | begin 68 | if (rising_edge(clk_WR)) then 69 | if ((WR = '1') and (ifull = '0')) then 70 | --ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D; 71 | end if; 72 | end if; 73 | end process; 74 | 75 | --Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0)))); 76 | 77 | ----------------------------------------- 78 | ----- Write address counter ------------- 79 | ----------------------------------------- 80 | 81 | add_WR_CE <= '0' when (ifull = '1') else 82 | '0' when (WR = '0') else 83 | '1'; 84 | 85 | n_add_WR <= std_logic_vector(unsigned(add_WR) + x"1"); 86 | 87 | process (clk_WR,rst) 88 | begin 89 | if (rst = '1') then 90 | add_WR <= (others => '0'); 91 | add_RD_WS <= "11000"; 92 | add_WR_GC <= (others => '0'); 93 | elsif (rising_edge(clk_WR)) then 94 | add_RD_WS <= add_RD_GCwc; 95 | if (srst_w = '1') then 96 | add_WR <= (others => '0'); 97 | add_WR_GC <= (others => '0'); 98 | elsif (add_WR_CE = '1') then 99 | add_WR <= n_add_WR; 100 | add_WR_GC(0) <= n_add_WR(0) xor n_add_WR(1); 101 | add_WR_GC(1) <= n_add_WR(1) xor n_add_WR(2); 102 | add_WR_GC(2) <= n_add_WR(2) xor n_add_WR(3); 103 | add_WR_GC(3) <= n_add_WR(3) xor n_add_WR(4); 104 | add_WR_GC(4) <= n_add_WR(4); 105 | else 106 | add_WR <= add_WR; 107 | add_WR_GC <= add_WR_GC; 108 | end if; 109 | end if; 110 | end process; 111 | 112 | full <= ifull; 113 | 114 | ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to "00000" 115 | '0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11000" 116 | '1'; 117 | 118 | ----------------------------------------- 119 | ----- Read address counter -------------- 120 | ----------------------------------------- 121 | 122 | add_RD_CE <= '0' when (iempty = '1') else 123 | '0' when (RD = '0') else 124 | '1'; 125 | 126 | n_add_RD <= std_logic_vector(unsigned(add_RD) + x"1"); 127 | 128 | process (clk_RD,rst) 129 | begin 130 | if (rst = '1') then 131 | add_RD <= (others => '0'); 132 | add_WR_RS <= (others => '0'); 133 | add_RD_GC <= (others => '0'); 134 | add_RD_GCwc <= "11000"; 135 | elsif (rising_edge(clk_RD)) then 136 | add_WR_RS <= add_WR_GC; 137 | if (srst_r = '1') then 138 | add_RD <= (others => '0'); 139 | add_RD_GC <= (others => '0'); 140 | add_RD_GCwc <= "11000"; 141 | elsif (add_RD_CE = '1') then 142 | add_RD <= n_add_RD; 143 | add_RD_GC(0) <= n_add_RD(0) xor n_add_RD(1); 144 | add_RD_GC(1) <= n_add_RD(1) xor n_add_RD(2); 145 | add_RD_GC(2) <= n_add_RD(2) xor n_add_RD(3); 146 | add_RD_GC(3) <= n_add_RD(3) xor n_add_RD(4); 147 | add_RD_GC(4) <= n_add_RD(4); 148 | add_RD_GCwc(0) <= n_add_RD(0) xor n_add_RD(1); 149 | add_RD_GCwc(1) <= n_add_RD(1) xor n_add_RD(2); 150 | add_RD_GCwc(2) <= n_add_RD(2) xor n_add_RD(3); 151 | add_RD_GCwc(3) <= n_add_RD(3) xor (not n_add_RD(4)); 152 | add_RD_GCwc(4) <= (not n_add_RD(4)); 153 | else 154 | add_RD <= add_RD; 155 | add_RD_GC <= add_RD_GC; 156 | add_RD_GCwc <= add_RD_GCwc; 157 | end if; 158 | end if; 159 | end process; 160 | 161 | empty <= iempty; 162 | 163 | iempty <= '1' when (add_WR_RS = add_RD_GC) else 164 | '0'; 165 | 166 | ---------------------------------- 167 | --- sync rest stuff -------------- 168 | --- srst is sync with clk_WR ----- 169 | --- srst_r is sync with clk_RD --- 170 | ---------------------------------- 171 | 172 | process (clk_WR,rst) 173 | begin 174 | if (rst = '1') then 175 | srst_w <= '0'; 176 | isrst_r <= '0'; 177 | elsif (rising_edge(clk_WR)) then 178 | isrst_r <= srst_r; 179 | if (srst = '1') then 180 | srst_w <= '1'; 181 | elsif (isrst_r = '1') then 182 | srst_w <= '0'; 183 | end if; 184 | end if; 185 | end process; 186 | 187 | process (clk_RD,rst) 188 | begin 189 | if (rst = '1') then 190 | srst_r <= '0'; 191 | isrst_w <= '0'; 192 | elsif (rising_edge(clk_RD)) then 193 | isrst_w <= srst_w; 194 | if (isrst_w = '1') then 195 | srst_r <= '1'; 196 | else 197 | srst_r <= '0'; 198 | end if; 199 | end if; 200 | end process; 201 | 202 | end architecture; 203 | -------------------------------------------------------------------------------- /examples/forgen.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all; 3 | 4 | entity forgen is 5 | generic( 6 | bus_width : integer := 15; 7 | TOP_GP2 : integer:= 0 8 | ); 9 | port( 10 | sysclk, reset, wrb : in std_logic; 11 | din : in std_logic_vector(bus_width downto 0); 12 | rdout: out std_logic_vector(bus_width downto 0) 13 | ); 14 | end forgen; 15 | 16 | architecture rtl of forgen is 17 | component wbit1 -- register bit default 1 18 | port( 19 | clk : in std_logic; 20 | wrb : in std_logic; 21 | reset : in std_logic; 22 | enb : in std_logic; 23 | din : in std_logic; 24 | dout : out std_logic); 25 | end component; 26 | 27 | signal regSelect : std_logic_vector(bus_width * 2 downto 0); 28 | begin 29 | ----------------------------------------------------- 30 | -- Reg : GP 2 31 | -- Active : 32 32 | -- Type : RW 33 | ----------------------------------------------------- 34 | reg_gp2 : for bitnum in 0 to bus_width generate 35 | wbit1_inst : wbit1 36 | PORT MAP( 37 | clk => sysclk, 38 | wrb => wrb, 39 | reset => reset, 40 | enb => regSelect(TOP_GP2), 41 | din => din(bitnum), 42 | dout => rdout(bitnum) 43 | ); 44 | end generate; 45 | 46 | process(sysclk) begin 47 | if sysclk'event and sysclk = '1' then 48 | regSelect(1) <= '1'; 49 | end if; 50 | end process; 51 | 52 | end rtl; 53 | -------------------------------------------------------------------------------- /examples/forloop.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity forloop is port( 6 | reset, sysclk : in std_logic 7 | ); 8 | end forloop; 9 | 10 | architecture rtl of forloop is 11 | signal selection : std_logic; 12 | signal egg_timer : std_logic_vector(6 downto 0); 13 | begin 14 | TIMERS : 15 | process(reset, sysclk) 16 | variable timer_var : integer; 17 | variable a, i, j, k : integer; 18 | variable zz5 : std_logic_vector(31 downto 0); 19 | variable zz : std_logic_vector(511 downto 0); 20 | begin 21 | if reset = '1' then 22 | selection <= '1'; 23 | timer_var := 2; 24 | egg_timer <= (others => '0'); 25 | elsif sysclk'event and sysclk = '1' then 26 | -- pulse only lasts for once cycle 27 | selection <= '0'; 28 | egg_timer <= (others => '1'); 29 | for i in 0 to j*k loop 30 | a := a + i; 31 | for k in a-9 downto -14 loop 32 | zz5 := zz(31+k downto k); 33 | end loop; -- k 34 | end loop; -- i 35 | end if; 36 | end process; 37 | end rtl; 38 | -------------------------------------------------------------------------------- /examples/genericmap.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all; 3 | entity genericmap is 4 | generic( 5 | rst_val : std_logic := '0'; 6 | thing_size: integer := 201 rem 2; 7 | bus_width : integer := 201 mod 32); 8 | port( 9 | clk, rstn : in std_logic; 10 | en, start_dec : in std_logic; 11 | addr : in std_logic_vector(2 downto 0); 12 | din : in std_logic_vector(25 downto 0); 13 | we : in std_logic; 14 | pixel_in : in std_logic_vector(7 downto 0); 15 | pix_req : in std_logic; 16 | bip : in std_logic; 17 | a, b : in std_logic_vector(7 downto 0); 18 | c, load : in std_logic_vector(7 downto 0); 19 | pack : in std_logic_vector(6 downto 0); 20 | base : in std_logic_vector(2 downto 0); 21 | qtd : in std_logic_vector(21 downto 0); 22 | -- Outputs 23 | dout : out std_logic_vector(25 downto 0); 24 | pixel_out : out std_logic_vector(7 downto 0); 25 | pixel_valid : out std_logic; 26 | code : out std_logic_vector(9 downto 0); 27 | complex : out std_logic_vector(23 downto 0); 28 | eno : out std_logic 29 | ); 30 | end genericmap; 31 | architecture rtl of genericmap is 32 | 33 | component dsp 34 | generic( 35 | rst_val : std_logic := '0'; 36 | thing_size: integer := 201; 37 | bus_width : integer := 24); 38 | port( 39 | -- Inputs 40 | clk, rstn : in std_logic; 41 | en, start : in std_logic; 42 | param : in std_logic_vector(7 downto 0); 43 | addr : in std_logic_vector(2 downto 0); 44 | din : in std_logic_vector(bus_width-1 downto 0); 45 | we : in std_logic; 46 | memdin : out std_logic_vector(13 downto 0); 47 | -- Outputs 48 | dout : out std_logic_vector(bus_width-1 downto 0); 49 | memaddr : out std_logic_vector(5 downto 0); 50 | memdout : out std_logic_vector(13 downto 0) 51 | ); 52 | end component; 53 | signal param : std_logic_vector(7 downto 0); 54 | signal selection : std_logic; 55 | signal start, enf : std_logic; -- Start and enable signals 56 | signal memdin : std_logic_vector(13 downto 0); 57 | signal memaddr : std_logic_vector(5 downto 0); 58 | signal memdout : std_logic_vector(13 downto 0); 59 | signal colour : std_logic_vector(1 downto 0); 60 | begin 61 | dsp_inst0 : dsp 62 | -- default bus_width is 24 63 | port map( 64 | -- Inputs 65 | clk => clk, 66 | rstn => rstn, 67 | en => '1', 68 | start => '0', 69 | param => X"42", 70 | addr => "101", 71 | din => "000100010001000100010001", 72 | we => '0', 73 | -- Outputs 74 | dout => dout(23 downto 0), 75 | memaddr => memaddr, 76 | memdout => memdout 77 | ); 78 | 79 | dsp_inst1 : dsp 80 | generic map( 81 | rst_val => '1', 82 | bus_width => 16) 83 | port map( 84 | -- Inputs 85 | clk => clk, 86 | rstn => rstn, 87 | en => '1', 88 | start => '0', 89 | param => X"42", 90 | addr => "101", 91 | din => "0001000100010001", 92 | we => '0', 93 | -- Outputs 94 | dout => dout(15 downto 0), 95 | memaddr => memaddr, 96 | memdout => memdout 97 | ); 98 | 99 | signextend_inst2 : entity work.signextend 100 | port map ( 101 | i => "0000000000000000", 102 | o => open 103 | ); 104 | 105 | end rtl; 106 | -------------------------------------------------------------------------------- /examples/ifchain.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all; 3 | 4 | entity ifchain is port( 5 | clk, rstn : in std_logic 6 | ); 7 | end ifchain; 8 | 9 | architecture rtl of ifchain is 10 | type t is array (3 downto 0) of std_logic_vector(31 downto 0); 11 | signal a : std_logic_vector(3 downto 0); 12 | signal b : std_logic_vector(3 downto 0); 13 | signal status : std_logic; 14 | signal c : t; 15 | begin 16 | 17 | process(clk) begin 18 | if clk'event and clk = '1' then 19 | if b(1) & a(3 downto 2) = "001" then 20 | status <= '1'; 21 | c(0) <= x"FFFFFFFF"; 22 | end if; 23 | end if; 24 | end process; 25 | 26 | end rtl; 27 | -------------------------------------------------------------------------------- /examples/ifchain2.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all; 3 | USE IEEE.numeric_std.all; 4 | 5 | entity ifchain2 is port( 6 | clk, rstn : in std_logic; 7 | enable: in std_logic; 8 | result: out std_logic 9 | ); 10 | end ifchain2; 11 | 12 | architecture rtl of ifchain2 is 13 | signal counter : unsigned(3 downto 0); 14 | constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4); 15 | begin 16 | 17 | clk_src : process(clk, rstn) is 18 | begin 19 | if (rstn = '0') then 20 | counter <= (others => '0'); 21 | result <= '0'; 22 | elsif (rising_edge(clk)) then -- Divide by 2 by default 23 | if (enable = '1') then 24 | if (counter = 0) then 25 | counter <= CLK_DIV_VAL; 26 | result <= '1'; 27 | else 28 | counter <= counter - 1; 29 | result <= '0'; 30 | end if; -- counter 31 | end if; -- enable 32 | end if; -- clk, rst_n 33 | end process clk_src; 34 | assert (counter < CLK_DIV_VAL) report "test case" severity error; 35 | 36 | end rtl; 37 | -------------------------------------------------------------------------------- /examples/mem.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity mem is 6 | generic( 7 | addr_width : integer := 6; 8 | bus_width : integer := 14 9 | ); 10 | port ( 11 | clk : in std_logic; 12 | rstn : in std_logic; -- not implemented 13 | en : in std_logic; 14 | cs : in std_logic; -- not implemented 15 | addr : in unsigned(addr_width-1 downto 0); 16 | din : in unsigned(bus_width-1 downto 0); 17 | dout : out unsigned(bus_width-1 downto 0) 18 | ); 19 | end entity; 20 | 21 | architecture rtl of mem is 22 | signal al : unsigned(addr_width-1 downto 0) := X"00"; 23 | type mem_Type is array (255 downto 0) of unsigned(bus_width-1 downto 0); 24 | signal mem : mem_Type; 25 | begin 26 | dout <= mem(to_integer(al)); 27 | process (clk) is 28 | begin 29 | if rising_edge(clk) then 30 | al <= addr; 31 | if en = '1' then 32 | mem(to_integer(addr)) <= din; 33 | end if; 34 | end if; 35 | end process; 36 | end architecture; 37 | -------------------------------------------------------------------------------- /examples/operators.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.numeric_std.all; 4 | 5 | entity operators is 6 | generic ( 7 | g_and : std_logic_vector(1 downto 0) := "11" and "10"; 8 | g_or : std_logic_vector(1 downto 0) := "11" or "10"; 9 | g_nand : std_logic_vector(1 downto 0) := "11" nand "10"; 10 | g_nor : std_logic_vector(1 downto 0) := "11" nor "10"; 11 | g_xor : std_logic_vector(1 downto 0) := "11" xor "10"; 12 | g_xnor : std_logic_vector(1 downto 0) := "11" xnor "10"; 13 | g_not : std_logic_vector(1 downto 0) := not "10" 14 | ); 15 | port ( 16 | clk_i : in std_logic 17 | ); 18 | end entity operators; 19 | 20 | architecture rtl of operators is 21 | constant c_and : std_logic_vector(1 downto 0) := "11" and "10"; 22 | constant c_or : std_logic_vector(1 downto 0) := "11" or "10"; 23 | constant c_nand : std_logic_vector(1 downto 0) := "11" nand "10"; 24 | constant c_nor : std_logic_vector(1 downto 0) := "11" nor "10"; 25 | constant c_xor : std_logic_vector(1 downto 0) := "11" xor "10"; 26 | constant c_xnor : std_logic_vector(1 downto 0) := "11" xnor "10"; 27 | constant c_not : std_logic_vector(1 downto 0) := not "10"; 28 | signal s_op1 : std_logic_vector(1 downto 0); 29 | signal s_op2 : std_logic_vector(1 downto 0); 30 | signal s_res : std_logic_vector(1 downto 0); 31 | signal s_int : integer; 32 | signal s_sig : signed(7 downto 0); 33 | signal s_uns : unsigned(7 downto 0); 34 | begin 35 | 36 | test_i: process(clk_i) 37 | variable v_op1 : std_logic_vector(1 downto 0); 38 | variable v_op2 : std_logic_vector(1 downto 0); 39 | variable v_res : std_logic_vector(1 downto 0); 40 | begin 41 | if rising_edge(clk_i) then 42 | if 43 | (s_op1="11" and s_op2="00") or 44 | (s_op1="11" or s_op2="00") or 45 | (s_op1="11" nand s_op2="00") or 46 | (s_op1="11" nor s_op2="00") or 47 | (not (s_op1="11")) 48 | then 49 | s_res <= s_op1 and s_op2; 50 | s_res <= s_op1 or s_op2; 51 | v_res := v_op1 nand v_op2; 52 | v_res := v_op1 nor v_op2; 53 | s_res <= s_op1 xor s_op2; 54 | v_res := v_op1 xnor v_op2; 55 | s_res <= not s_op1; 56 | s_int <= abs(s_int); 57 | s_sig <= abs(s_sig); 58 | s_sig <= s_sig sll 2; 59 | s_sig <= s_sig srl to_integer(s_sig); 60 | s_uns <= s_uns sll to_integer(s_uns); 61 | s_uns <= s_uns srl 9; 62 | s_sig <= shift_left(s_sig,2); 63 | s_sig <= shift_right(s_sig,to_integer(s_sig)); 64 | -- s_uns <= s_uns ror 3; -- Not yet implemented 65 | -- s_uns <= s_uns rol to_integer(s_uns); -- Not yet implemented 66 | -- s_uns <= rotate_right(s_uns,3); -- Not yet implemented 67 | -- s_uns <= rotate_left(s_uns,to_integer(s_uns)); -- Not yet implemented 68 | s_sig <= s_sig rem s_int; 69 | s_sig <= s_sig mod s_int; 70 | end if; 71 | if 72 | s_sig = signed(s_uns) or unsigned(s_sig) /= s_uns or s_sig < "101010101" or 73 | s_sig <= signed(s_uns) or unsigned(s_sig) > s_uns or s_sig >= "00000101" 74 | then 75 | s_sig <= s_sig + s_sig; 76 | s_sig <= s_sig - s_sig; 77 | s_sig <= s_sig * s_sig; 78 | s_sig <= s_sig / s_sig; 79 | s_sig <= s_sig(7 downto 4) & "10" & signed(s_uns(1 downto 0)); 80 | s_int <= 2 ** 3; 81 | end if; 82 | end if; 83 | end process test_i; 84 | 85 | end architecture rtl; 86 | -------------------------------------------------------------------------------- /examples/partselect.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | 4 | entity partselect is 5 | port( 6 | clk_i : in std_logic 7 | ); 8 | end entity partselect; 9 | 10 | architecture rtl of partselect is 11 | signal big_sig : std_logic_vector(31 downto 0); 12 | signal lit_sig : std_logic_vector(0 to 31); 13 | signal i : integer:=8; 14 | begin 15 | 16 | test_i: process(clk_i) 17 | variable big_var : std_logic_vector(31 downto 0); 18 | variable lit_var : std_logic_vector(0 to 31); 19 | variable j : integer; 20 | begin 21 | if rising_edge(clk_i) then 22 | big_sig(31 downto 24) <= big_sig(7 downto 0); 23 | big_var(31 downto 24) := big_var(7 downto 0); 24 | lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7); 25 | lit_var(j*3 to j*3+8) := lit_var(j*0 to 8+j*0); 26 | -- 27 | big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0); 28 | big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0); 29 | end if; 30 | end process test_i; 31 | 32 | end architecture rtl; 33 | -------------------------------------------------------------------------------- /examples/signextend.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | entity signextend is 6 | port( 7 | i : in std_logic_vector(15 downto 0); 8 | o : out std_logic_vector(31 downto 0) 9 | ); 10 | end entity signextend; 11 | 12 | architecture behavior of signextend is 13 | begin 14 | o(31 downto 24) <= (others => '0'); 15 | o(23 downto 16) <= (others => i(15)); 16 | o(15 downto 0) <= i; 17 | end architecture behavior; 18 | -------------------------------------------------------------------------------- /examples/test.vhd: -------------------------------------------------------------------------------- 1 | -- Project: VHDL to Verilog RTL translation 2 | -- Revision: 1.0 3 | -- Date of last Revision: February 27 2001 4 | -- Designer: Vincenzo Liguori 5 | -- vhd2vl test file 6 | -- This VHDL file exercises vhd2vl 7 | 8 | LIBRARY IEEE; 9 | 10 | USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; 11 | 12 | entity test is port( 13 | -- Inputs 14 | clk, rstn : in std_logic; 15 | en, start_dec : in std_logic; 16 | addr : in std_logic_vector(2 downto 0); 17 | din : in std_logic_vector(25 downto 0); 18 | we : in std_logic; 19 | pixel_in : in std_logic_vector(7 downto 0); 20 | pix_req : in std_logic; 21 | config1, bip : in std_logic; 22 | a, b : in std_logic_vector(7 downto 0); 23 | c, load : in std_logic_vector(7 downto 0); 24 | pack : in std_logic_vector(6 downto 0); 25 | base : in std_logic_vector(2 downto 0); 26 | qtd : in std_logic_vector(21 downto 0); 27 | -- Outputs 28 | dout : out std_logic_vector(23 downto 0); 29 | pixel_out : out std_logic_vector(7 downto 0); 30 | pixel_valid : out std_logic; 31 | code : out std_logic_vector(9 downto 0); 32 | code1 : out std_logic_vector(9 downto 0); 33 | complex : out std_logic_vector(23 downto 0); 34 | eno : out std_logic 35 | ); 36 | end test; 37 | 38 | architecture rtl of test is 39 | 40 | -- Components declarations are ignored by vhd2vl 41 | -- but they are still parsed 42 | 43 | component dsp port( 44 | -- Inputs 45 | clk, rstn : in std_logic; 46 | en, start : in std_logic; 47 | param : in std_logic_vector(7 downto 0); 48 | addr : in std_logic_vector(2 downto 0); 49 | din : in std_logic_vector(23 downto 0); 50 | we : in std_logic; 51 | memdin : out std_logic_vector(13 downto 0); 52 | -- Outputs 53 | dout : out std_logic_vector(23 downto 0); 54 | memaddr : out std_logic_vector(5 downto 0); 55 | memdout : out std_logic_vector(13 downto 0) 56 | ); 57 | end component; 58 | 59 | component mem port( 60 | -- Inputs 61 | clk, rstn : in std_logic; 62 | en : in std_logic; 63 | cs : in std_logic; 64 | addr : in std_logic_vector(5 downto 0); 65 | din : in std_logic_vector(13 downto 0); 66 | -- Outputs 67 | dout : out std_logic_vector(13 downto 0) 68 | ); 69 | end component; 70 | 71 | type state is (red, green, blue, yellow); 72 | signal status : state; 73 | constant PARAM1 : std_logic_vector(7 downto 0):="01101101"; 74 | constant PARAM2 : std_logic_vector(7 downto 0):="11001101"; 75 | constant PARAM3 : std_logic_vector(7 downto 0):="00010111"; 76 | signal param : std_logic_vector(7 downto 0); 77 | signal selection : std_logic := '0'; 78 | signal start, enf : std_logic; -- Start and enable signals 79 | signal memdin : std_logic_vector(13 downto 0); 80 | signal memaddr : std_logic_vector(5 downto 0); 81 | signal memdout : std_logic_vector(13 downto 0); 82 | signal colour : std_logic_vector(1 downto 0); 83 | begin 84 | 85 | param <= PARAM1 when config1 = '1' else PARAM2 when status = green else PARAM3; 86 | 87 | -- Synchronously process 88 | process(clk) begin 89 | if clk'event and clk = '1' then 90 | pixel_out <= pixel_in xor "11001100"; 91 | end if; 92 | end process; 93 | 94 | -- Synchronous process 95 | process(clk) begin 96 | if rising_edge(clk) then 97 | case status is 98 | when red => colour <= "00"; 99 | when green => colour <= B"01"; 100 | when blue => colour <= "10"; 101 | when others => colour <= "11"; 102 | end case; 103 | end if; 104 | end process; 105 | 106 | -- Synchronous process with asynch reset 107 | process(clk,rstn) begin 108 | if rstn = '0' then 109 | status <= red; 110 | elsif rising_edge(clk) then 111 | case status is 112 | when red => 113 | if pix_req = '1' then 114 | status <= green; 115 | end if; 116 | when green => 117 | if a(3) = '1' then 118 | start <= start_dec; 119 | status <= blue; 120 | elsif (b(5) & a(3 downto 2)) = "001" then 121 | status <= yellow; 122 | end if; 123 | when blue => 124 | status <= yellow; 125 | when others => 126 | start <= '0'; 127 | status <= red; 128 | end case; 129 | end if; 130 | end process; 131 | 132 | -- Example of with statement 133 | with memaddr(2 downto 0) select 134 | code(9 downto 2) <= "110" & pack(6 downto 2) when "000" | "110", 135 | "11100010" when "101", 136 | (others => '1') when "010", 137 | (others => '0') when "011", 138 | std_logic_vector(unsigned(a) + unsigned(b)) when others; 139 | code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); 140 | 141 | -- Asynch process 142 | decode : process(we, addr, config1, bip) begin 143 | if we = '1' then 144 | if addr(2 downto 0) = "100" then 145 | selection <= '1'; 146 | elsif (b & a) = a & b and bip = '0' then 147 | selection <= config1; 148 | else 149 | selection <= '1'; 150 | end if; 151 | else 152 | selection <= '0'; 153 | end if; 154 | end process decode; 155 | 156 | -- Components instantiation 157 | dsp_inst : dsp port map( 158 | -- Inputs 159 | clk => clk, 160 | rstn => rstn, 161 | en => en, 162 | start => start, 163 | param => param, 164 | addr => addr, 165 | din => din(23 downto 0), 166 | we => we, 167 | memdin => memdin, 168 | -- Outputs 169 | dout => dout, 170 | memaddr => memaddr, 171 | memdout => memdout 172 | ); 173 | 174 | dsp_mem : mem port map( 175 | -- Inputs 176 | clk => clk, 177 | rstn => rstn, 178 | en => en, 179 | cs => selection, 180 | addr => memaddr, 181 | din => memdout, 182 | -- Outputs 183 | dout => memdin 184 | ); 185 | 186 | complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001"; 187 | 188 | enf <= '1' when c < "1000111" else '0'; 189 | eno <= enf; 190 | 191 | end rtl; 192 | -------------------------------------------------------------------------------- /examples/todo.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.numeric_std.all; 4 | 5 | entity todo is 6 | generic( 7 | INBYLEVEL : boolean:=FALSE 8 | ); 9 | port ( 10 | clk_i : in std_logic; 11 | data_i : in std_logic_vector(7 downto 0); 12 | data_o : out std_logic_vector(7 downto 0) 13 | ); 14 | end todo; 15 | 16 | architecture rtl of todo is 17 | type mem_type is array (0 to 255) of integer; 18 | signal mem : mem_type; 19 | 20 | signal int : integer; 21 | signal uns : unsigned(7 downto 0); 22 | 23 | constant BYTES : positive:=4; 24 | constant WIDTH : positive:=BYTES*8; 25 | signal index : natural range 0 to BYTES-1; 26 | signal comma : std_logic_vector(BYTES*3-1 downto 0); 27 | 28 | -- (others => (others => '0')) must be replaced by an initial block with a for 29 | -- or something similar. 30 | --type ff_array is array (0 to 255) of std_logic_vector(7 downto 0); 31 | --signal data_r : ff_array :=(others => (others => '0')); 32 | begin 33 | --************************************************************************** 34 | -- Wrong translations 35 | --************************************************************************** 36 | -- 37 | test_i: process(clk_i) 38 | -- iverilog: variable declaration assignments are only allowed at the module level. 39 | variable i : integer:=8; 40 | begin 41 | for i in 0 to 7 loop 42 | if i=4 then 43 | exit; -- iverilog: error: malformed statement 44 | end if; 45 | end loop; 46 | end process test_i; 47 | -- indexed part-select not applied 48 | do_boundary: process (clk_i) 49 | begin 50 | if rising_edge(clk_i) then 51 | for i in 0 to BYTES-1 loop 52 | if comma(BYTES*2+i-1 downto BYTES+i)=comma(3 downto 0) then 53 | index <= i; 54 | end if; 55 | end loop; 56 | end if; 57 | end process; 58 | comma <= comma(BYTES+index-1 downto index); 59 | --************************************************************************** 60 | -- Translations which abort with syntax error (uncomment to test) 61 | --************************************************************************** 62 | -- Concatenation in port assignament fail 63 | -- uns <= "0000" & X"1"; -- It is supported 64 | -- dut1_i: entity work.signextend 65 | -- port map ( 66 | -- i => "00000000" & X"11", -- But here fail 67 | -- o => open 68 | -- ); 69 | -- Unsupported generate with boolean? 70 | -- in_by_level: 71 | -- if INBYLEVEL generate 72 | -- int <= 9; 73 | -- end generate in_by_level; 74 | end rtl; 75 | -------------------------------------------------------------------------------- /examples/wbit1.vhd: -------------------------------------------------------------------------------- 1 | -- Nearly useless stub, it's here to support generate.vhd 2 | LIBRARY IEEE; 3 | USE IEEE.std_logic_1164.all; 4 | 5 | entity wbit1 is 6 | port( 7 | clk : in std_logic; 8 | wrb : in std_logic; 9 | reset : in std_logic; 10 | enb : in std_logic; 11 | din : in std_logic; 12 | dout : out std_logic); 13 | end; 14 | 15 | architecture rtl of wbit1 is 16 | signal foo : std_logic; 17 | begin 18 | process(clk) begin 19 | dout <= '1'; 20 | end process; 21 | end rtl; 22 | -------------------------------------------------------------------------------- /examples/whileloop.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity whileloop is port( 6 | A : in integer; 7 | Z : out std_logic_vector(3 downto 0) 8 | ); 9 | end whileloop; 10 | 11 | architecture rtl of whileloop is 12 | begin 13 | 14 | process (A) 15 | variable I : integer range 0 to 4; 16 | begin 17 | Z <= "0000"; 18 | I := 0; 19 | while (I <= 3) loop 20 | if (A = I) then 21 | Z(I) <= '1'; 22 | end if; 23 | I := I + 1; 24 | end loop; 25 | end process; 26 | 27 | end rtl; 28 | -------------------------------------------------------------------------------- /examples/withselect.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; 3 | 4 | entity withselect is 5 | generic( 6 | dog_width : std_logic_vector(7 downto 0) := "10101100"; 7 | bus_width : integer := 32 8 | ); 9 | port( reset, sysclk : in std_logic; 10 | a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) 11 | ); 12 | end withselect; 13 | 14 | architecture rtl of withselect is 15 | signal foo : std_logic_vector(1+1 downto 0); 16 | signal code,code1: std_logic_vector(9 downto 0); 17 | signal egg : std_logic_vector(324 to 401); 18 | signal baz : std_logic_vector(bus_width*3-1 to bus_width*4); 19 | signal complex : std_logic_vector(31 downto 0); 20 | begin 21 | -- Example of with statement 22 | with foo(2 downto 0) select 23 | code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110", 24 | "11100010" when "101", 25 | (others => '1') when "010", 26 | (others => '0') when "011", 27 | std_logic_vector(unsigned(a) + unsigned(b)) when others; 28 | code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); 29 | 30 | foo <= (others => '0'); 31 | egg <= (others => '0'); 32 | baz <= (others => '1'); 33 | complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001"; 34 | end rtl; 35 | -------------------------------------------------------------------------------- /src/def.h: -------------------------------------------------------------------------------- 1 | /* 2 | vhd2vl v2.3 3 | VHDL to Verilog RTL translator 4 | Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com 5 | Modifications (C) 2006 Mark Gonzales - PMC Sierra Inc 6 | 7 | This program is free software; you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation; either version 2 of the License, or 10 | (at your option) any later version. 11 | 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License along 18 | with this program; if not, write to the Free Software Foundation, Inc., 19 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 | */ 21 | 22 | #ifndef __def_h 23 | #define __def_h 24 | 25 | #define MAXINDENT 36 26 | #define MAXEDGES 1000 /* maximum number of @(edge) processes supported in a source file */ 27 | 28 | typedef struct nlist { 29 | char *name; /* Name */ 30 | struct nlist *next; 31 | } nlist; 32 | 33 | enum slistType {tSLIST, tTXT, tVAL, tPTXT, tOTHERS}; 34 | typedef struct slist { 35 | enum slistType type; 36 | struct slist *slst; 37 | union { 38 | struct slist *sl; /* type 0 */ 39 | char *txt; /* type 1 */ 40 | char **ptxt; /* type 3!*/ 41 | int val; /* type 2,4 */ 42 | } data; 43 | } slist; 44 | 45 | enum vrangeType {tSCALAR, tSUBSCRIPT, tVRANGE}; 46 | typedef struct vrange { 47 | /* int hi, lo; */ 48 | enum vrangeType vtype; 49 | struct slist *nhi, *nlo; /* MAG index is a simple expression */ 50 | slist *size_expr; /* expression that calculates size (width) of this vrange */ 51 | int sizeval; /* precalculated size value */ 52 | int updown; /* only used for indexed part select case */ 53 | struct slist *xhi, *xlo; /* array index range; 0,0 for normal scalars */ 54 | } vrange; 55 | 56 | typedef struct slval { 57 | slist *sl; 58 | int val; /* Signal size */ 59 | vrange *range; /* Signal size */ 60 | } slval; 61 | 62 | typedef struct expdata { 63 | char op; 64 | int value; /* only set for simple_expr */ 65 | slist *sl; 66 | } expdata; 67 | /* Other people might use an enum for the op (operation). 68 | * I use a mnemonic character. 69 | * 'c' Chain 70 | * 'e' Expression 71 | * 'n' Natural 72 | * 't' Terminal symbol 73 | * 'o' Others 74 | * This is used to determine punctuation in the nesting process, 75 | * reducing the number of useless parenthesis levels. 76 | */ 77 | 78 | typedef struct sglist { 79 | char *name; /* Signal name */ 80 | char *type; /* Reg or wire */ 81 | const char *dir; /* input, output, inout */ 82 | vrange *range; /* Signal size */ 83 | struct sglist *next; 84 | } sglist; 85 | 86 | typedef struct blknamelist { 87 | char *name; /* Optional name */ 88 | struct blknamelist *next; 89 | } blknamelist; 90 | 91 | /* Routine common between vhd2vl.l and vhd2vl.y */ 92 | char *xstrdup(const char *s); 93 | 94 | #endif 95 | -------------------------------------------------------------------------------- /src/makefile: -------------------------------------------------------------------------------- 1 | # simplified version for general use, so as not to look so intimidating 2 | WARNS = -Wall -W 3 | # Even this level flags a known problem with flex-2.6.1 output, 4 | # regarding signed/unsigned comparison in YY_INPUT. 5 | # See https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=835542 6 | 7 | # Developers or anal compulsives: uncomment the following WARNS definition. 8 | # Leave off -Wtraditional-conversion until flex and bison get cleaned up. 9 | # Use -W for now instead of the more modern -Wextra, since lots of people 10 | # still use older compilers. 11 | # WARNS = -Wall -W -Wshadow -Wundef -Wredundant-decls -Wpointer-arith -Wcast-qual -Wcast-align -Wsign-compare -Wwrite-strings -Wstrict-prototypes -Wformat=2 -pedantic 12 | # Code generated by yacc-3.0.2 fails -Wstrict-overflow=5 13 | # Wish to add -Wmissing-prototypes someday 14 | 15 | # any of the following three should work: 16 | # STANDARD = 17 | # STANDARD = --std=c89 -D_DEFAULT_SOURCE 18 | STANDARD = --std=c99 -D_DEFAULT_SOURCE 19 | # some older versions of libc might need -D_POSIX_C_SOURCE -D_BSD_SOURCE 20 | # instead of -D_DEFAULT_SOURCE 21 | 22 | GIT_BASED_VERS := $(shell git rev-parse --short=8 HEAD) 23 | ifneq ($(GIT_BASED_VERS),) 24 | STANDARD += -DGIT_BASED_VERS=\"$(GIT_BASED_VERS)\" 25 | endif 26 | 27 | vhd2vl : lex.yy.c vhd2vl.tab.c 28 | $(CC) ${STANDARD} ${WARNS} -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c 29 | 30 | vhd2vl.tab.c : vhd2vl.y def.h 31 | bison -d -v -t vhd2vl.y 32 | 33 | lex.yy.c : vhd2vl.l def.h 34 | flex -i vhd2vl.l 35 | 36 | clean : 37 | rm -f lex.yy.c vhd2vl.tab.c vhd2vl.tab.h vhd2vl.output vhd2vl 38 | -------------------------------------------------------------------------------- /src/vhd2vl.l: -------------------------------------------------------------------------------- 1 | /* 2 | vhd2vl v2.3 3 | VHDL to Verilog RTL translator 4 | Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com 5 | Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc 6 | Modifications Copyright (C) 2008-2010 Larry Doolittle - LBNL 7 | 8 | This program is free software; you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation; either version 2 of the License, or 11 | (at your option) any later version. 12 | 13 | This program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License along 19 | with this program; if not, write to the Free Software Foundation, Inc., 20 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 | */ 22 | 23 | %option noinput 24 | %option nounput 25 | %option noyywrap 26 | 27 | %{ 28 | #include 29 | #include 30 | #include "def.h" 31 | #include "vhd2vl.tab.h" 32 | 33 | extern int lineno; 34 | 35 | extern int skipRem; 36 | 37 | void getstring(unsigned skip); 38 | void getbasedstring(unsigned skip); 39 | int scan_int(char *s); 40 | 41 | %} 42 | %% 43 | 44 | [ \t] {;} 45 | 46 | "--".*\n { 47 | lineno++; 48 | if (skipRem == 0) { 49 | /* sometimes comments should be dropped by lex - 50 | * e.g. in expressions - this makes the grammar much simpler 51 | */ 52 | size_t l=strlen(yytext); 53 | yylval.txt=xstrdup(yytext); 54 | yylval.txt[0]='/'; 55 | yylval.txt[1]='/'; 56 | if(yylval.txt[l-2]=='\r') { 57 | yylval.txt[l-2]='\n'; 58 | yylval.txt[l-1]='\0'; 59 | } 60 | return REM; 61 | } 62 | } 63 | 64 | "\x0d\n" | 65 | \n { lineno++; } 66 | 67 | "abs" { return ABS; } 68 | "after" { return AFTER; } 69 | "and" { return AND; } 70 | "architecture" { return ARCHITECTURE; } 71 | "array" { return ARRAY; } 72 | "assert" { return ASSERT; } 73 | "begin" { return BEGN; } 74 | "case" { return CASE; } 75 | "component" { return COMPONENT; } 76 | "constant" { return CONSTANT; } 77 | "downto" { return DOWNTO; } 78 | "else" { return ELSE; } 79 | "elsif" { return ELSIF; } 80 | "end" { return END; } 81 | "entity" { return ENTITY; } 82 | "entity ".*\. { ; /* to remove entity instantiation */ } 83 | "exit" { return EXIT; } 84 | "for" { return FOR; } 85 | "generate" { return GENERATE; } 86 | "generic" { return GENERIC; } 87 | "if" { return IF; } 88 | "in" { return IN; } 89 | "inout" { return INOUT; } 90 | "is" { return IS; } 91 | "library ".*\n { lineno++; } 92 | "loop" { return LOOP; } 93 | "map" { return MAP; } 94 | "mod" { return MOD; } 95 | "nand" { return NAND; } 96 | "nor" { return NOR; } 97 | "not" { return NOT; } 98 | "null" { return NULLV; } 99 | "of" { return OF; } 100 | "open" { return OPEN; } 101 | "out" { return OUT; } 102 | "or" { return OR; } 103 | "others" { return OTHERS; } 104 | "port" { return PORT; } 105 | "process" { return PROCESS; } 106 | "range" { return RANGE; } 107 | "rem" { return RW_REM; } 108 | "report" { return REPORT;} 109 | "rol" { return ROL; } 110 | "ror" { return ROR; } 111 | "select" { return SELECT; } 112 | "severity" { return SEVERITY;} 113 | "signal" { return SIGNAL; } 114 | "sla" { return SLA; } 115 | "sll" { return SLL; } 116 | "sra" { return SRA; } 117 | "srl" { return SRL; } 118 | "then" { return THEN; } 119 | "to" { return TO; } 120 | "type" { return TYPE; } 121 | "use ".*\n { lineno++; } 122 | "variable" { return VARIABLE; } 123 | "when" { return WHEN; } 124 | "while" { return WHILE; } 125 | "with" { return WITH; } 126 | "xnor" { return XNOR; } 127 | "xor" { return XOR; } 128 | 129 | "time" | 130 | "natural" | 131 | "positive" | 132 | "integer" { return INTEGER; } 133 | "boolean" | 134 | "std_logic" | 135 | "std_ulogic" { return BIT; } 136 | "signed" | 137 | "unsigned" | 138 | "std_logic_vector" | 139 | "std_ulogic_vector" { return BITVECT; } 140 | "real" { return REAL; } 141 | "resize" | 142 | "to_unsigned" { return CONVFUNC_2; } 143 | "to_integer" | 144 | "conv_integer" { return CONVFUNC_1; } 145 | 146 | "shift_left" { return SHIFT_LEFT; } 147 | "shift_right" { return SHIFT_RIGHT; } 148 | "rotate_left" { return ROTATE_LEFT; } 149 | "rotate_right" { return ROTATE_RIGHT; } 150 | 151 | "event" { return EVENT; } 152 | "rising_edge" { return POSEDGE; } 153 | "falling_edge" { return NEGEDGE; } 154 | 155 | "left" | 156 | "high" { return LEFT; } 157 | 158 | "failure" { return FAILURE; } 159 | "error" { return ERROR; } 160 | "warning" { return WARNING; } 161 | "note" { return NOTE; } 162 | 163 | "**" { return POW; } 164 | 165 | \"[ \!#-~]*\" | 166 | \'[01xz]\' { 167 | getstring(1); 168 | return STRING; 169 | } 170 | 171 | #[0-9a-f]*# { 172 | getbasedstring(1); /* skip leading # */ 173 | return BASED; 174 | } 175 | 176 | [a-zA-Z_$][a-zA-Z0-9_$.]* { 177 | yylval.txt=xstrdup(yytext); 178 | return NAME; 179 | } 180 | 181 | [0-9][0-9_]* { 182 | yylval.n = scan_int(yytext); 183 | return NATURAL; 184 | } 185 | 186 | [0-9]+e[-+]?[0-9]+ | 187 | [0-9]+\.[0-9]+e[-+]?[0-9]+ { 188 | yylval.txt=xstrdup(yytext); 189 | return SCIENTIFIC; 190 | } 191 | 192 | [0-9]+\.[0-9]+ { 193 | getstring(0); 194 | return FLOAT; 195 | } 196 | 197 | . { return yytext[0]; } 198 | 199 | %% 200 | 201 | void getstring(unsigned skip){ 202 | /* Gets a string excluding " or ' */ 203 | unsigned i; 204 | for(i=skip; yytext[i]!='"' && yytext[i]!='\'' && yytext[i]!=0; i++); 205 | yytext[i]=0; 206 | yylval.txt=malloc(i+1); 207 | strcpy(yylval.txt, yytext+skip); 208 | } 209 | 210 | void getbasedstring(unsigned skip){ 211 | /* Gets a string excluding # */ 212 | unsigned i; 213 | for(i=skip; yytext[i]!='#' && yytext[i]!=0; i++); 214 | yytext[i]=0; 215 | yylval.txt=malloc(i+1); 216 | strcpy(yylval.txt, yytext+skip); 217 | } 218 | 219 | int scan_int(char *s){ 220 | char c; 221 | int nn = 0; 222 | while ((c=*s++)) { 223 | if (c>='0' && c<='9') nn = nn*10 + (c-'0'); 224 | /* ignore underscores and any other non-digit; depend on 225 | * the lex pattern to only feed us digits and underscores */ 226 | } 227 | return nn; 228 | } 229 | 230 | void yyerror(char *s){ 231 | fprintf(stderr,"%s at \"%s\" in line %d.\n\n",s,yytext,lineno); 232 | } 233 | -------------------------------------------------------------------------------- /translated_examples/Makefile: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | IVERILOG = iverilog 4 | V_FILES = $(sort $(wildcard *.v)) 5 | all: $(V_FILES:%.v=%_check) 6 | 7 | %_check: %.v 8 | $(IVERILOG) -Wall -y . -t null $< 9 | -------------------------------------------------------------------------------- /translated_examples/Scientific.v: -------------------------------------------------------------------------------- 1 | 2 | module Scientific( 3 | input wire clk 4 | ); 5 | 6 | parameter [31:0] exp1=25e6; 7 | parameter [31:0] exp2=25E6; 8 | parameter exp3=25.0e6; 9 | parameter exp4=50.0e+3; 10 | parameter exp5=50.0e-3; 11 | 12 | 13 | 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /translated_examples/based.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module based( 4 | input wire sysclk 5 | ); 6 | 7 | 8 | 9 | 10 | wire [31:0] foo; wire [31:0] foo1; wire [31:0] foo2; wire [31:0] foo8; wire [31:0] foo10; wire [31:0] foo11; wire [31:0] foo16; 11 | 12 | assign foo = 123; 13 | assign foo1 = 123456; 14 | assign foo2 = 'B00101101110111; 15 | assign foo8 = 'O0177362; 16 | assign foo10 = 'D01234; 17 | //foo11<= 11#01234#; 18 | assign foo16 = 'H12af; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /translated_examples/bigfile.v: -------------------------------------------------------------------------------- 1 | // CONNECTIVITY DEFINITION 2 | // no timescale needed 3 | 4 | module bigfile( 5 | input wire sysclk, 6 | input wire [31:0] g_zaq_in, 7 | input wire [31:0] g_aux, 8 | input wire scanb, 9 | input wire g_wrb, 10 | input wire g_rdb, 11 | input wire [31:0] g_noop_clr, 12 | input wire swe_ed, 13 | input wire swe_lv, 14 | input wire [63:0] din, 15 | input wire [4:0] g_dout_w0x0f, 16 | input wire n9_bit_write, 17 | input wire reset, 18 | input wire [31:0] alu_u, 19 | input wire debct_ping, 20 | output wire [31:0] g_sys_in, 21 | output wire [31:0] g_zaq_in_rst_hold, 22 | output wire [31:0] g_zaq_hhh_enb, 23 | output wire [31:0] g_zaq_out, 24 | output wire [31:0] g_dout, 25 | output wire [31:0] g_zaq_ctl, 26 | output wire [31:0] g_zaq_qaz_hb, 27 | output wire [31:0] g_zaq_qaz_lb, 28 | output reg [31:0] gwerth, 29 | output wire [31:0] g_noop, 30 | output reg [8 * 32 - 1:0] g_vector, 31 | output reg [31:0] swe_qaz1 32 | ); 33 | 34 | // from external pins 35 | // from reset_gen block 36 | 37 | 38 | 39 | // IMPLEMENTATION 40 | // constants 41 | parameter g_t_klim_w0x0f = 5'b00000; 42 | parameter g_t_u_w0x0f = 5'b00001; 43 | parameter g_t_l_w0x0f = 5'b00010; 44 | parameter g_t_hhh_l_w0x0f = 5'b00011; 45 | parameter g_t_jkl_sink_l_w0x0f = 5'b00100; 46 | parameter g_secondary_t_l_w0x0f = 5'b00101; 47 | parameter g_style_c_l_w0x0f = 5'b00110; 48 | parameter g_e_z_w0x0f = 5'b00111; 49 | parameter g_n_both_qbars_l_w0x0f = 5'b01000; 50 | parameter g_style_vfr_w0x0f = 5'b01001; 51 | parameter g_style_klim_w0x0f = 5'b01010; 52 | parameter g_unklimed_style_vfr_w0x0f = 5'b01011; 53 | parameter g_style_t_y_w0x0f = 5'b01100; 54 | parameter g_n_l_w0x0f = 5'b01101; 55 | parameter g_n_vfr_w0x0f = 5'b01110; 56 | parameter g_e_n_r_w0x0f = 5'b01111; 57 | parameter g_n_r_bne_w0x0f = 5'b10000; 58 | parameter g_n_div_rebeq_w0x0f = 5'b10001; 59 | parameter g_alu_l_w0x0f = 5'b10010; 60 | parameter g_t_qaz_mult_low_w0x0f = 5'b10011; 61 | parameter g_t_qaz_mult_high_w0x0f = 5'b10100; 62 | parameter gwerthernal_style_u_w0x0f = 5'b10101; 63 | parameter gwerthernal_style_l_w0x0f = 5'b10110; 64 | parameter g_style_main_reset_hold_w0x0f = 5'b10111; // comment 65 | reg [31:0] g_t_klim_dout; 66 | reg [31:0] g_t_u_dout; 67 | reg [31:0] g_t_l_dout; 68 | reg [31:0] g_t_hhh_l_dout; 69 | reg [31:0] g_t_jkl_sink_l_dout; 70 | reg [31:0] g_secondary_t_l_dout; 71 | reg [3:0] g_style_c_l_dout; // not used 72 | reg [31:0] g_e_z_dout; 73 | reg [31:0] g_n_both_qbars_l_dout; 74 | wire [31:0] g_style_vfr_dout; 75 | reg [31:0] g_style_klim_dout; 76 | wire [31:0] g_unklimed_style_vfr_dout; 77 | reg [31:0] g_style_t_y_dout; 78 | reg [31:0] g_n_l_dout; 79 | reg [31:0] g_n_vfr_dout; 80 | reg [31:0] g_e_n_r_dout; 81 | reg g_n_r_bne_dout; 82 | reg [31:0] g_n_div_rebeq_dout; 83 | reg [31:0] g_alu_l_dout; 84 | reg [31:0] g_t_qaz_mult_low_dout; 85 | reg [31:0] g_t_qaz_mult_high_dout; 86 | reg [31:0] gwerthernal_style_u_dout; 87 | reg [31:0] gwerthernal_style_l_dout; 88 | reg [31:0] g_style_main_reset_hold_dout; // other 89 | reg [31:0] q_g_zaq_in; 90 | reg [31:0] q2_g_zaq_in; 91 | reg [31:0] q3_g_zaq_in; 92 | reg [3:0] q_g_zaq_in_cd; 93 | reg [31:0] q_g_style_vfr_dout; 94 | reg [3:0] q_g_unzq; 95 | wire [31:0] g_n_active; // inter 96 | wire [31:0] g_zaq_in_y; 97 | wire [31:0] g_zaq_in_y_no_dout; 98 | wire [31:0] g_zaq_out_i; 99 | wire [31:0] g_zaq_ctl_i; 100 | wire [31:0] g_sys_in_i; 101 | wire [31:0] g_sys_in_ii; 102 | wire [31:0] g_dout_i; 103 | 104 | // qaz out 105 | assign g_zaq_out_i = (g_secondary_t_l_dout & (g_aux ^ g_style_t_y_dout)) | (g_alu_l_dout & alu_u & ~g_secondary_t_l_dout) | ( ~g_alu_l_dout & ~g_secondary_t_l_dout & g_t_u_dout); 106 | // Changed 107 | assign g_zaq_out = g_zaq_out_i & ~g_t_jkl_sink_l_dout; 108 | // qaz 109 | // JLB 110 | assign g_zaq_ctl_i = ~((g_t_l_dout & ~g_t_jkl_sink_l_dout) | (g_t_l_dout & g_t_jkl_sink_l_dout & ~g_zaq_out_i)); 111 | // mux 112 | //vnavigatoroff 113 | assign g_zaq_ctl = scanb == 1'b1 ? g_zaq_ctl_i : 32'b00000000000000000000000000000000; 114 | //vnavigatoron 115 | assign g_zaq_hhh_enb = ~(g_t_hhh_l_dout); 116 | assign g_zaq_qaz_hb = g_t_qaz_mult_high_dout; 117 | assign g_zaq_qaz_lb = g_t_qaz_mult_low_dout; 118 | // Dout 119 | assign g_dout_i = g_dout_w0x0f == g_t_klim_w0x0f ? g_t_klim_dout & g_style_klim_dout : g_dout_w0x0f == g_t_u_w0x0f ? g_t_u_dout & g_style_klim_dout : g_dout_w0x0f == g_t_l_w0x0f ? g_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_hhh_l_w0x0f ? g_t_hhh_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_jkl_sink_l_w0x0f ? g_t_jkl_sink_l_dout & g_style_klim_dout : g_dout_w0x0f == g_secondary_t_l_w0x0f ? g_secondary_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_style_c_l_w0x0f ? ({28'b0000000000000000000000000000,g_style_c_l_dout}) & g_style_klim_dout : g_dout_w0x0f == g_e_z_w0x0f ? g_e_z_dout : g_dout_w0x0f == g_n_both_qbars_l_w0x0f ? g_n_both_qbars_l_dout : g_dout_w0x0f == g_style_vfr_w0x0f ? g_style_vfr_dout & g_style_klim_dout : g_dout_w0x0f == g_style_klim_w0x0f ? g_style_klim_dout : g_dout_w0x0f == g_unklimed_style_vfr_w0x0f ? g_unklimed_style_vfr_dout : g_dout_w0x0f == g_style_t_y_w0x0f ? g_style_t_y_dout & g_style_klim_dout : g_dout_w0x0f == g_n_l_w0x0f ? g_n_l_dout : g_dout_w0x0f == g_n_vfr_w0x0f ? g_n_vfr_dout : g_dout_w0x0f == g_e_n_r_w0x0f ? g_e_n_r_dout : g_dout_w0x0f == g_n_r_bne_w0x0f ? {31'b0000000000000000000000000000000,g_n_r_bne_dout} : g_dout_w0x0f == g_n_div_rebeq_w0x0f ? g_n_div_rebeq_dout : g_dout_w0x0f == g_alu_l_w0x0f ? g_alu_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_low_w0x0f ? g_t_qaz_mult_low_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_high_w0x0f ? g_t_qaz_mult_high_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_u_w0x0f ? gwerthernal_style_u_dout & g_style_klim_dout : g_dout_w0x0f == g_style_main_reset_hold_w0x0f ? g_style_main_reset_hold_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_l_w0x0f ? gwerthernal_style_l_dout & g_style_klim_dout : 32'b00000000000000000000000000000000; 120 | assign g_dout = g_rdb == 1'b0 ? g_dout_i : {32{1'b1}}; 121 | // this can be used to use zzz1 122 | always @(posedge sysclk) begin 123 | if((scanb == 1'b1)) begin 124 | if((reset == 1'b1)) begin 125 | g_style_main_reset_hold_dout <= g_zaq_in; 126 | end 127 | //vnavigatoroff 128 | end 129 | else begin 130 | g_style_main_reset_hold_dout <= q2_g_zaq_in; 131 | end 132 | //vnavigatoron 133 | end 134 | 135 | // qaz 136 | assign g_zaq_in_rst_hold = g_style_main_reset_hold_dout; 137 | // Din 138 | always @(posedge reset, posedge sysclk) begin : P5 139 | reg [4:0] g_dout_w0x0f_v; 140 | reg [31:0] i; 141 | reg [31:0] j; 142 | 143 | if((reset != 1'b0)) begin 144 | g_t_klim_dout <= {32{1'b0}}; 145 | g_t_u_dout <= {32{1'b0}}; 146 | g_t_l_dout <= {32{1'b0}}; 147 | g_t_hhh_l_dout <= {32{1'b0}}; 148 | g_t_jkl_sink_l_dout <= {32{1'b0}}; 149 | g_secondary_t_l_dout <= {32{1'b0}}; 150 | g_style_c_l_dout <= {4{1'b0}}; 151 | g_e_z_dout <= {32{1'b0}}; 152 | g_n_both_qbars_l_dout <= {32{1'b0}}; 153 | g_style_klim_dout <= {32{1'b0}}; 154 | g_style_t_y_dout <= {32{1'b0}}; 155 | g_n_l_dout <= {32{1'b0}}; 156 | g_e_n_r_dout <= {32{1'b0}}; 157 | g_n_r_bne_dout <= 1'b0; 158 | g_n_div_rebeq_dout <= {32{1'b1}}; 159 | g_alu_l_dout <= {32{1'b0}}; 160 | g_t_qaz_mult_low_dout <= {32{1'b1}}; 161 | // NOTE Low 162 | g_t_qaz_mult_high_dout <= {32{1'b0}}; 163 | gwerthernal_style_u_dout <= {32{1'b0}}; 164 | gwerthernal_style_l_dout <= {32{1'b0}}; 165 | end else begin 166 | // clear 167 | g_n_div_rebeq_dout <= g_n_div_rebeq_dout & ~g_noop_clr; 168 | if((g_wrb == 1'b0)) begin 169 | // because we now... 170 | for (i=0; i <= 1; i = i + 1) begin 171 | if((i == 0)) begin 172 | g_dout_w0x0f_v = g_dout_w0x0f; 173 | end 174 | else if((i == 1)) begin 175 | if((n9_bit_write == 1'b1)) begin 176 | // set 177 | g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b1}; 178 | end 179 | //vnavigatoroff 180 | end 181 | else begin 182 | // not possible but added for code coverage's sake 183 | end 184 | //vnavigatoron 185 | case(g_dout_w0x0f_v) 186 | g_t_klim_w0x0f : begin 187 | g_t_klim_dout <= din[i * 32 + 31 -: 31 + 1]; 188 | end 189 | g_t_u_w0x0f : begin 190 | // output klim 191 | for (j=0; j <= 31; j = j + 1) begin 192 | if(((g_t_klim_dout[j] == 1'b0 && n9_bit_write == 1'b0) || (din[j] == 1'b0 && n9_bit_write == 1'b1))) begin 193 | g_t_u_dout[j] <= din[32 * i + j]; 194 | end 195 | end 196 | end 197 | g_t_l_w0x0f : begin 198 | g_t_l_dout <= din[i * 32 + 31 -: 31 + 1]; 199 | end 200 | g_t_hhh_l_w0x0f : begin 201 | g_t_hhh_l_dout <= din[i * 32 + 31 -: 31 + 1]; 202 | end 203 | g_t_jkl_sink_l_w0x0f : begin 204 | g_t_jkl_sink_l_dout <= din[i * 32 + 31 -: 31 + 1]; 205 | end 206 | g_secondary_t_l_w0x0f : begin 207 | g_secondary_t_l_dout <= din[i * 32 + 31 -: 31 + 1]; 208 | end 209 | g_style_c_l_w0x0f : begin 210 | g_style_c_l_dout[3:0] <= din[3 + i * 32 -: 3 + 1]; 211 | end 212 | g_e_z_w0x0f : begin 213 | g_e_z_dout <= din[i * 32 + 31 -: 31 + 1]; 214 | end 215 | g_n_both_qbars_l_w0x0f : begin 216 | g_n_both_qbars_l_dout <= din[i * 32 + 31 -: 31 + 1]; 217 | end 218 | g_style_vfr_w0x0f : begin 219 | // read-only register 220 | end 221 | g_style_klim_w0x0f : begin 222 | g_style_klim_dout <= din[i * 32 + 31 -: 31 + 1]; 223 | end 224 | g_unklimed_style_vfr_w0x0f : begin 225 | // read-only register 226 | end 227 | g_style_t_y_w0x0f : begin 228 | g_style_t_y_dout <= din[i * 32 + 31 -: 31 + 1]; 229 | end 230 | g_n_l_w0x0f : begin 231 | g_n_l_dout <= din[i * 32 + 31 -: 31 + 1]; 232 | end 233 | g_n_vfr_w0x0f : begin 234 | // writes 235 | end 236 | g_e_n_r_w0x0f : begin 237 | g_e_n_r_dout <= din[i * 32 + 31 -: 31 + 1]; 238 | end 239 | g_n_r_bne_w0x0f : begin 240 | g_n_r_bne_dout <= din[i * 32]; 241 | end 242 | g_n_div_rebeq_w0x0f : begin 243 | g_n_div_rebeq_dout <= din[i * 32 + 31 -: 31 + 1] | g_n_div_rebeq_dout; 244 | // a '1' writes 245 | end 246 | g_alu_l_w0x0f : begin 247 | g_alu_l_dout <= din[i * 32 + 31 -: 31 + 1]; 248 | end 249 | g_t_qaz_mult_low_w0x0f : begin 250 | g_t_qaz_mult_low_dout <= din[i * 32 + 31 -: 31 + 1]; 251 | end 252 | g_t_qaz_mult_high_w0x0f : begin 253 | g_t_qaz_mult_high_dout <= din[i * 32 + 31 -: 31 + 1]; 254 | end 255 | gwerthernal_style_u_w0x0f : begin 256 | gwerthernal_style_u_dout <= din[i * 32 + 31 -: 31 + 1]; 257 | end 258 | gwerthernal_style_l_w0x0f : begin 259 | gwerthernal_style_l_dout <= din[i * 32 + 31 -: 31 + 1]; 260 | //vnavigatoroff 261 | end 262 | default : begin 263 | //vnavigatoron 264 | end 265 | endcase 266 | end 267 | end 268 | end 269 | end 270 | 271 | // sample 272 | always @(posedge reset, posedge sysclk) begin 273 | if((reset != 1'b0)) begin 274 | q_g_zaq_in <= {32{1'b0}}; 275 | q2_g_zaq_in <= {32{1'b0}}; 276 | q3_g_zaq_in <= {32{1'b0}}; 277 | end else begin 278 | q_g_zaq_in <= g_zaq_in; 279 | q2_g_zaq_in <= q_g_zaq_in; 280 | q3_g_zaq_in <= g_zaq_in_y; 281 | end 282 | end 283 | 284 | // vfr register 285 | assign g_unklimed_style_vfr_dout = q2_g_zaq_in; 286 | // switch 287 | assign g_zaq_in_y = g_style_t_y_dout ^ q2_g_zaq_in; 288 | // qaz 289 | assign g_style_vfr_dout = {g_zaq_in_y[31:4],(g_style_c_l_dout[3:0] & q_g_zaq_in_cd) | ( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])}; 290 | // in scan mode 291 | assign g_zaq_in_y_no_dout = scanb == 1'b1 ? g_style_t_y_dout ^ g_zaq_in : g_style_t_y_dout; 292 | //vnavigatoron 293 | assign g_sys_in_i = {g_zaq_in_y_no_dout[31:4],(g_style_c_l_dout[3:0] & q_g_zaq_in_cd) | ( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])}; 294 | assign g_sys_in_ii = (g_sys_in_i & ~gwerthernal_style_l_dout) | (gwerthernal_style_u_dout & gwerthernal_style_l_dout); 295 | assign g_sys_in = g_sys_in_ii; 296 | always @(posedge reset, posedge sysclk) begin : P4 297 | reg [31:0] i; 298 | 299 | if((reset != 1'b0)) begin 300 | q_g_zaq_in_cd <= {4{1'b0}}; 301 | q_g_unzq <= {4{1'b1}}; 302 | end else begin 303 | // sample 304 | if((debct_ping == 1'b1)) begin 305 | // taken 306 | for (i=0; i <= 3; i = i + 1) begin 307 | if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin 308 | q_g_unzq[i] <= 1'b1; 309 | end 310 | else begin 311 | if((q_g_unzq[i] == 1'b0)) begin 312 | q_g_zaq_in_cd[i] <= g_zaq_in_y[i]; 313 | end 314 | else begin 315 | q_g_unzq[i] <= 1'b0; 316 | end 317 | end 318 | end 319 | end 320 | else begin 321 | for (i=0; i <= 3; i = i + 1) begin 322 | if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin 323 | q_g_unzq[i] <= 1'b1; 324 | end 325 | end 326 | end 327 | end 328 | end 329 | 330 | // generate lqqs 331 | always @(posedge reset, posedge sysclk) begin 332 | if((reset != 1'b0)) begin 333 | q_g_style_vfr_dout <= {32{1'b0}}; 334 | end else begin 335 | if((scanb == 1'b1)) begin 336 | q_g_style_vfr_dout <= g_style_vfr_dout; 337 | //vnavigatoroff 338 | end 339 | else begin 340 | // in scan 341 | q_g_style_vfr_dout <= g_style_vfr_dout | ({g_zaq_out_i[31:17],1'b0,g_zaq_out_i[15:1],1'b0}) | g_zaq_ctl_i | g_sys_in_ii; 342 | end 343 | //vnavigatoron 344 | end 345 | end 346 | 347 | // generate 348 | assign g_n_active = ((q_g_style_vfr_dout & ~g_style_vfr_dout) | ( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout)) & g_n_l_dout; 349 | // check for lqq active and set lqq vfr register 350 | // also clear 351 | always @(posedge reset, posedge sysclk) begin : P3 352 | reg [31:0] i; 353 | 354 | if((reset != 1'b0)) begin 355 | g_n_vfr_dout <= {32{1'b0}}; 356 | gwerth <= {32{1'b0}}; 357 | end else begin 358 | for (i=0; i <= 31; i = i + 1) begin 359 | // lqq 360 | // vfr matches 361 | if((g_n_active[i] == 1'b1)) begin 362 | gwerth[i] <= 1'b1; 363 | if((g_e_z_dout[i] == 1'b1)) begin 364 | // lqq 365 | g_n_vfr_dout[i] <= 1'b1; 366 | end 367 | else begin 368 | g_n_vfr_dout[i] <= q_g_style_vfr_dout[i]; 369 | end 370 | end 371 | else begin 372 | // clear 373 | if((g_e_z_dout[i] == 1'b0)) begin 374 | g_n_vfr_dout[i] <= q_g_style_vfr_dout[i]; 375 | // default always assign 376 | // in both 377 | if((g_n_both_qbars_l_dout[i] == 1'b1 || g_style_vfr_dout[i] == 1'b1)) begin 378 | gwerth[i] <= 1'b0; 379 | end 380 | end 381 | else begin 382 | // write 383 | if((g_wrb == 1'b0 && g_dout_w0x0f == g_n_vfr_w0x0f && din[i] == 1'b1)) begin 384 | gwerth[i] <= 1'b0; 385 | g_n_vfr_dout[i] <= 1'b0; 386 | end 387 | end 388 | end 389 | end 390 | end 391 | end 392 | 393 | //-- 394 | // Create the Lqq 395 | always @(g_n_r_bne_dout, g_e_n_r_dout) begin : P2 396 | reg [31:0] imod8, idiv8; 397 | reg [31:0] i; 398 | 399 | for (i=0; i <= 31; i = i + 1) begin 400 | imod8 = i % 8; 401 | idiv8 = i / 8; 402 | if((g_n_r_bne_dout == 1'b0)) begin 403 | // non-unique 404 | g_vector[8 * i + 7 -: 7 + 1] <= g_e_n_r_dout[8 * idiv8 + 7 -: 7 + 1]; 405 | end 406 | else begin 407 | // unique 408 | if((imod8 == 0)) begin 409 | g_vector[8 * i + 7 -: 7 + 1] <= g_e_n_r_dout[8 * idiv8 + 7 -: 7 + 1]; 410 | end 411 | else begin 412 | g_vector[8 * i + 7 -: 7 + 1] <= (g_e_n_r_dout[8 * idiv8 + 7 -: 7 + 1]) + (imod8); 413 | end 414 | end 415 | end 416 | end 417 | 418 | //-- 419 | // Qaz 420 | assign g_noop = g_n_div_rebeq_dout; 421 | always @(swe_ed, swe_lv, g_e_z_dout) begin : P1 422 | reg [31:0] i; 423 | 424 | for (i=0; i <= 31; i = i + 1) begin 425 | if((g_e_z_dout[i] == 1'b1)) begin 426 | swe_qaz1[i] <= swe_ed; 427 | end 428 | else begin 429 | swe_qaz1[i] <= swe_lv; 430 | end 431 | end 432 | end 433 | 434 | 435 | endmodule 436 | -------------------------------------------------------------------------------- /translated_examples/clk.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module clk( 4 | input wire reset, 5 | input wire preset, 6 | input wire qreset, 7 | input wire sysclk, 8 | input wire dsysclk, 9 | input wire esysclk, 10 | input wire [31:0] ival 11 | ); 12 | 13 | 14 | 15 | 16 | reg [10 + 3:0] foo; 17 | reg [2:0] baz; 18 | reg [4:7 - 1] egg; 19 | 20 | always @(posedge reset, posedge sysclk) begin 21 | if((reset != 1'b0)) begin 22 | foo <= {((10 + 3)-(0)+1){1'b1}}; 23 | end else begin 24 | foo <= ival[31:31 - (10 + 3)]; 25 | end 26 | end 27 | 28 | always @(negedge preset, negedge dsysclk) begin 29 | if((preset != 1'b1)) begin 30 | baz <= {3{1'b0}}; 31 | end else begin 32 | baz <= ival[2:0]; 33 | end 34 | end 35 | 36 | always @(negedge qreset, negedge esysclk) begin 37 | if((qreset != 1'b1)) begin 38 | egg <= {((7 - 1)-(4)+1){1'b0}}; 39 | end else begin 40 | egg <= ival[6:4]; 41 | end 42 | end 43 | 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /translated_examples/concat.v: -------------------------------------------------------------------------------- 1 | 2 | module concat_demo( 3 | input wire reset 4 | ); 5 | 6 | parameter [26:0] abc={3'b010,12'haaa}; 7 | parameter [31:0] xyz=8'hff; 8 | 9 | 10 | 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /translated_examples/counters.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module counters( 4 | input wire sysclk, 5 | input wire foo_card, 6 | input wire wfoo0_baz, 7 | input wire wfoo0_blrb, 8 | input wire wfoo0_zz1pb, 9 | input wire [31:0] wfoo0_turn, 10 | input wire debct_baz, 11 | input wire debct_blrb, 12 | input wire debct_zz1pb, 13 | input wire debct_bar, 14 | input wire [31:0] debct_turn, 15 | input wire Z0_bar, 16 | input wire Z0_baz, 17 | input wire Z0_blrb, 18 | input wire Z0_zz1pb, 19 | input wire [31:0] Z0_turn, 20 | input wire Y1_bar, 21 | input wire Y1_baz, 22 | input wire Y1_blrb, 23 | input wire Y1_zz1pb, 24 | input wire [31:0] Y1_turn, 25 | input wire X2_bar, 26 | input wire X2_baz, 27 | input wire X2_blrb, 28 | input wire X2_zz1pb, 29 | input wire [31:0] X2_turn, 30 | input wire W3_bar, 31 | input wire W3_baz, 32 | input wire W3_blrb, 33 | input wire W3_zz1pb, 34 | input wire [31:0] W3_turn, 35 | output wire Z0_cwm, 36 | output wire [31:0] Z0, 37 | output wire Y1_cwm, 38 | output wire [31:0] Y1, 39 | output wire X2_cwm, 40 | output wire [31:0] X2, 41 | output wire W3_cwm, 42 | output wire [31:0] W3, 43 | output reg wfoo0_cwm, 44 | output wire [31:0] wfoo0_llwln, 45 | output wire debct_cwm, 46 | output reg debct_pull, 47 | output wire [31:0] debct, 48 | output wire wdfilecardA2P 49 | ); 50 | 51 | // to engine block 52 | 53 | 54 | 55 | reg [31:0] wfoo0_llwln_var; 56 | reg [31:0] debct_var; 57 | reg [31:0] Z0_var; 58 | reg [31:0] Y1_var; 59 | reg [31:0] X2_var; 60 | reg [31:0] W3_var; 61 | reg main_wfoo0_cwm; 62 | reg do_q3p_Z0; 63 | reg do_q3p_Y1; 64 | reg do_q3p_X2; 65 | reg do_q3p_W3; 66 | reg do_q3p_wfoo0; 67 | reg do_q3p_debct; 68 | reg Z0_cwm_i; 69 | reg Y1_cwm_i; 70 | reg X2_cwm_i; 71 | reg W3_cwm_i; 72 | reg debct_cwm_i; 73 | reg file_card_i; 74 | reg do_file_card_i; 75 | reg prev_do_file_card; 76 | 77 | //--- 78 | // form the outputs 79 | assign wfoo0_llwln = wfoo0_llwln_var; 80 | assign debct = debct_var; 81 | assign Z0 = Z0_var; 82 | assign Y1 = Y1_var; 83 | assign X2 = X2_var; 84 | assign W3 = W3_var; 85 | assign Z0_cwm = Z0_cwm_i; 86 | assign Y1_cwm = Y1_cwm_i; 87 | assign X2_cwm = X2_cwm_i; 88 | assign W3_cwm = W3_cwm_i; 89 | assign debct_cwm = debct_cwm_i; 90 | assign wdfilecardA2P = do_file_card_i; 91 | always @(posedge foo_card, posedge sysclk) begin 92 | if(foo_card == 1'b1) begin 93 | wfoo0_llwln_var <= {32{1'b0}}; 94 | debct_var <= {32{1'b0}}; 95 | Z0_var <= {32{1'b0}}; 96 | Y1_var <= {32{1'b0}}; 97 | X2_var <= {32{1'b0}}; 98 | W3_var <= {32{1'b0}}; 99 | wfoo0_cwm <= 1'b0; 100 | debct_cwm_i <= 1'b0; 101 | debct_pull <= 1'b0; 102 | Z0_cwm_i <= 1'b0; 103 | Y1_cwm_i <= 1'b0; 104 | X2_cwm_i <= 1'b0; 105 | W3_cwm_i <= 1'b0; 106 | main_wfoo0_cwm <= 1'b0; 107 | file_card_i <= 1'b0; 108 | do_q3p_wfoo0 <= 1'b0; 109 | do_file_card_i <= 1'b0; 110 | prev_do_file_card <= 1'b0; 111 | do_q3p_Z0 <= 1'b0; 112 | do_q3p_Y1 <= 1'b0; 113 | do_q3p_X2 <= 1'b0; 114 | do_q3p_W3 <= 1'b0; 115 | do_q3p_debct <= 1'b0; 116 | end else begin 117 | // pull 118 | debct_pull <= 1'b0; 119 | do_file_card_i <= 1'b0; 120 | //-- 121 | // wfoo0 122 | if(wfoo0_baz == 1'b1) begin 123 | wfoo0_llwln_var <= wfoo0_turn; 124 | main_wfoo0_cwm <= 1'b0; 125 | if(wfoo0_llwln_var == 32'b00000000000000000000000000000000) begin 126 | do_q3p_wfoo0 <= 1'b0; 127 | end 128 | else begin 129 | do_q3p_wfoo0 <= 1'b1; 130 | end 131 | end 132 | else begin 133 | if(do_q3p_wfoo0 == 1'b1 && wfoo0_blrb == 1'b1) begin 134 | wfoo0_llwln_var <= wfoo0_llwln_var - 1; 135 | if((wfoo0_llwln_var == 32'b00000000000000000000000000000000)) begin 136 | wfoo0_llwln_var <= wfoo0_turn; 137 | if(main_wfoo0_cwm == 1'b0) begin 138 | wfoo0_cwm <= 1'b1; 139 | main_wfoo0_cwm <= 1'b1; 140 | end 141 | else begin 142 | do_file_card_i <= 1'b1; 143 | do_q3p_wfoo0 <= 1'b0; 144 | end 145 | end 146 | end 147 | end 148 | if(wfoo0_zz1pb == 1'b0) begin 149 | wfoo0_cwm <= 1'b0; 150 | end 151 | if(Z0_baz == 1'b1) begin 152 | // counter Baz 153 | Z0_var <= Z0_turn; 154 | if(Z0_turn == 32'b00000000000000000000000000000000) begin 155 | do_q3p_Z0 <= 1'b0; 156 | end 157 | else begin 158 | do_q3p_Z0 <= 1'b1; 159 | end 160 | end 161 | else begin 162 | if(do_q3p_Z0 == 1'b1 && Z0_blrb == 1'b1) begin 163 | if(Z0_bar == 1'b0) begin 164 | if(Z0_cwm_i == 1'b0) begin 165 | if(do_q3p_Z0 == 1'b1) begin 166 | Z0_var <= Z0_var - 1; 167 | if((Z0_var == 32'b00000000000000000000000000000001)) begin 168 | Z0_cwm_i <= 1'b1; 169 | do_q3p_Z0 <= 1'b0; 170 | end 171 | end 172 | end 173 | end 174 | else begin 175 | Z0_var <= Z0_var - 1; 176 | if((Z0_var == 32'b00000000000000000000000000000000)) begin 177 | Z0_cwm_i <= 1'b1; 178 | Z0_var <= Z0_turn; 179 | end 180 | end 181 | // Z0_bar 182 | end 183 | end 184 | // Z0_blrb 185 | if(Z0_zz1pb == 1'b0) begin 186 | Z0_cwm_i <= 1'b0; 187 | end 188 | if(Y1_baz == 1'b1) begin 189 | // counter Baz 190 | Y1_var <= Y1_turn; 191 | if(Y1_turn == 32'b00000000000000000000000000000000) begin 192 | do_q3p_Y1 <= 1'b0; 193 | end 194 | else begin 195 | do_q3p_Y1 <= 1'b1; 196 | end 197 | end 198 | else if(do_q3p_Y1 == 1'b1 && Y1_blrb == 1'b1) begin 199 | if(Y1_bar == 1'b0) begin 200 | if(Y1_cwm_i == 1'b0) begin 201 | if(do_q3p_Y1 == 1'b1) begin 202 | Y1_var <= Y1_var - 1; 203 | if((Y1_var == 32'b00000000000000000000000000000001)) begin 204 | Y1_cwm_i <= 1'b1; 205 | do_q3p_Y1 <= 1'b0; 206 | end 207 | end 208 | end 209 | end 210 | else begin 211 | Y1_var <= Y1_var - 1; 212 | if((Y1_var == 32'b00000000000000000000000000000000)) begin 213 | Y1_cwm_i <= 1'b1; 214 | Y1_var <= Y1_turn; 215 | end 216 | end 217 | // Y1_bar 218 | end 219 | // Y1_blrb 220 | if(Y1_zz1pb == 1'b0) begin 221 | Y1_cwm_i <= 1'b0; 222 | end 223 | if(X2_baz == 1'b1) begin 224 | // counter Baz 225 | X2_var <= X2_turn; 226 | if(X2_turn == 32'b00000000000000000000000000000000) begin 227 | do_q3p_X2 <= 1'b0; 228 | end 229 | else begin 230 | do_q3p_X2 <= 1'b1; 231 | end 232 | end 233 | else if(do_q3p_X2 == 1'b1 && X2_blrb == 1'b1) begin 234 | if(X2_bar == 1'b0) begin 235 | if(X2_cwm_i == 1'b0) begin 236 | if(do_q3p_X2 == 1'b1) begin 237 | X2_var <= X2_var - 1; 238 | if((X2_var == 32'b00000000000000000000000000000001)) begin 239 | X2_cwm_i <= 1'b1; 240 | do_q3p_X2 <= 1'b0; 241 | end 242 | end 243 | end 244 | end 245 | else begin 246 | X2_var <= X2_var - 1; 247 | if((X2_var == 32'b00000000000000000000000000000000)) begin 248 | //{ 249 | X2_cwm_i <= 1'b1; 250 | X2_var <= X2_turn; 251 | end 252 | end 253 | //X2_bar 254 | end 255 | // X2_blrb 256 | if(X2_zz1pb == 1'b0) begin 257 | X2_cwm_i <= 1'b0; 258 | end 259 | if(W3_baz == 1'b1) begin 260 | // counter Baz 261 | W3_var <= W3_turn; 262 | if(W3_turn == 32'b00000000000000000000000000000000) begin 263 | do_q3p_W3 <= 1'b0; 264 | end 265 | else begin 266 | do_q3p_W3 <= 1'b1; 267 | end 268 | end 269 | else if(do_q3p_W3 == 1'b1 && W3_blrb == 1'b1) begin 270 | if(W3_bar == 1'b0) begin 271 | if(W3_cwm_i == 1'b0) begin 272 | if(do_q3p_W3 == 1'b1) begin 273 | W3_var <= W3_var - 1; 274 | if((W3_var == 32'b00000000000000000000000000000001)) begin 275 | W3_cwm_i <= 1'b1; 276 | do_q3p_W3 <= 1'b0; 277 | end 278 | end 279 | end 280 | end 281 | else begin 282 | W3_var <= W3_var - 1; 283 | if((W3_var == 32'b00000000000000000000000000000000)) begin 284 | //{ 285 | W3_cwm_i <= 1'b1; 286 | W3_var <= W3_turn; 287 | end 288 | end 289 | // W3_bar 290 | end 291 | // W3_blrb 292 | if(W3_zz1pb == 1'b0) begin 293 | W3_cwm_i <= 1'b0; 294 | end 295 | if(debct_baz == 1'b1) begin 296 | // counter Baz 297 | debct_var <= debct_turn; 298 | if(debct_turn == 32'b00000000000000000000000000000000) begin 299 | do_q3p_debct <= 1'b0; 300 | end 301 | else begin 302 | do_q3p_debct <= 1'b1; 303 | end 304 | end 305 | else if(do_q3p_debct == 1'b1 && debct_blrb == 1'b1) begin 306 | if(debct_bar == 1'b0) begin 307 | if(debct_cwm_i == 1'b0) begin 308 | if(do_q3p_debct == 1'b1) begin 309 | debct_var <= debct_var - 1; 310 | if((debct_var == 32'b00000000000000000000000000000001)) begin 311 | debct_cwm_i <= 1'b1; 312 | debct_pull <= 1'b1; 313 | do_q3p_debct <= 1'b0; 314 | end 315 | end 316 | end 317 | end 318 | else begin 319 | //-- T 320 | // Continue 321 | debct_var <= debct_var - 1; 322 | // ending 323 | if((debct_var == 32'b00000000000000000000000000000000)) begin 324 | //{ 325 | debct_cwm_i <= 1'b1; 326 | debct_pull <= 1'b1; 327 | debct_var <= debct_turn; 328 | end 329 | end 330 | // debct_bar 331 | end 332 | // debct_blrb 333 | // comment 334 | if(debct_zz1pb == 1'b0) begin 335 | debct_cwm_i <= 1'b0; 336 | end 337 | end 338 | end 339 | 340 | 341 | endmodule 342 | -------------------------------------------------------------------------------- /translated_examples/dsp.v: -------------------------------------------------------------------------------- 1 | // Nearly useless stub, it's here to support genericmap.vhd 2 | // no timescale needed 3 | 4 | module dsp( 5 | input wire clk, 6 | input wire rstn, 7 | input wire en, 8 | input wire start, 9 | input wire [7:0] param, 10 | input wire [2:0] addr, 11 | input wire [bus_width - 1:0] din, 12 | input wire we, 13 | output wire [13:0] memdin, 14 | output reg [bus_width - 1:0] dout, 15 | output wire [5:0] memaddr, 16 | output wire [13:0] memdout 17 | ); 18 | 19 | parameter rst_val=1'b0; 20 | parameter [31:0] thing_size=51; 21 | parameter [31:0] bus_width=24; 22 | // Inputs 23 | // Outputs 24 | 25 | 26 | 27 | wire foo; 28 | reg [63:0] sr; 29 | wire [31:0] iparam; 30 | 31 | assign iparam = param; 32 | always @(posedge clk) begin 33 | // dout <= std_logic_vector(to_unsigned(1,bus_width)); 34 | if(we == 1'b1) begin 35 | sr <= {sr[thing_size - bus_width - 1:0],din}; 36 | end 37 | dout <= sr[iparam * bus_width + bus_width - 1 -: bus_width - 1 + 1]; 38 | end 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /translated_examples/expr.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module expr( 4 | input wire reset, 5 | input wire sysclk, 6 | input wire ival 7 | ); 8 | 9 | parameter [31:0] SIZE=2 ** 8 - 1; 10 | 11 | 12 | 13 | parameter SIZE_OF = 2 ** 8 - 1; 14 | reg [13:0] foo; 15 | wire [2:0] baz; 16 | reg [22:0] bam; 17 | wire [5:3] out_i; 18 | wire [8:0] input_status; 19 | wire enable; wire debug; wire aux; wire outy; wire dv; wire value; 20 | wire [2 ** 3 - 1:0] expo; 21 | 22 | // drive input status 23 | assign input_status = {foo[9:4],(baz[2:0] & foo[3:0]) | ( ~baz[2:0] & bam[3:0])}; 24 | // drive based on foo 25 | assign out_i[4] = (enable & (aux ^ outy)) | (debug & dv & ~enable) | ( ~debug & ~enable & value); 26 | // not drive 27 | always @(negedge reset, negedge sysclk) begin 28 | if((reset != 1'b0)) begin 29 | foo <= {14{1'b0}}; 30 | end else begin 31 | foo[3 * (2 - 1)] <= baz[1 * (1 + 2) - 2]; 32 | bam[13:0] <= foo; 33 | end 34 | end 35 | 36 | assign expo = 2 ** 4; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /translated_examples/fifo.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | // Filename: gh_fifo_async16_sr.vhd 3 | // 4 | // Description: 5 | // an Asynchronous FIFO 6 | // 7 | // Copyright (c) 2006 by George Huber 8 | // an OpenCores.org Project 9 | // free to use, but see documentation for conditions 10 | // 11 | // Revision History: 12 | // Revision Date Author Comment 13 | // -------- ---------- --------- ----------- 14 | // 1.0 12/17/06 h lefevre Initial revision 15 | // 16 | //------------------------------------------------------ 17 | // no timescale needed 18 | 19 | module fifo( 20 | input wire clk_WR, 21 | input wire clk_RD, 22 | input wire rst, 23 | input wire srst, 24 | input wire WR, 25 | input wire RD, 26 | input wire [data_width - 1:0] D, 27 | output wire [data_width - 1:0] Q, 28 | output wire empty, 29 | output wire full 30 | ); 31 | 32 | parameter [31:0] data_width=8; 33 | // size of data bus 34 | // write clock 35 | // read clock 36 | // resets counters 37 | // resets counters (sync with clk_WR) 38 | // write control 39 | // read control 40 | 41 | 42 | 43 | 44 | wire [data_width - 1:0] ram_mem[15:0]; 45 | wire iempty; 46 | wire ifull; 47 | wire add_WR_CE; 48 | reg [4:0] add_WR; // 4 bits are used to address MEM 49 | reg [4:0] add_WR_GC; // 5 bits are used to compare 50 | wire [4:0] n_add_WR; // for empty, full flags 51 | reg [4:0] add_WR_RS; // synced to read clk 52 | wire add_RD_CE; 53 | reg [4:0] add_RD; 54 | reg [4:0] add_RD_GC; 55 | reg [4:0] add_RD_GCwc; 56 | wire [4:0] n_add_RD; 57 | reg [4:0] add_RD_WS; // synced to write clk 58 | reg srst_w; 59 | reg isrst_w; 60 | reg srst_r; 61 | reg isrst_r; 62 | 63 | //------------------------------------------ 64 | //----- memory ----------------------------- 65 | //------------------------------------------ 66 | always @(posedge clk_WR) begin 67 | if(((WR == 1'b1) && (ifull == 1'b0))) begin 68 | //ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D; 69 | end 70 | end 71 | 72 | //Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0)))); 73 | //--------------------------------------- 74 | //--- Write address counter ------------- 75 | //--------------------------------------- 76 | assign add_WR_CE = (ifull == 1'b1) ? 1'b0 : (WR == 1'b0) ? 1'b0 : 1'b1; 77 | assign n_add_WR = (add_WR) + 4'h1; 78 | always @(posedge clk_WR, posedge rst) begin 79 | if((rst == 1'b1)) begin 80 | add_WR <= {5{1'b0}}; 81 | add_RD_WS <= 5'b11000; 82 | add_WR_GC <= {5{1'b0}}; 83 | end else begin 84 | add_RD_WS <= add_RD_GCwc; 85 | if((srst_w == 1'b1)) begin 86 | add_WR <= {5{1'b0}}; 87 | add_WR_GC <= {5{1'b0}}; 88 | end 89 | else if((add_WR_CE == 1'b1)) begin 90 | add_WR <= n_add_WR; 91 | add_WR_GC[0] <= n_add_WR[0] ^ n_add_WR[1]; 92 | add_WR_GC[1] <= n_add_WR[1] ^ n_add_WR[2]; 93 | add_WR_GC[2] <= n_add_WR[2] ^ n_add_WR[3]; 94 | add_WR_GC[3] <= n_add_WR[3] ^ n_add_WR[4]; 95 | add_WR_GC[4] <= n_add_WR[4]; 96 | end 97 | else begin 98 | add_WR <= add_WR; 99 | add_WR_GC <= add_WR_GC; 100 | end 101 | end 102 | end 103 | 104 | assign full = ifull; 105 | assign ifull = (iempty == 1'b1) ? 1'b0 : (add_RD_WS != add_WR_GC) ? 1'b0 : 1'b1; 106 | //--------------------------------------- 107 | //--- Read address counter -------------- 108 | //--------------------------------------- 109 | assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1; 110 | assign n_add_RD = (add_RD) + 4'h1; 111 | always @(posedge clk_RD, posedge rst) begin 112 | if((rst == 1'b1)) begin 113 | add_RD <= {5{1'b0}}; 114 | add_WR_RS <= {5{1'b0}}; 115 | add_RD_GC <= {5{1'b0}}; 116 | add_RD_GCwc <= 5'b11000; 117 | end else begin 118 | add_WR_RS <= add_WR_GC; 119 | if((srst_r == 1'b1)) begin 120 | add_RD <= {5{1'b0}}; 121 | add_RD_GC <= {5{1'b0}}; 122 | add_RD_GCwc <= 5'b11000; 123 | end 124 | else if((add_RD_CE == 1'b1)) begin 125 | add_RD <= n_add_RD; 126 | add_RD_GC[0] <= n_add_RD[0] ^ n_add_RD[1]; 127 | add_RD_GC[1] <= n_add_RD[1] ^ n_add_RD[2]; 128 | add_RD_GC[2] <= n_add_RD[2] ^ n_add_RD[3]; 129 | add_RD_GC[3] <= n_add_RD[3] ^ n_add_RD[4]; 130 | add_RD_GC[4] <= n_add_RD[4]; 131 | add_RD_GCwc[0] <= n_add_RD[0] ^ n_add_RD[1]; 132 | add_RD_GCwc[1] <= n_add_RD[1] ^ n_add_RD[2]; 133 | add_RD_GCwc[2] <= n_add_RD[2] ^ n_add_RD[3]; 134 | add_RD_GCwc[3] <= n_add_RD[3] ^ ( ~n_add_RD[4]); 135 | add_RD_GCwc[4] <= ~n_add_RD[4]; 136 | end 137 | else begin 138 | add_RD <= add_RD; 139 | add_RD_GC <= add_RD_GC; 140 | add_RD_GCwc <= add_RD_GCwc; 141 | end 142 | end 143 | end 144 | 145 | assign empty = iempty; 146 | assign iempty = (add_WR_RS == add_RD_GC) ? 1'b1 : 1'b0; 147 | //-------------------------------- 148 | //- sync rest stuff -------------- 149 | //- srst is sync with clk_WR ----- 150 | //- srst_r is sync with clk_RD --- 151 | //-------------------------------- 152 | always @(posedge clk_WR, posedge rst) begin 153 | if((rst == 1'b1)) begin 154 | srst_w <= 1'b0; 155 | isrst_r <= 1'b0; 156 | end else begin 157 | isrst_r <= srst_r; 158 | if((srst == 1'b1)) begin 159 | srst_w <= 1'b1; 160 | end 161 | else if((isrst_r == 1'b1)) begin 162 | srst_w <= 1'b0; 163 | end 164 | end 165 | end 166 | 167 | always @(posedge clk_RD, posedge rst) begin 168 | if((rst == 1'b1)) begin 169 | srst_r <= 1'b0; 170 | isrst_w <= 1'b0; 171 | end else begin 172 | isrst_w <= srst_w; 173 | if((isrst_w == 1'b1)) begin 174 | srst_r <= 1'b1; 175 | end 176 | else begin 177 | srst_r <= 1'b0; 178 | end 179 | end 180 | end 181 | 182 | 183 | endmodule 184 | -------------------------------------------------------------------------------- /translated_examples/forgen.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module forgen( 4 | input wire sysclk, 5 | input wire reset, 6 | input wire wrb, 7 | input wire [bus_width:0] din, 8 | output wire [bus_width:0] rdout 9 | ); 10 | 11 | parameter [31:0] bus_width=15; 12 | parameter [31:0] TOP_GP2=0; 13 | 14 | 15 | 16 | reg [bus_width * 2:0] regSelect; 17 | 18 | //--------------------------------------------------- 19 | // Reg : GP 2 20 | // Active : 32 21 | // Type : RW 22 | //--------------------------------------------------- 23 | genvar bitnum; 24 | generate for (bitnum=0; bitnum <= bus_width; bitnum = bitnum + 1) begin: reg_gp2 25 | wbit1 wbit1_inst( 26 | .clk(sysclk), 27 | .wrb(wrb), 28 | .reset(reset), 29 | .enb(regSelect[TOP_GP2]), 30 | .din(din[bitnum]), 31 | .dout(rdout[bitnum])); 32 | 33 | end 34 | endgenerate 35 | always @(posedge sysclk) begin 36 | regSelect[1] <= 1'b1; 37 | end 38 | 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /translated_examples/forloop.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module forloop( 4 | input wire reset, 5 | input wire sysclk 6 | ); 7 | 8 | 9 | 10 | 11 | reg selection; 12 | reg [6:0] egg_timer; 13 | 14 | always @(posedge reset, posedge sysclk) begin : P1 15 | reg [31:0] timer_var; 16 | reg [31:0] a, i, j, k; 17 | reg [31:0] zz5; 18 | reg [511:0] zz; 19 | 20 | if(reset == 1'b1) begin 21 | selection <= 1'b1; 22 | timer_var = 2; 23 | egg_timer <= {7{1'b0}}; 24 | end else begin 25 | // pulse only lasts for once cycle 26 | selection <= 1'b0; 27 | egg_timer <= {7{1'b1}}; 28 | for (i=0; i <= j * k; i = i + 1) begin 29 | a = a + i; 30 | for (k=a - 9; k >= -14; k = k - 1) begin 31 | zz5 = zz[31 + k -: 31 + 1]; 32 | end 33 | // k 34 | end 35 | // i 36 | end 37 | end 38 | 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /translated_examples/genericmap.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module genericmap( 4 | input wire clk, 5 | input wire rstn, 6 | input wire en, 7 | input wire start_dec, 8 | input wire [2:0] addr, 9 | input wire [25:0] din, 10 | input wire we, 11 | input wire [7:0] pixel_in, 12 | input wire pix_req, 13 | input wire bip, 14 | input wire [7:0] a, 15 | input wire [7:0] b, 16 | input wire [7:0] c, 17 | input wire [7:0] load, 18 | input wire [6:0] pack, 19 | input wire [2:0] base, 20 | input wire [21:0] qtd, 21 | output wire [25:0] dout, 22 | output wire [7:0] pixel_out, 23 | output wire pixel_valid, 24 | output wire [9:0] code, 25 | output wire [23:0] complex, 26 | output wire eno 27 | ); 28 | 29 | parameter rst_val=1'b0; 30 | parameter [31:0] thing_size=201 % 2; 31 | parameter [31:0] bus_width=201 % 32; 32 | // Outputs 33 | 34 | 35 | 36 | wire [7:0] param; 37 | wire selection; 38 | wire start; wire enf; // Start and enable signals 39 | wire [13:0] memdin; 40 | wire [5:0] memaddr; 41 | wire [13:0] memdout; 42 | wire [1:0] colour; 43 | 44 | dsp dsp_inst0( 45 | // Inputs 46 | .clk(clk), 47 | .rstn(rstn), 48 | .en(1'b1), 49 | .start(1'b0), 50 | .param(8'h42), 51 | .addr(3'b101), 52 | .din(24'b000100010001000100010001), 53 | .we(1'b0), 54 | // Outputs 55 | .dout(dout[23:0]), 56 | .memaddr(memaddr), 57 | .memdout(memdout)); 58 | 59 | dsp #( 60 | .rst_val(1'b1), 61 | .bus_width(16)) 62 | dsp_inst1( 63 | // Inputs 64 | .clk(clk), 65 | .rstn(rstn), 66 | .en(1'b1), 67 | .start(1'b0), 68 | .param(8'h42), 69 | .addr(3'b101), 70 | .din(16'b0001000100010001), 71 | .we(1'b0), 72 | // Outputs 73 | .dout(dout[15:0]), 74 | .memaddr(memaddr), 75 | .memdout(memdout)); 76 | 77 | signextend signextend_inst2( 78 | .i(16'b0000000000000000), 79 | .o(/* open */)); 80 | 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /translated_examples/ifchain.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module ifchain( 4 | input wire clk, 5 | input wire rstn 6 | ); 7 | 8 | 9 | 10 | 11 | 12 | wire [3:0] a; 13 | wire [3:0] b; 14 | reg status; 15 | reg [31:0] c[3:0]; 16 | 17 | always @(posedge clk) begin 18 | if({b[1],a[3:2]} == 3'b001) begin 19 | status <= 1'b1; 20 | c[0] <= 32'hFFFFFFFF; 21 | end 22 | end 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /translated_examples/ifchain2.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module ifchain2( 4 | input wire clk, 5 | input wire rstn, 6 | input wire enable, 7 | output reg result 8 | ); 9 | 10 | 11 | 12 | 13 | reg [3:0] counter; 14 | parameter CLK_DIV_VAL = 11; 15 | 16 | always @(posedge clk, posedge rstn) begin 17 | if((rstn == 1'b0)) begin 18 | counter <= {4{1'b0}}; 19 | result <= 1'b0; 20 | end else begin 21 | // Divide by 2 by default 22 | if((enable == 1'b1)) begin 23 | if((counter == 0)) begin 24 | counter <= CLK_DIV_VAL; 25 | result <= 1'b1; 26 | end 27 | else begin 28 | counter <= counter - 1; 29 | result <= 1'b0; 30 | end 31 | // counter 32 | end 33 | // enable 34 | end 35 | end 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /translated_examples/mem.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module mem( 4 | input wire clk, 5 | input wire rstn, 6 | input wire en, 7 | input wire cs, 8 | input wire [addr_width - 1:0] addr, 9 | input wire [bus_width - 1:0] din, 10 | output wire [bus_width - 1:0] dout 11 | ); 12 | 13 | parameter [31:0] addr_width=6; 14 | parameter [31:0] bus_width=14; 15 | // not implemented 16 | // not implemented 17 | 18 | 19 | 20 | reg [addr_width - 1:0] al = 8'h00; 21 | 22 | reg [bus_width - 1:0] mem[255:0]; 23 | 24 | assign dout = mem[al]; 25 | always @(posedge clk) begin 26 | al <= addr; 27 | if(en == 1'b1) begin 28 | mem[addr] <= din; 29 | end 30 | end 31 | 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /translated_examples/operators.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module operators( 4 | input wire clk_i 5 | ); 6 | 7 | parameter [1:0] g_and=2'b11 & 2'b10; 8 | parameter [1:0] g_or=2'b11 | 2'b10; 9 | parameter [1:0] g_nand= ~(2'b11 & 2'b10); 10 | parameter [1:0] g_nor= ~(2'b11 | 2'b10); 11 | parameter [1:0] g_xor=2'b11 ^ 2'b10; 12 | parameter [1:0] g_xnor= ~(2'b11 ^ 2'b10); 13 | parameter [1:0] g_not= ~2'b10; 14 | 15 | 16 | 17 | parameter c_and = 2'b11 & 2'b10; 18 | parameter c_or = 2'b11 | 2'b10; 19 | parameter c_nand = ~(2'b11 & 2'b10); 20 | parameter c_nor = ~(2'b11 | 2'b10); 21 | parameter c_xor = 2'b11 ^ 2'b10; 22 | parameter c_xnor = ~(2'b11 ^ 2'b10); 23 | parameter c_not = ~2'b10; 24 | wire [1:0] s_op1; 25 | wire [1:0] s_op2; 26 | reg [1:0] s_res; 27 | reg [31:0] s_int; 28 | reg [7:0] s_sig; 29 | reg [7:0] s_uns; 30 | 31 | always @(posedge clk_i) begin : P1 32 | reg [1:0] v_op1; 33 | reg [1:0] v_op2; 34 | reg [1:0] v_res; 35 | 36 | if((s_op1 == 2'b11 && s_op2 == 2'b00) || (s_op1 == 2'b11 || s_op2 == 2'b00) || (!(s_op1 == 2'b11 && s_op2 == 2'b00)) || (!(s_op1 == 2'b11 || s_op2 == 2'b00)) || (!(s_op1 == 2'b11))) begin 37 | s_res <= s_op1 & s_op2; 38 | s_res <= s_op1 | s_op2; 39 | v_res = ~(v_op1 & v_op2); 40 | v_res = ~(v_op1 | v_op2); 41 | s_res <= s_op1 ^ s_op2; 42 | v_res = ~(v_op1 ^ v_op2); 43 | s_res <= ~s_op1; 44 | s_int <= ( ( $signed(s_int) < 0 ) ? -$signed(s_int) : s_int ); 45 | s_sig <= ( ( $signed(s_sig) < 0 ) ? -$signed(s_sig) : s_sig ); 46 | s_sig <= s_sig << 2; 47 | s_sig <= s_sig >> (s_sig); 48 | s_uns <= s_uns << (s_uns); 49 | s_uns <= s_uns >> 9; 50 | s_sig <= s_sig << 2; 51 | s_sig <= s_sig >> (s_sig); 52 | // s_uns <= s_uns ror 3; -- Not yet implemented 53 | // s_uns <= s_uns rol to_integer(s_uns); -- Not yet implemented 54 | // s_uns <= rotate_right(s_uns,3); -- Not yet implemented 55 | // s_uns <= rotate_left(s_uns,to_integer(s_uns)); -- Not yet implemented 56 | s_sig <= s_sig % s_int; 57 | s_sig <= s_sig % s_int; 58 | end 59 | if(s_sig == (s_uns) || (s_sig) != s_uns || s_sig < 9'b101010101 || s_sig <= (s_uns) || (s_sig) > s_uns || s_sig >= 8'b00000101) begin 60 | s_sig <= s_sig + s_sig; 61 | s_sig <= s_sig - s_sig; 62 | s_sig <= s_sig * s_sig; 63 | s_sig <= s_sig / s_sig; 64 | s_sig <= {s_sig[7:4],2'b10,s_uns[1:0]}; 65 | s_int <= 2 ** 3; 66 | end 67 | end 68 | 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /translated_examples/partselect.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module partselect( 4 | input wire clk_i 5 | ); 6 | 7 | 8 | 9 | 10 | reg [31:0] big_sig; 11 | reg [0:31] lit_sig; 12 | wire [31:0] i = 8; 13 | 14 | always @(posedge clk_i) begin : P1 15 | reg [31:0] big_var; 16 | reg [0:31] lit_var; 17 | reg [31:0] j; 18 | 19 | big_sig[31:24] <= big_sig[7:0]; 20 | big_var[31:24] = big_var[7:0]; 21 | lit_sig[i * 3 +: 7 + 1] <= lit_sig[0:7]; 22 | lit_var[j * 3 +: 8 + 1] = lit_var[j * 0 +: 8 + 1]; 23 | // 24 | big_sig[i * 3 + 8 -: 8 + 1] <= big_sig[8:0]; 25 | big_var[j * 3 + 8 -: 8 + 1] = big_var[j * 0 + 8 -: 8 + 1]; 26 | end 27 | 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /translated_examples/signextend.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module signextend( 4 | input wire [15:0] i, 5 | output wire [31:0] o 6 | ); 7 | 8 | 9 | 10 | 11 | 12 | assign o[31:24] = {8{1'b0}}; 13 | assign o[23:16] = {8{i[15]}}; 14 | assign o[15:0] = i; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /translated_examples/test.v: -------------------------------------------------------------------------------- 1 | // Project: VHDL to Verilog RTL translation 2 | // Revision: 1.0 3 | // Date of last Revision: February 27 2001 4 | // Designer: Vincenzo Liguori 5 | // vhd2vl test file 6 | // This VHDL file exercises vhd2vl 7 | // no timescale needed 8 | 9 | module test( 10 | input wire clk, 11 | input wire rstn, 12 | input wire en, 13 | input wire start_dec, 14 | input wire [2:0] addr, 15 | input wire [25:0] din, 16 | input wire we, 17 | input wire [7:0] pixel_in, 18 | input wire pix_req, 19 | input wire config1, 20 | input wire bip, 21 | input wire [7:0] a, 22 | input wire [7:0] b, 23 | input wire [7:0] c, 24 | input wire [7:0] load, 25 | input wire [6:0] pack, 26 | input wire [2:0] base, 27 | input wire [21:0] qtd, 28 | output wire [23:0] dout, 29 | output reg [7:0] pixel_out, 30 | output wire pixel_valid, 31 | output reg [9:0] code, 32 | output wire [9:0] code1, 33 | output wire [23:0] complex, 34 | output wire eno 35 | ); 36 | 37 | // Inputs 38 | // Outputs 39 | 40 | 41 | 42 | // Components declarations are ignored by vhd2vl 43 | // but they are still parsed 44 | parameter [1:0] 45 | red = 0, 46 | green = 1, 47 | blue = 2, 48 | yellow = 3; 49 | 50 | reg [1:0] status; 51 | parameter PARAM1 = 8'b01101101; 52 | parameter PARAM2 = 8'b11001101; 53 | parameter PARAM3 = 8'b00010111; 54 | wire [7:0] param; 55 | reg selection = 1'b0; 56 | reg start; wire enf; // Start and enable signals 57 | wire [13:0] memdin; 58 | wire [5:0] memaddr; 59 | wire [13:0] memdout; 60 | reg [1:0] colour; 61 | 62 | assign param = config1 == 1'b1 ? PARAM1 : status == green ? PARAM2 : PARAM3; 63 | // Synchronously process 64 | always @(posedge clk) begin 65 | pixel_out <= pixel_in ^ 8'b11001100; 66 | end 67 | 68 | // Synchronous process 69 | always @(posedge clk) begin 70 | case(status) 71 | red : begin 72 | colour <= 2'b00; 73 | end 74 | green : begin 75 | colour <= 2'b01; 76 | end 77 | blue : begin 78 | colour <= 2'b10; 79 | end 80 | default : begin 81 | colour <= 2'b11; 82 | end 83 | endcase 84 | end 85 | 86 | // Synchronous process with asynch reset 87 | always @(posedge clk, posedge rstn) begin 88 | if(rstn == 1'b0) begin 89 | status <= red; 90 | end else begin 91 | case(status) 92 | red : begin 93 | if(pix_req == 1'b1) begin 94 | status <= green; 95 | end 96 | end 97 | green : begin 98 | if(a[3] == 1'b1) begin 99 | start <= start_dec; 100 | status <= blue; 101 | end 102 | else if(({b[5],a[3:2]}) == 3'b001) begin 103 | status <= yellow; 104 | end 105 | end 106 | blue : begin 107 | status <= yellow; 108 | end 109 | default : begin 110 | start <= 1'b0; 111 | status <= red; 112 | end 113 | endcase 114 | end 115 | end 116 | 117 | // Example of with statement 118 | always @(*) begin 119 | case(memaddr[2:0]) 120 | 3'b000,3'b110 : code[9:2] <= {3'b110,pack[6:2]}; 121 | 3'b101 : code[9:2] <= 8'b11100010; 122 | 3'b010 : code[9:2] <= {8{1'b1}}; 123 | 3'b011 : code[9:2] <= {8{1'b0}}; 124 | default : code[9:2] <= (a) + (b); 125 | endcase 126 | end 127 | 128 | assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); 129 | // Asynch process 130 | always @(we, addr, config1, bip) begin 131 | if(we == 1'b1) begin 132 | if(addr[2:0] == 3'b100) begin 133 | selection <= 1'b1; 134 | end 135 | else if(({b,a}) == {a,b} && bip == 1'b0) begin 136 | selection <= config1; 137 | end 138 | else begin 139 | selection <= 1'b1; 140 | end 141 | end 142 | else begin 143 | selection <= 1'b0; 144 | end 145 | end 146 | 147 | // Components instantiation 148 | dsp dsp_inst( 149 | // Inputs 150 | .clk(clk), 151 | .rstn(rstn), 152 | .en(en), 153 | .start(start), 154 | .param(param), 155 | .addr(addr), 156 | .din(din[23:0]), 157 | .we(we), 158 | .memdin(memdin), 159 | // Outputs 160 | .dout(dout), 161 | .memaddr(memaddr), 162 | .memdout(memdout)); 163 | 164 | mem dsp_mem( 165 | // Inputs 166 | .clk(clk), 167 | .rstn(rstn), 168 | .en(en), 169 | .cs(selection), 170 | .addr(memaddr), 171 | .din(memdout), 172 | // Outputs 173 | .dout(memdin)); 174 | 175 | assign complex = {enf,3'b110 * (load),qtd[3:0],base,5'b11001}; 176 | assign enf = c < 7'b1000111 ? 1'b1 : 1'b0; 177 | assign eno = enf; 178 | 179 | endmodule 180 | -------------------------------------------------------------------------------- /translated_examples/wbit1.v: -------------------------------------------------------------------------------- 1 | // Nearly useless stub, it's here to support generate.vhd 2 | // no timescale needed 3 | 4 | module wbit1( 5 | input wire clk, 6 | input wire wrb, 7 | input wire reset, 8 | input wire enb, 9 | input wire din, 10 | output reg dout 11 | ); 12 | 13 | 14 | 15 | 16 | wire foo; 17 | 18 | always @(clk) begin 19 | dout <= 1'b1; 20 | end 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /translated_examples/whileloop.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module whileloop( 4 | input wire [31:0] A, 5 | output reg [3:0] Z 6 | ); 7 | 8 | 9 | 10 | 11 | 12 | always @(A) begin : P1 13 | reg [31:0] I; 14 | 15 | Z <= 4'b0000; 16 | I = 0; 17 | while ((I <= 3)) begin 18 | if((A == I)) begin 19 | Z[I] <= 1'b1; 20 | end 21 | I = I + 1; 22 | end 23 | end 24 | 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /translated_examples/withselect.v: -------------------------------------------------------------------------------- 1 | // no timescale needed 2 | 3 | module withselect( 4 | input wire reset, 5 | input wire sysclk, 6 | input wire [bus_width:0] a, 7 | input wire [bus_width:0] b, 8 | input wire [bus_width:0] enf, 9 | input wire [bus_width:0] load, 10 | input wire [bus_width:0] qtd, 11 | input wire [bus_width:0] base 12 | ); 13 | 14 | parameter [7:0] dog_width=8'b10101100; 15 | parameter [31:0] bus_width=32; 16 | 17 | 18 | 19 | wire [1 + 1:0] foo; 20 | reg [9:0] code; wire [9:0] code1; 21 | wire [324:401] egg; 22 | wire [bus_width * 3 - 1:bus_width * 4] baz; 23 | wire [31:0] complex; 24 | 25 | // Example of with statement 26 | always @(*) begin 27 | case(foo[2:0]) 28 | 3'b000,3'b110 : code[9:2] <= {3'b110,egg[325:329]}; 29 | 3'b101 : code[9:2] <= 8'b11100010; 30 | 3'b010 : code[9:2] <= {8{1'b1}}; 31 | 3'b011 : code[9:2] <= {8{1'b0}}; 32 | default : code[9:2] <= (a) + (b); 33 | endcase 34 | end 35 | 36 | assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); 37 | assign foo = {((1 + 1)-(0)+1){1'b0}}; 38 | assign egg = {78{1'b0}}; 39 | assign baz = {((bus_width * 4)-(bus_width * 3 - 1)+1){1'b1}}; 40 | assign complex = {enf,3'b110 * (load),qtd[3:0],base,5'b11001}; 41 | 42 | endmodule 43 | --------------------------------------------------------------------------------