├── img ├── 1_top.jpg ├── 2_top_mask.jpg ├── 3_top_replaced.jpg ├── 4_bottom_mask.jpg ├── 5_bottom-lifted.jpg ├── 6_bottom_replaced.jpg └── IMG_20141101_142704.jpg ├── patches ├── vmalloc_size.patch └── 4gb_dma_zone.patch ├── README.md └── PM375_Hynix_4GB_H5TC8G63AMR_PBA_792MHz.cfg /img/1_top.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/1_top.jpg -------------------------------------------------------------------------------- /img/2_top_mask.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/2_top_mask.jpg -------------------------------------------------------------------------------- /img/3_top_replaced.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/3_top_replaced.jpg -------------------------------------------------------------------------------- /img/4_bottom_mask.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/4_bottom_mask.jpg -------------------------------------------------------------------------------- /img/5_bottom-lifted.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/5_bottom-lifted.jpg -------------------------------------------------------------------------------- /img/6_bottom_replaced.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/6_bottom_replaced.jpg -------------------------------------------------------------------------------- /img/IMG_20141101_142704.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/jetson_hw_hacking/HEAD/img/IMG_20141101_142704.jpg -------------------------------------------------------------------------------- /patches/vmalloc_size.patch: -------------------------------------------------------------------------------- 1 | --- a/arch/arm/mm/mmu.c 2 | +++ b/arch/arm/mm/mmu.c 3 | @@ -988,7 +988,7 @@ 4 | #endif 5 | 6 | static void * __initdata vmalloc_min = 7 | - (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 8 | + (void *)(VMALLOC_END - (300 << 20) - VMALLOC_OFFSET); 9 | 10 | /* 11 | * vmalloc=size forces the vmalloc area to be exactly 'size' 12 | 13 | -------------------------------------------------------------------------------- /patches/4gb_dma_zone.patch: -------------------------------------------------------------------------------- 1 | --- a/arch/arm/mach-tegra/board-ardbeg.c 2 | +++ b/arch/arm/mach-tegra/board-ardbeg.c 3 | @@ -1517,6 +1517,9 @@ 4 | MACHINE_END 5 | 6 | DT_MACHINE_START(JETSON_TK1, "jetson-tk1") 7 | +#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) 8 | + .dma_zone_size = (4UL * SZ_1G), 9 | +#endif 10 | .atag_offset = 0x100, 11 | .smp = smp_ops(tegra_smp_ops), 12 | .map_io = tegra_map_common_io, 13 | 14 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Jetson TK1 4GB DRAM upgrade 2 | =========================== 3 | 4 | Hardware 5 | -------- 6 | 7 | Jetson TK1 ships with four [H5TC4G63AFR-RDA](https://www.skhynix.com/products/computing/view.jsp?info.ramKind=19&info.serialNo=H5TC4G63AFR) 256Mb x 16 DDR3L ICs. These can be replaced with 512Mb x 16 DDR3L ICs for a total capacity of 4GB. The replacements I've used are [H5TC8G63AMR-PBA](https://www.skhynix.com/products/computing/view.jsp?info.ramKind=19&info.serialNo=H5TC8G63AMR). 8 | 9 | 10 | **Requirements:** 11 | * BGA rework capabilities - outside the scope of this document 12 | * 8Gb replacement ICs - these are quite difficult to find, I got mine on Aliexpress (listing no longer available) 13 | * replacement thermal paste because the heatsink must be removed while reworking the board 14 | * a host computer with the [Jetson driver package](https://developer.nvidia.com/jetson-tk1-support) for setting up the Jetson board 15 | * the [L4T kernel source](https://developer.nvidia.com/jetson-tk1-support) 16 | 17 | 18 | I recommend replacing one IC at a time and testing that everything works correctly in between. This makes it possible to catch any soldering issues. A mix of H5TC4G63AFR and H5TC8G63AMR seems to work correctly with the default SDRAM configuration, but only 2 GB of memory are available. 19 | 20 | ![Kapton tape mask on the bottom](img/4_bottom_mask.jpg) 21 | 22 | ![DDR chips lifted](img/5_bottom-lifted.jpg) 23 | 24 | ![Replaced DDR chips](img/6_bottom_replaced.jpg) 25 | 26 | Software configuration 27 | ---------------------- 28 | 29 | The default kernel configuration doesn't allow use of more than 2GB of RAM. The following options must be enabled: 30 | * System Type > Full 4GB physical memory support 31 | * System Type > Support for the Large Physical Address Extension 32 | 33 | A patch is required to [limit the range of memory used for DMA buffers to the first 4GB of physical memory](patches/4gb_dma_zone.patch). 34 | 35 | The default vmalloc size might need to be increased, either by passing a kernel argument (e.g. `vmalloc=300M`) or by applying another patch to [increase the default size](patches/vmalloc_size.patch). 36 | 37 | The updated kernel image can be flashed by replacing `Linux_for_Tegra/kernel/zImage` and running: 38 | 39 | ``` 40 | sudo ./flash.sh -k 6 jetson-tk1 mmcblk0p1 41 | ``` 42 | 43 | Finally, access to the full 4GB of RAM is enabled by writing a new BCT file with the updated SDRAM configuration: 44 | 45 | ``` 46 | sudo nvflash --bct PM375_Hynix_4GB_H5TC8G63AMR_PBA_792MHz.cfg --updatebct SDRAM --bl ./fastboot.bin --go 47 | ``` 48 | 49 | This configuration was derived from the E1780_Hynix_4GB_H5TC8G63AMR_PBA_792Mhz.cfg and PM375_Hynix_2GB_H5TC4G63AFR_RDA_792MHz.cfg files provided by NVIDIA. This configuration works for me, but it might not be stable on other units. 50 | 51 | The bootloader should then automatically pass similar parameters to the kernel: 52 | 53 | mem=1862M@2048M mem=2048M@4096M ddr_die=2048M@2048M ddr_die=2048M@4096M 54 | 55 | License 56 | ------- 57 | 58 | This document is licensed under a [Creative Commons Attribution-ShareAlike 4.0 International License](http://creativecommons.org/licenses/by-sa/4.0/). 59 | -------------------------------------------------------------------------------- /PM375_Hynix_4GB_H5TC8G63AMR_PBA_792MHz.cfg: -------------------------------------------------------------------------------- 1 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; 2 | SDRAM[0].PllMInputDivider = 0x00000001; 3 | SDRAM[0].PllMFeedbackDivider = 0x00000042; 4 | SDRAM[0].PllMStableTime = 0x0000012c; 5 | SDRAM[0].PllMSetupControl = 0x00000000; 6 | SDRAM[0].PllMSelectDiv2 = 0x00000000; 7 | SDRAM[0].PllMPDLshiftPh45 = 0x00000001; 8 | SDRAM[0].PllMPDLshiftPh90 = 0x00000001; 9 | SDRAM[0].PllMPDLshiftPh135 = 0x00000001; 10 | SDRAM[0].PllMKCP = 0x00000000; 11 | SDRAM[0].PllMKVCO = 0x00000000; 12 | SDRAM[0].EmcBctSpare0 = 0x00000000; 13 | SDRAM[0].EmcBctSpare1 = 0x00000000; 14 | SDRAM[0].EmcBctSpare2 = 0x00000000; 15 | SDRAM[0].EmcBctSpare3 = 0x00000000; 16 | SDRAM[0].EmcBctSpare4 = 0x00000000; 17 | SDRAM[0].EmcBctSpare5 = 0x00000000; 18 | SDRAM[0].EmcBctSpare6 = 0x00000000; 19 | SDRAM[0].EmcBctSpare7 = 0x00000000; 20 | SDRAM[0].EmcBctSpare8 = 0x00000000; 21 | SDRAM[0].EmcBctSpare9 = 0x00000000; 22 | SDRAM[0].EmcBctSpare10 = 0x00000000; 23 | SDRAM[0].EmcBctSpare11 = 0x00000000; 24 | SDRAM[0].EmcClockSource = 0x80000000; 25 | SDRAM[0].EmcAutoCalInterval = 0x001fffff; 26 | SDRAM[0].EmcAutoCalConfig = 0xa1430404; 27 | SDRAM[0].EmcAutoCalConfig2 = 0x00000000; 28 | SDRAM[0].EmcAutoCalConfig3 = 0x00000000; 29 | SDRAM[0].EmcAutoCalWait = 0x00000190; 30 | SDRAM[0].EmcAdrCfg = 0x00000001; 31 | SDRAM[0].EmcPinProgramWait = 0x00000001; 32 | SDRAM[0].EmcPinExtraWait = 0x00000000; 33 | SDRAM[0].EmcTimingControlWait = 0x00000000; 34 | SDRAM[0].EmcRc = 0x00000025; 35 | SDRAM[0].EmcRfc = 0x00000114; 36 | SDRAM[0].EmcRfcSlr = 0x00000000; 37 | SDRAM[0].EmcRas = 0x00000019; 38 | SDRAM[0].EmcRp = 0x0000000a; 39 | SDRAM[0].EmcR2r = 0x00000000; 40 | SDRAM[0].EmcW2w = 0x00000000; 41 | SDRAM[0].EmcR2w = 0x00000007; 42 | SDRAM[0].EmcW2r = 0x0000000d; 43 | SDRAM[0].EmcR2p = 0x00000004; 44 | SDRAM[0].EmcW2p = 0x00000013; 45 | SDRAM[0].EmcRdRcd = 0x0000000a; 46 | SDRAM[0].EmcWrRcd = 0x0000000a; 47 | SDRAM[0].EmcRrd = 0x00000003; 48 | SDRAM[0].EmcRext = 0x00000002; 49 | SDRAM[0].EmcWext = 0x00000000; 50 | SDRAM[0].EmcWdv = 0x00000006; 51 | SDRAM[0].EmcWdvMask = 0x00000006; 52 | SDRAM[0].EmcQUse = 0x0000000b; 53 | SDRAM[0].EmcQuseWidth = 0x00000002; 54 | SDRAM[0].EmcIbdly = 0x00000000; 55 | SDRAM[0].EmcEInput = 0x00000003; 56 | SDRAM[0].EmcEInputDuration = 0x0000000c; 57 | SDRAM[0].EmcPutermExtra = 0x00090000; 58 | SDRAM[0].EmcPutermWidth = 0x00000004; 59 | SDRAM[0].EmcPutermAdj = 0x00000000; 60 | SDRAM[0].EmcCdbCntl1 = 0x00000000; 61 | SDRAM[0].EmcCdbCntl2 = 0x00000000; 62 | SDRAM[0].EmcCdbCntl3 = 0x00000000; 63 | SDRAM[0].EmcQRst = 0x00000002; 64 | SDRAM[0].EmcQSafe = 0x00000013; 65 | SDRAM[0].EmcRdv = 0x00000017; 66 | SDRAM[0].EmcRdvMask = 0x00000019; 67 | SDRAM[0].EmcQpop = 0x0000000f; 68 | SDRAM[0].EmcCtt = 0x00000000; 69 | SDRAM[0].EmcCttDuration = 0x00000004; 70 | SDRAM[0].EmcRefresh = 0x000017eb; 71 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 72 | SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa; 73 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 74 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 75 | SDRAM[0].EmcPChg2Pden = 0x00000001; 76 | SDRAM[0].EmcAct2Pden = 0x00000000; 77 | SDRAM[0].EmcAr2Pden = 0x0000010d; 78 | SDRAM[0].EmcRw2Pden = 0x00000018; 79 | SDRAM[0].EmcTxsr = 0x0000011e; 80 | SDRAM[0].EmcTxsrDll = 0x00000200; 81 | SDRAM[0].EmcTcke = 0x00000005; 82 | SDRAM[0].EmcTckesr = 0x00000006; 83 | SDRAM[0].EmcTpd = 0x00000005; 84 | SDRAM[0].EmcTfaw = 0x0000001d; 85 | SDRAM[0].EmcTrpab = 0x00000000; 86 | SDRAM[0].EmcTClkStable = 0x00000008; 87 | SDRAM[0].EmcTClkStop = 0x00000008; 88 | SDRAM[0].EmcTRefBw = 0x0000182c; 89 | SDRAM[0].EmcFbioCfg5 = 0x104ab898; 90 | SDRAM[0].EmcFbioCfg6 = 0x00000004; 91 | SDRAM[0].EmcFbioSpare = 0x00000000; 92 | SDRAM[0].EmcCfgRsv = 0xff00ff00; 93 | SDRAM[0].EmcMrs = 0x00001d71; 94 | SDRAM[0].EmcEmrs = 0x00100002; 95 | SDRAM[0].EmcEmrs2 = 0x00200018; 96 | SDRAM[0].EmcEmrs3 = 0x00300000; 97 | SDRAM[0].EmcMrw1 = 0x00000000; 98 | SDRAM[0].EmcMrw2 = 0x00000000; 99 | SDRAM[0].EmcMrw3 = 0x00000000; 100 | SDRAM[0].EmcMrw4 = 0x00000000; 101 | SDRAM[0].EmcMrwExtra = 0x00000000; 102 | SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; 103 | SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; 104 | SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; 105 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 106 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 107 | SDRAM[0].EmcMrsWaitCnt = 0x006f000e; 108 | SDRAM[0].EmcMrsWaitCnt2 = 0x006f000e; 109 | SDRAM[0].EmcCfg = 0x73300000; 110 | SDRAM[0].EmcCfg2 = 0x0000089d; 111 | SDRAM[0].EmcCfgPipe = 0x000040a0; 112 | SDRAM[0].EmcDbg = 0x01000c00; 113 | SDRAM[0].EmcCmdQ = 0x10004408; 114 | SDRAM[0].EmcMc2EmcQ = 0x06000404; 115 | SDRAM[0].EmcDynSelfRefControl = 0x80003025; 116 | SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; 117 | SDRAM[0].EmcCfgDigDll = 0xe00701b1; 118 | SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; 119 | SDRAM[0].EmcDevSelect = 0x00000000; 120 | SDRAM[0].EmcSelDpdCtrl = 0x00040000; 121 | SDRAM[0].EmcDllXformDqs0 = 0x00000004; 122 | SDRAM[0].EmcDllXformDqs1 = 0x00000004; 123 | SDRAM[0].EmcDllXformDqs2 = 0x00000004; 124 | SDRAM[0].EmcDllXformDqs3 = 0x00000004; 125 | SDRAM[0].EmcDllXformDqs4 = 0x00000004; 126 | SDRAM[0].EmcDllXformDqs5 = 0x00000004; 127 | SDRAM[0].EmcDllXformDqs6 = 0x00000004; 128 | SDRAM[0].EmcDllXformDqs7 = 0x00000004; 129 | SDRAM[0].EmcDllXformDqs8 = 0x00000004; 130 | SDRAM[0].EmcDllXformDqs9 = 0x00000004; 131 | SDRAM[0].EmcDllXformDqs10 = 0x00000004; 132 | SDRAM[0].EmcDllXformDqs11 = 0x00000004; 133 | SDRAM[0].EmcDllXformDqs12 = 0x00000004; 134 | SDRAM[0].EmcDllXformDqs13 = 0x00000004; 135 | SDRAM[0].EmcDllXformDqs14 = 0x00000004; 136 | SDRAM[0].EmcDllXformDqs15 = 0x00000004; 137 | SDRAM[0].EmcDllXformQUse0 = 0x00000000; 138 | SDRAM[0].EmcDllXformQUse1 = 0x00000000; 139 | SDRAM[0].EmcDllXformQUse2 = 0x00000000; 140 | SDRAM[0].EmcDllXformQUse3 = 0x00000000; 141 | SDRAM[0].EmcDllXformQUse4 = 0x00000000; 142 | SDRAM[0].EmcDllXformQUse5 = 0x00000000; 143 | SDRAM[0].EmcDllXformQUse6 = 0x00000000; 144 | SDRAM[0].EmcDllXformQUse7 = 0x00000000; 145 | SDRAM[0].EmcDllXformAddr0 = 0x00034000; 146 | SDRAM[0].EmcDllXformAddr1 = 0x00034000; 147 | SDRAM[0].EmcDllXformAddr2 = 0x00000000; 148 | SDRAM[0].EmcDllXformAddr3 = 0x00034000; 149 | SDRAM[0].EmcDllXformAddr4 = 0x00034000; 150 | SDRAM[0].EmcDllXformAddr5 = 0x00000000; 151 | SDRAM[0].EmcDllXformQUse8 = 0x00000000; 152 | SDRAM[0].EmcDllXformQUse9 = 0x00000000; 153 | SDRAM[0].EmcDllXformQUse10 = 0x00000000; 154 | SDRAM[0].EmcDllXformQUse11 = 0x00000000; 155 | SDRAM[0].EmcDllXformQUse12 = 0x00000000; 156 | SDRAM[0].EmcDllXformQUse13 = 0x00000000; 157 | SDRAM[0].EmcDllXformQUse14 = 0x00000000; 158 | SDRAM[0].EmcDllXformQUse15 = 0x00000000; 159 | SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; 160 | SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; 161 | SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; 162 | SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; 163 | SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; 164 | SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; 165 | SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; 166 | SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; 167 | SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; 168 | SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; 169 | SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; 170 | SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; 171 | SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; 172 | SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; 173 | SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; 174 | SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; 175 | SDRAM[0].EmcDllXformDq0 = 0x0000000b; 176 | SDRAM[0].EmcDllXformDq1 = 0x0000000b; 177 | SDRAM[0].EmcDllXformDq2 = 0x0000000b; 178 | SDRAM[0].EmcDllXformDq3 = 0x0000000b; 179 | SDRAM[0].EmcDllXformDq4 = 0x0000000b; 180 | SDRAM[0].EmcDllXformDq5 = 0x0000000b; 181 | SDRAM[0].EmcDllXformDq6 = 0x0000000b; 182 | SDRAM[0].EmcDllXformDq7 = 0x0000000b; 183 | SDRAM[0].WarmBootWait = 0x00000002; 184 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 185 | SDRAM[0].EmcOdtWrite = 0x00000000; 186 | SDRAM[0].EmcOdtRead = 0x00000000; 187 | SDRAM[0].EmcZcalInterval = 0x00020000; 188 | SDRAM[0].EmcZcalWaitCnt = 0x00000042; 189 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 190 | SDRAM[0].EmcMrsResetDll = 0x00000000; 191 | SDRAM[0].EmcZcalInitDev0 = 0x80000011; 192 | SDRAM[0].EmcZcalInitDev1 = 0x40000011; 193 | SDRAM[0].EmcZcalInitWait = 0x00000001; 194 | SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; 195 | SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; 196 | SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; 197 | SDRAM[0].EmcZcalWarmBootWait = 0x00000001; 198 | SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; 199 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 200 | SDRAM[0].EmcMrsExtra = 0x00000d71; 201 | SDRAM[0].EmcWarmBootMrsExtra = 0x00100002; 202 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; 203 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; 204 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; 205 | SDRAM[0].EmcDdr2Wait = 0x00000000; 206 | SDRAM[0].EmcClkenOverride = 0x00000000; 207 | SDRAM[0].McDisExtraSnapLevels = 0x00000000; 208 | SDRAM[0].EmcExtraRefreshNum = 0x00000002; 209 | SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; 210 | SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; 211 | SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; 212 | SDRAM[0].PmcVddpSel = 0x00000002; 213 | SDRAM[0].PmcVddpSelWait = 0x00000002; 214 | SDRAM[0].PmcDdrPwr = 0x00000003; 215 | SDRAM[0].PmcDdrCfg = 0x00002002; 216 | SDRAM[0].PmcIoDpd3Req = 0x4fffffff; 217 | SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; 218 | SDRAM[0].PmcRegShort = 0x00000000; 219 | SDRAM[0].PmcNoIoPower = 0x00000000; 220 | SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; 221 | SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; 222 | SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; 223 | SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; 224 | SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; 225 | SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; 226 | SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; 227 | SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; 228 | SDRAM[0].EmcXm2DqsPadCtrl3 = 0x69a69a20; 229 | SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; 230 | SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; 231 | SDRAM[0].EmcXm2DqsPadCtrl6 = 0x69a69a00; 232 | SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; 233 | SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; 234 | SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; 235 | SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; 236 | SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000505; 237 | SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; 238 | SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; 239 | SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; 240 | SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff; 241 | SDRAM[0].EmcAcpdControl = 0x00000000; 242 | SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; 243 | SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; 244 | SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; 245 | SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; 246 | SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; 247 | SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; 248 | SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; 249 | SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; 250 | SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; 251 | SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; 252 | SDRAM[0].EmcDsrVttgenDrv = 0x0505003f; 253 | SDRAM[0].EmcTxdsrvttgen = 0x00000000; 254 | SDRAM[0].EmcBgbiasCtl0 = 0x00000000; 255 | SDRAM[0].McEmemAdrCfg = 0x00000001; 256 | SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; 257 | SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; 258 | SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; 259 | SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; 260 | SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; 261 | SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; 262 | SDRAM[0].McEmemCfg = 0x00001000; 263 | SDRAM[0].McEmemArbCfg = 0x0e00000b; 264 | SDRAM[0].McEmemArbOutstandingReq = 0x80000040; 265 | SDRAM[0].McEmemArbTimingRcd = 0x00000004; 266 | SDRAM[0].McEmemArbTimingRp = 0x00000005; 267 | SDRAM[0].McEmemArbTimingRc = 0x00000013; 268 | SDRAM[0].McEmemArbTimingRas = 0x0000000c; 269 | SDRAM[0].McEmemArbTimingFaw = 0x0000000f; 270 | SDRAM[0].McEmemArbTimingRrd = 0x00000002; 271 | SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; 272 | SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; 273 | SDRAM[0].McEmemArbTimingR2R = 0x00000002; 274 | SDRAM[0].McEmemArbTimingW2W = 0x00000002; 275 | SDRAM[0].McEmemArbTimingR2W = 0x00000005; 276 | SDRAM[0].McEmemArbTimingW2R = 0x00000008; 277 | SDRAM[0].McEmemArbDaTurns = 0x08050202; 278 | SDRAM[0].McEmemArbDaCovers = 0x00170e13; 279 | SDRAM[0].McEmemArbMisc0 = 0x746c2414; 280 | SDRAM[0].McEmemArbMisc1 = 0x70000f02; 281 | SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; 282 | SDRAM[0].McEmemArbOverride = 0x10000000; 283 | SDRAM[0].McEmemArbOverride1 = 0x00000000; 284 | SDRAM[0].McEmemArbRsv = 0xff00ff00; 285 | SDRAM[0].McClkenOverride = 0x00000000; 286 | SDRAM[0].McStatControl = 0x00000000; 287 | SDRAM[0].McDisplaySnapRing = 0x00000003; 288 | SDRAM[0].McVideoProtectBom = 0xfff00000; 289 | SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; 290 | SDRAM[0].McVideoProtectSizeMb = 0x00000000; 291 | SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; 292 | SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; 293 | SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; 294 | SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; 295 | SDRAM[0].McSecCarveoutBom = 0xfff00000; 296 | SDRAM[0].McSecCarveoutAdrHi = 0x00000000; 297 | SDRAM[0].McSecCarveoutSizeMb = 0x00000000; 298 | SDRAM[0].McVideoProtectWriteAccess = 0x00000000; 299 | SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; 300 | SDRAM[0].EmcCaTrainingEnable = 0x00000000; 301 | SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; 302 | SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; 303 | SDRAM[0].SwizzleRankByteEncode = 0x0000006f; 304 | SDRAM[0].BootRomPatchControl = 0x00000000; 305 | SDRAM[0].BootRomPatchData = 0x00000000; 306 | SDRAM[0].McMtsCarveoutBom = 0xfff00000; 307 | SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; 308 | SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; 309 | SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; 310 | #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013; 311 | #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c; 312 | #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038; 313 | #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038; 314 | #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c; 315 | #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090; 316 | #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041; 317 | #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090; 318 | #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041; 319 | #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; 320 | #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080; 321 | #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004; 322 | #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004; 323 | #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; 324 | #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081; 325 | #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004; 326 | #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019; 327 | #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018; 328 | #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024; 329 | #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c; 330 | #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081; 331 | #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; 332 | #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081; 333 | #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; 334 | #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081; 335 | #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; 336 | #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; 337 | #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081; 338 | #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081; 339 | #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065; 340 | #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c; 341 | --------------------------------------------------------------------------------