├── bench ├── sysc │ ├── include │ │ ├── DebugUnitSC.h │ │ ├── GdbServerSC.h │ │ ├── JtagDriverSC.h │ │ ├── JtagSC.h │ │ ├── JtagSC_includes.h │ │ ├── MemCache.h │ │ ├── MemoryLoad.h │ │ ├── MpHash.h │ │ ├── Or1200MonitorSC.h │ │ ├── OrpsocAccess.h │ │ ├── OrpsocMain.h │ │ ├── ResetSC.h │ │ ├── RspConnection.h │ │ ├── RspPacket.h │ │ ├── SprCache.h │ │ ├── TapAction.h │ │ ├── TapActionDRScan.h │ │ ├── TapActionIRScan.h │ │ ├── TapActionReset.h │ │ ├── TapStateMachine.h │ │ ├── TraceSC.h │ │ ├── UartSC.h │ │ ├── Utils.h │ │ ├── coff.h │ │ └── elf.h │ └── src │ │ ├── DebugUnitSC.cpp │ │ ├── GdbServerSC.cpp │ │ ├── JtagDriverSC.cpp │ │ ├── JtagSC.cpp │ │ ├── MemCache.cpp │ │ ├── MemoryLoad.cpp │ │ ├── Modules.make │ │ ├── MpHash.cpp │ │ ├── Or1200MonitorSC.cpp │ │ ├── OrpsocAccess.cpp │ │ ├── OrpsocMain.cpp │ │ ├── ResetSC.cpp │ │ ├── RspConnection.cpp │ │ ├── RspPacket.cpp │ │ ├── SprCache.cpp │ │ ├── TapAction.cpp │ │ ├── TapActionDRScan.cpp │ │ ├── TapActionIRScan.cpp │ │ ├── TapActionReset.cpp │ │ ├── TapStateMachine.cpp │ │ ├── TraceSC.cpp │ │ ├── UartSC.cpp │ │ └── Utils.cpp └── verilog │ ├── AT26DFxxx.v │ ├── eth_phy.v │ ├── include │ ├── cfi_flash_BankLib.h │ ├── cfi_flash_CUIcommandData.h │ ├── cfi_flash_TimingData.h │ ├── cfi_flash_UserData.h │ ├── cfi_flash_data.h │ ├── cfi_flash_def.h │ ├── eth_phy_defines.v │ ├── or1200_monitor_defines.v │ ├── orpsoc-testbench-defines.v │ └── timescale.v │ ├── mt48lc16m16a2.v │ ├── or1200_monitor.v │ ├── orpsoc_testbench.v │ ├── smii_phy.v │ ├── uart_decoder.v │ ├── uart_stim.v │ ├── usbhostslave │ ├── HCTxPortArbiter_simlib.v │ ├── RxFifo_simlib.v │ ├── RxfifoBI_simlib.v │ ├── SCTxPortArbiter_simlib.v │ ├── SIEReceiver_simlib.v │ ├── SIETransmitter_simlib.v │ ├── SOFController_simlib.v │ ├── SOFTransmit_simlib.v │ ├── TxFifo_simlib.v │ ├── TxfifoBI_simlib.v │ ├── USBHostControlBI_simlib.v │ ├── USBSlaveControlBI_simlib.v │ ├── USBTxWireArbiter_simlib.v │ ├── directControl_simlib.v │ ├── dpMem_dc_simlib.v │ ├── endpMux_simlib.v │ ├── fifoMux_simlib.v │ ├── fifoRTL_simlib.v │ ├── getPacket_simlib.v │ ├── hostSlaveMuxBI_simlib.v │ ├── hostSlaveMux_simlib.v │ ├── hostcontroller_simlib.v │ ├── lineControlUpdate_simlib.v │ ├── processRxBit_simlib.v │ ├── processRxByte_simlib.v │ ├── processTxByte_simlib.v │ ├── readUSBWireData_simlib.v │ ├── rxStatusMonitor_simlib.v │ ├── sendPacketArbiter_simlib.v │ ├── sendPacketCheckPreamble_simlib.v │ ├── sendPacket_simlib.v │ ├── slaveDirectControl_simlib.v │ ├── slaveGetPacket_simlib.v │ ├── slaveRxStatusMonitor_simlib.v │ ├── slaveSendPacket_simlib.v │ ├── slavecontroller_simlib.v │ ├── speedCtrlMux_simlib.v │ ├── updateCRC16_simlib.v │ ├── updateCRC5_simlib.v │ ├── usbConstants_h.v │ ├── usbHostControl_h.v │ ├── usbHostControl_simlib.v │ ├── usbHostSlave_h.v │ ├── usbSerialInterfaceEngine_h.v │ ├── usbSerialInterfaceEngine_simlib.v │ ├── usbSlaveControl_h.v │ ├── usbSlaveControl_simlib.v │ ├── usb_hostslave_tb.v │ ├── usb_slave_tb.v │ ├── usbhost_simlib.v │ ├── usbhostslave_simlib.v │ ├── usbslave_simlib.v │ ├── wb_master_model.v │ ├── wishBoneBI_simlib.v │ ├── wishBoneBus_h.v │ └── writeUSBWireData_simlib.v │ ├── vpi │ ├── c │ │ ├── Makefile │ │ ├── gdb.c │ │ ├── gdb.h │ │ ├── jp_vpi.c │ │ ├── rsp-rtl_sim.c │ │ ├── rsp-rtl_sim.h │ │ └── rsp-vpi.h │ └── verilog │ │ ├── vpi_debug_defines.v │ │ └── vpi_debug_module.v │ ├── wiredelay.v │ └── x28fxxxp30.v ├── boards ├── README ├── actel │ ├── backend │ │ └── rtl │ │ │ └── verilog │ │ │ └── proasic3.v │ └── ordb1a3pe1500 │ │ ├── Makefile.inc │ │ ├── backend │ │ ├── par │ │ │ ├── README │ │ │ ├── bin │ │ │ │ ├── Makefile │ │ │ │ ├── orsoccpuboard.mkpins │ │ │ │ ├── orsoccpuexpio.mkpinassigns │ │ │ │ └── orsocexpboard.mkpins │ │ │ └── run │ │ │ │ └── Makefile │ │ └── rtl │ │ │ └── verilog │ │ │ ├── README │ │ │ ├── eth_pll.v │ │ │ ├── gbuf.v │ │ │ ├── orpsoc_flashROM.v │ │ │ ├── pll_xtal25_wb20.v │ │ │ ├── pll_xtal25_wb24.v │ │ │ ├── pll_xtal64_wb16.v │ │ │ ├── pll_xtal64_wb20.v │ │ │ ├── pll_xtal64_wb24.v │ │ │ ├── pll_xtal64_wb30.v │ │ │ └── reset_buffer.v │ │ ├── bench │ │ └── verilog │ │ │ ├── include │ │ │ ├── eth_stim.v │ │ │ ├── orpsoc-testbench-defines.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ ├── orpsoc_testbench.v │ │ │ └── spi_slave.v │ │ ├── rtl │ │ └── verilog │ │ │ ├── arbiter │ │ │ ├── README │ │ │ ├── arbiter_bytebus.v │ │ │ ├── arbiter_dbus.v │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ └── clkgen.v │ │ │ ├── flashrom │ │ │ ├── README │ │ │ └── flashrom.v │ │ │ ├── gpio │ │ │ ├── README │ │ │ └── gpio.v │ │ │ ├── include │ │ │ ├── dbg_cpu_defines.v │ │ │ ├── dbg_defines.v │ │ │ ├── dbg_wb_defines.v │ │ │ ├── ethmac_defines.v │ │ │ ├── i2c_master_slave_defines.v │ │ │ ├── or1200_defines.v │ │ │ ├── orpsoc-defines.v │ │ │ ├── orpsoc-params.v │ │ │ ├── sd_defines.v │ │ │ ├── tap_defines.v │ │ │ ├── uart_defines.v │ │ │ ├── usbhostslave_constants_h.v │ │ │ ├── usbhostslave_hostcontrol_h.v │ │ │ ├── usbhostslave_hostslave_h.v │ │ │ ├── usbhostslave_serialinterfaceengine_h.v │ │ │ ├── usbhostslave_slavecontrol_h.v │ │ │ └── usbhostslave_wishbonebus_h.v │ │ │ ├── orpsoc_top │ │ │ └── orpsoc_top.v │ │ │ ├── sdc_controller │ │ │ ├── sd_bd.v │ │ │ ├── sd_clock_divider.v │ │ │ ├── sd_cmd_master.v │ │ │ ├── sd_cmd_serial_host.v │ │ │ ├── sd_controller_wb.v │ │ │ ├── sd_crc_16.v │ │ │ ├── sd_crc_7.v │ │ │ ├── sd_data_master.v │ │ │ ├── sd_data_serial_host.v │ │ │ ├── sd_fifo_rx_filler.v │ │ │ ├── sd_fifo_tx_filler.v │ │ │ ├── sd_rx_fifo.v │ │ │ ├── sd_rx_fifo_tb.v │ │ │ ├── sd_tx_fifo.v │ │ │ └── sdc_controller.v │ │ │ └── versatile_mem_ctrl │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── Makefile │ │ │ │ ├── burst_length_counter_defines.v │ │ │ │ ├── cke_delay_counter_defines.v │ │ │ │ ├── codec.v │ │ │ │ ├── copyright.v │ │ │ │ ├── ctrl_counter_defines.v │ │ │ │ ├── dcm_pll.v │ │ │ │ ├── ddr_16.fzm │ │ │ │ ├── ddr_16_defines.v │ │ │ │ ├── ddr_ff.v │ │ │ │ ├── delay.v │ │ │ │ ├── egress_fifo.v │ │ │ │ ├── fifo.v │ │ │ │ ├── fifo_adr_counter_defines.v │ │ │ │ ├── fifo_fill.fzm │ │ │ │ ├── fizzim.pl │ │ │ │ ├── fsm_sdr_16.v │ │ │ │ ├── fsm_wb.v │ │ │ │ ├── inc_adr.v │ │ │ │ ├── latency_counter_defines.v │ │ │ │ ├── pre_delay_counter_defines.v │ │ │ │ ├── ref_counter_defines.v │ │ │ │ ├── ref_delay_counter_defines.v │ │ │ │ ├── sdr_16.fzm │ │ │ │ ├── sdr_16_defines.v │ │ │ │ ├── versatile_counter.xls │ │ │ │ ├── versatile_fifo_dual_port_ram_dc_sw.v │ │ │ │ ├── versatile_mem_ctrl_ddr.v │ │ │ │ ├── versatile_mem_ctrl_defines.v │ │ │ │ ├── versatile_mem_ctrl_ip.v │ │ │ │ ├── versatile_mem_ctrl_top.v │ │ │ │ └── versatile_mem_ctrl_wb.v │ │ │ └── versatile_mem_ctrl.v │ │ ├── sim │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── ordb1a3pe1500-or1ksim.cfg │ │ └── run │ │ │ └── Makefile │ │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ ├── bootrom │ │ │ └── Makefile │ │ ├── drivers │ │ │ └── usbhostslave │ │ │ │ ├── Makefile │ │ │ │ ├── include │ │ │ │ ├── usbhostslave-host.h │ │ │ │ └── usbhostslave-slave.h │ │ │ │ ├── usbhostslave-host.c │ │ │ │ └── usbhostslave-slave.c │ │ └── tests │ │ │ ├── i2c_master_slave │ │ │ └── sim │ │ │ │ ├── Makefile │ │ │ │ └── i2c_master_slave-loopback.c │ │ │ └── usbhostslave │ │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── usbhostslave-hostsimple.c │ │ │ └── usbhostslave-slavesimple.c │ │ └── syn │ │ └── synplify │ │ ├── bin │ │ └── Makefile │ │ └── run │ │ └── Makefile ├── altera │ ├── de0_nano │ │ ├── Makefile.inc │ │ ├── backend │ │ │ └── rtl │ │ │ │ └── verilog │ │ │ │ └── pll.v │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── include │ │ │ │ ├── eth_stim.v │ │ │ │ ├── orpsoc-testbench-defines.v │ │ │ │ ├── synthesis-defines.v │ │ │ │ └── timescale.v │ │ │ │ ├── orpsoc_testbench.v │ │ │ │ └── spi_slave.v │ │ ├── rtl │ │ │ ├── verilog │ │ │ │ ├── adv_debugsys │ │ │ │ │ ├── adbg_crc32.v │ │ │ │ │ ├── adbg_jsp_biu.v │ │ │ │ │ ├── adbg_jsp_module.v │ │ │ │ │ ├── adbg_or1k_biu.v │ │ │ │ │ ├── adbg_or1k_module.v │ │ │ │ │ ├── adbg_or1k_status_reg.v │ │ │ │ │ ├── adbg_wb_biu.v │ │ │ │ │ ├── adbg_wb_module.v │ │ │ │ │ ├── adv_dbg_if.v │ │ │ │ │ ├── bytefifo.v │ │ │ │ │ ├── syncflop.v │ │ │ │ │ └── syncreg.v │ │ │ │ ├── arbiter │ │ │ │ │ ├── README │ │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ │ ├── arbiter_dbus.v │ │ │ │ │ └── arbiter_ibus.v │ │ │ │ ├── clkgen │ │ │ │ │ └── clkgen.v │ │ │ │ ├── flashrom │ │ │ │ │ ├── README │ │ │ │ │ └── flashrom.v │ │ │ │ ├── gpio │ │ │ │ │ ├── README │ │ │ │ │ └── gpio.v │ │ │ │ ├── include │ │ │ │ │ ├── adbg_defines.v │ │ │ │ │ ├── adbg_or1k_defines.v │ │ │ │ │ ├── adbg_wb_defines.v │ │ │ │ │ ├── dbg_cpu_defines.v │ │ │ │ │ ├── dbg_defines.v │ │ │ │ │ ├── dbg_wb_defines.v │ │ │ │ │ ├── ethmac_defines.v │ │ │ │ │ ├── i2c_master_slave_defines.v │ │ │ │ │ ├── or1200_defines.v │ │ │ │ │ ├── orpsoc-defines.v │ │ │ │ │ ├── orpsoc-params.v │ │ │ │ │ ├── sd_defines.v │ │ │ │ │ ├── tap_defines.v │ │ │ │ │ ├── uart_defines.v │ │ │ │ │ ├── usbhostslave_constants_h.v │ │ │ │ │ ├── usbhostslave_hostcontrol_h.v │ │ │ │ │ ├── usbhostslave_hostslave_h.v │ │ │ │ │ ├── usbhostslave_serialinterfaceengine_h.v │ │ │ │ │ ├── usbhostslave_slavecontrol_h.v │ │ │ │ │ ├── usbhostslave_wishbonebus_h.v │ │ │ │ │ └── vga_defines.v │ │ │ │ ├── orpsoc_top │ │ │ │ │ └── orpsoc_top.v │ │ │ │ ├── sdc_controller │ │ │ │ │ ├── sd_bd.v │ │ │ │ │ ├── sd_clock_divider.v │ │ │ │ │ ├── sd_cmd_master.v │ │ │ │ │ ├── sd_cmd_serial_host.v │ │ │ │ │ ├── sd_controller_wb.v │ │ │ │ │ ├── sd_crc_16.v │ │ │ │ │ ├── sd_crc_7.v │ │ │ │ │ ├── sd_data_master.v │ │ │ │ │ ├── sd_data_serial_host.v │ │ │ │ │ ├── sd_fifo_rx_filler.v │ │ │ │ │ ├── sd_fifo_tx_filler.v │ │ │ │ │ ├── sd_rx_fifo.v │ │ │ │ │ ├── sd_rx_fifo_tb.v │ │ │ │ │ ├── sd_tx_fifo.v │ │ │ │ │ └── sdc_controller.v │ │ │ │ ├── vga_lcd │ │ │ │ │ ├── generic_dpram.v │ │ │ │ │ ├── generic_spram.v │ │ │ │ │ ├── timescale.v │ │ │ │ │ ├── vga_clkgen.v │ │ │ │ │ ├── vga_colproc.v │ │ │ │ │ ├── vga_csm_pb.v │ │ │ │ │ ├── vga_cur_cregs.v │ │ │ │ │ ├── vga_curproc.v │ │ │ │ │ ├── vga_enh_top.v │ │ │ │ │ ├── vga_fifo.v │ │ │ │ │ ├── vga_fifo_dc.v │ │ │ │ │ ├── vga_pgen.v │ │ │ │ │ ├── vga_tgen.v │ │ │ │ │ ├── vga_vtim.v │ │ │ │ │ ├── vga_wb_master.v │ │ │ │ │ └── vga_wb_slave.v │ │ │ │ └── wb_sdram_ctrl │ │ │ │ │ ├── arbiter.v │ │ │ │ │ ├── sdram_ctrl.v │ │ │ │ │ ├── wb_port.v │ │ │ │ │ └── wb_sdram_ctrl.v │ │ │ └── vhdl │ │ │ │ └── adv_debugsys │ │ │ │ └── altera_virtual_jtag.vhd │ │ ├── sim │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ └── run │ │ │ │ └── Makefile │ │ ├── sw │ │ │ ├── Makefile.inc │ │ │ ├── board │ │ │ │ └── include │ │ │ │ │ └── board.h │ │ │ ├── bootrom │ │ │ │ └── Makefile │ │ │ ├── drivers │ │ │ │ └── usbhostslave │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── include │ │ │ │ │ ├── usbhostslave-host.h │ │ │ │ │ └── usbhostslave-slave.h │ │ │ │ │ ├── usbhostslave-host.c │ │ │ │ │ └── usbhostslave-slave.c │ │ │ └── tests │ │ │ │ ├── i2c_master_slave │ │ │ │ └── sim │ │ │ │ │ ├── Makefile │ │ │ │ │ └── i2c_master_slave-loopback.c │ │ │ │ └── usbhostslave │ │ │ │ └── sim │ │ │ │ ├── Makefile │ │ │ │ ├── usbhostslave-hostsimple.c │ │ │ │ └── usbhostslave-slavesimple.c │ │ └── syn │ │ │ └── quartus │ │ │ ├── bin │ │ │ └── Makefile │ │ │ ├── run │ │ │ └── Makefile │ │ │ ├── sdc │ │ │ ├── JTAG_DEBUG.sdc │ │ │ └── common.sdc │ │ │ └── tcl │ │ │ ├── GENERIC_JTAG_TAP_pin_assignments.tcl │ │ │ ├── GPIO0_pin_assignments.tcl │ │ │ ├── UART0_pin_assignments.tcl │ │ │ ├── VERSATILE_SDRAM_pin_assignments.tcl │ │ │ ├── VGA0_pin_assignments.tcl │ │ │ └── common_pin_assignments.tcl │ └── de2_115 │ │ ├── Makefile.inc │ │ ├── README │ │ ├── backend │ │ └── rtl │ │ │ └── verilog │ │ │ └── pll.v │ │ ├── bench │ │ └── verilog │ │ │ ├── include │ │ │ ├── eth_stim.v │ │ │ ├── orpsoc-testbench-defines.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ ├── orpsoc_testbench.v │ │ │ └── spi_slave.v │ │ ├── rtl │ │ ├── verilog │ │ │ ├── adv_debugsys │ │ │ │ ├── adbg_crc32.v │ │ │ │ ├── adbg_jsp_biu.v │ │ │ │ ├── adbg_jsp_module.v │ │ │ │ ├── adbg_or1k_biu.v │ │ │ │ ├── adbg_or1k_module.v │ │ │ │ ├── adbg_or1k_status_reg.v │ │ │ │ ├── adbg_wb_biu.v │ │ │ │ ├── adbg_wb_module.v │ │ │ │ ├── adv_dbg_if.v │ │ │ │ ├── bytefifo.v │ │ │ │ ├── syncflop.v │ │ │ │ └── syncreg.v │ │ │ ├── arbiter │ │ │ │ ├── README │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ ├── arbiter_dbus.v │ │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ │ └── clkgen.v │ │ │ ├── flashrom │ │ │ │ ├── README │ │ │ │ └── flashrom.v │ │ │ ├── gpio │ │ │ │ ├── README │ │ │ │ └── gpio.v │ │ │ ├── include │ │ │ │ ├── adbg_defines.v │ │ │ │ ├── adbg_or1k_defines.v │ │ │ │ ├── adbg_wb_defines.v │ │ │ │ ├── dbg_cpu_defines.v │ │ │ │ ├── dbg_defines.v │ │ │ │ ├── dbg_wb_defines.v │ │ │ │ ├── ethmac_defines.v │ │ │ │ ├── i2c_master_slave_defines.v │ │ │ │ ├── or1200_defines.v │ │ │ │ ├── orpsoc-defines.v │ │ │ │ ├── orpsoc-params.v │ │ │ │ ├── sd_defines.v │ │ │ │ ├── tap_defines.v │ │ │ │ ├── uart_defines.v │ │ │ │ ├── usbhostslave_constants_h.v │ │ │ │ ├── usbhostslave_hostcontrol_h.v │ │ │ │ ├── usbhostslave_hostslave_h.v │ │ │ │ ├── usbhostslave_serialinterfaceengine_h.v │ │ │ │ ├── usbhostslave_slavecontrol_h.v │ │ │ │ └── usbhostslave_wishbonebus_h.v │ │ │ ├── orpsoc_top │ │ │ │ └── orpsoc_top.v │ │ │ ├── sdc_controller │ │ │ │ ├── sd_bd.v │ │ │ │ ├── sd_clock_divider.v │ │ │ │ ├── sd_cmd_master.v │ │ │ │ ├── sd_cmd_serial_host.v │ │ │ │ ├── sd_controller_wb.v │ │ │ │ ├── sd_crc_16.v │ │ │ │ ├── sd_crc_7.v │ │ │ │ ├── sd_data_master.v │ │ │ │ ├── sd_data_serial_host.v │ │ │ │ ├── sd_fifo_rx_filler.v │ │ │ │ ├── sd_fifo_tx_filler.v │ │ │ │ ├── sd_rx_fifo.v │ │ │ │ ├── sd_rx_fifo_tb.v │ │ │ │ ├── sd_tx_fifo.v │ │ │ │ └── sdc_controller.v │ │ │ └── versatile_mem_ctrl │ │ │ │ ├── Makefile │ │ │ │ ├── README │ │ │ │ ├── rtl │ │ │ │ └── verilog │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── async_fifo_mq.v │ │ │ │ │ ├── burst_length_counter_defines.v │ │ │ │ │ ├── cke_delay_counter_defines.v │ │ │ │ │ ├── codec.v │ │ │ │ │ ├── copyright.v │ │ │ │ │ ├── ctrl_counter_defines.v │ │ │ │ │ ├── dcm_pll.v │ │ │ │ │ ├── ddr_16.fzm │ │ │ │ │ ├── ddr_16_defines.v │ │ │ │ │ ├── ddr_ff.v │ │ │ │ │ ├── delay.v │ │ │ │ │ ├── dff_sr.v │ │ │ │ │ ├── egress_fifo.v │ │ │ │ │ ├── fifo.v │ │ │ │ │ ├── fifo_adr_counter_defines.v │ │ │ │ │ ├── fifo_fill.fzm │ │ │ │ │ ├── fizzim.pl │ │ │ │ │ ├── fsm_sdr_16.v │ │ │ │ │ ├── fsm_wb.v │ │ │ │ │ ├── gray_counter.v │ │ │ │ │ ├── inc_adr.v │ │ │ │ │ ├── latency_counter_defines.v │ │ │ │ │ ├── pre_delay_counter_defines.v │ │ │ │ │ ├── ref_counter.v │ │ │ │ │ ├── ref_counter_defines.v │ │ │ │ │ ├── ref_delay_counter_defines.v │ │ │ │ │ ├── sdr_16.fzm │ │ │ │ │ ├── sdr_16_defines.v │ │ │ │ │ ├── versatile_counter.xls │ │ │ │ │ ├── versatile_fifo_async_cmp.v │ │ │ │ │ ├── versatile_fifo_dual_port_ram_dc_sw.v │ │ │ │ │ ├── versatile_mem_ctrl_ddr.v │ │ │ │ │ ├── versatile_mem_ctrl_defines.v │ │ │ │ │ ├── versatile_mem_ctrl_ip.v │ │ │ │ │ ├── versatile_mem_ctrl_top.v │ │ │ │ │ └── versatile_mem_ctrl_wb.v │ │ │ │ └── versatile_mem_ctrl.v │ │ └── vhdl │ │ │ └── adv_debugsys │ │ │ └── altera_virtual_jtag.vhd │ │ ├── sim │ │ ├── bin │ │ │ └── Makefile │ │ └── run │ │ │ └── Makefile │ │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ ├── bootrom │ │ │ ├── Makefile │ │ │ └── bootrom.v │ │ ├── drivers │ │ │ └── usbhostslave │ │ │ │ ├── Makefile │ │ │ │ ├── include │ │ │ │ ├── usbhostslave-host.h │ │ │ │ └── usbhostslave-slave.h │ │ │ │ ├── usbhostslave-host.c │ │ │ │ └── usbhostslave-slave.c │ │ └── tests │ │ │ ├── i2c_master_slave │ │ │ └── sim │ │ │ │ ├── Makefile │ │ │ │ └── i2c_master_slave-loopback.c │ │ │ └── usbhostslave │ │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── usbhostslave-hostsimple.c │ │ │ └── usbhostslave-slavesimple.c │ │ └── syn │ │ └── quartus │ │ ├── bin │ │ └── Makefile │ │ ├── run │ │ └── Makefile │ │ ├── sdc │ │ ├── JTAG_DEBUG.sdc │ │ └── common.sdc │ │ └── tcl │ │ ├── GENERIC_JTAG_TAP_pin_assignments.tcl │ │ ├── GPIO0_pin_assignments.tcl │ │ ├── UART0_pin_assignments.tcl │ │ ├── VERSATILE_SDRAM_pin_assignments.tcl │ │ └── common_pin_assignments.tcl └── xilinx │ ├── atlys │ ├── Makefile.inc │ ├── README │ ├── backend │ │ ├── bin │ │ │ └── xilinx_ddr2_if_cache.ngc │ │ └── par │ │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── atlys.ucf │ │ │ └── run │ │ │ └── Makefile │ ├── bench │ │ └── verilog │ │ │ ├── ddr2_model.v │ │ │ ├── include │ │ │ ├── ddr2_model_parameters.v │ │ │ ├── ddr2_model_preload.v │ │ │ ├── eth_phy_defines.v │ │ │ ├── eth_stim.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ ├── or1200_monitor.v │ │ │ └── orpsoc_testbench.v │ ├── rtl │ │ └── verilog │ │ │ ├── arbiter │ │ │ ├── arbiter_bytebus.v │ │ │ ├── arbiter_dbus.v │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ └── clkgen.v │ │ │ ├── gpio │ │ │ ├── README │ │ │ └── gpio.v │ │ │ ├── include │ │ │ ├── dbg_cpu_defines.v │ │ │ ├── dbg_defines.v │ │ │ ├── dbg_wb_defines.v │ │ │ ├── ethmac_defines.v │ │ │ ├── i2c_master_slave_defines.v │ │ │ ├── or1200_defines.v │ │ │ ├── orpsoc-defines.v │ │ │ ├── orpsoc-params.v │ │ │ ├── tap_defines.v │ │ │ ├── uart_defines.v │ │ │ └── xilinx_ddr2_params.v │ │ │ ├── lfsr │ │ │ └── lfsr.v │ │ │ ├── orpsoc_top │ │ │ └── orpsoc_top.v │ │ │ └── xilinx_ddr2 │ │ │ ├── README │ │ │ ├── ddr2_mig.v │ │ │ ├── infrastructure.v │ │ │ ├── iodrp_controller.v │ │ │ ├── iodrp_mcb_controller.v │ │ │ ├── mcb_raw_wrapper.v │ │ │ ├── mcb_soft_calibration.v │ │ │ ├── mcb_soft_calibration_top.v │ │ │ ├── mcb_ui_top.v │ │ │ ├── memc_wrapper.v │ │ │ ├── xilinx_ddr2.v │ │ │ ├── xilinx_ddr2_if.v │ │ │ └── xilinx_ddr2_if_cache.v │ ├── sim │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── atlys-or1ksim.cfg │ │ └── run │ │ │ └── Makefile │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ └── bootrom │ │ │ └── Makefile │ └── syn │ │ └── xst │ │ ├── bin │ │ └── Makefile │ │ ├── coregen │ │ ├── coregen.cgp │ │ └── xilinx_ddr2_if_cache.xco │ │ └── run │ │ └── Makefile │ ├── ml501 │ ├── Makefile.inc │ ├── README │ ├── backend │ │ ├── bin │ │ │ └── xilinx_ddr2_if_cache.ngc │ │ └── par │ │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── ml501.ucf │ │ │ └── run │ │ │ └── Makefile │ ├── bench │ │ └── verilog │ │ │ ├── cy7c1354.v │ │ │ ├── ddr2_model.v │ │ │ ├── include │ │ │ ├── ddr2_model_parameters.v │ │ │ ├── ddr2_model_preload.v │ │ │ ├── eth_phy_defines.v │ │ │ ├── eth_stim.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ └── orpsoc_testbench.v │ ├── rtl │ │ └── verilog │ │ │ ├── arbiter │ │ │ ├── arbiter_bytebus.v │ │ │ ├── arbiter_dbus.v │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ └── clkgen.v │ │ │ ├── gpio │ │ │ ├── README │ │ │ └── gpio.v │ │ │ ├── include │ │ │ ├── dbg_cpu_defines.v │ │ │ ├── dbg_defines.v │ │ │ ├── dbg_wb_defines.v │ │ │ ├── ethmac_defines.v │ │ │ ├── i2c_master_slave_defines.v │ │ │ ├── or1200_defines.v │ │ │ ├── orpsoc-defines.v │ │ │ ├── orpsoc-params.v │ │ │ ├── tap_defines.v │ │ │ ├── uart_defines.v │ │ │ └── xilinx_ddr2_params.v │ │ │ ├── lfsr │ │ │ └── lfsr.v │ │ │ ├── orpsoc_top │ │ │ └── orpsoc_top.v │ │ │ ├── xilinx_ddr2 │ │ │ ├── README │ │ │ ├── ddr2_chipscope.v │ │ │ ├── ddr2_ctrl.v │ │ │ ├── ddr2_idelay_ctrl.v │ │ │ ├── ddr2_infrastructure.v │ │ │ ├── ddr2_mem_if_top.v │ │ │ ├── ddr2_mig.v │ │ │ ├── ddr2_phy_calib.v │ │ │ ├── ddr2_phy_ctl_io.v │ │ │ ├── ddr2_phy_dm_iob.v │ │ │ ├── ddr2_phy_dq_iob.v │ │ │ ├── ddr2_phy_dqs_iob.v │ │ │ ├── ddr2_phy_init.v │ │ │ ├── ddr2_phy_io.v │ │ │ ├── ddr2_phy_top.v │ │ │ ├── ddr2_phy_write.v │ │ │ ├── ddr2_top.v │ │ │ ├── ddr2_usr_addr_fifo.v │ │ │ ├── ddr2_usr_rd.v │ │ │ ├── ddr2_usr_top.v │ │ │ ├── ddr2_usr_wr.v │ │ │ ├── xilinx_ddr2.v │ │ │ ├── xilinx_ddr2_if.v │ │ │ └── xilinx_ddr2_if_cache.v │ │ │ └── xilinx_ssram │ │ │ └── xilinx_ssram.v │ ├── sim │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── ml501-or1ksim.cfg │ │ └── run │ │ │ └── Makefile │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ ├── bootrom │ │ │ └── Makefile │ │ └── tests │ │ │ └── ethmac │ │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── ethmac-rx.c │ │ │ ├── ethmac-rxtx.c │ │ │ ├── ethmac-rxtxcallresponse.c │ │ │ └── ethmac-tx.c │ └── syn │ │ └── xst │ │ ├── bin │ │ └── Makefile │ │ └── run │ │ └── Makefile │ └── s3adsp1800 │ ├── Makefile.inc │ ├── README │ ├── backend │ ├── bin │ │ └── s3adsp_ddr2_cache.ngc │ └── par │ │ ├── bin │ │ ├── Makefile │ │ └── s3adsp1800.ucf │ │ └── run │ │ └── Makefile │ ├── bench │ └── verilog │ │ ├── ddr2_model.v │ │ ├── include │ │ ├── ddr2_model_parameters.v │ │ ├── ddr2_model_preload.v │ │ ├── eth_phy_defines.v │ │ ├── eth_stim.v │ │ ├── synthesis-defines.v │ │ └── timescale.v │ │ └── orpsoc_testbench.v │ ├── rtl │ └── verilog │ │ ├── arbiter │ │ ├── arbiter_bytebus.v │ │ ├── arbiter_dbus.v │ │ └── arbiter_ibus.v │ │ ├── clkgen │ │ └── clkgen.v │ │ ├── gpio │ │ ├── README │ │ └── gpio.v │ │ ├── include │ │ ├── dbg_cpu_defines.v │ │ ├── dbg_defines.v │ │ ├── dbg_wb_defines.v │ │ ├── ethmac_defines.v │ │ ├── i2c_master_slave_defines.v │ │ ├── or1200_defines.v │ │ ├── orpsoc-defines.v │ │ ├── orpsoc-params.v │ │ ├── s3adsp_ddr2_parameters_0.v │ │ ├── tap_defines.v │ │ └── uart_defines.v │ │ ├── orpsoc_top │ │ └── orpsoc_top.v │ │ └── xilinx_s3adsp_ddr2 │ │ ├── s3adsp_ddr2.v │ │ ├── s3adsp_ddr2_cache.v │ │ ├── s3adsp_ddr2_cal_ctl.v │ │ ├── s3adsp_ddr2_cal_top.v │ │ ├── s3adsp_ddr2_clk_dcm.v │ │ ├── s3adsp_ddr2_controller_0.v │ │ ├── s3adsp_ddr2_controller_iobs_0.v │ │ ├── s3adsp_ddr2_data_path_0.v │ │ ├── s3adsp_ddr2_data_path_iobs_0.v │ │ ├── s3adsp_ddr2_data_read_0.v │ │ ├── s3adsp_ddr2_data_read_controller_0.v │ │ ├── s3adsp_ddr2_data_write_0.v │ │ ├── s3adsp_ddr2_dqs_delay.v │ │ ├── s3adsp_ddr2_fifo_0_wr_en_0.v │ │ ├── s3adsp_ddr2_fifo_1_wr_en_0.v │ │ ├── s3adsp_ddr2_infrastructure.v │ │ ├── s3adsp_ddr2_infrastructure_iobs_0.v │ │ ├── s3adsp_ddr2_infrastructure_top.v │ │ ├── s3adsp_ddr2_iobs_0.v │ │ ├── s3adsp_ddr2_ram8d_0.v │ │ ├── s3adsp_ddr2_rd_gray_cntr.v │ │ ├── s3adsp_ddr2_s3_dm_iob.v │ │ ├── s3adsp_ddr2_s3_dq_iob.v │ │ ├── s3adsp_ddr2_s3_dqs_iob.v │ │ ├── s3adsp_ddr2_tap_dly.v │ │ ├── s3adsp_ddr2_top_0.v │ │ ├── s3adsp_ddr2_wr_gray_cntr.v │ │ ├── xilinx_s3adsp_ddr2.v │ │ └── xilinx_s3adsp_ddr2_if.v │ ├── sim │ ├── bin │ │ └── Makefile │ └── run │ │ └── Makefile │ ├── sw │ ├── Makefile.inc │ ├── board │ │ └── include │ │ │ └── board.h │ ├── bootrom │ │ ├── Makefile │ │ └── bootrom.v │ └── tests │ │ ├── ddr2cache │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── ddr2cache-1.S │ │ │ └── ddr2cache-2.S │ │ └── ethmac │ │ └── sim │ │ ├── Makefile │ │ ├── ethmac-rx.c │ │ ├── ethmac-rxtx.c │ │ ├── ethmac-rxtxcallresponse.c │ │ └── ethmac-tx.c │ └── syn │ └── xst │ ├── bin │ └── Makefile │ └── run │ └── Makefile ├── doc ├── Makefile.am ├── Makefile.in ├── aclocal.m4 ├── autom4te.cache │ ├── output.0 │ ├── output.1 │ ├── output.2 │ ├── requests │ ├── traces.0 │ ├── traces.1 │ └── traces.2 ├── config.texi ├── configure ├── configure.in ├── fdl-1.2.texi ├── install-sh ├── missing ├── orpsoc.texi └── texinfo.tex ├── rtl └── verilog │ ├── arbiter │ ├── README │ ├── arbiter_bytebus.v │ ├── arbiter_dbus.v │ └── arbiter_ibus.v │ ├── cfi_ctrl │ ├── cfi_ctrl.v │ └── cfi_ctrl_engine.v │ ├── clkgen │ ├── README │ └── clkgen.v │ ├── dbg_if │ ├── dbg_cpu.v │ ├── dbg_cpu_registers.v │ ├── dbg_crc32_d1.v │ ├── dbg_if.v │ ├── dbg_register.v │ └── dbg_wb.v │ ├── ethmac │ ├── README │ ├── eth_clockgen.v │ ├── eth_crc.v │ ├── eth_fifo.v │ ├── eth_maccontrol.v │ ├── eth_macstatus.v │ ├── eth_miim.v │ ├── eth_outputcontrol.v │ ├── eth_random.v │ ├── eth_receivecontrol.v │ ├── eth_register.v │ ├── eth_registers.v │ ├── eth_rxaddrcheck.v │ ├── eth_rxcounters.v │ ├── eth_rxethmac.v │ ├── eth_rxstatem.v │ ├── eth_shiftreg.v │ ├── eth_spram_256x32.v │ ├── eth_transmitcontrol.v │ ├── eth_txcounters.v │ ├── eth_txethmac.v │ ├── eth_txstatem.v │ ├── eth_wishbone.v │ ├── ethmac.v │ └── xilinx_dist_ram_16x32.v │ ├── i2c_master_slave │ ├── README │ ├── i2c_master_bit_ctrl.v │ ├── i2c_master_byte_ctrl.v │ └── i2c_master_slave.v │ ├── include │ ├── dbg_cpu_defines.v │ ├── dbg_defines.v │ ├── dbg_wb_defines.v │ ├── ethmac_defines.v │ ├── i2c_master_slave_defines.v │ ├── or1200_defines.v │ ├── orpsoc-defines.v │ ├── orpsoc-params.v │ ├── tap_defines.v │ ├── uart_defines.v │ ├── usbhostslave_constants_h.v │ ├── usbhostslave_hostcontrol_h.v │ ├── usbhostslave_hostslave_h.v │ ├── usbhostslave_serialinterfaceengine_h.v │ ├── usbhostslave_slavecontrol_h.v │ └── usbhostslave_wishbonebus_h.v │ ├── intgen │ └── intgen.v │ ├── jtag_tap │ ├── README │ └── jtag_tap.v │ ├── or1200 │ ├── or1200_alu.v │ ├── or1200_amultp2_32x32.v │ ├── or1200_cfgr.v │ ├── or1200_cpu.v │ ├── or1200_ctrl.v │ ├── or1200_dc_fsm.v │ ├── or1200_dc_ram.v │ ├── or1200_dc_tag.v │ ├── or1200_dc_top.v │ ├── or1200_dmmu_tlb.v │ ├── or1200_dmmu_top.v │ ├── or1200_dpram.v │ ├── or1200_dpram_256x32.v │ ├── or1200_dpram_32x32.v │ ├── or1200_du.v │ ├── or1200_except.v │ ├── or1200_fpu.v │ ├── or1200_fpu_addsub.v │ ├── or1200_fpu_arith.v │ ├── or1200_fpu_div.v │ ├── or1200_fpu_fcmp.v │ ├── or1200_fpu_intfloat_conv.v │ ├── or1200_fpu_mul.v │ ├── or1200_fpu_post_norm_addsub.v │ ├── or1200_fpu_post_norm_div.v │ ├── or1200_fpu_post_norm_intfloat_conv.v │ ├── or1200_fpu_post_norm_mul.v │ ├── or1200_fpu_pre_norm_addsub.v │ ├── or1200_fpu_pre_norm_div.v │ ├── or1200_fpu_pre_norm_mul.v │ ├── or1200_freeze.v │ ├── or1200_genpc.v │ ├── or1200_gmultp2_32x32.v │ ├── or1200_ic_fsm.v │ ├── or1200_ic_ram.v │ ├── or1200_ic_tag.v │ ├── or1200_ic_top.v │ ├── or1200_if.v │ ├── or1200_immu_tlb.v │ ├── or1200_immu_top.v │ ├── or1200_iwb_biu.v │ ├── or1200_lsu.v │ ├── or1200_mem2reg.v │ ├── or1200_mult_mac.v │ ├── or1200_operandmuxes.v │ ├── or1200_pic.v │ ├── or1200_pm.v │ ├── or1200_qmem_top.v │ ├── or1200_reg2mem.v │ ├── or1200_rf.v │ ├── or1200_rfram_generic.v │ ├── or1200_sb.v │ ├── or1200_sb_fifo.v │ ├── or1200_spram.v │ ├── or1200_spram_1024x32.v │ ├── or1200_spram_1024x32_bw.v │ ├── or1200_spram_1024x8.v │ ├── or1200_spram_128x32.v │ ├── or1200_spram_2048x32.v │ ├── or1200_spram_2048x32_bw.v │ ├── or1200_spram_2048x8.v │ ├── or1200_spram_256x21.v │ ├── or1200_spram_32_bw.v │ ├── or1200_spram_32x24.v │ ├── or1200_spram_512x20.v │ ├── or1200_spram_64x14.v │ ├── or1200_spram_64x22.v │ ├── or1200_spram_64x24.v │ ├── or1200_sprs.v │ ├── or1200_top.v │ ├── or1200_tpram_32x32.v │ ├── or1200_tt.v │ ├── or1200_wb_biu.v │ ├── or1200_wbmux.v │ └── or1200_xcv_ram32x8d.v │ ├── orpsoc_top │ └── orpsoc_top.v │ ├── ram_wb │ ├── ram_wb.v │ └── ram_wb_b3.v │ ├── rom │ ├── README │ └── rom.v │ ├── simple_spi │ ├── README │ ├── fifo4.v │ └── simple_spi.v │ ├── smii │ ├── README │ ├── smii.v │ ├── smii_if.v │ └── smii_sync.v │ ├── uart16550 │ ├── README │ ├── raminfr.v │ ├── uart16550.v │ ├── uart_debug_if.v │ ├── uart_receiver.v │ ├── uart_regs.v │ ├── uart_rfifo.v │ ├── uart_sync_flops.v │ ├── uart_tfifo.v │ ├── uart_transmitter.v │ └── uart_wb.v │ ├── usbhostslave │ ├── HCTxPortArbiter.v │ ├── README │ ├── RxFifo.v │ ├── RxfifoBI.v │ ├── SCTxPortArbiter.v │ ├── SIEReceiver.v │ ├── SIETransmitter.v │ ├── SOFController.v │ ├── SOFTransmit.v │ ├── TxFifo.v │ ├── TxfifoBI.v │ ├── USBHostControlBI.v │ ├── USBSlaveControlBI.v │ ├── USBTxWireArbiter.v │ ├── directControl.v │ ├── dpMem_dc.v │ ├── endpMux.v │ ├── fifoMux.v │ ├── fifoRTL.v │ ├── getPacket.v │ ├── hostSlaveMux.v │ ├── hostSlaveMuxBI.v │ ├── hostcontroller.v │ ├── lineControlUpdate.v │ ├── processRxBit.v │ ├── processRxByte.v │ ├── processTxByte.v │ ├── readUSBWireData.v │ ├── rxStatusMonitor.v │ ├── sendPacket.v │ ├── sendPacketArbiter.v │ ├── sendPacketCheckPreamble.v │ ├── slaveDirectControl.v │ ├── slaveGetPacket.v │ ├── slaveRxStatusMonitor.v │ ├── slaveSendPacket.v │ ├── slavecontroller.v │ ├── speedCtrlMux.v │ ├── updateCRC16.v │ ├── updateCRC5.v │ ├── usbHostControl.v │ ├── usbSerialInterfaceEngine.v │ ├── usbSlaveControl.v │ ├── usbhost.v │ ├── usbhostslave.v │ ├── usbslave.v │ ├── wishBoneBI.v │ └── writeUSBWireData.v │ ├── wb_ram_b3 │ └── wb_ram_b3.v │ └── wb_switch_b3 │ └── wb_switch_b3.v ├── scripts └── make │ ├── Makefile-board-benchsrc.inc │ ├── Makefile-board-definesparse.inc │ ├── Makefile-board-icarus.inc │ ├── Makefile-board-modelsim.inc │ ├── Makefile-board-paths.inc │ ├── Makefile-board-rtlmodules.inc │ ├── Makefile-board-simclean.inc │ ├── Makefile-board-sw.inc │ ├── Makefile-board-tops.inc │ ├── Makefile-misc.inc │ ├── Makefile-rtltestrules.inc │ ├── Makefile-sim-definesgen.inc │ ├── Makefile-simulators.inc │ └── Makefile-swrules.inc ├── sim ├── bin │ ├── Makefile │ ├── definesgen.inc │ └── refdesign-or1ksim.cfg └── run │ └── Makefile └── sw ├── Makefile.inc ├── README ├── apps ├── cfi_ctrl_programmer │ ├── Makefile │ ├── cfi_ctrl_programmer.c │ └── cfi_ctrl_programmer.ld ├── dhry │ ├── Makefile │ ├── dhry.c │ └── dhry.h ├── spiflash │ ├── Makefile │ ├── README │ ├── spiflash-program.c │ └── spiflash-program.ld └── testfloat │ ├── Makefile │ ├── README │ ├── fail.c │ ├── fail.h │ ├── milieu.h │ ├── or1k-gcc.h │ ├── random.c │ ├── random.h │ ├── slowfloat.c │ ├── slowfloat.h │ ├── softfloat.c │ ├── softfloat.h │ ├── systflags.c │ ├── systflags.h │ ├── systfloat.S │ ├── systfloat.h │ ├── systmodes.c │ ├── systmodes.h │ ├── testCases.c │ ├── testCases.h │ ├── testFunction.c │ ├── testFunction.h │ ├── testLoops.c │ ├── testLoops.h │ ├── testfloat.c │ ├── testsoftfloat.c │ ├── writeHex.c │ └── writeHex.h ├── board └── include │ └── board.h ├── bootrom ├── Makefile └── bootrom.S ├── drivers ├── cfi-ctrl │ ├── Makefile │ ├── cfi_ctrl.c │ └── include │ │ └── cfi_ctrl.h ├── ethmac │ ├── Makefile │ ├── ethmac.c │ └── include │ │ ├── eth-phy-mii.h │ │ └── ethmac.h ├── i2c_master_slave │ ├── Makefile │ ├── i2c_master_slave.c │ └── include │ │ └── i2c_master_slave.h ├── or1200 │ ├── Makefile │ ├── cache.S │ ├── crt0.S │ ├── exceptions.c │ ├── include │ │ ├── int.h │ │ ├── or1200-utils.h │ │ └── spr-defs.h │ ├── int.c │ ├── link.ld │ ├── mmu.S │ └── or1200-utils.c ├── simple-spi │ ├── Makefile │ ├── include │ │ └── simple-spi.h │ └── simple-spi.c └── uart │ ├── Makefile │ ├── include │ └── uart.h │ └── uart.c ├── lib ├── Makefile ├── include │ ├── cpu-utils.h │ ├── lib-utils.h │ └── printf.h ├── lib-utils.c └── printf.c ├── tests ├── cfi_ctrl │ ├── board │ │ ├── Makefile │ │ ├── cfi_ctrl-readid.c │ │ └── cfi_ctrl-simple.c │ └── sim │ │ ├── Makefile │ │ ├── cfi_ctrl-readid.c │ │ └── cfi_ctrl-simple.c ├── ethmac │ ├── board │ │ ├── Makefile │ │ └── ethmac-ping.c │ └── sim │ │ ├── Makefile │ │ ├── ethmac-rx.c │ │ ├── ethmac-rxtx.c │ │ ├── ethmac-rxtxcallresponse.c │ │ ├── ethmac-rxtxoverflow.c │ │ └── ethmac-tx.c ├── or1200 │ ├── board │ │ ├── Makefile │ │ ├── or1200-configdetect.c │ │ ├── or1200-div.c │ │ ├── or1200-mmu.c │ │ ├── or1200-mul.c │ │ ├── or1200-rfemmu.S │ │ └── or1200-timerdemo.c │ └── sim │ │ ├── Makefile │ │ ├── or1200-basic.S │ │ ├── or1200-cbasic.c │ │ ├── or1200-cy.S │ │ ├── or1200-dctest.c │ │ ├── or1200-div.c │ │ ├── or1200-except.S │ │ ├── or1200-ext.S │ │ ├── or1200-ffl1.S │ │ ├── or1200-float.c │ │ ├── or1200-fp.S │ │ ├── or1200-intsyscall.S │ │ ├── or1200-linkregtest.S │ │ ├── or1200-mac.S │ │ ├── or1200-maci.S │ │ ├── or1200-mmu.c │ │ ├── or1200-mul.c │ │ ├── or1200-ov.S │ │ ├── or1200-rfe.S │ │ ├── or1200-rfemmu.S │ │ ├── or1200-sf.S │ │ ├── or1200-simple.c │ │ ├── or1200-tick.S │ │ └── or1200-ticksyscall.S ├── sdram │ ├── board │ │ ├── Makefile │ │ └── sdram-rows.c │ └── sim │ │ ├── Makefile │ │ ├── sdram-bankrows.c │ │ ├── sdram-banks.c │ │ ├── sdram-cols.c │ │ ├── sdram-rows.c │ │ └── sdram.h ├── spi │ ├── board │ │ ├── Makefile │ │ └── simplespi-readflash.c │ └── sim │ │ ├── Makefile │ │ ├── spi-interrupt.c │ │ └── spi-simple.c └── uart │ ├── board │ ├── Makefile │ └── uart-echo.c │ └── sim │ ├── Makefile │ ├── uart-interrupt.c │ ├── uart-interruptloopback.c │ └── uart-simple.c └── utils ├── Makefile ├── bin2binsizeword.c ├── bin2c.c ├── bin2flimg.c ├── bin2hex.c ├── bin2srec.c ├── bin2vlogarray.c ├── bin2vmem.c ├── binlog2readable.cpp ├── loader.c └── or32-idecode ├── Makefile ├── ansidecl.h ├── bfd.h ├── dis-asm.h ├── example_input ├── or32-dis.c ├── or32-opc.c ├── or32.h └── symcat.h /bench/sysc/include/JtagSC_includes.h: -------------------------------------------------------------------------------- 1 | // ---------------------------------------------------------------------------- 2 | 3 | // Unified Header file for the Embecosm cycle accurate SystemC JTAG library 4 | 5 | // Copyright (C) 2009 Embecosm Limited 6 | 7 | // Contributor Jeremy Bennett 8 | 9 | // This file is part of the Embecosm cycle accurate SystemC JTAG library. 10 | 11 | // This program is free software: you can redistribute it and/or modify it 12 | // under the terms of the GNU Lesser General Public License as published by 13 | // the Free Software Foundation, either version 3 of the License, or (at your 14 | // option) any later version. 15 | 16 | // This program is distributed in the hope that it will be useful, but WITHOUT 17 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 19 | // License for more details. 20 | 21 | // You should have received a copy of the GNU Lesser General Public License 22 | // along with this program. If not, see . 23 | 24 | // The C/C++ parts of this program are commented throughout in a fashion 25 | // suitable for processing with Doxygen. 26 | 27 | // ---------------------------------------------------------------------------- 28 | 29 | // $Id$ 30 | 31 | #include "JtagSC.h" 32 | #include "TapActionDRScan.h" 33 | #include "TapAction.h" 34 | #include "TapActionIRScan.h" 35 | #include "TapActionReset.h" 36 | #include "TapStateMachine.h" 37 | -------------------------------------------------------------------------------- /bench/sysc/include/ResetSC.h: -------------------------------------------------------------------------------- 1 | // ---------------------------------------------------------------------------- 2 | 3 | // SystemC reset signal generator header 4 | 5 | // Copyright (C) 2008 Embecosm Limited 6 | 7 | // Contributor Jeremy Bennett 8 | 9 | // This file is part of the cycle accurate model of the OpenRISC 1000 based 10 | // system-on-chip, ORPSoC, built using Verilator. 11 | 12 | // This program is free software: you can redistribute it and/or modify it 13 | // under the terms of the GNU Lesser General Public License as published by 14 | // the Free Software Foundation, either version 3 of the License, or (at your 15 | // option) any later version. 16 | 17 | // This program is distributed in the hope that it will be useful, but WITHOUT 18 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 20 | // License for more details. 21 | 22 | // You should have received a copy of the GNU Lesser General Public License 23 | // along with this program. If not, see . 24 | 25 | // ---------------------------------------------------------------------------- 26 | 27 | // $Id: ResetSC.h 286 2009-02-03 11:19:30Z jeremy $ 28 | 29 | #ifndef RESET_SC__H 30 | #define RESET_SC__H 31 | 32 | #include "systemc" 33 | 34 | //! Provide a SystemC reset signal at startup 35 | 36 | //! The reset signal is driven for a specified number of cycles after 37 | //! creation. For convenience synchronous versions of the reset signal are 38 | //! provided in both active high and active low formats. 39 | 40 | class ResetSC:public sc_core::sc_module { 41 | public: 42 | 43 | // Constructor 44 | ResetSC(sc_core::sc_module_name name, int _resetCounter = 5); 45 | 46 | // Method to drive the reset 47 | void driveReset(); 48 | 49 | // The ports 50 | sc_core::sc_in < bool > clk; 51 | sc_core::sc_out < bool > rst; // Active high reset 52 | sc_core::sc_out < bool > rstn; // Active low reset 53 | 54 | private: 55 | 56 | int resetCounter; 57 | 58 | }; // ResetSC () 59 | 60 | #endif // RESET_SC__H 61 | -------------------------------------------------------------------------------- /bench/sysc/include/TapActionReset.h: -------------------------------------------------------------------------------- 1 | // ---------------------------------------------------------------------------- 2 | 3 | // TAP reset action : definition 4 | 5 | // Copyright (C) 2009 Embecosm Limited 6 | 7 | // Contributor Jeremy Bennett 8 | 9 | // This file is part of the Embecosm cycle accurate SystemC JTAG library. 10 | 11 | // This program is free software: you can redistribute it and/or modify it 12 | // under the terms of the GNU Lesser General Public License as published by 13 | // the Free Software Foundation, either version 3 of the License, or (at your 14 | // option) any later version. 15 | 16 | // This program is distributed in the hope that it will be useful, but WITHOUT 17 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 19 | // License for more details. 20 | 21 | // You should have received a copy of the GNU Lesser General Public License 22 | // along with this program. If not, see . 23 | 24 | // The C/C++ parts of this program are commented throughout in a fashion 25 | // suitable for processing with Doxygen. 26 | 27 | // ---------------------------------------------------------------------------- 28 | 29 | // $Id$ 30 | 31 | #ifndef TAP_RESET_ACTION__H 32 | #define TAP_RESET_ACTION__H 33 | 34 | #include "TapAction.h" 35 | #include "TapStateMachine.h" 36 | 37 | //! Class to represent a TAP reset action. 38 | 39 | //! This can be very simple, since it reuses the parent class method to do the 40 | //! reset. 41 | 42 | class TapActionReset:public TapAction { 43 | public: 44 | 45 | // Constructor 46 | TapActionReset(sc_core::sc_event * _doneEvent); 47 | 48 | protected: 49 | 50 | // Process the action for reset 51 | bool process(TapStateMachine * tapStateMachine, 52 | bool & tdi, bool tdo, bool & tms); 53 | 54 | private: 55 | 56 | //!< Flag to mark first call to process method 57 | bool firstTime; 58 | 59 | }; // TapActionReset 60 | 61 | #endif // TAP_RESET_ACTION__H 62 | -------------------------------------------------------------------------------- /bench/sysc/include/UartSC.h: -------------------------------------------------------------------------------- 1 | // ---------------------------------------------------------------------------- 2 | 3 | // SystemC Uart: definition 4 | 5 | // This file is part of the cycle accurate model of the OpenRISC 1000 based 6 | // system-on-chip, ORPSoC, built using Verilator. 7 | 8 | // This program is free software: you can redistribute it and/or modify it 9 | // under the terms of the GNU Lesser General Public License as published by 10 | // the Free Software Foundation, either version 3 of the License, or (at your 11 | // option) any later version. 12 | 13 | // This program is distributed in the hope that it will be useful, but WITHOUT 14 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 16 | // License for more details. 17 | 18 | // You should have received a copy of the GNU Lesser General Public License 19 | // along with this program. If not, see . 20 | 21 | // ---------------------------------------------------------------------------- 22 | 23 | // $Id: $ 24 | 25 | #ifndef UART_SC__H 26 | #define UART_SC__H 27 | 28 | #include "systemc.h" 29 | #include 30 | 31 | //! Handle UART I/O 32 | 33 | class UartSC:public sc_core::sc_module { 34 | public: 35 | 36 | // Constructor 37 | UartSC(sc_core::sc_module_name name); 38 | 39 | // The ports 40 | sc_in < bool > clk; 41 | sc_in < bool > uarttx; 42 | sc_out < bool > uartrx; 43 | 44 | // Init function 45 | void initUart(int uart_baud); 46 | // Transmit (from ORPSoC) handling function 47 | void checkTx(); 48 | // Receieve (in ORPSoC) generation function 49 | void driveRx(); 50 | // Check keyboard for entry 51 | int kbhit(); 52 | // Enable canonical mode on console 53 | void nonblock(int state); 54 | 55 | private: 56 | uint8_t current_char; 57 | int counter; 58 | int bits_received; 59 | int ns_per_bit; 60 | 61 | int rx_state; 62 | int rx_counter; 63 | int rx_bits_sent; 64 | char rx_char; 65 | 66 | }; // UartSC () 67 | 68 | #endif // UART_SC__H 69 | -------------------------------------------------------------------------------- /bench/sysc/src/ResetSC.cpp: -------------------------------------------------------------------------------- 1 | // ---------------------------------------------------------------------------- 2 | 3 | // SystemC reset signal generator 4 | 5 | // Copyright (C) 2008 Embecosm Limited 6 | 7 | // Contributor Jeremy Bennett 8 | 9 | // This file is part of the cycle accurate model of the OpenRISC 1000 based 10 | // system-on-chip, ORPSoC, built using Verilator. 11 | 12 | // This program is free software: you can redistribute it and/or modify it 13 | // under the terms of the GNU Lesser General Public License as published by 14 | // the Free Software Foundation, either version 3 of the License, or (at your 15 | // option) any later version. 16 | 17 | // This program is distributed in the hope that it will be useful, but WITHOUT 18 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 20 | // License for more details. 21 | 22 | // You should have received a copy of the GNU Lesser General Public License 23 | // along with this program. If not, see . 24 | 25 | // ---------------------------------------------------------------------------- 26 | 27 | // $Id: ResetSC.cpp 286 2009-02-03 11:19:30Z jeremy $ 28 | 29 | #include "ResetSC.h" 30 | 31 | SC_HAS_PROCESS(ResetSC); 32 | 33 | //! Constructor for the reset generator 34 | 35 | //! @param name Name of this module, passed to the parent 36 | //! constructor. 37 | //! @param resetCounter Number of cycles of reset to provide. 38 | 39 | ResetSC::ResetSC(sc_core::sc_module_name name, int _resetCounter): 40 | sc_module(name), resetCounter(_resetCounter) 41 | { 42 | SC_METHOD(driveReset); 43 | sensitive << clk.neg(); 44 | 45 | } // ResetSC () 46 | 47 | //! Method to drive the reset port (active low). We will be called as an 48 | //! initialization, which can be used to drive the reset low. 49 | void ResetSC::driveReset() 50 | { 51 | if (resetCounter > 0) { 52 | rst = 1; 53 | rstn = 0; 54 | resetCounter--; 55 | } else { 56 | rst = 0; 57 | rstn = 1; 58 | } 59 | } // driveReset() 60 | -------------------------------------------------------------------------------- /bench/verilog/include/cfi_flash_UserData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F256P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 256Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / single die / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.3 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // ************************************ 23 | // 24 | // User Data definition file : 25 | // 26 | // here are defined all parameters 27 | // that the user can change 28 | // 29 | // ************************************ 30 | 31 | 32 | `define organization "top" // top or bottom 33 | `define BLOCKPROTECT "on" // if on the blocks are locked at power-up 34 | `define TimingChecks "on" // on for checking timing constraints 35 | `define t_access 100 // Access Time 100 ns, 110 ns 36 | `define FILENAME_mem "cfi-flash.vmem" // Memory File Name 37 | -------------------------------------------------------------------------------- /bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /bench/verilog/mt48lc16m16a2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/orpsoc/673f53248125fc6ff7414bb7360c9f61237308f8/bench/verilog/mt48lc16m16a2.v -------------------------------------------------------------------------------- /bench/verilog/usbhostslave/usbConstants_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// usbConstants_h.v 3 | /////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef usbConstants_h_vdefined 6 | `else 7 | `define usbConstants_h_vdefined 8 | 9 | //PIDTypes 10 | `define OUT 4'h1 11 | `define IN 4'h9 12 | `define SOF 4'h5 13 | `define SETUP 4'hd 14 | `define DATA0 4'h3 15 | `define DATA1 4'hb 16 | `define ACK 4'h2 17 | `define NAK 4'ha 18 | `define STALL 4'he 19 | `define PREAMBLE 4'hc 20 | 21 | 22 | //PIDGroups 23 | `define SPECIAL 2'b00 24 | `define TOKEN 2'b01 25 | `define HANDSHAKE 2'b10 26 | `define DATA 2'b11 27 | 28 | // start of packet SyncByte 29 | `define SYNC_BYTE 8'h80 30 | 31 | `endif //usbConstants_h_vdefined 32 | 33 | -------------------------------------------------------------------------------- /bench/verilog/usbhostslave/wishBoneBus_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // wishBoneBus_h.v 3 | ////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef wishBoneBus_h_vdefined 6 | `else 7 | `define wishBoneBus_h_vdefined 8 | 9 | //memoryMap 10 | `define HCREG_BASE 8'h00 11 | `define HCREG_BASE_PLUS_0X10 8'h10 12 | `define HOST_RX_FIFO_BASE 8'h20 13 | `define HOST_TX_FIFO_BASE 8'h30 14 | `define SCREG_BASE 8'h40 15 | `define SCREG_BASE_PLUS_0X10 8'h50 16 | `define EP0_RX_FIFO_BASE 8'h60 17 | `define EP0_TX_FIFO_BASE 8'h70 18 | `define EP1_RX_FIFO_BASE 8'h80 19 | `define EP1_TX_FIFO_BASE 8'h90 20 | `define EP2_RX_FIFO_BASE 8'ha0 21 | `define EP2_TX_FIFO_BASE 8'hb0 22 | `define EP3_RX_FIFO_BASE 8'hc0 23 | `define EP3_TX_FIFO_BASE 8'hd0 24 | `define HOST_SLAVE_CONTROL_BASE 8'he0 25 | `define ADDRESS_DECODE_MASK 8'hf0 26 | 27 | //FifoAddresses 28 | `define FIFO_DATA_REG 3'b000 29 | `define FIFO_STATUS_REG 3'b001 30 | `define FIFO_DATA_COUNT_MSB 3'b010 31 | `define FIFO_DATA_COUNT_LSB 3'b011 32 | `define FIFO_CONTROL_REG 3'b100 33 | 34 | `endif //wishBoneBus_h_vdefined 35 | 36 | -------------------------------------------------------------------------------- /bench/verilog/wiredelay.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module wiredelay # ( 5 | parameter Delay_g = 0, 6 | parameter Delay_rd = 0 7 | ) 8 | ( 9 | inout A, 10 | inout B, 11 | input reset 12 | ); 13 | 14 | reg A_r; 15 | reg B_r; 16 | reg line_en; 17 | 18 | assign A = A_r; 19 | assign B = B_r; 20 | 21 | always @(*) begin 22 | if (!reset) begin 23 | A_r <= 1'bz; 24 | B_r <= 1'bz; 25 | line_en <= 1'b0; 26 | end else begin 27 | if (line_en) begin 28 | A_r <= #Delay_rd B; 29 | B_r <= 1'bz; 30 | end else begin 31 | B_r <= #Delay_g A; 32 | A_r <= 1'bz; 33 | end 34 | end 35 | end 36 | 37 | always @(A or B) begin 38 | if (!reset) begin 39 | line_en <= 1'b0; 40 | end else if (A !== A_r) begin 41 | line_en <= 1'b0; 42 | end else if (B_r !== B) begin 43 | line_en <= 1'b1; 44 | end else begin 45 | line_en <= line_en; 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /boards/README: -------------------------------------------------------------------------------- 1 | ORPSoC board builds 2 | 3 | This directory contains a path for each technology vendor the board builds 4 | target. 5 | 6 | Under each of those vendor paths are the specific board paths. 7 | 8 | See the main documentation in ORPSoC's root path doc/ for more information. -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/README: -------------------------------------------------------------------------------- 1 | Actel Verilog RTL files 2 | 3 | The files in this directory are Actel specific RTL 4 | 5 | These are all, at present, wrappers for Actel primitives. Most, if not all, were 6 | generated with Actel's smartgen tool 7 | 8 | eth_pll.v: 9 | PLL for the 125MHz ethernet clock on the ORDB1 with as little 10 | insertion delay as possible. 11 | 12 | gbuf.v: 13 | Buffer for clocks (used in clkgen module) 14 | 15 | pll_xtalXX_wbYY: 16 | PLL taking external oscillator at XX MHz and generating Wishbone 17 | clock at frequency YY. 18 | 19 | reset_buffer.v: 20 | Buffer for reset (used in clkgen module) 21 | 22 | orpsoc_flashROM.v: 23 | Instantiation of UFR. 24 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/eth_pll.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module eth_pll(POWERDOWN,CLKA,LOCK,GLA); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA; 8 | 9 | wire CLKAP, VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(125.000) ) Core(.CLKA(CLKAP), .EXTFB( 14 | GND), .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB( 15 | ), .YB(), .GLC(), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(VCC), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(GND), 19 | .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(GND) 28 | , .FINDIV1(VCC), .FINDIV2(VCC), .FINDIV3(GND), .FINDIV4( 29 | VCC), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1( 30 | VCC), .FBDIV2(VCC), .FBDIV3(GND), .FBDIV4(VCC), .FBDIV5( 31 | GND), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(GND), .VCOSEL1(GND), 34 | .VCOSEL2(VCC)); 35 | PLLINT pllint1(.A(CLKA), .Y(CLKAP)); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/gbuf.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.4 8.4.0.33 3 | 4 | 5 | module gbuf(GL,CLK); 6 | output GL; 7 | input CLK; 8 | 9 | wire GND; 10 | 11 | GND GND_1_net(.Y(GND)); 12 | CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND), 13 | .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/orpsoc_flashROM.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module orpsoc_flashROM(CLK,ADDR,DOUT); 6 | input CLK; 7 | input [6:0] ADDR; 8 | output [7:0] DOUT; 9 | 10 | wire U_7_PIN2; 11 | 12 | GND GND_1_net(.Y(U_7_PIN2)); 13 | UFROMH #( .MEMORYFILE("devboard_flashROM.mem"), .ACT_PROGFILE("devboard_flashROM.ufc") 14 | ) UFROM0(.CLK(CLK), .DO0(DOUT[0]), .DO1(DOUT[1]), .DO2( 15 | DOUT[2]), .DO3(DOUT[3]), .DO4(DOUT[4]), .DO5(DOUT[5]), 16 | .DO6(DOUT[6]), .DO7(DOUT[7]), .ADDR0(ADDR[0]), .ADDR1( 17 | ADDR[1]), .ADDR2(ADDR[2]), .ADDR3(ADDR[3]), .ADDR4( 18 | ADDR[4]), .ADDR5(ADDR[5]), .ADDR6(ADDR[6])); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal25_wb20.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module pll_xtal25_wb20(POWERDOWN,CLKA,LOCK,GLA,GLB,GLC); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA, GLB, GLC; 8 | 9 | wire VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(240.000) ) Core(.CLKA(CLKA), .EXTFB(GND) 14 | , .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(GLB) 15 | , .YB(), .GLC(GLC), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(GND), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(VCC), 19 | .OBDIV1(VCC), .OBDIV2(GND), .OBDIV3(VCC), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(VCC), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(VCC), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(VCC), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(GND) 28 | , .FINDIV1(GND), .FINDIV2(VCC), .FINDIV3(GND), .FINDIV4( 29 | GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(VCC), .FBDIV1( 30 | VCC), .FBDIV2(VCC), .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5( 31 | VCC), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(VCC), .VCOSEL1(VCC), 34 | .VCOSEL2(VCC)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal25_wb24.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module pll_xtal25_wb24(POWERDOWN,CLKA,LOCK,GLA,GLB,GLC); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA, GLB, GLC; 8 | 9 | wire VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(240.000) ) Core(.CLKA(CLKA), .EXTFB(GND) 14 | , .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(GLB) 15 | , .YB(), .GLC(GLC), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(GND), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(VCC), 19 | .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(VCC), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(VCC), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(VCC), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(VCC), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(GND) 28 | , .FINDIV1(GND), .FINDIV2(VCC), .FINDIV3(GND), .FINDIV4( 29 | GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(VCC), .FBDIV1( 30 | VCC), .FBDIV2(VCC), .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5( 31 | VCC), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(VCC), .VCOSEL1(VCC), 34 | .VCOSEL2(VCC)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb16.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module pll_xtal64_wb16(POWERDOWN,CLKA,LOCK,GLA,GLB,GLC); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA, GLB, GLC; 8 | 9 | wire VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(48.000) ) Core(.CLKA(CLKA), .EXTFB(GND), 14 | .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(GLB), 15 | .YB(), .GLC(GLC), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(GND), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(GND), 19 | .OBDIV1(VCC), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(VCC), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(VCC), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC) 28 | , .FINDIV1(VCC), .FINDIV2(GND), .FINDIV3(VCC), .FINDIV4( 29 | GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1( 30 | GND), .FBDIV2(GND), .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5( 31 | GND), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(VCC), .VCOSEL1(VCC), 34 | .VCOSEL2(GND)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb20.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module pll_xtal64_wb20(POWERDOWN,CLKA,LOCK,GLA,GLB,GLC); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA, GLB, GLC; 8 | 9 | wire VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(240.000) ) Core(.CLKA(CLKA), .EXTFB(GND) 14 | , .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(GLB) 15 | , .YB(), .GLC(GLC), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(GND), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(VCC), 19 | .OBDIV1(VCC), .OBDIV2(GND), .OBDIV3(VCC), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(VCC), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(VCC), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(VCC), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC) 28 | , .FINDIV1(VCC), .FINDIV2(GND), .FINDIV3(VCC), .FINDIV4( 29 | GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1( 30 | GND), .FBDIV2(VCC), .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5( 31 | VCC), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(VCC), .VCOSEL1(VCC), 34 | .VCOSEL2(VCC)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb24.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module pll_xtal64_wb24(POWERDOWN,CLKA,LOCK,GLA,GLB,GLC); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA, GLB, GLC; 8 | 9 | wire VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(48.000) ) Core(.CLKA(CLKA), .EXTFB(GND), 14 | .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(GLB), 15 | .YB(), .GLC(GLC), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(GND), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(VCC), 19 | .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(VCC), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(VCC), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC) 28 | , .FINDIV1(VCC), .FINDIV2(GND), .FINDIV3(VCC), .FINDIV4( 29 | GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1( 30 | GND), .FBDIV2(GND), .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5( 31 | GND), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(VCC), .VCOSEL1(VCC), 34 | .VCOSEL2(GND)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb30.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module pll_xtal64_wb30(POWERDOWN,CLKA,LOCK,GLA,GLB,GLC); 6 | input POWERDOWN, CLKA; 7 | output LOCK, GLA, GLB, GLC; 8 | 9 | wire VCC, GND; 10 | 11 | VCC VCC_1_net(.Y(VCC)); 12 | GND GND_1_net(.Y(GND)); 13 | PLL #( .VCOFREQUENCY(240.000) ) Core(.CLKA(CLKA), .EXTFB(GND) 14 | , .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(GLB) 15 | , .YB(), .GLC(GLC), .YC(), .OADIV0(GND), .OADIV1(GND), 16 | .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), 17 | .OAMUX1(GND), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND), 18 | .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(VCC), 19 | .OBDIV1(VCC), .OBDIV2(VCC), .OBDIV3(GND), .OBDIV4(GND), 20 | .OBMUX0(GND), .OBMUX1(VCC), .OBMUX2(GND), .DLYYB0(GND), 21 | .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), 22 | .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND) 23 | , .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(VCC), 24 | .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(VCC), 25 | .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), 26 | .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), 27 | .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC) 28 | , .FINDIV1(VCC), .FINDIV2(GND), .FINDIV3(VCC), .FINDIV4( 29 | GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1( 30 | GND), .FBDIV2(VCC), .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5( 31 | VCC), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2( 32 | GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1( 33 | GND), .XDLYSEL(VCC), .VCOSEL0(VCC), .VCOSEL1(VCC), 34 | .VCOSEL2(VCC)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/backend/rtl/verilog/reset_buffer.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: 8.6 8.6.0.34 3 | 4 | 5 | module reset_buffer(GL,CLK); 6 | output GL; 7 | input CLK; 8 | 9 | wire CLKP, GND; 10 | 11 | GND GND_1_net(.Y(GND)); 12 | PLLINT pllint1(.A(CLK), .Y(CLKP)); 13 | CLKDLY Inst1(.CLK(CLKP), .GL(GL), .DLYGL0(GND), .DLYGL1(GND), 14 | .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/bench/verilog/include/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/flashrom/README: -------------------------------------------------------------------------------- 1 | This is a Wishbone wrapper for the Actel user flash ROM (UFR) found on its 2 | FPGAs. This flash ROM cannot be inferred and must be explicitly instantiated. 3 | The instantiated module devboard_flashrom should be in the 4 | backend/actel/rtl/verilog path, and was generated with Actel's smartgen. 5 | 6 | See the user flashrom handbook from Actel for further information on the UFR: 7 | http://www.actel.com/documents/LPD_FlashROM_HBs.pdf 8 | 9 | This document from Actel says that "the access time is 10 ns for a device 10 | supporting commercial specifications", and the Wishbone interface asserts 11 | wb_ack after 2 cycles, allowing even a 200MHz wishbone bus to access the module 12 | in time, however after PAR, timing reports a maximum access frequency of 14MHz, 13 | so do more testing before relying on this module. 14 | 15 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/flashrom/flashrom.v: -------------------------------------------------------------------------------- 1 | // Wrapper for Actel flash ROM 2 | // 2 cycles from request to ACK 3 | 4 | module flashrom( 5 | wb_clk, 6 | wb_rst, 7 | wb_adr_i, 8 | wb_cyc_i, 9 | wb_stb_i, 10 | 11 | wb_ack_o, 12 | wb_dat_o, 13 | wb_err_o, 14 | wb_rty_o); 15 | 16 | 17 | input wb_clk; 18 | input wb_rst; 19 | input [6:0] wb_adr_i; 20 | input wb_cyc_i; 21 | input wb_stb_i; 22 | 23 | output wb_ack_o; 24 | output reg [7:0] wb_dat_o; 25 | output wb_err_o; 26 | output wb_rty_o; 27 | 28 | 29 | reg [3:0] ack_shr; 30 | reg [6:0] addr; 31 | wire [7:0] dat; 32 | reg [7:0] dat_r; 33 | 34 | wire wb_access; 35 | 36 | assign wb_access = wb_cyc_i & wb_stb_i; 37 | 38 | always @(posedge wb_clk) 39 | if (wb_rst) 40 | ack_shr <= 0; 41 | else if (wb_access & !(|ack_shr)) 42 | ack_shr[0] <= 1'b1; 43 | else 44 | ack_shr <= {ack_shr[2:0],1'b0}; 45 | 46 | assign wb_ack_o = ack_shr[3]; 47 | 48 | always @(posedge wb_clk) 49 | if (wb_access & !(|ack_shr)) 50 | addr <= wb_adr_i; 51 | 52 | orpsoc_flashROM orpsoc_flashROM0 53 | ( 54 | .CLK(wb_clk), 55 | .ADDR(addr), 56 | .DOUT(dat) 57 | ); 58 | 59 | always @(posedge wb_clk) 60 | dat_r <= dat; 61 | 62 | always @(posedge wb_clk) 63 | wb_dat_o <= dat_r; 64 | 65 | assign wb_err_o = 0; 66 | assign wb_rty_o = 0; 67 | 68 | endmodule // flashrom 69 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- 1 | GPIO RTL 2 | 3 | This is a simple GPIO implementation. It is variable width, however widths of 4 | multiples of 8 are advised. The first width/8 bytes control are for 5 | reading/writing to the GPIO registers, the second set of width/8 bytes control 6 | the direction. 7 | 8 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/include/sd_defines.v: -------------------------------------------------------------------------------- 1 | //Read the documentation before changing values 2 | 3 | `define BIG_ENDIAN 4 | //`define LITLE_ENDIAN 5 | 6 | //`define SIM 7 | `define SYN 8 | 9 | `define SDC_IRQ_ENABLE 10 | 11 | `define ACTEL 12 | 13 | //`define CUSTOM 14 | //`define ALTERA 15 | //`define XLINX 16 | //`define SIMULATOR 17 | 18 | `define RESEND_MAX_CNT 3 19 | 20 | //MAX 255 BD 21 | //BD size/4 22 | 23 | `ifdef ACTEL 24 | `define BD_WIDTH 5 25 | `define BD_SIZE 32 26 | `define RAM_MEM_WIDTH_16 27 | `define RAM_MEM_WIDTH 16 28 | 29 | `endif 30 | 31 | //`ifdef CUSTOM 32 | // `define NR_O_BD_4 33 | // `define BD_WIDTH 5 34 | // `define BD_SIZE 32 35 | // `define RAM_MEM_WIDTH_32 36 | // `define RAM_MEM_WIDTH 32 37 | //`endif 38 | 39 | 40 | 41 | `ifdef SYN 42 | `define RESET_CLK_DIV 0 43 | `define MEM_OFFSET 4 44 | `endif 45 | 46 | `ifdef SIM 47 | `define RESET_CLK_DIV 0 48 | `define MEM_OFFSET 4 49 | `endif 50 | 51 | //SD-Clock Defines --------- 52 | //Use bus clock or a seperate clock 53 | `define SDC_CLK_BUS_CLK 54 | //`define SDC_CLK_SEP 55 | 56 | // Use of internal clock divider 57 | //`define SDC_CLK_STATIC 58 | `define SDC_CLK_DYNAMIC 59 | 60 | 61 | //SD DATA-transfer defines--- 62 | `define BLOCK_SIZE 512 63 | `define SD_BUS_WIDTH_4 64 | `define SD_BUS_W 4 65 | 66 | //at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit. 67 | //Add 18 for crc, endbit and z. 68 | `define BIT_BLOCK 1044 69 | `define CRC_OFF 19 70 | `define BIT_BLOCK_REC 1024 71 | `define BIT_CRC_CYCLE 16 72 | 73 | 74 | //FIFO defines--------------- 75 | `define FIFO_RX_MEM_DEPTH 8 76 | `define FIFO_RX_MEM_ADR_SIZE 4 77 | 78 | `define FIFO_TX_MEM_DEPTH 8 79 | `define FIFO_TX_MEM_ADR_SIZE 4 80 | //--------------------------- 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_constants_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// usbConstants_h.v 3 | /////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef usbConstants_h_vdefined 6 | `else 7 | `define usbConstants_h_vdefined 8 | 9 | //PIDTypes 10 | `define OUT 4'h1 11 | `define IN 4'h9 12 | `define SOF 4'h5 13 | `define SETUP 4'hd 14 | `define DATA0 4'h3 15 | `define DATA1 4'hb 16 | `define ACK 4'h2 17 | `define NAK 4'ha 18 | `define STALL 4'he 19 | `define PREAMBLE 4'hc 20 | 21 | 22 | //PIDGroups 23 | `define SPECIAL 2'b00 24 | `define TOKEN 2'b01 25 | `define HANDSHAKE 2'b10 26 | `define DATA 2'b11 27 | 28 | // start of packet SyncByte 29 | `define SYNC_BYTE 8'h80 30 | 31 | `endif //usbConstants_h_vdefined 32 | 33 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_wishbonebus_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // wishBoneBus_h.v 3 | ////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef wishBoneBus_h_vdefined 6 | `else 7 | `define wishBoneBus_h_vdefined 8 | 9 | //memoryMap 10 | `define HCREG_BASE 8'h00 11 | `define HCREG_BASE_PLUS_0X10 8'h10 12 | `define HOST_RX_FIFO_BASE 8'h20 13 | `define HOST_TX_FIFO_BASE 8'h30 14 | `define SCREG_BASE 8'h40 15 | `define SCREG_BASE_PLUS_0X10 8'h50 16 | `define EP0_RX_FIFO_BASE 8'h60 17 | `define EP0_TX_FIFO_BASE 8'h70 18 | `define EP1_RX_FIFO_BASE 8'h80 19 | `define EP1_TX_FIFO_BASE 8'h90 20 | `define EP2_RX_FIFO_BASE 8'ha0 21 | `define EP2_TX_FIFO_BASE 8'hb0 22 | `define EP3_RX_FIFO_BASE 8'hc0 23 | `define EP3_TX_FIFO_BASE 8'hd0 24 | `define HOST_SLAVE_CONTROL_BASE 8'he0 25 | `define ADDRESS_DECODE_MASK 8'hf0 26 | 27 | //FifoAddresses 28 | `define FIFO_DATA_REG 3'b000 29 | `define FIFO_STATUS_REG 3'b001 30 | `define FIFO_DATA_COUNT_MSB 3'b010 31 | `define FIFO_DATA_COUNT_LSB 3'b011 32 | `define FIFO_CONTROL_REG 3'b100 33 | 34 | `endif //wishBoneBus_h_vdefined 35 | 36 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_clock_divider.v: -------------------------------------------------------------------------------- 1 | `include "sd_defines.v"//nononw 2 | module sd_clock_divider ( 3 | input wire CLK, 4 | input [7:0] DIVIDER, 5 | input wire RST, 6 | output SD_CLK 7 | ); 8 | 9 | reg [7:0] ClockDiv; 10 | reg SD_CLK_O; 11 | `ifdef SYN 12 | `ifdef ACTEL 13 | CLKINT CLKA 14 | (.A (SD_CLK_O), 15 | .Y (SD_CLK) 16 | ); 17 | `else 18 | 19 | assign SD_CLK = SDC_CLK_O; 20 | 21 | `endif 22 | 23 | `endif 24 | 25 | `ifdef SIM 26 | assign SD_CLK = SD_CLK_O; 27 | `endif 28 | 29 | always @ (posedge CLK or posedge RST) 30 | begin 31 | if (RST) begin 32 | ClockDiv <=8'b0000_0000; 33 | SD_CLK_O <= 0; 34 | end 35 | else if (ClockDiv == DIVIDER )begin 36 | ClockDiv <= 0; 37 | SD_CLK_O <= ~SD_CLK_O; 38 | end else begin 39 | ClockDiv <= ClockDiv + 1; 40 | SD_CLK_O <= SD_CLK_O; 41 | end 42 | 43 | end 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_crc_16.v: -------------------------------------------------------------------------------- 1 | // ========================================================================== 2 | // CRC Generation Unit - Linear Feedback Shift Register implementation 3 | // (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL 4 | // https://www.ghsi.de/CRC/index.php? 5 | 6 | // https://www.ghsi.de/CRC/index.php? 7 | // ========================================================================= 8 | module sd_crc_16(BITVAL, Enable, CLK, RST, CRC); 9 | input BITVAL;// Next input bit 10 | input Enable; 11 | input CLK; // Current bit valid (Clock) 12 | input RST; // Init CRC value 13 | output reg [15:0] CRC; // Current output CRC value 14 | 15 | 16 | // We need output registers 17 | wire inv; 18 | 19 | assign inv = BITVAL ^ CRC[15]; // XOR required? 20 | 21 | always @(posedge CLK or posedge RST) begin 22 | if (RST) begin 23 | CRC = 0; 24 | 25 | end 26 | else begin 27 | if (Enable==1) begin 28 | CRC[15] = CRC[14]; 29 | CRC[14] = CRC[13]; 30 | CRC[13] = CRC[12]; 31 | CRC[12] = CRC[11] ^ inv; 32 | CRC[11] = CRC[10]; 33 | CRC[10] = CRC[9]; 34 | CRC[9] = CRC[8]; 35 | CRC[8] = CRC[7]; 36 | CRC[7] = CRC[6]; 37 | CRC[6] = CRC[5]; 38 | CRC[5] = CRC[4] ^ inv; 39 | CRC[4] = CRC[3]; 40 | CRC[3] = CRC[2]; 41 | CRC[2] = CRC[1]; 42 | CRC[1] = CRC[0]; 43 | CRC[0] = inv; 44 | end 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_crc_7.v: -------------------------------------------------------------------------------- 1 | module sd_crc_7(BITVAL, Enable, CLK, RST, CRC); 2 | input BITVAL;// Next input bit 3 | input Enable; 4 | input CLK; // Current bit valid (Clock) 5 | input RST; // Init CRC value 6 | output [6:0] CRC; // Current output CRC value 7 | 8 | reg [6:0] CRC; 9 | // We need output registers 10 | wire inv; 11 | 12 | assign inv = BITVAL ^ CRC[6]; // XOR required? 13 | 14 | 15 | always @(posedge CLK or posedge RST) begin 16 | if (RST) begin 17 | CRC = 0; 18 | 19 | end 20 | else begin 21 | if (Enable==1) begin 22 | CRC[6] = CRC[5]; 23 | CRC[5] = CRC[4]; 24 | CRC[4] = CRC[3]; 25 | CRC[3] = CRC[2] ^ inv; 26 | CRC[2] = CRC[1]; 27 | CRC[1] = CRC[0]; 28 | CRC[0] = inv; 29 | end 30 | end 31 | end 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/burst_length_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME burst_length_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 3 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd3 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/cke_delay_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME cke_delay_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | `define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 15 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | // set 23 | //`define CNT_SET 24 | `define CNT_SET_VALUE `CNT_LENGTH'h0 25 | 26 | // wrap around creates shorter cycle than maximum length 27 | //`define CNT_WRAP 28 | `define CNT_WRAP_VALUE `CNT_LENGTH'h6200 29 | 30 | // clock enable 31 | `define CNT_CE 32 | 33 | // q_next as an output 34 | //`define CNT_QNEXT 35 | 36 | // q=0 as an output 37 | //`define CNT_Z 38 | 39 | // q_next=0 as a registered output 40 | //`define CNT_ZQ 41 | 42 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ctrl_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME ctrl_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | //`define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | `define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 5 16 | 17 | // clear 18 | `define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'h1f 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/delay.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module delay (d, q, clk, rst); 3 | 4 | parameter width = 4; 5 | parameter depth = 3; 6 | 7 | input [width-1:0] d; 8 | output [width-1:0] q; 9 | input clk; 10 | input rst; 11 | 12 | reg [width-1:0] dffs [1:depth]; 13 | 14 | integer i; 15 | 16 | always @ (posedge clk or posedge rst) 17 | if (rst) 18 | for ( i=1; i <= depth; i=i+1) 19 | dffs[i] <= {width{1'b0}}; 20 | else 21 | begin 22 | dffs[1] <= d; 23 | for ( i=2; i <= depth; i=i+1 ) 24 | dffs[i] <= dffs[i-1]; 25 | end 26 | 27 | assign q = dffs[depth]; 28 | 29 | endmodule //delay 30 | 31 | 32 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_adr_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME fifo_adr_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | //`define CNT_TYPE_BINARY 6 | `define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | `define CNT_Q 11 | // for gray type counter optional binary output 12 | `define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 5 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | // set 23 | //`define CNT_SET 24 | `define CNT_SET_VALUE `CNT_LENGTH'h0 25 | 26 | // wrap around creates shorter cycle than maximum length 27 | //`define CNT_WRAP 28 | `define CNT_WRAP_VALUE `CNT_LENGTH'h9 29 | 30 | // clock enable 31 | `define CNT_CE 32 | 33 | // q_next as an output 34 | //`define CNT_QNEXT 35 | 36 | // q=0 as an output 37 | //`define CNT_Z 38 | 39 | // q_next=0 as a registered output 40 | //`define CNT_ZQ 41 | 42 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/inc_adr.v: -------------------------------------------------------------------------------- 1 | module inc_adr 2 | ( 3 | input [3:0] adr_i, 4 | input [2:0] cti_i, 5 | input [1:0] bte_i, 6 | input init, 7 | input inc, 8 | output reg [3:0] adr_o, 9 | output reg done, 10 | input clk, 11 | input rst 12 | ); 13 | 14 | reg init_i; 15 | 16 | reg [1:0] bte; 17 | reg [3:0] cnt; 18 | 19 | // delay init one clock cycle to be able to read from mem 20 | always @ (posedge clk or posedge rst) 21 | if (rst) 22 | init_i <= 1'b0; 23 | else 24 | init_i <= init; 25 | 26 | // bte 27 | always @ (posedge clk or posedge rst) 28 | if (rst) 29 | bte <= 2'b00; 30 | else 31 | if (init_i) 32 | bte <= bte_i; 33 | 34 | // adr_o 35 | always @ (posedge clk or posedge rst) 36 | if (rst) 37 | adr_o <= 4'd0; 38 | else 39 | if (init_i) 40 | adr_o <= adr_i; 41 | else 42 | if (inc) 43 | case (bte) 44 | 2'b01: adr_o <= {adr_o[3:2], adr_o[1:0] + 2'd1}; 45 | 2'b10: adr_o <= {adr_o[3], adr_o[2:0] + 3'd1}; 46 | default: adr_o <= adr_o + 4'd1; 47 | endcase // case (bte) 48 | 49 | // done 50 | always @ (posedge clk or posedge rst) 51 | if (rst) 52 | {done,cnt} <= {1'b0,4'd0}; 53 | else 54 | if (init_i) 55 | begin 56 | done <= ({bte_i,cti_i} == {2'b00,3'b000}); 57 | case (bte_i) 58 | 2'b01: cnt <= 4'd12; 59 | 2'b10: cnt <= 4'd8; 60 | 2'b11: cnt <= 4'd0; 61 | default: cnt <= adr_i; 62 | endcase 63 | end 64 | else 65 | if (inc) 66 | {done,cnt} <= cnt + 4'd1; 67 | 68 | endmodule // inc_adr 69 | 70 | 71 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/latency_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME latency_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 4 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd3 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/pre_delay_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME pre_delay_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 2 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd2 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME ref_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | //`define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | `define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 10 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'h250 30 | 31 | // clock enable 32 | //`define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_delay_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME ref_delay_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 6 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd12 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/orpsoc/673f53248125fc6ff7414bb7360c9f61237308f8/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v: -------------------------------------------------------------------------------- 1 | // true dual port RAM, sync 2 | 3 | `ifdef ACTEL 4 | `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/ 5 | `endif 6 | module vfifo_dual_port_ram_dc_sw 7 | ( 8 | d_a, 9 | adr_a, 10 | we_a, 11 | clk_a, 12 | q_b, 13 | adr_b, 14 | clk_b 15 | ); 16 | parameter DATA_WIDTH = 32; 17 | parameter ADDR_WIDTH = 8; 18 | input [(DATA_WIDTH-1):0] d_a; 19 | input [(ADDR_WIDTH-1):0] adr_a; 20 | input [(ADDR_WIDTH-1):0] adr_b; 21 | input we_a; 22 | output [(DATA_WIDTH-1):0] q_b; 23 | input clk_a, clk_b; 24 | reg [(ADDR_WIDTH-1):0] adr_b_reg; 25 | reg [DATA_WIDTH-1:0] ram [(1< $@ 9 | 10 | %.bin: %.elf 11 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 12 | 13 | clean: 14 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 15 | 16 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | 7 | %.dis: %.elf 8 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 9 | 10 | %.bin: %.elf 11 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 12 | 13 | clean: 14 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 15 | 16 | -------------------------------------------------------------------------------- /boards/actel/ordb1a3pe1500/syn/synplify/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/bench/verilog/include/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/flashrom/README: -------------------------------------------------------------------------------- 1 | This is a Wishbone wrapper for the Actel user flash ROM (UFR) found on its 2 | FPGAs. This flash ROM cannot be inferred and must be explicitly instantiated. 3 | The instantiated module devboard_flashrom should be in the 4 | backend/actel/rtl/verilog path, and was generated with Actel's smartgen. 5 | 6 | See the user flashrom handbook from Actel for further information on the UFR: 7 | http://www.actel.com/documents/LPD_FlashROM_HBs.pdf 8 | 9 | This document from Actel says that "the access time is 10 ns for a device 10 | supporting commercial specifications", and the Wishbone interface asserts 11 | wb_ack after 2 cycles, allowing even a 200MHz wishbone bus to access the module 12 | in time, however after PAR, timing reports a maximum access frequency of 14MHz, 13 | so do more testing before relying on this module. 14 | 15 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/flashrom/flashrom.v: -------------------------------------------------------------------------------- 1 | // Wrapper for Actel flash ROM 2 | // 2 cycles from request to ACK 3 | 4 | module flashrom( 5 | wb_clk, 6 | wb_rst, 7 | wb_adr_i, 8 | wb_cyc_i, 9 | wb_stb_i, 10 | 11 | wb_ack_o, 12 | wb_dat_o, 13 | wb_err_o, 14 | wb_rty_o); 15 | 16 | 17 | input wb_clk; 18 | input wb_rst; 19 | input [6:0] wb_adr_i; 20 | input wb_cyc_i; 21 | input wb_stb_i; 22 | 23 | output wb_ack_o; 24 | output reg [7:0] wb_dat_o; 25 | output wb_err_o; 26 | output wb_rty_o; 27 | 28 | 29 | reg [3:0] ack_shr; 30 | reg [6:0] addr; 31 | wire [7:0] dat; 32 | reg [7:0] dat_r; 33 | 34 | wire wb_access; 35 | 36 | assign wb_access = wb_cyc_i & wb_stb_i; 37 | 38 | always @(posedge wb_clk) 39 | if (wb_rst) 40 | ack_shr <= 0; 41 | else if (wb_access & !(|ack_shr)) 42 | ack_shr[0] <= 1'b1; 43 | else 44 | ack_shr <= {ack_shr[2:0],1'b0}; 45 | 46 | assign wb_ack_o = ack_shr[3]; 47 | 48 | always @(posedge wb_clk) 49 | if (wb_access & !(|ack_shr)) 50 | addr <= wb_adr_i; 51 | 52 | orpsoc_flashROM orpsoc_flashROM0 53 | ( 54 | .CLK(wb_clk), 55 | .ADDR(addr), 56 | .DOUT(dat) 57 | ); 58 | 59 | always @(posedge wb_clk) 60 | dat_r <= dat; 61 | 62 | always @(posedge wb_clk) 63 | wb_dat_o <= dat_r; 64 | 65 | assign wb_err_o = 0; 66 | assign wb_rty_o = 0; 67 | 68 | endmodule // flashrom 69 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- 1 | GPIO RTL 2 | 3 | This is a simple GPIO implementation. It is variable width, however widths of 4 | multiples of 8 are advised. The first width/8 bytes control are for 5 | reading/writing to the GPIO registers, the second set of width/8 bytes control 6 | the direction. 7 | 8 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/include/sd_defines.v: -------------------------------------------------------------------------------- 1 | //Read the documentation before changing values 2 | 3 | `define BIG_ENDIAN 4 | //`define LITLE_ENDIAN 5 | 6 | //`define SIM 7 | `define SYN 8 | 9 | `define SDC_IRQ_ENABLE 10 | 11 | `define ACTEL 12 | 13 | //`define CUSTOM 14 | //`define ALTERA 15 | //`define XLINX 16 | //`define SIMULATOR 17 | 18 | `define RESEND_MAX_CNT 3 19 | 20 | //MAX 255 BD 21 | //BD size/4 22 | 23 | `ifdef ACTEL 24 | `define BD_WIDTH 5 25 | `define BD_SIZE 32 26 | `define RAM_MEM_WIDTH_16 27 | `define RAM_MEM_WIDTH 16 28 | 29 | `endif 30 | 31 | //`ifdef CUSTOM 32 | // `define NR_O_BD_4 33 | // `define BD_WIDTH 5 34 | // `define BD_SIZE 32 35 | // `define RAM_MEM_WIDTH_32 36 | // `define RAM_MEM_WIDTH 32 37 | //`endif 38 | 39 | 40 | 41 | `ifdef SYN 42 | `define RESET_CLK_DIV 0 43 | `define MEM_OFFSET 4 44 | `endif 45 | 46 | `ifdef SIM 47 | `define RESET_CLK_DIV 0 48 | `define MEM_OFFSET 4 49 | `endif 50 | 51 | //SD-Clock Defines --------- 52 | //Use bus clock or a seperate clock 53 | `define SDC_CLK_BUS_CLK 54 | //`define SDC_CLK_SEP 55 | 56 | // Use of internal clock divider 57 | //`define SDC_CLK_STATIC 58 | `define SDC_CLK_DYNAMIC 59 | 60 | 61 | //SD DATA-transfer defines--- 62 | `define BLOCK_SIZE 512 63 | `define SD_BUS_WIDTH_4 64 | `define SD_BUS_W 4 65 | 66 | //at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit. 67 | //Add 18 for crc, endbit and z. 68 | `define BIT_BLOCK 1044 69 | `define CRC_OFF 19 70 | `define BIT_BLOCK_REC 1024 71 | `define BIT_CRC_CYCLE 16 72 | 73 | 74 | //FIFO defines--------------- 75 | `define FIFO_RX_MEM_DEPTH 8 76 | `define FIFO_RX_MEM_ADR_SIZE 4 77 | 78 | `define FIFO_TX_MEM_DEPTH 8 79 | `define FIFO_TX_MEM_ADR_SIZE 4 80 | //--------------------------- 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/include/usbhostslave_constants_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// usbConstants_h.v 3 | /////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef usbConstants_h_vdefined 6 | `else 7 | `define usbConstants_h_vdefined 8 | 9 | //PIDTypes 10 | `define OUT 4'h1 11 | `define IN 4'h9 12 | `define SOF 4'h5 13 | `define SETUP 4'hd 14 | `define DATA0 4'h3 15 | `define DATA1 4'hb 16 | `define ACK 4'h2 17 | `define NAK 4'ha 18 | `define STALL 4'he 19 | `define PREAMBLE 4'hc 20 | 21 | 22 | //PIDGroups 23 | `define SPECIAL 2'b00 24 | `define TOKEN 2'b01 25 | `define HANDSHAKE 2'b10 26 | `define DATA 2'b11 27 | 28 | // start of packet SyncByte 29 | `define SYNC_BYTE 8'h80 30 | 31 | `endif //usbConstants_h_vdefined 32 | 33 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/include/usbhostslave_wishbonebus_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // wishBoneBus_h.v 3 | ////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef wishBoneBus_h_vdefined 6 | `else 7 | `define wishBoneBus_h_vdefined 8 | 9 | //memoryMap 10 | `define HCREG_BASE 8'h00 11 | `define HCREG_BASE_PLUS_0X10 8'h10 12 | `define HOST_RX_FIFO_BASE 8'h20 13 | `define HOST_TX_FIFO_BASE 8'h30 14 | `define SCREG_BASE 8'h40 15 | `define SCREG_BASE_PLUS_0X10 8'h50 16 | `define EP0_RX_FIFO_BASE 8'h60 17 | `define EP0_TX_FIFO_BASE 8'h70 18 | `define EP1_RX_FIFO_BASE 8'h80 19 | `define EP1_TX_FIFO_BASE 8'h90 20 | `define EP2_RX_FIFO_BASE 8'ha0 21 | `define EP2_TX_FIFO_BASE 8'hb0 22 | `define EP3_RX_FIFO_BASE 8'hc0 23 | `define EP3_TX_FIFO_BASE 8'hd0 24 | `define HOST_SLAVE_CONTROL_BASE 8'he0 25 | `define ADDRESS_DECODE_MASK 8'hf0 26 | 27 | //FifoAddresses 28 | `define FIFO_DATA_REG 3'b000 29 | `define FIFO_STATUS_REG 3'b001 30 | `define FIFO_DATA_COUNT_MSB 3'b010 31 | `define FIFO_DATA_COUNT_LSB 3'b011 32 | `define FIFO_CONTROL_REG 3'b100 33 | 34 | `endif //wishBoneBus_h_vdefined 35 | 36 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/sdc_controller/sd_clock_divider.v: -------------------------------------------------------------------------------- 1 | `include "sd_defines.v"//nononw 2 | module sd_clock_divider ( 3 | input wire CLK, 4 | input [7:0] DIVIDER, 5 | input wire RST, 6 | output SD_CLK 7 | ); 8 | 9 | reg [7:0] ClockDiv; 10 | reg SD_CLK_O; 11 | `ifdef SYN 12 | `ifdef ACTEL 13 | CLKINT CLKA 14 | (.A (SD_CLK_O), 15 | .Y (SD_CLK) 16 | ); 17 | `else 18 | 19 | assign SD_CLK = SDC_CLK_O; 20 | 21 | `endif 22 | 23 | `endif 24 | 25 | `ifdef SIM 26 | assign SD_CLK = SD_CLK_O; 27 | `endif 28 | 29 | always @ (posedge CLK or posedge RST) 30 | begin 31 | if (RST) begin 32 | ClockDiv <=8'b0000_0000; 33 | SD_CLK_O <= 0; 34 | end 35 | else if (ClockDiv == DIVIDER )begin 36 | ClockDiv <= 0; 37 | SD_CLK_O <= ~SD_CLK_O; 38 | end else begin 39 | ClockDiv <= ClockDiv + 1; 40 | SD_CLK_O <= SD_CLK_O; 41 | end 42 | 43 | end 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/sdc_controller/sd_crc_16.v: -------------------------------------------------------------------------------- 1 | // ========================================================================== 2 | // CRC Generation Unit - Linear Feedback Shift Register implementation 3 | // (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL 4 | // https://www.ghsi.de/CRC/index.php? 5 | 6 | // https://www.ghsi.de/CRC/index.php? 7 | // ========================================================================= 8 | module sd_crc_16(BITVAL, Enable, CLK, RST, CRC); 9 | input BITVAL;// Next input bit 10 | input Enable; 11 | input CLK; // Current bit valid (Clock) 12 | input RST; // Init CRC value 13 | output reg [15:0] CRC; // Current output CRC value 14 | 15 | 16 | // We need output registers 17 | wire inv; 18 | 19 | assign inv = BITVAL ^ CRC[15]; // XOR required? 20 | 21 | always @(posedge CLK or posedge RST) begin 22 | if (RST) begin 23 | CRC = 0; 24 | 25 | end 26 | else begin 27 | if (Enable==1) begin 28 | CRC[15] = CRC[14]; 29 | CRC[14] = CRC[13]; 30 | CRC[13] = CRC[12]; 31 | CRC[12] = CRC[11] ^ inv; 32 | CRC[11] = CRC[10]; 33 | CRC[10] = CRC[9]; 34 | CRC[9] = CRC[8]; 35 | CRC[8] = CRC[7]; 36 | CRC[7] = CRC[6]; 37 | CRC[6] = CRC[5]; 38 | CRC[5] = CRC[4] ^ inv; 39 | CRC[4] = CRC[3]; 40 | CRC[3] = CRC[2]; 41 | CRC[2] = CRC[1]; 42 | CRC[1] = CRC[0]; 43 | CRC[0] = inv; 44 | end 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/sdc_controller/sd_crc_7.v: -------------------------------------------------------------------------------- 1 | module sd_crc_7(BITVAL, Enable, CLK, RST, CRC); 2 | input BITVAL;// Next input bit 3 | input Enable; 4 | input CLK; // Current bit valid (Clock) 5 | input RST; // Init CRC value 6 | output [6:0] CRC; // Current output CRC value 7 | 8 | reg [6:0] CRC; 9 | // We need output registers 10 | wire inv; 11 | 12 | assign inv = BITVAL ^ CRC[6]; // XOR required? 13 | 14 | 15 | always @(posedge CLK or posedge RST) begin 16 | if (RST) begin 17 | CRC = 0; 18 | 19 | end 20 | else begin 21 | if (Enable==1) begin 22 | CRC[6] = CRC[5]; 23 | CRC[5] = CRC[4]; 24 | CRC[4] = CRC[3]; 25 | CRC[3] = CRC[2] ^ inv; 26 | CRC[2] = CRC[1]; 27 | CRC[1] = CRC[0]; 28 | CRC[0] = inv; 29 | end 30 | end 31 | end 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/rtl/verilog/vga_lcd/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sw/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | # Expecting BOARD_SW_ROOT already set to indicate how far below directory we're 3 | # in the board's software root path is. 4 | 5 | # Root from the board's sw/ path 6 | PROJ_ROOT=../../../.. 7 | 8 | # Figure out actual path the common software directory 9 | SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw 10 | 11 | # Set the BOARD to be the path within the board/ path of the project that goes 12 | # to this project. 13 | BOARD=actel/ordb1a3pe1500 14 | 15 | # Set RTL_VERILOG_INCLUDE_DIR so software 16 | RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include 17 | 18 | # Set the processor capability flags 19 | #MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float 20 | MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float 21 | export MARCH_FLAGS 22 | 23 | # Finally include the main software include file 24 | 25 | include $(SW_ROOT)/Makefile.inc 26 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sw/bootrom/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for bootROM Verilog 2 | # We will do it by building the main one, and applying our local board's 3 | # settings. 4 | # To rebuild after board.h is changed, a clean must be done first. 5 | 6 | # Set the path to our board's root directory 7 | BOARD_SW_ROOT=.. 8 | 9 | include $(BOARD_SW_ROOT)/Makefile.inc 10 | 11 | all: bootrom.v 12 | 13 | # Copy the one build in the root software path to here. 14 | bootrom.v: $(SW_ROOT)/bootrom/bootrom.v 15 | $(Q)cp -v $< . 16 | 17 | # Export BOARD so the Make script in the root software path knows we're to 18 | # use our board.h file, not theirs. 19 | export BOARD 20 | 21 | $(SW_ROOT)/bootrom/bootrom.v: 22 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v 23 | 24 | clean: 25 | $(Q)rm -f *.o *.bin *.hex *.in *.dis *.v 26 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean 27 | 28 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sw/drivers/usbhostslave/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../.. 3 | 4 | # Declare sources for the driver before we include everything 5 | COMPILE_SRCS=usbhostslave-host.c usbhostslave-slave.c 6 | 7 | include $(BOARD_SW_ROOT)/Makefile.inc 8 | 9 | clean: 10 | $(Q)rm -f *.a *.o 11 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sw/drivers/usbhostslave/usbhostslave-host.c: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * 4 | * USB usbhostslave core host functions 5 | * 6 | * Julius Baxter, julius@opencores.org 7 | * 8 | */ 9 | 10 | #include "cpu-utils.h" 11 | #include "board.h" 12 | #include "usbhostslave-host.h" 13 | 14 | const int USBHOSTSLAVE_HOST_CORE_ADR[2] = { USB0_BASE, USB1_BASE }; 15 | 16 | // ------------------------ usbInit ----------------------------- 17 | char usb_host_init(int core) 18 | { 19 | volatile int i; 20 | 21 | // Reset the thing 22 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HOST_SLAVE_MODE) = 0x2; 23 | 24 | // Wait 10 USB cycles ( this should be plenty) 25 | for (i = 0; i < 8; i++) ; 26 | 27 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_INTERRUPT_MASK_REG) = 0x00; // Disable interrupts 28 | 29 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_INTERRUPT_STATUS_REG) = 0xff; // Clear interrupt statuses 30 | 31 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_TX_LINE_CONTROL_REG) = 0x00; // low speed normal 32 | 33 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_TX_SOF_ENABLE_REG) = 0x00; // No SOF 34 | 35 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HOST_SLAVE_MODE) = 0x01; // Set core to HOST mode 36 | 37 | // Reset RX FIFO buffer 38 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_RX_FIFO_CONTROL_REG) = 39 | 0xff; 40 | // Reset TX FIFO buffer 41 | REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_TX_FIFO_CONTROL_REG) = 42 | 0xff; 43 | 44 | // Return version number reg 45 | return REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HOST_SLAVE_VERSION); 46 | 47 | } 48 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sw/tests/i2c_master_slave/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | 7 | %.dis: %.elf 8 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 9 | 10 | %.bin: %.elf 11 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 12 | 13 | clean: 14 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 15 | 16 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/sw/tests/usbhostslave/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | 7 | %.dis: %.elf 8 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 9 | 10 | %.bin: %.elf 11 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 12 | 13 | clean: 14 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 15 | 16 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/sdc/JTAG_DEBUG.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name "tck_pad_i" -period 100.000ns [get_ports {tck_pad_i}] 2 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/sdc/common.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | 10 | # Ignore timing on the reset input 11 | set_false_path -through [get_nets {rst_n_pad_i}] 12 | 13 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/tcl/GENERIC_JTAG_TAP_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_A14 -to tck_pad_i 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tck_pad_i 3 | set_location_assignment PIN_C14 -to tdo_pad_o 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tdo_pad_o 5 | set_location_assignment PIN_B16 -to tdi_pad_i 6 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tdi_pad_i 7 | set_location_assignment PIN_C15 -to tms_pad_i 8 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tms_pad_i 9 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/tcl/GPIO0_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_A15 -to gpio0_io[0] 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0] 3 | set_location_assignment PIN_A13 -to gpio0_io[1] 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1] 5 | set_location_assignment PIN_B13 -to gpio0_io[2] 6 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2] 7 | set_location_assignment PIN_A11 -to gpio0_io[3] 8 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3] 9 | set_location_assignment PIN_D1 -to gpio0_io[4] 10 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4] 11 | set_location_assignment PIN_F3 -to gpio0_io[5] 12 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5] 13 | set_location_assignment PIN_B1 -to gpio0_io[6] 14 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6] 15 | set_location_assignment PIN_L3 -to gpio0_io[7] 16 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7] 17 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/tcl/UART0_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_C16 -to uart0_srx_pad_i 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i 3 | set_location_assignment PIN_D15 -to uart0_stx_pad_o 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o 5 | -------------------------------------------------------------------------------- /boards/altera/de0_nano/syn/quartus/tcl/common_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_J15 -to rst_n_pad_i 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i 3 | set_location_assignment PIN_R8 -to sys_clk_pad_i 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i 5 | -------------------------------------------------------------------------------- /boards/altera/de2_115/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /boards/altera/de2_115/bench/verilog/include/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/flashrom/README: -------------------------------------------------------------------------------- 1 | This is a Wishbone wrapper for the Actel user flash ROM (UFR) found on its 2 | FPGAs. This flash ROM cannot be inferred and must be explicitly instantiated. 3 | The instantiated module devboard_flashrom should be in the 4 | backend/actel/rtl/verilog path, and was generated with Actel's smartgen. 5 | 6 | See the user flashrom handbook from Actel for further information on the UFR: 7 | http://www.actel.com/documents/LPD_FlashROM_HBs.pdf 8 | 9 | This document from Actel says that "the access time is 10 ns for a device 10 | supporting commercial specifications", and the Wishbone interface asserts 11 | wb_ack after 2 cycles, allowing even a 200MHz wishbone bus to access the module 12 | in time, however after PAR, timing reports a maximum access frequency of 14MHz, 13 | so do more testing before relying on this module. 14 | 15 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/flashrom/flashrom.v: -------------------------------------------------------------------------------- 1 | // Wrapper for Actel flash ROM 2 | // 2 cycles from request to ACK 3 | 4 | module flashrom( 5 | wb_clk, 6 | wb_rst, 7 | wb_adr_i, 8 | wb_cyc_i, 9 | wb_stb_i, 10 | 11 | wb_ack_o, 12 | wb_dat_o, 13 | wb_err_o, 14 | wb_rty_o); 15 | 16 | 17 | input wb_clk; 18 | input wb_rst; 19 | input [6:0] wb_adr_i; 20 | input wb_cyc_i; 21 | input wb_stb_i; 22 | 23 | output wb_ack_o; 24 | output reg [7:0] wb_dat_o; 25 | output wb_err_o; 26 | output wb_rty_o; 27 | 28 | 29 | reg [3:0] ack_shr; 30 | reg [6:0] addr; 31 | wire [7:0] dat; 32 | reg [7:0] dat_r; 33 | 34 | wire wb_access; 35 | 36 | assign wb_access = wb_cyc_i & wb_stb_i; 37 | 38 | always @(posedge wb_clk) 39 | if (wb_rst) 40 | ack_shr <= 0; 41 | else if (wb_access & !(|ack_shr)) 42 | ack_shr[0] <= 1'b1; 43 | else 44 | ack_shr <= {ack_shr[2:0],1'b0}; 45 | 46 | assign wb_ack_o = ack_shr[3]; 47 | 48 | always @(posedge wb_clk) 49 | if (wb_access & !(|ack_shr)) 50 | addr <= wb_adr_i; 51 | 52 | orpsoc_flashROM orpsoc_flashROM0 53 | ( 54 | .CLK(wb_clk), 55 | .ADDR(addr), 56 | .DOUT(dat) 57 | ); 58 | 59 | always @(posedge wb_clk) 60 | dat_r <= dat; 61 | 62 | always @(posedge wb_clk) 63 | wb_dat_o <= dat_r; 64 | 65 | assign wb_err_o = 0; 66 | assign wb_rty_o = 0; 67 | 68 | endmodule // flashrom 69 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- 1 | GPIO RTL 2 | 3 | This is a simple GPIO implementation. It is variable width, however widths of 4 | multiples of 8 are advised. The first width/8 bytes control are for 5 | reading/writing to the GPIO registers, the second set of width/8 bytes control 6 | the direction. 7 | 8 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/include/sd_defines.v: -------------------------------------------------------------------------------- 1 | //Read the documentation before changing values 2 | 3 | `define BIG_ENDIAN 4 | //`define LITLE_ENDIAN 5 | 6 | //`define SIM 7 | `define SYN 8 | 9 | `define SDC_IRQ_ENABLE 10 | 11 | `define ACTEL 12 | 13 | //`define CUSTOM 14 | //`define ALTERA 15 | //`define XLINX 16 | //`define SIMULATOR 17 | 18 | `define RESEND_MAX_CNT 3 19 | 20 | //MAX 255 BD 21 | //BD size/4 22 | 23 | `ifdef ACTEL 24 | `define BD_WIDTH 5 25 | `define BD_SIZE 32 26 | `define RAM_MEM_WIDTH_16 27 | `define RAM_MEM_WIDTH 16 28 | 29 | `endif 30 | 31 | //`ifdef CUSTOM 32 | // `define NR_O_BD_4 33 | // `define BD_WIDTH 5 34 | // `define BD_SIZE 32 35 | // `define RAM_MEM_WIDTH_32 36 | // `define RAM_MEM_WIDTH 32 37 | //`endif 38 | 39 | 40 | 41 | `ifdef SYN 42 | `define RESET_CLK_DIV 0 43 | `define MEM_OFFSET 4 44 | `endif 45 | 46 | `ifdef SIM 47 | `define RESET_CLK_DIV 0 48 | `define MEM_OFFSET 4 49 | `endif 50 | 51 | //SD-Clock Defines --------- 52 | //Use bus clock or a seperate clock 53 | `define SDC_CLK_BUS_CLK 54 | //`define SDC_CLK_SEP 55 | 56 | // Use of internal clock divider 57 | //`define SDC_CLK_STATIC 58 | `define SDC_CLK_DYNAMIC 59 | 60 | 61 | //SD DATA-transfer defines--- 62 | `define BLOCK_SIZE 512 63 | `define SD_BUS_WIDTH_4 64 | `define SD_BUS_W 4 65 | 66 | //at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit. 67 | //Add 18 for crc, endbit and z. 68 | `define BIT_BLOCK 1044 69 | `define CRC_OFF 19 70 | `define BIT_BLOCK_REC 1024 71 | `define BIT_CRC_CYCLE 16 72 | 73 | 74 | //FIFO defines--------------- 75 | `define FIFO_RX_MEM_DEPTH 8 76 | `define FIFO_RX_MEM_ADR_SIZE 4 77 | 78 | `define FIFO_TX_MEM_DEPTH 8 79 | `define FIFO_TX_MEM_ADR_SIZE 4 80 | //--------------------------- 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/include/usbhostslave_constants_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// usbConstants_h.v 3 | /////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef usbConstants_h_vdefined 6 | `else 7 | `define usbConstants_h_vdefined 8 | 9 | //PIDTypes 10 | `define OUT 4'h1 11 | `define IN 4'h9 12 | `define SOF 4'h5 13 | `define SETUP 4'hd 14 | `define DATA0 4'h3 15 | `define DATA1 4'hb 16 | `define ACK 4'h2 17 | `define NAK 4'ha 18 | `define STALL 4'he 19 | `define PREAMBLE 4'hc 20 | 21 | 22 | //PIDGroups 23 | `define SPECIAL 2'b00 24 | `define TOKEN 2'b01 25 | `define HANDSHAKE 2'b10 26 | `define DATA 2'b11 27 | 28 | // start of packet SyncByte 29 | `define SYNC_BYTE 8'h80 30 | 31 | `endif //usbConstants_h_vdefined 32 | 33 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/include/usbhostslave_wishbonebus_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // wishBoneBus_h.v 3 | ////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef wishBoneBus_h_vdefined 6 | `else 7 | `define wishBoneBus_h_vdefined 8 | 9 | //memoryMap 10 | `define HCREG_BASE 8'h00 11 | `define HCREG_BASE_PLUS_0X10 8'h10 12 | `define HOST_RX_FIFO_BASE 8'h20 13 | `define HOST_TX_FIFO_BASE 8'h30 14 | `define SCREG_BASE 8'h40 15 | `define SCREG_BASE_PLUS_0X10 8'h50 16 | `define EP0_RX_FIFO_BASE 8'h60 17 | `define EP0_TX_FIFO_BASE 8'h70 18 | `define EP1_RX_FIFO_BASE 8'h80 19 | `define EP1_TX_FIFO_BASE 8'h90 20 | `define EP2_RX_FIFO_BASE 8'ha0 21 | `define EP2_TX_FIFO_BASE 8'hb0 22 | `define EP3_RX_FIFO_BASE 8'hc0 23 | `define EP3_TX_FIFO_BASE 8'hd0 24 | `define HOST_SLAVE_CONTROL_BASE 8'he0 25 | `define ADDRESS_DECODE_MASK 8'hf0 26 | 27 | //FifoAddresses 28 | `define FIFO_DATA_REG 3'b000 29 | `define FIFO_STATUS_REG 3'b001 30 | `define FIFO_DATA_COUNT_MSB 3'b010 31 | `define FIFO_DATA_COUNT_LSB 3'b011 32 | `define FIFO_CONTROL_REG 3'b100 33 | 34 | `endif //wishBoneBus_h_vdefined 35 | 36 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/sdc_controller/sd_clock_divider.v: -------------------------------------------------------------------------------- 1 | `include "sd_defines.v"//nononw 2 | module sd_clock_divider ( 3 | input wire CLK, 4 | input [7:0] DIVIDER, 5 | input wire RST, 6 | output SD_CLK 7 | ); 8 | 9 | reg [7:0] ClockDiv; 10 | reg SD_CLK_O; 11 | `ifdef SYN 12 | `ifdef ACTEL 13 | CLKINT CLKA 14 | (.A (SD_CLK_O), 15 | .Y (SD_CLK) 16 | ); 17 | `else 18 | 19 | assign SD_CLK = SDC_CLK_O; 20 | 21 | `endif 22 | 23 | `endif 24 | 25 | `ifdef SIM 26 | assign SD_CLK = SD_CLK_O; 27 | `endif 28 | 29 | always @ (posedge CLK or posedge RST) 30 | begin 31 | if (RST) begin 32 | ClockDiv <=8'b0000_0000; 33 | SD_CLK_O <= 0; 34 | end 35 | else if (ClockDiv == DIVIDER )begin 36 | ClockDiv <= 0; 37 | SD_CLK_O <= ~SD_CLK_O; 38 | end else begin 39 | ClockDiv <= ClockDiv + 1; 40 | SD_CLK_O <= SD_CLK_O; 41 | end 42 | 43 | end 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/sdc_controller/sd_crc_16.v: -------------------------------------------------------------------------------- 1 | // ========================================================================== 2 | // CRC Generation Unit - Linear Feedback Shift Register implementation 3 | // (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL 4 | // https://www.ghsi.de/CRC/index.php? 5 | 6 | // https://www.ghsi.de/CRC/index.php? 7 | // ========================================================================= 8 | module sd_crc_16(BITVAL, Enable, CLK, RST, CRC); 9 | input BITVAL;// Next input bit 10 | input Enable; 11 | input CLK; // Current bit valid (Clock) 12 | input RST; // Init CRC value 13 | output reg [15:0] CRC; // Current output CRC value 14 | 15 | 16 | // We need output registers 17 | wire inv; 18 | 19 | assign inv = BITVAL ^ CRC[15]; // XOR required? 20 | 21 | always @(posedge CLK or posedge RST) begin 22 | if (RST) begin 23 | CRC = 0; 24 | 25 | end 26 | else begin 27 | if (Enable==1) begin 28 | CRC[15] = CRC[14]; 29 | CRC[14] = CRC[13]; 30 | CRC[13] = CRC[12]; 31 | CRC[12] = CRC[11] ^ inv; 32 | CRC[11] = CRC[10]; 33 | CRC[10] = CRC[9]; 34 | CRC[9] = CRC[8]; 35 | CRC[8] = CRC[7]; 36 | CRC[7] = CRC[6]; 37 | CRC[6] = CRC[5]; 38 | CRC[5] = CRC[4] ^ inv; 39 | CRC[4] = CRC[3]; 40 | CRC[3] = CRC[2]; 41 | CRC[2] = CRC[1]; 42 | CRC[1] = CRC[0]; 43 | CRC[0] = inv; 44 | end 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/sdc_controller/sd_crc_7.v: -------------------------------------------------------------------------------- 1 | module sd_crc_7(BITVAL, Enable, CLK, RST, CRC); 2 | input BITVAL;// Next input bit 3 | input Enable; 4 | input CLK; // Current bit valid (Clock) 5 | input RST; // Init CRC value 6 | output [6:0] CRC; // Current output CRC value 7 | 8 | reg [6:0] CRC; 9 | // We need output registers 10 | wire inv; 11 | 12 | assign inv = BITVAL ^ CRC[6]; // XOR required? 13 | 14 | 15 | always @(posedge CLK or posedge RST) begin 16 | if (RST) begin 17 | CRC = 0; 18 | 19 | end 20 | else begin 21 | if (Enable==1) begin 22 | CRC[6] = CRC[5]; 23 | CRC[5] = CRC[4]; 24 | CRC[4] = CRC[3]; 25 | CRC[3] = CRC[2] ^ inv; 26 | CRC[2] = CRC[1]; 27 | CRC[1] = CRC[0]; 28 | CRC[0] = inv; 29 | end 30 | end 31 | end 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/burst_length_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME burst_length_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 3 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd3 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/cke_delay_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME cke_delay_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | `define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 15 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | // set 23 | //`define CNT_SET 24 | `define CNT_SET_VALUE `CNT_LENGTH'h0 25 | 26 | // wrap around creates shorter cycle than maximum length 27 | //`define CNT_WRAP 28 | `define CNT_WRAP_VALUE `CNT_LENGTH'h6200 29 | 30 | // clock enable 31 | `define CNT_CE 32 | 33 | // q_next as an output 34 | //`define CNT_QNEXT 35 | 36 | // q=0 as an output 37 | //`define CNT_Z 38 | 39 | // q_next=0 as a registered output 40 | //`define CNT_ZQ 41 | 42 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ctrl_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME ctrl_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | //`define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | `define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 5 16 | 17 | // clear 18 | `define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'h1f 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/delay.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module delay (d, q, clk, rst); 3 | 4 | parameter width = 4; 5 | parameter depth = 3; 6 | 7 | input [width-1:0] d; 8 | output [width-1:0] q; 9 | input clk; 10 | input rst; 11 | 12 | reg [width-1:0] dffs [1:depth]; 13 | 14 | integer i; 15 | 16 | always @ (posedge clk or posedge rst) 17 | if (rst) 18 | for ( i=1; i <= depth; i=i+1) 19 | dffs[i] <= {width{1'b0}}; 20 | else 21 | begin 22 | dffs[1] <= d; 23 | for ( i=2; i <= depth; i=i+1 ) 24 | dffs[i] <= dffs[i-1]; 25 | end 26 | 27 | assign q = dffs[depth]; 28 | 29 | endmodule //delay 30 | 31 | 32 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_adr_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME fifo_adr_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | //`define CNT_TYPE_BINARY 6 | `define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | `define CNT_Q 11 | // for gray type counter optional binary output 12 | `define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 5 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | // set 23 | //`define CNT_SET 24 | `define CNT_SET_VALUE `CNT_LENGTH'h0 25 | 26 | // wrap around creates shorter cycle than maximum length 27 | //`define CNT_WRAP 28 | `define CNT_WRAP_VALUE `CNT_LENGTH'h9 29 | 30 | // clock enable 31 | `define CNT_CE 32 | 33 | // q_next as an output 34 | //`define CNT_QNEXT 35 | 36 | // q=0 as an output 37 | //`define CNT_Z 38 | 39 | // q_next=0 as a registered output 40 | //`define CNT_ZQ 41 | 42 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/inc_adr.v: -------------------------------------------------------------------------------- 1 | module inc_adr 2 | ( 3 | input [3:0] adr_i, 4 | input [2:0] cti_i, 5 | input [1:0] bte_i, 6 | input init, 7 | input inc, 8 | output reg [3:0] adr_o, 9 | output reg done, 10 | input clk, 11 | input rst 12 | ); 13 | 14 | reg init_i; 15 | 16 | reg [1:0] bte; 17 | reg [3:0] cnt; 18 | 19 | // delay init one clock cycle to be able to read from mem 20 | always @ (posedge clk or posedge rst) 21 | if (rst) 22 | init_i <= 1'b0; 23 | else 24 | init_i <= init; 25 | 26 | // bte 27 | always @ (posedge clk or posedge rst) 28 | if (rst) 29 | bte <= 2'b00; 30 | else 31 | if (init_i) 32 | bte <= bte_i; 33 | 34 | // adr_o 35 | always @ (posedge clk or posedge rst) 36 | if (rst) 37 | adr_o <= 4'd0; 38 | else 39 | if (init_i) 40 | adr_o <= adr_i; 41 | else 42 | if (inc) 43 | case (bte) 44 | 2'b01: adr_o <= {adr_o[3:2], adr_o[1:0] + 2'd1}; 45 | 2'b10: adr_o <= {adr_o[3], adr_o[2:0] + 3'd1}; 46 | default: adr_o <= adr_o + 4'd1; 47 | endcase // case (bte) 48 | 49 | // done 50 | always @ (posedge clk or posedge rst) 51 | if (rst) 52 | {done,cnt} <= {1'b0,4'd0}; 53 | else 54 | if (init_i) 55 | begin 56 | done <= ({bte_i,cti_i} == {2'b00,3'b000}); 57 | case (bte_i) 58 | 2'b01: cnt <= 4'd12; 59 | 2'b10: cnt <= 4'd8; 60 | 2'b11: cnt <= 4'd0; 61 | default: cnt <= adr_i; 62 | endcase 63 | end 64 | else 65 | if (inc) 66 | {done,cnt} <= cnt + 4'd1; 67 | 68 | endmodule // inc_adr 69 | 70 | 71 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/latency_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME latency_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 4 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd3 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/pre_delay_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME pre_delay_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 2 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd2 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME ref_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | //`define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | `define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 10 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'h250 30 | 31 | // clock enable 32 | //`define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_delay_counter_defines.v: -------------------------------------------------------------------------------- 1 | // module name 2 | `define CNT_MODULE_NAME ref_delay_counter 3 | 4 | // counter type = [BINARY, GRAY, LFSR] 5 | `define CNT_TYPE_BINARY 6 | //`define CNT_TYPE_GRAY 7 | //`define CNT_TYPE_LFSR 8 | 9 | // q as output 10 | //`define CNT_Q 11 | // for gray type counter optional binary output 12 | //`define CNT_Q_BIN 13 | 14 | // number of CNT bins 15 | `define CNT_LENGTH 6 16 | 17 | // clear 18 | //`define CNT_CLEAR 19 | 20 | // async reset 21 | `define CNT_RESET_VALUE `CNT_LENGTH'h0 22 | 23 | // set 24 | //`define CNT_SET 25 | `define CNT_SET_VALUE `CNT_LENGTH'h0 26 | 27 | // wrap around creates shorter cycle than maximum length 28 | `define CNT_WRAP 29 | `define CNT_WRAP_VALUE `CNT_LENGTH'd12 30 | 31 | // clock enable 32 | `define CNT_CE 33 | 34 | // q_next as an output 35 | //`define CNT_QNEXT 36 | 37 | // q=0 as an output 38 | //`define CNT_Z 39 | 40 | // q_next=0 as a registered output 41 | `define CNT_ZQ 42 | 43 | -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lgeek/orpsoc/673f53248125fc6ff7414bb7360c9f61237308f8/boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls -------------------------------------------------------------------------------- /boards/altera/de2_115/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v: -------------------------------------------------------------------------------- 1 | // true dual port RAM, sync 2 | 3 | `ifdef ACTEL 4 | `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/ 5 | `endif 6 | module vfifo_dual_port_ram_dc_sw 7 | ( 8 | d_a, 9 | adr_a, 10 | we_a, 11 | clk_a, 12 | q_b, 13 | adr_b, 14 | clk_b 15 | ); 16 | parameter DATA_WIDTH = 32; 17 | parameter ADDR_WIDTH = 8; 18 | input [(DATA_WIDTH-1):0] d_a; 19 | input [(ADDR_WIDTH-1):0] adr_a; 20 | input [(ADDR_WIDTH-1):0] adr_b; 21 | input we_a; 22 | output [(DATA_WIDTH-1):0] q_b; 23 | input clk_a, clk_b; 24 | reg [(ADDR_WIDTH-1):0] adr_b_reg; 25 | reg [DATA_WIDTH-1:0] ram [(1< $@ 9 | 10 | %.bin: %.elf 11 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 12 | 13 | clean: 14 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 15 | 16 | -------------------------------------------------------------------------------- /boards/altera/de2_115/sw/tests/usbhostslave/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | 7 | %.dis: %.elf 8 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 9 | 10 | %.bin: %.elf 11 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 12 | 13 | clean: 14 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 15 | 16 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/sdc/JTAG_DEBUG.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name "tck_pad_i" -period 100.000ns [get_ports {tck_pad_i}] 2 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/sdc/common.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | 10 | # Ignore timing on the reset input 11 | set_false_path -through [get_nets {rst_n_pad_i}] 12 | 13 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/tcl/GENERIC_JTAG_TAP_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_AF22 -to tck_pad_i ; #Dummy - JTAG[20] 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tck_pad_i 3 | set_location_assignment PIN_AD22 -to tdo_pad_o ; #Dummy - JTAG[21] 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tdo_pad_o 5 | set_location_assignment PIN_AG25 -to tdi_pad_i ; #Dummy - JTAG[22] 6 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tdi_pad_i 7 | set_location_assignment PIN_AD25 -to tms_pad_i ; #Dummy - JTAG[23] 8 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tms_pad_i 9 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/tcl/GPIO0_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_AB22 -to gpio0_io[0] 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0] 3 | set_location_assignment PIN_AC15 -to gpio0_io[1] 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1] 5 | set_location_assignment PIN_AB21 -to gpio0_io[2] 6 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2] 7 | set_location_assignment PIN_Y17 -to gpio0_io[3] 8 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3] 9 | set_location_assignment PIN_AC21 -to gpio0_io[4] 10 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4] 11 | set_location_assignment PIN_Y16 -to gpio0_io[5] 12 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5] 13 | set_location_assignment PIN_AD21 -to gpio0_io[6] 14 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6] 15 | set_location_assignment PIN_AE16 -to gpio0_io[7] 16 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7] 17 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/tcl/UART0_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_G12 -to uart0_srx_pad_i 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i 3 | set_location_assignment PIN_G9 -to uart0_stx_pad_o 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o 5 | -------------------------------------------------------------------------------- /boards/altera/de2_115/syn/quartus/tcl/common_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_M23 -to rst_n_pad_i ; #KEY[0] 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i 3 | set_location_assignment PIN_Y2 -to sys_clk_pad_i ; #CLOCK_50 4 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i 5 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/README: -------------------------------------------------------------------------------- 1 | Digilent Atlys Spartan-6 board build 2 | 3 | The building process for this board is identical to the ML501 build. 4 | See the project's main documentation in doc/ for information on the ML501 build. 5 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/bench/verilog/include/ddr2_model_preload.v: -------------------------------------------------------------------------------- 1 | // File intended to be included in the generate statement for each DDR2 part. 2 | // The following loads a vmem file, "sram.vmem" by default, into the SDRAM. 3 | 4 | // Wait until the DDR memory is initialised, and then magically 5 | // load it 6 | @(posedge dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_calib_done); 7 | //$display("%t: Loading DDR2",$time); 8 | 9 | $readmemh("sram.vmem", program_array); 10 | /* Now dish it out to the DDR2 model's memory */ 11 | for(ram_ptr = 0 ; ram_ptr < 4096 ; ram_ptr = ram_ptr + 1) 12 | begin 13 | 14 | // Construct the burst line 15 | program_word_ptr = ram_ptr*4; 16 | tmp_program_word = program_array[program_word_ptr]; 17 | ddr2_ram_mem_line[31:0] = tmp_program_word; 18 | 19 | program_word_ptr = program_word_ptr + 1; 20 | tmp_program_word = program_array[program_word_ptr]; 21 | ddr2_ram_mem_line[63:32] = tmp_program_word; 22 | 23 | 24 | program_word_ptr = program_word_ptr + 1; 25 | tmp_program_word = program_array[program_word_ptr]; 26 | ddr2_ram_mem_line[95:64] = tmp_program_word; 27 | 28 | 29 | program_word_ptr = program_word_ptr + 1; 30 | tmp_program_word = program_array[program_word_ptr]; 31 | ddr2_ram_mem_line[127:96] = tmp_program_word; 32 | 33 | // Put this assembled line into the RAM using its memory writing TASK 34 | if (C3_MEM_ADDR_ORDER == "BANK_ROW_COLUMN") begin 35 | u_mem0.memory_write(2'b00,ram_ptr[19:7], 36 | {ram_ptr[6:0],3'b000},ddr2_ram_mem_line); 37 | end else if (C3_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin 38 | u_mem0.memory_write(ram_ptr[8:7],{2'b00,ram_ptr[19:9]}, 39 | {ram_ptr[6:0],3'b000},ddr2_ram_mem_line); 40 | 41 | end 42 | //$display("Writing 0x%h, ramline=%d",ddr2_ram_mem_line, ram_ptr); 43 | 44 | end // for (ram_ptr = 0 ; ram_ptr < ... 45 | $display("(%t) * DDR2 RAM preloaded",$time); 46 | 47 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/bench/verilog/include/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps -------------------------------------------------------------------------------- /boards/xilinx/atlys/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- 1 | GPIO RTL 2 | 3 | This is a simple GPIO implementation. It is variable width, however widths of 4 | multiples of 8 are advised. The first width/8 bytes control are for 5 | reading/writing to the GPIO registers, the second set of width/8 bytes control 6 | the direction. 7 | 8 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v: -------------------------------------------------------------------------------- 1 | parameter C3_P0_MASK_SIZE = 16; 2 | parameter C3_P0_DATA_PORT_SIZE = 128; 3 | parameter DEBUG_EN = 0; 4 | parameter C3_MEMCLK_PERIOD = 3750; 5 | parameter C3_CALIB_SOFT_IP = "TRUE"; 6 | parameter C3_SIMULATION = "FALSE"; 7 | parameter C3_RST_ACT_LOW = 0; 8 | parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED"; 9 | parameter C3_MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; 10 | parameter C3_NUM_DQ_PINS = 16; 11 | parameter C3_MEM_ADDR_WIDTH = 13; 12 | parameter C3_MEM_BANKADDR_WIDTH = 3; 13 | 14 | // Simulation parameter defines 15 | parameter DQ_WIDTH = 16; 16 | parameter DQS_WIDTH = 1; 17 | parameter DM_WIDTH = 1; 18 | parameter CLK_WIDTH = 1; 19 | parameter ROW_WIDTH = 13; 20 | parameter BANK_WIDTH = 3; 21 | parameter CKE_WIDTH = 1; 22 | parameter ODT_WIDTH = 1; 23 | 24 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README: -------------------------------------------------------------------------------- 1 | Xilinx DDR2 controller with Wishbone interface 2 | 3 | This is a Xilinx technology-dependent DDR2 memory controller, based on a 4 | controller from Xilinx's memory interface generator (MIG), with a small cache 5 | memory and Wishbone wrapper. 6 | 7 | The xilinx_ddr2_wb_if.v is a 3-master arbiter for the controller. 8 | The xilinx_ddr2_if.v is the actual interface between the Wishbone bus and 9 | Xilinx MIG control interface. 10 | 11 | When synthesizing, take note of the xilinx_ddr2_if_cache module, that is a 12 | dual-port memory, with different aspects on each size, and cannot be inferred. 13 | The NGC should be in the appropriate place in the synthesis or backend 14 | directories. 15 | 16 | 17 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/sw/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | # Expecting BOARD_SW_ROOT already set to indicate how far below directory we're 3 | # in the board's software root path is. 4 | 5 | # Root from the board's sw/ path 6 | PROJ_ROOT=../../../.. 7 | 8 | # Figure out actual path the common software directory 9 | SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw 10 | 11 | # Set the BOARD_PATH to point to the root of this board build 12 | BOARD=xilinx/atlys 13 | 14 | # Set RTL_VERILOG_INCLUDE_DIR so software 15 | RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include 16 | 17 | # Set the processor capability flags 18 | MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float 19 | #MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float 20 | export MARCH_FLAGS 21 | 22 | # Finally include the main software include file 23 | 24 | include $(SW_ROOT)/Makefile.inc 25 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/sw/board/include/board.h: -------------------------------------------------------------------------------- 1 | #ifndef _BOARD_H_ 2 | #define _BOARD_H_ 3 | 4 | #define IN_CLK 50000000 // Hz 5 | 6 | // 7 | // ROM bootloader 8 | // 9 | // Uncomment the appropriate bootloader define. This will effect the bootrom.S 10 | // file, which is compiled and converted into Verilog for inclusion at 11 | // synthesis time. See bootloader/bootloader.S for details on each option. 12 | #ifndef PRELOAD_RAM 13 | #define BOOTROM_SPI_FLASH 14 | //#define BOOTROM_GOTO_RESET 15 | //#define BOOTROM_LOOP_AT_ZERO 16 | //#define BOOTROM_LOOP_IN_ROM 17 | #else 18 | #define BOOTROM_GOTO_RESET 19 | #endif 20 | 21 | // Address bootloader should start from in FLASH 22 | // Offset 0x1c0000 23 | #define BOOTROM_ADDR_BYTE2 0x1c 24 | #define BOOTROM_ADDR_BYTE1 0x00 25 | #define BOOTROM_ADDR_BYTE0 0x00 26 | // Causes SPI bootloader to loop if SPI didn't give correct size of image 27 | #define SPI_RETRY_IF_INSANE_SIZEWORD 28 | 29 | // 30 | // Defines for each core (memory map base, OR1200 interrupt line number, etc.) 31 | // 32 | #define SDRAM_BASE 0x0 33 | 34 | #define GPIO_0_BASE 0x91000000 35 | 36 | #define UART0_BASE 0x90000000 37 | #define UART0_IRQ 2 38 | #define UART0_BAUD_RATE 115200 39 | 40 | 41 | #define SPI0_BASE 0xb0000000 42 | #define SPI0_IRQ 6 43 | 44 | #define I2C_0_BASE 0xa0000000 45 | #define I2C_0_IRQ 10 46 | 47 | #define I2C_1_BASE 0xa1000000 48 | #define I2C_1_IRQ 11 49 | 50 | #define ETH0_BASE 0x92000000 51 | #define ETH0_IRQ 4 52 | 53 | #define ETH_MACADDR0 0x00 54 | #define ETH_MACADDR1 0x12 55 | #define ETH_MACADDR2 0x34 56 | #define ETH_MACADDR3 0x56 57 | #define ETH_MACADDR4 0x78 58 | #define ETH_MACADDR5 0x9a 59 | 60 | // 61 | // OR1200 tick timer period define 62 | // 63 | #define TICKS_PER_SEC 100 64 | 65 | 66 | 67 | // 68 | // UART driver configuration 69 | // 70 | #define UART_NUM_CORES 1 71 | #define UART_BASE_ADDRESSES_CSV UART0_BASE 72 | #define UART_BAUD_RATES_CSV UART0_BAUD_RATE 73 | 74 | #endif 75 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/sw/bootrom/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for bootROM Verilog 2 | # We will do it by building the main one, and applying our local board's 3 | # settings. 4 | # To rebuild after board.h is changed, a clean must be done first. 5 | 6 | # Set the path to our board's root directory 7 | BOARD_SW_ROOT=.. 8 | 9 | include $(BOARD_SW_ROOT)/Makefile.inc 10 | 11 | all: bootrom.v 12 | 13 | # Copy the one build in the root software path to here. 14 | bootrom.v: $(SW_ROOT)/bootrom/bootrom.v 15 | $(Q)cp -v $< . 16 | 17 | # Export BOARD so the Make script in the root software path knows we're to 18 | # use our board.h file, not theirs. 19 | export BOARD 20 | 21 | $(SW_ROOT)/bootrom/bootrom.v: 22 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v 23 | 24 | clean: 25 | $(Q)rm -f *.o *.bin *.hex *.in *.dis *.v 26 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean 27 | 28 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/syn/xst/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET designentry = VHDL 2 | SET BusFormat = BusFormatAngleBracketNotRipped 3 | SET devicefamily = spartan6 4 | SET device = xc6slx45 5 | SET package = csg324 6 | SET speedgrade = -2 7 | SET FlowVendor = Foundation_ISE 8 | SET VerilogSim = True 9 | SET VHDLSim = True 10 | -------------------------------------------------------------------------------- /boards/xilinx/atlys/syn/xst/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/README: -------------------------------------------------------------------------------- 1 | Xilinx ML501 board build 2 | 3 | See the project's main documentation in doc/ for information on this build. 4 | 5 | 6 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/bench/verilog/include/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps -------------------------------------------------------------------------------- /boards/xilinx/ml501/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- 1 | GPIO RTL 2 | 3 | This is a simple GPIO implementation. It is variable width, however widths of 4 | multiples of 8 are advised. The first width/8 bytes control are for 5 | reading/writing to the GPIO registers, the second set of width/8 bytes control 6 | the direction. 7 | 8 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/README: -------------------------------------------------------------------------------- 1 | Xilinx DDR2 controller with Wishbone interface 2 | 3 | This is a Xilinx technology-dependent DDR2 memory controller, based on a 4 | controller from Xilinx's memory interface generator (MIG), with a small cache 5 | memory and Wishbone wrapper. 6 | 7 | The xilinx_ddr2_wb_if.v is a 3-master arbiter for the controller. 8 | The xilinx_ddr2_if.v is the actual interface between the Wishbone bus and 9 | Xilinx MIG control interface. 10 | 11 | When synthesizing, take note of the xilinx_ddr2_if_cache module, that is a 12 | dual-port memory, with different aspects on each size, and cannot be inferred. 13 | The NGC should be in the appropriate place in the synthesis or backend 14 | directories. 15 | 16 | Wishbone B3-compliant bursting is yet to be implemented. 17 | 18 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/sw/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | # Expecting BOARD_SW_ROOT already set to indicate how far below directory we're 3 | # in the board's software root path is. 4 | 5 | # Root from the board's sw/ path 6 | PROJ_ROOT=../../../.. 7 | 8 | # Figure out actual path the common software directory 9 | SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw 10 | 11 | # Set the BOARD_PATH to point to the root of this board build 12 | BOARD=xilinx/ml501 13 | 14 | # Set RTL_VERILOG_INCLUDE_DIR so software 15 | RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include 16 | 17 | # Set the processor capability flags 18 | MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float 19 | #MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float 20 | export MARCH_FLAGS 21 | 22 | # Finally include the main software include file 23 | 24 | include $(SW_ROOT)/Makefile.inc 25 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/sw/bootrom/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for bootROM Verilog 2 | # We will do it by building the main one, and applying our local board's 3 | # settings. 4 | # To rebuild after board.h is changed, a clean must be done first. 5 | 6 | # Set the path to our board's root directory 7 | BOARD_SW_ROOT=.. 8 | 9 | include $(BOARD_SW_ROOT)/Makefile.inc 10 | 11 | all: bootrom.v 12 | 13 | # Copy the one build in the root software path to here. 14 | bootrom.v: $(SW_ROOT)/bootrom/bootrom.v 15 | $(Q)cp -v $< . 16 | 17 | # Export BOARD so the Make script in the root software path knows we're to 18 | # use our board.h file, not theirs. 19 | export BOARD 20 | 21 | $(SW_ROOT)/bootrom/bootrom.v: 22 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v 23 | 24 | clean: 25 | $(Q)rm -f *.o *.bin *.hex *.in *.dis *.v 26 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean 27 | 28 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | %.dis: %.elf 7 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 8 | 9 | %.bin: %.elf 10 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 11 | 12 | clean: 13 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 14 | 15 | -------------------------------------------------------------------------------- /boards/xilinx/ml501/syn/xst/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/README: -------------------------------------------------------------------------------- 1 | Xilinx Spartan 3A DSP board build 2 | 3 | See the project's main documentation in doc/ for information on this build. 4 | 5 | 6 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/bench/verilog/include/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- 1 | GPIO RTL 2 | 3 | This is a simple GPIO implementation. It is variable width, however widths of 4 | multiples of 8 are advised. The first width/8 bytes control are for 5 | reading/writing to the GPIO registers, the second set of width/8 bytes control 6 | the direction. 7 | 8 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/sw/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | # Expecting BOARD_SW_ROOT already set to indicate how far below directory we're 3 | # in the board's software root path is. 4 | 5 | # Root from the board's sw/ path 6 | PROJ_ROOT=../../../.. 7 | 8 | # Figure out actual path the common software directory 9 | SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw 10 | 11 | # Set the BOARD_PATH to point to the root of this board build 12 | BOARD=xilinx/s3adsp1800 13 | 14 | # Set RTL_VERILOG_INCLUDE_DIR so software 15 | RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include 16 | 17 | # Set the processor capability flags 18 | MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float 19 | #MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float 20 | export MARCH_FLAGS 21 | 22 | # Finally include the main software include file 23 | 24 | include $(SW_ROOT)/Makefile.inc 25 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/sw/bootrom/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for bootROM Verilog 2 | # We will do it by building the main one, and applying our local board's 3 | # settings. 4 | # To rebuild after board.h is changed, a clean must be done first. 5 | 6 | # Set the path to our board's root directory 7 | BOARD_SW_ROOT=.. 8 | 9 | include $(BOARD_SW_ROOT)/Makefile.inc 10 | 11 | all: bootrom.v 12 | 13 | # Copy the one build in the root software path to here. 14 | bootrom.v: $(SW_ROOT)/bootrom/bootrom.v 15 | $(Q)cp -v $< . 16 | 17 | # Export BOARD so the Make script in the root software path knows we're to 18 | # use our board.h file, not theirs. 19 | export BOARD 20 | 21 | $(SW_ROOT)/bootrom/bootrom.v: 22 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v 23 | 24 | clean: 25 | $(Q)rm -f *.o *.bin *.hex *.in *.dis *.v 26 | $(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean 27 | 28 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/sw/bootrom/bootrom.v: -------------------------------------------------------------------------------- 1 | 0 : wb_dat_o <= 32'h18000000; 2 | 1 : wb_dat_o <= 32'h18800000; 3 | 2 : wb_dat_o <= 32'ha8840100; 4 | 3 : wb_dat_o <= 32'h44002000; 5 | 4 : wb_dat_o <= 32'h15000000; 6 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | %.dis: %.elf 7 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 8 | 9 | %.bin: %.elf 10 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 11 | 12 | clean: 13 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 14 | 15 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Set the path to our board's root directory 2 | BOARD_SW_ROOT=../../.. 3 | 4 | include $(BOARD_SW_ROOT)/Makefile.inc 5 | 6 | %.dis: %.elf 7 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 8 | 9 | %.bin: %.elf 10 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 11 | 12 | clean: 13 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 14 | 15 | -------------------------------------------------------------------------------- /boards/xilinx/s3adsp1800/syn/xst/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /doc/Makefile.am: -------------------------------------------------------------------------------- 1 | ## Process this file with automake to produce Makefile.in 2 | 3 | MAINTAINERCLEANFILES = Makefile.in 4 | info_TEXINFOS = orpsoc.texi 5 | 6 | -------------------------------------------------------------------------------- /doc/config.texi: -------------------------------------------------------------------------------- 1 | @c ORPSoC MANUAL configuration file. 2 | @c 3 | @c Copyright (C) 2008 Embecosm Limited 4 | @c 5 | @c Contributor Jeremy Bennett 6 | @c Contributor Julius Baxter 7 | @c 8 | @c This file is part of the OpenRISC Reference Platform SoC. 9 | @c 10 | @c This program is free software; you can redistribute it and/or modify it 11 | @c under the terms of the GNU General Public License as published by the Free 12 | @c Software Foundation; either version 3 of the License, or (at your option) 13 | @c any later version. 14 | @c 15 | @c This program is distributed in the hope that it will be useful, but WITHOUT 16 | @c ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 | @c FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 | @c more details. 19 | @c 20 | @c You should have received a copy of the GNU General Public License along 21 | @c with this program. If not, see . 22 | @c 23 | @c ---------------------------------------------------------------------- 24 | @c Parameters 25 | @c 26 | @c Paragraph indentation 27 | @paragraphindent 0 28 | @c ---------------------------------------------------------------------- 29 | @c STRINGS: 30 | @c 31 | @c Name of ORPSoC 32 | @set ORPSOC ORPSoC 33 | -------------------------------------------------------------------------------- /doc/configure.in: -------------------------------------------------------------------------------- 1 | dnl Process this file with autoconf to produce a configure script. 2 | 3 | AC_PREREQ(2.59) 4 | 5 | AC_INIT([orpsoc_doc], [0.1], [openrisc@opencores.org]) 6 | 7 | AM_INIT_AUTOMAKE([1.9 foreign]) 8 | 9 | AC_CONFIG_FILES([Makefile]) 10 | 11 | # Generate the output 12 | AC_COPYRIGHT([Copyright (C) 2010 OpenCores 13 | 14 | Contributor Julius Baxter 15 | 16 | This file is part of OpenRISC Reference Platform SoC. 17 | 18 | This program is free software; you can redistribute it and/or modify it 19 | under the terms of the GNU General Public License as published by the Free 20 | Software Foundation; either version 3 of the License, or (at your option) 21 | any later version. 22 | 23 | This program is distributed in the hope that it will be useful, but WITHOUT 24 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 25 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 26 | more details. 27 | 28 | You should have received a copy of the GNU General Public License along 29 | with this program. If not, see .]) 30 | 31 | 32 | AC_OUTPUT -------------------------------------------------------------------------------- /rtl/verilog/clkgen/README: -------------------------------------------------------------------------------- 1 | Clock and reset generation module 2 | 3 | This module should be used as the main reset and clock generation module. It 4 | should have the asynchronous resets and unbuffered clock lines coming in, and 5 | depending on defines in the main design file, generate the appropriate clocks 6 | and clock-synchronous resets. 7 | 8 | Currently Actel and Xilinx technlogies are supported. It is unclear if the way 9 | it is handling clock-configurations depending on boards is ideal, potentially 10 | it could become very cluttered if further board support is added and this would 11 | need to be looked at. 12 | 13 | The technology-dependent modules (PLLs, buffers) instantiated here should be 14 | located under the backend/vendor/rtl paths. 15 | 16 | As mentioned previously, it is unclear if this is the best way to manage the 17 | task of clock and reset generation, particularly if further specialised clock 18 | domains wish to be added, however there is some benefit in that it is all 19 | managed in one place and with the strict rules that all clocks and resets come 20 | to this module to be generated. -------------------------------------------------------------------------------- /rtl/verilog/ethmac/README: -------------------------------------------------------------------------------- 1 | 10/100MBps ethernet MAC core 2 | 3 | This is based on the core from OpenCores, but heavily modified and improved to provide better bus usage, and buffer configurability. 4 | 5 | See the include file, include/ethmac_defines.v for options. 6 | -------------------------------------------------------------------------------- /rtl/verilog/i2c_master_slave/README: -------------------------------------------------------------------------------- 1 | i2c master and slave 2 | 3 | This core is based on the i2c master by Richard Herveille from OpenCores.org, 4 | with added slave capability by ORSoC. See the driver software in sw/drivers 5 | for details on use of the core. 6 | 7 | -------------------------------------------------------------------------------- /rtl/verilog/include/usbhostslave_constants_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// usbConstants_h.v 3 | /////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef usbConstants_h_vdefined 6 | `else 7 | `define usbConstants_h_vdefined 8 | 9 | //PIDTypes 10 | `define OUT 4'h1 11 | `define IN 4'h9 12 | `define SOF 4'h5 13 | `define SETUP 4'hd 14 | `define DATA0 4'h3 15 | `define DATA1 4'hb 16 | `define ACK 4'h2 17 | `define NAK 4'ha 18 | `define STALL 4'he 19 | `define PREAMBLE 4'hc 20 | 21 | 22 | //PIDGroups 23 | `define SPECIAL 2'b00 24 | `define TOKEN 2'b01 25 | `define HANDSHAKE 2'b10 26 | `define DATA 2'b11 27 | 28 | // start of packet SyncByte 29 | `define SYNC_BYTE 8'h80 30 | 31 | `endif //usbConstants_h_vdefined 32 | 33 | -------------------------------------------------------------------------------- /rtl/verilog/include/usbhostslave_wishbonebus_h.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // wishBoneBus_h.v 3 | ////////////////////////////////////////////////////////////////////// 4 | 5 | `ifdef wishBoneBus_h_vdefined 6 | `else 7 | `define wishBoneBus_h_vdefined 8 | 9 | //memoryMap 10 | `define HCREG_BASE 8'h00 11 | `define HCREG_BASE_PLUS_0X10 8'h10 12 | `define HOST_RX_FIFO_BASE 8'h20 13 | `define HOST_TX_FIFO_BASE 8'h30 14 | `define SCREG_BASE 8'h40 15 | `define SCREG_BASE_PLUS_0X10 8'h50 16 | `define EP0_RX_FIFO_BASE 8'h60 17 | `define EP0_TX_FIFO_BASE 8'h70 18 | `define EP1_RX_FIFO_BASE 8'h80 19 | `define EP1_TX_FIFO_BASE 8'h90 20 | `define EP2_RX_FIFO_BASE 8'ha0 21 | `define EP2_TX_FIFO_BASE 8'hb0 22 | `define EP3_RX_FIFO_BASE 8'hc0 23 | `define EP3_TX_FIFO_BASE 8'hd0 24 | `define HOST_SLAVE_CONTROL_BASE 8'he0 25 | `define ADDRESS_DECODE_MASK 8'hf0 26 | 27 | //FifoAddresses 28 | `define FIFO_DATA_REG 3'b000 29 | `define FIFO_STATUS_REG 3'b001 30 | `define FIFO_DATA_COUNT_MSB 3'b010 31 | `define FIFO_DATA_COUNT_LSB 3'b011 32 | `define FIFO_CONTROL_REG 3'b100 33 | 34 | `endif //wishBoneBus_h_vdefined 35 | 36 | -------------------------------------------------------------------------------- /rtl/verilog/intgen/intgen.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Interrupt generation module 4 | * 5 | * A counter is loaded with a value over the Wishbone bus interface, which then 6 | * counts down and issues an interrupt when the value is 1 7 | * 8 | * 9 | * Register 0 - write only - counter value 10 | * 11 | * Register 1 - read/write - interrupt status/clear 12 | * 13 | */ 14 | 15 | module intgen( 16 | clk_i, 17 | rst_i, 18 | wb_adr_i, 19 | wb_cyc_i, 20 | wb_stb_i, 21 | wb_dat_i, 22 | wb_we_i, 23 | wb_ack_o, 24 | wb_dat_o, 25 | 26 | irq_o 27 | ); 28 | 29 | 30 | input clk_i; 31 | input rst_i; 32 | 33 | input wb_adr_i; 34 | input wb_cyc_i; 35 | input wb_stb_i; 36 | input [7:0] wb_dat_i; 37 | input wb_we_i; 38 | output wb_ack_o; 39 | output [7:0] wb_dat_o; 40 | 41 | output reg irq_o; 42 | 43 | reg [7:0] counter; 44 | 45 | always @(posedge clk_i or posedge rst_i) 46 | if (rst_i) 47 | counter <= 0; 48 | else if (wb_stb_i & wb_cyc_i & wb_we_i & !wb_adr_i) 49 | // Write to adress 0 loads counter 50 | counter <= wb_dat_i; 51 | else if (|counter) 52 | counter <= counter - 1; 53 | 54 | always @(posedge clk_i or posedge rst_i) 55 | if (rst_i) 56 | irq_o <= 0; 57 | else if (wb_stb_i & wb_cyc_i & wb_we_i & wb_adr_i) 58 | // Clear on write to reg 1 59 | irq_o <= 0; 60 | else if (counter==8'd1) 61 | irq_o <= 1; 62 | 63 | assign wb_ack_o = wb_stb_i & wb_cyc_i; 64 | assign wb_dat_o = (wb_adr_i) ? {7'd0,irq_o} : counter; 65 | 66 | endmodule // intgen 67 | 68 | 69 | 70 | -------------------------------------------------------------------------------- /rtl/verilog/jtag_tap/README: -------------------------------------------------------------------------------- 1 | JTAG TAP RTL 2 | 3 | See the project's page on OpenCores for more information: 4 | http://opencores.org/project,jtag 5 | 6 | -------------------------------------------------------------------------------- /rtl/verilog/rom/README: -------------------------------------------------------------------------------- 1 | ROM module 2 | 3 | This module will act as a read-only memory with a Wishbone interface. It relies 4 | on a generated list of verilog assigns for each address requested. This included 5 | verilog file is from the sw/bootrom path. Anything building the system should 6 | also build this bootrom.v (requires compilation of assembly file with or32 7 | toolchain and parsing with custom tool in sw/utils, all done automagically by 8 | Makefile in sw/bootrom) 9 | 10 | This ROM can support Wishbone B3 bursting, but obviously then requires more 11 | logic. The `NONBLOCK_DEFINE is to accomodate those annoying coding 12 | methodologies that do all sequential assigns with a #delay, like the or1200 was. 13 | 14 | -------------------------------------------------------------------------------- /rtl/verilog/simple_spi/README: -------------------------------------------------------------------------------- 1 | "Simple SPI" SPI controller RTL 2 | 3 | http://opencores.org/project,simple_spi 4 | 5 | The core has had a variable-width slave-select register and corresponding I/O 6 | lines added. 7 | 8 | There is also optional boot-up logic, that sends a series of bus-commands upon 9 | reset, initialising, say a SPI flash chip, to read-state. This could potentially 10 | save space in any bootloader code or FSM wishing to read from an SPI-bus chip 11 | at boot time. Defparam the 'startup_state_reset' to 4'h10 to enable it, and 12 | see the RTL for more details. 13 | 14 | -------------------------------------------------------------------------------- /rtl/verilog/smii/README: -------------------------------------------------------------------------------- 1 | MII to SMII converter RTL 2 | 3 | This implements conversion between the 3-pin SMII bus and the higher-pin count MII interface for communication between a 10/100 ethernet MAC and ethernet PHY. 4 | 5 | 6 | -------------------------------------------------------------------------------- /rtl/verilog/uart16550/README: -------------------------------------------------------------------------------- 1 | UART 16550 compatible (mostly) core RTL 2 | 3 | http://opencores.org/project,uart16550 4 | 5 | The core is configured to be in 8-bit mode in this project. 6 | -------------------------------------------------------------------------------- /rtl/verilog/usbhostslave/README: -------------------------------------------------------------------------------- 1 | USB 1.1 host/slave RTL 2 | 3 | http://opencores.org/project,usbhostslave 4 | 5 | This RTL contains both usbhost and slave cores. See the top-level files, usbhost.v, usbslave.v and usbhostslave.v for the desired configuration of the core. 6 | 7 | Include files are prefixed with usbhostslave_ in the include/ directory. 8 | 9 | -------------------------------------------------------------------------------- /scripts/make/Makefile-board-definesparse.inc: -------------------------------------------------------------------------------- 1 | # Main defines file is from board include path 2 | PROJECT_VERILOG_DEFINES ?=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v 3 | 4 | # Detect technology to use for the simulation 5 | DESIGN_DEFINES ?=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g ) 6 | 7 | # Rule to look at what defines are being extracted from main file 8 | print-defines: 9 | @echo echo; echo "\t### Design defines ###"; echo; 10 | @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:" 11 | @echo $(DESIGN_DEFINES) 12 | -------------------------------------------------------------------------------- /scripts/make/Makefile-board-paths.inc: -------------------------------------------------------------------------------- 1 | # Paths to RTL and testbench directories for board ports. 2 | 3 | COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl 4 | COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog 5 | #COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl 6 | 7 | BOARD_RTL_DIR=$(BOARD_ROOT)/rtl 8 | BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog 9 | #BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl 10 | BOARD_EXT_MODULES_DIR=$(BOARD_ROOT)/modules 11 | 12 | # Only 1 include path for board builds - their own! 13 | BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include 14 | 15 | BOARD_BENCH_DIR=$(BOARD_ROOT)/bench 16 | BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog 17 | BOARD_BENCH_VERILOG_INCLUDE_DIR=$(BOARD_BENCH_VERILOG_DIR)/include 18 | 19 | COMMON_BENCH_DIR=$(PROJECT_ROOT) 20 | COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog 21 | COMMON_BENCH_VERILOG_INCLUDE_DIR=$(COMMON_BENCH_VERILOG_DIR)/include 22 | 23 | # Simulation directories 24 | SIM_DIR ?=$(BOARD_ROOT)/sim 25 | RTL_SIM_DIR=$(SIM_DIR) 26 | RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run 27 | RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin 28 | RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out 29 | 30 | # Testbench paths 31 | BOARD_BENCH_DIR=$(BOARD_ROOT)/bench 32 | BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog 33 | COMMON_BENCH_DIR=$(PROJECT_ROOT)/bench 34 | COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog 35 | 36 | #COMMON_BENCH_VHDL_DIR=$(COMMON_BENCH_DIR)/vhdl 37 | #BOARD_BENCH_VHDL_DIR=$(BOARD_BENCH_DIR)/vhdl 38 | 39 | COMMON_BENCH_SYSC_DIR=$(COMMON_BENCH_DIR)/sysc 40 | COMMON_BENCH_SYSC_SRC_DIR=$(COMMON_BENCH_SYSC_DIR)/src 41 | COMMON_BENCH_SYSC_INCLUDE_DIR=$(COMMON_BENCH_SYSC_DIR)/include 42 | 43 | 44 | # Software directories 45 | COMMON_SW_DIR=$(PROJECT_ROOT)/sw 46 | BOARD_SW_DIR=$(BOARD_ROOT)/sw 47 | 48 | # Synthesis directory for board 49 | BOARD_SYN_DIR=$(BOARD_ROOT)/syn/$(SYNTHESIS_TOOL) 50 | BOARD_SYN_RUN_DIR=$(BOARD_SYN_DIR)/run 51 | BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out 52 | -------------------------------------------------------------------------------- /scripts/make/Makefile-board-simclean.inc: -------------------------------------------------------------------------------- 1 | # Clean rules 2 | 3 | clean: clean-sim clean-sim-test-sw clean-bootrom clean-out clean-sw 4 | 5 | clean-sim: 6 | $(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo; 7 | $(Q)rm -rf *.* lib_* work transcript check-test-log orpsoc_testbench 8 | $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi 9 | 10 | clean-out: 11 | $(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.* 12 | 13 | clean-test-defines: 14 | $(Q)rm -f $(TEST_DEFINES_VLG) 15 | 16 | distclean: clean -------------------------------------------------------------------------------- /scripts/make/Makefile-board-sw.inc: -------------------------------------------------------------------------------- 1 | # 2 | # Software compile rules for boards (mainly used during simulation) 3 | # 4 | 5 | # Path for the current test 6 | # First check for a local copy of the test. If it doesn't exist then we 7 | # default to the software tests in the root directory 8 | TEST_MODULE=$(shell echo $(TEST) | cut -d "-" -f 1) 9 | BOARD_SW_TEST_DIR=$(BOARD_SW_DIR)/tests/$(TEST_MODULE)/sim 10 | COMMON_SW_TEST_DIR=$(COMMON_SW_DIR)/tests/$(TEST_MODULE)/sim 11 | # Do this by testing for the file's existence 12 | SW_TEST_DIR=$(shell if [ -e $(BOARD_SW_TEST_DIR)/$(TEST).[cS] ]; then echo $(BOARD_SW_TEST_DIR); else echo $(COMMON_SW_TEST_DIR); fi) 13 | 14 | print-test-sw-dir: 15 | @echo; echo "\tTest software is in the following path"; echo; 16 | @echo $(BOARD_SW_DIR); echo; 17 | @echo $(BOARD_SW_TEST_DIR); echo; 18 | @echo $(SW_TEST_DIR); echo; 19 | 20 | print-sw-tests: 21 | $(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib print-sw-tests 22 | $(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib print-sw-tests-subdirs 23 | 24 | 25 | include $(PROJECT_ROOT)/scripts/make/Makefile-swrules.inc 26 | 27 | # 28 | # Board-specific clean rules 29 | # 30 | 31 | clean-sw: 32 | $(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo; 33 | $(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib distclean -------------------------------------------------------------------------------- /scripts/make/Makefile-board-tops.inc: -------------------------------------------------------------------------------- 1 | # Variables holding the names and paths to top-level files 2 | 3 | # Name of testbench top 4 | RTL_TESTBENCH_TOP_NAME=$(DESIGN_NAME)_testbench 5 | 6 | # Paths to top-level files 7 | DUT_TOP_FILE=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v 8 | BENCH_TOP_FILE=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v 9 | -------------------------------------------------------------------------------- /scripts/make/Makefile-misc.inc: -------------------------------------------------------------------------------- 1 | # Miscellaneous rules 2 | 3 | # Set V=1 when calling make to enable verbose output 4 | # mainly for debugging purposes. 5 | ifeq ($(V), 1) 6 | Q= 7 | QUIET= 8 | else 9 | Q ?=@ 10 | QUIET=-quiet 11 | endif 12 | -------------------------------------------------------------------------------- /scripts/make/Makefile-rtltestrules.inc: -------------------------------------------------------------------------------- 1 | # RTL test rules 2 | 3 | 4 | print-tests: 5 | @echo; echo; echo "\t### Software tests to be run ###"; echo; 6 | @echo $(TESTS) 7 | @echo 8 | 9 | 10 | # Suffix of file to check after each test for the string 11 | TEST_OUT_FILE_SUFFIX=-general.log 12 | TEST_OK_STRING=8000000d 13 | 14 | .PHONY: rtl-test 15 | rtl-test: clean-sim-test-sw sw clean-test-defines $(TEST_DEFINES_VLG) \ 16 | $(SIMULATOR) 17 | 18 | # Run an RTL test followed by checking of generated results 19 | rtl-test-with-check: rtl-test 20 | $(Q)$(MAKE) check-test-log; \ 21 | if [ $$? -ne 0 ]; then \ 22 | echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \ 23 | else \ 24 | echo; echo "\t### "$(TEST)" test OK ###"; echo; \ 25 | fi 26 | 27 | # Do check, don't print anything out 28 | rtl-test-with-check-no-print: rtl-test check-test-log 29 | 30 | # Main RTL test loop 31 | rtl-tests: 32 | $(Q)for test in $(TESTS); do \ 33 | export TEST=$$test; \ 34 | $(MAKE) rtl-test-with-check-no-print; \ 35 | if [ $$? -ne 0 ]; then break; fi; \ 36 | echo; echo "\t### $$test test OK ###"; echo; \ 37 | done 38 | 39 | 40 | .PHONY: check-test-log 41 | check-test-log: 42 | $(Q)echo "#!/bin/bash" > $@ 43 | $(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@ 44 | $(Q)echo "check-test-log" >> $@ 45 | $(Q)chmod +x $@ 46 | $(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo; 47 | $(Q)./$@ 48 | -------------------------------------------------------------------------------- /scripts/make/Makefile-sim-definesgen.inc: -------------------------------------------------------------------------------- 1 | # A make rule that creates the test defines verilog file. 2 | 3 | 4 | # Dynamically generated verilog file defining configuration for various things 5 | # Rule actually generating this is found in definesgen.inc file. 6 | TEST_DEFINES_VLG=test-defines.v 7 | 8 | 9 | # Test defines.v file made .PHONY to force its generation every time 10 | .PHONY: $(TEST_DEFINES_VLG) 11 | $(TEST_DEFINES_VLG): 12 | $(Q)echo "\`define "$(SIM_TYPE)"_SIM" > $@ 13 | $(Q)echo "\`define SIMULATOR_"`echo $(SIMULATOR) | tr "[:lower:]" "[:upper:]"` >> $@ 14 | $(Q)echo "\`define TEST_NAME_STRING \""$(TEST)"\"" >> $@ 15 | $(Q)if [ ! -z $$VCD ]; \ 16 | then echo "\`define VCD" >> $@; \ 17 | fi 18 | $(Q)if [ ! -z $$VCD_DELAY ]; \ 19 | then echo "\`define VCD_DELAY "$$VCD_DELAY >> $@; \ 20 | fi 21 | $(Q)if [ ! -z $$VCD_DELAY_MULTIPLY ]; \ 22 | then echo "\`define VCD_DELAY_MULTIPLY "$$VCD_DELAY_MULTIPLY >> $@; \ 23 | fi 24 | $(Q)if [ ! -z $$VCD_DEPTH ]; \ 25 | then echo "\`define VCD_DEPTH "$$VCD_DEPTH >> $@; \ 26 | fi 27 | $(Q)if [ ! -z $$VCD_DELAY_INSNS ]; \ 28 | then echo "\`define VCD_DELAY_INSNS "$$VCD_DELAY_INSNS >> $@; \ 29 | fi 30 | $(Q)if [ ! -z $$END_TIME ]; \ 31 | then echo "\`define END_TIME "$$END_TIME >> $@; \ 32 | fi 33 | $(Q)if [ ! -z $$END_INSNS ]; \ 34 | then echo "\`define END_INSNS "$$END_INSNS >> $@; \ 35 | fi 36 | $(Q)if [ ! -z $$PRELOAD_RAM ]; \ 37 | then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \ 38 | fi 39 | $(Q)if [ -z $$DISABLE_PROCESSOR_LOGS ]; \ 40 | then echo "\`define PROCESSOR_MONITOR_ENABLE_LOGS" >> $@; \ 41 | fi 42 | $(Q)if [ ! -z $$VPI ]; \ 43 | then echo "\`define VPI_DEBUG" >> $@; \ 44 | fi 45 | $(Q)if [ ! -z $$SIM_QUIET ]; \ 46 | then echo "\`define SIM_QUIET" >> $@; \ 47 | fi 48 | $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done 49 | 50 | 51 | 52 | -------------------------------------------------------------------------------- /scripts/make/Makefile-simulators.inc: -------------------------------------------------------------------------------- 1 | # Various simulator commands 2 | 3 | 4 | # Icarus verilog commands 5 | ICARUS_COMPILE=iverilog 6 | ICARUS_RUN=vvp 7 | ICARUS_SCRIPT=icarus.scr 8 | ICARUS_SIM_EXE=vlogsim.elf 9 | ICARUS=icarus 10 | 11 | 12 | # Modelsim variables 13 | MGC_VSIM=vsim 14 | MGC_VLOG_COMP=vlog 15 | MGC_VHDL_COMP=vcom 16 | MODELSIM=modelsim 17 | -------------------------------------------------------------------------------- /scripts/make/Makefile-swrules.inc: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Software compilation rules used mostly in simulation. 4 | # 5 | 6 | # Name of the image the RAM model will attempt to load via Verilog $readmemh 7 | # system function. 8 | 9 | # Set PRELOAD_RAM=1 to preload the system memory 10 | ifeq ($(PRELOAD_RAM), 1) 11 | SIM_SW_IMAGE ?=sram.vmem 12 | endif 13 | 14 | ifeq ($(SIM_SW_IMAGE),) 15 | SIM_SW_IMAGE ?=flash.in 16 | endif 17 | 18 | .PHONY : sw 19 | sw: $(SIM_SW_IMAGE) 20 | 21 | 22 | flash.in: $(SW_TEST_DIR)/$(TEST).flashin 23 | $(Q)if [ -L $@ ]; then unlink $@; fi 24 | $(Q)ln -s $< $@ 25 | 26 | flash16.in: $(SW_TEST_DIR)/$(TEST).flash16 27 | $(Q)if [ -L $@ ]; then unlink $@; fi 28 | $(Q)ln -s $< $@ 29 | 30 | sram.vmem: $(SW_TEST_DIR)/$(TEST).vmem 31 | $(Q)if [ -L $@ ]; then unlink $@; fi 32 | $(Q)ln -s $< $@ 33 | 34 | .PHONY: $(SW_TEST_DIR)/$(TEST).flashin 35 | $(SW_TEST_DIR)/$(TEST).flashin: 36 | $(Q) echo; echo "\t### Compiling software ###"; echo; 37 | $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).flashin 38 | 39 | .PHONY: $(SW_TEST_DIR)/$(TEST).vmem 40 | $(SW_TEST_DIR)/$(TEST).vmem: 41 | $(Q) echo; echo "\t### Compiling software ###"; echo; 42 | $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem 43 | 44 | .PHONY: $(SW_TEST_DIR)/$(TEST).flash16 45 | $(SW_TEST_DIR)/$(TEST).flash16: 46 | $(Q) echo; echo "\t### Compiling software ###"; echo; 47 | $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).flash16 48 | 49 | # Create test software disassembly 50 | 51 | sw-dis: $(SW_TEST_DIR)/$(TEST).dis 52 | $(Q)cp -v $< . 53 | 54 | $(SW_TEST_DIR)/$(TEST).dis: 55 | $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis 56 | 57 | 58 | # 59 | # Clean rules 60 | # 61 | 62 | clean-sim-test-sw: 63 | $(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi 64 | -------------------------------------------------------------------------------- /sim/bin/definesgen.inc: -------------------------------------------------------------------------------- 1 | # A make rule that creates the test defines verilog file. 2 | 3 | # Test defines.v file, called recursively, .PHONY to force its generation 4 | .PHONY: $(TEST_DEFINES_VLG) 5 | $(TEST_DEFINES_VLG): 6 | $(Q)echo "\`define "$(SIM_TYPE)"_SIM" > $@ 7 | $(Q)echo "\`define SIMULATOR_"`echo $(SIMULATOR) | tr "[:lower:]" "[:upper:]"` >> $@ 8 | $(Q)echo "\`define TEST_NAME_STRING \""$(TEST)"\"" >> $@ 9 | $(Q)if [ ! -z $$VCD ]; \ 10 | then echo "\`define VCD" >> $@; \ 11 | fi 12 | $(Q)if [ ! -z $$VCD_DELAY ]; \ 13 | then echo "\`define VCD_DELAY "$$VCD_DELAY >> $@; \ 14 | fi 15 | $(Q)if [ ! -z $$VCD_DEPTH ]; \ 16 | then echo "\`define VCD_DEPTH "$$VCD_DEPTH >> $@; \ 17 | fi 18 | $(Q)if [ ! -z $$VCD_DELAY_INSNS ]; \ 19 | then echo "\`define VCD_DELAY_INSNS "$$VCD_DELAY_INSNS >> $@; \ 20 | fi 21 | $(Q)if [ ! -z $$END_TIME ]; \ 22 | then echo "\`define END_TIME "$$END_TIME >> $@; \ 23 | fi 24 | $(Q)if [ ! -z $$END_INSNS ]; \ 25 | then echo "\`define END_INSNS "$$END_INSNS >> $@; \ 26 | fi 27 | $(Q)if [ ! -z $$PRELOAD_RAM ]; \ 28 | then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \ 29 | fi 30 | $(Q)if [ -z $$DISABLE_PROCESSOR_LOGS ]; \ 31 | then echo "\`define PROCESSOR_MONITOR_ENABLE_LOGS" >> $@; \ 32 | fi 33 | $(Q)if [ ! -z $$VPI ]; \ 34 | then echo "\`define VPI_DEBUG" >> $@; \ 35 | fi 36 | $(Q)if [ ! -z $$SIM_QUIET ]; \ 37 | then echo "\`define SIM_QUIET" >> $@; \ 38 | fi 39 | $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /sw/apps/cfi_ctrl_programmer/Makefile: -------------------------------------------------------------------------------- 1 | # Program to control the cfi_ctrl module to manage contents of flash memory. 2 | # 3 | # author: julius.baxter@orsoc.se 4 | # 5 | 6 | SW_ROOT=../.. 7 | 8 | #PROGRAMMINGFILE= 9 | PROGRAMMINGFILE_SWBIN=progfile.swbin # Binary file with sizeword 10 | PROGRAMMINGFILE_DATA=progfile.o 11 | 12 | ELF_DEPENDS +=$(PROGRAMMINGFILE_DATA) 13 | 14 | include $(SW_ROOT)/Makefile.inc 15 | 16 | OR32_LDFLAGS = -L$(SW_ROOT)/lib -lorpsoc -lgcc -Tcfi_ctrl_programmer.ld -e 256 17 | 18 | $(PROGRAMMINGFILE_DATA): $(PROGRAMMINGFILE) 19 | $(Q)$(OR32_LD) -r -b binary -o $@ $< 20 | $(Q)$(OR32_OBJCOPY) --rename-section .data=.userprogram $@ 21 | 22 | %.dis: %.elf 23 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 24 | 25 | %.bin: %.elf 26 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 27 | 28 | clean: 29 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis $(PROGRAMMINGFILE_SWBIN) $(PROGRAMMINGFILE_DATA) 30 | 31 | #distclean: clean 32 | -------------------------------------------------------------------------------- /sw/apps/dhry/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | # Force it to be regenerated each time, as the NUM_RUNS is likely to be changed 4 | 5 | 6 | include $(SW_ROOT)/Makefile.inc 7 | 8 | NUM_RUNS ?= 10 9 | 10 | OR32_CFLAGS+= -DNUM_RUNS=$(NUM_RUNS) 11 | 12 | %.dis: %.elf 13 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 14 | 15 | %.bin: %.elf 16 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 17 | 18 | clean: 19 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 20 | 21 | -------------------------------------------------------------------------------- /sw/apps/spiflash/Makefile: -------------------------------------------------------------------------------- 1 | # This makefile allows you generate a program which will program an SPI flash 2 | # part with another program. 3 | 4 | # It requires that the PROGRAMMINGFILE variable to set to a binary copy of a 5 | # program to program the SPI flash with. The file must already exist, the script 6 | # will not automagically compile it for you. 7 | # eg. 8 | # $ make spiflash-program.elf PROGRAMMINGFILE=../gpio/gpio-board.bin 9 | 10 | # This binary file is then converted to a version that will be loaded into the 11 | # SPI flash (the size of the image is set in the first word), and then converted 12 | # to an object file with the data in a section called .spiprogram 13 | 14 | # A linker script is then used to put this section into the resulting ELF file 15 | # that will do the programming of the SPI flash 16 | 17 | # Simply running this program on the processor should program the SPI flash 18 | # memory. 19 | 20 | # 21 | # author: julius.baxter@orsoc.se 22 | # 23 | 24 | SW_ROOT=../.. 25 | 26 | #PROGRAMMINGFILE= 27 | PROGRAMMINGFILE_SWBIN=progfile.swbin # Binary file with sizeword 28 | PROGRAMMINGFILE_DATA=progfile.o 29 | 30 | ELF_DEPENDS +=$(PROGRAMMINGFILE_DATA) 31 | 32 | include $(SW_ROOT)/Makefile.inc 33 | 34 | OR32_LDFLAGS = -L$(SW_ROOT)/lib -lorpsoc -lgcc -Tspiflash-program.ld -e 256 35 | 36 | $(SW_ROOT)/utils/bin2binsizeword: 37 | $(Q)$(MAKE) -C $(SW_ROOT)/utils bin2binsizeword 38 | 39 | $(PROGRAMMINGFILE_SWBIN): $(PROGRAMMINGFILE) $(SW_ROOT)/utils/bin2binsizeword 40 | $(Q)$(SW_ROOT)/utils/bin2binsizeword $< $@ 41 | 42 | $(PROGRAMMINGFILE_DATA): $(PROGRAMMINGFILE_SWBIN) 43 | $(Q)$(OR32_LD) -r -b binary -o $@ $< 44 | $(Q)$(OR32_OBJCOPY) --rename-section .data=.spiprogram $@ 45 | 46 | %.dis: %.elf 47 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 48 | 49 | %.bin: %.elf 50 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 51 | 52 | clean: 53 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis $(PROGRAMMINGFILE_SWBIN) $(PROGRAMMINGFILE_DATA) 54 | 55 | #distclean: clean 56 | -------------------------------------------------------------------------------- /sw/apps/testfloat/Makefile: -------------------------------------------------------------------------------- 1 | 2 | common_testfloat_sources = fail.c \ 3 | random.c \ 4 | writeHex.c \ 5 | softfloat.c \ 6 | testCases.c \ 7 | testLoops.c 8 | 9 | testsoftfloat_SOURCES = slowfloat.c \ 10 | testsoftfloat.c 11 | 12 | testfloat_SOURCES = systmodes.c \ 13 | systflags.c \ 14 | systfloat.S \ 15 | testFunction.c \ 16 | testfloat.c 17 | 18 | ELF_DEPENDS= $(common_testfloat_sources) $(testfloat_SOURCES) 19 | 20 | SW_ROOT=../.. 21 | 22 | include $(SW_ROOT)/Makefile.inc 23 | 24 | 25 | #testfloat.elf: 26 | # $(Q)$(OR32_CC) $^ -o $@ 27 | 28 | 29 | %.dis: %.elf 30 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 31 | 32 | %.bin: %.elf 33 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 34 | 35 | clean: 36 | $(Q)rm -f *.bin *.vmem *.flashin *.dis 37 | 38 | -------------------------------------------------------------------------------- /sw/apps/testfloat/fail.c: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C source file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | /* 30 | #include 31 | #include 32 | #include 33 | */ 34 | #include "cpu-utils.h" // OR1k support C library 35 | #include "milieu.h" 36 | #include "printf.h" 37 | #include "fail.h" 38 | 39 | char *fail_programName = ""; 40 | 41 | void fail( const char *message, ... ) 42 | { 43 | va_list varArgs; 44 | 45 | // No stderr in or1k support library, just print normally 46 | printf( "%s: ", fail_programName ); 47 | va_start( varArgs, message ); 48 | printf( message, varArgs ); 49 | va_end( varArgs ); 50 | printf( ".\n" ); 51 | exit( 0x1 ); 52 | 53 | } 54 | 55 | -------------------------------------------------------------------------------- /sw/apps/testfloat/fail.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C header file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | 30 | extern char *fail_programName; 31 | 32 | void fail( const char *, ... ); 33 | 34 | -------------------------------------------------------------------------------- /sw/apps/testfloat/random.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C header file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | 30 | uint8 randomUint8( void ); 31 | uint16 randomUint16( void ); 32 | uint32 randomUint32( void ); 33 | #ifdef BITS64 34 | uint64 randomUint64( void ); 35 | #endif 36 | 37 | -------------------------------------------------------------------------------- /sw/apps/testfloat/systflags.c: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C source file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | 30 | #include "milieu.h" 31 | #include "systflags.h" 32 | #include "spr-defs.h" 33 | //#include 34 | 35 | /* 36 | ------------------------------------------------------------------------------- 37 | Clears the system's IEC/IEEE floating-point exception flags. - Not anymore! 38 | Returns the previous value of the flags. 39 | ------------------------------------------------------------------------------- 40 | */ 41 | 42 | int8 fpcsr_flags; 43 | 44 | int8 syst_float_flags_clear( void ) 45 | { 46 | int8 tmp_flags = fpcsr_flags; 47 | fpcsr_flags = 0; 48 | return tmp_flags; 49 | } 50 | 51 | -------------------------------------------------------------------------------- /sw/apps/testfloat/systflags.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C header file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | 30 | /* 31 | ------------------------------------------------------------------------------- 32 | Target-specific function for clearing the system's IEC/IEEE floating-point 33 | exception flags. The previous value of the flags is returned. 34 | ------------------------------------------------------------------------------- 35 | */ 36 | int8 syst_float_flags_clear( void ); 37 | 38 | // Extern flags value - stored in softfloat's format, not OR1K's fpcsr format 39 | extern int8 fpcsr_flags; 40 | -------------------------------------------------------------------------------- /sw/apps/testfloat/systmodes.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C header file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | 30 | /* 31 | ------------------------------------------------------------------------------- 32 | Target-specific function for setting the system's IEC/IEEE floating-point 33 | rounding mode. Other system modes are also initialized as necessary (for 34 | example, exception trapping may be disabled). 35 | ------------------------------------------------------------------------------- 36 | */ 37 | void syst_float_set_rounding_mode( int8 ); 38 | 39 | /* 40 | ------------------------------------------------------------------------------- 41 | Target-specific function for setting the IEC/IEEE rounding precision of 42 | subsequent extended double-precision operations performed by the system. 43 | ------------------------------------------------------------------------------- 44 | */ 45 | void syst_float_set_rounding_precision( int8 ); 46 | 47 | -------------------------------------------------------------------------------- /sw/apps/testfloat/writeHex.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | =============================================================================== 4 | 5 | This C header file is part of TestFloat, Release 2a, a package of programs 6 | for testing the correctness of floating-point arithmetic complying to the 7 | IEC/IEEE Standard for Floating-Point. 8 | 9 | Written by John R. Hauser. More information is available through the Web 10 | page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. 11 | 12 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 13 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 14 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 15 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 16 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 17 | 18 | Derivative works are acceptable, even for commercial purposes, so long as 19 | (1) they include prominent notice that the work is derivative, and (2) they 20 | include prominent notice akin to these four paragraphs for those parts of 21 | this code that are retained. 22 | 23 | Modified for use with or1ksim's testsuite. 24 | 25 | Contributor Julius Baxter 26 | 27 | =============================================================================== 28 | */ 29 | 30 | //#include 31 | 32 | void writeHex_flag( flag/*, FILE* */ ); 33 | void writeHex_bits32( bits32/*, FILE* */ ); 34 | #ifdef BITS64 35 | void writeHex_bits64( bits64/*, FILE* */ ); 36 | #endif 37 | void writeHex_float32( float32/*, FILE* */ ); 38 | void writeHex_float64( float64/*, FILE* */ ); 39 | #ifdef FLOATX80 40 | void writeHex_floatx80( floatx80/*, FILE* */ ); 41 | #endif 42 | #ifdef FLOAT128 43 | void writeHex_float128( float128/*, FILE* */ ); 44 | #endif 45 | void writeHex_float_flags( uint8/*, FILE* */ ); 46 | 47 | -------------------------------------------------------------------------------- /sw/board/include/board.h: -------------------------------------------------------------------------------- 1 | #ifndef _BOARD_H_ 2 | #define _BOARD_H_ 3 | 4 | #define IN_CLK 50000000 // Hz 5 | 6 | 7 | // 8 | // Defines for each core (memory map base, OR1200 interrupt line number, etc.) 9 | // 10 | #define RAM_BASE 0x00000000 11 | 12 | #define UART0_BASE 0x90000000 13 | #define UART0_IRQ 2 14 | #define UART0_BAUD_RATE 115200 15 | 16 | #define SPI0_BASE 0xb0000000 17 | 18 | #define INTGEN_BASE 0xe1000000 19 | #define INTGEN_IRQ 19 20 | 21 | 22 | // 23 | // OR1200 tick timer period define 24 | // 25 | #define TICKS_PER_SEC 100 26 | 27 | 28 | // 29 | // UART driver configuration 30 | // 31 | #define UART_NUM_CORES 1 32 | #define UART_BASE_ADDRESSES_CSV UART0_BASE 33 | #define UART_BAUD_RATES_CSV UART0_BAUD_RATE 34 | 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /sw/bootrom/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for bootROM Verilog 2 | SW_ROOT=.. 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | # Whenever PRELOAD_RAM is defined on command line, we probably want the bootrom 6 | # to be jumping to reset instead of doing a full boot preload. 7 | ifeq ($(PRELOAD_RAM),1) 8 | OR32_CFLAGS += -DPRELOAD_RAM 9 | endif 10 | 11 | all: bootrom.v 12 | 13 | %.v: %.bin $(SW_ROOT)/utils/bin2vlogarray 14 | $(Q)$(SW_ROOT)/utils/bin2vlogarray < $< > $@ 15 | 16 | %.dis: %.o 17 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 18 | 19 | %.bin: %.o 20 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 21 | 22 | $(SW_ROOT)/utils/bin2vlogarray: 23 | $(Q)$(MAKE) -C $(SW_ROOT)/utils bin2vlogarray 24 | 25 | clean: 26 | $(Q)rm -f *.o *.bin *.hex *.in *.dis *.v 27 | 28 | -------------------------------------------------------------------------------- /sw/drivers/cfi-ctrl/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | COMPILE_SRCS=cfi_ctrl.c 4 | 5 | include $(SW_ROOT)/Makefile.inc 6 | 7 | clean: 8 | $(Q)rm -f *.a *.o 9 | -------------------------------------------------------------------------------- /sw/drivers/cfi-ctrl/include/cfi_ctrl.h: -------------------------------------------------------------------------------- 1 | /* cfi_ctrl driver header */ 2 | 3 | #define CFI_CTRL_UNLOCKBLOCK_OFFSET 0x04000000 4 | #define CFI_CTRL_ERASEBLOCK_OFFSET 0x08000000 5 | #define CFI_CTRL_REGS_OFFSET 0x0c000000 6 | #define CFI_CTRL_DEVICEIDENT_OFFSET 0x0e000000 7 | #define CFI_CTRL_CFIQUERY_OFFSET 0x0e010000 8 | 9 | #define CFI_CTRL_SCR_OFFSET (CFI_CTRL_REGS_OFFSET + 0) 10 | #define CFI_CTRL_FSR_OFFSET (CFI_CTRL_REGS_OFFSET + 4) 11 | 12 | #define CFI_CTRL_SCR_CONTROLLER_BUSY (1 << 0) 13 | #define CFI_CTRL_SCR_CLEAR_FSR (1 << 1) 14 | #define CFI_CTRL_SCR_RESET_DEVICE (1 << 2) 15 | 16 | /* Flash status register (FSR) bit meanings - from CFI standard */ 17 | #define CFI_FSR_DWS (1<<7) /* Device write status. 0 - busy, 1 - ready */ 18 | #define CFI_FSR_ERR (1<<6) /* Erase suspend status - N/A here */ 19 | #define CFI_FSR_ES (1<<5) /* Erase status. 0 - successful, 1 - fail/seq err. */ 20 | #define CFI_FSR_PS (1<<4) /* Program status. 0 - successful, 1 - fail/seq err*/ 21 | #define CFI_FSR_VPPS (1<<3) /* VPP status. N/A here */ 22 | #define CFI_FSR_PSS (1<<2) /* Program suspend status. N/A here */ 23 | #define CFI_FSR_BLS (1<<1) /* Block-locked status */ 24 | #define CFI_FSR_BWS (1<<0) /* Buffer-enhanced programming status - N/A here */ 25 | 26 | 27 | /* Driver function prototypes */ 28 | void cfi_ctrl_reset_flash(void); 29 | void cfi_ctrl_clear_status(void); 30 | int cfi_ctrl_busy(void); 31 | unsigned char cfi_ctrl_get_status(void); 32 | void cfi_ctrl_unlock_block(unsigned int addr); 33 | int cfi_ctrl_erase_block(unsigned int addr); 34 | void cfi_ctrl_erase_block_no_wait(unsigned int addr); 35 | int cfi_ctrl_write_short(short data, unsigned int addr); 36 | short cfi_ctrl_read_identifier(unsigned int addr); 37 | short cfi_ctrl_query_info(unsigned int addr); 38 | void cfi_ctrl_enable_data_read(void); 39 | -------------------------------------------------------------------------------- /sw/drivers/ethmac/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | COMPILE_SRCS=ethmac.c 4 | 5 | include $(SW_ROOT)/Makefile.inc 6 | 7 | clean: 8 | $(Q)rm -f *.a *.o 9 | -------------------------------------------------------------------------------- /sw/drivers/i2c_master_slave/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | COMPILE_SRCS=i2c_master_slave.c 4 | 5 | include $(SW_ROOT)/Makefile.inc 6 | 7 | clean: 8 | $(Q)rm -f *.a *.o 9 | -------------------------------------------------------------------------------- /sw/drivers/or1200/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | # Sources to go into the liborpsoc.a support library 4 | COMPILE_SRCS=exceptions.c int.c mmu.S or1200-utils.c cache.S 5 | 6 | include $(SW_ROOT)/Makefile.inc 7 | 8 | clean: 9 | $(Q)rm -f *.a *.o 10 | -------------------------------------------------------------------------------- /sw/drivers/or1200/include/int.h: -------------------------------------------------------------------------------- 1 | #ifndef _INT_H_ 2 | #define _INT_H_ 3 | 4 | /* Number of interrupt handlers - really depends on PIC width in OR1200*/ 5 | #define MAX_INT_HANDLERS 32 6 | 7 | /* Handler entry */ 8 | struct ihnd { 9 | void (*handler)(void *); 10 | void *arg; 11 | }; 12 | 13 | /* Add interrupt handler */ 14 | int int_add(unsigned long vect, void (* handler)(void *), void *arg); 15 | 16 | /* Add exception vector handler */ 17 | void add_handler(unsigned long vector, void (* handler) (void)); 18 | 19 | /* Initialize routine */ 20 | int int_init(); 21 | 22 | /* Actual interrup handler function */ 23 | void int_main(); 24 | #endif // _INT_H_ 25 | -------------------------------------------------------------------------------- /sw/drivers/or1200/include/or1200-utils.h: -------------------------------------------------------------------------------- 1 | #ifndef _OR1200_UTILS_H_ 2 | #define _OR1200_UTILS_H_ 3 | 4 | // Pull in interrupt defines here 5 | #include "int.h" 6 | 7 | /* Register access macros */ 8 | #define REG8(add) *((volatile unsigned char *)(add)) 9 | #define REG16(add) *((volatile unsigned short *)(add)) 10 | #define REG32(add) *((volatile unsigned long *)(add)) 11 | 12 | /* 13 | * l.nop constants 14 | * 15 | */ 16 | #define NOP_NOP 0x0000 /* Normal nop instruction */ 17 | #define NOP_EXIT 0x0001 /* End of simulation */ 18 | #define NOP_REPORT 0x0002 /* Simple report */ 19 | #define NOP_PRINTF 0x0003 /* Simprintf instruction */ 20 | #define NOP_PUTC 0x0004 /* Simulation putc instruction */ 21 | #define NOP_REPORT_FIRST 0x0400 /* Report with number */ 22 | #define NOP_REPORT_LAST 0x03ff /* Report with number */ 23 | 24 | /* For writing into SPR. */ 25 | void mtspr(unsigned long spr, unsigned long value); 26 | 27 | /* For reading SPR. */ 28 | unsigned long mfspr(unsigned long spr); 29 | 30 | /* Print out a character via simulator */ 31 | void sim_putc(unsigned char c); 32 | 33 | /* Prints out a value */ 34 | void report(unsigned long value); 35 | 36 | /* Loops/exits simulation */ 37 | void exit(int i); 38 | 39 | /* Enable user interrupts */ 40 | void cpu_enable_user_interrupts(void); 41 | 42 | /* Variable keeping track of timer ticks */ 43 | extern unsigned long timer_ticks; 44 | /* Enable tick timer and interrupt generation */ 45 | void cpu_enable_timer(void); 46 | /* Disable tick timer and interrupt generation */ 47 | void cpu_disable_timer(void); 48 | /* Timer increment - called by interrupt routine */ 49 | void cpu_timer_tick(void); 50 | /* Reset tick counter */ 51 | void cpu_reset_timer_ticks(void); 52 | /* Get tick counter */ 53 | unsigned long cpu_get_timer_ticks(void); 54 | /* Wait for 10ms */ 55 | void cpu_sleep_10ms(void); 56 | 57 | #endif 58 | -------------------------------------------------------------------------------- /sw/drivers/or1200/int.c: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * User interrupt handler software for OR1200 4 | * 5 | */ 6 | 7 | #include "or1200-utils.h" 8 | #include "spr-defs.h" 9 | #include "int.h" 10 | 11 | /* Interrupt handlers table */ 12 | struct ihnd int_handlers[MAX_INT_HANDLERS]; 13 | 14 | /* Initialize routine */ 15 | int int_init() 16 | { 17 | int i; 18 | 19 | for(i = 0; i < MAX_INT_HANDLERS; i++) { 20 | int_handlers[i].handler = 0; 21 | int_handlers[i].arg = 0; 22 | } 23 | 24 | return 0; 25 | } 26 | 27 | /* Add interrupt handler */ 28 | int int_add(unsigned long irq, void (* handler)(void *), void *arg) 29 | { 30 | if(irq >= MAX_INT_HANDLERS) 31 | return -1; 32 | 33 | int_handlers[irq].handler = handler; 34 | int_handlers[irq].arg = arg; 35 | 36 | mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq)); 37 | 38 | return 0; 39 | } 40 | 41 | /* Disable interrupt */ 42 | int int_disable(unsigned long irq) 43 | { 44 | if(irq >= MAX_INT_HANDLERS) 45 | return -1; 46 | 47 | mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << irq)); 48 | 49 | return 0; 50 | } 51 | 52 | /* Enable interrupt */ 53 | int int_enable(unsigned long irq) 54 | { 55 | if(irq >= MAX_INT_HANDLERS) 56 | return -1; 57 | 58 | mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq)); 59 | 60 | return 0; 61 | } 62 | 63 | /* Main interrupt handler */ 64 | void int_main() 65 | { 66 | unsigned long picsr = mfspr(SPR_PICSR); 67 | unsigned long i = 0; 68 | 69 | mtspr(SPR_PICSR, 0); 70 | 71 | while(i < 32) { 72 | if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { 73 | (*int_handlers[i].handler)(int_handlers[i].arg); 74 | #ifdef OR1200_INT_CHECK_BIT_CLEARED 75 | // Ensure PICSR bit is cleared, incase it takes some time for the 76 | // IRQ line going low to propagate back to PIC 77 | while (mfspr(SPR_PICSR) & (0x00000001L << i)) 78 | #endif 79 | mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i)); 80 | } 81 | i++; 82 | } 83 | } 84 | 85 | 86 | -------------------------------------------------------------------------------- /sw/drivers/or1200/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH(or32) 2 | SEARCH_DIR(.) 3 | __DYNAMIC = 0; 4 | 5 | MEMORY 6 | { 7 | vectors : ORIGIN = 0, LENGTH = 0x1000 8 | ram : ORIGIN = 0x1000, LENGTH = (8M - 0x1000) 9 | } 10 | 11 | 12 | /* Stack information variables */ 13 | _min_stack = 0x2000; /* 8K - minimum stack space to reserve */ 14 | 15 | 16 | SECTIONS 17 | { 18 | .vectors : 19 | { 20 | *(.vectors) 21 | } > vectors 22 | 23 | .text : { 24 | _stext = .; 25 | *(.text) 26 | _etext = .; 27 | __CTOR_LIST__ = .; 28 | LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) 29 | *(.ctors) 30 | LONG(0) 31 | __CTOR_END__ = .; 32 | __DTOR_LIST__ = .; 33 | LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) 34 | *(.dtors) 35 | LONG(0) 36 | __DTOR_END__ = .; 37 | *(.lit) 38 | *(.shdata) 39 | _endtext = .; 40 | } > ram 41 | 42 | .rodata : { 43 | *(.rodata); 44 | *(.rodata.*) 45 | } > ram 46 | 47 | .shbss : 48 | { 49 | *(.shbss) 50 | } > ram 51 | 52 | .talias : 53 | { 54 | } > ram 55 | 56 | .data : { 57 | sdata = .; 58 | _sdata = .; 59 | *(.data) 60 | edata = .; 61 | _edata = .; 62 | } > ram 63 | 64 | .bss : 65 | { 66 | _bss_start = .; 67 | *(.bss) 68 | *(COMMON) 69 | _bss_end = .; 70 | } > ram 71 | 72 | /* ensure there is enough room for stack */ 73 | .stack (NOLOAD): { 74 | . = ALIGN(4); 75 | . = . + _min_stack ; 76 | . = ALIGN(4); 77 | stack = . ; 78 | _stack = . ; 79 | } > ram 80 | 81 | .stab 0 (NOLOAD) : 82 | { 83 | [ .stab ] 84 | } 85 | 86 | .stabstr 0 (NOLOAD) : 87 | { 88 | [ .stabstr ] 89 | } 90 | } 91 | -------------------------------------------------------------------------------- /sw/drivers/or1200/mmu.S: -------------------------------------------------------------------------------- 1 | #include "spr-defs.h" 2 | 3 | /* MMU enable functions */ 4 | .global lo_dmmu_en 5 | lo_dmmu_en: 6 | l.mfspr r3,r0,SPR_SR 7 | l.ori r3,r3,SPR_SR_DME 8 | l.mtspr r0,r3,SPR_ESR_BASE 9 | l.mtspr r0,r9,SPR_EPCR_BASE 10 | l.rfe 11 | l.nop 12 | 13 | .global lo_immu_en 14 | lo_immu_en: 15 | l.mfspr r3,r0,SPR_SR 16 | l.ori r3,r3,SPR_SR_IME 17 | l.mtspr r0,r3,SPR_ESR_BASE 18 | l.mtspr r0,r9,SPR_EPCR_BASE 19 | l.rfe 20 | l.nop 21 | 22 | -------------------------------------------------------------------------------- /sw/drivers/simple-spi/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | COMPILE_SRCS=simple-spi.c 4 | 5 | include $(SW_ROOT)/Makefile.inc 6 | 7 | clean: 8 | $(Q)rm -f *.a *.o 9 | -------------------------------------------------------------------------------- /sw/drivers/uart/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../.. 2 | 3 | COMPILE_SRCS=uart.c 4 | 5 | include $(SW_ROOT)/Makefile.inc 6 | 7 | clean: 8 | $(Q)rm -f *.a *.o 9 | -------------------------------------------------------------------------------- /sw/lib/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=.. 2 | include $(SW_ROOT)/Makefile.inc 3 | 4 | LIBORPSOC_SRC= lib-utils.c printf.c 5 | 6 | %/$(DRIVER_OBJ): 7 | $(Q)$(MAKE) -C $* $(DRIVER_OBJ) 8 | 9 | LIBORPSOC_OBJS=$(LIBORPSOC_SRC:%.c=%.o) 10 | 11 | liborpsoc.a: $(LIBORPSOC_OBJS) $(SW_DRIVER_PATHS:%=%/$(DRIVER_OBJ)) 12 | $(Q)$(OR32_AR) cru $@ $^ 13 | $(Q)$(OR32_RANLIB) $@ 14 | 15 | clean: 16 | $(Q)rm -f *.a *.o 17 | 18 | # Special rule to help simulation Makefile compile VMEMs from ELFs passed via 19 | # the USER_ELF variable 20 | $(USER_ELF_BIN): $(USER_ELF) 21 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 22 | $(USER_ELF_VMEM): $(USER_ELF_BIN) $(UTILS_BIN2VMEM) 23 | $(Q)$(UTILS_BIN2VMEM) $< $(USER_ELF_VMEM_GEN_OPTS) > $@ 24 | gen-user-elf-vmem: $(USER_ELF_VMEM) 25 | -------------------------------------------------------------------------------- /sw/lib/include/cpu-utils.h: -------------------------------------------------------------------------------- 1 | #ifndef _CPU_UTILS_H_ 2 | #define _CPU_UTILS_H_ 3 | 4 | // Somehow in future detect which CPU we're using, but for now hardcode OR1200 5 | #include "or1200-utils.h" 6 | 7 | #endif 8 | -------------------------------------------------------------------------------- /sw/lib/include/lib-utils.h: -------------------------------------------------------------------------------- 1 | #ifndef _LIB_UTILS_H_ 2 | #define _LIB_UTILS_H_ 3 | 4 | // null from stddef.h 5 | #define NULL ((void *)0) 6 | // valist stuff from stddef.h 7 | typedef __builtin_va_list __gnuc_va_list; 8 | typedef __gnuc_va_list va_list; 9 | #define va_start(v,l) __builtin_va_start(v,l) 10 | #define va_end(v) __builtin_va_end(v) 11 | #define va_arg(v,l) __builtin_va_arg(v,l) 12 | #define va_copy(d,s) __builtin_va_copy(d,s) 13 | 14 | // size_t and wchar definitions 15 | typedef unsigned int size_t; 16 | // wchar def 17 | #ifndef __WCHAR_TYPE__ 18 | #define __WCHAR_TYPE__ int 19 | #endif 20 | #ifndef __cplusplus 21 | typedef __WCHAR_TYPE__ wchar_t; 22 | #endif 23 | 24 | /* memcpy */ 25 | void* memcpy( void* s1, void* s2, size_t n); 26 | 27 | /* strlen */ 28 | size_t strlen(const char*s); 29 | 30 | /* memchr */ 31 | void *memchr(const void *s, int c, size_t n); 32 | 33 | /* Seed for LFSR function used in rand() */ 34 | /* This seed was derived from running the LFSR with a seed of 1 - helps skip the 35 | first iterations which outputs the value shifting through. */ 36 | #define RAND_LFSR_SEED 0x14b6bc3c 37 | /* Pseudo-random number generation */ 38 | unsigned long int rand (); 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /sw/lib/include/printf.h: -------------------------------------------------------------------------------- 1 | #ifndef _PRINTF_H_ 2 | #define _PRINTF_H_ 3 | 4 | int sprintf(char* str, const char *fmt, ...); 5 | 6 | #define PRINTFBUFFER_SIZE 512 7 | extern char PRINTFBUFFER[PRINTFBUFFER_SIZE]; // Declare a global printf buffer 8 | //int vfnprintf ( char *stream, size_t n, const char *format, va_list arg); 9 | 10 | 11 | int printf_to_uart(const char *fmt, ...); 12 | int printf_to_sim(const char *fmt, ...); 13 | 14 | int putchar_to_uart(int c); 15 | int putchar_to_sim(int c); 16 | 17 | int puts_to_uart(const char *str); 18 | int puts_to_sim(const char *str); 19 | 20 | // for now... 21 | 22 | #ifdef _UART_H_ 23 | #define printf printf_to_uart 24 | #define putchar putchar_to_uart 25 | #define puts puts_to_uart 26 | #else 27 | #define printf printf_to_sim 28 | #define putchar putchar_to_sim 29 | #define puts puts_to_sim 30 | #endif 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /sw/lib/lib-utils.c: -------------------------------------------------------------------------------- 1 | #include "lib-utils.h" 2 | 3 | /* Simple C functions */ 4 | 5 | /* memcpy */ 6 | 7 | void* memcpy( void* s1, void* s2, size_t n) 8 | { 9 | char* r1 = (char *) s1; 10 | const char* r2 = (const char*) s2; 11 | #ifdef __BCC__ 12 | while (n--) { 13 | *r1++ = *r2++; 14 | } 15 | #else 16 | while (n) { 17 | *r1++ = *r2++; 18 | --n; 19 | } 20 | #endif 21 | return s1; 22 | } 23 | 24 | /* strlen */ 25 | size_t strlen(const char*s) 26 | { 27 | const char* p; 28 | for (p=s; *p; p++); 29 | return p - s; 30 | } 31 | 32 | /* memchr */ 33 | void *memchr(const void *s, int c, size_t n) 34 | { 35 | const unsigned char *r = (const unsigned char *) s; 36 | #ifdef __BCC__ 37 | /* bcc can optimize the counter if it thinks it is a pointer... */ 38 | const char *np = (const char *) n; 39 | #else 40 | # define np n 41 | #endif 42 | 43 | while (np) { 44 | if (*r == ((unsigned char)c)) { 45 | return (void *) r; /* silence the warning */ 46 | } 47 | ++r; 48 | --np; 49 | } 50 | 51 | return NULL; 52 | } 53 | 54 | /* --------------------------------------------------------------------------*/ 55 | /*!Pseudo-random number generator 56 | 57 | This should return pseudo-random numbers, based on a Galois LFSR 58 | 59 | @return The next pseudo-random number */ 60 | /* --------------------------------------------------------------------------*/ 61 | unsigned long int 62 | rand () 63 | { 64 | static unsigned long int lfsr = RAND_LFSR_SEED; 65 | static int period = 0; 66 | /* taps: 32 31 29 1; characteristic polynomial: x^32 + x^31 + x^29 + x + 1 */ 67 | lfsr = (lfsr >> 1) ^ (unsigned long int)((0 - (lfsr & 1u)) & 0xd0000001u); 68 | ++period; 69 | return lfsr; 70 | } 71 | -------------------------------------------------------------------------------- /sw/tests/cfi_ctrl/board/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/cfi_ctrl/board/cfi_ctrl-readid.c: -------------------------------------------------------------------------------- 1 | #include "board.h" 2 | #include "cpu-utils.h" 3 | #include "cfi_ctrl.h" 4 | #include "uart.h" 5 | #include "printf.h" 6 | 7 | #include "orpsoc-defines.h" 8 | 9 | 10 | int main(void) 11 | { 12 | uart_init(DEFAULT_UART); 13 | 14 | printf("\nReading some CFI ID\n"); 15 | printf("manufacturer code: %04x\n",cfi_ctrl_read_identifier(0x00)&0xffff); 16 | printf("Device ID: %04x\n",cfi_ctrl_read_identifier(0x01)&0xffff); 17 | printf("RCR: %04x\n",cfi_ctrl_read_identifier(0x05)&0xffff); 18 | 19 | printf("query info: %04x\n",cfi_ctrl_query_info(0x10)&0xffff); 20 | printf("query info: %04x\n",cfi_ctrl_query_info(0x11)&0xffff); 21 | printf("query info: %04x\n",cfi_ctrl_query_info(0x12)&0xffff); 22 | printf("device timing & voltage info: %04x\n", 23 | cfi_ctrl_query_info(0x1b)&0xffff); 24 | 25 | report(0x8000000d); 26 | exit(0); 27 | } 28 | -------------------------------------------------------------------------------- /sw/tests/cfi_ctrl/board/cfi_ctrl-simple.c: -------------------------------------------------------------------------------- 1 | #include "board.h" 2 | #include "cpu-utils.h" 3 | #include "cfi_ctrl.h" 4 | #include "uart.h" 5 | #include "printf.h" 6 | #include "orpsoc-defines.h" 7 | 8 | 9 | int main(void) 10 | { 11 | uart_init(DEFAULT_UART); 12 | 13 | printf("cfi_ctrl-simple test"); 14 | 15 | /* Reset the flash */ 16 | cfi_ctrl_reset_flash(); 17 | 18 | /* wait for the controller to be done */ 19 | while (cfi_ctrl_busy()); 20 | 21 | #define NUM_PAGES 8 22 | #define TEST_LENGTH 64 23 | int i,j; 24 | unsigned int page_base; 25 | unsigned short check_data[TEST_LENGTH]; 26 | unsigned short tmp; 27 | 28 | /* test for number of blocks... */ 29 | for(j=0;j $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/cfi_ctrl/sim/cfi_ctrl-readid.c: -------------------------------------------------------------------------------- 1 | #include "board.h" 2 | #include "cpu-utils.h" 3 | #include "cfi_ctrl.h" 4 | #include "printf.h" 5 | 6 | #include "orpsoc-defines.h" 7 | 8 | 9 | int main(void) 10 | { 11 | printf("\nReading some CFI ID\n"); 12 | printf("manufacturer code: %04x\n",cfi_ctrl_read_identifier(0x00)&0xffff); 13 | printf("Device ID: %04x\n",cfi_ctrl_read_identifier(0x01)&0xffff); 14 | printf("RCR: %04x\n",cfi_ctrl_read_identifier(0x05)&0xffff); 15 | 16 | printf("query info: %04x\n",cfi_ctrl_query_info(0x10)&0xffff); 17 | printf("query info: %04x\n",cfi_ctrl_query_info(0x11)&0xffff); 18 | printf("query info: %04x\n",cfi_ctrl_query_info(0x12)&0xffff); 19 | printf("device timing & voltage info: %04x\n", 20 | cfi_ctrl_query_info(0x1b)&0xffff); 21 | 22 | report(0x8000000d); 23 | exit(0); 24 | } 25 | -------------------------------------------------------------------------------- /sw/tests/ethmac/board/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/ethmac/sim/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/or1200/board/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/or1200/sim/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/or1200/sim/or1200-float.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Trivial test of floating point capability, be it hardware or software. 3 | * 4 | */ 5 | 6 | #include "cpu-utils.h" 7 | 8 | int main() 9 | { 10 | 11 | volatile int a = 5; 12 | volatile float a_float; 13 | volatile int * int_ptr; 14 | volatile float b = 9232.25; 15 | 16 | report((int)b); 17 | // test float to int 18 | if ((int) b != 9232) 19 | exit(1); 20 | 21 | a_float = (float) a; // Should convert to float 22 | int_ptr = (int*) &a_float; 23 | //report((int)*((int*)void_ptr)); 24 | report(*int_ptr); 25 | 26 | if (*int_ptr != 0x40A00000)// is decimal 5 in single prec. float 27 | exit(2); 28 | 29 | // Should be 343.3 * 8.6 30 | volatile float c = (float) 343.3 * (float) ((float) 79397.35 / (float) b ); 31 | 32 | volatile float* d = 0x0; 33 | 34 | *d = c; 35 | 36 | // C should be 0x45388615 37 | int_ptr = (int*) &c; 38 | report(*int_ptr); 39 | if (*int_ptr != 0x45388615) 40 | exit(3); 41 | 42 | report(0x8000000d); 43 | 44 | exit(0); 45 | 46 | } 47 | -------------------------------------------------------------------------------- /sw/tests/or1200/sim/or1200-simple.c: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Test run first, to check the main loop is reached and the exit mechanism 4 | * functions OK 5 | * 6 | */ 7 | 8 | 9 | #include "cpu-utils.h" 10 | 11 | int main() 12 | { 13 | report(0x8000000d); 14 | exit(0); 15 | } 16 | -------------------------------------------------------------------------------- /sw/tests/sdram/board/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | include $(SW_ROOT)/Makefile.inc 3 | 4 | OR32_CFLAGS += -I. 5 | 6 | %.dis: %.elf 7 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 8 | 9 | %.bin: %.elf 10 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 11 | 12 | clean: 13 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 14 | 15 | -------------------------------------------------------------------------------- /sw/tests/sdram/sim/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | include $(SW_ROOT)/Makefile.inc 3 | 4 | OR32_CFLAGS += -I. 5 | 6 | %.dis: %.elf 7 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 8 | 9 | %.bin: %.elf 10 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 11 | 12 | clean: 13 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 14 | 15 | -------------------------------------------------------------------------------- /sw/tests/sdram/sim/sdram-bankrows.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SDRAM row/bank test 3 | * 4 | * Tests accessing different rows on different banks 5 | * 6 | */ 7 | 8 | #include "cpu-utils.h" 9 | #include "board.h" 10 | #include "sdram.h" 11 | 12 | #define NUM_SDRAM_BANKS 4 13 | #define SDRAM_BANK_SIZE (SDRAM_SIZE / NUM_SDRAM_BANKS) 14 | #define SDRAM_BANK_START(bank) ((SDRAM_BANK_SIZE*bank) + SDRAM_BASE) 15 | #define SDRAM_BANK_LAST_WORD(bank) ((SDRAM_BANK_START((bank+1)))-4) 16 | #define SDRAM_BANK_MIDDLE_WORD(bank) ((SDRAM_BANK_START((bank)))+(SDRAM_BANK_SIZE/2)) 17 | 18 | int main() 19 | { 20 | 21 | REG32(SDRAM_BANK_LAST_WORD(0)) = 0x00001111; 22 | REG32(SDRAM_BANK_MIDDLE_WORD(1)) = 0x22223333; 23 | REG32(SDRAM_BANK_LAST_WORD(1)) = 0x44445555; 24 | REG32(SDRAM_BANK_MIDDLE_WORD(2)) = 0x66667777; 25 | REG32(SDRAM_BANK_LAST_WORD(2)) = 0x88889999; 26 | REG32(SDRAM_BANK_MIDDLE_WORD(3)) = 0xaaaabbbb; 27 | REG32(SDRAM_BANK_LAST_WORD(3)) = 0xccccdddd; 28 | 29 | unsigned long read_result = 0; 30 | read_result += REG32(SDRAM_BANK_LAST_WORD(0)); 31 | read_result += REG32(SDRAM_BANK_MIDDLE_WORD(1)); 32 | read_result += REG32(SDRAM_BANK_LAST_WORD(1)); 33 | read_result += REG32(SDRAM_BANK_MIDDLE_WORD(2)); 34 | read_result += REG32(SDRAM_BANK_LAST_WORD(2)); 35 | read_result += REG32(SDRAM_BANK_MIDDLE_WORD(3)); 36 | read_result += REG32(SDRAM_BANK_LAST_WORD(3)); 37 | report(read_result); 38 | // read_result should be 0xCCCD4441 39 | exit((read_result^0x4ccd444c)); /* should result in 8000000d */ 40 | } 41 | -------------------------------------------------------------------------------- /sw/tests/sdram/sim/sdram-banks.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SDRAM bank test 3 | * 4 | * Tests the extremeties of the SDRAM banks 5 | * 6 | */ 7 | 8 | #include "cpu-utils.h" 9 | #include "board.h" 10 | #include "sdram.h" 11 | 12 | #define SDRAM_BANK_SIZE (SDRAM_SIZE / SDRAM_NUM_BANKS) 13 | #define SDRAM_BANK_START(bank) ((SDRAM_BANK_SIZE*bank) + SDRAM_BASE) 14 | #define SDRAM_BANK_LAST_WORD(bank) ((SDRAM_BANK_START((bank+1)))-4) 15 | 16 | int main() 17 | { 18 | report (SDRAM_SIZE); 19 | report (SDRAM_BANK_SIZE); 20 | report (SDRAM_BANK_START(0)); 21 | report (SDRAM_BANK_LAST_WORD(0)); 22 | report (SDRAM_BANK_START(1)); 23 | report (SDRAM_BANK_LAST_WORD(1)); 24 | report (SDRAM_BANK_START(2)); 25 | report (SDRAM_BANK_LAST_WORD(2)); 26 | report (SDRAM_BANK_START(3)); 27 | report (SDRAM_BANK_LAST_WORD(3)); 28 | 29 | REG32(SDRAM_BANK_LAST_WORD(0)) = 0x11111111; 30 | REG32(SDRAM_BANK_LAST_WORD(1)) = 0x22222222; 31 | REG32(SDRAM_BANK_LAST_WORD(2)) = 0x33333333; 32 | REG32(SDRAM_BANK_LAST_WORD(3)) = 0x44444444; 33 | 34 | 35 | unsigned long read_result = 0; 36 | read_result += REG32(SDRAM_BANK_LAST_WORD(0)); 37 | read_result += REG32(SDRAM_BANK_LAST_WORD(1)); 38 | read_result += REG32(SDRAM_BANK_LAST_WORD(2)); 39 | read_result += REG32(SDRAM_BANK_LAST_WORD(3)); 40 | 41 | exit((read_result-0x2aaaaa9d)); /* should result in 8000000d */ 42 | } 43 | -------------------------------------------------------------------------------- /sw/tests/sdram/sim/sdram-cols.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SDRAM column test 3 | * 4 | * Tests accessing beginning and middle of column. Should detect any mismatch 5 | * between SDRAM row size configuration. 6 | * 7 | */ 8 | 9 | #include "cpu-utils.h" 10 | #include "board.h" 11 | #include "sdram.h" 12 | 13 | // Start some rows after the program/data 14 | 15 | #define STACK_AT (128*1024) 16 | #define START_ROW ((STACK_AT/SDRAM_ROW_SIZE)+1) 17 | 18 | 19 | // For a short test, set the following to 1 20 | #define SHORT_TEST 0 21 | 22 | #if SHORT_TEST==1 23 | # define SDRAM_NUM_ROWS (START_ROW + 512) 24 | #else 25 | # define SDRAM_NUM_ROWS (SDRAM_NUM_ROWS_PER_BANK * SDRAM_NUM_BANKS) 26 | #endif 27 | 28 | #define SDRAM_ROW_BEGINNING 0 29 | #define SDRAM_ROW_MIDDLE (SDRAM_ROW_SIZE/2) 30 | 31 | int main() 32 | { 33 | 34 | int i; // Skip first 64KB, code/stack resides there 35 | for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++) 36 | { 37 | REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_BEGINNING) = i; 38 | REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_MIDDLE) = ~i; 39 | } 40 | 41 | int read_result = 0; 42 | int read_result_inv = 0; 43 | 44 | for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++) 45 | { 46 | read_result = REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_BEGINNING); 47 | read_result_inv = REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_MIDDLE); 48 | if ((read_result != i) || (read_result_inv != ~i)) 49 | { 50 | report(0xbaaaaaad); 51 | report(i); 52 | report(read_result); 53 | exit(0xbaaaaaad); 54 | } 55 | } 56 | exit(0x8000000d); 57 | } 58 | -------------------------------------------------------------------------------- /sw/tests/sdram/sim/sdram-rows.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SDRAM row test 3 | * 4 | * Tests accessing every row 5 | * 6 | */ 7 | 8 | #include "cpu-utils.h" 9 | #include "board.h" 10 | #include "sdram.h" 11 | 12 | #define SDRAM_NUM_ROWS (SDRAM_NUM_ROWS_PER_BANK * SDRAM_NUM_BANKS) 13 | 14 | #define STACK_AT (128*1024) 15 | #define START_ROW ((STACK_AT/SDRAM_ROW_SIZE)+1) 16 | 17 | int main() 18 | { 19 | 20 | int i; // Skip first 64KB, code/stack resides there 21 | for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++) 22 | REG32((i*(SDRAM_ROW_SIZE))) = i; 23 | 24 | int read_result = 0; 25 | 26 | for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++) 27 | { 28 | read_result = REG32((i*(SDRAM_ROW_SIZE))); 29 | if (read_result != i) 30 | { 31 | report(0xbaaaaaad); 32 | report(i); 33 | report(read_result); 34 | exit(0xbaaaaaad); 35 | } 36 | } 37 | exit(0x8000000d); 38 | } 39 | -------------------------------------------------------------------------------- /sw/tests/sdram/sim/sdram.h: -------------------------------------------------------------------------------- 1 | #ifndef _SDRAM_H_ 2 | #define _SDRAM_H_ 3 | 4 | #ifdef MT48LC32M16A2 // 64MB SDRAM part 5 | #define SDRAM_SIZE 0x04000000 6 | #define SDRAM_ROW_SIZE 2048 // in bytes (10 bits col addr, 2 bytes per) 7 | #define SDRAM_NUM_ROWS_PER_BANK (8192) // 13-bit row address 8 | #define SDRAM_NUM_BANKS 4 9 | #endif 10 | 11 | #ifdef MT48LC16M16A2 // 32MB SDRAM part 12 | #define SDRAM_SIZE 0x02000000 13 | #define SDRAM_ROW_SIZE 1024 // in bytes (9 bits col addr, 2 bytes per) 14 | #define SDRAM_NUM_ROWS_PER_BANK (8192) // 13-bit row address 15 | #define SDRAM_NUM_BANKS 4 16 | #endif 17 | 18 | #ifdef MT48LC4M16A2 // 8MB SDRAM part 19 | #define SDRAM_SIZE 0x800000 20 | #define SDRAM_ROW_SIZE 512 // in bytes (8 bits col addr, 2 bytes per) 21 | #define SDRAM_NUM_ROWS_PER_BANK (4096) // 12-bit row address 22 | #define SDRAM_NUM_BANKS 4 23 | #endif 24 | 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /sw/tests/spi/board/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/spi/sim/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/spi/sim/spi-simple.c: -------------------------------------------------------------------------------- 1 | /* 2 | SPI controller simple test 3 | 4 | Do some reads from the SPI slaves. Select a different slave each loop 5 | and does a read and reports the value. 6 | 7 | Nothing much actually gets tested here. 8 | 9 | Ensure the slave selects for the spi are enabled in orpsoc-defines.v 10 | 11 | */ 12 | 13 | 14 | #include "cpu-utils.h" 15 | #include "simple-spi.h" 16 | 17 | #include "orpsoc-defines.h" 18 | 19 | // Detect which of the SPI cores are enabled, tailor the test for that 20 | #ifndef SPI1 21 | # ifndef SPI2 22 | # error 23 | # error No SPI cores to test with! Please enable SPI1 and/or SPI2 24 | # error 25 | # else 26 | # define NUM_SPI_CORES 1 27 | # define FIRST_SPI_CORE 2 28 | # endif 29 | #else 30 | # ifdef SPI2 31 | # define NUM_SPI_CORES 2 32 | # define FIRST_SPI_CORE 1 33 | # else 34 | # define NUM_SPI_CORES 1 35 | # define FIRST_SPI_CORE 1 36 | # endif 37 | #endif 38 | 39 | int main() 40 | { 41 | int spi_master = FIRST_SPI_CORE; 42 | int spi_slave = 2; 43 | int i; 44 | 45 | // Init the masters 46 | for (spi_master = FIRST_SPI_CORE; 47 | spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES; 48 | spi_master++) 49 | { 50 | spi_core_clock_setup(spi_master, 0, 0, 2, 0); 51 | spi_core_enable(spi_master); 52 | } 53 | 54 | 55 | // Play with the slaves 56 | for(i=0;i<64;i++) 57 | { 58 | for (spi_master = FIRST_SPI_CORE; 59 | spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES; 60 | spi_master++) 61 | { 62 | spi_slave = i % 3; 63 | spi_slave = (1 << spi_slave); 64 | // Select slave on SPI bus 65 | spi_core_slave_select(spi_master, spi_slave); 66 | // Do a SPI bus transaction - we're only interested in the read data 67 | // coming back 68 | while (!spi_core_write_avail(spi_master)); 69 | spi_core_write_data(spi_master, (i&0xff)); 70 | while (!spi_core_data_avail(spi_master)); 71 | report(spi_core_read_data(spi_master)); 72 | // Deselect slaves 73 | spi_core_slave_select(spi_master, 0); 74 | } 75 | } 76 | 77 | exit(0x8000000d); 78 | 79 | } 80 | -------------------------------------------------------------------------------- /sw/tests/uart/board/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/uart/board/uart-echo.c: -------------------------------------------------------------------------------- 1 | #include "cpu-utils.h" 2 | #include "uart.h" 3 | #include "printf.h" 4 | 5 | // Echo some characters until we recieve a '!' charecter, after which 6 | // we will exit simulation. 7 | 8 | 9 | int 10 | main() 11 | { 12 | 13 | uart_init(DEFAULT_UART); // init the UART before we can printf 14 | 15 | char c; 16 | printf("Echo - type and see it echo back:\n"); 17 | while (1) 18 | { 19 | c = uart_getc(DEFAULT_UART); 20 | printf("%c",c); 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /sw/tests/uart/sim/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/Makefile.inc 4 | 5 | %.dis: %.elf 6 | $(Q)$(OR32_OBJDUMP) -d $< > $@ 7 | 8 | %.bin: %.elf 9 | $(Q)$(OR32_OBJCOPY) -O binary $< $@ 10 | 11 | clean: 12 | $(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis 13 | 14 | -------------------------------------------------------------------------------- /sw/tests/uart/sim/uart-simple.c: -------------------------------------------------------------------------------- 1 | /* 2 | * UART hello world 3 | * 4 | * Tests UARTs by printing a hello world string. 5 | * 6 | * Julius Baxter, julius.baxter@orsoc.se 7 | * 8 | */ 9 | 10 | #include "cpu-utils.h" 11 | #include "board.h" 12 | #include "uart.h" 13 | #include "printf.h" 14 | 15 | void hello_from_uart(int uart_core) 16 | { 17 | uart_init(uart_core); 18 | printf("\n\tHello world from UART%d \n\0", uart_core); 19 | } 20 | 21 | int main() 22 | { 23 | 24 | hello_from_uart(0); 25 | 26 | report(0x8000000d); 27 | 28 | exit(0); 29 | 30 | } 31 | -------------------------------------------------------------------------------- /sw/utils/or32-idecode/example_input: -------------------------------------------------------------------------------- 1 | 18000000 2 | A8200000 3 | 1880B000 4 | A8A00520 5 | A8600001 6 | 04000014 7 | D4041818 8 | 04000012 9 | D4040000 10 | E0431804 11 | 0400000F 12 | 9C210008 13 | 0400000D 14 | E1031804 15 | E4080000 16 | 0FFFFFFB 17 | D4081800 18 | 04000008 19 | 9C210004 20 | D4011800 21 | E4011000 22 | 0FFFFFFC 23 | A8C00100 24 | 44003000 25 | D4040018 26 | D4042810 27 | 84640010 28 | BC030520 29 | 13FFFFFE 30 | 0x15000000 31 | 0x44004800 32 | 0x84640000 33 | -------------------------------------------------------------------------------- /sw/utils/or32-idecode/symcat.h: -------------------------------------------------------------------------------- 1 | /* Symbol concatenation utilities. 2 | 3 | Copyright (C) 1998, 2000 Free Software Foundation, Inc. 4 | 5 | This program is free software; you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation; either version 2 of the License, or 8 | (at your option) any later version. 9 | 10 | This program is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License along 16 | with this program; if not, write to the Free Software Foundation, Inc., 17 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 18 | 19 | #ifndef SYM_CAT_H 20 | #define SYM_CAT_H 21 | 22 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 23 | #define CONCAT2(a,b) a##b 24 | #define CONCAT3(a,b,c) a##b##c 25 | #define CONCAT4(a,b,c,d) a##b##c##d 26 | #define STRINGX(s) #s 27 | #else 28 | /* Note one should never pass extra whitespace to the CONCATn macros, 29 | e.g. CONCAT2(foo, bar) because traditonal C will keep the space between 30 | the two labels instead of concatenating them. Instead, make sure to 31 | write CONCAT2(foo,bar). */ 32 | #define CONCAT2(a,b) a/**/b 33 | #define CONCAT3(a,b,c) a/**/b/**/c 34 | #define CONCAT4(a,b,c,d) a/**/b/**/c/**/d 35 | #define STRINGX(s) "s" 36 | #endif 37 | 38 | #define XCONCAT2(a,b) CONCAT2(a,b) 39 | #define XCONCAT3(a,b,c) CONCAT3(a,b,c) 40 | #define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d) 41 | 42 | /* Note the layer of indirection here is typically used to allow 43 | stringification of the expansion of macros. I.e. "#define foo 44 | bar", "XSTRING(foo)", to yield "bar". Be aware that this only 45 | works for __STDC__, not for traditional C which will still resolve 46 | to "foo". */ 47 | #define XSTRING(s) STRINGX(s) 48 | 49 | #endif /* SYM_CAT_H */ 50 | --------------------------------------------------------------------------------