├── .gitignore ├── .gitmodules ├── Jenkinsfile ├── LICENSE ├── Makefile ├── README.md ├── doc ├── 1stage.xml ├── 2stage.xml ├── 3stage.xml ├── 5stage.xml ├── lab1.pdf ├── overview.xml ├── ucode.xml ├── zscale.pdf └── zscale.png ├── emulator ├── common │ ├── Makefile.include │ ├── SimDTM.cc │ ├── emulator.cpp │ └── verilator.h ├── rv32_1stage │ └── Makefile ├── rv32_2stage │ └── Makefile ├── rv32_3stage │ └── Makefile ├── rv32_5stage │ └── Makefile └── rv32_ucode │ └── Makefile ├── sbt-launch.jar ├── src ├── common │ ├── abstract_commands.scala │ ├── configurations.scala │ ├── consts.scala │ ├── csr.scala │ ├── debug.scala │ ├── dm_registers.scala │ ├── instructions.scala │ ├── memory.scala │ └── util.scala ├── rv32_1stage │ ├── consts.scala │ ├── core.scala │ ├── cpath.scala │ ├── dpath.scala │ ├── tile.scala │ └── top.scala ├── rv32_2stage │ ├── consts.scala │ ├── core.scala │ ├── cpath.scala │ ├── dpath.scala │ ├── tile.scala │ └── top.scala ├── rv32_3stage │ ├── alu.scala │ ├── arbiter.scala │ ├── consts.scala │ ├── core.scala │ ├── cpath.scala │ ├── dpath.scala │ ├── frontend.scala │ ├── tile.scala │ └── top.scala ├── rv32_5stage │ ├── consts.scala │ ├── core.scala │ ├── cpath.scala │ ├── dpath.scala │ ├── regfile.scala │ ├── tile.scala │ └── top.scala ├── rv32_ucode │ ├── consts.scala │ ├── core.scala │ ├── cpath.scala │ ├── dpath.scala │ ├── microcode.scala │ ├── microcodecompiler.scala │ ├── tile.scala │ └── top.scala └── test │ ├── testdebug.scala │ └── testmemory.scala └── vsrc ├── AsyncReadMem.sv ├── SimDTM.v └── SyncMem.sv /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/.gitmodules -------------------------------------------------------------------------------- /Jenkinsfile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/Jenkinsfile -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/README.md -------------------------------------------------------------------------------- /doc/1stage.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/1stage.xml -------------------------------------------------------------------------------- /doc/2stage.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/2stage.xml -------------------------------------------------------------------------------- /doc/3stage.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/3stage.xml -------------------------------------------------------------------------------- /doc/5stage.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/5stage.xml -------------------------------------------------------------------------------- /doc/lab1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/lab1.pdf -------------------------------------------------------------------------------- /doc/overview.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/overview.xml -------------------------------------------------------------------------------- /doc/ucode.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/ucode.xml -------------------------------------------------------------------------------- /doc/zscale.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/zscale.pdf -------------------------------------------------------------------------------- /doc/zscale.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/doc/zscale.png -------------------------------------------------------------------------------- /emulator/common/Makefile.include: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/common/Makefile.include -------------------------------------------------------------------------------- /emulator/common/SimDTM.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/common/SimDTM.cc -------------------------------------------------------------------------------- /emulator/common/emulator.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/common/emulator.cpp -------------------------------------------------------------------------------- /emulator/common/verilator.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/common/verilator.h -------------------------------------------------------------------------------- /emulator/rv32_1stage/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/rv32_1stage/Makefile -------------------------------------------------------------------------------- /emulator/rv32_2stage/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/rv32_2stage/Makefile -------------------------------------------------------------------------------- /emulator/rv32_3stage/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/rv32_3stage/Makefile -------------------------------------------------------------------------------- /emulator/rv32_5stage/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/rv32_5stage/Makefile -------------------------------------------------------------------------------- /emulator/rv32_ucode/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/emulator/rv32_ucode/Makefile -------------------------------------------------------------------------------- /sbt-launch.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/sbt-launch.jar -------------------------------------------------------------------------------- /src/common/abstract_commands.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/abstract_commands.scala -------------------------------------------------------------------------------- /src/common/configurations.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/configurations.scala -------------------------------------------------------------------------------- /src/common/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/consts.scala -------------------------------------------------------------------------------- /src/common/csr.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/csr.scala -------------------------------------------------------------------------------- /src/common/debug.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/debug.scala -------------------------------------------------------------------------------- /src/common/dm_registers.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/dm_registers.scala -------------------------------------------------------------------------------- /src/common/instructions.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/instructions.scala -------------------------------------------------------------------------------- /src/common/memory.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/memory.scala -------------------------------------------------------------------------------- /src/common/util.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/common/util.scala -------------------------------------------------------------------------------- /src/rv32_1stage/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_1stage/consts.scala -------------------------------------------------------------------------------- /src/rv32_1stage/core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_1stage/core.scala -------------------------------------------------------------------------------- /src/rv32_1stage/cpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_1stage/cpath.scala -------------------------------------------------------------------------------- /src/rv32_1stage/dpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_1stage/dpath.scala -------------------------------------------------------------------------------- /src/rv32_1stage/tile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_1stage/tile.scala -------------------------------------------------------------------------------- /src/rv32_1stage/top.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_1stage/top.scala -------------------------------------------------------------------------------- /src/rv32_2stage/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_2stage/consts.scala -------------------------------------------------------------------------------- /src/rv32_2stage/core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_2stage/core.scala -------------------------------------------------------------------------------- /src/rv32_2stage/cpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_2stage/cpath.scala -------------------------------------------------------------------------------- /src/rv32_2stage/dpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_2stage/dpath.scala -------------------------------------------------------------------------------- /src/rv32_2stage/tile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_2stage/tile.scala -------------------------------------------------------------------------------- /src/rv32_2stage/top.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_2stage/top.scala -------------------------------------------------------------------------------- /src/rv32_3stage/alu.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/alu.scala -------------------------------------------------------------------------------- /src/rv32_3stage/arbiter.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/arbiter.scala -------------------------------------------------------------------------------- /src/rv32_3stage/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/consts.scala -------------------------------------------------------------------------------- /src/rv32_3stage/core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/core.scala -------------------------------------------------------------------------------- /src/rv32_3stage/cpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/cpath.scala -------------------------------------------------------------------------------- /src/rv32_3stage/dpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/dpath.scala -------------------------------------------------------------------------------- /src/rv32_3stage/frontend.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/frontend.scala -------------------------------------------------------------------------------- /src/rv32_3stage/tile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/tile.scala -------------------------------------------------------------------------------- /src/rv32_3stage/top.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_3stage/top.scala -------------------------------------------------------------------------------- /src/rv32_5stage/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/consts.scala -------------------------------------------------------------------------------- /src/rv32_5stage/core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/core.scala -------------------------------------------------------------------------------- /src/rv32_5stage/cpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/cpath.scala -------------------------------------------------------------------------------- /src/rv32_5stage/dpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/dpath.scala -------------------------------------------------------------------------------- /src/rv32_5stage/regfile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/regfile.scala -------------------------------------------------------------------------------- /src/rv32_5stage/tile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/tile.scala -------------------------------------------------------------------------------- /src/rv32_5stage/top.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_5stage/top.scala -------------------------------------------------------------------------------- /src/rv32_ucode/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/consts.scala -------------------------------------------------------------------------------- /src/rv32_ucode/core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/core.scala -------------------------------------------------------------------------------- /src/rv32_ucode/cpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/cpath.scala -------------------------------------------------------------------------------- /src/rv32_ucode/dpath.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/dpath.scala -------------------------------------------------------------------------------- /src/rv32_ucode/microcode.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/microcode.scala -------------------------------------------------------------------------------- /src/rv32_ucode/microcodecompiler.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/microcodecompiler.scala -------------------------------------------------------------------------------- /src/rv32_ucode/tile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/tile.scala -------------------------------------------------------------------------------- /src/rv32_ucode/top.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/rv32_ucode/top.scala -------------------------------------------------------------------------------- /src/test/testdebug.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/test/testdebug.scala -------------------------------------------------------------------------------- /src/test/testmemory.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/src/test/testmemory.scala -------------------------------------------------------------------------------- /vsrc/AsyncReadMem.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/vsrc/AsyncReadMem.sv -------------------------------------------------------------------------------- /vsrc/SimDTM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/vsrc/SimDTM.v -------------------------------------------------------------------------------- /vsrc/SyncMem.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/librecores/riscv-sodor/HEAD/vsrc/SyncMem.sv --------------------------------------------------------------------------------