├── README.md ├── multicycleCPU54 ├── multicycleCPU54.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── multicycleCPU54.hw │ ├── hw_1 │ │ └── hw.xml │ ├── multicycleCPU54.lpr │ └── webtalk │ │ ├── .xsim_webtallk.info │ │ ├── labtool_webtalk.log │ │ ├── usage_statistics_ext_labtool.html │ │ └── usage_statistics_ext_labtool.xml ├── multicycleCPU54.ip_user_files │ ├── README.txt │ ├── ip │ │ ├── DMEM │ │ │ ├── DMEM.veo │ │ │ ├── DMEM.vho │ │ │ ├── DMEM_stub.v │ │ │ └── DMEM_stub.vhdl │ │ └── IMEM │ │ │ ├── IMEM.veo │ │ │ ├── IMEM.vho │ │ │ ├── IMEM_stub.v │ │ │ └── IMEM_stub.vhdl │ ├── ipstatic │ │ └── dist_mem_gen_v8_0_10 │ │ │ └── simulation │ │ │ └── dist_mem_gen_v8_0.v │ ├── mem_init_files │ │ ├── CP0test.coe │ │ ├── DMEM.coe │ │ ├── DMEM.mif │ │ ├── IMEM.mif │ │ ├── mips_54_mars_board_switch_student.coe │ │ └── mips_54_mars_simulate_student_ForWeb.coe │ └── sim_scripts │ │ ├── DMEM │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── DMEM.udo │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── DMEM.udo │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── DMEM.udo │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── DMEM.udo │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ └── xsim │ │ │ ├── DMEM.coe │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.sh │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ └── IMEM │ │ ├── README.txt │ │ ├── activehdl │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── IMEM.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ ├── modelsim │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── IMEM.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── IMEM.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── IMEM.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ └── xsim │ │ ├── CP0test.coe │ │ ├── IMEM.mif │ │ ├── IMEM.sh │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vlog.prj │ │ └── xsim.ini ├── multicycleCPU54.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_26.xml │ │ ├── vrs_config_27.xml │ │ ├── vrs_config_28.xml │ │ ├── vrs_config_29.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_30.xml │ │ ├── vrs_config_31.xml │ │ ├── vrs_config_32.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ ├── DMEM_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── DMEM.dcp │ │ ├── DMEM.tcl │ │ ├── DMEM.vds │ │ ├── DMEM_utilization_synth.pb │ │ ├── DMEM_utilization_synth.rpt │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── IMEM_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── IMEM.dcp │ │ ├── IMEM.tcl │ │ ├── IMEM.vds │ │ ├── IMEM_utilization_synth.pb │ │ ├── IMEM_utilization_synth.rpt │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── sccomp_dataflow_with_ipcore_11580.backup.vdi │ │ ├── top.bit │ │ ├── top.tcl │ │ ├── top.vdi │ │ ├── top_15304.backup.vdi │ │ ├── top_18000.backup.vdi │ │ ├── top_24176.backup.vdi │ │ ├── top_25844.backup.vdi │ │ ├── top_6780.backup.vdi │ │ ├── top_clock_utilization_routed.rpt │ │ ├── top_control_sets_placed.rpt │ │ ├── top_drc_opted.rpt │ │ ├── top_drc_routed.pb │ │ ├── top_drc_routed.rpt │ │ ├── top_io_placed.rpt │ │ ├── top_opt.dcp │ │ ├── top_placed.dcp │ │ ├── top_power_routed.rpt │ │ ├── top_power_routed.rpx │ │ ├── top_power_summary_routed.pb │ │ ├── top_route_status.pb │ │ ├── top_route_status.rpt │ │ ├── top_routed.dcp │ │ ├── top_timing_summary_routed.rpt │ │ ├── top_timing_summary_routed.rpx │ │ ├── top_utilization_placed.pb │ │ ├── top_utilization_placed.rpt │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ ├── vivado_11580.backup.jou │ │ ├── vivado_15304.backup.jou │ │ ├── vivado_24176.backup.jou │ │ ├── vivado_25844.backup.jou │ │ ├── vivado_6780.backup.jou │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── top_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── exception.log │ │ ├── fsm_encoding.os │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── sccomp_dataflow_with_ipcore_15836.backup.vds │ │ ├── sccomp_dataflow_with_ipcore_16352.backup.vds │ │ ├── top.dcp │ │ ├── top.tcl │ │ ├── top.vds │ │ ├── top_utilization_synth.pb │ │ ├── top_utilization_synth.rpt │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── vivado_15836.backup.jou ├── multicycleCPU54.sim │ └── sim_1 │ │ ├── behav │ │ ├── CP0test.coe │ │ ├── DMEM.coe │ │ ├── DMEM.mif │ │ ├── IMEM.mif │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── glbl.v │ │ ├── mips_54_mars_board_switch_student.coe │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ ├── modelsim.ini │ │ ├── msim │ │ │ ├── _info │ │ │ └── xil_defaultlib │ │ │ │ ├── _info │ │ │ │ ├── _lib.qdb │ │ │ │ ├── _lib1_0.qdb │ │ │ │ ├── _lib1_0.qpg │ │ │ │ ├── _lib1_0.qtl │ │ │ │ └── _vmake │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── test.udo │ │ ├── test_compile.do │ │ ├── test_simulate.do │ │ ├── test_wave.do │ │ ├── vsim.wlf │ │ └── work │ │ │ └── _info │ │ └── synth │ │ └── timing │ │ ├── CP0test.coe │ │ ├── DMEM.coe │ │ ├── DMEM.mif │ │ ├── IMEM.mif │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ ├── modelsim.ini │ │ ├── msim │ │ ├── _info │ │ └── xil_defaultlib │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_0.qdb │ │ │ ├── _lib1_0.qpg │ │ │ ├── _lib1_0.qtl │ │ │ └── _vmake │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── test_post_synthesis.udo │ │ ├── test_post_synthesis_compile.do │ │ ├── test_post_synthesis_simulate.do │ │ ├── test_post_synthesis_time_synth.sdf │ │ ├── test_post_synthesis_time_synth.sdf_typ.csd │ │ ├── test_post_synthesis_time_synth.v │ │ ├── test_post_synthesis_wave.do │ │ ├── vsim.wlf │ │ └── work │ │ └── _info ├── multicycleCPU54.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── icf.xdc │ ├── sim_1 │ │ └── new │ │ │ ├── cpu_tb.v │ │ │ └── cpu_tb_post_synthesis.v │ └── sources_1 │ │ ├── ip │ │ ├── DMEM │ │ │ ├── DMEM.dcp │ │ │ ├── DMEM.mif │ │ │ ├── DMEM.veo │ │ │ ├── DMEM.vho │ │ │ ├── DMEM.xci │ │ │ ├── DMEM.xml │ │ │ ├── DMEM_ooc.xdc │ │ │ ├── DMEM_sim_netlist.v │ │ │ ├── DMEM_sim_netlist.vhdl │ │ │ ├── DMEM_stub.v │ │ │ ├── DMEM_stub.vhdl │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ │ ├── hdl │ │ │ │ │ ├── dist_mem_gen_v8_0.vhd │ │ │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── dist_mem_gen_v8_0.v │ │ │ ├── doc │ │ │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ │ ├── sim │ │ │ │ └── DMEM.v │ │ │ └── synth │ │ │ │ └── DMEM.vhd │ │ └── IMEM │ │ │ ├── IMEM.dcp │ │ │ ├── IMEM.mif │ │ │ ├── IMEM.veo │ │ │ ├── IMEM.vho │ │ │ ├── IMEM.xci │ │ │ ├── IMEM.xml │ │ │ ├── IMEM_ooc.xdc │ │ │ ├── IMEM_sim_netlist.v │ │ │ ├── IMEM_sim_netlist.vhdl │ │ │ ├── IMEM_stub.v │ │ │ ├── IMEM_stub.vhdl │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ ├── hdl │ │ │ │ ├── dist_mem_gen_v8_0.vhd │ │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ │ └── simulation │ │ │ │ └── dist_mem_gen_v8_0.v │ │ │ ├── doc │ │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ │ ├── sim │ │ │ └── IMEM.v │ │ │ └── synth │ │ │ └── IMEM.vhd │ │ └── new │ │ ├── ADD.v │ │ ├── ADDU.v │ │ ├── AND.v │ │ ├── Asynchronous_D_FF.v │ │ ├── II.v │ │ ├── LUI.v │ │ ├── NOR.v │ │ ├── OR.v │ │ ├── SLLSLR.v │ │ ├── SLT.v │ │ ├── SLTU.v │ │ ├── SRA.v │ │ ├── SRL.v │ │ ├── SUB.v │ │ ├── SUBU.v │ │ ├── XOR.v │ │ ├── alu.v │ │ ├── clz.v │ │ ├── complement.v │ │ ├── cp0.v │ │ ├── cpmem.v │ │ ├── cpu.v │ │ ├── cu.v │ │ ├── decoder.v │ │ ├── div.v │ │ ├── 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