├── LICENSE ├── README.assets ├── example.png ├── image-20230518211228482.png ├── image-20230518211305285.png ├── image-20230518211349526.png ├── image-20230518211425095.png ├── image-20230518211525845.png ├── image-20230518211558057.png ├── image-20230518211617652.png └── image-20230518211631655.png ├── README.md ├── Wishbone ├── Wishbone.cache │ ├── ip │ │ └── 2020.2 │ │ │ ├── 0dc8f7dabe002cd7 │ │ │ ├── 0dc8f7dabe002cd7.xci │ │ │ ├── dist_mem_gen_0.dcp │ │ │ ├── dist_mem_gen_0_sim_netlist.v │ │ │ ├── dist_mem_gen_0_sim_netlist.vhdl │ │ │ ├── dist_mem_gen_0_stub.v │ │ │ └── dist_mem_gen_0_stub.vhdl │ │ │ ├── 2e3544930bd9429d │ │ │ ├── 2e3544930bd9429d.xci │ │ │ ├── clk_wiz_200MHZ.dcp │ │ │ ├── clk_wiz_200MHZ_sim_netlist.v │ │ │ ├── clk_wiz_200MHZ_sim_netlist.vhdl │ │ │ ├── clk_wiz_200MHZ_stub.v │ │ │ └── clk_wiz_200MHZ_stub.vhdl │ │ │ ├── 573835d33ac6d806 │ │ │ ├── 573835d33ac6d806.xci │ │ │ ├── clk_wiz_25MHZ.dcp │ │ │ ├── clk_wiz_25MHZ_sim_netlist.v │ │ │ ├── clk_wiz_25MHZ_sim_netlist.vhdl │ │ │ ├── clk_wiz_25MHZ_stub.v │ │ │ └── clk_wiz_25MHZ_stub.vhdl │ │ │ ├── 64271aa26210cb63 │ │ │ ├── 64271aa26210cb63.xci │ │ │ ├── sdram.dcp │ │ │ ├── sdram_sim_netlist.v │ │ │ ├── sdram_sim_netlist.vhdl │ │ │ ├── sdram_stub.v │ │ │ └── sdram_stub.vhdl │ │ │ └── 7371866d533f4d24 │ │ │ ├── 7371866d533f4d24.xci │ │ │ ├── sd_buf.dcp │ │ │ ├── sd_buf_sim_netlist.v │ │ │ ├── sd_buf_sim_netlist.vhdl │ │ │ ├── sd_buf_stub.v │ │ │ └── sd_buf_stub.vhdl │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml ├── Wishbone.gen │ └── sources_1 │ │ └── ip │ │ ├── clk_wiz_200MHZ │ │ ├── clk_wiz_200MHZ.dcp │ │ ├── clk_wiz_200MHZ.v │ │ ├── clk_wiz_200MHZ.xdc │ │ ├── clk_wiz_200MHZ.xml │ │ ├── clk_wiz_200MHZ_board.xdc │ │ ├── clk_wiz_200MHZ_clk_wiz.v │ │ ├── clk_wiz_200MHZ_ooc.xdc │ │ ├── clk_wiz_200MHZ_sim_netlist.v │ │ ├── clk_wiz_200MHZ_sim_netlist.vhdl │ │ ├── clk_wiz_200MHZ_stub.v │ │ ├── clk_wiz_200MHZ_stub.vhdl │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ └── mmcm_pll_drp_func_us_plus_pll.vh │ │ ├── clk_wiz_25MHZ │ │ ├── clk_wiz_25MHZ.dcp │ │ ├── clk_wiz_25MHZ.v │ │ ├── clk_wiz_25MHZ.xdc │ │ ├── clk_wiz_25MHZ.xml │ │ ├── clk_wiz_25MHZ_board.xdc │ │ ├── clk_wiz_25MHZ_clk_wiz.v │ │ ├── clk_wiz_25MHZ_ooc.xdc │ │ ├── clk_wiz_25MHZ_sim_netlist.v │ │ ├── clk_wiz_25MHZ_sim_netlist.vhdl │ │ ├── clk_wiz_25MHZ_stub.v │ │ ├── clk_wiz_25MHZ_stub.vhdl │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ └── mmcm_pll_drp_func_us_plus_pll.vh │ │ ├── clk_wiz_5MHZ │ │ └── clk_wiz_5MHZ.xml │ │ ├── sd_buf │ │ ├── hdl │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ ├── sd_buf.dcp │ │ ├── sd_buf.xml │ │ ├── sd_buf_ooc.xdc │ │ ├── sd_buf_sim_netlist.v │ │ ├── sd_buf_sim_netlist.vhdl │ │ ├── sd_buf_stub.v │ │ ├── sd_buf_stub.vhdl │ │ └── synth │ │ │ └── sd_buf.vhd │ │ └── sdram │ │ ├── sdram.dcp │ │ ├── sdram.veo │ │ ├── sdram.xml │ │ ├── sdram │ │ ├── datasheet.txt │ │ ├── docs │ │ │ └── phy_only_support_readme.txt │ │ ├── example_design │ │ │ ├── par │ │ │ │ ├── compatible_ucf │ │ │ │ │ └── xc7a100ticsg324_pkg.xdc │ │ │ │ ├── example_top.xdc │ │ │ │ └── readme.txt │ │ │ ├── rtl │ │ │ │ ├── example_top.v │ │ │ │ └── traffic_gen │ │ │ │ │ ├── mig_7series_v4_2_afifo.v │ │ │ │ │ ├── mig_7series_v4_2_cmd_gen.v │ │ │ │ │ ├── mig_7series_v4_2_cmd_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_data_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_init_mem_pattern_ctr.v │ │ │ │ │ ├── mig_7series_v4_2_memc_flow_vcontrol.v │ │ │ │ │ ├── mig_7series_v4_2_memc_traffic_gen.v │ │ │ │ │ ├── mig_7series_v4_2_rd_data_gen.v │ │ │ │ │ ├── mig_7series_v4_2_read_data_path.v │ │ │ │ │ ├── mig_7series_v4_2_read_posted_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_s7ven_data_gen.v │ │ │ │ │ ├── mig_7series_v4_2_tg_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_tg_status.v │ │ │ │ │ ├── mig_7series_v4_2_traffic_gen_top.v │ │ │ │ │ ├── mig_7series_v4_2_vio_init_pattern_bram.v │ │ │ │ │ ├── mig_7series_v4_2_wr_data_gen.v │ │ │ │ │ └── mig_7series_v4_2_write_data_path.v │ │ │ └── sim │ │ │ │ ├── ddr2_model.v │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ ├── ies_run.sh │ │ │ │ ├── readme.txt │ │ │ │ ├── sim.do │ │ │ │ ├── sim_tb_top.v │ │ │ │ ├── vcs_run.sh │ │ │ │ ├── wiredly.v │ │ │ │ ├── xsim_files.prj │ │ │ │ ├── xsim_options.tcl │ │ │ │ └── xsim_run.bat │ │ ├── mig.prj │ │ └── user_design │ │ │ ├── constraints │ │ │ ├── compatible_ucf │ │ │ │ └── xc7a100ticsg324_pkg.xdc │ │ │ ├── sdram.xdc │ │ │ └── sdram_ooc.xdc │ │ │ └── rtl │ │ │ ├── clocking │ │ │ ├── mig_7series_v4_2_clk_ibuf.v │ │ │ ├── mig_7series_v4_2_infrastructure.v │ │ │ ├── mig_7series_v4_2_iodelay_ctrl.v │ │ │ └── mig_7series_v4_2_tempmon.v │ │ │ ├── controller │ │ │ ├── mig_7series_v4_2_arb_mux.v │ │ │ ├── mig_7series_v4_2_arb_row_col.v │ │ │ ├── mig_7series_v4_2_arb_select.v │ │ │ ├── mig_7series_v4_2_bank_cntrl.v │ │ │ ├── mig_7series_v4_2_bank_common.v │ │ │ ├── mig_7series_v4_2_bank_compare.v │ │ │ ├── mig_7series_v4_2_bank_mach.v │ │ │ ├── mig_7series_v4_2_bank_queue.v │ │ │ ├── mig_7series_v4_2_bank_state.v │ │ │ ├── mig_7series_v4_2_col_mach.v │ │ │ ├── mig_7series_v4_2_mc.v │ │ │ ├── mig_7series_v4_2_rank_cntrl.v │ │ │ ├── mig_7series_v4_2_rank_common.v │ │ │ ├── mig_7series_v4_2_rank_mach.v │ │ │ └── mig_7series_v4_2_round_robin_arb.v │ │ │ ├── ecc │ │ │ ├── mig_7series_v4_2_ecc_buf.v │ │ │ ├── mig_7series_v4_2_ecc_dec_fix.v │ │ │ ├── mig_7series_v4_2_ecc_gen.v │ │ │ ├── mig_7series_v4_2_ecc_merge_enc.v │ │ │ └── mig_7series_v4_2_fi_xor.v │ │ │ ├── ip_top │ │ │ ├── mig_7series_v4_2_mem_intfc.v │ │ │ └── mig_7series_v4_2_memc_ui_top_std.v │ │ │ ├── phy │ │ │ ├── mig_7series_v4_2_ddr_byte_group_io.v │ │ │ ├── mig_7series_v4_2_ddr_byte_lane.v │ │ │ ├── mig_7series_v4_2_ddr_calib_top.v │ │ │ ├── mig_7series_v4_2_ddr_if_post_fifo.v │ │ │ ├── mig_7series_v4_2_ddr_mc_phy.v │ │ │ ├── mig_7series_v4_2_ddr_mc_phy_wrapper.v │ │ │ ├── mig_7series_v4_2_ddr_of_pre_fifo.v │ │ │ ├── mig_7series_v4_2_ddr_phy_4lanes.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v │ │ │ ├── mig_7series_v4_2_ddr_phy_dqs_found_cal.v │ │ │ ├── mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v │ │ │ ├── mig_7series_v4_2_ddr_phy_init.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_cntlr.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_data.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_edge.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_lim.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_mux.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_samp.v │ │ │ ├── mig_7series_v4_2_ddr_phy_oclkdelay_cal.v │ │ │ ├── mig_7series_v4_2_ddr_phy_prbs_rdlvl.v │ │ │ ├── mig_7series_v4_2_ddr_phy_rdlvl.v │ │ │ ├── mig_7series_v4_2_ddr_phy_tempmon.v │ │ │ ├── mig_7series_v4_2_ddr_phy_top.v │ │ │ ├── mig_7series_v4_2_ddr_phy_wrcal.v │ │ │ ├── mig_7series_v4_2_ddr_phy_wrlvl.v │ │ │ ├── mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v │ │ │ ├── mig_7series_v4_2_ddr_prbs_gen.v │ │ │ ├── mig_7series_v4_2_poc_cc.v │ │ │ ├── mig_7series_v4_2_poc_edge_store.v │ │ │ ├── mig_7series_v4_2_poc_meta.v │ │ │ ├── mig_7series_v4_2_poc_pd.v │ │ │ ├── mig_7series_v4_2_poc_tap_base.v │ │ │ └── mig_7series_v4_2_poc_top.v │ │ │ ├── sdram.v │ │ │ ├── sdram_mig.v │ │ │ ├── sdram_mig_sim.v │ │ │ └── ui │ │ │ ├── mig_7series_v4_2_ui_cmd.v │ │ │ ├── mig_7series_v4_2_ui_rd_data.v │ │ │ ├── mig_7series_v4_2_ui_top.v │ │ │ └── mig_7series_v4_2_ui_wr_data.v │ │ ├── sdram_sim_netlist.v │ │ ├── sdram_sim_netlist.vhdl │ │ ├── sdram_stub.v │ │ ├── sdram_stub.vhdl │ │ ├── sdram_xmdf.tcl │ │ ├── xil_txt.in │ │ └── xil_txt.out ├── Wishbone.hw │ ├── Wishbone.lpr │ └── hw_1 │ │ └── hw.xml ├── Wishbone.ip_user_files │ ├── README.txt │ ├── ip │ │ ├── clk_wiz_200MHZ │ │ │ ├── clk_wiz_200MHZ.veo │ │ │ ├── clk_wiz_200MHZ_stub.v │ │ │ └── clk_wiz_200MHZ_stub.vhdl │ │ ├── clk_wiz_25MHZ │ │ │ ├── clk_wiz_25MHZ.veo │ │ │ ├── clk_wiz_25MHZ_stub.v │ │ │ └── clk_wiz_25MHZ_stub.vhdl │ │ ├── clk_wiz_5MHZ │ │ │ ├── clk_wiz_5MHZ.veo │ │ │ ├── clk_wiz_5MHZ_stub.v │ │ │ └── clk_wiz_5MHZ_stub.vhdl │ │ ├── sd_buf │ │ │ ├── sd_buf.veo │ │ │ ├── sd_buf.vho │ │ │ ├── sd_buf_stub.v │ │ │ └── sd_buf_stub.vhdl │ │ └── sdram │ │ │ ├── sdram.veo │ │ │ ├── sdram_stub.v │ │ │ └── sdram_stub.vhdl │ ├── mem_init_files │ │ ├── bigendian_mips.coe │ │ ├── dist_mem_gen_0.mif │ │ ├── loader.hex.coe │ │ ├── mig_a.prj │ │ ├── mig_b.prj │ │ └── test.coe │ └── sim_scripts │ │ ├── clk_wiz_200MHZ │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── clk_wiz_200MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── clk_wiz_200MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── modelsim.ini │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── clk_wiz_200MHZ.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── clk_wiz_200MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_200MHZ.sh │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ ├── clk_wiz_25MHZ │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── clk_wiz_25MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── clk_wiz_25MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── modelsim.ini │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── clk_wiz_25MHZ.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── clk_wiz_25MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_25MHZ.sh │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ ├── clk_wiz_5MHZ │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── clk_wiz_5MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── clk_wiz_5MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── clk_wiz_5MHZ.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── clk_wiz_5MHZ.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_5MHZ.sh │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ ├── sd_buf │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── sd_buf.sh │ │ │ ├── sd_buf.udo │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── run.f │ │ │ └── sd_buf.sh │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── sd_buf.sh │ │ │ ├── sd_buf.udo │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── sd_buf.sh │ │ │ ├── sd_buf.udo │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── sd_buf.sh │ │ │ ├── sd_buf.udo │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── sd_buf.sh │ │ │ └── simulate.do │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── run.f │ │ │ └── sd_buf.sh │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── sd_buf.sh │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ └── sdram │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── sdram.sh │ │ ├── sdram.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── run.f │ │ └── sdram.sh │ │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── sdram.sh │ │ ├── sdram.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── sdram.sh │ │ ├── sdram.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── sdram.sh │ │ ├── sdram.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── sdram.sh │ │ └── simulate.do │ │ ├── xcelium │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── run.f │ │ └── sdram.sh │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── mig_b.prj │ │ ├── sdram.sh │ │ ├── vlog.prj │ │ └── xsim.ini ├── Wishbone.sim │ └── sim_1 │ │ └── behav │ │ ├── modelsim │ │ ├── bigendian_mips.coe │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── cpu_test.udo │ │ ├── cpu_test_compile.do │ │ ├── cpu_test_simulate.do │ │ ├── cpu_test_wave.do │ │ ├── dist_mem_gen_0.mif │ │ ├── glbl.v │ │ ├── loader.hex.coe │ │ ├── modelsim.ini │ │ ├── modelsim_lib │ │ │ ├── msim │ │ │ │ ├── _info │ │ │ │ ├── dist_mem_gen_v8_0_13 │ │ │ │ │ ├── _info │ │ │ │ │ ├── _lib.qdb │ │ │ │ │ ├── _lib1_1.qdb │ │ │ │ │ ├── _lib1_1.qpg │ │ │ │ │ ├── _lib1_1.qtl │ │ │ │ │ └── _vmake │ │ │ │ ├── xil_defaultlib │ │ │ │ │ ├── _info │ │ │ │ │ ├── _lib.qdb │ │ │ │ │ ├── _lib1_14.qdb │ │ │ │ │ ├── _lib1_14.qpg │ │ │ │ │ ├── _lib1_14.qtl │ │ │ │ │ └── _vmake │ │ │ │ └── xpm │ │ │ │ │ ├── _info │ │ │ │ │ ├── _lib.qdb │ │ │ │ │ ├── _lib1_7.qdb │ │ │ │ │ ├── _lib1_7.qpg │ │ │ │ │ ├── _lib1_7.qtl │ │ │ │ │ └── _vmake │ │ │ └── work │ │ │ │ └── _info │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── test.coe │ │ └── vsim.wlf │ │ └── xsim │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── cpu_test.tcl │ │ ├── cpu_test_behav.wdb │ │ ├── cpu_test_vlog.prj │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── hs_err_pid22636.dmp │ │ ├── hs_err_pid22636.log │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── wb_conmax_top.tcl │ │ ├── wb_conmax_top_behav.wdb │ │ ├── wb_conmax_top_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_10584.backup.jou │ │ ├── webtalk_10584.backup.log │ │ ├── webtalk_11300.backup.jou │ │ ├── webtalk_11300.backup.log │ │ ├── webtalk_14112.backup.jou │ │ ├── webtalk_14112.backup.log │ │ ├── webtalk_18052.backup.jou │ │ ├── webtalk_18052.backup.log │ │ ├── webtalk_7816.backup.jou │ │ ├── webtalk_7816.backup.log │ │ ├── wishbone_tb.tcl │ │ ├── wishbone_tb_behav.wdb │ │ ├── wishbone_tb_vlog.prj │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── cpu_test_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.win64.obj │ │ │ │ ├── xsim_2.c │ │ │ │ └── xsim_2.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── wb_conmax_top_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── wishbone_tb_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @a@d@d.sdb │ │ │ ├── @a@d@d@u.sdb │ │ │ ├── @a@n@d.sdb │ │ │ ├── @ansynchronous.sdb │ │ │ ├── @l@lbit_reg.sdb │ │ │ ├── @l@u@i.sdb │ │ │ ├── @n@o@r.sdb │ │ │ ├── @o@r.sdb │ │ │ ├── @pipe@d@ereg.sdb │ │ │ ├── @pipe@e@mreg.sdb │ │ │ ├── @pipe@e@x@e.sdb │ │ │ ├── @pipe@i@d.sdb │ │ │ ├── @pipe@i@f.sdb │ │ │ ├── @pipe@i@r.sdb │ │ │ ├── @pipe@m@e@m.sdb │ │ │ ├── @pipe@m@wreg.sdb │ │ │ ├── @pipe@w@b.sdb │ │ │ ├── @s@l@l@s@l@r.sdb │ │ │ ├── @s@l@t.sdb │ │ │ ├── @s@l@t@u.sdb │ │ │ ├── @s@r@a.sdb │ │ │ ├── @s@r@l.sdb │ │ │ ├── @s@u@b.sdb │ │ │ ├── @s@u@b@u.sdb │ │ │ ├── @x@o@r.sdb │ │ │ ├── alu.sdb │ │ │ ├── alu_selector.sdb │ │ │ ├── clk_wiz_5@m@h@z.sdb │ │ │ ├── clk_wiz_5@m@h@z_clk_wiz.sdb │ │ │ ├── clo.sdb │ │ │ ├── clz.sdb │ │ │ ├── complement32.sdb │ │ │ ├── complement64.sdb │ │ │ ├── cp0.sdb │ │ │ ├── cpmem.sdb │ │ │ ├── cpu.sdb │ │ │ ├── cpu_test.sdb │ │ │ ├── cpu_top.sdb │ │ │ ├── cu.sdb │ │ │ ├── decoder.sdb │ │ │ ├── direct.sdb │ │ │ ├── div.sdb │ │ │ ├── divu.sdb │ │ │ ├── extend1.sdb │ │ │ ├── extend16.sdb │ │ │ ├── extend18.sdb │ │ │ ├── extend5.sdb │ │ │ ├── extend8.sdb │ │ │ ├── glbl.sdb │ │ │ ├── hi_lo_function.sdb │ │ │ ├── ii.sdb │ │ │ ├── mult.sdb │ │ │ ├── multu.sdb │ │ │ ├── mux2_32.sdb │ │ │ ├── mux_alu.sdb │ │ │ ├── mux_hi.sdb │ │ │ ├── mux_lo.sdb │ │ │ ├── mux_pc.sdb │ │ │ ├── mux_rf.sdb │ │ │ ├── npc.sdb │ │ │ ├── pcreg.sdb │ │ │ ├── predictor.sdb │ │ │ ├── regfile.sdb │ │ │ ├── wb_conmax_arb.sdb │ │ │ ├── wb_conmax_master_if.sdb │ │ │ ├── wb_conmax_msel.sdb │ │ │ ├── wb_conmax_pri_dec.sdb │ │ │ ├── wb_conmax_pri_enc.sdb │ │ │ ├── wb_conmax_rf.sdb │ │ │ ├── wb_conmax_slave_if.sdb │ │ │ ├── wb_conmax_top.sdb │ │ │ ├── wishbone_tb.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xsim.ini.bak │ │ ├── xvlog.log │ │ └── xvlog.pb ├── Wishbone.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── wb.xdc │ ├── sim_1 │ │ └── new │ │ │ ├── cpu_test.v │ │ │ └── wishbone_tb.v │ └── sources_1 │ │ ├── ip │ │ ├── clk_wiz_200MHZ │ │ │ └── clk_wiz_200MHZ.xci │ │ ├── clk_wiz_25MHZ │ │ │ └── clk_wiz_25MHZ.xci │ │ ├── clk_wiz_5MHZ │ │ │ └── clk_wiz_5MHZ.xci │ │ ├── sd_buf │ │ │ └── sd_buf.xci │ │ └── sdram │ │ │ ├── mig_a.prj │ │ │ ├── mig_b.prj │ │ │ └── sdram.xci │ │ └── new │ │ ├── cpu │ │ ├── Asynchronous_D_FF.v │ │ ├── II.v │ │ ├── LLbit_reg.v │ │ ├── PipeDEreg.v │ │ ├── PipeEMreg.v │ │ ├── PipeEXE.v │ │ ├── PipeID.v │ │ ├── PipeIF.v │ │ ├── PipeIR.v │ │ ├── PipeMEM.v │ │ ├── PipeMWreg.v │ │ ├── PipeWB.v │ │ ├── alu.v │ │ ├── clo.v │ │ ├── clz.v │ │ ├── complement.v │ │ ├── cp0.v │ │ ├── cpmem.v │ │ ├── cpu.v │ │ ├── cpu_defines.v │ │ ├── cpu_top.v │ │ ├── cu.v │ │ ├── decoder.v │ │ ├── direct.v │ │ ├── div.v │ │ ├── extend.v │ │ ├── hi_lo_function.v │ │ ├── mult.v │ │ ├── mux.v │ │ ├── npc.v │ │ ├── pcreg.v │ │ ├── predictor.v │ │ └── regfile.v │ │ ├── divider.v │ │ ├── flash │ │ ├── sd_func_controller.v │ │ └── sd_signal_controller.v │ │ ├── gpio │ │ ├── gpio_defines.v │ │ └── gpio_top.v │ │ ├── sdram │ │ ├── ddr2_func_controller.v │ │ └── ddr2_signal_controller.v │ │ ├── seg7x16.v │ │ ├── top.v │ │ ├── uart │ │ ├── raminfr.v │ │ ├── timescale.v │ │ ├── uart_debug_if.v │ │ ├── uart_defines.v │ │ ├── uart_receiver.v │ │ ├── uart_regs.v │ │ ├── uart_rfifo.v │ │ ├── uart_sync_flops.v │ │ ├── uart_tfifo.v │ │ ├── uart_top.v │ │ ├── uart_transmitter.v │ │ └── uart_wb.v │ │ └── wishbone │ │ ├── wb_conmax_arb.v │ │ ├── wb_conmax_defines.v │ │ ├── wb_conmax_master_if.v │ │ ├── wb_conmax_msel.v │ │ ├── wb_conmax_pri_dec.v │ │ ├── wb_conmax_pri_enc.v │ │ ├── wb_conmax_rf.v │ │ ├── wb_conmax_slave_if.v │ │ └── wb_conmax_top.v ├── Wishbone.xpr ├── bigendian_mips.coe ├── test.coe └── ucOSii.img └── μCOSii操作系统工程 ├── BinMerge.exe ├── BootLoader.bin ├── Makefile ├── Makefile~ ├── OS.bin ├── common ├── Makefile ├── common.o ├── openmips.c ├── openmips.c~ └── openmips.o ├── config.mk ├── config.mk~ ├── include ├── app_cfg.h ├── cpu.h ├── includes.h ├── openmips.h ├── os_cfg.h ├── os_cpu.h └── ucos_ii.h ├── port ├── Makefile ├── os_cpu_a.S ├── os_cpu_a.S~ ├── os_cpu_a.o ├── os_cpu_c.c ├── os_cpu_c.o └── port.o ├── ram.ld ├── ucos ├── Makefile ├── os_cfg_r.h ├── os_core.c ├── os_core.o ├── os_dbg_r.c ├── os_dbg_r.o ├── os_flag.c ├── os_flag.o ├── os_mbox.c ├── os_mbox.o ├── os_mem.c ├── os_mem.o ├── os_mutex.c ├── os_mutex.o ├── os_q.c ├── os_q.o ├── os_sem.c ├── os_sem.o ├── os_task.c ├── os_task.o ├── os_time.c ├── os_time.o ├── os_tmr.c ├── os_tmr.o ├── ucos.o ├── ucos_ii.c └── ucos_ii.h ├── ucosii.asm ├── ucosii.bin ├── ucosii.om └── 说明.txt /LICENSE: -------------------------------------------------------------------------------- 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