├── README.md ├── cpu ├── Makefile ├── NOTES.txt ├── README ├── focal.v ├── maketraces.sh ├── pdp8.v ├── pdp8_io.v ├── pdp8_ram.v ├── ram_32kx12.v └── run.v ├── images ├── bintotxt.c ├── focal.lst ├── focal.pal └── focal569.bin ├── pdf ├── 1966_PDP8_UsersHandbook.pdf ├── DEC-08-HIEA-DA_RF08_Jun70.pdf ├── SmallComputerHandbook_1970.pdf └── kt8-a.pdf ├── pli ├── disassemble │ ├── Makefile │ ├── pli_disassemble.c │ └── win32.bat ├── ide │ ├── Makefile │ ├── pli_ide.c │ └── win32.bat └── rf │ ├── Makefile │ ├── pli_ram.c │ ├── pli_rf.c │ └── win32.bat ├── rom ├── Makefile ├── rom.mem ├── rom.pal ├── uart.mem └── uart.pal ├── rtl ├── NOTES.txt ├── bootrom.v ├── brg.v ├── debounce.v ├── display.v ├── ide.v ├── ide_disk.v ├── pdp8.v ├── pdp8_io.v ├── pdp8_kw.v ├── pdp8_ram.v ├── pdp8_rf.v ├── pdp8_tt.v ├── ram_256x12.v ├── ram_32kx12.v ├── sevensegdecode.v ├── top.v └── uart.v ├── sim ├── Makefile ├── a.out ├── io.c ├── m.c ├── pdp8.c ├── replay.sh └── tss8.cmd ├── simhv36-1 ├── 0readme_36.txt ├── 0readme_ethernet.txt ├── BIN │ ├── pdp1 │ ├── pdp11 │ ├── pdp4 │ ├── pdp7 │ ├── pdp8 │ ├── vax │ ├── vax730 │ └── vax780 ├── PDP8 │ ├── pdp8_clk.c │ ├── pdp8_cpu.c │ ├── pdp8_defs.h │ ├── pdp8_df.c │ ├── pdp8_dt.c │ ├── pdp8_lp.c │ ├── pdp8_mt.c │ ├── pdp8_pt.c │ ├── pdp8_rf.c │ ├── pdp8_rk.c │ ├── pdp8_rl.c │ ├── pdp8_rx.c │ ├── pdp8_sys.c │ ├── pdp8_td.c │ ├── pdp8_tsc.c │ ├── pdp8_tt.c │ └── pdp8_ttx.c ├── build_mingw.bat ├── build_mingw_ether.bat ├── descrip.mms ├── makefile ├── scp.c ├── scp.h ├── sim_console.c ├── sim_console.h ├── sim_defs.h ├── sim_ether.c ├── sim_ether.h ├── sim_fio.c ├── sim_fio.h ├── sim_rev.h ├── sim_sock.c ├── sim_sock.h ├── sim_tape.c ├── sim_tape.h ├── sim_timer.c ├── sim_timer.h ├── sim_tmxr.c └── sim_tmxr.h ├── synth └── s3board.ucf ├── tests ├── Makefile ├── NOTES.txt ├── basic │ ├── Makefile │ ├── uart.pal │ └── user.pal ├── bin │ ├── MAINDEC-08-D1EB-PB.pt │ ├── MAINDEC-08-D1GD-PB.pt │ ├── MAINDEC-08-D1HA-PB.pt │ ├── MAINDEC-08-D5EB.bin │ ├── MAINDEC-08-D5FA.bin │ ├── MAINDEC-8I-D01C-PB.pt │ ├── MAINDEC-8I-D01C-PB.pt.fixed │ ├── MAINDEC-8I-D02B-PB.pt │ ├── MAINDEC-8I-D02B-PB.pt.fixed │ ├── MAINDEX-08-D1GB-PB.pt │ ├── MAINDEX-08-D1GB-PB.pt.fixed │ └── MAINDEX-08-D1GB.bin ├── diags │ ├── MAINDEC-08-D5EA.simh.script │ ├── MAINDEC-08-D5FA.simh.script │ ├── MAINDEC-8I-D01C.simh.script │ ├── MAINDEC-8I-D02B.simh.script │ ├── MAINDEX-08-D1GB.simh.script │ └── Makefile ├── pdf │ ├── MAINDEC-08-D02B-D.pdf │ ├── MAINDEC-08-D1GB-D.pdf │ ├── MAINDEC-8I-D01C-D.pdf │ └── MAINDEC-8I-D02B-D.pdf └── src │ ├── MAINDEC-08-D1GB-D.doc │ ├── MAINDEC-08-D1GB-D.pal │ ├── MAINDEC-8I-D01C-D.doc │ ├── MAINDEC-8I-D01C-D.pal │ ├── MAINDEC-8I-D02B-D.doc │ └── Makefile ├── tss8.2 ├── Makefile ├── NOTES.txt ├── README ├── fip.pal ├── init.pal ├── link.pal ├── melrose.pal ├── param.pal ├── si.pal └── ts8.pal ├── tss8.23 ├── ASM.BI ├── ASMJOB.BI ├── BATCH.SV ├── DOWN.PA ├── FD.PA ├── FIP.CM ├── FIP.PA ├── INIT.CM ├── INIT.PA ├── INIT.PA.1 ├── INIT.XD ├── INIT.XD.bin ├── Makefile ├── PARAM.PA ├── PHAM.PA ├── PHAM20.PA ├── PIP2.SV ├── SCAN.TE ├── SI.CM ├── SI.PA ├── TEST.BI ├── TS8.CM ├── TS8.PA ├── TS8II.CM ├── TS8II.PA ├── UWM.PA ├── fip.bin ├── fip.lst ├── init.bin ├── init.lst ├── orig │ ├── ASM.BI │ ├── ASMJOB.BI │ ├── BATCH.SV │ ├── DOWN.PA │ ├── FD.PA │ ├── FIP.CM │ ├── FIP.PA │ ├── INIT.CM │ ├── INIT.PA │ ├── INIT.XD │ ├── PARAM.PA │ ├── PHAM.PA │ ├── PHAM20.PA │ ├── PIP2.SV │ ├── SCAN.TE │ ├── SI.CM │ ├── SI.PA │ ├── TEST.BI │ ├── TS8.CM │ ├── TS8.PA │ ├── TS8II.CM │ ├── TS8II.PA │ └── UWM.PA ├── si.bin ├── si.lst ├── ts8.bin ├── ts8.lst ├── ts8ii.bin └── ts8ii.lst ├── tss8 ├── rf.dsk ├── rim.txt ├── system │ ├── NOTES.txt │ ├── README │ ├── fipa.pal │ ├── fipb.pal │ ├── fipc.pal │ ├── inita.pal │ ├── initb.pal │ ├── initc.pal │ ├── link.pal │ ├── param.pal │ ├── si.pal │ ├── ts8a.pal │ ├── ts8b.pal │ ├── ts8c.pal │ ├── ts8d.pal │ ├── ts8e.pal │ └── ts8f.pal ├── tss8_boostrap.txt ├── tss8_init.bin ├── tss8_init.v ├── tss8_rf.dsk └── tss8_rf.dsk.orig ├── tss8_uwm ├── COPY.BN ├── FIP.CM ├── FIP.PA ├── INIT.CM ├── INIT.PA ├── INIT.XD ├── INIT.XD.bin ├── Makefile ├── PARA.PA ├── PARB.PA ├── PARC.PA ├── PHAM.PA ├── SI.CM ├── SI.PA ├── TS8.PA ├── TS8II.PA ├── TS8II.PA.1 ├── UWM.PA ├── diffs.txt ├── fip.bin ├── fip.lst ├── init.bin ├── init.lst ├── orig-bitsavers │ ├── COPY.BN │ ├── FIP.CM │ ├── FIP.PA │ ├── INIT.CM │ ├── INIT.PA │ ├── INIT.XD │ ├── PARA.PA │ ├── PARB.PA │ ├── PARC.PA │ ├── PHAM.PA │ ├── SI.CM │ ├── SI.PA │ └── UWM.PA ├── orig-dectapes │ ├── ASM.BI │ ├── ASMJOB.BI │ ├── COPY.BN │ ├── DOWN.PA │ ├── FD.PA │ ├── FIP.CM │ ├── FIP.PA │ ├── GLITCH.TE │ ├── INIT.CM │ ├── INIT.PA │ ├── INIT.XD │ ├── LINKB.BI │ ├── LINKC.BI │ ├── LK.TE │ ├── PARA.PA │ ├── PARB.PA │ ├── PARC.PA │ ├── PHAM.PA │ ├── PIP2.SV │ ├── SI.CM │ ├── SI.PA │ ├── TECO.SV │ ├── TEST.BI │ ├── TS8.CM │ ├── TS8.PA │ ├── TS8II.CM │ ├── TS8II.PA │ ├── TSASM.BI │ ├── TSBLD.BI │ ├── TSBLD.PA │ ├── TSGEN.BI │ ├── TSLIST.BI │ ├── TVBAT.SV │ └── UWM.PA ├── si.bin ├── si.lst ├── ts8.bin ├── ts8.lst ├── ts8ii.bin └── ts8ii.lst ├── utils ├── Makefile ├── filer │ ├── Makefile │ ├── NOTES.txt │ ├── filer │ ├── filer.c │ ├── script │ ├── tss8_rf.dsk │ └── tss8_rf.dsk.orig ├── macro │ ├── Makefile │ ├── macro8x.1 │ └── macro8x.c ├── maker │ ├── Makefile │ ├── dump.orig │ ├── dump.src │ ├── maker.c │ ├── script │ ├── script2 │ ├── script3 │ ├── tss8.23.cmd │ ├── tss8.cmd │ └── tss8_uwm.cmd ├── pal │ └── PAL.EXE ├── showbin │ ├── Makefile │ └── showbin.c ├── skipz │ ├── Makefile │ └── skipz.c └── ushow │ ├── Makefile │ └── ushow.c ├── v ├── char_rom.v ├── crt.v ├── fpga.ucf ├── fpga.v ├── fpga2.ucf ├── fpga2.v ├── fpga3.v ├── programramdac.v ├── ps2.v ├── run.v ├── scancode.v ├── scancode2.v ├── scancode_rom.v ├── vga.v ├── vgacore.v ├── video_mem.v ├── video_ram.v └── xsa-200.ucf ├── verif ├── Makefile ├── NOTEs.txt ├── fake_ide.v ├── fake_ram.v ├── fake_uart.v ├── ram_s3board.v ├── run.sh ├── run_rf.sh ├── run_tt.sh ├── runtest.sh ├── test_io.v ├── test_pdp8.v ├── test_rf.v ├── test_top.v ├── test_tt.v ├── tss8.cmd ├── verilator.sh └── verilator_pdp8.v ├── verilator ├── ide.cpp ├── ram.cpp └── test.cpp └── xilinx ├── TODO.txt ├── pdp8 ├── .lso ├── _ngo │ └── netlist.lst ├── _xmsgs │ ├── bitgen.xmsgs │ ├── map.xmsgs │ ├── ngdbuild.xmsgs │ ├── par.xmsgs │ ├── trce.xmsgs │ └── xst.xmsgs ├── pdp8.ise ├── pdp8.ise_ISE_Backup ├── pdp8.ntrc_log ├── top.bgn ├── top.bit ├── top.bld ├── top.cmd_log ├── top.drc ├── top.lso ├── top.ncd ├── top.ngc ├── top.ngd ├── top.ngr ├── top.pad ├── top.par ├── top.pcf ├── top.prj ├── top.stx ├── top.syr ├── top.twr ├── top.twx ├── top.unroutes ├── top.ut ├── top.xpi ├── top.xst ├── top_last_par.ncd ├── top_map.mrp ├── top_map.ncd ├── top_map.ngm ├── top_pad.csv ├── top_pad.txt ├── top_prev_built.ngd ├── top_summary.html ├── top_usage.xml ├── top_vhdl.prj └── xst │ ├── dump.xst │ └── top.prj │ │ └── ntrc.scr │ └── work │ ├── hdllib.ref │ ├── vlg10 │ └── ide__disk.bin │ ├── vlg1A │ └── ide.bin │ ├── vlg1D │ └── debounce.bin │ ├── vlg2F │ └── pdp8__io.bin │ ├── vlg33 │ └── brg.bin │ ├── vlg37 │ └── ram__256x12.bin │ ├── vlg41 │ └── pdp8__kw.bin │ ├── vlg48 │ └── uart.bin │ ├── vlg53 │ └── pdp8__rf.bin │ ├── vlg5C │ └── pdp8.bin │ ├── vlg6B │ └── pdp8__tt.bin │ ├── vlg6F │ └── top.bin │ ├── vlg73 │ └── pdp8__ram.bin │ └── vlg7A │ └── ram__32kx12.bin ├── ps2 ├── _ngo │ └── netlist.lst ├── _xmsgs │ ├── bitgen.xmsgs │ ├── map.xmsgs │ ├── ngdbuild.xmsgs │ ├── par.xmsgs │ ├── trce.xmsgs │ └── xst.xmsgs ├── fpga.bgn ├── fpga.bit ├── fpga.bld ├── fpga.cmd_log ├── fpga.drc ├── fpga.lso ├── fpga.ncd ├── fpga.ngc ├── fpga.ngd ├── fpga.ngr ├── fpga.pad ├── fpga.par ├── fpga.pcf ├── fpga.prj ├── fpga.stx ├── fpga.syr ├── fpga.twr ├── fpga.twx ├── fpga.unroutes ├── fpga.ut ├── fpga.xpi ├── fpga.xst ├── fpga_last_par.ncd ├── fpga_map.mrp ├── fpga_map.ncd ├── fpga_map.ngm ├── fpga_pad.csv ├── fpga_pad.txt ├── fpga_summary.html ├── fpga_usage.xml ├── fpga_vhdl.prj ├── ps2.ise ├── ps2.ise_ISE_Backup ├── ps2.ntrc_log └── xst │ └── work │ ├── hdllib.ref │ ├── vlg22 │ └── fpga.bin │ └── vlg61 │ └── ps2.bin ├── scancode ├── _xmsgs │ └── xst.xmsgs ├── fpga.cmd_log ├── fpga.lso ├── fpga.ngc ├── fpga.ngr ├── fpga.prj ├── fpga.stx ├── fpga.syr ├── fpga.xst ├── fpga_summary.html ├── fpga_vhdl.prj ├── scancode.ise ├── scancode.ise_ISE_Backup └── xst │ └── work │ ├── hdllib.ref │ ├── vlg22 │ └── fpga.bin │ ├── vlg34 │ └── test.bin │ ├── vlg39 │ └── scancode__rom.bin │ └── vlg3C │ └── scancode__convert.bin ├── scancode2 ├── _xmsgs │ └── xst.xmsgs ├── fpga.cmd_log ├── fpga.lso ├── fpga.prj ├── fpga.syr ├── fpga.xst ├── fpga_summary.html ├── fpga_vhdl.prj ├── scancode2.ise ├── scancode2.ise_ISE_Backup └── xst │ └── work │ ├── hdllib.ref │ ├── vlg22 │ └── fpga.bin │ ├── vlg34 │ └── test.bin │ ├── vlg39 │ └── scancode__rom.bin │ └── vlg3C │ └── scancode__convert.bin └── vga ├── __ISE_repository_vga.ise_.lock ├── _ngo └── netlist.lst ├── _xmsgs ├── bitgen.xmsgs ├── map.xmsgs ├── netgen.xmsgs ├── ngdbuild.xmsgs ├── par.xmsgs ├── trce.xmsgs └── xst.xmsgs ├── fpga.bgn ├── fpga.bit ├── fpga.bld ├── fpga.cmd_log ├── fpga.drc ├── fpga.lso ├── fpga.ncd ├── fpga.ngc ├── fpga.ngd ├── fpga.ngr ├── fpga.pad ├── fpga.par ├── fpga.pcf ├── fpga.prj ├── fpga.stx ├── fpga.syr ├── fpga.twr ├── fpga.twx ├── fpga.unroutes ├── fpga.ut ├── fpga.xpi ├── fpga.xst ├── fpga_last_par.ncd ├── fpga_map.mrp ├── fpga_map.ncd ├── fpga_map.ngm ├── fpga_pad.csv ├── fpga_pad.txt ├── fpga_summary.html ├── fpga_usage.xml ├── fpga_vhdl.prj ├── netgen ├── par │ ├── fpga_timesim.nlf │ ├── fpga_timesim.sdf │ └── fpga_timesim.v └── synthesis │ ├── fpga_synthesis.nlf │ ├── fpga_synthesis.v │ ├── go.sh │ └── verilog.log ├── vga.ise ├── vga.ise_ISE_Backup ├── vga.ntrc_log └── xst └── work ├── hdllib.ref ├── vlg13 └── char__rom.bin ├── vlg17 └── vgacore.bin ├── vlg22 └── fpga.bin ├── vlg39 └── scancode__rom.bin ├── vlg3C └── scancode__convert.bin ├── vlg59 └── crt.bin ├── vlg61 └── ps2.bin ├── vlg6A └── vga.bin └── vlg6E └── video__ram.bin /README.md: -------------------------------------------------------------------------------- 1 | # cpus-pdp8 2 | Verilog FPGA PDP-8/i cpu 3 | 4 | A working PDP-8/i cpu with an RF08 disk emulator which uses a IDE disk as a backing store. It boots TSS/8. 5 | 6 | Included are several versions of TSS/8 sources with utilites to build the base o/s from scratch. 7 | 8 | A base file system with utilties is required as I have not yet found all the sources for the base utilties. 9 | 10 | 11 | -------------------------------------------------------------------------------- /cpu/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # 3 | # 4 | 5 | IVERILOG=iverilog 6 | VERILOG=cver 7 | 8 | #all: igo 9 | all: go 10 | 11 | pdp8.o: pdp8.v 12 | $(VERILOG) -o pdp8.o $(PARTS) 13 | 14 | irun: $(PARTS) run.v pdp8.v 15 | $(IVERILOG) -o run run.v 16 | 17 | crun: $(PARTS) run.v pdp8.v 18 | $(VERILOG) +change_port_type run.v 19 | echo "exit 0" > run 20 | chmod +x run 21 | 22 | go: crun 23 | ./run 24 | 25 | igo: irun 26 | ./run 27 | 28 | display: 29 | ./maketraces.sh >traces 30 | gtkwave caddr.vcd traces 31 | 32 | snapshot: 33 | (suffix=`date +%Y%m%d`; \ 34 | cd ..; \ 35 | tar cfz pdp8_verilog_$$suffix.tar.gz pdp8/*.v pdp8/Makefile ; \ 36 | mv pdp8_verilog* ~/html/heeltoe/html/download/pdp8) 37 | -------------------------------------------------------------------------------- /cpu/README: -------------------------------------------------------------------------------- 1 | focal.v -cd win -------------------------------------------------------------------------------- /cpu/maketraces.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | -------------------------------------------------------------------------------- /cpu/pdp8_ram.v: -------------------------------------------------------------------------------- 1 | // 2 | 3 | `include "ram_32kx12.v" 4 | 5 | module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr); 6 | 7 | input clk; 8 | input reset; 9 | input [14:0] addr; 10 | input [11:0] data_in; 11 | output [11:0] data_out; 12 | input rd; 13 | input wr; 14 | 15 | 16 | ram_32kx12 ram(.A(addr), 17 | .DI(data_in), 18 | .DO(data_out), 19 | .CE_N(1'b0), 20 | .WE_N(~wr)); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /cpu/ram_32kx12.v: -------------------------------------------------------------------------------- 1 | 2 | /* 32kx12 static ram */ 3 | module ram_32kx12(A, DI, DO, CE_N, WE_N); 4 | 5 | input[14:0] A; 6 | input[11:0] DI; 7 | input CE_N, WE_N; 8 | output[11:0] DO; 9 | 10 | reg[11:0] ram [0:32767]; 11 | integer i; 12 | 13 | initial 14 | begin 15 | for (i = 0; i < 32768; i=i+1) 16 | ram[i] = 12'b0; 17 | 18 | ram[15'o0000] = 12'o5177; 19 | ram[15'o0200] = 12'o7300; 20 | ram[15'o0201] = 12'o1300; 21 | ram[15'o0202] = 12'o1301; 22 | ram[15'o0203] = 12'o3302; 23 | ram[15'o0204] = 12'o7402; 24 | ram[15'o0205] = 12'o5200; 25 | 26 | `include "focal.v" 27 | ram[15'o0000] = 12'o5404; 28 | ram[15'o0004] = 12'o0200; 29 | end 30 | 31 | always @(WE_N or CE_N or A or DI) 32 | begin 33 | if (WE_N == 0 && CE_N == 0) 34 | begin 35 | $display("ram: write [%o] <- %o", A, DI); 36 | ram[ A ] = DI; 37 | end 38 | end 39 | 40 | //always @(A) 41 | // begin 42 | // $display("ram: ce %b, we %b [%o] -> %o", CE_N, WE_N, A, ram[A]); 43 | // end 44 | 45 | // assign DO = ram[ A ]; 46 | assign DO = (^A === 1'bX || A === 1'bz) ? ram[0] : ram[A]; 47 | 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /cpu/run.v: -------------------------------------------------------------------------------- 1 | // run.v 2 | // testing top end for pdp8.v 3 | // 4 | 5 | `include "pdp8.v" 6 | `include "pdp8_io.v" 7 | `include "pdp8_ram.v" 8 | 9 | `timescale 1ns / 1ns 10 | 11 | module test; 12 | 13 | reg clk, reset; 14 | reg [11:0] switches; 15 | 16 | wire [11:0] ram_data_in; 17 | wire ram_rd; 18 | wire ram_wr; 19 | wire [11:0] ram_data_out; 20 | wire [14:0] ram_addr; 21 | wire [11:0] io_data_in; 22 | wire [11:0] io_data_out; 23 | wire [11:0] io_addr; 24 | wire io_data_avail; 25 | wire io_interrupt; 26 | wire io_skip; 27 | wire [5:0] io_select; 28 | 29 | wire iot; 30 | wire [3:0] state; 31 | wire [11:0] mb; 32 | 33 | pdp8 cpu(.clk(clk), 34 | .reset(reset), 35 | .ram_addr(ram_addr), 36 | .ram_data_in(ram_data_out), 37 | .ram_data_out(ram_data_in), 38 | .ram_rd(ram_rd), 39 | .ram_wr(ram_wr), 40 | .state(state), 41 | .io_select(io_select), 42 | .io_data_in(io_data_in), 43 | .io_data_out(io_data_out), 44 | .io_data_avail(io_data_avail), 45 | .io_interrupt(io_interrupt), 46 | .io_skip(io_skip), 47 | .iot(iot), 48 | .mb(mb), 49 | .switches(switches)); 50 | 51 | pdp8_io io(.clk(clk), 52 | .reset(reset), 53 | .iot(iot), 54 | .state(state), 55 | .mb(mb), 56 | .io_data_in(io_data_out), 57 | .io_data_out(io_data_in), 58 | .io_select(io_select), 59 | .io_data_avail(io_data_avail), 60 | .io_interrupt(io_interrupt), 61 | .io_skip(io_skip)); 62 | 63 | pdp8_ram ram(.clk(clk), 64 | .reset(reset), 65 | .addr(ram_addr), 66 | .data_in(ram_data_in), 67 | .data_out(ram_data_out), 68 | .rd(ram_rd), 69 | .wr(ram_wr)); 70 | 71 | 72 | initial 73 | begin 74 | $timeformat(-9, 0, "ns", 7); 75 | 76 | $dumpfile("pdp8.vcd"); 77 | $dumpvars(0, test.cpu); 78 | end 79 | 80 | initial 81 | begin 82 | clk = 0; 83 | reset = 0; 84 | 85 | #1 begin 86 | reset = 1; 87 | end 88 | 89 | #50 begin 90 | reset = 0; 91 | end 92 | 93 | #3000000 $finish; 94 | end 95 | 96 | always 97 | begin 98 | #10 clk = 0; 99 | #10 clk = 1; 100 | end 101 | 102 | //---- 103 | integer cycle; 104 | 105 | initial 106 | cycle = 0; 107 | 108 | always @(posedge cpu.clk) 109 | if (cpu.state == 4'b0000) 110 | begin 111 | cycle = cycle + 1; 112 | // #1 $display("#%d, r%b s%d, pc %o ir%o ma %o mb %o j%b l%b ac %o, i%b/%b", 113 | // cycle, cpu.run, cpu.state, cpu.pc, 114 | // cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac, 115 | // cpu.interrupt_enable, cpu.interrupt); 116 | //#1 $display(" io_data_in %o, io_data_out %o", 117 | //io_data_in, io_data_out); 118 | 119 | #1 $display("pc %o ir %o l %b ac %o ion %o", 120 | cpu.pc, cpu.mb, cpu.l, cpu.ac, cpu.interrupt_enable); 121 | 122 | if (state == 4'b1100) 123 | $finish; 124 | end 125 | 126 | endmodule 127 | 128 | -------------------------------------------------------------------------------- /images/bintotxt.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define MEMSIZE 32*1024 4 | int M[32*1024]; 5 | 6 | main() 7 | { 8 | int i; 9 | int rubout, newf, state, high, low, word, csum; 10 | int field, origin; 11 | 12 | rubout = 0; 13 | newf = 0; 14 | state = 0; 15 | csum = 0; 16 | 17 | while ((i = getchar()) != EOF) { /* BIN format */ 18 | if (rubout) { 19 | rubout = 0; 20 | continue; } 21 | if (i == 0377) { 22 | rubout = 1; 23 | continue; } 24 | if (i > 0200) { 25 | newf = (i & 070) << 9; 26 | continue; } 27 | switch (state) { 28 | case 0: /* leader */ 29 | if ((i != 0) && (i != 0200)) state = 1; 30 | high = i; /* save as high */ 31 | break; 32 | case 1: /* low byte */ 33 | low = i; 34 | state = 2; 35 | break; 36 | case 2: /* high with test */ 37 | word = (high << 6) | low; 38 | if (i == 0200) { /* end of tape? */ 39 | if ((csum - word) & 07777) { 40 | printf("checksum bad\n"); 41 | goto done; 42 | } 43 | 44 | printf("checksum ok\n"); 45 | goto done; 46 | } 47 | csum = csum + low + high; 48 | if (word >= 010000) origin = word & 07777; 49 | else { 50 | if ((field | origin) >= MEMSIZE) { 51 | printf("SCPE_NXM\n"); 52 | } 53 | 54 | M[field | origin] = word & 07777; 55 | printf("ram[12'o%o] = 12'o%o;\n", 56 | field | origin, word & 07777); 57 | 58 | origin = (origin + 1) & 07777; 59 | } 60 | field = newf; 61 | high = i; 62 | state = 1; 63 | break; 64 | } /* end switch */ 65 | } /* end while */ 66 | 67 | done: 68 | exit(0); 69 | } 70 | -------------------------------------------------------------------------------- /images/focal569.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/images/focal569.bin -------------------------------------------------------------------------------- /pdf/1966_PDP8_UsersHandbook.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/pdf/1966_PDP8_UsersHandbook.pdf -------------------------------------------------------------------------------- /pdf/DEC-08-HIEA-DA_RF08_Jun70.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/pdf/DEC-08-HIEA-DA_RF08_Jun70.pdf -------------------------------------------------------------------------------- /pdf/SmallComputerHandbook_1970.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/pdf/SmallComputerHandbook_1970.pdf -------------------------------------------------------------------------------- /pdf/kt8-a.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/pdf/kt8-a.pdf -------------------------------------------------------------------------------- /pli/disassemble/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | 3 | INCS = -I../../cver/gplcver-2.12a.src/pli_incs 4 | 5 | CFLAGS= -fPIC -Wall -g $(INCS) -D__CVER__ 6 | LFLAGS= -G -shared -export-dynamic 7 | 8 | all: pli_disassemble.so pli_disassemble.vpi 9 | 10 | pli_disassemble.o: pli_disassemble.c 11 | $(CC) $(CFLAGS) -c pli_disassemble.c 12 | 13 | pli_disassemble.so: pli_disassemble.o 14 | $(LD) $(LFLAGS) pli_disassemble.o -o pli_disassemble.so 15 | 16 | pli_disassemble.vpi: pli_disassemble.o 17 | $(LD) $(LFLAGS) pli_disassemble.o -o pli_disassemble.vpi 18 | 19 | clean: 20 | rm -f *.o *.so *.vpi 21 | -------------------------------------------------------------------------------- /pli/disassemble/win32.bat: -------------------------------------------------------------------------------- 1 | rem c:\program files\microsoft visual studio\vcvars32.bat 2 | 3 | set MTI_HOME=c:\Modeltech_6.2g 4 | 5 | cl -c -I%MTI_HOME%\include -D__MODELSIM__ pli_disassemble.c 6 | link -dll -export:vlog_startup_routines pli_disassemble.obj %MTI_HOME%\win32\mtipli.lib 7 | -------------------------------------------------------------------------------- /pli/ide/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | 3 | INCS = -I../../cver/gplcver-2.12a.src/pli_incs 4 | 5 | CFLAGS= -fPIC -Wall -g $(INCS) -D__CVER__ 6 | LFLAGS= -G -shared -export-dynamic 7 | 8 | all: pli_ide.so pli_ide.vpi 9 | 10 | pli_ide.o: pli_ide.c 11 | $(CC) $(CFLAGS) -c pli_ide.c 12 | 13 | pli_ide.so: pli_ide.o 14 | $(LD) $(LFLAGS) pli_ide.o -o pli_ide.so 15 | 16 | pli_ide.vpi: pli_ide.o 17 | $(LD) $(LFLAGS) pli_ide.o -o pli_ide.vpi 18 | 19 | clean: 20 | rm -f *.o *.so *.vpi 21 | -------------------------------------------------------------------------------- /pli/ide/win32.bat: -------------------------------------------------------------------------------- 1 | rem c:\program files\microsoft visual studio\vcvars32.bat 2 | 3 | set MTI_HOME=c:\Modeltech_6.2g 4 | 5 | cl -c -I%MTI_HOME%\include -D__MODELSIM__ pli_ide.c 6 | link -dll -export:vlog_startup_routines pli_ide.obj %MTI_HOME%\win32\mtipli.lib 7 | -------------------------------------------------------------------------------- /pli/rf/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | 3 | INCS = -I../../cver/gplcver-2.12a.src/pli_incs 4 | 5 | CFLAGS= -fPIC -Wall -g $(INCS) -D__CVER__ 6 | LFLAGS= -G -shared -export-dynamic 7 | 8 | all: pli_rf.so pli_rf.vpi 9 | 10 | pli_rf.o: pli_rf.c 11 | $(CC) $(CFLAGS) -c pli_rf.c 12 | 13 | pli_ram.o: pli_ram.c 14 | $(CC) $(CFLAGS) -c pli_ram.c 15 | 16 | pli_rf.so: pli_rf.o pli_ram.o 17 | $(LD) $(LFLAGS) pli_rf.o pli_ram.o -o pli_rf.so 18 | 19 | pli_rf.vpi: pli_rf.o pli_ram.o 20 | $(LD) $(LFLAGS) pli_rf.o pli_ram.o -o pli_rf.vpi 21 | 22 | 23 | clean: 24 | rm -f *.o *.so *.vpi 25 | 26 | -------------------------------------------------------------------------------- /pli/rf/win32.bat: -------------------------------------------------------------------------------- 1 | rem c:\program files\microsoft visual studio\vcvars32.bat 2 | 3 | set MTI_HOME=c:\Modeltech_6.2g 4 | 5 | cl -c -I%MTI_HOME%\include -D__MODELSIM__ pli_rf.c 6 | cl -c -I%MTI_HOME%\include -D__MODELSIM__ pli_ram.c 7 | link -dll -export:vlog_startup_routines pli_rf.obj pli_ram.obj %MTI_HOME%\win32\mtipli.lib 8 | -------------------------------------------------------------------------------- /rom/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: rom.mem uart.mem 3 | 4 | %.bin: %.pal 5 | ../utils/macro/macro8x $< 6 | 7 | %.mem: %.bin 8 | ../utils/showbin/showbin $< >$@ 9 | 10 | clean: 11 | rm -rf *.lst *.bin *.mem 12 | -------------------------------------------------------------------------------- /rom/rom.mem: -------------------------------------------------------------------------------- 1 | 07400 7240 2 | 07401 1224 3 | 07402 3010 4 | 07403 1217 5 | 07404 3410 6 | 07405 1220 7 | 07406 3410 8 | 07407 1221 9 | 07410 3410 10 | 07411 1222 11 | 07412 3410 12 | 07413 1223 13 | 07414 3410 14 | 07415 7300 15 | 07416 5624 16 | 07417 7600 17 | 07420 6603 18 | 07421 6622 19 | 07422 5352 20 | 07423 5752 21 | 07424 7750 22 | -------------------------------------------------------------------------------- /rom/rom.pal: -------------------------------------------------------------------------------- 1 | / ROM IS ONE PAGE AT 7400 - 7577 2 | 3 | *7400 4 | / copy tss/8 bootstram to ram and run it 5 | CLA CMA 6 | TAD DEST 7 | DCA 10 8 | 9 | TAD V1 10 | DCA I 10 11 | TAD V2 12 | DCA I 10 13 | TAD V3 14 | DCA I 10 15 | TAD V4 16 | DCA I 10 17 | TAD V5 18 | DCA I 10 19 | 20 | CLA CLL 21 | JMP I DEST 22 | 23 | /07750 7600 CLA 24 | /07751 6603 DMAR 25 | /07752 6622 DISK 26 | /07753 5352 JMP .-1 27 | /07754 5752 JMP I 7752 (6622) 28 | 29 | V1, 7600 30 | V2, 6603 31 | V3, 6622 32 | V4, 5352 33 | V5, 5752 34 | 35 | DEST, 7750 36 | 37 | 38 | -------------------------------------------------------------------------------- /rom/uart.mem: -------------------------------------------------------------------------------- 1 | 07400 7240 2 | 07401 1215 3 | 07402 3010 4 | 07403 1216 5 | 07404 3007 6 | 07405 7200 7 | 07406 1410 8 | 07407 6046 9 | 07410 6041 10 | 07411 5210 11 | 07412 2007 12 | 07413 5205 13 | 07414 5200 14 | 07415 7417 15 | 07416 7766 16 | 07417 0215 17 | 07420 0212 18 | 07421 0310 19 | 07422 0305 20 | 07423 0314 21 | 07424 0314 22 | 07425 0317 23 | 07426 0241 24 | 07427 0215 25 | 07430 0212 26 | -------------------------------------------------------------------------------- /rom/uart.pal: -------------------------------------------------------------------------------- 1 | / ROM IS ONE PAGE AT 7400 - 7577 2 | 3 | *7400 4 | / test uart 5 | START, 6 | CLA CMA 7 | 8 | TAD KMSG 9 | DCA 10 10 | 11 | TAD KLEN 12 | DCA 7 13 | 14 | LOOP, 15 | CLA 16 | TAD I 10 17 | TLS 18 | TSF 19 | JMP .-1 20 | 21 | ISZ 7 22 | JMP LOOP 23 | 24 | DONE, 25 | / JMP DONE 26 | JMP START 27 | 28 | 29 | KMSG, MSG 30 | KLEN, -12 31 | 32 | MSG, 215;212;"H;"E;"L;"L;"O;"!;215;212 33 | 34 | 35 | -------------------------------------------------------------------------------- /rtl/brg.v: -------------------------------------------------------------------------------- 1 | // brg.v 2 | // baud rate generator for uart 3 | 4 | module brg(clk, reset, tx_baud_clk, rx_baud_clk); 5 | 6 | input clk; 7 | input reset; 8 | output tx_baud_clk; 9 | output rx_baud_clk; 10 | 11 | parameter SYS_CLK = 26'd50000000; 12 | parameter BAUD = 16'd9600; 13 | 14 | `ifdef sim_time 15 | parameter RX_CLK_DIV = 13'd5; 16 | parameter TX_CLK_DIV = 13'd5; 17 | `else 18 | parameter RX_CLK_DIV = SYS_CLK / (BAUD * 16 * 2); 19 | parameter TX_CLK_DIV = SYS_CLK / (BAUD * 2); 20 | `endif 21 | 22 | reg [12:0] rx_clk_div; 23 | reg [12:0] tx_clk_div; 24 | reg tx_baud_clk; 25 | reg rx_baud_clk; 26 | 27 | 28 | always @(posedge clk or posedge reset) 29 | if (reset) 30 | begin 31 | rx_clk_div <= 0; 32 | rx_baud_clk <= 0; 33 | end 34 | else 35 | if (rx_clk_div == RX_CLK_DIV) 36 | begin 37 | rx_clk_div <= 0; 38 | rx_baud_clk <= ~rx_baud_clk; 39 | end 40 | else 41 | begin 42 | rx_clk_div <= rx_clk_div + 13'b1; 43 | rx_baud_clk <= rx_baud_clk; 44 | end 45 | 46 | always @(posedge clk or posedge reset) 47 | if (reset) 48 | begin 49 | tx_clk_div <= 0; 50 | tx_baud_clk <= 0; 51 | end 52 | else 53 | if (tx_clk_div == TX_CLK_DIV) 54 | begin 55 | tx_clk_div <= 0; 56 | tx_baud_clk <= ~tx_baud_clk; 57 | end 58 | else 59 | begin 60 | tx_clk_div <= tx_clk_div + 13'b1; 61 | tx_baud_clk <= tx_baud_clk; 62 | end 63 | 64 | endmodule 65 | 66 | 67 | -------------------------------------------------------------------------------- /rtl/debounce.v: -------------------------------------------------------------------------------- 1 | // debounce.v 2 | 3 | module debounce(clk, in, out); 4 | input clk; 5 | input in; 6 | output out; 7 | 8 | `ifdef sim_time 9 | reg [1:0] clkdiv; 10 | `else 11 | reg [14:0] clkdiv; 12 | `endif 13 | reg slowclk; 14 | reg [9:0] hold; 15 | reg onetime; 16 | 17 | initial 18 | begin 19 | onetime = 0; 20 | hold = 0; 21 | clkdiv = 0; 22 | slowclk = 0; 23 | end 24 | 25 | assign out = hold == 10'b1111111111 || ~onetime; 26 | 27 | always @(posedge clk) 28 | begin 29 | clkdiv <= clkdiv + 15'b1; 30 | if (clkdiv == 0) 31 | slowclk <= ~slowclk; 32 | end 33 | 34 | always @(posedge slowclk) 35 | begin 36 | hold <= { hold[8:0], in }; 37 | onetime <= 1; 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/display.v: -------------------------------------------------------------------------------- 1 | // display.v 2 | // display pc on led'and 4x7 segment digits 3 | 4 | module display(clk, reset, pc, dots, sevenseg, sevenseg_an); 5 | 6 | input clk; 7 | input reset; 8 | input [11:0] pc; 9 | input [3:0] dots; 10 | output [7:0] sevenseg; 11 | output [3:0] sevenseg_an; 12 | 13 | // 14 | wire [2:0] digit; 15 | reg [1:0] anode; 16 | 17 | reg [10:0] divider; 18 | reg aclk; 19 | 20 | assign digit = (anode == 2'b11) ? pc[11:9] : 21 | (anode == 2'b10) ? pc[8:6] : 22 | (anode == 2'b01) ? pc[5:3] : 23 | (anode == 2'b00) ? pc[2:0] : 24 | 3'b0; 25 | 26 | assign sevenseg_an = (anode == 2'b11) ? 4'b0111 : 27 | (anode == 2'b10) ? 4'b1011 : 28 | (anode == 2'b01) ? 4'b1101 : 29 | (anode == 2'b00) ? 4'b1110 : 30 | 4'b1111; 31 | 32 | 33 | assign sevenseg[0] = ~dots[anode]; 34 | 35 | sevensegdecode decode({1'b0, digit}, sevenseg[7:1]); 36 | 37 | always @(posedge clk) 38 | begin 39 | divider <= divider + 11'b1; 40 | if (divider == 0) 41 | aclk = ~aclk; 42 | end 43 | 44 | // digit scan clock 45 | always @(posedge aclk) 46 | anode <= anode + 1'b1; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /rtl/ide.v: -------------------------------------------------------------------------------- 1 | // 2 | // ide.v 3 | // simple state machine to do proper read & write cycles to ATA IDE device 4 | // 5 | 6 | module ide(clk, reset, ata_rd, ata_wr, ata_addr, ata_in, ata_out, ata_done, 7 | ide_data_in, ide_data_out, ide_dior, ide_diow, ide_cs, ide_da); 8 | 9 | input clk; 10 | input reset; 11 | 12 | input ata_rd; 13 | input ata_wr; 14 | input [4:0] ata_addr; 15 | input [15:0] ata_in; 16 | output [15:0] ata_out; 17 | reg [15:0] ata_out; 18 | output ata_done; 19 | 20 | input [15:0] ide_data_in; 21 | output [15:0] ide_data_out; 22 | output ide_dior; 23 | output ide_diow; 24 | output [1:0] ide_cs; 25 | output [2:0] ide_da; 26 | 27 | 28 | reg [2:0] ata_state; 29 | 30 | parameter [2:0] 31 | idle = 3'd0, 32 | s0 = 3'd1, 33 | s1 = 3'd2, 34 | s2 = 3'd3, 35 | s3 = 3'd4, 36 | s4 = 3'd5; 37 | 38 | wire assert_cs; 39 | wire assert_rw; 40 | 41 | reg [2:0] ata_state_next; 42 | 43 | 44 | // if write, drive ide_bus 45 | assign ide_data_out = (ata_wr && (ata_state == s0 || 46 | ata_state == s1 || 47 | ata_state == s2 || 48 | ata_state == s3)) ? ata_in : 16'b0; 49 | 50 | // assert cs & da during r/w cycle 51 | assign assert_cs = (ata_rd || ata_wr) && ata_state != s4; 52 | 53 | assign ide_cs = assert_cs ? ata_addr[4:3] : 2'b11; 54 | assign ide_da = assert_cs ? ata_addr[2:0] : 3'b111; 55 | 56 | // assert r/w one cycle sort 57 | assign assert_rw = ata_state == s0 || 58 | ata_state == s1 || 59 | ata_state == s2; 60 | 61 | assign ide_dior = (assert_rw && ata_rd) ? 1'b0 : 1'b1; 62 | assign ide_diow = (assert_rw && ata_wr) ? 1'b0 : 1'b1; 63 | 64 | // send back done pulse at end 65 | assign ata_done = ata_state == s3; 66 | 67 | always @(posedge clk) 68 | if (reset) 69 | ata_state <= idle; 70 | else 71 | ata_state <= ata_state_next; 72 | 73 | always @(clk or ata_state or ata_rd or ata_wr or ata_addr) 74 | begin 75 | case (ata_state) 76 | idle: 77 | begin 78 | if (ata_rd || ata_wr) 79 | ata_state_next = s0; 80 | else 81 | ata_state_next = idle; 82 | end 83 | 84 | s0: ata_state_next = s1; 85 | s1: ata_state_next = s2; 86 | s2: ata_state_next = s3; 87 | s3: ata_state_next = s4; 88 | s4: ata_state_next = idle; 89 | default: ata_state_next = idle; 90 | endcase 91 | end 92 | 93 | always @(posedge clk) 94 | if (reset) 95 | ata_out <= 0; 96 | else 97 | if (ata_state == s2 && ata_rd) 98 | ata_out <= ide_data_in; 99 | 100 | endmodule // ide 101 | -------------------------------------------------------------------------------- /rtl/pdp8_ram.v: -------------------------------------------------------------------------------- 1 | // 2 | // interface to async sram 3 | // used on s3board 4 | // 5 | // multiplexes between to high speed SRAMs 6 | // 7 | 8 | //`define use_sim_model 1 9 | 10 | module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr, 11 | sram_a, sram_oe_n, sram_we_n, 12 | sram1_io, sram1_ce_n, sram1_ub_n, sram1_lb_n, 13 | sram2_io, sram2_ce_n, sram2_ub_n, sram2_lb_n); 14 | 15 | input clk; 16 | input reset; 17 | input [14:0] addr; 18 | input [11:0] data_in; 19 | output [11:0] data_out; 20 | input rd; 21 | input wr; 22 | 23 | output [17:0] sram_a; 24 | output sram_oe_n, sram_we_n; 25 | inout [15:0] sram1_io; 26 | output sram1_ce_n, sram1_ub_n, sram1_lb_n; 27 | inout [15:0] sram2_io; 28 | output sram2_ce_n, sram2_ub_n, sram2_lb_n; 29 | 30 | // 31 | wire rom_decode; 32 | wire [11:0] rom_data; 33 | 34 | bootrom rom(.clk(clk), 35 | .reset(reset), 36 | .addr(addr), 37 | .data_out(rom_data), 38 | .rd(rd), 39 | .selected(rom_decode)); 40 | 41 | 42 | `ifdef use_sim_ram_model 43 | 44 | wire [11:0] sram_data_in; 45 | wire [11:0] sram_data_out; 46 | 47 | ram_32kx12 ram(.A(addr), 48 | .DI(sram_data_in), 49 | .DO(sram_data_out), 50 | .CE_N(1'b0), 51 | .WE_N(~wr)); 52 | 53 | assign sram_data_in = data_in; 54 | 55 | assign data_out = rom_decode ? rom_data : sram_data_out; 56 | 57 | // always @(posedge clk) 58 | // $display("addr %o, rom_decode %b %o", addr, rom_decode, rom_data); 59 | 60 | `else 61 | // 62 | wire sram1_ub, sram1_lb; 63 | 64 | // common 65 | assign sram_a = {3'b0, addr}; 66 | assign sram_oe_n = ~rd; 67 | assign sram_we_n = ~wr; 68 | 69 | // sram1 70 | assign sram1_ub = 1'b1; 71 | assign sram1_lb = 1'b1; 72 | 73 | assign sram1_ce_n = 1'b0; 74 | assign sram1_ub_n = ~sram1_ub; 75 | assign sram1_lb_n = ~sram1_lb; 76 | 77 | assign data_out = rom_decode ? rom_data : sram1_io[11:0]; 78 | assign sram1_io = ~sram_oe_n ? 16'bz : {4'b0, data_in}; 79 | 80 | // sram2 not used 81 | assign sram2_io = 16'b0; 82 | assign sram2_ce_n = 1'b1; 83 | assign sram2_ub_n = 1'b1; 84 | assign sram2_lb_n = 1'b1; 85 | `endif 86 | 87 | endmodule 88 | 89 | -------------------------------------------------------------------------------- /rtl/ram_256x12.v: -------------------------------------------------------------------------------- 1 | /* 256x12 static ram */ 2 | module ram_256x12(clk, reset, a, din, dout, ce, we); 3 | 4 | input clk; 5 | input reset; 6 | 7 | input [7:0] a; 8 | input [11:0] din; 9 | input ce, we; 10 | output [11:0] dout; 11 | 12 | reg [11:0] ram [0:255]; 13 | 14 | // synthesis translate_off 15 | integer i; 16 | `ifdef debug 17 | integer ram_debug; 18 | `endif 19 | 20 | initial 21 | begin 22 | for (i = 0; i < 256; i=i+1) 23 | ram[i] = 12'b0; 24 | end 25 | // synthesis translate_on 26 | 27 | always @(posedge clk) 28 | begin 29 | if (we && ce) 30 | begin 31 | `ifdef debug_rf_buffer 32 | if (ram_debug != 0) 33 | $display("rf: buffer ram write [%o] <- %o", a, din); 34 | `endif 35 | ram[a] = din; 36 | end 37 | 38 | `ifdef debug_rf_buffer 39 | if (ram_debug != 0&& we == 0 && ce == 1) 40 | $display("rf: buffer ram read [%o] -> %o", a, ram[a]); 41 | `endif 42 | end 43 | 44 | //`define is_async 45 | `ifdef is_async 46 | assign dout = ram[a]; 47 | `else 48 | reg [11:0] dout; 49 | 50 | always @(posedge clk) 51 | if (reset) 52 | dout <= 0; 53 | else 54 | if (~we && ce) 55 | dout <= ram[a]; 56 | `endif 57 | 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /rtl/ram_32kx12.v: -------------------------------------------------------------------------------- 1 | /* 32kx12 static ram */ 2 | module ram_32kx12(A, DI, DO, CE_N, WE_N); 3 | 4 | input[14:0] A; 5 | input[11:0] DI; 6 | input CE_N, WE_N; 7 | output[11:0] DO; 8 | 9 | reg[11:0] ram [0:32767]; 10 | 11 | // synthesis translate_off 12 | integer i; 13 | reg [11:0] v; 14 | reg [63:0] file; 15 | reg [1023:0] str; 16 | reg [1023:0] testfilename; 17 | integer n; 18 | 19 | initial 20 | begin 21 | for (i = 0; i < 32768; i=i+1) 22 | ram[i] = 12'b0; 23 | 24 | n = 0; 25 | 26 | `ifdef __ICARUS__ 27 | n = $value$plusargs("test=%s", testfilename); 28 | `endif 29 | 30 | `ifdef __CVER__ 31 | n = $scan$plusargs("test=", testfilename); 32 | `endif 33 | 34 | if (n == 0) 35 | begin 36 | testfilename = "../verif/default.mem"; 37 | n = 1; 38 | end 39 | 40 | if (n > 0) 41 | begin 42 | $display("ram: code filename: %s", testfilename); 43 | file = $fopen(testfilename, "r"); 44 | if (file > 0) 45 | begin 46 | while ($fscanf(file, "%o %o\n", i, v) > 0) 47 | begin 48 | $display("ram[%o] <- %o", i, v); 49 | ram[i] = v; 50 | end 51 | 52 | $display("ram: done reading"); 53 | $fclose(file); 54 | end 55 | end 56 | end 57 | // synthesis translate_on 58 | 59 | 60 | always @(WE_N or CE_N or A or DI) 61 | begin 62 | if (WE_N == 0 && CE_N == 0) 63 | begin 64 | `ifdef debug_ram 65 | $display("ram: write [%o] <- %o", A, DI); 66 | `endif 67 | ram[ A ] = DI; 68 | end 69 | 70 | `ifdef debug_ram_read 71 | if (WE_N == 1 && CE_N == 0) 72 | $display("ram: read [%o] -> %o", A, ram[A]); 73 | `endif 74 | end 75 | 76 | assign DO = ram[ A ]; 77 | // assign DO = (^A === 1'bX || A === 1'bz) ? ram[0] : ram[A]; 78 | 79 | endmodule 80 | 81 | -------------------------------------------------------------------------------- /rtl/sevensegdecode.v: -------------------------------------------------------------------------------- 1 | // sevensegdecode.v 2 | // seven segment decoder for s3board 3 | 4 | module sevensegdecode(digit, ss_out); 5 | 6 | input [3:0] digit; 7 | output [6:0] ss_out; 8 | 9 | // segments abcdefg 10 | // a 11 | // f b 12 | // g 13 | // e c 14 | // d 15 | 16 | assign ss_out = 17 | (digit == 4'd0) ? 7'b0000001 : 18 | (digit == 4'd1) ? 7'b1001111 : 19 | (digit == 4'd2) ? 7'b0010010 : 20 | (digit == 4'd3) ? 7'b0000110 : 21 | (digit == 4'd4) ? 7'b1001100 : 22 | (digit == 4'd5) ? 7'b0100100 : 23 | (digit == 4'd6) ? 7'b1100000 : 24 | (digit == 4'd7) ? 7'b0001111 : 25 | (digit == 4'd8) ? 7'b0000000 : 26 | (digit == 4'd9) ? 7'b0001100 : 27 | (digit == 4'ha) ? 7'b0001001 : 28 | (digit == 4'hb) ? 7'b1100000 : 29 | (digit == 4'hc) ? 7'b0110001 : 30 | (digit == 4'hd) ? 7'b1000010 : 31 | (digit == 4'he) ? 7'b0010000 : 32 | (digit == 4'hf) ? 7'b0111000 : 33 | 7'b1111111; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /sim/Makefile: -------------------------------------------------------------------------------- 1 | 2 | pdp8i: pdp8.c io.c 3 | cc -o pdp8i -g pdp8.c io.c 4 | -------------------------------------------------------------------------------- /sim/a.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/sim/a.out -------------------------------------------------------------------------------- /sim/io.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /sim/m.c: -------------------------------------------------------------------------------- 1 | #define bitmask(h,l) ((unsigned int)0xffffffff >> (31-(h-l)+1)) 2 | 3 | main() 4 | { 5 | #define bitmask(l) ((unsigned int)0xffffffff >> (32-(l))) 6 | printf("%08x ", bitmask(3)); 7 | printf("%08x ", bitmask(2)); 8 | printf("%08x ", bitmask(1)); 9 | } 10 | -------------------------------------------------------------------------------- /sim/replay.sh: -------------------------------------------------------------------------------- 1 | (cd ../simhv36-1; make BIN/pdp8) 2 | make 3 | ../simhv36-1/BIN/pdp8 tss8.cmd >simh.log 4 | ./pdp8i >8.log 5 | diff -u -d 8.log simh.log >d 6 | head -100000 d >d1 7 | ls -l *.log d d1 8 | -------------------------------------------------------------------------------- /sim/tss8.cmd: -------------------------------------------------------------------------------- 1 | load ../tss8/tss8_init.bin 2 | set df disabled 3 | set rf enabled 4 | att rf ../tss8/tss8_rf.dsk 5 | run 24200 6 | -------------------------------------------------------------------------------- /simhv36-1/0readme_36.txt: -------------------------------------------------------------------------------- 1 | Notes For V3.6-0 2 | 3 | The save/restore format has been updated to improve its reliability. 4 | As a result, save files prior to release 3.0 are no longer supported. 5 | 6 | The text documentation files are obsolete and are no longer included 7 | with the distribution. Up-to-date PDF documentation files are 8 | available on the SimH web site. 9 | 10 | 11 | 1. New Features 12 | 13 | 1.1 3.6-0 14 | 15 | 1.1.1 Most magnetic tapes 16 | 17 | - Added support for limiting tape capacity to a particular size in MB 18 | 19 | 1.1.2 IBM 7090/7094 20 | 21 | - First release 22 | 23 | 1.1.3 VAX-11/780 24 | 25 | - Added FLOAD command, loads system file from console floppy disk 26 | 27 | 1.1.4 VAX, VAX-11/780, and PDP-11 28 | 29 | - Added card reader support (from John Dundas) 30 | 31 | 1.1.5 PDP-11 32 | 33 | - Added instruction history 34 | 35 | 1.2 3.6-1 36 | 37 | 1.2.1 PDP-11 38 | 39 | - Added RF11 support 40 | - Added multiple KL11/DL11 support 41 | - Added upper-case only mode to TTI, TTO 42 | 43 | 1.2.2 44 | 45 | - Added binary loader (courtesy of Dave Pitt) 46 | 47 | 48 | 2. Bugs Fixed 49 | 50 | Please see the revision history on http://simh.trailing-edge.com or 51 | in the source module sim_rev.h. 52 | -------------------------------------------------------------------------------- /simhv36-1/BIN/pdp1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/pdp1 -------------------------------------------------------------------------------- /simhv36-1/BIN/pdp11: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/pdp11 -------------------------------------------------------------------------------- /simhv36-1/BIN/pdp4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/pdp4 -------------------------------------------------------------------------------- /simhv36-1/BIN/pdp7: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/pdp7 -------------------------------------------------------------------------------- /simhv36-1/BIN/pdp8: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/pdp8 -------------------------------------------------------------------------------- /simhv36-1/BIN/vax: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/vax -------------------------------------------------------------------------------- /simhv36-1/BIN/vax730: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/vax730 -------------------------------------------------------------------------------- /simhv36-1/BIN/vax780: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/simhv36-1/BIN/vax780 -------------------------------------------------------------------------------- /simhv36-1/build_mingw.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem Compile all of SIMH using MINGW make and gcc environment 3 | rem Individual simulator sources are in .\simulator_name 4 | rem Individual simulator executables are to .\bin 5 | rem 6 | rem If needed, define the path for the MINGW bin directory. 7 | rem (this should already be set if MINGW was installed correctly) 8 | rem 9 | gcc -v 1>NUL 2>NUL 10 | if ERRORLEVEL 1 path C:\MinGW\bin;%path% 11 | if not exist BIN mkdir BIN 12 | gcc -v 1>NUL 2>NUL 13 | if ERRORLEVEL 1 echo "MinGW Environment Unavailable" 14 | mingw32-make WIN32=1 -f makefile %1 %2 %3 %4 15 | -------------------------------------------------------------------------------- /simhv36-1/build_mingw_ether.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem 12-Nov-02 rms Ethernet support 3 | rem Compile all of SIMH using MINGW make and gcc environment 4 | rem Individual simulator sources are in .\simulator_name 5 | rem Individual simulator executables are to .\bin 6 | rem 7 | rem If needed, define the path for the MINGW bin directory. 8 | rem (this should already be set if MINGW was installed correctly) 9 | rem 10 | gcc -v 1>NUL 2>NUL 11 | if ERRORLEVEL 1 path C:\MinGW\bin;%path% 12 | if not exist BIN mkdir BIN 13 | gcc -v 1>NUL 2>NUL 14 | if ERRORLEVEL 1 echo "MinGW Environment Unavailable" 15 | mingw32-make WIN32=1 USE_NETWORK=1 -f makefile %1 %2 %3 %4 16 | -------------------------------------------------------------------------------- /simhv36-1/sim_fio.h: -------------------------------------------------------------------------------- 1 | /* sim_fio.h: simulator file I/O library headers 2 | 3 | Copyright (c) 1993-2006, Robert M Supnik 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a 6 | copy of this software and associated documentation files (the "Software"), 7 | to deal in the Software without restriction, including without limitation 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 | and/or sell copies of the Software, and to permit persons to whom the 10 | Software is furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 | 22 | Except as contained in this notice, the name of Robert M Supnik shall not be 23 | be used in advertising or otherwise to promote the sale, use or other dealings 24 | in this Software without prior written authorization from Robert M Supnik. 25 | 26 | 15-May-06 RMS Added sim_fsize_name 27 | 16-Aug-05 RMS Fixed C++ declaration and cast problems 28 | 02-Jan-04 RMS Split out from SCP 29 | */ 30 | 31 | #ifndef _SIM_FIO_H_ 32 | #define _SIM_FIO_H_ 0 33 | 34 | #define FLIP_SIZE (1 << 16) /* flip buf size */ 35 | #define fxread(a,b,c,d) sim_fread (a, b, c, d) 36 | #define fxwrite(a,b,c,d) sim_fwrite (a, b, c, d) 37 | 38 | int32 sim_finit (void); 39 | FILE *sim_fopen (const char *file, const char *mode); 40 | int sim_fseek (FILE *st, t_addr offset, int whence); 41 | size_t sim_fread (void *bptr, size_t size, size_t count, FILE *fptr); 42 | size_t sim_fwrite (void *bptr, size_t size, size_t count, FILE *fptr); 43 | uint32 sim_fsize (FILE *fptr); 44 | uint32 sim_fsize_name (char *fname); 45 | 46 | #endif 47 | -------------------------------------------------------------------------------- /simhv36-1/sim_timer.h: -------------------------------------------------------------------------------- 1 | /* sim_timer.h: simulator timer library headers 2 | 3 | Copyright (c) 1993-2005, Robert M Supnik 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a 6 | copy of this software and associated documentation files (the "Software"), 7 | to deal in the Software without restriction, including without limitation 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 | and/or sell copies of the Software, and to permit persons to whom the 10 | Software is furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 | 22 | Except as contained in this notice, the name of Robert M Supnik shall not be 23 | used in advertising or otherwise to promote the sale, use or other dealings 24 | in this Software without prior written authorization from Robert M Supnik. 25 | 26 | 02-Jan-04 RMS Split out from SCP 27 | */ 28 | 29 | #ifndef _SIM_TIMER_H_ 30 | #define _SIM_TIMER_H_ 0 31 | 32 | #define SIM_NTIMERS 8 /* # timers */ 33 | #define SIM_TMAX 500 /* max timer makeup */ 34 | 35 | int32 sim_rtcn_init (int32 time, int32 tmr); 36 | int32 sim_rtcn_calb (int32 ticksper, int32 tmr); 37 | int32 sim_rtc_init (int32 time); 38 | int32 sim_rtc_calb (int32 ticksper); 39 | uint32 sim_os_msec (void); 40 | void sim_os_sleep (unsigned int sec); 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /tests/Makefile: -------------------------------------------------------------------------------- 1 | 2 | SUBDIRS = basic diags 3 | 4 | define makeone 5 | echo "[ $(1) ]"; 6 | make -C $(1) $(2); 7 | endef 8 | 9 | all clean: 10 | @$(foreach dir,$(SUBDIRS),$(call makeone,$(dir),$@)) 11 | -------------------------------------------------------------------------------- /tests/NOTES.txt: -------------------------------------------------------------------------------- 1 | MAINDEC 2 | 3 | 801-2C 8/30/65 JMS & JMP test 1x 4 | 801-1 RIM 5/ 4/65 Instruction test - part 1 1x 5 | 802-2B BIN 3/22/66 Instruction test - part 2b 1x 6 | 7 | 8E-D1EB-PB 5/ 1/68 PDP-8, 8I Extended memory 1x 8 | 9 | 08-D1GD-PB 7/27/70 PDP-8, 8I, 8S Extended memory control 1x 10 | 08-D1HA-PB 10/ 1/68 PDP-8, 8I extended memory address test 1x 11 | 12 | 8I-D01B-PB 3/25/68 Instruction test 1 1x 13 | 8I-D02B-PB 3/25/68 Instruction test 2 1x 14 | 8I-D02B-PB 1/ 3/68 Instruction test 2b 1x 15 | 8I-D02B-PB 1/ 3/68 Instruction test 2b 1x 16 | 17 | --- 18 | 19 | http://pdp-8.org/papertape/MAINDEC-08-D1EB-PB.pt 20 | http://pdp-8.org/papertape/MAINDEC-08-D1GD-PB.pt 21 | http://pdp-8.org/papertape/MAINDEC-08-D1HA-PB.pt 22 | 23 | http://pdp-8.org/papertape/MAINDEC-8I-D01C-PB.pt x 24 | http://pdp-8.org/papertape/MAINDEC-8I-D02B-PB.pt x 25 | 26 | http://pdp-8.org/papertape/MAINDEX-08-D1GB-PB.pt x 27 | 28 | --- 29 | 30 | MAINDEX-08-D1GB-PB 5/5/68 31 | PDP 8I,8,8/S 32 | EXTENDED MEMORY CONTROL TEST 33 | 34 | Maindec-8I-DO1C-Pb 12/10/69 x 35 | Instruction Test 1 36 | Dec Copyright December 1969 37 | 38 | MAINDEC-8I-DO2B-PB 3/21/68 x 39 | Instruction Test 2 40 | 41 | MAINDEX-08-DO2B-PB 1/3/68 x 42 | INSTRUCTION TEST - PART 2B 43 | 44 | -------------------------------------------------------------------------------- /tests/basic/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | 3 | PALD = ../../utils/macro/macro8x 4 | SHOWBIN = ../../utils/showbin/showbin 5 | 6 | all: user.bin uart.bin 7 | 8 | user.bin: user.pal 9 | $(PALD) $< 10 | $(SHOWBIN) $@ >$(basename $<).mem 11 | 12 | uart.bin: uart.pal 13 | $(PALD) $< 14 | $(SHOWBIN) $@ >$(basename $<).mem 15 | 16 | clean: 17 | rm -f *.mem *.bin *.lst *~ 18 | 19 | -------------------------------------------------------------------------------- /tests/basic/uart.pal: -------------------------------------------------------------------------------- 1 | / 2 | / simple uart output test 3 | / 4 | 5 | *400 6 | / test uart 7 | START, 8 | CLA CMA 9 | 10 | TAD KMSG 11 | DCA 10 12 | 13 | TAD KLEN 14 | DCA 7 15 | 16 | LOOP, 17 | CLA 18 | TAD I 10 19 | TLS 20 | TSF 21 | JMP .-1 22 | 23 | ISZ 7 24 | JMP LOOP 25 | 26 | DONE, 27 | JMP START 28 | 29 | 30 | KMSG, MSG 31 | KLEN, -10 32 | 33 | MSG, "H;"E;"L;"L;"O;"!;215;212 34 | 35 | 36 | -------------------------------------------------------------------------------- /tests/basic/user.pal: -------------------------------------------------------------------------------- 1 | / 2 | / test basic user mode in/out 3 | / 4 | 5 | CINT=6204 /CLEAR USER IOT 6 | SINT=6254 /SKIP ON USER IOT 7 | CUF=6264 /USER FLAG OFF 8 | SUF=6274 /USER FLAG ON 9 | 10 | *1 11 | JMP I .+1 12 | 200 13 | 14 | *200 15 | INT, 16 | SINT /USER IOT? 17 | JMP INT0 18 | RMF /RESTORE IF, DF, & MODE 19 | ION 20 | JMP I 0 21 | INT0, JMP INT0 22 | 23 | *400 24 | CODE, 25 | CLA 26 | ION 27 | SUF 28 | JMP LOOP 29 | LOOP, 30 | CLA 31 | 6040 32 | JMP LOOP 33 | -------------------------------------------------------------------------------- /tests/bin/MAINDEC-08-D1EB-PB.pt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-08-D1EB-PB.pt -------------------------------------------------------------------------------- /tests/bin/MAINDEC-08-D1GD-PB.pt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-08-D1GD-PB.pt -------------------------------------------------------------------------------- /tests/bin/MAINDEC-08-D1HA-PB.pt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-08-D1HA-PB.pt -------------------------------------------------------------------------------- /tests/bin/MAINDEC-08-D5EB.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-08-D5EB.bin -------------------------------------------------------------------------------- /tests/bin/MAINDEC-08-D5FA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-08-D5FA.bin -------------------------------------------------------------------------------- /tests/bin/MAINDEC-8I-D01C-PB.pt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-8I-D01C-PB.pt -------------------------------------------------------------------------------- /tests/bin/MAINDEC-8I-D01C-PB.pt.fixed: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-8I-D01C-PB.pt.fixed -------------------------------------------------------------------------------- /tests/bin/MAINDEC-8I-D02B-PB.pt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-8I-D02B-PB.pt -------------------------------------------------------------------------------- /tests/bin/MAINDEC-8I-D02B-PB.pt.fixed: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEC-8I-D02B-PB.pt.fixed -------------------------------------------------------------------------------- /tests/bin/MAINDEX-08-D1GB-PB.pt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEX-08-D1GB-PB.pt -------------------------------------------------------------------------------- /tests/bin/MAINDEX-08-D1GB-PB.pt.fixed: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/bin/MAINDEX-08-D1GB-PB.pt.fixed -------------------------------------------------------------------------------- /tests/bin/MAINDEX-08-D1GB.bin: -------------------------------------------------------------------------------- 1 | €€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€B@(@," 2 |   < =<22 ??8??7?/?'????>?=?<:*5*,:.2)2 8 <(+ <:+/212 8 <(+<:+ +20!$0:2<(+#<+2 0:2 <(++<+#028 <(+2<+#+/5D:20:2 <(* 4 | <*128 <(*<*20:2 <(*<*228 <(* <**:2!0:2 <(*,<*$328 <(*3<*$2)0:2 <(*;<*3428 <(+<*3*$:210:2 <(+<+528 <(+<+290:2 <(+<+628 <(+$<++/'F$8 &2(<*& 5 | *$8 &2 (8!> ***%**.& 6 | *<:*2$ &72 $<*? 7 | 7*520!$$2 8 | 08+<2*8 >(+2<:+++,208+<2+8 >(+%2<:++*+,208+.<2,8 >(+82<:+*/=+,H2"08*<2-8 >(*2<:**,"+ 9 | 2*08*<2.8 >(*!2<:**&,"+ 10 | 2208**<2/8 >(*42<:*&*9,"+ 11 | 2:08*=<2)8 >(+2<:*9,"+ 12 | $  &8 28 > ++ $ &2<+( +20!$)78$ &9!&: :#$2 2 13 | +<8<+9J2 <(*<:-2 14 | 2$222 88 >(*2$2<:22-88!>(* <:-*&.%- -:  *2 8 > *+2 32 2 & & 8#-<(+ 15 | <:,<+ = =2 16 | 0, 17 |    9 2 2  + '2 2 2 - 2 2 3 2 2 9 2 '2/L0!$(2 (2 (  08<*:2 2 18 | 2$,(**2)$ & 19 | &&&8 2 *'2 ;  20 | &52 2  *36%8 *=8 '2 !2 21 | ' * *++ : < < < < 22 | < < < < < < < < < < < <22+>&> /6 /0&0!+2/5N:6>%8!%<(.*)>%89888! 2 8!8>*/"1*,.( 23 | +).* 1 00& &#*!2: 8  8 *8 >(+ <*<22.12: 8  + 8 <(+8 <:+22/>%8!/: $0&0!+':/"> €€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ -------------------------------------------------------------------------------- /tests/diags/MAINDEC-08-D5EA.simh.script: -------------------------------------------------------------------------------- 1 | set dt disabled 2 | set mt disabled 3 | set rx disabled 4 | set lpt disabled 5 | set rk disabled 6 | set df disabled 7 | set rf enabled 8 | att rf rf.dsk 9 | load ../bin/MAINDEC-08-D5EB.bin 10 | d SR 4000 11 | go 200 12 | -------------------------------------------------------------------------------- /tests/diags/MAINDEC-08-D5FA.simh.script: -------------------------------------------------------------------------------- 1 | set dt disabled 2 | set mt disabled 3 | set rx disabled 4 | set lpt disabled 5 | set rk disabled 6 | set df disabled 7 | set rf enabled 8 | att rf rf.dsk 9 | load ../bin/MAINDEC-08-D5FA.bin 10 | go 150 11 | -------------------------------------------------------------------------------- /tests/diags/MAINDEC-8I-D01C.simh.script: -------------------------------------------------------------------------------- 1 | load ../bin/MAINDEC-8I-D01C-PB.pt.fixed 2 | d SR 07777 3 | run 0200 4 | quit 5 | -------------------------------------------------------------------------------- /tests/diags/MAINDEC-8I-D02B.simh.script: -------------------------------------------------------------------------------- 1 | load ../bin/MAINDEC-8I-D02B-PB.pt.fixed 2 | d SR 0 3 | run 0200 4 | quit 5 | -------------------------------------------------------------------------------- /tests/diags/MAINDEX-08-D1GB.simh.script: -------------------------------------------------------------------------------- 1 | load ../bin/MAINDEX-08-D1GB-PB.pt.fixed 2 | d SR 017 3 | run 0200 4 | quit 5 | 6 | -------------------------------------------------------------------------------- /tests/diags/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # make "mem" files for simulation from various binary formats 3 | # we get to xxdp and other places. 4 | # 5 | 6 | SIMH_PDP8 = ../../simhv36-1/BIN/pdp8 7 | 8 | DIAGS = MAINDEX-08-D1GB MAINDEC-8I-D01C MAINDEC-8I-D02B \ 9 | MAINDEC-08-D5EB MAINDEC-08-D5FA \ 10 | MAINDEC-08-D1GD MAINDEC-08-D1EB MAINDEC-08-D1HA 11 | 12 | 13 | MEMS = $(addsuffix .mem,$(basename $(DIAGS))) 14 | LOGS = $(addsuffix .log,$(basename $(DIAGS))) 15 | 16 | #all: loadtomem mems logs 17 | all: mems logs 18 | 19 | mems: $(MEMS) 20 | 21 | define loadone-skip 22 | ../../utils/showbin/showbin -z $(1) >$(2); 23 | ../../utils/skipz/skipz $(1) >$(1).fixed; 24 | endef 25 | 26 | define loadone 27 | ../../utils/showbin/showbin $(1) >$(2); 28 | endef 29 | 30 | # dd if=/dev/zero of=rf.dsk bs=1024 count=512 31 | 32 | define genlog_from_script 33 | M=10000 $(SIMH_PDP8) $(1) >$(2) 34 | endef 35 | 36 | #------------------------------ 37 | 38 | %.mem: ../bin/%-PB.pt 39 | $(call loadone-skip,$<,$@) 40 | 41 | %.mem: ../bin/%.bin 42 | $(call loadone,$<,$@) 43 | 44 | #------------------------------ 45 | 46 | .PRECIOUS: $(LOGS) 47 | 48 | logs: $(LOGS) 49 | 50 | %.log : %.simh.script 51 | $(call genlog_from_script,$<,$@) 52 | 53 | 54 | #------------------------------ 55 | 56 | clean: 57 | rm -rf *.mem *.log 58 | rm -rf loadtomem 59 | -------------------------------------------------------------------------------- /tests/pdf/MAINDEC-08-D02B-D.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/pdf/MAINDEC-08-D02B-D.pdf -------------------------------------------------------------------------------- /tests/pdf/MAINDEC-08-D1GB-D.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/pdf/MAINDEC-08-D1GB-D.pdf -------------------------------------------------------------------------------- /tests/pdf/MAINDEC-8I-D01C-D.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/pdf/MAINDEC-8I-D01C-D.pdf -------------------------------------------------------------------------------- /tests/pdf/MAINDEC-8I-D02B-D.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/pdf/MAINDEC-8I-D02B-D.pdf -------------------------------------------------------------------------------- /tests/src/MAINDEC-08-D1GB-D.pal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tests/src/MAINDEC-08-D1GB-D.pal -------------------------------------------------------------------------------- /tests/src/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PALD = ../../utils/macro/macro8x 3 | 4 | BIN = MAINDEC-08-D1GB-D.bin MAINDEC-8I-D01C-D.bin 5 | 6 | all: $(BIN) 7 | 8 | MAINDEC-08-D1GB-D.bin: MAINDEC-08-D1GB-D.pal 9 | $(PALD) $< 10 | 11 | MAINDEC-8I-D01C-D.bin: MAINDEC-8I-D01C-D.pal 12 | $(PALD) $< 13 | 14 | clean: 15 | rm -f *.bin *.err *.lst 16 | -------------------------------------------------------------------------------- /tss8.2/Makefile: -------------------------------------------------------------------------------- 1 | 2 | MACRO = ../utils/macro/macro8x 3 | SHOWBIN = ../utils/showbin 4 | 5 | all: init.bin fip.bin si.bin ts8.bin 6 | 7 | clean: 8 | rm -f *.bin *.prm *.lst *.err *.mem *.dump 9 | 10 | init.bin: 11 | rm -f init.err init.lst 12 | $(MACRO) -o init melrose.pal param.pal link.pal init.pal 13 | 14 | fip.bin: 15 | rm -f fip.err fip.lst 16 | $(MACRO) -o fip melrose.pal param.pal link.pal fip.pal 17 | 18 | si.bin: 19 | rm -f si.err si.lst 20 | $(MACRO) -o si melrose.pal param.pal link.pal si.pal 21 | 22 | ts8.bin: 23 | rm -f ts8.err ts8.lst 24 | $(MACRO) -o ts8 melrose.pal param.pal link.pal ts8.pal 25 | 26 | xxx: 27 | $(SHOWBIN) fip.bin >fip.src.mem 28 | $(SHOWBIN) init.bin >init.src.mem 29 | $(SHOWBIN) si.bin >si.src.mem 30 | $(SHOWBIN) ts8.bin >ts8.src.mem 31 | # sdiff fip.rf.mem fip.src.mem 32 | # sdiff init.rf.mem init.src.mem 33 | # sdiff si.rf.mem si.src.mem -------------------------------------------------------------------------------- /tss8.2/NOTES.txt: -------------------------------------------------------------------------------- 1 | fip.pal - line 2029, added missing "I" 2 | si.pal - line 270; orig was "jmp com1", changed to be "jmp com2" 3 | init.pal - line 626; orig was "ksr", changed to be "ksf" 4 | ts8.pal - line 6608; "I" added to label 5 | line 6803; typo 6 | ------ 7 | 8 | README 9 | 10 | fipb.pal 11 | fipa.pal 12 | fipc.pal 13 | 14 | inita.pal 15 | initb.pal 16 | initc.pal 17 | 18 | link.pal 19 | 20 | param.pal 21 | 22 | si.pal 23 | 24 | ts8a.pal 25 | ts8b.pal 26 | ts8c.pal 27 | ts8d.pal 28 | ts8e.pal 29 | ts8f.pal 30 | 31 | ---- 32 | 33 | si 34 | fip 35 | xddt? 36 | ts8 37 | init 38 | link 39 | 40 | ------------ 41 | 42 | in memory: 43 | 44 | SI 00000 - 07777 45 | FIP 10000 - 17777 46 | INIT 20000 - 27777 47 | TS8 30000 - 37777 48 | TS8II 40000 - 47777 49 | 50 | on disk 51 | 52 | SI 0 53 | FIP 1 54 | INIT 2 55 | TS8 3 56 | TS8II 4 57 | swap & file 5 58 | fixed swap for each job 59 | file area 60 | 61 | ... 62 | INIT 63 | 0000 64 | 0200 disk look 65 | 0777 initializer 66 | 4400 xddr 67 | 68 | 69 | -------------------------------------------------------------------------------- /tss8.2/link.pal: -------------------------------------------------------------------------------- 1 | /SUPER CRITICAL LOCATIONS 2 | /THESE LOCATIONS ARE USED TO LINK TS8, TS8II, FIP, SI AND INIT. 3 | 4 | /IT MAY BE NECESSARY TO ADJUST THEM ACCORDINGLY 5 | 6 | /DEFINED IN TS8: 7 | 8 | WSCHED=2573 /ADDRESS FOR WAIT 9 | GETJTB=401 /GETJTA 10 | CORSRC=1317 /SEARCH CORE TABLE 11 | OVERLA=5171 /FILE STUFF 12 | READFI=574 /MORE FILE STUFF 13 | CONDBA=132 /DEVTBL POINTER USED BY "PRINT" ETC. 14 | RETB=611 /RETURN A BLOCK TO FREE CORE 15 | GETB=1405 /GET A BLOCK OF FREE CORE 16 | GETDB0=1447 /GET A DDB 17 | CLK1=51 /LOW ORDER DAYTIME CLOCK 18 | CLK2=50 /HIGH ORDER DAYTIME CLOCK 19 | DATE=166 /12 BIT DATE WORD 20 | TTCHAR=31 /SAVE REG. FOR CONSOLE CHARACTERS 21 | KBD00=3201 /PROCESS KEYBOARD INPUT 22 | PRINT0=1205 /TYPE OUT A CHARACTER 23 | OVRLA1=562 /MORE FILE STUFF 24 | RUNFI=605 /SI FILE TRANSFER INITIALIZER 25 | L2SF=103 /LEVEL 2 SAVED MODE AND FIELD 26 | SICLR=6572 /SI CLEAR LINKED BUFFER 27 | TIMSI=2421 /TIMER FOR SI "COMWAT" 28 | SIWAIT=1702 /NUMBER OF SI COMMANDS BEING WAITED ON 29 | TIMFIP=2423 /TIMER FOR FIPLOCK 30 | FIPLOK=2724 /CORTBL STATUS CHECK FOR FORCE OUT 31 | CLKINI=322 /CONVERT HARDWARE CLOCK TO SYSTEM-TICKS (100MS) 32 | BLT0=1602 /BLOCK TRANSFER FROM CORE TO CORE 33 | KBDSQ=3213 /ADDRESS OF JMS TO ^S/^Q CODE 34 | 35 | 36 | /DEFINED IN TS8II: 37 | 38 | F1TCNT=175 /SI DDB CHARACTER COUNT 39 | F1ECNT=176 /SI DDB EMPTY COUNT 40 | F1BUF=177 /SI DDB EMPTY BLOCK POINTER 41 | DTJOB=20 /JOB OWNING THE DECTAPE CONTROLLER 42 | RKJOB=54 /JOB OWNING RK05 CONTROLLER 43 | DTSI=1175 /SI TERMINATE A DECTAPE ON TIMER 44 | DATA1=2200+DCSIZE 45 | DEVTBL=DATA1+140 46 | DEVTBE=DEVTBL+NULINE+NULINE+2 47 | JOBTBL=DEVTBE+22 48 | CLKTBL=JOBTBL+JOBMAX+1 49 | TTYTBL=CLKTBL+JOBMAX+1 50 | PRGTBL=TTYTBL+JOBMAX+1 51 | DSUTBL=PRGTBL+JOBMAX+JOBMAX+JOBMAX-7 52 | FIPBLK=7720 /FIXED BLOCK FOR FIP IO 53 | WINBAS=7730 /ADDRESS OF THE BASIC WINDOW 54 | OUTDIF=-OUTREG^2+DEVTBL /FOR LINKING BETWEEN OUTREG AND DEVTBL 55 | F1OFFJ=164 /FOR OFF /ON COMMANDS USED BY SI 56 | IFNZRO DEVTBL&1 57 | 58 | /DEFINED IN SI 59 | 60 | DTSIDT=7270 /RETURNED FROM STOPPING A DECTAPE ON TIMER 61 | VERBRK=7600 /START OF INSTALLATION DEFINED LOGIN MESSAGE 62 | -------------------------------------------------------------------------------- /tss8.2/melrose.pal: -------------------------------------------------------------------------------- 1 | /EDUSYSTEM 50 MONITOR FOR MELROSE HIGH SCHOOL #495AB 2 | /COPYRIGHT 1975 3 | /DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS. 4 | / 5 | /THIS SECTION DEFINES THE HARDWARE CONFIGURATION ON WHICH INDIVIDUAL 6 | /EDUSYSTEM 50 MONITORS ARE TO RUN. 7 | /FOR EACH STATEMENT, THE COMMENT INDICATES THE POSSIBLE RESPONSES. 8 | 9 | CPU= 2 /1 IF CPU IS PDP-8; 0 IF CPU IS PDP-8/I; 10 | /2 IF CPU IS PDP-8/E 11 | 12 | CORMEM= 70 /HIGHEST DATA FIELD SELECT. FOR 12K SYSTEM, 13 | /RESPOND 20, FOR 16K SYSTEM, RESPOND 30, ETC. (70 MAX) 14 | 15 | PHONES= 0 /1 IF DC08 INCLUDES 689AG; 16 | /0 IF IT DOES NOT OR IF TTY INTERFACING IS OTHER THAN DC08 17 | 18 | EAE= 0 /20 IF PROCESSOR INCLUDES EAE; 0 IF IT DOES NOT 19 | 20 | RF08= 0 /40 IF SYSTEM DISC IS DF32; 0 IF SYSTEM DISK IS RF08 21 | 22 | RS08= 1 /NUMBER OF DISCS ON THE SYSTEM, WHETHER DF/DS OR RF/RS. 23 | /RESPOND WITH 1, 2, 3, OR 4. 24 | 25 | PUNCH= 0 /1 IF SYSTEM INCLUDES PUNCH; 0 IF IT DOES NOT 26 | 27 | TC01= 0 /1 IF SYSTEM INCLUDES DECTAPE(S); 0 IF IT DOES NOT 28 | 29 | RK05= 0 /NUMBER OF RK05 CARTRIDGE DISK DRIVES ON THE SYSTEM; 0 TO 4 30 | 31 | CDR= 0 /1 IF SYSTEM INCLUDES CARD READER; 0 IF IT DOES NOT 32 | 33 | LPT= 0 /1 IF SYSTEM INCLUDES LINE PRINTER; 0 IF NO LINE PRINTER 34 | 35 | DECIMAL /MONITOR CAPACITY FOR THIS SYSTEM 36 | 37 | JOBMAX= 20 /NUMBER OF SIMULTANEOUS USERS (20 MAXIMUM) 38 | 39 | /THE FOLLOWING ENTRIES DEFINE THE NUMBER OF TERMINALS 40 | /ATTACHED TO THE SYSTEM, AND ALSO THE METHOD OF INTERFACING 41 | 42 | CONTTY= 1 /WE ALWAYS HAVE A CONSOLE (K00) 43 | 44 | DC08A= 0 /NUMBER OF TERMINALS INTERFACED VIA DC08A (PDP-8/I ONLY, 19 MAX.) 45 | 46 | DC08LO= 0 /LOWEST HARDWARE LINE NUMBER UTILIZED ON DC08A; USUALLY 0 47 | 48 | PT08= 0 /NUMBER OF TERMINALS INTERFACED VIA PT08 (PDP-8 & PDP-8/I ONLY) 49 | 50 | KL8= 0 /NUMBER OF ADDITIONAL TERMINALS INTERFACED VIA KL8 (PDP-8/E ONLY, 19 MAX.) 51 | 52 | -------------------------------------------------------------------------------- /tss8.23/ASM.BI: -------------------------------------------------------------------------------- 1 | $JOB ASSEMBLE TSS/8 2 | /TSS/8 CONFIG PARMS IN DSK:TSCON.PA ?? 3 | $MSG MT TSS/8 #1 & #2 ON D1 & D2 4 | .R PIP 5 | *DSK:INIT.XD.bin 34 | 35 | xxx: 36 | $(SHOWBIN) fip.bin >fip.src.mem 37 | $(SHOWBIN) init.bin >init.src.mem 38 | $(SHOWBIN) si.bin >si.src.mem 39 | $(SHOWBIN) ts8.bin >ts8.src.mem 40 | $(SHOWBIN) ts8ii.bin >ts8ii.src.mem 41 | # sdiff fip.rf.mem fip.src.mem 42 | # sdiff init.rf.mem init.src.mem 43 | # sdiff si.rf.mem si.src.mem 44 | -------------------------------------------------------------------------------- /tss8.23/PIP2.SV: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tss8.23/PIP2.SV -------------------------------------------------------------------------------- /tss8.23/SCAN.TE: -------------------------------------------------------------------------------- 1 | 2 | !LOOP!1J : "L OLOOP' 3 | :N Z"N OLOOP' EF 4 | -------------------------------------------------------------------------------- /tss8.23/SI.CM: -------------------------------------------------------------------------------- 1 | SI "L OLOOP' 3 | :N Z"N OLOOP' EF 4 | -------------------------------------------------------------------------------- /tss8.23/orig/SI.CM: -------------------------------------------------------------------------------- 1 | SI 57 | 58 | /DEFINED IN SI 59 | 60 | DTSIDT=7270 /RETURNED FROM STOPPING A DECTAPE ON TIMER 61 | VERBRK=7600 /START OF INSTALLATION DEFINED LOGIN MESSAGE 62 | -------------------------------------------------------------------------------- /tss8/tss8_boostrap.txt: -------------------------------------------------------------------------------- 1 | Loading TSS/8 2 | ------------- 3 | 4 | Note: your environment must have a functioning second Teletype; that is, you cannot 5 | at present run Foreground/Background if your host system is VMS or OS/2. 6 | 7 | 1. Load the paper-tape bootstrap: 8 | 9 | sim> load tss8_init.bin 10 | 11 | 2. Enable the RF08, if it is not enabled, and disable the DF32, if it is enabled: 12 | 13 | sim> set rf enabled 14 | sim> set df disabled 15 | 16 | 3. Mount the TSS/8 disk image of the RF08: 17 | 18 | sim> attach rf tss8_rf.dsk 19 | 20 | 4. Assign a TCP/IP port to the Telnet listener for the extra terminals: 21 | 22 | sim> attach tti1 -- 4000 typically works 23 | 24 | 5. Run the bootstrap: 25 | 26 | sim> run 24200 27 | 28 | 5. TSS/8 will boot and go through its startup dialog 29 | 30 | LOAD, DUMP, START, ETC? START 31 | MONTH-DAY-YEAR: mm:dd:yy -- numeric, yy in range [74:85] 32 | HR:MIN - hh:mm -- numeric, 24 hour format 33 | (type cr to get attention) 34 | 35 | . 36 | 37 | and is now ready for login. The list of accounts and passwords: 38 | 39 | PPN Password 40 | [0,1] VH3M 41 | [0,2] LXHE 42 | [0,3] SHUG 43 | [77,77] 44 | [1,10] WBCN 45 | [20,1] DT 46 | [20,2] PT 47 | [20,3] TSS8 48 | [20,4] EDIT 49 | [20,5] 4TH 50 | [1,50] JERK 51 | 52 | 6. Login using one of the existing accounts. The login command won't echo: 53 | 54 | .LOGIN 2 LXHE -- privileged library account 55 | 56 | TSS/8.24 JOB 01 [00,02] K00 23:23:06 57 | 58 | SYSTEM IS DOWN, INC. 59 | 60 | 7. The system is now ready for commands. To get a directory listing: 61 | 62 | .R CAT 63 | 64 | 8. Other users can log in by connecting, from a Telnet client, to localhost 65 | on the port specified in the attach tti1 command. 66 | -------------------------------------------------------------------------------- /tss8/tss8_init.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tss8/tss8_init.bin -------------------------------------------------------------------------------- /tss8/tss8_rf.dsk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tss8/tss8_rf.dsk -------------------------------------------------------------------------------- /tss8/tss8_rf.dsk.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/tss8/tss8_rf.dsk.orig -------------------------------------------------------------------------------- /tss8_uwm/COPY.BN: -------------------------------------------------------------------------------- 1 | B@,*@  ,$6 . : >%-= >?9,B: <6%?!?5$<$;$: $%?!?9$=%%9</?& 2 | 6> ! 3 | 4 | 6 *"*+ ;%%?!?8$=0$>(/>0> /=0 5 | '6 :> ! 6 | 96> + 7 | '6> ! 8 | % 8> -7 66 : 7:6 <6 < + 50 4?$%+$0+?! 9 | %?#?7 37 <6 10 | *0 ;>(+';5$0%*"2 16*C;/6<#D:* #:  >(! 11 | 0 ?*$ 8?*) /#*)#:   -------------------------------------------------------------------------------- /tss8_uwm/FIP.CM: -------------------------------------------------------------------------------- 1 | DSK:FIP 8! 0&0$0"0! 0 0 0 -------------------------------------------------------------------------------- /tss8_uwm/Makefile: -------------------------------------------------------------------------------- 1 | 2 | MACRO = ../utils/macro/macro8x 3 | SHOWBIN = ../utils/showbin 4 | 5 | all: init.bin fip.bin si.bin ts8.bin ts8ii.bin INIT.XD.bin 6 | 7 | clean: 8 | rm -f *.bin *.prm *.lst *.err *.mem *.dump 9 | 10 | init.bin: INIT.PA 11 | rm -f init.err init.lst 12 | $(MACRO) -o init -d UWM.PA PARA.PA PARB.PA PARC.PA INIT.PA 13 | 14 | fip.bin: FIP.PA 15 | rm -f fip.err fip.lst 16 | $(MACRO) -o fip -d UWM.PA PARA.PA PARB.PA PARC.PA FIP.PA 17 | 18 | si.bin: SI.PA 19 | rm -f si.err si.lst 20 | $(MACRO) -o si -d UWM.PA PARA.PA PARB.PA PARC.PA SI.PA 21 | 22 | ts8.bin: TS8.PA 23 | rm -f ts8.err ts8.lst 24 | $(MACRO) -o ts8 -d UWM.PA PARA.PA PARB.PA PARC.PA TS8.PA 25 | 26 | ts8ii.bin: TS8II.PA 27 | rm -f ts8ii.err ts8ii.lst 28 | $(MACRO) -o ts8ii -d UWM.PA PARA.PA PARB.PA PARC.PA TS8II.PA 29 | 30 | INIT.XD.bin: orig-dectapes/INIT.XD 31 | #it's a bin format papertape encoded as ascii bytes 32 | #but we dumped it as binary 33 | ../tapes/tools/asc INIT.XD.bin 34 | 35 | xxx: 36 | $(SHOWBIN) fip.bin >fip.src.mem 37 | $(SHOWBIN) init.bin >init.src.mem 38 | $(SHOWBIN) si.bin >si.src.mem 39 | $(SHOWBIN) ts8.bin >ts8.src.mem 40 | $(SHOWBIN) ts8ii.bin >ts8ii.src.mem 41 | # sdiff fip.rf.mem fip.src.mem 42 | # sdiff init.rf.mem init.src.mem 43 | # sdiff si.rf.mem si.src.mem -------------------------------------------------------------------------------- /tss8_uwm/PARB.PA: -------------------------------------------------------------------------------- 1 | BLT0= 5200 /BLOCK TRANSFER 2 | CLK1= 0033 /SYSTEM DAYCLOCK (LOW) 3 | CLK2= 0034 / (HIGH) 4 | CONDBA= 0030 /POINTER TO DEVTBL ENTRY IN USE 5 | CONDDB= 0031 /POINTER TO DDB IN USE 6 | CORSRC= 1317 /CORTBL SEARCH 7 | CORTBL= 7001 /CORE ALLOCATION TABLE (FIXED) 8 | DATE= 0035 9 | DEVCHK= 7045 /CHECK DEVICE OWNERSHIP 10 | DSBUSY= 0036 /DISC BUSY COUNT 11 | DTDEF0= 0535 /DECTAPE ERROR REGISTRATION 12 | DTDSF0= 0541 /DECTAPE BUFFER TO SWAP AREA 13 | DTDSK= 0527 /DECTAPE DISC COMPLETION 14 | DTL20= 0551 /DECTAPE LEVEL-2 DISPATCH 15 | DTRKHG= 3671 /ERROR SETTING FROM FIELD 1 16 | ENDIOT= 5333 /JMP TO EXIT HANDLER 17 | F1RTN= 0277 /RETURN FROM FIELD 1 INTERRUPT HANDLERS 18 | FIPJOB= 0057 /JOB REQUESTING 'FIP' 19 | FRECNT= 0040 /AVAILABLE FREE-CORE BLOCKS 20 | FREE= 0037 /LINK TO FIRST FREE-CORE BLOCK 21 | GETB= 1400 /GET A FREE-BLOCK 22 | GETDB0= 1440 /GET DDB BLOCK 23 | GETJTB= 7200 /GET ADDRESS OF LINKED ENTRY 24 | GIR00= 6200 /GENERAL INPUT ROUTINE 25 | JOB= 0062 /CURRENTLY ACTIVE JOB 26 | L2EXIT= 4051 /LEVEL-2 EXIT ROUTINE 27 | L2SF= 0041 /LEVEL 2: SAVED FIELD AND MODE 28 | L2SV0= 0042 /LEVEL 2: SAVED PC 29 | L2TIM3= 2631 /RETURN FROM 'TIMER' ROUTINE 30 | NFSEGS= 5533 /NUMBER OF FREE DISC SEGMENTS 31 | OUTIOT= 2340 /INCREMENT 'ACFLG' TO SIGNAL OUTPUT 32 | OVERL1= 5764 33 | OVERLA= 2364 /DISC TERMINATION FOR OVERLAYS 34 | OVRLA1= 0572 /SYSTEM OVERLAY COMPLETION DISPATCHER 35 | PRINT0= 1203 /TYPE CHARACTER 36 | QUEUE0= 1473 /REGISTER LEVEL-2 FOR FIELD 1 37 | READFI= 3652 /SI FILE-LOADER 38 | REDO0= 4172 /'REDO' AND IOT 39 | RELOAD= 3600 /AUTO-RESTART STARTUP 40 | RETB= 0600 /FREE A CORE-BLOCK 41 | RKL20= 3676 /LEVEL-2 DISPATCH FOR RK05 42 | SCHED0= 3640 /'RSCHED' ENTRY 43 | SICLR= 4400 /BUFFER CLEAR ROUTINE 44 | SIDATA= 0020 /SI CONTROL WORDS 45 | SLEEP= 2357 /PUT THE JOB TO SLEEP 46 | TIMCDR= 2621 /CARD READ TIMER 47 | TTCHAR= 0032 /CHARACTER FOR FEED ROUTINES 48 | UUDF= 0172 /USER FIELD SELECT 49 | UUOERR= 4404 /USER IOT ERROR 50 | UUOEX1= 0336 /IOT EXIT ROUTINE 51 | WSCHED= 3006 /'WAIT' ENTRY 52 | -------------------------------------------------------------------------------- /tss8_uwm/PARC.PA: -------------------------------------------------------------------------------- 1 | CDL11= 1720 /LEVEL-1 INTERRUPT FOR CARD READER 2 | CDL21= 1704 /LEVEL-2 HANDLER FOR CARD READER 3 | CJOBDA= 0020 /CURRENT JOB DATA POINTER 4 | DTJOB= 0027 /JOB HOLDING DECTAPE CONTROLLER 5 | DTL11= 0601 /LEVEL-1 INTERRUPT FOR DECTAPE 6 | DTL21= 1004 /DECTAPE LEVEL-2 COMPLETION 7 | F1BUF= 0177 /DDB EMPTY BLOCK 8 | F1DTST= 2512 /DECTAPE STOP ROUTINE 9 | F1ECNT= 0176 /DDB EMPTY COUNT 10 | F1OFFJ= 0036 /SYSTEM OFF/ON COMMAND FLAG 11 | F1TCNT= 0175 /DDB CHARACTER COUNT 12 | RKJOB= 0045 /JOB HOLDING RK05 CONTROLLER 13 | RKL11= 2000 /LEVEL-1 INTERRUPT FOR RK05 14 | RKL21= 1615 /LEVEL-2 HANDLER FOR RK05 15 | TIMER0= 2200 /FIELD 1 TIMER ROUTINE 16 | UPEEK1= 2445 /FIELD 1 PEEK IOT CODE 17 | UPTIM1= 0174 /SYSTEM UPTIME 18 | UPTIM2= 0173 19 | UUCDR= 1735 /UUO ENTRY FOR CARD READER 20 | UUDTRK= 1415 /UUO ENTRY FOR DECTAPE & RK05 21 | WINBAS= 7730 /BASIC RETRIEVAL WINDOW 22 | 23 | -------------------------------------------------------------------------------- /tss8_uwm/SI.CM: -------------------------------------------------------------------------------- 1 | DSK:SI%-= >?9,B: <6%?!?5$<$;$: $%?!?9$=%%9</?& 2 | 6> ! 3 | 4 | 6 *"*+ ;%%?!?8$=0$>(/>0> /=0 5 | '6 :> ! 6 | 96> + 7 | '6> ! 8 | % 8> -7 66 : 7:6 <6 < + 50 4?$%+$0+?! 9 | %?#?7 37 <6 10 | *0 ;>(+';5$0%*"2 16*C;/6<#D:* #:  >(! 11 | 0 ?*$ 8?*) /#*)#:   -------------------------------------------------------------------------------- /tss8_uwm/orig-bitsavers/FIP.CM: -------------------------------------------------------------------------------- 1 | DSK:FIP 8! 0&0$0"0! 0 0 0 -------------------------------------------------------------------------------- /tss8_uwm/orig-bitsavers/PARB.PA: -------------------------------------------------------------------------------- 1 | BLT0= 5200 /BLOCK TRANSFER CLK1= 0033 /SYSTEM DAYCLOCK (LOW) CLK2= 0034 / (HIGH) CONDBA= 0030 /POINTER TO DEVTBL ENTRY IN USE CONDDB= 0031 /POINTER TO DDB IN USE CORSRC= 1317 /CORTBL SEARCH CORTBL= 7001 /CORE ALLOCATION TABLE (FIXED) DATE= 0035 DEVCHK= 7045 /CHECK DEVICE OWNERSHIP DSBUSY= 0036 /DISC BUSY COUNT DTDEF0= 0535 /DECTAPE ERROR REGISTRATION DTDSF0= 0541 /DECTAPE BUFFER TO SWAP AREA DTDSK= 0527 /DECTAPE DISC COMPLETION DTL20= 0551 /DECTAPE LEVEL-2 DISPATCH DTRKHG= 3671 /ERROR SETTING FROM FIELD 1 ENDIOT= 5333 /JMP TO EXIT HANDLER F1RTN= 0277 /RETURN FROM FIELD 1 INTERRUPT HANDLERS FIPJOB= 0057 /JOB REQUESTING 'FIP' FRECNT= 0040 /AVAILABLE FREE-CORE BLOCKS FREE= 0037 /LINK TO FIRST FREE-CORE BLOCK GETB= 1400 /GET A FREE-BLOCK GETDB0= 1440 /GET DDB BLOCK GETJTB= 7200 /GET ADDRESS OF LINKED ENTRY GIR00= 6200 /GENERAL INPUT ROUTINE JOB= 0062 /CURRENTLY ACTIVE JOB L2EXIT= 4051 /LEVEL-2 EXIT ROUTINE L2SF= 0041 /LEVEL 2: SAVED FIELD AND MODE L2SV0= 0042 /LEVEL 2: SAVED PC L2TIM3= 2631 /RETURN FROM 'TIMER' ROUTINE NFSEGS= 5533 /NUMBER OF FREE DISC SEGMENTS OUTIOT= 2340 /INCREMENT 'ACFLG' TO SIGNAL OUTPUT OVERL1= 5764 OVERLA= 2364 /DISC TERMINATION FOR OVERLAYS OVRLA1= 0572 /SYSTEM OVERLAY COMPLETION DISPATCHER PRINT0= 1203 /TYPE CHARACTER QUEUE0= 1473 /REGISTER LEVEL-2 FOR FIELD 1 READFI= 3652 /SI FILE-LOADER REDO0= 4172 /'REDO' AND IOT RELOAD= 3600 /AUTO-RESTART STARTUP RETB= 0600 /FREE A CORE-BLOCK RKL20= 3676 /LEVEL-2 DISPATCH FOR RK05 SCHED0= 3640 /'RSCHED' ENTRY SICLR= 4400 /BUFFER CLEAR ROUTINE SIDATA= 0020 /SI CONTROL WORDS SLEEP= 2357 /PUT THE JOB TO SLEEP TIMCDR= 2621 /CARD READ TIMER TTCHAR= 0032 /CHARACTER FOR FEED ROUTINES UUDF= 0172 /USER FIELD SELECT UUOERR= 4404 /USER IOT ERROR UUOEX1= 0336 /IOT EXIT ROUTINE WSCHED= 3006 /'WAIT' ENTRY -------------------------------------------------------------------------------- /tss8_uwm/orig-bitsavers/PARC.PA: -------------------------------------------------------------------------------- 1 | CDL11= 1720 /LEVEL-1 INTERRUPT FOR CARD READER CDL21= 1704 /LEVEL-2 HANDLER FOR CARD READER CJOBDA= 0020 /CURRENT JOB DATA POINTER DTJOB= 0027 /JOB HOLDING DECTAPE CONTROLLER DTL11= 0601 /LEVEL-1 INTERRUPT FOR DECTAPE DTL21= 1004 /DECTAPE LEVEL-2 COMPLETION F1BUF= 0177 /DDB EMPTY BLOCK F1DTST= 2512 /DECTAPE STOP ROUTINE F1ECNT= 0176 /DDB EMPTY COUNT F1OFFJ= 0036 /SYSTEM OFF/ON COMMAND FLAG F1TCNT= 0175 /DDB CHARACTER COUNT RKJOB= 0045 /JOB HOLDING RK05 CONTROLLER RKL11= 2000 /LEVEL-1 INTERRUPT FOR RK05 RKL21= 1615 /LEVEL-2 HANDLER FOR RK05 TIMER0= 2200 /FIELD 1 TIMER ROUTINE UPEEK1= 2445 /FIELD 1 PEEK IOT CODE UPTIM1= 0174 /SYSTEM UPTIME UPTIM2= 0173 UUCDR= 1735 /UUO ENTRY FOR CARD READER UUDTRK= 1415 /UUO ENTRY FOR DECTAPE & RK05 WINBAS= 7730 /BASIC RETRIEVAL WINDOW -------------------------------------------------------------------------------- /tss8_uwm/orig-bitsavers/SI.CM: -------------------------------------------------------------------------------- 1 | DSK:SI "L OLOOP' 3 | :N Z"N OLOOP' EF 4 | -------------------------------------------------------------------------------- /tss8_uwm/orig-dectapes/INIT.CM: -------------------------------------------------------------------------------- 1 | DSK:INIT 7 | #include 8 | #include 9 | #include 10 | 11 | size_t binfile_size; 12 | 13 | unsigned char binfile[64*1024]; 14 | 15 | main(int argc, char *argv[]) 16 | { 17 | if (argc > 1) { 18 | int f, ret; 19 | char ch; 20 | 21 | f = open(argv[1], O_RDONLY); 22 | if (f < 0) { 23 | perror(argv[1]); 24 | return -1; 25 | } 26 | 27 | while (1) { 28 | ret = read(f, &ch, 1); 29 | if (ret != 1) 30 | return -1; 31 | if (ch == 'Z'-'@') 32 | break; 33 | } 34 | 35 | binfile_size = read(f, binfile, sizeof(binfile)); 36 | ret = write(1, binfile, binfile_size); 37 | close(f); 38 | } 39 | 40 | exit(0); 41 | } 42 | 43 | 44 | /* 45 | * Local Variables: 46 | * indent-tabs-mode:nil 47 | * c-basic-offset:4 48 | * End: 49 | */ 50 | -------------------------------------------------------------------------------- /utils/ushow/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | 3 | all: ushow 4 | 5 | ushow: ushow.c 6 | cc -o ushow ushow.c 7 | 8 | clean: 9 | rm -f ushow 10 | -------------------------------------------------------------------------------- /utils/ushow/ushow.c: -------------------------------------------------------------------------------- 1 | /* 2 | * grab tt output from verilog simulator log file 3 | * brad@heeltoe.com 4 | * 5 | * as in, "cat verilog.log | ./ushow" 6 | * 7 | * displays tt output in a rational manner 8 | */ 9 | 10 | #include 11 | #include 12 | 13 | int c; 14 | char b[1024*16]; 15 | 16 | int show_cummulative = 0; 17 | int show_rx = 0; 18 | int show_int = 0; 19 | 20 | void show(void) 21 | { 22 | printf("\n-------\noutput: %s\n", b); 23 | printf("\n"); 24 | fflush(stdout); 25 | } 26 | 27 | void show_part(void) 28 | { 29 | printf("%s", b); 30 | fflush(stdout); 31 | c = 0; 32 | } 33 | 34 | void add_int(void) 35 | { 36 | b[c++] = '*'; 37 | b[c] = 0; 38 | if (show_cummulative) { 39 | show_part(); 40 | } 41 | } 42 | 43 | void add_rx(int v) 44 | { 45 | v &= 0x7f; 46 | b[c++] = '['; 47 | if (v >= ' ') 48 | b[c++] = v; 49 | else { 50 | c += sprintf(&b[c], "\\%03o", v); 51 | } 52 | b[c++] = ']'; 53 | b[c] = 0; 54 | if (show_cummulative) { 55 | show_part(); 56 | } 57 | } 58 | 59 | void add(int v) 60 | { 61 | v &= 0x7f; 62 | if (v == 0) v = '@'; 63 | b[c++] = v; 64 | b[c] = 0; 65 | if (show_cummulative) { 66 | show_part(); 67 | } 68 | } 69 | 70 | main(int argc, char *argv[]) 71 | { 72 | char line[1024]; 73 | int i; 74 | 75 | for (i = 1; i < argc; i++) { 76 | if (argv[i][0] == '-') 77 | switch (argv[i][1]) { 78 | case 's': show_cummulative = 1; break; 79 | case 'r': show_rx = 1; break; 80 | case 'i': show_int = 1; break; 81 | } 82 | } 83 | 84 | while (fgets(line, sizeof(line), stdin)) { 85 | int v; 86 | 87 | if (memcmp(&line[4], "tx_data ", 8) == 0) { 88 | sscanf(line, "xxx tx_data %o", &v); 89 | add(v); 90 | } 91 | 92 | #if 0 93 | if (memcmp(&line[4], "rx_data ", 8) == 0) { 94 | sscanf(line, "xxx rx_data %o", &v); 95 | if (show_rx) 96 | add_rx(v); 97 | } 98 | #else 99 | if (memcmp(&line[4], "dispense ", 9) == 0) { 100 | sscanf(line, "xxx dispense %o", &v); 101 | if (show_rx) 102 | add_rx(v); 103 | } 104 | #endif 105 | if (memcmp(&line[4], "interrupt", 9) == 0) { 106 | if (show_int) 107 | add_int(); 108 | } 109 | 110 | 111 | if (memcmp(&line[4], "rx input ", 9) == 0) { 112 | sscanf(line, "xxx rx input %o", &v); 113 | if (show_rx) 114 | add_rx(v); 115 | } 116 | if (memcmp(&line[4], "int_req ", 8) == 0) { 117 | if (show_int) 118 | add_int(); 119 | } 120 | if (memcmp(line, "reset on", 8) == 0) { 121 | c = 0; 122 | printf("\n"); 123 | } 124 | } 125 | 126 | show(); 127 | } 128 | -------------------------------------------------------------------------------- /v/fpga.ucf: -------------------------------------------------------------------------------- 1 | net clka loc=r8; 2 | #net clkb loc=b8; 3 | net reset_n loc=e3; 4 | 5 | net ps2_clk loc=f4; 6 | net ps2_data loc=e1; 7 | 8 | net vga_blue0 loc=h4; 9 | net vga_blue1 loc=k3; 10 | net vga_blue2 loc=l5; 11 | net vga_green0 loc=h2; 12 | net vga_green1 loc=k5; 13 | net vga_green2 loc=r1; 14 | net vga_red0 loc=j1; 15 | net vga_red1 loc=m1; 16 | net vga_red2 loc=t2; 17 | net vga_hsync_n loc=k4; 18 | net vga_vsync_n loc=k1; 19 | 20 | net fpga_din_d0 loc=d14; 21 | net fpga_d1 loc=e16; 22 | net fpga_d2 loc=f15; 23 | net fpga_d3 loc=g16; 24 | net fpga_d4 loc=j16; 25 | net fpga_d5 loc=m16; 26 | net fpga_d6 loc=n16; 27 | net fpga_d7 loc=n14; 28 | -------------------------------------------------------------------------------- /v/fpga.v: -------------------------------------------------------------------------------- 1 | // fpga.v 2 | 3 | module fpga (clka, 4 | reset_n, 5 | ps2_clk, 6 | ps2_data, 7 | vga_blue0, 8 | vga_blue1, 9 | vga_blue2, 10 | vga_green0, 11 | vga_green1, 12 | vga_green2, 13 | vga_red0, 14 | vga_red1, 15 | vga_red2, 16 | vga_hsync_n, 17 | vga_vsync_n, 18 | fpga_din_d0, 19 | fpga_d1, 20 | fpga_d2, 21 | fpga_d3, 22 | fpga_d4, 23 | fpga_d5, 24 | fpga_d6, 25 | fpga_d7 26 | ); 27 | 28 | input clka; // 100mhz 29 | input reset_n; 30 | 31 | input ps2_clk, ps2_data; 32 | 33 | output vga_blue0, vga_blue1, vga_blue2; 34 | output vga_green0, vga_green1, vga_green2; 35 | output vga_red0, vga_red1, vga_red2; 36 | output vga_hsync_n, vga_vsync_n; 37 | 38 | output fpga_din_d0, fpga_d1, fpga_d2, fpga_d3, 39 | fpga_d4, fpga_d5, fpga_d6, fpga_d7; 40 | 41 | // 42 | wire hsync, vsync; 43 | wire [8:0] pixel; 44 | 45 | // 46 | wire [7:0] led_data; 47 | 48 | // signals to create a 25MHz clock from the 100MHz input clock 49 | wire clk25; 50 | reg [1:0] gray_cnt; 51 | 52 | // clock divider by 4 to for a slower clock 53 | // uses grey code for minimized logic 54 | always @(posedge clka or negedge reset_n) 55 | if (~reset_n) 56 | gray_cnt <= 2'b00; 57 | else 58 | case (gray_cnt) 59 | 2'b00: gray_cnt <= 2'b01; 60 | 2'b01: gray_cnt <= 2'b11; 61 | 2'b11: gray_cnt <= 2'b10; 62 | 2'b10: gray_cnt <= 2'b00; 63 | default: gray_cnt <= 2'b00; 64 | endcase 65 | 66 | // assign 25mhz clock 67 | assign clk25 = gray_cnt[1]; 68 | 69 | vga vga (.reset_n(reset_n), 70 | .clock(clk25), 71 | .pixel(pixel), 72 | .blank_n(), 73 | .hsync(hsync), 74 | .vsync(vsync), 75 | .ps2_clk(ps2_clk), 76 | .ps2_data(ps2_data), 77 | .led_data(led_data)); 78 | 79 | assign vga_hsync_n = ~hsync; 80 | assign vga_vsync_n = ~vsync; 81 | 82 | assign {vga_red2, vga_red1, vga_red0, 83 | vga_green2, vga_green1, vga_green0, 84 | vga_blue2, vga_blue1, vga_blue0} = pixel; 85 | 86 | assign {fpga_din_d0, fpga_d1, fpga_d2, fpga_d3, 87 | fpga_d4, fpga_d5, fpga_d6, fpga_d7} = led_data; 88 | 89 | endmodule // fpga 90 | -------------------------------------------------------------------------------- /v/fpga2.ucf: -------------------------------------------------------------------------------- 1 | net clka loc=r8; 2 | #net clkb loc=b8; 3 | net reset_n loc=e3; 4 | 5 | net ps2_clk loc=f4; 6 | net ps2_data loc=e1; 7 | 8 | #net vga_blue0 loc=h4; 9 | #net vga_blue1 loc=k3; 10 | #net vga_blue2 loc=l5; 11 | #net vga_green0 loc=h2; 12 | #net vga_green1 loc=k5; 13 | #net vga_green2 loc=r1; 14 | #net vga_red0 loc=j1; 15 | #net vga_red1 loc=m1; 16 | #net vga_red2 loc=t2; 17 | #net vga_hsync_n loc=k4; 18 | #net vga_vsync_n loc=k1; 19 | 20 | net fpga_din_d0 loc=d14; 21 | net fpga_d1 loc=e16; 22 | net fpga_d2 loc=f15; 23 | net fpga_d3 loc=g16; 24 | net fpga_d4 loc=j16; 25 | net fpga_d5 loc=m16; 26 | net fpga_d6 loc=n16; 27 | net fpga_d7 loc=n14; 28 | -------------------------------------------------------------------------------- /v/fpga2.v: -------------------------------------------------------------------------------- 1 | // fpga2.v 2 | 3 | // simple test module for ps2 module 4 | 5 | module fpga (clka, 6 | clkb, 7 | reset_n, 8 | ps2_clk, 9 | ps2_data, 10 | vga_blue0, 11 | vga_blue1, 12 | vga_blue2, 13 | vga_green0, 14 | vga_green1, 15 | vga_green2, 16 | vga_red0, 17 | vga_red1, 18 | vga_red2, 19 | vga_hsync_n, 20 | vga_vsync_n, 21 | fpga_din_d0, 22 | fpga_d1, 23 | fpga_d2, 24 | fpga_d3, 25 | fpga_d4, 26 | fpga_d5, 27 | fpga_d6, 28 | fpga_d7 29 | ); 30 | 31 | input clka; // 100mhz 32 | input clkb; // 50mhz 33 | input reset_n; 34 | 35 | input ps2_clk, ps2_data; 36 | 37 | output vga_blue0, vga_blue1, vga_blue2; 38 | output vga_green0, vga_green1, vga_green2; 39 | output vga_red0, vga_red1, vga_red2; 40 | output vga_hsync_n, vga_vsync_n; 41 | 42 | output fpga_din_d0, fpga_d1, fpga_d2, fpga_d3, 43 | fpga_d4, fpga_d5, fpga_d6, fpga_d7; 44 | 45 | // 46 | wire hsync, vsync; 47 | wire [8:0] pixel; 48 | 49 | // signals to create a 25MHz clock from the 100MHz input clock 50 | wire clk25; 51 | reg [1:0] gray_cnt; 52 | 53 | // clock divider by 4 to for a slower clock 54 | // uses grey code for minimized logic 55 | always @(posedge clka or negedge reset_n) 56 | if (~reset_n) 57 | gray_cnt <= 2'b00; 58 | else 59 | case (gray_cnt) 60 | 2'b00: gray_cnt <= 2'b01; 61 | 2'b01: gray_cnt <= 2'b11; 62 | 2'b11: gray_cnt <= 2'b10; 63 | 2'b10: gray_cnt <= 2'b00; 64 | default: gray_cnt <= 2'b00; 65 | endcase 66 | 67 | // assign the clock that this entity runs off 68 | assign clk25 = gray_cnt[1]; 69 | 70 | wire kb_rdy; 71 | wire kb_bsy; 72 | wire [7:0] kb_scancode; 73 | 74 | wire [7:0] data; 75 | 76 | ps2 ps2(.clk(clk25), 77 | .rst_n(reset_n), 78 | .ps2_clk(ps2_clk), 79 | .ps2_data(ps2_data), 80 | .scancode(kb_scancode), 81 | .parity(), 82 | .busy(kb_bsy), 83 | .rdy(kb_rdy), 84 | .error()); 85 | 86 | //xc2s200-5fg256 87 | 88 | reg rdy; 89 | 90 | always @(posedge kb_rdy or negedge reset_n) 91 | if (~reset_n) 92 | rdy <= 0; 93 | else 94 | rdy <= ~rdy; 95 | 96 | assign {fpga_din_d0, fpga_d1, fpga_d2, fpga_d3, 97 | fpga_d4, fpga_d5, fpga_d6, fpga_d7} = 98 | { kb_scancode[6], rdy, kb_scancode[5:0] }; 99 | 100 | endmodule // fpga 101 | -------------------------------------------------------------------------------- /v/fpga3.v: -------------------------------------------------------------------------------- 1 | // fpga2.v 2 | 3 | // simple test module for scancode module 4 | 5 | module fpga (clka, 6 | clkb, 7 | reset_n, 8 | ps2_clk, 9 | ps2_data, 10 | vga_blue0, 11 | vga_blue1, 12 | vga_blue2, 13 | vga_green0, 14 | vga_green1, 15 | vga_green2, 16 | vga_red0, 17 | vga_red1, 18 | vga_red2, 19 | vga_hsync_n, 20 | vga_vsync_n, 21 | fpga_din_d0, 22 | fpga_d1, 23 | fpga_d2, 24 | fpga_d3, 25 | fpga_d4, 26 | fpga_d5, 27 | fpga_d6, 28 | fpga_d7 29 | ); 30 | 31 | input clka; // 100mhz 32 | input clkb; // 50mhz 33 | input reset_n; 34 | 35 | input ps2_clk, ps2_data; 36 | 37 | output vga_blue0, vga_blue1, vga_blue2; 38 | output vga_green0, vga_green1, vga_green2; 39 | output vga_red0, vga_red1, vga_red2; 40 | output vga_hsync_n, vga_vsync_n; 41 | 42 | output fpga_din_d0, fpga_d1, fpga_d2, fpga_d3, 43 | fpga_d4, fpga_d5, fpga_d6, fpga_d7; 44 | 45 | // 46 | wire hsync, vsync; 47 | wire [8:0] pixel; 48 | 49 | // signals to create a 25MHz clock from the 100MHz input clock 50 | wire clk25; 51 | reg [1:0] gray_cnt; 52 | 53 | // clock divider by 4 to for a slower clock 54 | // uses grey code for minimized logic 55 | always @(posedge clka or negedge reset_n) 56 | if (~reset_n) 57 | gray_cnt <= 2'b00; 58 | else 59 | case (gray_cnt) 60 | 2'b00: gray_cnt <= 2'b01; 61 | 2'b01: gray_cnt <= 2'b11; 62 | 2'b11: gray_cnt <= 2'b10; 63 | 2'b10: gray_cnt <= 2'b00; 64 | default: gray_cnt <= 2'b00; 65 | endcase 66 | 67 | // assign the clock that this entity runs off 68 | assign clk25 = gray_cnt[1]; 69 | 70 | reg [7:0] kb_scancode; 71 | reg kb_rdy; 72 | 73 | wire [7:0] kb_ascii; 74 | wire kb_release; 75 | wire kb_ascii_rdy; 76 | 77 | scancode_convert scancode_convert(.clock(clk25), 78 | .reset_n(reset_n), 79 | .scancode(kb_scancode), 80 | .ascii(kb_ascii), 81 | .key_up(kb_release), 82 | .strobe_in(kb_rdy), 83 | .strobe_out(kb_ascii_rdy)); 84 | 85 | //xc2s200-5fg256 86 | 87 | reg [2:0] clk8; 88 | always @(posedge clk25 or negedge reset_n) 89 | if (~reset_n) 90 | clk8 = 3'b111; 91 | else 92 | clk8 = clk8 + 1; 93 | 94 | always @(posedge clk25 or negedge reset_n) 95 | if (~reset_n) 96 | kb_scancode = 0; 97 | else 98 | if (clk8 == 8'b111) 99 | begin 100 | kb_scancode = kb_scancode + 1; 101 | kb_rdy = 1; 102 | end 103 | else 104 | kb_rdy = 0; 105 | 106 | assign {fpga_din_d0, fpga_d1, fpga_d2, fpga_d3, 107 | fpga_d4, fpga_d5, fpga_d6, fpga_d7} = kb_ascii; 108 | 109 | endmodule // fpga 110 | -------------------------------------------------------------------------------- /v/run.v: -------------------------------------------------------------------------------- 1 | // run.v 2 | 3 | `include "vga.v" 4 | 5 | `timescale 1ns / 1ns 6 | 7 | module test; 8 | 9 | reg clk, reset_n; 10 | 11 | wire [8:0] pixel; 12 | wire blank_n; 13 | wire hsync; 14 | wire vsync; 15 | reg ps2_clk; 16 | reg ps2_data; 17 | wire [7:0] led_data; 18 | 19 | vga vga(.reset_n(reset_n), 20 | .clock(clk25), 21 | .pixel(pixel), 22 | .blank_n(blank_n), 23 | .hsync(hsync), 24 | .vsync(vsync), 25 | .ps2_clk(ps2_clk), 26 | .ps2_data(ps2_data), 27 | .led_data(led_data)); 28 | 29 | // clock divider by 4 to for a slower clock 30 | // uses grey code for minimized logic 31 | reg [1:0] gray_cnt; 32 | 33 | always @(posedge clk or negedge reset_n) 34 | if (~reset_n) 35 | gray_cnt <= 2'b00; 36 | else 37 | case (gray_cnt) 38 | 2'b00: gray_cnt <= 2'b01; 39 | 2'b01: gray_cnt <= 2'b11; 40 | 2'b11: gray_cnt <= 2'b10; 41 | 2'b10: gray_cnt <= 2'b00; 42 | default: gray_cnt <= 2'b00; 43 | endcase 44 | 45 | wire clk25; 46 | assign clk25 = gray_cnt[1]; 47 | 48 | initial 49 | begin 50 | $timeformat(-9, 0, "ns", 7); 51 | 52 | $dumpfile("vga.vcd"); 53 | // $dumpvars(0, test.vga); 54 | $dumpvars(0, test); 55 | end 56 | 57 | initial 58 | begin 59 | clk = 0; 60 | reset_n = 1; 61 | ps2_clk <= 0; 62 | ps2_data <= 0; 63 | 64 | #1 begin 65 | reset_n = 0; 66 | end 67 | 68 | #100 begin 69 | reset_n = 1; 70 | end 71 | 72 | #400000 73 | begin 74 | vga.scancode_convert.strobe_out = 1; 75 | vga.crt_data = 8'h41; 76 | vga.scancode_convert.ascii = 8'h41; 77 | end 78 | #200 vga.scancode_convert.strobe_out = 0; 79 | 80 | #400 81 | begin 82 | vga.scancode_convert.strobe_out = 1; 83 | vga.crt_data = 8'h42; 84 | vga.scancode_convert.ascii = 8'h42; 85 | end 86 | #200 vga.scancode_convert.strobe_out = 0; 87 | 88 | // #100000 $finish; 89 | // #500000 $finish; 90 | // #1000000 $finish; 91 | #20000000 $finish; 92 | end 93 | 94 | always 95 | begin 96 | #5 clk = 0; 97 | #5 clk = 1; 98 | end 99 | 100 | endmodule 101 | 102 | -------------------------------------------------------------------------------- /v/video_mem.v: -------------------------------------------------------------------------------- 1 | // video_mem.v 2 | 3 | /* 1kx32 static ram */ 4 | 5 | module video_ram(addr, data_in, data_out, ce_n, we_n); 6 | 7 | input [10:0] addr; 8 | input [7:0] data_in; 9 | input ce_n, we_n; 10 | output [7:0] data_out; 11 | 12 | reg [7:0] ram [0:2047]; 13 | 14 | always @(negedge we_n) 15 | begin 16 | if (ce_n == 0) 17 | ram[addr] = data_in; 18 | end 19 | 20 | assign data_out = ram[addr]; 21 | endmodule 22 | 23 | 24 | -------------------------------------------------------------------------------- /v/video_ram.v: -------------------------------------------------------------------------------- 1 | // video_mem.v 2 | 3 | /* 2kx8 static sync ram */ 4 | 5 | module video_ram(addr, data_in, data_out, clk_r, clk_w, we_n); 6 | 7 | input [11:0] addr; 8 | input [7:0] data_in; 9 | input clk_r, clk_w, we_n; 10 | output [7:0] data_out; 11 | 12 | reg [7:0] ram [0:2048]; 13 | reg [11:0] ram_addr_w; 14 | reg [11:0] ram_addr_r; 15 | 16 | always @(posedge clk_w) 17 | begin 18 | ram_addr_w <= addr; 19 | if (we_n == 0) 20 | ram[ram_addr_w] <= data_in; 21 | end 22 | 23 | always @(posedge clk_r) 24 | begin 25 | ram_addr_r <= addr; 26 | end 27 | 28 | assign data_out = ram[ram_addr_r]; 29 | 30 | // assign data_out = 8'h20 + addr[7:0]; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /v/xsa-200.ucf: -------------------------------------------------------------------------------- 1 | net clka loc=r8; 2 | net clkb loc=b8; 3 | 4 | net ps2_clk loc=f4; 5 | net ps2_data loc=e1; 6 | 7 | net vga_blue0 loc=h4; 8 | net vga_blue1 loc=k3; 9 | net vga_blue2 loc=l5; 10 | net vga_green0 loc=h2; 11 | net vga_green1 loc=k5; 12 | net vga_green2 loc=r1; 13 | net vga_red0 loc=j1; 14 | net vga_red1 loc=m1; 15 | net vga_red2 loc=t2; 16 | net vga_hsync_n loc=k4; 17 | net vga_vsync_n loc=k1; 18 | -------------------------------------------------------------------------------- /verif/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CVER_FLAGS = +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap 3 | #CVER_FLAGS = 4 | 5 | RTESTS = test_tt test_rf test_io 6 | 7 | RTL = \ 8 | ../rtl/pdp8_tt.v ../rtl/pdp8_rf.v ../rtl/pdp8_io.v \ 9 | ../rtl/pdp8_ram.v ../rtl/ram_32kx12.v ../rtl/ram_256x12.v \ 10 | ../rtl/ide_disk.v ../rtl/ide.v \ 11 | ../rtl/top.v \ 12 | ../rtl/pdp8.v 13 | 14 | all: regress 15 | 16 | #--------------------------------------------------------------------- 17 | 18 | #cver +showpc +test=../tests/diags/MAINDEX-08-D1GB.mem +pc=0326 +switches=7777 +cycles=20 test_pdp8.v 19 | 20 | #cver +test=../tests/diags/MAINDEC-8I-D01C.mem +pc=0200 +switches=7777 +cycles=2000000 test_pdp8.v 21 | 22 | #cver +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v 23 | 24 | #cver +showpc +cycles=5000 +test=tss8_init.mem +pc=24200 +cycles=2000000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v 25 | 26 | #cver +showpc +cycles=100000 +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v > xx 27 | 28 | define runone_verilog_regression 29 | cver $(CVER_FLAGS) $(1) >$(2); 30 | @if grep -q ERROR $(2); then exit 1; fi; 31 | @if grep -q FAILURE $(2); then exit 1; fi; 32 | @echo success 33 | endef 34 | 35 | RTEST_LOGS = $(addsuffix .log,$(RTESTS)) 36 | 37 | $(RTEST_LOGS) : %.log : %.v $(RTL) 38 | $(call runone_verilog_regression,$<,$@) 39 | 40 | # verilog testbench regression tests 41 | regress: $(RTEST_LOGS) 42 | 43 | test_tt: test_tt.v 44 | $(call runone_verilog_regression,$<,$@) 45 | 46 | test_rf: test_rf.v 47 | $(call runone_verilog_regression,$<,$@) 48 | echo ok 49 | 50 | test_io: test_io.v 51 | $(call runone_verilog_regression,$<,$@) 52 | echo ok 53 | 54 | # 55 | clean: 56 | rm -f verilog.log 57 | rm -f *.vcd *.log 58 | -------------------------------------------------------------------------------- /verif/fake_ide.v: -------------------------------------------------------------------------------- 1 | 2 | module fake_ide(ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus); 3 | 4 | input ide_dior; 5 | input ide_diow; 6 | input [1:0] ide_cs; 7 | input [2:0] ide_da; 8 | inout [15:0] ide_data_bus; 9 | 10 | reg [7:0] data_out; 11 | reg [7:0] cmd; 12 | reg [7:0] status; 13 | reg [7:0] drvhead; 14 | 15 | integer fifo; 16 | 17 | wire is_rd; 18 | wire is_wr; 19 | 20 | assign is_rd = ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0); 21 | assign is_wr = ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0); 22 | 23 | assign ide_data_bus = is_rd ? data_out : 12'bz; 24 | 25 | initial 26 | begin 27 | status = 8'h50; 28 | end 29 | 30 | always @(*) 31 | begin 32 | if (ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0)) 33 | begin 34 | if (ide_da != 0) 35 | #1 $display("ide r cs %b; da %b; bus %x", 36 | ide_cs, ide_da, ide_data_bus); 37 | case (ide_da) 38 | 3'd0: 39 | begin 40 | if (fifo > 0) 41 | begin 42 | data_out = 0; 43 | fifo = fifo - 1; 44 | //$display("fifo %d", fifo); 45 | end 46 | if (fifo == 0) 47 | begin 48 | $display("ide empty!"); 49 | status = 8'h50; 50 | cmd = 0; 51 | end 52 | end 53 | 3'd7: 54 | data_out = status; 55 | endcase 56 | 57 | end 58 | if (ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0)) 59 | begin 60 | #1 $display("ide w cs %b; da %b; bus %x", 61 | ide_cs, ide_da, ide_data_bus); 62 | case (ide_da) 63 | 3'd6: 64 | drvhead = ide_data_bus; 65 | 66 | 3'd7: 67 | begin 68 | //release ide_data_bus; 69 | cmd = ide_data_bus; 70 | #1 $display("ide cmd %x", cmd); 71 | case (cmd) 72 | 8'h20: 73 | begin 74 | status = 8'h58; 75 | fifo = 256; 76 | end 77 | endcase 78 | end 79 | endcase 80 | end 81 | end 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /verif/fake_ram.v: -------------------------------------------------------------------------------- 1 | module fake_ram(clk, reset, 2 | ram_read_req, ram_write_req, ram_done, 3 | ram_ma, ram_in, ram_out); 4 | 5 | input clk; 6 | input reset; 7 | 8 | input ram_read_req; 9 | input ram_write_req; 10 | 11 | output ram_done; 12 | 13 | input [14:0] ram_ma; 14 | input [11:0] ram_in; 15 | output [11:0] ram_out; 16 | 17 | //-------------- 18 | 19 | reg [11:0] ram [0:32767]; 20 | integer i; 21 | integer ram_debug; 22 | 23 | initial 24 | begin 25 | ram_debug = 0; 26 | for (i = 0; i < 32768; i=i+1) 27 | ram[i] = 12'b0; 28 | end 29 | 30 | reg [2:0] ram_state; 31 | wire [2:0] ram_state_next; 32 | 33 | always @(posedge clk) 34 | if (reset) 35 | ram_state <= 0; 36 | else 37 | ram_state <= ram_state_next; 38 | 39 | assign ram_state_next = 40 | (ram_state == 0 && ram_read_req) ? 1 : 41 | (ram_state == 1) ? 0 : 42 | (ram_state == 0 && ram_write_req) ? 2 : 43 | (ram_state == 2) ? 0 : 44 | 0; 45 | assign ram_done = ram_state == 1 || ram_state == 2; 46 | 47 | always @(ram_state) 48 | begin 49 | if (ram_state == 2) 50 | begin 51 | if (ram_debug) $display("ram: write [%o] <- %o", ram_ma, ram_in); 52 | ram[ ram_ma ] = ram_in; 53 | end 54 | 55 | if (ram_state == 1) 56 | begin 57 | if (ram_debug) $display("ram: read [%o] -> %o", ram_ma, ram[ram_ma]); 58 | end 59 | end 60 | 61 | assign ram_out = ram[ ram_ma ]; 62 | 63 | endmodule 64 | 65 | -------------------------------------------------------------------------------- /verif/run.sh: -------------------------------------------------------------------------------- 1 | ../cver/gplcver-2.12a.src/bin/cver \ 2 | +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \ 3 | +define+use_fake_uart=1 \ 4 | +showpc \ 5 | +cycles=2000000 \ 6 | +pc=07400 \ 7 | test_pdp8.v 8 | exit 0 9 | 10 | # +loadvpi=../pli/disassemble/pli_disassemble.so:vpi_compat_bootstrap \ 11 | # 12 | 13 | cver \ 14 | +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \ 15 | +loadvpi=../pli/disassemble/pli_disassemble.so:vpi_compat_bootstrap \ 16 | +showpc \ 17 | +cycles=2000000 \ 18 | +pc=07400 \ 19 | test_pdp8.v 20 | exit 0 21 | 22 | cver \ 23 | +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \ 24 | +test=../tests/basic/user.mem +pc=0400 \ 25 | +showpc \ 26 | +cycles=100 \ 27 | +define+no_fake_input=1 \ 28 | test_pdp8.v 29 | exit 0 30 | 31 | 32 | # +test=tss8_init.mem +pc=24200 \ 33 | # 34 | 35 | #cver +showpc +test=../tests/diags/MAINDEC-08-D5FA.mem +pc=0150 +switches=0000 +cycles=200000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >zz 36 | 37 | #cver +showpc +test=../tests/diags/MAINDEC-08-D5EB.mem +pc=0200 +switches=4000 +cycles=50000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >zz 38 | 39 | #cver +cycles=1000000 +test=boot.mem +pc=7750 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >yy2 40 | 41 | #grep "rf: go\!" xx 42 | #cat xx | ../utils/ushow/ushow 43 | -------------------------------------------------------------------------------- /verif/run_rf.sh: -------------------------------------------------------------------------------- 1 | ../cver/gplcver-2.12a.src/bin/cver \ 2 | +loadvpi=../pli/rf/pli_rf.so:vpi_compat_bootstrap \ 3 | +define+use_rf_pli=1 \ 4 | +define+use_fake_uart=1 \ 5 | +define+sim_time_kw=1 \ 6 | +showpc \ 7 | +cycles=2000000 \ 8 | +pc=07400 \ 9 | test_pdp8.v 10 | exit 0 11 | 12 | -------------------------------------------------------------------------------- /verif/run_tt.sh: -------------------------------------------------------------------------------- 1 | ../cver/gplcver-2.12a.src/bin/cver \ 2 | +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \ 3 | +test=../tests/basic/uart.mem +pc=00400 \ 4 | +define+debug_vcd=1 \ 5 | +showpc \ 6 | +cycles=100000 \ 7 | test_pdp8.v 8 | exit 0 9 | 10 | -------------------------------------------------------------------------------- /verif/runtest.sh: -------------------------------------------------------------------------------- 1 | ../cver/gplcver-2.12a.src/bin/cver \ 2 | +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \ 3 | test_rf.v 4 | exit 0 5 | 6 | -------------------------------------------------------------------------------- /verif/test_io.v: -------------------------------------------------------------------------------- 1 | // run_io.v 2 | // testing top end for pdp8_io.v 3 | // 4 | 5 | `define debug 6 | `define sim_time 7 | 8 | `include "../rtl/pdp8_tt.v" 9 | `include "../rtl/pdp8_rf.v" 10 | `include "../rtl/pdp8_kw.v" 11 | `include "../rtl/pdp8_io.v" 12 | 13 | `include "../verif/fake_uart.v" 14 | `include "../rtl/brg.v" 15 | 16 | `include "../rtl/ide_disk.v" 17 | `include "../rtl/ide.v" 18 | `include "../rtl/ram_256x12.v" 19 | 20 | 21 | `timescale 1ns / 1ns 22 | 23 | module test; 24 | 25 | reg clk, reset; 26 | 27 | wire [11:0] io_data_in; 28 | wire [11:0] io_data_out; 29 | wire io_data_avail; 30 | wire io_interrupt; 31 | wire io_skip; 32 | wire io_clear_ac; 33 | wire [5:0] io_select; 34 | 35 | wire iot; 36 | wire [3:0] state; 37 | wire [11:0] mb; 38 | 39 | wire ext_ram_read_req; 40 | wire ext_ram_write_req; 41 | wire [14:0] ext_ram_ma; 42 | wire [11:0] ext_ram_in; 43 | wire ext_ram_done; 44 | wire [11:0] ext_ram_out; 45 | 46 | wire [15:0] ide_data_bus; 47 | wire ide_dior, ide_diow; 48 | wire [1:0] ide_cs; 49 | wire [2:0] ide_da; 50 | 51 | reg rs232_in; 52 | wire rs232_out; 53 | 54 | pdp8_io io(.clk(clk), 55 | .brgclk(clk), 56 | .reset(reset), 57 | .iot(iot), 58 | .state(state), 59 | .mb(mb), 60 | .io_data_in(io_data_out), 61 | .io_data_out(io_data_in), 62 | .io_select(io_select), 63 | .io_data_avail(io_data_avail), 64 | .io_interrupt(io_interrupt), 65 | .io_skip(io_skip), 66 | .io_clear_ac(io_clear_ac), 67 | .io_ram_read_req(ext_ram_read_req), 68 | .io_ram_write_req(ext_ram_write_req), 69 | .io_ram_done(ext_ram_done), 70 | .io_ram_ma(ext_ram_ma), 71 | .io_ram_in(ext_ram_in), 72 | .io_ram_out(ext_ram_out), 73 | .ide_dior(ide_dior), 74 | .ide_diow(ide_diow), 75 | .ide_cs(ide_cs), 76 | .ide_da(ide_da), 77 | .ide_data_bus(ide_data_bus), 78 | .rs232_in(rs232_in), 79 | .rs232_out(rs232_out)); 80 | 81 | initial 82 | begin 83 | $timeformat(-9, 0, "ns", 7); 84 | 85 | $dumpfile("pdp8_io.vcd"); 86 | $dumpvars(0, test.io); 87 | end 88 | 89 | initial 90 | begin 91 | clk = 0; 92 | reset = 0; 93 | rs232_in = 0; 94 | 95 | #1 begin 96 | reset = 1; 97 | end 98 | 99 | #50 begin 100 | reset = 0; 101 | end 102 | 103 | #3000 $finish; 104 | end 105 | 106 | always 107 | begin 108 | #10 clk = 0; 109 | #10 clk = 1; 110 | end 111 | 112 | //---- 113 | integer cycle; 114 | 115 | initial 116 | cycle = 0; 117 | 118 | always @(posedge io.clk) 119 | begin 120 | cycle = cycle + 1; 121 | end 122 | 123 | endmodule 124 | 125 | -------------------------------------------------------------------------------- /verif/tss8.cmd: -------------------------------------------------------------------------------- 1 | set rf enabled 2 | set df disabled 3 | set lp disabled 4 | set ptr disabled 5 | set ptp disabled 6 | set ttix disabled 7 | set ttox disabled 8 | set rk disabled 9 | set rx disabled 10 | set mt disabled 11 | attach rf rf.dsk 12 | boot rf 13 | exit 14 | 15 | 16 | -------------------------------------------------------------------------------- /verif/verilator.sh: -------------------------------------------------------------------------------- 1 | verilator -cc -exe --trace --Mdir ./tmp --top-module test verilator_pdp8.v ../verilator/test.cpp ../verilator/ide.cpp && \ 2 | (cd tmp; make OPT="-O2" -f Vtest.mk) 3 | -------------------------------------------------------------------------------- /verilator/ram.cpp: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "Vtest_top__Dpi.h" 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | unsigned char ram_h[262144]; 11 | unsigned char ram_l[262144]; 12 | 13 | static int last_r; 14 | static int last_w; 15 | 16 | void dpi_ram (int a, int r, int w, int u, int l, int in, int* out) 17 | { 18 | int o; 19 | int assert_r, assert_w; 20 | 21 | assert_r = r && !last_r; 22 | assert_w = w && !last_w; 23 | 24 | last_r = r; 25 | last_w = w; 26 | 27 | o = 0; 28 | if (r) { 29 | if (u) o |= ram_h[a] << 8; 30 | if (l) o |= ram_l[a]; 31 | if (assert_r) printf("dpi_ram: read [%o] -> %o\n", a, o); 32 | } 33 | *out = o; 34 | 35 | if (w) { 36 | if (u) ram_h[a] = in >> 8; 37 | if (l) ram_l[a] = in; 38 | if (assert_w) printf("dpi_ram: write [%o] -> %o\n", a, in); 39 | } 40 | } 41 | 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | -------------------------------------------------------------------------------- /verilator/test.cpp: -------------------------------------------------------------------------------- 1 | // 2 | // test.cpp 3 | // 4 | // 5 | 6 | #include 7 | #include 8 | #include "Vtest.h" 9 | 10 | #include 11 | 12 | Vtest *top; // Instantiation of module 13 | 14 | unsigned int main_time = 0; // Current simulation time 15 | 16 | double sc_time_stamp () { // Called by $time in Verilog 17 | return main_time; 18 | } 19 | 20 | int main(int argc, char** argv) 21 | { 22 | VerilatedVcdC* tfp = NULL; 23 | Verilated::commandArgs(argc, argv); // Remember args 24 | 25 | top = new Vtest; // Create instance 26 | 27 | #ifdef VM_TRACE 28 | if (0) { 29 | Verilated::traceEverOn(true); 30 | VL_PRINTF("Enabling waves...\n"); 31 | tfp = new VerilatedVcdC; 32 | top->trace(tfp, 99); // Trace 99 levels of hierarchy 33 | tfp->open("test.vcd"); // Open the dump file 34 | } 35 | #endif 36 | 37 | top->v__DOT__io__DOT__rf__DOT__buffer__DOT__ram_debug = 1; 38 | top->v__DOT__sysclk = 0; 39 | 40 | while (!Verilated::gotFinish()) { 41 | 42 | // Resets 43 | if (main_time < 500) { 44 | if (main_time == 20) { 45 | VL_PRINTF("reset on\n"); 46 | top->v__DOT__reset = 1; 47 | top->v__DOT__initial_pc = 07400; 48 | } 49 | if (main_time == 50) { 50 | VL_PRINTF("reset off\n"); 51 | top->v__DOT__reset = 0; 52 | } 53 | } 54 | 55 | // Toggle clock 56 | top->v__DOT__sysclk = ~top->v__DOT__sysclk; 57 | 58 | // Evaluate model 59 | top->eval(); 60 | 61 | //if (top->v__DOT__sysclk) { 62 | //printf("state %d\n", top->v__DOT__state); 63 | //} 64 | 65 | if (top->v__DOT__sysclk && 66 | top->v__DOT__state == 1) 67 | { 68 | VL_PRINTF("pc %o ir %o l%d ac %o ion %o " 69 | "(IF%o DF%o UF%o SF%o IB%o UB%o) state %d\n", 70 | top->v__DOT__cpu__DOT__pc, 71 | top->v__DOT__mb, 72 | top->v__DOT__cpu__DOT__l, 73 | top->v__DOT__cpu__DOT__ac, 74 | top->v__DOT__cpu__DOT__interrupt_enable, 75 | top->v__DOT__cpu__DOT__IF, 76 | top->v__DOT__cpu__DOT__DF, 77 | top->v__DOT__cpu__DOT__UF, 78 | top->v__DOT__cpu__DOT__SF, 79 | top->v__DOT__cpu__DOT__IB, 80 | top->v__DOT__cpu__DOT__UB, 81 | top->v__DOT__state); 82 | } 83 | 84 | #ifdef VM_TRACE 85 | //#define MIN_TIME 0 86 | //#define MAX_TIME 100000 87 | 88 | #define MIN_TIME 5196000 89 | #define MAX_TIME 5313000 90 | 91 | 92 | if (tfp) { 93 | if (main_time > MIN_TIME) 94 | tfp->dump(main_time); 95 | 96 | if (main_time > MAX_TIME) 97 | vl_finish("test.cpp",__LINE__,""); 98 | } 99 | #endif 100 | 101 | main_time += 10; 102 | } 103 | 104 | top->final(); 105 | 106 | if (tfp) 107 | tfp->close(); 108 | } 109 | -------------------------------------------------------------------------------- /xilinx/TODO.txt: -------------------------------------------------------------------------------- 1 | 2 | pdp-8 3 | register file 4 | 5 | caddr 6 | ddr controller 7 | video bitmap 8 | disk interface 9 | 10 | xc2s200-5fg256 11 | -------------------------------------------------------------------------------- /xilinx/pdp8/.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /xilinx/pdp8/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | C:\brad\pdp8\xilinx\pdp8\top.ngc 1272077251 2 | OK 3 | -------------------------------------------------------------------------------- /xilinx/pdp8/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Gated clock. Clock net ram_rd is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 9 | 10 | 11 | The signal <slideswitch<4>_IBUF> is incomplete. The signal does not drive any load pins in the design. 12 | 13 | 14 | The signal <slideswitch<5>_IBUF> is incomplete. The signal does not drive any load pins in the design. 15 | 16 | 17 | The signal <slideswitch<6>_IBUF> is incomplete. The signal does not drive any load pins in the design. 18 | 19 | 20 | The signal <slideswitch<7>_IBUF> is incomplete. The signal does not drive any load pins in the design. 21 | 22 | 23 | The signal <button<0>_IBUF> is incomplete. The signal does not drive any load pins in the design. 24 | 25 | 26 | The signal <button<1>_IBUF> is incomplete. The signal does not drive any load pins in the design. 27 | 28 | 29 | The signal <button<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /xilinx/pdp8/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /xilinx/pdp8/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No timing constraints found, doing default enumeration. 9 | 10 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 11 | 12 | 13 | -------------------------------------------------------------------------------- /xilinx/pdp8/pdp8.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/pdp8.ise -------------------------------------------------------------------------------- /xilinx/pdp8/pdp8.ise_ISE_Backup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/pdp8.ise_ISE_Backup -------------------------------------------------------------------------------- /xilinx/pdp8/pdp8.ntrc_log: -------------------------------------------------------------------------------- 1 | -------------------- 2 | Xst NTRC: "/top" : OUT_OF_DATE 3 | -------------------- 4 | Map NTRC: "/top" : OUT_OF_DATE 5 | -------------------- 6 | Xst NTRC: "/top" : OUT_OF_DATE 7 | -------------------- 8 | Map NTRC: "/top" : OUT_OF_DATE 9 | -------------------- 10 | Xst NTRC: "/top" : OUT_OF_DATE 11 | -------------------- 12 | Xst NTRC: "/top" : OUT_OF_DATE 13 | -------------------- 14 | Xst NTRC: "/top" : OUT_OF_DATE 15 | -------------------- 16 | Map NTRC: "/top" : OUT_OF_DATE 17 | -------------------- 18 | Xst NTRC: "/top" : OUT_OF_DATE 19 | -------------------- 20 | Map NTRC: "/top" : OUT_OF_DATE 21 | -------------------- 22 | Xst NTRC: "/top" : OUT_OF_DATE 23 | -------------------- 24 | Map NTRC: "/top" : OUT_OF_DATE 25 | -------------------- 26 | Xst NTRC: "/top" : OUT_OF_DATE 27 | -------------------- 28 | Map NTRC: "/top" : OUT_OF_DATE 29 | -------------------- 30 | Xst NTRC: "/top" : OUT_OF_DATE 31 | -------------------- 32 | Map NTRC: "/top" : OUT_OF_DATE 33 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/top.bit -------------------------------------------------------------------------------- /xilinx/pdp8/top.bld: -------------------------------------------------------------------------------- 1 | Release 8.2.03i ngdbuild I.34 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise 5 | C:/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise -dd _ngo -nt timestamp -uc 6 | C:/brad/pdp8/synth/s3board.ucf -p xc3s1000-ft256-5 top.ngc top.ngd 7 | 8 | Reading NGO file 'C:/brad/pdp8/xilinx/pdp8/top.ngc' ... 9 | 10 | Applying constraints in "C:/brad/pdp8/synth/s3board.ucf" to the design... 11 | 12 | Checking timing specifications ... 13 | Checking Partitions ... 14 | Checking expanded design ... 15 | 16 | Partition Implementation Status 17 | ------------------------------- 18 | 19 | No Partitions were found in this design. 20 | 21 | ------------------------------- 22 | 23 | NGDBUILD Design Results Summary: 24 | Number of errors: 0 25 | Number of warnings: 0 26 | 27 | Total memory usage is 73504 kilobytes 28 | 29 | Writing NGD file "top.ngd" ... 30 | 31 | Writing NGDBUILD log file "top.bld"... 32 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.drc: -------------------------------------------------------------------------------- 1 | WARNING:PhysDesignRules:372 - Gated clock. Clock net ram_rd is sourced by a 2 | combinatorial pin. This is not good design practice. Use the CE pin to 3 | control the loading of data into the flip-flop. 4 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. 5 | The signal does not drive any load pins in the design. 6 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. 7 | The signal does not drive any load pins in the design. 8 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. 9 | The signal does not drive any load pins in the design. 10 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. 11 | The signal does not drive any load pins in the design. 12 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The 13 | signal does not drive any load pins in the design. 14 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The 15 | signal does not drive any load pins in the design. 16 | WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The 17 | signal does not drive any load pins in the design. 18 | DRC detected 0 errors and 8 warnings. 19 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.prj: -------------------------------------------------------------------------------- 1 | verilog work "../../rtl/ide.v" 2 | verilog work "../../rtl/uart.v" 3 | verilog work "../../rtl/ram_256x12.v" 4 | verilog work "../../rtl/ide_disk.v" 5 | verilog work "../../rtl/brg.v" 6 | verilog work "../../rtl/sevensegdecode.v" 7 | verilog work "../../rtl/pdp8_tt.v" 8 | verilog work "../../rtl/pdp8_rf.v" 9 | verilog work "../../rtl/pdp8_kw.v" 10 | verilog work "../../rtl/bootrom.v" 11 | verilog work "../../rtl/pdp8_ram.v" 12 | verilog work "../../rtl/pdp8_io.v" 13 | verilog work "../../rtl/pdp8.v" 14 | verilog work "../../rtl/display.v" 15 | verilog work "../../rtl/debounce.v" 16 | verilog work "../../rtl/top.v" 17 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/top.stx -------------------------------------------------------------------------------- /xilinx/pdp8/top.twr: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | Release 8.2.03i Trace 3 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 4 | 5 | C:\Xilinx\bin\nt\trce.exe -ise C:/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise 6 | -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf 7 | C:/brad/pdp8/synth/s3board.ucf 8 | 9 | Design file: top.ncd 10 | Physical constraint file: top.pcf 11 | Device,speed: xc3s1000,-5 (PRODUCTION 1.39 2006-08-18) 12 | Report level: error report 13 | 14 | Environment Variable Effect 15 | -------------------- ------ 16 | NONE No environment variables were set 17 | -------------------------------------------------------------------------------- 18 | 19 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. 20 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 21 | option. All paths that are not constrained will be reported in the 22 | unconstrained paths section(s) of the report. 23 | 24 | 25 | 26 | Data Sheet report: 27 | ----------------- 28 | All values displayed in nanoseconds (ns) 29 | 30 | Setup/Hold to clock sysclk 31 | --------------+------------+------------+------------------+--------+ 32 | | Setup to | Hold to | | Clock | 33 | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | 34 | --------------+------------+------------+------------------+--------+ 35 | slideswitch<2>| 4.986(R)| -1.884(R)|sysclk_BUFGP | 0.000| 36 | slideswitch<3>| 5.549(R)| -2.335(R)|sysclk_BUFGP | 0.000| 37 | --------------+------------+------------+------------------+--------+ 38 | 39 | Clock to Setup on destination clock sysclk 40 | ---------------+---------+---------+---------+---------+ 41 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 42 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 43 | ---------------+---------+---------+---------+---------+ 44 | sysclk | 4.720| | | | 45 | ---------------+---------+---------+---------+---------+ 46 | 47 | 48 | Analysis completed Fri Apr 23 22:48:33 2010 49 | -------------------------------------------------------------------------------- 50 | 51 | Trace Settings: 52 | ------------------------- 53 | Trace Settings 54 | 55 | Peak Memory Usage: 144 MB 56 | 57 | 58 | 59 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.unroutes: -------------------------------------------------------------------------------- 1 | Release 8.2.03i - par I.34 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Apr 23 22:48:26 2010 5 | 6 | There are 0 unrouted networks: 7 | 8 | 9 | There are 7 sourceless or loadless networks: 10 | 11 | button<0>_IBUF 12 | button<1>_IBUF 13 | button<2>_IBUF 14 | slideswitch<4>_IBUF 15 | slideswitch<5>_IBUF 16 | slideswitch<6>_IBUF 17 | slideswitch<7>_IBUF 18 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g ConfigRate:6 6 | -g CclkPin:PullUp 7 | -g M0Pin:PullUp 8 | -g M1Pin:PullUp 9 | -g M2Pin:PullUp 10 | -g ProgPin:PullUp 11 | -g DonePin:PullUp 12 | -g TckPin:PullUp 13 | -g TdiPin:PullUp 14 | -g TdoPin:PullUp 15 | -g TmsPin:PullUp 16 | -g UnusedPin:PullDown 17 | -g UserID:0xFFFFFFFF 18 | -g DCMShutdown:Disable 19 | -g DCIUpdateMode:AsRequired 20 | -g StartUpClk:CClk 21 | -g DONE_cycle:4 22 | -g GTS_cycle:5 23 | -g GWE_cycle:6 24 | -g LCK_cycle:NoWait 25 | -g Match_cycle:Auto 26 | -g Security:None 27 | -g DonePipe:No 28 | -g DriveDone:No 29 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /xilinx/pdp8/top.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "./xst/projnav.tmp" 2 | set -xsthdpdir "./xst" 3 | run 4 | -ifn top.prj 5 | -ifmt mixed 6 | -ofn top 7 | -ofmt NGC 8 | -p xc3s1000-5-ft256 9 | -top top 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -lso top.lso 14 | -keep_hierarchy NO 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case maintain 23 | -slice_utilization_ratio 100 24 | -verilog2001 YES 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style lut 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -mux_style Auto 32 | -decoder_extract YES 33 | -priority_extract YES 34 | -shreg_extract YES 35 | -shift_extract YES 36 | -xor_collapse YES 37 | -rom_style Auto 38 | -mux_extract YES 39 | -resource_sharing YES 40 | -mult_style auto 41 | -iobuf YES 42 | -max_fanout 500 43 | -bufg 8 44 | -register_duplication YES 45 | -register_balancing No 46 | -slice_packing YES 47 | -optimize_primitives NO 48 | -use_clock_enable Yes 49 | -use_sync_set Yes 50 | -use_sync_reset Yes 51 | -iob auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /xilinx/pdp8/top_vhdl.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/top_vhdl.prj -------------------------------------------------------------------------------- /xilinx/pdp8/xst/dump.xst/top.prj/ntrc.scr: -------------------------------------------------------------------------------- 1 | set -xsthdpdir ./xst\ 2 | set -checkcmdline no 3 | run -ifn top.prj -ifmt mixed -ofn top -ofmt NGC -p xc3s1000-5-ft256 -top top -opt_mode Speed -opt_level 1 -iuc NO -lso top.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 -crit Speed -power 1 -mapstyle lut -fsm_encoding Auto -t XILINX -addsub_extract yes 4 | -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO ide_disk NULL ../../rtl/ide_disk.v vlg10/ide__disk.bin 1272077203 2 | MO bootrom NULL ../../rtl/bootrom.v vlg4A/bootrom.bin 1272077203 3 | MO display NULL ../../rtl/display.v vlg1E/display.bin 1272077203 4 | MO pdp8_io NULL ../../rtl/pdp8_io.v vlg2F/pdp8__io.bin 1272077203 5 | MO brg NULL ../../rtl/brg.v vlg33/brg.bin 1272077203 6 | MO pdp8_kw NULL ../../rtl/pdp8_kw.v vlg41/pdp8__kw.bin 1272077203 7 | MO pdp8_rf NULL ../../rtl/pdp8_rf.v vlg53/pdp8__rf.bin 1272077203 8 | MO pdp8_tt NULL ../../rtl/pdp8_tt.v vlg6B/pdp8__tt.bin 1272077203 9 | MO debounce NULL ../../rtl/debounce.v vlg1D/debounce.bin 1272077203 10 | MO top NULL ../../rtl/top.v vlg6F/top.bin 1272077203 11 | MO ram_256x12 NULL ../../rtl/ram_256x12.v vlg37/ram__256x12.bin 1272077203 12 | MO pdp8 NULL ../../rtl/pdp8.v vlg5C/pdp8.bin 1272077203 13 | MO ide NULL ../../rtl/ide.v vlg1A/ide.bin 1272077203 14 | MO sevensegdecode NULL ../../rtl/sevensegdecode.v vlg28/sevensegdecode.bin 1272077203 15 | MO pdp8_ram NULL ../../rtl/pdp8_ram.v vlg73/pdp8__ram.bin 1272077203 16 | MO uart NULL ../../rtl/uart.v vlg48/uart.bin 1272077203 17 | -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg10/ide__disk.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg10/ide__disk.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg1A/ide.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg1A/ide.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg1D/debounce.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg1D/debounce.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg2F/pdp8__io.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg2F/pdp8__io.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg33/brg.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg33/brg.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg37/ram__256x12.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg37/ram__256x12.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg41/pdp8__kw.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg41/pdp8__kw.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg48/uart.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg48/uart.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg53/pdp8__rf.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg53/pdp8__rf.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg5C/pdp8.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg5C/pdp8.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg6B/pdp8__tt.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg6B/pdp8__tt.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg6F/top.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg6F/top.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin -------------------------------------------------------------------------------- /xilinx/pdp8/xst/work/vlg7A/ram__32kx12.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/pdp8/xst/work/vlg7A/ram__32kx12.bin -------------------------------------------------------------------------------- /xilinx/ps2/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | /mwave/work/nt/xess/xilinx/ps2/fpga.ngc 1166710707 2 | OK 3 | -------------------------------------------------------------------------------- /xilinx/ps2/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /xilinx/ps2/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Logical network clkb has no load. 9 | 10 | 11 | The above warning message base_net_load_rule is repeated 11 more times for the following (max. 5 shown): 12 | vga_hsync_n, 13 | vga_red0, 14 | vga_red1, 15 | vga_red2, 16 | vga_green0 17 | To see the details of these warning messages, please use the -detail switch. 18 | 19 | 20 | No environment variables are currently set. 21 | 22 | 23 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. 24 | 25 | 26 | Clock buffer is designated to drive clock loads. BUFG symbol "gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and non-clock loads. The non-clock loads are: 27 | Pin D of gray_cnt_FFd2 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /xilinx/ps2/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /xilinx/ps2/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". 9 | 10 | 11 | N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. 12 | 13 | 14 | -------------------------------------------------------------------------------- /xilinx/ps2/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No timing constraints found, doing default enumeration. 9 | 10 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 11 | 12 | 13 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/fpga.bit -------------------------------------------------------------------------------- /xilinx/ps2/fpga.bld: -------------------------------------------------------------------------------- 1 | Release 8.2i ngdbuild I.31 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: ngdbuild -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise 5 | -dd _ngo -nt timestamp -uc /mwave/work/nt/xess/v/fpga2.ucf -p xc2s200-fg256-5 6 | fpga.ngc fpga.ngd 7 | 8 | Reading NGO file '/mwave/work/nt/xess/xilinx/ps2/fpga.ngc' ... 9 | 10 | Applying constraints in "/mwave/work/nt/xess/v/fpga2.ucf" to the design... 11 | 12 | Checking timing specifications ... 13 | Checking Partitions ... 14 | Checking expanded design ... 15 | 16 | Partition Implementation Status 17 | ------------------------------- 18 | 19 | No Partitions were found in this design. 20 | 21 | ------------------------------- 22 | 23 | NGDBUILD Design Results Summary: 24 | Number of errors: 0 25 | Number of warnings: 0 26 | 27 | Total memory usage is 239836 kilobytes 28 | 29 | Writing NGD file "fpga.ngd" ... 30 | 31 | Writing NGDBUILD log file "fpga.bld"... 32 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.drc: -------------------------------------------------------------------------------- 1 | DRC detected 0 errors and 0 warnings. 2 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map I.31 on Thu Dec 21 09:18:43 2006 3 | //! ************************************************************************** 4 | 5 | SCHEMATIC START; 6 | COMP "reset_n" LOCATE = SITE "E3" LEVEL 1; 7 | COMP "clka" LOCATE = SITE "R8" LEVEL 1; 8 | COMP "fpga_d1" LOCATE = SITE "E16" LEVEL 1; 9 | COMP "fpga_din_d0" LOCATE = SITE "D14" LEVEL 1; 10 | COMP "fpga_d2" LOCATE = SITE "F15" LEVEL 1; 11 | COMP "fpga_d3" LOCATE = SITE "G16" LEVEL 1; 12 | COMP "fpga_d4" LOCATE = SITE "J16" LEVEL 1; 13 | COMP "fpga_d5" LOCATE = SITE "M16" LEVEL 1; 14 | COMP "fpga_d6" LOCATE = SITE "N16" LEVEL 1; 15 | COMP "fpga_d7" LOCATE = SITE "N14" LEVEL 1; 16 | COMP "ps2_data" LOCATE = SITE "E1" LEVEL 1; 17 | COMP "ps2_clk" LOCATE = SITE "F4" LEVEL 1; 18 | SCHEMATIC END; 19 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.prj: -------------------------------------------------------------------------------- 1 | verilog work "../../v/ps2.v" 2 | verilog work "../../v/fpga2.v" 3 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/fpga.stx -------------------------------------------------------------------------------- /xilinx/ps2/fpga.twr: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | Release 8.2i Trace 3 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 4 | 5 | trce -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise -e 3 -l 3 -s 5 6 | -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf 7 | 8 | Design file: fpga.ncd 9 | Physical constraint file: fpga.pcf 10 | Device,speed: xc2s200,-5 (PRODUCTION 1.27 2006-05-03) 11 | Report level: error report 12 | 13 | Environment Variable Effect 14 | -------------------- ------ 15 | NONE No environment variables were set 16 | -------------------------------------------------------------------------------- 17 | 18 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. 19 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 20 | option. All paths that are not constrained will be reported in the 21 | unconstrained paths section(s) of the report. 22 | 23 | 24 | 25 | Data Sheet report: 26 | ----------------- 27 | All values displayed in nanoseconds (ns) 28 | 29 | Clock to Setup on destination clock clka 30 | ---------------+---------+---------+---------+---------+ 31 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 32 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 33 | ---------------+---------+---------+---------+---------+ 34 | clka | 6.308| | | | 35 | ---------------+---------+---------+---------+---------+ 36 | 37 | 38 | Analysis completed Thu Dec 21 09:18:57 2006 39 | -------------------------------------------------------------------------------- 40 | 41 | Trace Settings: 42 | ------------------------- 43 | Trace Settings 44 | 45 | Peak Memory Usage: 194 MB 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.unroutes: -------------------------------------------------------------------------------- 1 | Release 8.2i - par I.31 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Dec 21 09:18:52 2006 5 | 6 | There are 0 unrouted networks: 7 | 8 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Gclkdel0:11111 5 | -g Gclkdel1:11111 6 | -g Gclkdel2:11111 7 | -g Gclkdel3:11111 8 | -g ConfigRate:4 9 | -g CclkPin:PullUp 10 | -g M0Pin:PullUp 11 | -g M1Pin:PullUp 12 | -g M2Pin:PullUp 13 | -g ProgPin:PullUp 14 | -g DonePin:PullUp 15 | -g TckPin:PullUp 16 | -g TdiPin:PullUp 17 | -g TdoPin:PullUp 18 | -g TmsPin:PullUp 19 | -g UnusedPin:PullDown 20 | -g UserID:0xFFFFFFFF 21 | -g StartUpClk:CClk 22 | -g DONE_cycle:4 23 | -g GTS_cycle:5 24 | -g GSR_cycle:6 25 | -g GWE_cycle:6 26 | -g LCK_cycle:NoWait 27 | -g Security:None 28 | -g DonePipe:No 29 | -g DriveDone:No 30 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "./xst/projnav.tmp" 2 | set -xsthdpdir "./xst" 3 | run 4 | -ifn fpga.prj 5 | -ifmt mixed 6 | -ofn fpga 7 | -ofmt NGC 8 | -p xc2s200-5-fg256 9 | -top fpga 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -lso fpga.lso 14 | -keep_hierarchy NO 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case maintain 23 | -slice_utilization_ratio 100 24 | -verilog2001 YES 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style lut 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -mux_style Auto 32 | -decoder_extract YES 33 | -priority_extract YES 34 | -shreg_extract YES 35 | -shift_extract YES 36 | -xor_collapse YES 37 | -rom_style Auto 38 | -mux_extract YES 39 | -resource_sharing YES 40 | -mult_style lut 41 | -iobuf YES 42 | -max_fanout 100 43 | -bufg 4 44 | -register_duplication YES 45 | -register_balancing No 46 | -slice_packing YES 47 | -optimize_primitives NO 48 | -tristate2logic Yes 49 | -use_clock_enable Yes 50 | -use_sync_set Yes 51 | -use_sync_reset Yes 52 | -iob auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -------------------------------------------------------------------------------- /xilinx/ps2/fpga_vhdl.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/fpga_vhdl.prj -------------------------------------------------------------------------------- /xilinx/ps2/ps2.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/ps2.ise -------------------------------------------------------------------------------- /xilinx/ps2/ps2.ise_ISE_Backup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/ps2.ise_ISE_Backup -------------------------------------------------------------------------------- /xilinx/ps2/ps2.ntrc_log: -------------------------------------------------------------------------------- 1 | -------------------- 2 | -------------------- 3 | -------------------- 4 | -------------------- 5 | -------------------- 6 | -------------------- 7 | -------------------- 8 | -------------------- 9 | -------------------- 10 | -------------------- 11 | -------------------- 12 | -------------------- 13 | -------------------- 14 | -------------------- 15 | -------------------- 16 | -------------------- 17 | -------------------- 18 | -------------------- 19 | -------------------- 20 | -------------------------------------------------------------------------------- /xilinx/ps2/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO fpga NULL ../../v/fpga2.v vlg22/fpga.bin 1166710699 2 | MO ps2 NULL ../../v/ps2.v vlg61/ps2.bin 1166710699 3 | -------------------------------------------------------------------------------- /xilinx/ps2/xst/work/vlg22/fpga.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/xst/work/vlg22/fpga.bin -------------------------------------------------------------------------------- /xilinx/ps2/xst/work/vlg61/ps2.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/ps2/xst/work/vlg61/ps2.bin -------------------------------------------------------------------------------- /xilinx/scancode/fpga.cmd_log: -------------------------------------------------------------------------------- 1 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 2 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 3 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 4 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 5 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 6 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 7 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 8 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 9 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 10 | xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 11 | -------------------------------------------------------------------------------- /xilinx/scancode/fpga.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /xilinx/scancode/fpga.prj: -------------------------------------------------------------------------------- 1 | verilog work "../../v/scancode.v" 2 | verilog work "../../v/fpga3.v" 3 | -------------------------------------------------------------------------------- /xilinx/scancode/fpga.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/fpga.stx -------------------------------------------------------------------------------- /xilinx/scancode/fpga.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "./xst/projnav.tmp" 2 | set -xsthdpdir "./xst" 3 | run 4 | -ifn fpga.prj 5 | -ifmt mixed 6 | -ofn fpga 7 | -ofmt NGC 8 | -p xc2s200-5-fg256 9 | -top fpga 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -lso fpga.lso 14 | -keep_hierarchy NO 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case maintain 23 | -slice_utilization_ratio 100 24 | -verilog2001 YES 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style lut 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -mux_style Auto 32 | -decoder_extract YES 33 | -priority_extract YES 34 | -shreg_extract YES 35 | -shift_extract YES 36 | -xor_collapse YES 37 | -rom_style Auto 38 | -mux_extract YES 39 | -resource_sharing YES 40 | -mult_style lut 41 | -iobuf YES 42 | -max_fanout 100 43 | -bufg 4 44 | -register_duplication YES 45 | -register_balancing No 46 | -slice_packing YES 47 | -optimize_primitives NO 48 | -tristate2logic Yes 49 | -use_clock_enable Yes 50 | -use_sync_set Yes 51 | -use_sync_reset Yes 52 | -iob auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -------------------------------------------------------------------------------- /xilinx/scancode/fpga_vhdl.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/fpga_vhdl.prj -------------------------------------------------------------------------------- /xilinx/scancode/scancode.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/scancode.ise -------------------------------------------------------------------------------- /xilinx/scancode/scancode.ise_ISE_Backup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/scancode.ise_ISE_Backup -------------------------------------------------------------------------------- /xilinx/scancode/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167237688 2 | MO scancode_convert NULL ../../v/scancode.v vlg3C/scancode__convert.bin 1167237688 3 | MO fpga NULL ../../v/fpga3.v vlg22/fpga.bin 1167237688 4 | MO test NULL ../../v/scancode.v vlg34/test.bin 1167237381 5 | -------------------------------------------------------------------------------- /xilinx/scancode/xst/work/vlg22/fpga.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/xst/work/vlg22/fpga.bin -------------------------------------------------------------------------------- /xilinx/scancode/xst/work/vlg34/test.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/xst/work/vlg34/test.bin -------------------------------------------------------------------------------- /xilinx/scancode/xst/work/vlg39/scancode__rom.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/xst/work/vlg39/scancode__rom.bin -------------------------------------------------------------------------------- /xilinx/scancode/xst/work/vlg3C/scancode__convert.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode/xst/work/vlg3C/scancode__convert.bin -------------------------------------------------------------------------------- /xilinx/scancode2/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | "../../v/scancode2.v" line 63: Unsupported Event Control Statement. 9 | 10 | 11 | "../../v/scancode2.v" line 69: Unsupported Event Control Statement. 12 | 13 | 14 | "../../v/scancode2.v" line 75: Unsupported Event Control Statement. 15 | 16 | 17 | "../../v/scancode2.v" line 80: Unsupported Event Control Statement. 18 | 19 | 20 | "../../v/scancode2.v" line 87: Unsupported Event Control Statement. 21 | 22 | 23 | "../../v/scancode2.v" line 92: Unsupported Event Control Statement. 24 | 25 | 26 | "../../v/scancode2.v" line 93: Unsupported Event Control Statement. 27 | 28 | 29 | "../../v/scancode2.v" line 101: Unsupported Event Control Statement. 30 | 31 | 32 | "../../v/scancode2.v" line 109: Unsupported Event Control Statement. 33 | 34 | 35 | "../../v/scancode2.v" line 110: Unsupported Event Control Statement. 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /xilinx/scancode2/fpga.cmd_log: -------------------------------------------------------------------------------- 1 | xst -ise "/mwave/work/nt/xess/xilinx/scancode2/scancode2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr 2 | -------------------------------------------------------------------------------- /xilinx/scancode2/fpga.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /xilinx/scancode2/fpga.prj: -------------------------------------------------------------------------------- 1 | verilog work "../../v/scancode2.v" 2 | verilog work "../../v/fpga3.v" 3 | -------------------------------------------------------------------------------- /xilinx/scancode2/fpga.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "./xst/projnav.tmp" 2 | set -xsthdpdir "./xst" 3 | run 4 | -ifn fpga.prj 5 | -ifmt mixed 6 | -ofn fpga 7 | -ofmt NGC 8 | -p xc2s200-5-fg256 9 | -top fpga 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -lso fpga.lso 14 | -keep_hierarchy NO 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case maintain 23 | -slice_utilization_ratio 100 24 | -verilog2001 YES 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style lut 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -mux_style Auto 32 | -decoder_extract YES 33 | -priority_extract YES 34 | -shreg_extract YES 35 | -shift_extract YES 36 | -xor_collapse YES 37 | -rom_style Auto 38 | -mux_extract YES 39 | -resource_sharing YES 40 | -mult_style lut 41 | -iobuf YES 42 | -max_fanout 100 43 | -bufg 4 44 | -register_duplication YES 45 | -register_balancing No 46 | -slice_packing YES 47 | -optimize_primitives NO 48 | -tristate2logic Yes 49 | -use_clock_enable Yes 50 | -use_sync_set Yes 51 | -use_sync_reset Yes 52 | -iob auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -------------------------------------------------------------------------------- /xilinx/scancode2/fpga_summary.html: -------------------------------------------------------------------------------- 1 | Xilinx Design Summary 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 |
SCANCODE2 Project Status
Project File:scancode2.iseCurrent State:Synthesized
Module Name:fpga
  • Errors:
10 Errors
Target Device:xc2s200-5fg256
  • Warnings:
No Warnings
Product Version:ISE 8.2i
  • Updated:
Wed Dec 27 11:33:33 2006
31 |  
32 | 33 | 34 |
SCANCODE2 Partition Summary
No partition information was found.
35 | 36 | 37 |  
38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 |
Detailed Reports
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 27 11:33:31 200610 Errors00
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     
48 |  
49 | 50 | 51 | 52 |
Secondary Reports
Report NameStatusGenerated
Xplorer Report  
53 | -------------------------------------------------------------------------------- /xilinx/scancode2/fpga_vhdl.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/fpga_vhdl.prj -------------------------------------------------------------------------------- /xilinx/scancode2/scancode2.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/scancode2.ise -------------------------------------------------------------------------------- /xilinx/scancode2/scancode2.ise_ISE_Backup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/scancode2.ise_ISE_Backup -------------------------------------------------------------------------------- /xilinx/scancode2/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167237210 2 | MO scancode_convert NULL ../../v/scancode2.v vlg3C/scancode__convert.bin 1167237210 3 | MO fpga NULL ../../v/fpga3.v vlg22/fpga.bin 1167237210 4 | MO test NULL ../../v/scancode2.v vlg34/test.bin 1167237210 5 | -------------------------------------------------------------------------------- /xilinx/scancode2/xst/work/vlg22/fpga.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/xst/work/vlg22/fpga.bin -------------------------------------------------------------------------------- /xilinx/scancode2/xst/work/vlg34/test.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/xst/work/vlg34/test.bin -------------------------------------------------------------------------------- /xilinx/scancode2/xst/work/vlg39/scancode__rom.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/xst/work/vlg39/scancode__rom.bin -------------------------------------------------------------------------------- /xilinx/scancode2/xst/work/vlg3C/scancode__convert.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/scancode2/xst/work/vlg3C/scancode__convert.bin -------------------------------------------------------------------------------- /xilinx/vga/__ISE_repository_vga.ise_.lock: -------------------------------------------------------------------------------- 1 | /tmp/xil_D9256R__vga.ise__F5C01604-2C8A-0000-A0C7-4E973BCB9245 2 | /mwave/work/nt/xess/xilinx/vga/vga.ise 3 | Wed Dec 27 11:45:16 2006 4 |  -------------------------------------------------------------------------------- /xilinx/vga/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | /mwave/work/nt/xess/xilinx/vga/fpga.ngc 1167708110 2 | OK 3 | -------------------------------------------------------------------------------- /xilinx/vga/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Gated clock. Clock net vga/crt/_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /xilinx/vga/_xmsgs/netgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | The generated Verilog netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM simulation library for correct compilation and simulation. 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /xilinx/vga/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". 9 | 10 | 11 | N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. 12 | 13 | 14 | -------------------------------------------------------------------------------- /xilinx/vga/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No timing constraints found, doing default enumeration. 9 | 10 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 11 | 12 | 13 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/fpga.bit -------------------------------------------------------------------------------- /xilinx/vga/fpga.drc: -------------------------------------------------------------------------------- 1 | WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced 2 | by a combinatorial pin. This is not good design practice. Use the CE pin to 3 | control the loading of data into the flip-flop. 4 | DRC detected 0 errors and 1 warnings. 5 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map I.31 on Mon Jan 01 22:22:14 2007 3 | //! ************************************************************************** 4 | 5 | SCHEMATIC START; 6 | COMP "ps2_clk" LOCATE = SITE "F4" LEVEL 1; 7 | COMP "fpga_d1" LOCATE = SITE "E16" LEVEL 1; 8 | COMP "fpga_d2" LOCATE = SITE "F15" LEVEL 1; 9 | COMP "fpga_d3" LOCATE = SITE "G16" LEVEL 1; 10 | COMP "fpga_d4" LOCATE = SITE "J16" LEVEL 1; 11 | COMP "fpga_d5" LOCATE = SITE "M16" LEVEL 1; 12 | COMP "fpga_d6" LOCATE = SITE "N16" LEVEL 1; 13 | COMP "fpga_d7" LOCATE = SITE "N14" LEVEL 1; 14 | COMP "ps2_data" LOCATE = SITE "E1" LEVEL 1; 15 | COMP "fpga_din_d0" LOCATE = SITE "D14" LEVEL 1; 16 | COMP "vga_blue0" LOCATE = SITE "H4" LEVEL 1; 17 | COMP "vga_blue1" LOCATE = SITE "K3" LEVEL 1; 18 | COMP "vga_vsync_n" LOCATE = SITE "K1" LEVEL 1; 19 | COMP "vga_blue2" LOCATE = SITE "L5" LEVEL 1; 20 | COMP "vga_hsync_n" LOCATE = SITE "K4" LEVEL 1; 21 | COMP "clka" LOCATE = SITE "R8" LEVEL 1; 22 | COMP "vga_red0" LOCATE = SITE "J1" LEVEL 1; 23 | COMP "vga_red1" LOCATE = SITE "M1" LEVEL 1; 24 | COMP "vga_red2" LOCATE = SITE "T2" LEVEL 1; 25 | COMP "reset_n" LOCATE = SITE "E3" LEVEL 1; 26 | COMP "vga_green0" LOCATE = SITE "H2" LEVEL 1; 27 | COMP "vga_green1" LOCATE = SITE "K5" LEVEL 1; 28 | COMP "vga_green2" LOCATE = SITE "R1" LEVEL 1; 29 | SCHEMATIC END; 30 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.prj: -------------------------------------------------------------------------------- 1 | verilog work "../../v/vga.v" 2 | verilog work "../../v/fpga.v" 3 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/fpga.stx -------------------------------------------------------------------------------- /xilinx/vga/fpga.twr: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | Release 8.2i Trace 3 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 4 | 5 | trce -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise -e 3 -l 3 -s 5 6 | -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf 7 | 8 | Design file: fpga.ncd 9 | Physical constraint file: fpga.pcf 10 | Device,speed: xc2s200,-5 (PRODUCTION 1.27 2006-05-03) 11 | Report level: error report 12 | 13 | Environment Variable Effect 14 | -------------------- ------ 15 | NONE No environment variables were set 16 | -------------------------------------------------------------------------------- 17 | 18 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. 19 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 20 | option. All paths that are not constrained will be reported in the 21 | unconstrained paths section(s) of the report. 22 | 23 | 24 | 25 | Data Sheet report: 26 | ----------------- 27 | All values displayed in nanoseconds (ns) 28 | 29 | Clock to Setup on destination clock clka 30 | ---------------+---------+---------+---------+---------+ 31 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 32 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 33 | ---------------+---------+---------+---------+---------+ 34 | clka | 7.120| | | | 35 | ---------------+---------+---------+---------+---------+ 36 | 37 | 38 | Analysis completed Mon Jan 1 22:22:52 2007 39 | -------------------------------------------------------------------------------- 40 | 41 | Trace Settings: 42 | ------------------------- 43 | Trace Settings 44 | 45 | Peak Memory Usage: 203 MB 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.unroutes: -------------------------------------------------------------------------------- 1 | Release 8.2i - par I.31 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Mon Jan 1 22:22:44 2007 5 | 6 | There are 0 unrouted networks: 7 | 8 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Gclkdel0:11111 5 | -g Gclkdel1:11111 6 | -g Gclkdel2:11111 7 | -g Gclkdel3:11111 8 | -g ConfigRate:4 9 | -g CclkPin:PullUp 10 | -g M0Pin:PullUp 11 | -g M1Pin:PullUp 12 | -g M2Pin:PullUp 13 | -g ProgPin:PullUp 14 | -g DonePin:PullUp 15 | -g TckPin:PullUp 16 | -g TdiPin:PullUp 17 | -g TdoPin:PullUp 18 | -g TmsPin:PullUp 19 | -g UnusedPin:PullDown 20 | -g UserID:0xFFFFFFFF 21 | -g StartUpClk:CClk 22 | -g DONE_cycle:4 23 | -g GTS_cycle:5 24 | -g GSR_cycle:6 25 | -g GWE_cycle:6 26 | -g LCK_cycle:NoWait 27 | -g Security:None 28 | -g DonePipe:No 29 | -g DriveDone:No 30 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /xilinx/vga/fpga.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "./xst/projnav.tmp" 2 | set -xsthdpdir "./xst" 3 | run 4 | -ifn fpga.prj 5 | -ifmt mixed 6 | -ofn fpga 7 | -ofmt NGC 8 | -p xc2s200-5-fg256 9 | -top fpga 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -lso fpga.lso 14 | -keep_hierarchy NO 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case maintain 23 | -slice_utilization_ratio 100 24 | -verilog2001 YES 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style lut 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -mux_style Auto 32 | -decoder_extract YES 33 | -priority_extract YES 34 | -shreg_extract YES 35 | -shift_extract YES 36 | -xor_collapse YES 37 | -rom_style Auto 38 | -mux_extract YES 39 | -resource_sharing YES 40 | -mult_style lut 41 | -iobuf YES 42 | -max_fanout 100 43 | -bufg 4 44 | -register_duplication YES 45 | -register_balancing No 46 | -slice_packing YES 47 | -optimize_primitives NO 48 | -tristate2logic Yes 49 | -use_clock_enable Yes 50 | -use_sync_set Yes 51 | -use_sync_reset Yes 52 | -iob auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -------------------------------------------------------------------------------- /xilinx/vga/fpga_vhdl.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/fpga_vhdl.prj -------------------------------------------------------------------------------- /xilinx/vga/netgen/par/fpga_timesim.nlf: -------------------------------------------------------------------------------- 1 | Release 8.2i - netgen I.31 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: netgen -intstyle ise -s 5 -pcf fpga.pcf -sdf_anno true -sdf_path 5 | netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim fpga.ncd 6 | fpga_timesim.v 7 | 8 | Read and Annotate design 'fpga.ncd' ... 9 | Loading device for application Rf_Device from file 'v200.nph' in environment 10 | /opt/Xilinx. 11 | "fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5 12 | Loading constraints from 'fpga.pcf'... 13 | The speed grade (-5) differs from the speed grade specified in the .ncd file 14 | (-5). 15 | The number of routable networks is 686 16 | Flattening design ... 17 | Processing design ... 18 | Preping design's networks ... 19 | Preping design's macros ... 20 | Writing Verilog SDF file 'netgen/par/fpga_timesim.sdf' ... 21 | Writing Verilog netlist file 22 | '/mwave/work/nt/xess/xilinx/vga/netgen/par/fpga_timesim.v' ... 23 | INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM 24 | simulation primitives and has to be used with SIMPRIM simulation library for 25 | correct compilation and simulation. 26 | Number of warnings: 0 27 | Number of info messages: 1 28 | Total memory usage is 232020 kilobytes 29 | -------------------------------------------------------------------------------- /xilinx/vga/netgen/synthesis/fpga_synthesis.nlf: -------------------------------------------------------------------------------- 1 | Release 8.2i - netgen I.31 2 | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis 5 | -ofmt verilog -sim fpga.ngc fpga_synthesis.v 6 | 7 | Reading design 'fpga.ngc' ... 8 | Flattening design ... 9 | Processing design ... 10 | Preping design's networks ... 11 | Preping design's macros ... 12 | Writing Verilog netlist file 13 | '/mwave/work/nt/xess/xilinx/vga/netgen/synthesis/fpga_synthesis.v' ... 14 | INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM 15 | simulation primitives and has to be used with UNISIM simulation library for 16 | correct compilation and simulation. 17 | Number of warnings: 0 18 | Number of info messages: 1 19 | Total memory usage is 151704 kilobytes 20 | -------------------------------------------------------------------------------- /xilinx/vga/netgen/synthesis/go.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | B=/wide/opt/Xilinx/verilog/src/unisims 4 | C=/wide/opt/Xilinx/verilog/src/uni9000 5 | 6 | #cver 7 | iverilog $B/LUT*.v $B/VCC.v $B/GND.v $B/INV.* $B/IBUF.v $B/OBUF.v $B/MUXCY.v $B/FDCE.v $B/FDE.v $B/MUXF5.v $B/FDP.v $B/FDR.v $B/FDC.v $B/FD.v $B/RAMB4_S1_S1.v $B/MULT_AND.v $B/XORCY.v $B/FDC_1.v $B/BUFGP.v $B/BUFG.v $B/MUXF6.v fpga_synthesis.v 8 | 9 | 10 | -------------------------------------------------------------------------------- /xilinx/vga/vga.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/vga.ise -------------------------------------------------------------------------------- /xilinx/vga/vga.ise_ISE_Backup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/vga.ise_ISE_Backup -------------------------------------------------------------------------------- /xilinx/vga/vga.ntrc_log: -------------------------------------------------------------------------------- 1 | -------------------- 2 | -------------------- 3 | -------------------- 4 | -------------------- 5 | -------------------- 6 | -------------------- 7 | -------------------- 8 | -------------------- 9 | -------------------- 10 | -------------------- 11 | -------------------- 12 | -------------------- 13 | -------------------- 14 | -------------------- 15 | -------------------- 16 | -------------------- 17 | -------------------- 18 | -------------------- 19 | -------------------- 20 | -------------------- 21 | -------------------- 22 | -------------------- 23 | -------------------- 24 | -------------------- 25 | -------------------- 26 | -------------------- 27 | -------------------- 28 | -------------------- 29 | -------------------- 30 | -------------------- 31 | -------------------- 32 | -------------------- 33 | -------------------- 34 | -------------------- 35 | -------------------- 36 | -------------------- 37 | -------------------- 38 | -------------------- 39 | -------------------- 40 | -------------------- 41 | -------------------- 42 | -------------------- 43 | -------------------- 44 | -------------------- 45 | -------------------- 46 | -------------------- 47 | -------------------- 48 | -------------------- 49 | -------------------- 50 | -------------------- 51 | -------------------- 52 | -------------------- 53 | -------------------- 54 | -------------------- 55 | -------------------- 56 | -------------------- 57 | -------------------- 58 | -------------------- 59 | -------------------- 60 | -------------------- 61 | -------------------- 62 | -------------------- 63 | -------------------- 64 | -------------------- 65 | -------------------- 66 | -------------------- 67 | -------------------- 68 | -------------------- 69 | -------------------- 70 | -------------------- 71 | -------------------- 72 | -------------------- 73 | -------------------- 74 | -------------------- 75 | -------------------- 76 | -------------------- 77 | -------------------- 78 | -------------------- 79 | -------------------- 80 | -------------------- 81 | -------------------- 82 | -------------------- 83 | -------------------- 84 | -------------------------------------------------------------------------------- /xilinx/vga/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO video_ram NULL ../../v/video_ram.v vlg6E/video__ram.bin 1167708079 2 | MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167708079 3 | MO scancode_convert NULL ../../v/scancode.v vlg3C/scancode__convert.bin 1167708079 4 | MO crt NULL ../../v/crt.v vlg59/crt.bin 1167708079 5 | MO vga NULL ../../v/vga.v vlg6A/vga.bin 1167708079 6 | MO char_rom NULL ../../v/char_rom.v vlg13/char__rom.bin 1167708079 7 | MO fpga NULL ../../v/fpga.v vlg22/fpga.bin 1167708079 8 | MO ps2 NULL ../../v/ps2.v vlg61/ps2.bin 1167708079 9 | MO vgacore NULL ../../v/vgacore.v vlg17/vgacore.bin 1167708079 10 | -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg13/char__rom.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg13/char__rom.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg17/vgacore.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg17/vgacore.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg22/fpga.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg22/fpga.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg39/scancode__rom.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg39/scancode__rom.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg3C/scancode__convert.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg3C/scancode__convert.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg59/crt.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg59/crt.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg61/ps2.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg61/ps2.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg6A/vga.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg6A/vga.bin -------------------------------------------------------------------------------- /xilinx/vga/xst/work/vlg6E/video__ram.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lisper/cpus-pdp8/116cbe08db4c8b8e024a020d79eb5c80d307a993/xilinx/vga/xst/work/vlg6E/video__ram.bin --------------------------------------------------------------------------------