├── README.md
├── cr_ie_info.json
├── digital-design.qpf
├── digital-design.qsf
├── digital-design.sdc
├── doc
└── final_report.pdf
├── io.tcl
├── ip
└── pll
│ ├── ip_pll.ppf
│ ├── ip_pll.qip
│ └── ip_pll.v
├── spinalPro
├── .gitignore
├── README.md
├── build.sbt
├── data
│ ├── _weight.bin
│ ├── test_batch.bin
│ └── weight.bin
├── project
│ ├── .bloop
│ │ ├── bloop.settings.json
│ │ └── spinalpro-build.json
│ ├── build.properties
│ ├── metals.sbt
│ ├── plugins.sbt
│ ├── project
│ │ ├── .bloop
│ │ │ ├── bloop.settings.json
│ │ │ └── spinalpro-build-build.json
│ │ ├── metals.sbt
│ │ ├── project
│ │ │ ├── metals.sbt
│ │ │ ├── project
│ │ │ │ └── target
│ │ │ │ │ └── config-classes
│ │ │ │ │ ├── $82ffa1936be93273e966$.class
│ │ │ │ │ ├── $82ffa1936be93273e966.cache
│ │ │ │ │ └── $82ffa1936be93273e966.class
│ │ │ └── target
│ │ │ │ ├── config-classes
│ │ │ │ ├── $5cd71d3f32ea60a531a3$.class
│ │ │ │ ├── $5cd71d3f32ea60a531a3.cache
│ │ │ │ └── $5cd71d3f32ea60a531a3.class
│ │ │ │ ├── scala-2.12
│ │ │ │ └── sbt-1.0
│ │ │ │ │ └── update
│ │ │ │ │ └── update_cache_2.12
│ │ │ │ │ ├── inputs
│ │ │ │ │ └── output
│ │ │ │ └── streams
│ │ │ │ ├── _global
│ │ │ │ ├── _global
│ │ │ │ │ ├── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ │ └── out
│ │ │ │ │ └── csrLogger
│ │ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── csrConfiguration
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── csrProject
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── dependencyPositions
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── update_cache_2.12
│ │ │ │ │ │ ├── input_dsp
│ │ │ │ │ │ └── output_dsp
│ │ │ │ ├── ivyConfiguration
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── ivySbt
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── moduleSettings
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── projectDescriptors
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── scalaCompilerBridgeScope
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ └── update
│ │ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ │ ├── compile
│ │ │ │ ├── _global
│ │ │ │ │ └── _global
│ │ │ │ │ │ ├── compileBinaryFileInputs
│ │ │ │ │ │ └── previous
│ │ │ │ │ │ ├── compileOutputs
│ │ │ │ │ │ └── previous
│ │ │ │ │ │ ├── compileSourceFileInputs
│ │ │ │ │ │ └── previous
│ │ │ │ │ │ ├── dependencyClasspathFiles
│ │ │ │ │ │ └── previous
│ │ │ │ │ │ ├── discoveredMainClasses
│ │ │ │ │ │ └── data
│ │ │ │ │ │ └── managedSourcePaths
│ │ │ │ │ │ └── previous
│ │ │ │ ├── compile
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ ├── compileIncremental
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ ├── export
│ │ │ │ │ │ └── out
│ │ │ │ ├── copyResources
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ ├── copy-resources
│ │ │ │ │ │ └── out
│ │ │ │ ├── dependencyClasspath
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── export
│ │ │ │ ├── exportedProducts
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── export
│ │ │ │ ├── externalDependencyClasspath
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── export
│ │ │ │ ├── internalDependencyClasspath
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── export
│ │ │ │ ├── managedClasspath
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── export
│ │ │ │ ├── unmanagedClasspath
│ │ │ │ │ └── _global
│ │ │ │ │ │ └── streams
│ │ │ │ │ │ └── export
│ │ │ │ └── unmanagedJars
│ │ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ └── runtime
│ │ │ │ ├── dependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ ├── exportedProducts
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ ├── externalDependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ ├── fullClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ ├── internalDependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ ├── managedClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ ├── unmanagedClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ │ └── unmanagedJars
│ │ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ └── target
│ │ │ ├── config-classes
│ │ │ ├── $570d04bed24069049d03$.class
│ │ │ ├── $570d04bed24069049d03.cache
│ │ │ └── $570d04bed24069049d03.class
│ │ │ ├── scala-2.12
│ │ │ └── sbt-1.0
│ │ │ │ └── update
│ │ │ │ └── update_cache_2.12
│ │ │ │ ├── inputs
│ │ │ │ └── output
│ │ │ └── streams
│ │ │ ├── _global
│ │ │ ├── _global
│ │ │ │ ├── _global
│ │ │ │ │ └── streams
│ │ │ │ │ │ └── out
│ │ │ │ └── csrLogger
│ │ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── csrConfiguration
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── csrProject
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── dependencyPositions
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── update_cache_2.12
│ │ │ │ │ ├── input_dsp
│ │ │ │ │ └── output_dsp
│ │ │ ├── ivyConfiguration
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── ivySbt
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── moduleSettings
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── projectDescriptors
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── scalaCompilerBridgeScope
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── update
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ └── updateSbtClassifiers
│ │ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ │ ├── compile
│ │ │ ├── _global
│ │ │ │ └── _global
│ │ │ │ │ ├── compileBinaryFileInputs
│ │ │ │ │ └── previous
│ │ │ │ │ ├── compileOutputs
│ │ │ │ │ └── previous
│ │ │ │ │ ├── compileSourceFileInputs
│ │ │ │ │ └── previous
│ │ │ │ │ ├── dependencyClasspathFiles
│ │ │ │ │ └── previous
│ │ │ │ │ ├── discoveredMainClasses
│ │ │ │ │ └── data
│ │ │ │ │ └── managedSourcePaths
│ │ │ │ │ └── previous
│ │ │ ├── bloopGenerate
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── bloopPostGenerate
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── compile
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ ├── compileIncremental
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ ├── export
│ │ │ │ │ └── out
│ │ │ ├── copyResources
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ ├── copy-resources
│ │ │ │ │ └── out
│ │ │ ├── dependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── exportedProducts
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── externalDependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── internalDependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── managedClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── unmanagedClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ └── unmanagedJars
│ │ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ │ ├── it
│ │ │ ├── bloopGenerate
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ └── bloopPostGenerate
│ │ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ │ ├── runtime
│ │ │ ├── dependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── exportedProducts
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── externalDependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── fullClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── internalDependencyClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── managedClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ ├── unmanagedClasspath
│ │ │ │ └── _global
│ │ │ │ │ └── streams
│ │ │ │ │ └── export
│ │ │ └── unmanagedJars
│ │ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ │ └── test
│ │ │ ├── bloopGenerate
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ │ └── bloopPostGenerate
│ │ │ └── _global
│ │ │ └── streams
│ │ │ └── out
│ └── target
│ │ ├── config-classes
│ │ ├── $0ee2a55c087916402264$.class
│ │ ├── $0ee2a55c087916402264.cache
│ │ ├── $0ee2a55c087916402264.class
│ │ ├── $50405c8d0affe7b128dc$.class
│ │ ├── $50405c8d0affe7b128dc.cache
│ │ ├── $50405c8d0affe7b128dc.class
│ │ ├── $7f37f83adacf9ef48ec5$.class
│ │ ├── $7f37f83adacf9ef48ec5.cache
│ │ ├── $7f37f83adacf9ef48ec5.class
│ │ ├── $c2e2d1d3c1064f335bfc$.class
│ │ ├── $c2e2d1d3c1064f335bfc.cache
│ │ ├── $c2e2d1d3c1064f335bfc.class
│ │ ├── $daae7ff53c5a6928e407$.class
│ │ ├── $daae7ff53c5a6928e407.cache
│ │ ├── $daae7ff53c5a6928e407.class
│ │ ├── $fd293f8d5f8d48c3b567$.class
│ │ ├── $fd293f8d5f8d48c3b567.cache
│ │ └── $fd293f8d5f8d48c3b567.class
│ │ ├── scala-2.12
│ │ └── sbt-1.0
│ │ │ └── update
│ │ │ └── update_cache_2.12
│ │ │ ├── inputs
│ │ │ └── output
│ │ └── streams
│ │ ├── _global
│ │ ├── _global
│ │ │ ├── _global
│ │ │ │ └── streams
│ │ │ │ │ └── out
│ │ │ └── csrLogger
│ │ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── csrConfiguration
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── csrProject
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── dependencyPositions
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── update_cache_2.12
│ │ │ │ ├── input_dsp
│ │ │ │ └── output_dsp
│ │ ├── ivyConfiguration
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── ivySbt
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── moduleSettings
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── projectDescriptors
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── scalaCompilerBridgeScope
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── update
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ └── updateSbtClassifiers
│ │ │ └── _global
│ │ │ └── streams
│ │ │ └── out
│ │ ├── compile
│ │ ├── _global
│ │ │ └── _global
│ │ │ │ ├── compileBinaryFileInputs
│ │ │ │ └── previous
│ │ │ │ ├── compileOutputs
│ │ │ │ └── previous
│ │ │ │ ├── compileSourceFileInputs
│ │ │ │ └── previous
│ │ │ │ ├── dependencyClasspathFiles
│ │ │ │ └── previous
│ │ │ │ ├── discoveredMainClasses
│ │ │ │ └── data
│ │ │ │ └── managedSourcePaths
│ │ │ │ └── previous
│ │ ├── bloopGenerate
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── bloopPostGenerate
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── compile
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ ├── compileIncremental
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ ├── export
│ │ │ │ └── out
│ │ ├── copyResources
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ ├── copy-resources
│ │ │ │ └── out
│ │ ├── dependencyClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── exportedProducts
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── externalDependencyClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── internalDependencyClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── managedClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── unmanagedClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ └── unmanagedJars
│ │ │ └── _global
│ │ │ └── streams
│ │ │ └── export
│ │ ├── it
│ │ ├── bloopGenerate
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── out
│ │ └── bloopPostGenerate
│ │ │ └── _global
│ │ │ └── streams
│ │ │ └── out
│ │ ├── runtime
│ │ ├── dependencyClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── exportedProducts
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── externalDependencyClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── fullClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── internalDependencyClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── managedClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ ├── unmanagedClasspath
│ │ │ └── _global
│ │ │ │ └── streams
│ │ │ │ └── export
│ │ └── unmanagedJars
│ │ │ └── _global
│ │ │ └── streams
│ │ │ └── export
│ │ └── test
│ │ ├── bloopGenerate
│ │ └── _global
│ │ │ └── streams
│ │ │ └── out
│ │ └── bloopPostGenerate
│ │ └── _global
│ │ └── streams
│ │ └── out
├── src
│ └── main
│ │ └── scala
│ │ └── mylib
│ │ ├── AvgPoolBlock.scala
│ │ ├── AvgPoolLayer.scala
│ │ ├── ConvolutionBlock.scala
│ │ ├── ConvolutionLayer.scala
│ │ ├── FeatureMap.scala
│ │ ├── GlobalFunction.scala
│ │ ├── LayerCtrl.scala
│ │ ├── MyTopLevel.scala
│ │ ├── MyTopLevelSim.scala
│ │ ├── Net.scala
│ │ ├── Relu.scala
│ │ └── WeightMem.scala
├── task.md
└── verilog
│ ├── ClassificationNet.v
│ ├── ClassificationNet.v_toplevel_avgPoolBlock_1_core_fmRAM.bin
│ ├── ClassificationNet.v_toplevel_convolutionBlock_2_core_fmRAM.bin
│ ├── ClassificationNet.v_toplevel_convolutionBlock_2_core_layer_rom_ROM.bin
│ ├── ClassificationNet.v_toplevel_convolutionBlock_3_core_fmRAM.bin
│ └── ClassificationNet.v_toplevel_convolutionBlock_3_core_layer_rom_ROM.bin
├── src
├── ClassificationNet.sv
├── ClassificationNet.v_toplevel_avgPoolBlock_1_core_fmRAM.bin
├── ClassificationNet.v_toplevel_convolutionBlock_2_core_fmRAM.bin
├── ClassificationNet.v_toplevel_convolutionBlock_2_core_layer_rom_ROM.bin
├── ClassificationNet.v_toplevel_convolutionBlock_3_core_fmRAM.bin
├── ClassificationNet.v_toplevel_convolutionBlock_3_core_layer_rom_ROM.bin
├── dir_parser.sv
├── dpy_scan.v
├── mod_top.sv
├── ram30728.sv
├── ram_for_layer.sv
├── sd_file_reader.sv
├── sd_spi_sector_reader.sv
├── spi_session.sv
└── vga.v
├── tools
└── cifar10_net.ipynb
└── 最终答辩.pptx
/README.md:
--------------------------------------------------------------------------------
1 | # 仓库介绍
2 |
3 | 本仓库是数字逻辑设计2021基于FPGA的CNN图像分类系统代码仓库。
4 |
5 | 以下是仓库内容简介。
6 |
7 | - `/`根目录是Quartus工程项目
8 |
9 | - `/src/`下为源代码文件。**注意**:由于路径的原因,再次打开Quartus工程时可能需要**重新添加源文件**,直接添加该目录下的文件即可。
10 |
11 | - `/ip/`下为ip模块的目录。
12 |
13 | - `/doc/`下为实验报告。
14 |
15 | - `/tools/`下为训练神经网络及生成其权重的代码文件。
16 |
17 | `cifar10_net.ipynb`为训练神经网络的代码文件。
18 |
19 | 在代码中,顺序执行定义神经网络并且进行训练。训练完后执行最后一个block`Output Binary Files`的代码生成二进制格式的权重文件。
20 |
21 | **注意**:运行代码需要确保安装
22 |
23 | - python 3.8.8
24 | - jupyter 1.0.0
25 | - torch 1.8.1
26 | - torchsummary 1.5.1
27 | - torchvision 0.9.1
28 | - matplotlib 3.4.2
29 |
30 | - `/spinalPro/`下为SpinalHDL代码仓库。
31 |
32 | - `/spinalPro/data/`下为以二进制格式存储的权重和用于仿真的数据集文件。
33 | - `/spinalPro/project/`下为SpinalHDL工程文件。
34 | - `/spinalPro/src/`下为SpinalHDL的源代码文件,包含仿真文件。**注意**:Spinal的仿真需要Verilator的支持,详情见https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Getting%20Started/index.html。
35 | - `/spinalPro/verilog/`下为SpinalHDL生成的Verilog文件。
36 |
37 | - `/README.md`为本文件。
38 |
39 |
--------------------------------------------------------------------------------
/cr_ie_info.json:
--------------------------------------------------------------------------------
1 | {
2 | "system" : {
3 | "platform" : "windows64",
4 | "os_name" : "Windows 7",
5 | "os_version" : "6.2"
6 | },
7 | "error" : {
8 | "executable" : "quartus_map",
9 | "comment" : "none",
10 | "error_message" : "Access Violation at 0X00007FF97F572570",
11 | "source_file" : "unknown",
12 | "line" : "0",
13 | "stack_trace" : "\t0x7ff97f57256f: synth_vrfx + 0x13256f (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0x867bf)\n\t0x7ff97f5731b9: synth_vrfx + 0x1331b9 (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0x87409)\n\t0x7ff97f5cbfce: synth_vrfx + 0x18bfce (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xe021e)\n\t0x7ff97f5cc16b: synth_vrfx + 0x18c16b (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xe03bb)\n\t0x7ff97f5cbaa2: synth_vrfx + 0x18baa2 (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xdfcf2)\n\t0x7ff97f5cc16b: synth_vrfx + 0x18c16b (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xe03bb)\n\t0x7ff97f5caedd: synth_vrfx + 0x18aedd (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xdf12d)\n\t0x7ff97f5cc16b: synth_vrfx + 0x18c16b (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xe03bb)\n\t0x7ff97f5cbaa2: synth_vrfx + 0x18baa2 (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xdfcf2)\n\t0x7ff97f5cc16b: synth_vrfx + 0x18c16b (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xe03bb)\n\t0x7ff97f5cb15b: synth_vrfx + 0x18b15b (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xdf3ab)\n\t0x7ff97f5cc16b: synth_vrfx + 0x18c16b (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xe03bb)\n\t0x7ff97f5c5d48: synth_vrfx + 0x185d48 (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0xd9f98)\n\t0x7ff97f52c856: synth_vrfx + 0xec856 (?vrfx_add_to_extractor_migration_report@@YAXW4VRFX_EXTRACTOR_MIGRATION_ENUM@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@@Z + 0x40aa6)\n\t0x7ff97f4a7396: synth_vrfx + 0x67396 (??1VRFX_ELABORATOR@@UEAA@XZ + 0xce26)\n\t0x7ff98f7550a5: synth_sgn + 0x950a5 (?sgn_source_file_processing@@YA?AW4SGN_STATE_ENUM@@PEAVCMP_FACADE@@@Z + 0x80f25)\n\t0x7ff98f6d365c: synth_sgn + 0x1365c (?sgn_qic_full@@YA?AW4SGN_STATE_ENUM@@PEAVCMP_FACADE@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@V?$MEM_STL_ALLOCATOR@V?$basic_string@DU?$char_traits@D@std@@V?$MEM_STL_ALLOCATOR@D@@@std@@@@@std@@AEAV?$vector@NV?$MEM_STL_ALLOCATOR@N@@@4@@Z + 0x15c)\n\t0x7ff73e96489f: quartus_map + 0x489f\n\t0x7ff73e975356: quartus_map + 0x15356\n\t0x7ff73e974dea: quartus_map + 0x14dea\n\t0x7ff9d488252c: comp_qexe + 0x1252c (?qexe_apply_ini_vars@@YAXXZ + 0x245c)\n\t0x7ff9d4887872: comp_qexe + 0x17872 (?qexe_process_cmdline_arguments@@YA_NPEAVQEXE_CMDLINE@@HPEAPEBD@Z + 0x2762)\n\t0x7ff9d4888601: comp_qexe + 0x18601 (?qexe_standard_main@@YAHPEAVQEXE_FRAMEWORK@@PEAPEBUQEXE_OPTION_DEFINITION@@HPEAPEBD@Z + 0xc1)\n\t0x7ff73e97c71d: quartus_map + 0x1c71d\n\t0x7ff9d19fcbe8: CCL_MSG + 0xcbe8 (?msg_initialize_out_of_memory_handler@@YAXXZ + 0x378)\n\t0x7ff9d19fe31c: CCL_MSG + 0xe31c (?msg_set_stack_size@@YAXH@Z + 0x7c)\n\t0x7ff9d1b24c0c: ccl_mem + 0x4c0c (?mem_malloc_wrapper@@YAPEAX_KPEAVMEM_TRACKER_THUNK@@PEBD@Z + 0x18c)\n\t0x7ff9d19fc831: CCL_MSG + 0xc831 (?msg_exe_main@@YAHHPEAPEBDP6AHH0@Z@Z + 0xa1)\n\t0x7ff73e98b072: quartus_map + 0x2b072\n\t0x7ff9f0787033: KERNEL32 + 0x17033 (BaseThreadInitThunk + 0x13)\n\t0x7ff9f1e02650: ntdll + 0x52650 (RtlUserThreadStart + 0x20)\n",
14 | "subsystem" : "unknown"
15 | },
16 | "quartus" : {
17 | "quartus_bits" : "64",
18 | "version" : "15.0.0",
19 | "build" : "145",
20 | "edition" : "Full Version"
21 | }
22 | }
--------------------------------------------------------------------------------
/digital-design.qpf:
--------------------------------------------------------------------------------
1 | # -------------------------------------------------------------------------- #
2 | #
3 | # Copyright (C) 2020 Intel Corporation. All rights reserved.
4 | # Your use of Intel Corporation's design tools, logic functions
5 | # and other software and tools, and any partner logic
6 | # functions, and any output files from any of the foregoing
7 | # (including device programming or simulation files), and any
8 | # associated documentation or information are expressly subject
9 | # to the terms and conditions of the Intel Program License
10 | # Subscription Agreement, the Intel Quartus Prime License Agreement,
11 | # the Intel FPGA IP License Agreement, or other applicable license
12 | # agreement, including, without limitation, that your use is for
13 | # the sole purpose of programming logic devices manufactured by
14 | # Intel and sold by Intel or its authorized distributors. Please
15 | # refer to the applicable agreement for further details, at
16 | # https://fpgasoftware.intel.com/eula.
17 | #
18 | # -------------------------------------------------------------------------- #
19 | #
20 | # Quartus Prime
21 | # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
22 | # Date created = 20:54:43 April 12, 2021
23 | #
24 | # -------------------------------------------------------------------------- #
25 |
26 | QUARTUS_VERSION = "20.1"
27 | DATE = "20:54:43 April 12, 2021"
28 |
29 | # Revisions
30 |
31 | PROJECT_REVISION = "digital-design"
32 |
--------------------------------------------------------------------------------
/digital-design.qsf:
--------------------------------------------------------------------------------
1 | # -------------------------------------------------------------------------- #
2 | #
3 | # Copyright (C) 2020 Intel Corporation. All rights reserved.
4 | # Your use of Intel Corporation's design tools, logic functions
5 | # and other software and tools, and any partner logic
6 | # functions, and any output files from any of the foregoing
7 | # (including device programming or simulation files), and any
8 | # associated documentation or information are expressly subject
9 | # to the terms and conditions of the Intel Program License
10 | # Subscription Agreement, the Intel Quartus Prime License Agreement,
11 | # the Intel FPGA IP License Agreement, or other applicable license
12 | # agreement, including, without limitation, that your use is for
13 | # the sole purpose of programming logic devices manufactured by
14 | # Intel and sold by Intel or its authorized distributors. Please
15 | # refer to the applicable agreement for further details, at
16 | # https://fpgasoftware.intel.com/eula.
17 | #
18 | # -------------------------------------------------------------------------- #
19 | #
20 | # Quartus Prime
21 | # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
22 | # Date created = 20:54:08 April 12, 2021
23 | #
24 | # -------------------------------------------------------------------------- #
25 | #
26 | # Notes:
27 | #
28 | # 1) The default values for assignments are stored in the file:
29 | # digital-design_assignment_defaults.qdf
30 | # If this file doesn't exist, see file:
31 | # assignment_defaults.qdf
32 | #
33 | # 2) Altera recommends that you do not modify this file. This
34 | # file is updated automatically by the Quartus Prime software
35 | # and any changes you make may be lost or overwritten.
36 | #
37 | # -------------------------------------------------------------------------- #
38 |
39 |
40 | set_global_assignment -name FAMILY "Cyclone IV E"
41 | set_global_assignment -name DEVICE EP4CE115F29I7
42 | set_global_assignment -name TOP_LEVEL_ENTITY mod_top
43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:54:08 APRIL 12, 2021"
45 | set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
50 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
51 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
52 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
53 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
54 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
55 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
56 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
57 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
58 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
59 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
60 |
61 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
62 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
63 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
64 | set_global_assignment -name ENABLE_OCT_DONE OFF
65 | set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
66 | set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
67 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
68 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
69 |
70 | set_global_assignment -name QIP_FILE ip/pll/ip_pll.qip
71 | set_global_assignment -name VERILOG_FILE src/dpy_scan.v
72 | set_global_assignment -name VERILOG_FILE src/vga.v
73 | set_global_assignment -name SOURCE_TCL_SCRIPT_FILE io.tcl
74 | set_global_assignment -name SYSTEMVERILOG_FILE src/mod_top.sv
75 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
76 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
77 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
78 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
79 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
80 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
81 | set_global_assignment -name SYSTEMVERILOG_FILE ram30728.sv
82 | set_global_assignment -name SYSTEMVERILOG_FILE ram_for_layer.sv
83 | set_global_assignment -name SYSTEMVERILOG_FILE dir_parser.sv
84 | set_global_assignment -name SYSTEMVERILOG_FILE spi_session.sv
85 | set_global_assignment -name SYSTEMVERILOG_FILE sd_file_reader.sv
86 | set_global_assignment -name SYSTEMVERILOG_FILE sd_spi_sector_reader.sv
87 | set_global_assignment -name SYSTEMVERILOG_FILE ClassificationNet.sv
88 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
89 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
90 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
91 | set_global_assignment -name CDF_FILE output_files/Chain1.cdf
92 | set_global_assignment -name CDF_FILE output_files/Chain2.cdf
93 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
94 | set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
95 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--------------------------------------------------------------------------------
/digital-design.sdc:
--------------------------------------------------------------------------------
1 | # This is a basic timing constriant file
2 | set_time_format -unit ns -decimal_places 3
3 |
4 | # 100MHz input clock
5 | create_clock -name {clk_100m} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk_100m}]
6 | set_clock_uncertainty -rise_from [get_clocks {clk_100m}] -rise_to [get_clocks {clk_100m}] 0.020
7 | set_clock_uncertainty -rise_from [get_clocks {clk_100m}] -fall_to [get_clocks {clk_100m}] 0.020
8 | set_clock_uncertainty -fall_from [get_clocks {clk_100m}] -rise_to [get_clocks {clk_100m}] 0.020
9 | set_clock_uncertainty -fall_from [get_clocks {clk_100m}] -fall_to [get_clocks {clk_100m}] 0.020
10 |
11 | # Clocks generated by PLL
12 | derive_pll_clocks -create_base_clocks
13 |
--------------------------------------------------------------------------------
/doc/final_report.pdf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/liuch00/fpga_cnn/377f77932bf8ad5b50aff3503a11ef17eed98966/doc/final_report.pdf
--------------------------------------------------------------------------------
/ip/pll/ip_pll.ppf:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
--------------------------------------------------------------------------------
/ip/pll/ip_pll.qip:
--------------------------------------------------------------------------------
1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL"
2 | set_global_assignment -name IP_TOOL_VERSION "20.1"
3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ip_pll.v"]
5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ip_pll_inst.v"]
6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ip_pll_bb.v"]
7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ip_pll.ppf"]
8 |
--------------------------------------------------------------------------------
/spinalPro/.gitignore:
--------------------------------------------------------------------------------
1 | spinalPro/*.class
2 | spinalPro/*.log
3 | spinalPro/*.bak
4 |
5 | # sbt specific
6 | spinalPro/.cache/
7 | spinalPro/.history/
8 | spinalPro/.lib/
9 | spinalPro/dist/*
10 | spinalPro/target
11 | spinalPro/lib_managed/
12 | spinalPro/src_managed/
13 | spinalPro/project/boot/
14 | spinalPro/project/plugins/project/
15 |
16 | # Scala-IDE specific
17 | spinalPro/.scala_dependencies
18 | spinalPro/.worksheet
19 |
20 | spinalPro/.idea
21 | spinalPro/out
22 |
23 | # Eclipse
24 | spinalPro/bin/
25 | spinalPro/.classpath
26 | spinalPro/.project
27 | spinalPro/.settings
28 | spinalPro/.cache-main
29 |
30 | #User
31 | spinalPro/*.vhd
32 | spinalPro/*.v
33 | spinalPro/*.cf
34 | spinalPro/*.json
35 | spinalPro/*.vcd
36 | !spinalPro/tester/src/test/resources/*.vhd
37 |
38 |
39 | spinalPro/simWorkspace/
40 | spinalPro/tmp/
41 | spinalPro/null
42 |
--------------------------------------------------------------------------------
/spinalPro/README.md:
--------------------------------------------------------------------------------
1 | Spinal Base Project
2 | ============
3 | This repository is a base SBT project added to help non Scala/SBT native people in their first steps.
4 |
5 | Just one important note, you need a java JDK >= 8
6 |
7 | On debian :
8 |
9 | ```sh
10 | sudo add-apt-repository -y ppa:openjdk-r/ppa
11 | sudo apt-get update
12 | sudo apt-get install openjdk-8-jdk -y
13 |
14 | #To set the default java
15 | sudo update-alternatives --config java
16 | sudo update-alternatives --config javac
17 | ```
18 |
19 | ## Basics, without any IDE
20 |
21 | You need to install SBT
22 |
23 | ```sh
24 | echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
25 | sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
26 | sudo apt-get update
27 | sudo apt-get install sbt
28 | ```
29 |
30 | If you want to run the scala written testbench, you have to be on linux and have Verilator installed (a recent version) :
31 |
32 | ```sh
33 | sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites
34 | git clone http://git.veripool.org/git/verilator # Only first time
35 | unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
36 | unset VERILATOR_ROOT # For bash
37 | cd verilator
38 | git pull # Make sure we're up-to-date
39 | git checkout v4.040
40 | autoconf # Create ./configure script
41 | ./configure
42 | make -j$(nproc)
43 | sudo make install
44 | cd ..
45 | echo "DONE"
46 |
47 | ```
48 |
49 | Clone or download this repository.
50 |
51 | ```sh
52 | git clone https://github.com/SpinalHDL/SpinalTemplateSbt.git
53 | ```
54 |
55 | Open a terminal in the root of it and run "sbt run". At the first execution, the process could take some seconds
56 |
57 | ```sh
58 | cd SpinalTemplateSbt
59 |
60 | //If you want to generate the Verilog of your design
61 | sbt "runMain mylib.MyTopLevelVerilog"
62 |
63 | //If you want to generate the VHDL of your design
64 | sbt "runMain mylib.MyTopLevelVhdl"
65 |
66 | //If you want to run the scala written testbench
67 | sbt "runMain mylib.MyTopLevelSim"
68 | ```
69 |
70 | The top level spinal code is defined into src\main\scala\mylib
71 |
72 | ## Basics, with Intellij IDEA and its scala plugin
73 |
74 | You need to install :
75 |
76 | - Java JDK 8
77 | - SBT
78 | - Intellij IDEA (the free Community Edition is good enough)
79 | - Intellij IDEA Scala plugin (when you run Intellij IDEA the first time, he will ask you about it)
80 |
81 | And do the following :
82 |
83 | - Clone or download this repository.
84 | - In Intellij IDEA, "import project" with the root of this repository, Import project from external model SBT
85 | - In addition maybe you need to specify some path like JDK to Intellij
86 | - In the project (Intellij project GUI), go in src/main/scala/mylib/MyTopLevel.scala, right click on MyTopLevelVerilog, "Run MyTopLevelVerilog"
87 |
88 | Normally, this must generate an MyTopLevel.v output files.
89 |
90 | ## Basics, with Eclipse and its scala plugin
91 |
92 | First, i "strongly" suggest to use intellij idea instead.
93 |
94 | You need to install :
95 |
96 | - Java JDK
97 | - Scala
98 | - SBT
99 | - Eclipse (tested with Mars.2 - 4.5.2)
100 | - [scala plugin](http://scala-ide.org/) (tested with 4.4.1)
101 |
102 | And do the following :
103 |
104 | - Clone or download this repository.
105 | - Revert changes from https://github.com/SpinalHDL/SpinalTemplateSbt/commit/173bbb9bb8cbf70087339104f6ebced9321908dd
106 | - Run ```sbt eclipse``` in the ```SpinalTemplateSbt``` directory.
107 | - Import the eclipse project from eclipse.
108 | - In the project (eclipse project GUI), right click on src/main/scala/mylib/MyTopLevel.scala, right click on MyTopLevelVerilog, and select run it
109 |
110 | Normally, this must generate output file ```MyTopLevel.v```.
111 |
112 |
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/spinalPro/build.sbt:
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1 | name := "SpinalTemplateSbt"
2 | version := "1.0"
3 | scalaVersion := "2.11.12"
4 | val spinalVersion = "1.4.3"
5 |
6 | libraryDependencies ++= Seq(
7 | "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion,
8 | "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion,
9 | compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion)
10 | )
11 |
12 | fork := true
13 |
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1 | {
2 | "semanticDBVersion": "4.4.20",
3 | "supportedScalaVersions": [
4 | "2.13.6",
5 | "2.12.14",
6 | "2.12.13",
7 | "2.12.12",
8 | "2.12.11",
9 | "2.12.10",
10 | "2.13.3",
11 | "2.13.4",
12 | "2.13.5",
13 | "2.11.12",
14 | "2.12.8",
15 | "2.12.9",
16 | "2.13.0",
17 | "2.13.1",
18 | "2.13.2"
19 | ]
20 | }
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/spinalPro/project/build.properties:
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1 | sbt.version=1.3.13
2 |
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/spinalPro/project/metals.sbt:
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1 | // DO NOT EDIT! This file is auto-generated.
2 | // This file enables sbt-bloop to create bloop config files.
3 |
4 | addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.8-19-4d9f966b")
5 |
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1 | {
2 | "semanticDBVersion": "4.4.20",
3 | "supportedScalaVersions": [
4 | "2.13.6",
5 | "2.12.14",
6 | "2.12.13",
7 | "2.12.12",
8 | "2.12.11",
9 | "2.12.10",
10 | "2.13.3",
11 | "2.13.4",
12 | "2.13.5",
13 | "2.11.12",
14 | "2.12.8",
15 | "2.12.9",
16 | "2.13.0",
17 | "2.13.1",
18 | "2.13.2"
19 | ]
20 | }
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/spinalPro/project/project/metals.sbt:
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1 | // DO NOT EDIT! This file is auto-generated.
2 | // This file enables sbt-bloop to create bloop config files.
3 |
4 | addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.8-19-4d9f966b")
5 |
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/spinalPro/project/project/project/metals.sbt:
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1 | // DO NOT EDIT! This file is auto-generated.
2 | // This file enables sbt-bloop to create bloop config files.
3 |
4 | addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.8-19-4d9f966b")
5 |
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1 | [debug] "not up to date. inChanged = true, force = false
2 | [debug] Updating ProjectRef(uri("file:/C:/Users/90628/OneDrive/Code/SpinalHDL/digital-design-grp-01/spinalPro/project/project/project/"), "spinalpro-build-build-build")...
3 | [debug] Done updating ProjectRef(uri("file:/C:/Users/90628/OneDrive/Code/SpinalHDL/digital-design-grp-01/spinalPro/project/project/project/"), "spinalpro-build-build-build")
4 | [warn] There may be incompatibilities among your library dependencies; run 'evicted' to see detailed eviction warnings.
5 |
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1 | ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["C:\\Users\\90628\\OneDrive\\Code\\SpinalHDL\\digital-design-grp-01\\spinalPro\\project\\project\\project\\target\\streams\\compile\\compileOutputs\\_global\\streams\\inc_compile_2.12.zip"]]
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1 | ["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[]}}]
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1 | [debug] Full compilation, no sources in previous analysis.
2 |
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1 | [[{},{}],{}]
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1 | [debug] Copy resource mappings:
2 | [debug]
3 |
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2 |
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1 |
2 |
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2 |
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2 |
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2 |
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2 |
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1 | C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\project\project\target\scala-2.12\sbt-1.0\classes
2 |
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2 |
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1 |
2 |
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1 | [debug] downloaded https://repo1.maven.org/maven2/com/lihaoyi/fastparse-utils_2.12/0.4.2/fastparse-utils_2.12-0.4.2-sources.jar
2 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5-sources.jar
3 | [debug] downloaded https://repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.8.3/sjson-new-murmurhash_2.12-0.8.3-sources.jar
4 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.13/scripted-plugin_2.12-1.3.13-sources.jar
5 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.4/librarymanagement-core_2.12-1.3.4-sources.jar
6 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3-sources.jar
7 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.4/librarymanagement-ivy_2.12-1.3.4-sources.jar
8 | [debug] downloaded https://repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3-sources.jar
9 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.3.5/zinc-classfile_2.12-1.3.5-sources.jar
10 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.13/testing_2.12-1.3.13-sources.jar
11 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.13/completion_2.12-1.3.13-sources.jar
12 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.13/tasks_2.12-1.3.13-sources.jar
13 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3-sources.jar
14 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.3.5/zinc-persist_2.12-1.3.5-sources.jar
15 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3-sources.jar
16 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.13/zinc-lm-integration_2.12-1.3.13-sources.jar
17 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.3.5/zinc-apiinfo_2.12-1.3.5-sources.jar
18 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.13/command_2.12-1.3.13-sources.jar
19 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.13/core-macros_2.12-1.3.13-sources.jar
20 | [debug] downloaded https://repo1.maven.org/maven2/com/trueaccord/lenses/lenses_2.12/0.4.12/lenses_2.12-0.4.12-sources.jar
21 | [debug] downloaded https://repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0-sources.jar
22 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.3.5/zinc-classpath_2.12-1.3.5-sources.jar
23 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.5/zinc-compile-core_2.12-1.3.5-sources.jar
24 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.4/launcher-interface-1.1.4-sources.jar
25 | [debug] downloaded https://repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-4/lm-coursier-shaded_2.12-2.0.0-RC6-4-sources.jar
26 | [debug] downloaded https://repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.12/0.1.3/sourcecode_2.12-0.1.3-sources.jar
27 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.0.1/ipcsocket-1.0.1-sources.jar
28 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.13/task-system_2.12-1.3.13-sources.jar
29 | [debug] downloaded https://repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3-sources.jar
30 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.13/logic_2.12-1.3.13-sources.jar
31 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-sources.jar
32 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.13/main_2.12-1.3.13-sources.jar
33 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4-sources.jar
34 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-sources.jar
35 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.13/run_2.12-1.3.13-sources.jar
36 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.13/scripted-sbt-redux_2.12-1.3.13-sources.jar
37 | [debug] downloaded https://repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4-sources.jar
38 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.13/test-agent-1.3.13-sources.jar
39 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3-sources.jar
40 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.13/actions_2.12-1.3.13-sources.jar
41 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.3.5/zinc-core_2.12-1.3.5-sources.jar
42 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.5/compiler-bridge_2.12-1.3.5-sources.jar
43 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5-sources.jar
44 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.3.3/util-tracking_2.12-1.3.3-sources.jar
45 | [debug] downloaded https://repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.8.3/sjson-new-scalajson_2.12-0.8.3-sources.jar
46 | [debug] downloaded https://repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0-sources.jar
47 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3-sources.jar
48 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3-sources.jar
49 | [debug] downloaded https://repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6-sources.jar
50 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.13/collections_2.12-1.3.13-sources.jar
51 | [debug] downloaded https://repo1.maven.org/maven2/com/trueaccord/scalapb/scalapb-runtime_2.12/0.6.0/scalapb-runtime_2.12-0.6.0-sources.jar
52 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.13/main-settings_2.12-1.3.13-sources.jar
53 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.13/sbt-1.3.13-sources.jar
54 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.13/protocol_2.12-1.3.13-sources.jar
55 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-lang/scala-compiler/2.12.10/scala-compiler-2.12.10-sources.jar
56 | [debug] downloaded https://repo1.maven.org/maven2/com/lihaoyi/fastparse_2.12/0.4.2/fastparse_2.12-0.4.2-sources.jar
57 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-839fad1cdc07cf6fc81364d74c323867230432ad/ivy-2.3.0-sbt-839fad1cdc07cf6fc81364d74c323867230432ad-sources.jar
58 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.5/zinc_2.12-1.3.5-sources.jar
59 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.0/sbinary_2.12-0.5.0-sources.jar
60 | [debug] downloaded https://repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3-sources.jar
61 | [debug] downloaded https://repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0-sources.jar
62 |
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/spinalPro/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp:
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1 | -474989356
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/spinalPro/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp:
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1 | {"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"1.4.8-19-4d9f966b\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"C:\\Users\\90628\\OneDrive\\Code\\SpinalHDL\\digital-design-grp-01\\spinalPro\\project\\project\\metals.sbt","range":{"$fields":["start","end"],"start":4,"end":5}},"type":"RangePosition"}}
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/spinalPro/project/project/target/streams/_global/ivySbt/_global/streams/out:
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/spinalPro/project/project/target/streams/_global/moduleSettings/_global/streams/out:
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/spinalPro/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out:
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/spinalPro/project/project/target/streams/_global/update/_global/streams/out:
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1 | [debug] "not up to date. inChanged = true, force = false
2 | [debug] Updating ProjectRef(uri("file:/C:/Users/90628/OneDrive/Code/SpinalHDL/digital-design-grp-01/spinalPro/project/project/"), "spinalpro-build-build")...
3 | [debug] Done updating ProjectRef(uri("file:/C:/Users/90628/OneDrive/Code/SpinalHDL/digital-design-grp-01/spinalPro/project/project/"), "spinalpro-build-build")
4 | [warn] There may be incompatibilities among your library dependencies; run 'evicted' to see detailed eviction warnings.
5 |
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/spinalPro/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out:
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1 | [debug] Other repositories:
2 | [debug] Default repositories:
3 |
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/spinalPro/project/project/target/streams/compile/_global/_global/compileOutputs/previous:
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1 | ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["C:\\Users\\90628\\OneDrive\\Code\\SpinalHDL\\digital-design-grp-01\\spinalPro\\project\\project\\target\\streams\\compile\\compileOutputs\\_global\\streams\\inc_compile_2.12.zip"]]
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/spinalPro/project/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous:
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1 | ["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[]}}]
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/spinalPro/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data:
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1 | []
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/spinalPro/project/project/target/streams/compile/_global/_global/managedSourcePaths/previous:
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1 | ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]]
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/spinalPro/project/project/target/streams/compile/bloopGenerate/_global/streams/out:
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1 | [debug] [spinalpro-build-build] Classpath dependencies List()
2 | [debug] [spinalpro-build-build] Dependencies from configurations List()
3 | [debug] Bloop wrote the configuration of project 'spinalpro-build-build' to 'C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\project\.bloop\spinalpro-build-build.json'
4 | [success] Generated .bloop\spinalpro-build-build.json
5 |
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/spinalPro/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out:
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1 | [debug] Running postGenerate for spinalpro-build-build
2 |
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/spinalPro/project/project/target/streams/compile/compileIncremental/_global/streams/out:
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1 | [debug] Full compilation, no sources in previous analysis.
2 |
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/spinalPro/project/project/target/streams/compile/copyResources/_global/streams/copy-resources:
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1 | [[{},{}],{}]
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/spinalPro/project/project/target/streams/compile/copyResources/_global/streams/out:
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1 | [debug] Copy resource mappings:
2 | [debug]
3 |
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/spinalPro/project/project/target/streams/compile/dependencyClasspath/_global/streams/export:
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1 | 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2 |
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1 | C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\project\target\scala-2.12\sbt-1.0\classes
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1 | C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\ch\epfl\scala\sbt-bloop_2.12_1.0\1.4.8-19-4d9f966b\sbt-bloop-1.4.8-19-4d9f966b.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\net\java\dev\jna\jna\5.5.0\jna-5.5.0.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\net\java\dev\jna\jna-platform\5.5.0\jna-platform-5.5.0.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\com\google\code\gson\gson\2.7\gson-2.7.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\com\google\code\findbugs\jsr305\3.0.2\jsr305-3.0.2.jar
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2 |
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1 | C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\ch\epfl\scala\sbt-bloop_2.12_1.0\1.4.8-19-4d9f966b\sbt-bloop-1.4.8-19-4d9f966b.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\net\java\dev\jna\jna\5.5.0\jna-5.5.0.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\net\java\dev\jna\jna-platform\5.5.0\jna-platform-5.5.0.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\com\google\code\gson\gson\2.7\gson-2.7.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\com\google\code\findbugs\jsr305\3.0.2\jsr305-3.0.2.jar
2 |
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1 | [debug] "not up to date. inChanged = true, force = false
2 | [debug] Updating ProjectRef(uri("file:/C:/Users/90628/OneDrive/Code/SpinalHDL/digital-design-grp-01/spinalPro/project/"), "spinalpro-build")...
3 | [debug] Done updating ProjectRef(uri("file:/C:/Users/90628/OneDrive/Code/SpinalHDL/digital-design-grp-01/spinalPro/project/"), "spinalpro-build")
4 | [warn] There may be incompatibilities among your library dependencies; run 'evicted' to see detailed eviction warnings.
5 |
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1 | [debug] Other repositories:
2 | [debug] Default repositories:
3 |
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1 | [debug] [spinalpro-build] Classpath dependencies List()
2 | [debug] [spinalpro-build] Dependencies from configurations List()
3 | [debug] Bloop wrote the configuration of project 'spinalpro-build' to 'C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\.bloop\spinalpro-build.json'
4 | [success] Generated .bloop\spinalpro-build.json
5 |
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1 | [debug] Running postGenerate for spinalpro-build
2 |
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1 | [debug] Full compilation, no sources in previous analysis.
2 |
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1 | [debug] Copy resource mappings:
2 | [debug]
3 |
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1 | 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2 |
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/spinalPro/project/target/streams/compile/exportedProducts/_global/streams/export:
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1 | C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\target\scala-2.12\sbt-1.0\classes
2 |
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/spinalPro/project/target/streams/compile/internalDependencyClasspath/_global/streams/export:
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1 |
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/spinalPro/project/target/streams/compile/managedClasspath/_global/streams/export:
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2 |
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1 | C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\target\scala-2.12\sbt-1.0\classes
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2 |
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1 | C:\Users\90628\OneDrive\Code\SpinalHDL\digital-design-grp-01\spinalPro\project\target\scala-2.12\sbt-1.0\classes
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1 | C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\ch\epfl\scala\sbt-bloop_2.12_1.0\1.4.8-19-4d9f966b\sbt-bloop-1.4.8-19-4d9f966b.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\net\java\dev\jna\jna\5.5.0\jna-5.5.0.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\net\java\dev\jna\jna-platform\5.5.0\jna-platform-5.5.0.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\com\google\code\gson\gson\2.7\gson-2.7.jar;C:\Users\90628\AppData\Local\Coursier\cache\v1\https\repo1.maven.org\maven2\com\google\code\findbugs\jsr305\3.0.2\jsr305-3.0.2.jar
2 |
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/spinalPro/project/target/streams/test/bloopPostGenerate/_global/streams/out:
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https://raw.githubusercontent.com/liuch00/fpga_cnn/377f77932bf8ad5b50aff3503a11ef17eed98966/spinalPro/project/target/streams/test/bloopPostGenerate/_global/streams/out
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/spinalPro/src/main/scala/mylib/AvgPoolBlock.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 池化层接口
6 | object AvgPool2d {
7 | def apply(
8 | input : FeatureMap,
9 | kernel_size: Int,
10 | stride: Int,
11 | padding : Int,
12 | peak : Int = 5,
13 | resolution: Int = 10
14 | ) : FeatureMap = {
15 | val width_out = (input.width + 2 * padding - kernel_size) / stride + 1
16 | val height_out = (input.height + 2 * padding - kernel_size) / stride + 1
17 | val block = new AvgPoolBlock(
18 | peak = peak,
19 | resolution = resolution,
20 | channel_in = input.channel,
21 | channel_out = input.channel,
22 | width_in = input.width,
23 | height_in = input.height,
24 | layer_index = input.layer,
25 | file_path = input.file_path,
26 | weight_config = input.weight_config,
27 | stride = stride,
28 | kernel_size = kernel_size,
29 | padding = padding
30 | )
31 | block.io.input := input.points
32 | val output = FeatureMap(
33 | peak = peak,
34 | resolution = resolution,
35 | height = height_out,
36 | width = width_out,
37 | channel = input.channel,
38 | file_path = input.file_path,
39 | weight_config = input.weight_config,
40 | layer = input.layer
41 | )
42 | output.points := block.io.output
43 | output
44 | }
45 | }
46 |
47 | // 池化层的模块
48 | class AvgPoolBlock(
49 | peak : Int = 5,
50 | resolution: Int = 10,
51 | channel_in : Int,
52 | channel_out : Int,
53 | width_in : Int,
54 | height_in : Int,
55 | layer_index : Int,
56 | file_path : String,
57 | weight_config : List[List[Int]],
58 | stride : Int,
59 | kernel_size : Int,
60 | padding : Int
61 | ) extends Component {
62 | // 根据卷积层的有关公式计算输出的维度
63 | val width_out = (width_in + 2 * padding - kernel_size) / stride + 1
64 | val height_out = (height_in + 2 * padding - kernel_size) / stride + 1
65 |
66 | val io = new Bundle {
67 | val input = in (Flow(
68 | Vec (SFix( peak exp, -resolution exp), width_in)
69 | ))
70 | val output = out (Flow(
71 | Vec (SFix( peak exp, -resolution exp), width_out)
72 | ))
73 | }
74 |
75 |
76 | // 创建控制核心
77 | val core = new AvgPoolCore(
78 | peak,
79 | resolution,
80 | width_in,
81 | height_in,
82 | channel_in,
83 | 1,
84 | kernel_size,
85 | stride,
86 | padding,
87 | file_path,
88 | weight_config,
89 | layer_index
90 | )
91 | core.io.valid_in := io.input.valid
92 | core.io.data_in := io.input.payload
93 |
94 | // 输出流
95 | val output = Flow(
96 | Vec (SFix( peak exp, -resolution exp), width_out)
97 | )
98 | // 输出矩阵
99 | val output_matrix = Vec(
100 | Vec(Reg(SFix( peak exp, -resolution exp)) init(0), width_out
101 | ), 1)
102 |
103 | // 设置输出
104 | when (core.io.valid_out) {
105 | output_matrix := core.io.data_out
106 | }
107 |
108 | // 设置使能
109 | val output_valid = Reg(Bool) init(False)
110 | when(core.io.valid_out){
111 | output_valid := True
112 | }.elsewhen (Delay(core.io.valid_out, 1)) {
113 | output_valid := False
114 | }
115 | output.valid := output_valid
116 | // 池化层需要除以kernel_size^2
117 | // 算平均值
118 | output.payload := (Vec(
119 | output_matrix(0).map{x =>
120 | val res = cloneOf(x);
121 | res.raw := x.raw / (kernel_size * kernel_size);
122 | res
123 | }
124 | ))
125 |
126 | io.output := output
127 | }
128 |
129 | // 池化层控制核心
130 | class AvgPoolCore(
131 | peak : Int = 5,
132 | resolution: Int = 10,
133 | width_in : Int,
134 | height_in : Int,
135 | channel_in : Int,
136 | channel_out: Int,
137 | kernel_size: Int,
138 | stride : Int,
139 | padding : Int,
140 | file_path : String,
141 | weight_config : List[List[Int]],
142 | layer_index : Int
143 | ) extends Component {
144 | // 根据池化层的有关公式计算输出的维度
145 | val width_out = (width_in + 2 * padding - kernel_size) / stride + 1
146 | val height_out = (height_in + 2 * padding - kernel_size) / stride + 1
147 |
148 | val io = new Bundle {
149 | val valid_in = in Bool
150 | val valid_out = out Bool
151 | val data_in = in (
152 | Vec (SFix( peak exp, -resolution exp), width_in)
153 | )
154 | val data_out = out (
155 | Vec(Vec (SFix( peak exp, -resolution exp), width_out), channel_out)
156 | )
157 | }
158 |
159 |
160 | // 开辟feature map的ram, 初始化为全0
161 | val fmRAM = Mem(Vec(
162 | SFix( peak exp, -resolution exp), width_in),
163 | wordCount = (height_in + 2 * padding) * channel_in * 2
164 | )
165 | fmRAM.init(
166 | Vec(
167 | (0 until (height_in + 2 * padding) * channel_in * 2).map(
168 | x => Vec((0 until width_in).map{
169 | x => val ret = SFix(peak exp, -resolution exp);
170 | ret := 0;
171 | ret
172 | }.toList))
173 | )
174 | )
175 |
176 | // 读写信号
177 | val write_signal = Reg(Bool) init(False)
178 | val read_signal = Reg(Bool) init(True)
179 |
180 | // feature map地址
181 | val fm_addr = Reg(UInt(
182 | log2Up(channel_in * (height_in + 2 * padding))bits
183 | )) init(channel_in * padding)
184 |
185 | // 写入
186 | when (io.valid_in) {
187 | when(fm_addr < channel_in * (height_in + padding) - 1) {
188 | fm_addr := fm_addr + 1
189 | }.otherwise{
190 | fm_addr := channel_in * padding
191 | }
192 | }
193 | fmRAM.write(
194 | address = U(fm_addr ## write_signal),
195 | data = io.data_in,
196 | enable = io.valid_in
197 | )
198 |
199 | val start = Reg(Bool) init(False) // 是否为开头
200 | when (
201 | io.valid_in &&
202 | fm_addr === channel_in * (height_in + padding) - 1
203 | ) {
204 | start := True
205 | read_signal := !read_signal
206 | write_signal := !write_signal
207 | }.otherwise {
208 | start := False
209 | }
210 |
211 | // control 逻辑
212 | val avgpool_ctrl = new LayerCtrl(
213 | channel_in, height_in, height_out,
214 | kernel_size, stride, padding, channel_in
215 | )
216 | avgpool_ctrl.io.start := start
217 |
218 | // 从ram中读取feature map
219 | val content = Vec(
220 | SFix( peak exp, -resolution exp), width_in)
221 | content := fmRAM.readSync(
222 | address = U(avgpool_ctrl.io.fm_addr ## read_signal)
223 | )
224 | val raw_fm = Vec(Reg(
225 | SFix(peak exp, -resolution exp)) init(0),
226 | 2 * padding + width_in
227 | )
228 |
229 | // 读入feature map
230 | when(Delay(avgpool_ctrl.io.shift, 1)) {
231 | for (i <- 0 until (2 * padding + width_in - 1)) {
232 | raw_fm(i) := raw_fm(i + 1)
233 | }
234 | }.otherwise {
235 | // 这里还需要在考虑一下
236 | // padding是否会影响正常赋值
237 | for(i <- 0 until width_in) {
238 | raw_fm(i) := content(i)
239 | }
240 | }
241 |
242 | // 设置Layer
243 | val avgpool_layer = new AvgPoolLayer(
244 | width_out = width_out,
245 | channel_out = channel_out,
246 | peak = peak,
247 | resolution = resolution
248 | )
249 |
250 | avgpool_layer.io.clear := avgpool_ctrl.io.clear
251 | for (i <- 0 until width_out) {
252 | avgpool_layer.io.map(i) := raw_fm(i * stride)
253 | }
254 |
255 | // 连线
256 | // 等四个时钟周期
257 | // 直到数据处理完毕
258 | io.valid_out := Delay(avgpool_ctrl.io.valid, 4, init = False)
259 | io.data_out := avgpool_layer.io.output
260 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/AvgPoolLayer.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 定义平均池化层的类
6 |
7 | class AvgPoolLayer(
8 | peak : Int = 5,
9 | resolution: Int = 10,
10 | channel_out: Int,
11 | width_out: Int
12 | ) extends Component {
13 | val io = new Bundle {
14 | val clear = in Bool
15 | val map = in (
16 | Vec (SFix( peak exp, -resolution exp), width_out)
17 | )
18 | val output = out (Vec(
19 | Vec (SFix( peak exp, -resolution exp), width_out)
20 | , channel_out))
21 | }
22 |
23 | val res = Vec(
24 | Vec(Reg(SFix( (peak * 2) exp, -resolution exp))
25 | init(0), width_out),
26 | channel_out)
27 | val output = Vec(
28 | Vec(Reg(SFix( (peak) exp, -resolution exp))
29 | init(0), width_out),
30 | channel_out)
31 |
32 | // 池化运算
33 | for (c <- 0 until channel_out) {
34 | for (w <- 0 until width_out) {
35 | res(c)(w) := io.map(w)
36 | }
37 | }
38 |
39 | // clear 接口
40 | when (Delay (io.clear, 3)) {
41 | for (c <- 0 until channel_out) {
42 | for (w <- 0 until width_out) {
43 | output(c)(w) := res(c)(w).truncated
44 | }
45 | }
46 | }.otherwise {
47 | for (c <- 0 until channel_out) {
48 | for (w <- 0 until width_out) {
49 | output(c)(w) := (output(c)(w) + res(c)(w)).truncated
50 | }
51 | }
52 | }
53 |
54 | io.output := output
55 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/ConvolutionBlock.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 卷积层接口
6 | object Convolution2d {
7 | def apply(
8 | input : FeatureMap,
9 | channel_in : Int,
10 | channel_out: Int,
11 | kernel_size: Int,
12 | stride: Int,
13 | padding : Int,
14 | bias : Bool,
15 | peak : Int = 5,
16 | resolution: Int = 10
17 | ) : FeatureMap = {
18 | val width_out = (input.width + 2 * padding - kernel_size) / stride + 1
19 | val height_out = (input.height + 2 * padding - kernel_size) / stride + 1
20 | val block = new ConvolutionBlock(
21 | peak = peak,
22 | resolution = resolution,
23 | channel_in = channel_in,
24 | channel_out = channel_out,
25 | width_in = input.width,
26 | height_in = input.height,
27 | layer_index = input.layer,
28 | file_path = input.file_path,
29 | weight_config = input.weight_config,
30 | stride = stride,
31 | kernel_size = kernel_size,
32 | padding = padding
33 | )
34 | block.io.input := input.points
35 | val output = FeatureMap(
36 | peak = peak,
37 | resolution = resolution,
38 | height = height_out,
39 | width = width_out,
40 | channel = channel_out,
41 | file_path = input.file_path,
42 | weight_config = input.weight_config,
43 | layer = input.layer + 1
44 | )
45 | output.points := block.io.output
46 | output
47 | }
48 | }
49 |
50 | // 卷积层的模块
51 | class ConvolutionBlock(
52 | peak : Int = 5,
53 | resolution: Int = 10,
54 | channel_in : Int,
55 | channel_out : Int,
56 | width_in : Int,
57 | height_in : Int,
58 | layer_index : Int,
59 | file_path : String,
60 | weight_config : List[List[Int]],
61 | stride : Int,
62 | kernel_size : Int,
63 | padding : Int
64 | ) extends Component {
65 | // 根据卷积层的有关公式计算输出的维度
66 | val width_out = (width_in + 2 * padding - kernel_size) / stride + 1
67 | val height_out = (height_in + 2 * padding - kernel_size) / stride + 1
68 |
69 | val io = new Bundle {
70 | val input = in (Flow(
71 | Vec (SFix( peak exp, -resolution exp), width_in)
72 | ))
73 | val output = out (Flow(
74 | Vec (SFix( peak exp, -resolution exp), width_out)
75 | ))
76 | }
77 |
78 |
79 | // 创建控制核心
80 | val core = new ConvolutionCore(
81 | peak,
82 | resolution,
83 | width_in,
84 | height_in,
85 | channel_in,
86 | channel_out,
87 | kernel_size,
88 | stride,
89 | padding,
90 | file_path,
91 | weight_config,
92 | layer_index
93 | )
94 | core.io.valid_in := io.input.valid
95 | core.io.data_in := io.input.payload
96 |
97 | // 输出流
98 | val output = Flow(
99 | Vec (SFix( peak exp, -resolution exp), width_out)
100 | )
101 | // 输出矩阵
102 | val output_matrix = Vec(
103 | Vec(Reg(SFix( peak exp, -resolution exp) ) init(0), width_out
104 | ), channel_out)
105 |
106 | // 设置输出
107 | when (core.io.valid_out) {
108 | output_matrix := core.io.data_out
109 | }.otherwise {
110 | for (i <- 0 until channel_out - 1) {
111 | output_matrix(i) := output_matrix(i+1)
112 | }
113 | }
114 |
115 | // 设置使能
116 | val output_valid = Reg(Bool) init(False)
117 | when(core.io.valid_out){
118 | output_valid := True
119 | }.elsewhen (Delay(core.io.valid_out, channel_out)) {
120 | output_valid := False
121 | }
122 | output.valid := output_valid
123 | output.payload := output_matrix(0)
124 |
125 | io.output := output
126 | }
127 |
128 |
129 | // 卷积层控制核心
130 | class ConvolutionCore(
131 | peak : Int = 5,
132 | resolution: Int = 10,
133 | width_in : Int,
134 | height_in : Int,
135 | channel_in : Int,
136 | channel_out: Int,
137 | kernel_size: Int,
138 | stride : Int,
139 | padding : Int,
140 | file_path : String,
141 | weight_config : List[List[Int]],
142 | layer_index : Int
143 | ) extends Component {
144 | // 根据卷积层的有关公式计算输出的维度
145 | val width_out = (width_in + 2 * padding - kernel_size) / stride + 1
146 | val height_out = (height_in + 2 * padding - kernel_size) / stride + 1
147 |
148 | val io = new Bundle {
149 | val valid_in = in Bool
150 | val valid_out = out Bool
151 | val data_in = in (
152 | Vec (SFix( peak exp, -resolution exp), width_in)
153 | )
154 | val data_out = out (
155 | Vec(Vec (SFix( peak exp, -resolution exp), width_out), channel_out)
156 | )
157 | }
158 |
159 |
160 | // 开辟feature map的ram, 初始化为全0
161 | val fmRAM = Mem(Vec(
162 | SFix( peak exp, -resolution exp), width_in),
163 | wordCount = (height_in + 2 * padding) * channel_in * 2
164 | )
165 | fmRAM.init(
166 | Vec(
167 | (0 until (height_in + 2 * padding) * channel_in * 2).map(
168 | x => Vec((0 until width_in).map{
169 | x => val ret = SFix(peak exp, -resolution exp);
170 | ret := 0;
171 | ret
172 | }.toList))
173 | )
174 | )
175 |
176 | // 读写信号
177 | val write_signal = Reg(Bool) init(False)
178 | val read_signal = Reg(Bool) init(True)
179 |
180 | // feature map地址
181 | val fm_addr = Reg(UInt(
182 | log2Up(channel_in * (height_in + 2 * padding))bits
183 | )) init(channel_in * padding)
184 |
185 | // 写入
186 | when (io.valid_in) {
187 | when(fm_addr < channel_in * (height_in + padding) - 1) {
188 | fm_addr := fm_addr + 1
189 | }.otherwise{
190 | fm_addr := channel_in * padding
191 | }
192 | }
193 | fmRAM.write(
194 | address = U(fm_addr ## write_signal),
195 | data = io.data_in,
196 | enable = io.valid_in
197 | )
198 |
199 | val start = Reg(Bool) init(False) // 是否为开头
200 | when (
201 | io.valid_in &&
202 | fm_addr === channel_in * (height_in + padding) - 1
203 | ) {
204 | start := True
205 | read_signal := !read_signal
206 | write_signal := !write_signal
207 | }.otherwise {
208 | start := False
209 | }
210 |
211 | // control 逻辑
212 | val conv_ctrl = new LayerCtrl(
213 | channel_in, height_in, height_out,
214 | kernel_size, stride, padding
215 | )
216 | conv_ctrl.io.start := start
217 |
218 | // 从ram中读取feature map
219 | val content = Vec(
220 | SFix( peak exp, -resolution exp), width_in)
221 | content := fmRAM.readSync(
222 | address = U(conv_ctrl.io.fm_addr ## read_signal)
223 | )
224 | val raw_fm = Vec(Reg(
225 | SFix(peak exp, -resolution exp)) init(0),
226 | 2 * padding + width_in
227 | )
228 |
229 | // 读入feature map
230 | when(Delay(conv_ctrl.io.shift, 1)) {
231 | for (i <- 0 until width_in + 2 * padding - 1) {
232 | raw_fm(i) := raw_fm(i + 1)
233 | }
234 | }.otherwise {
235 | // 这里还需要在考虑一下
236 | // padding是否会影响正常赋值
237 | for(i <- 0 until width_in) {
238 | raw_fm(i) := content(i)
239 | }
240 | }
241 |
242 | // 读入权重
243 | val weight_list = LoadWeight(file_path, weight_config, resolution)(layer_index)
244 | // val weight_peak : Int = log2Up(
245 | // weight_list.map(x => scala.math.abs(x)).max.toInt + 1
246 | // )
247 | // val weight_resolution : Int = Array(
248 | // log2Up(
249 | // (1 / (weight_list.map(
250 | // x => scala.math.abs(x)
251 | // ).max)).toInt
252 | // ) + resolution, resolution
253 | // ).max
254 |
255 | // 设置Layer
256 | val conv_layer = new ConvolutionLayer(
257 | width_out = width_out,
258 | channel_out = channel_out,
259 | peak = peak,
260 | resolution = resolution
261 | )
262 |
263 | // 权重
264 | val layer_rom = new WeightMem(
265 | weight_list,
266 | peak,
267 | resolution,
268 | channel_out
269 | )
270 | // println(channel_in , kernel_size)
271 | // println(weight_list(0) * (1 << resolution))
272 | // println(weight_list.size)
273 |
274 | layer_rom.io.address := Delay(conv_ctrl.io.weight_addr, 1)
275 | conv_layer.io.weight := layer_rom.io.weights_out
276 | conv_layer.io.clear := conv_ctrl.io.clear
277 |
278 | for (i <- 0 until width_out) {
279 | conv_layer.io.map(i) := raw_fm(i * stride)
280 | }
281 |
282 | // 连线
283 | // 等四个时钟周期
284 | // 直到数据处理完毕
285 | io.valid_out := Delay(conv_ctrl.io.valid, 4, init = False)
286 | io.data_out := conv_layer.io.output
287 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/ConvolutionLayer.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 定义卷积层的类
6 |
7 | class ConvolutionLayer(
8 | peak : Int = 5,
9 | resolution: Int = 10,
10 | channel_out: Int,
11 | width_out: Int
12 | ) extends Component {
13 | val io = new Bundle {
14 | val clear = in Bool
15 | val weight = in (
16 | Vec (SFix( peak exp, -resolution exp), channel_out)
17 | )
18 | val map = in (
19 | Vec (SFix( peak exp, -resolution exp), width_out)
20 | )
21 | val output = out (Vec(
22 | Vec (SFix( peak exp, -resolution exp), width_out)
23 | , channel_out))
24 | }
25 |
26 | val res = Vec(
27 | Vec(Reg(SFix( (peak * 2) exp, -resolution exp))
28 | init(0), width_out),
29 | channel_out)
30 | val output = Vec(
31 | Vec(Reg(SFix( (peak) exp, -resolution exp))
32 | init(0), width_out),
33 | channel_out)
34 |
35 | // 卷积运算
36 | for (c <- 0 until channel_out) {
37 | for (w <- 0 until width_out) {
38 | res(c)(w) := (io.map(w) * io.weight(c)).truncated
39 | }
40 | }
41 |
42 | // clear 接口
43 | when (Delay (io.clear, 3)) {
44 | for (c <- 0 until channel_out) {
45 | for (w <- 0 until width_out) {
46 | output(c)(w) := res(c)(w).truncated
47 | }
48 | }
49 | }.otherwise {
50 | for (c <- 0 until channel_out) {
51 | for (w <- 0 until width_out) {
52 | output(c)(w) := (output(c)(w) + res(c)(w)).truncated
53 | }
54 | }
55 | }
56 |
57 | io.output := output
58 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/FeatureMap.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | import spinal.sim._
6 | import spinal.core.sim._
7 |
8 | // 伴随对象
9 | object FeatureMap {
10 | def apply(
11 | input : FeatureMap,
12 | layer_add : Int
13 | ) : FeatureMap = {
14 | val map = FeatureMap (
15 | input.peak,
16 | input.resolution,
17 | input.height,
18 | input.width,
19 | input.channel,
20 | input.layer + layer_add,
21 | input.file_path,
22 | input.weight_config
23 | )
24 | map
25 | }
26 | }
27 |
28 | // 定义特征图的类
29 | case class FeatureMap(
30 | // 定点数的精度
31 | peak : Int = 5,
32 | resolution: Int = 10,
33 | // 图片的大小
34 | height: Int,
35 | width : Int,
36 | channel : Int,
37 | // 层编号
38 | // 用于从权重列表中取相应的权重
39 | // 注意: 池化层没有权重
40 | layer : Int,
41 | file_path : String,
42 | weight_config : List[List[Int]]
43 | ) extends Bundle {
44 | // 特征图中的各个点
45 | val points = (Flow(
46 | Vec (SFix( peak exp, -resolution exp), width)
47 | )) simPublic()
48 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/GlobalFunction.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 | import spinal.sim._
5 | import spinal.core.sim._
6 | import java.io.{File, FileInputStream}
7 |
8 |
9 | // 定义一些需要用到的全局函数
10 |
11 | // 计算给定参数的卷积层/池化层的维度计数器
12 | // 用于获取下一步应该读的FeatureMap和Weight的地址
13 | object MakeCnt {
14 | def judge (idx : Int) : Int = {
15 | if (idx == 0)
16 | return 2
17 | else
18 | return 1
19 | }
20 |
21 | def apply (start : Bool, input : List[Int]) : List[UInt] = {
22 | val cnt = input.map(x =>
23 | Reg(UInt(log2Up(x) bits)) init(0)
24 | )
25 |
26 | val num = input.zipWithIndex.map{
27 | case (value, idx) =>
28 | (if (value > 1)
29 | (value, idx)
30 | else
31 | null)
32 | }.filter(_ != null)
33 |
34 | val res = Reg(Bool)
35 | res := num.zipWithIndex.map{
36 | case ((value1, value2), idx) =>
37 | (cnt(value2) === (
38 | value1 - (judge(idx)))
39 | )
40 | }.reduce(_ && _)
41 |
42 | val enable = Reg(Bool) init(False)
43 | when (start) {
44 | enable := True
45 | }.elsewhen(res){
46 | enable := False
47 | }
48 |
49 | input.zipWithIndex.map{
50 | case (value, idx) => (
51 | if (value > 1) {
52 | when ((
53 | List(
54 | if(idx > 1)
55 | True
56 | else
57 | enable, True) :::
58 | ((0 until idx).map{
59 | case x => cnt(x) === input(x) - 1
60 | }).toList).reduce(_ && _)) {
61 | when(cnt(idx) < value - 1) {
62 | cnt(idx) := cnt(idx) + 1
63 | }.otherwise {
64 | cnt(idx) := 0
65 | }
66 | }
67 | }
68 | )
69 | }
70 | cnt
71 | }
72 | }
73 |
74 | // 载入权重
75 | object LoadWeight {
76 | // 过滤掉溢出值
77 | def filter_neg(num : Int) : Int = {
78 | if (num < 0)
79 | return num + 256
80 | else
81 | return num
82 | }
83 |
84 | // 将字节表示的值转为Int
85 | def convert(wb : Array[Byte], i : Int) : Int = {
86 | val b1 = wb(4 * i)
87 | val b2 = wb(4 * i + 1)
88 | val b3 = wb(4 * i + 2)
89 | val b4 = wb(4 * i + 3)
90 | return (
91 | b4.toInt * 256 * 256 * 256 +
92 | filter_neg(b3.toInt) * 256 * 256 +
93 | filter_neg(b2.toInt) * 256 +
94 | filter_neg(b1.toInt)
95 | )
96 | }
97 |
98 | def apply(
99 | file_path : String,
100 | weight_config : List[List[Int]],
101 | resolution : Int
102 | ):
103 | List[Array[Double]] = {
104 | val file_open = new File(file_path)
105 | val file_stream = new FileInputStream(file_open)
106 | val weights_in_bytes = new Array[Byte] (file_open.length.toInt)
107 |
108 | // read
109 | file_stream.read(weights_in_bytes)
110 | file_stream.close()
111 |
112 | // load
113 | // 将字节数据转换为Double权重值
114 | var i = 0 // 起始下标
115 | val base = (1 << resolution) // 扩大的倍数
116 | val weights = weight_config.map{x =>
117 | if(x.length == 1) {
118 | (0 until x(0)).map{y =>
119 | val ret = convert(weights_in_bytes, i).toDouble / base
120 | i = i + 1
121 | ret}.toArray
122 | }else {
123 | val w = (0 until x(0)).map{y =>
124 | val ret = convert(weights_in_bytes, i).toDouble / base
125 | i = i + 1
126 | ret}.toArray
127 | val b = (0 until x(0)).map{y =>
128 | val ret = convert(weights_in_bytes, i).toDouble / base
129 | i = i + 1
130 | ret}.toArray
131 | val mean = (0 until x(0)).map{y =>
132 | val ret = convert(weights_in_bytes, i).toDouble / base
133 | i = i + 1
134 | ret}.toArray
135 | val varX = (0 until x(0)).map{y =>
136 | var ret = convert(weights_in_bytes, i).toDouble / base
137 | i = i + 1
138 | if(ret == 0)
139 | ret = 100 // 避免除零
140 | ret}.toArray
141 | i = i + 1
142 | val weight = (0 until x(0)).map{y =>
143 | val ret = w(y) / scala.math.sqrt(varX(y))
144 | ret}.toList
145 | val bias = (0 until x(0)).map{y =>
146 | val ret = (b(y) - w(y) * mean(y) / scala.math.sqrt(varX(y)))
147 | ret}.toList
148 | (weight ++ bias).toArray
149 | }
150 | }
151 | weights
152 | }
153 | }
154 |
155 | // 从神经网络的最后一层中找到值最大的一个维度
156 | // 将该维度作为label的输出
157 | object SearchMax {
158 | def apply(input : Flow[Vec[SFix]], sig : SFix, sig2 : UInt) : Flow[UInt] = {
159 | val lower_bound = -(1 << (input.payload(0).asBits.getWidth - 1))
160 | val max_idx = Reg(UInt(log2Up(10) bits)) init(0) simPublic
161 | val max_val = Reg(SFix(11 exp, -20 exp)) init(-1) simPublic()
162 | sig := max_val
163 | val cnt = Reg(UInt(log2Up(10) bits)) init(9)
164 | val last_cnt = Reg(UInt(log2Up(10) bits)) init(9)
165 | max_val.raw.init(lower_bound)
166 | // 输出流
167 | val output = Flow(UInt(log2Up(10) bits))
168 |
169 | // 更新最大值
170 | last_cnt := cnt
171 | sig2 := cnt - last_cnt
172 | when (input.valid) {
173 | when (cnt === 9) {
174 | max_val.raw := input.payload(0).raw
175 | max_idx := 0
176 | cnt := 0
177 | }.otherwise {
178 | when(input.payload(0) > max_val) {
179 | max_val.raw := input.payload(0).raw
180 | max_idx := cnt + 1
181 | }
182 | cnt := cnt + 1
183 | }
184 | }
185 |
186 | // output
187 | output.payload := max_idx
188 | when (last_cnt === 8 && cnt === 9) {
189 | output.valid := True
190 | }.otherwise {
191 | output.valid := False
192 | }
193 | output
194 | }
195 | }
196 |
197 | object LoadCifar10 {
198 | def apply(
199 | resolution : Int
200 | ):(Array[Array[Array[Array[Double]]]], Array[Int]) = {
201 | // 图片数据集
202 | val images = Array.ofDim[Double](10000, 3, 32, 32) // 10000张图片, 大小3*32*32
203 | val labels = new Array[Int](10000)
204 |
205 | // 打开文件
206 | val file = new File("./data/test_batch.bin")
207 | val file_stream = new FileInputStream(file)
208 | val bytes = new Array[Byte](file.length.toInt)
209 | file_stream.read(bytes)
210 |
211 | // 读取标签和图片
212 | for(k <- 0 until 10000) {
213 | labels(k) = bytes(k * 3073).toInt
214 | }
215 | // 归一化因子
216 | for(k <- 0 until 10000) {
217 | for(i <- 0 until 3) {
218 | for(j <- 0 until 32) {
219 | for(m <- 0 until 32) {
220 | val t = k * 3073 + i * 32 * 32 + j * 32 + m + 1
221 | if(bytes(t) < 0) {
222 | images(k)(i)(j)(m) = 256 + bytes(t).toInt.toDouble
223 | }else {
224 | images(k)(i)(j)(m) = bytes(t).toInt.toDouble
225 | }
226 | // 直接读图片
227 | images(k)(i)(j)(m) = images(k)(i)(j)(m).toInt
228 | }
229 | }
230 | }
231 | }
232 |
233 | file_stream.close()
234 | (images , labels)
235 | }
236 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/LayerCtrl.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 定义神经网络层的控制类 (池化层和卷积层)
6 | // 主要负责读写等的控制逻辑
7 |
8 | class LayerCtrl(
9 | channel_in: Int,
10 | height_in: Int,
11 | height_out: Int,
12 | kernel_size : Int,
13 | stride : Int,
14 | padding : Int,
15 | group : Int = 1
16 | ) extends Component {
17 | val io = new Bundle {
18 | val start = in Bool
19 | val clear = out Bool
20 | val shift = out Bool
21 | val valid = out Bool
22 | // 输入地址(feature map)与权重地址
23 | val fm_addr = out UInt (
24 | log2Up(channel_in * (height_in + 2 * padding)) bits
25 | )
26 | val weight_addr = out UInt (
27 | log2Up(channel_in * kernel_size * kernel_size) bits
28 | )
29 | }
30 |
31 | // 获取计数器
32 | val cnt_list = MakeCnt(
33 | io.start,
34 | List(
35 | kernel_size,
36 | channel_in / group,
37 | kernel_size,
38 | 1,
39 | height_out,
40 | group // 默认Group为1
41 | )
42 | )
43 |
44 | val fm_addr = Reg(UInt(
45 | log2Up(channel_in * (height_in + 2 * padding))bits
46 | )) init(channel_in * padding)
47 |
48 | val group_mult = (
49 | if (group == 1)
50 | U(0, 0 bits)
51 | else
52 | cnt_list(5) * (channel_in / group)
53 | )
54 |
55 | if (height_out > 1) {
56 | fm_addr := cnt_list(1) + group_mult + (cnt_list(2) * channel_in)(Array((cnt_list(2)*channel_in).getWidth,log2Up((height_in + 2*padding) * channel_in)).min - 1 downto 0) + (cnt_list(4)* channel_in * stride)(log2Up((height_in + 2*padding) * channel_in) - 1 downto 0)
57 | } else {
58 | fm_addr := cnt_list(1) + group_mult + (cnt_list(2) * channel_in)(log2Up(height_in * channel_in) - 1 downto 0)
59 | }
60 |
61 | val weight_addr = Reg(UInt(
62 | log2Up(channel_in * kernel_size * kernel_size) bits
63 | )) init(0)
64 |
65 | weight_addr := (((cnt_list(1) + group_mult) * kernel_size * kernel_size)(log2Up(channel_in*kernel_size*kernel_size) - 1 downto 0) + cnt_list(2) * kernel_size + cnt_list(0))
66 |
67 | val clear = Reg(Bool) init(False)
68 | val shift = Reg(Bool) init(False)
69 | val valid = Reg(Bool) init(False)
70 |
71 | when(
72 | cnt_list.apply(0) === 0 &&
73 | cnt_list.apply(1) === 0 &&
74 | cnt_list.apply(2) === 0
75 | ) {
76 | clear := True
77 | }.otherwise {
78 | clear := False
79 | }
80 | when (cnt_list.apply(0) > 0) {
81 | shift := True
82 | }.otherwise {
83 | shift := False
84 | }
85 | when(
86 | cnt_list.apply(0) === kernel_size - 1 &&
87 | cnt_list.apply(1) === channel_in / group - 1 &&
88 | cnt_list.apply(2) === kernel_size - 1
89 | ) {
90 | valid := True
91 | }.otherwise {
92 | valid := False
93 | }
94 |
95 | io.fm_addr := fm_addr
96 | io.weight_addr := weight_addr
97 | io.clear := clear
98 | io.shift := shift
99 | io.valid := valid
100 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/MyTopLevel.scala:
--------------------------------------------------------------------------------
1 | /*
2 | * SpinalHDL
3 | * Copyright (c) Dolu, All rights reserved.
4 | *
5 | * This library is free software; you can redistribute it and/or
6 | * modify it under the terms of the GNU Lesser General Public
7 | * License as published by the Free Software Foundation; either
8 | * version 3.0 of the License, or (at your option) any later version.
9 | *
10 | * This library is distributed in the hope that it will be useful,
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 | * Lesser General Public License for more details.
14 | *
15 | * You should have received a copy of the GNU Lesser General Public
16 | * License along with this library.
17 | */
18 |
19 | package mylib
20 |
21 | import spinal.core._
22 | import spinal.lib._
23 |
24 |
25 | //Generate the MyTopLevel's Verilog
26 | object MyTopLevelVerilog {
27 | def main(args: Array[String]) {
28 | SpinalVerilog(new ClassificationNet(11, 20))
29 | }
30 | }
31 |
32 | //Generate the MyTopLevel's VHDL
33 | object MyTopLevelVhdl {
34 | def main(args: Array[String]) {
35 | SpinalVhdl(new ClassificationNet(11, 20))
36 | }
37 | }
38 |
39 |
40 | //Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere
41 | object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC))
42 |
43 | //Generate the MyTopLevel's Verilog using the above custom configuration.
44 | object MyTopLevelVerilogWithCustomConfig {
45 | def main(args: Array[String]) {
46 | MySpinalConfig.generateVerilog(new ClassificationNet(11, 20))
47 | }
48 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/MyTopLevelSim.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 |
3 | import spinal.core._
4 | import spinal.lib._
5 | import spinal.sim._
6 | import spinal.core.sim._
7 | import java.io._
8 |
9 |
10 | //MyTopLevel's testbench
11 | object MyTopLevelSim {
12 | // debug输出文件
13 | val writer_1 = new PrintWriter(new File("./output/input.txt" ))
14 | val writer_2 = new PrintWriter(new File("./output/layer2.txt" ))
15 | val writer_3 = new PrintWriter(new File("./output/layer3.txt" ))
16 | val writer_4 = new PrintWriter(new File("./output/display.txt" ))
17 |
18 | // 测试入口
19 | def main(args : Array[String]) {
20 | // 测试用的精度
21 | val peak = 11
22 | val resolution = 20
23 |
24 | val (images_mat, labels) = LoadCifar10(resolution)
25 | var delay = 20000
26 | // 总输出与正确输出
27 | var tot_out = 0
28 | var correct_out = 0
29 | SimConfig.doSim(new ClassificationNet(peak, resolution)){dut => //.withWave
30 | //Fork a process to generate the reset and the clock on the dut
31 | dut.clockDomain.forkStimulus(period = 10)
32 | for(idx <- 0 until 50000000) {
33 | if(idx % delay > 2 && idx % delay <= 2 + 4 * 32 * 3) {
34 | dut.io.input.valid #= true
35 | for(i <- 0 until 8) {
36 | dut.io.input.payload(i) #= (images_mat(idx / delay)
37 | ((idx % delay - 3) % 12 / 4)
38 | ((idx % delay - 3) / 12)
39 | (i + 8 * ((idx % delay - 3) % 4))
40 | ).toInt
41 | }
42 | }else {
43 | dut.io.input.valid #= false
44 | for(i <- 0 until 8) {
45 | dut.io.input.payload(i) #= 0
46 | }
47 | }
48 | dut.clockDomain.waitRisingEdge()
49 |
50 | // debug
51 | // 注意:type cast不要在sim类中做
52 | // 需要在main类做,例如asSInt
53 | val base = (1 << resolution)
54 |
55 | if(dut.inp.points.valid.toBoolean) {
56 | for(i <- 0 until 32) {
57 | writer_1.write(dut.plot1(i).toInt.toDouble / base + ",")
58 | }
59 | writer_1.write("\n")
60 | }
61 | if(dut.l2.points.valid.toBoolean) {
62 | for(i <- 0 until 14) {
63 | writer_2.write(dut.plot2(i).toInt.toDouble / base + ",")
64 | }
65 | writer_2.write("\n")
66 | }
67 | if(dut.l3.points.valid.toBoolean) {
68 | for(i <- 0 until 1) {
69 | writer_3.write(dut.plot3(i).toInt.toDouble / base + ",")
70 | }
71 | writer_3.write("\n")
72 | }
73 | if(dut.io.layer1_rgb.valid.toBoolean) {
74 | for(i <- 0 until 14) {
75 | writer_4.write(dut.plot4(i).toLong + ",")
76 | }
77 | writer_4.write("\n")
78 | }
79 |
80 | // 统计输出结果
81 | if(dut.io.ans.valid.toBoolean == true) {
82 | // println(dut.io.ans.payload.toLong)
83 | // println(dut.io.cnt_in.toLong)
84 | if(labels(tot_out) == dut.io.ans.payload.toLong) {
85 | correct_out = correct_out + 1
86 | }
87 | tot_out = tot_out + 1
88 | }
89 | if(idx % (delay * 5) == 0) {
90 | println(correct_out + ";" + tot_out)
91 | }
92 | }
93 | }
94 | // 输出分类结果
95 | println(correct_out + ";" + tot_out)
96 | // 关闭文件
97 | writer_1.close()
98 | writer_2.close()
99 | writer_3.close()
100 | writer_4.close()
101 | }
102 | }
103 |
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/Net.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 |
3 | import spinal.core._
4 | import spinal.lib._
5 | import spinal.sim._
6 | import spinal.core.sim._
7 |
8 | case class NetConfig() {
9 | var weight_table = List[List[Int]]()
10 | }
11 |
12 | trait Net {
13 | def conv2d(
14 | x : NetConfig,
15 | channel_in : Int,
16 | channel_out : Int,
17 | kernel_size : Int,
18 | stride : Int = 1,
19 | padding : Int = 0,
20 | bias: Boolean = true
21 | ): NetConfig = {
22 | x.weight_table = x.weight_table :+
23 | List((channel_in * channel_out * kernel_size * kernel_size))
24 | x
25 | }
26 | def relu(x : NetConfig): NetConfig = {
27 | x
28 | }
29 | def avgpool(x : NetConfig, kernel_size : Int, stride : Int = 1): NetConfig = {
30 | x
31 | }
32 | }
33 |
34 | case class mynet() extends Net {
35 | var x = NetConfig()
36 | x = conv2d(x, 3, 4, 5, 2, 0)
37 | x = relu(x)
38 | x = avgpool(x, 10, 10)
39 | x = conv2d(x, 4, 10, 1, 1, 0)
40 | }
41 |
42 | class ClassificationNet(
43 | // 全局的精度参数
44 | peak : Int = 5,
45 | resolution : Int = 10
46 | ) extends Component {
47 | val io = new Bundle {
48 | // 神经网络的输入
49 | // 1个时钟周期接受8个 8 位数
50 | val input = in (Flow(Vec(UInt(8 bits), 8)))
51 |
52 | // 隐藏层输出
53 | // 注意:红绿蓝三通道的值完全相等
54 | // 因此只需要一个接口即可
55 | // 宽度为14
56 | val layer1_rgb = out (Flow(Vec(UInt(8 bits), 14)))
57 |
58 | // 神经网络的分类结果,一共十个类别
59 | // 由一个4位数来标志
60 | val ans = out (Flow(UInt(4 bits)))
61 |
62 | // 收到了多少数据
63 | val cnt_in = out(UInt(9 bits))
64 | }
65 |
66 | // 接受图片的输入
67 | val layer1_in = Vec(Reg(SFix(peak exp, -resolution exp)) init(0), 32)
68 | // debug
69 | val cnt_in = Reg(UInt(9 bits)) init(0)
70 | io.cnt_in := cnt_in
71 | when(io.input.valid) {
72 | for(i <- 0 until 8) {
73 | layer1_in(i + 24).raw := (((io.input.payload(i).intoSInt - 255 + io.input.payload(i).intoSInt) * (1 << resolution)) / 255).resized
74 | }
75 | for(i <- 0 until 24) {
76 | layer1_in(i) := layer1_in(i+8)
77 | }
78 | cnt_in := cnt_in + 1
79 | }
80 | val cnt = Reg(UInt(2 bits)) init(0)
81 | when(io.input.valid) {
82 | when(cnt < 3) {
83 | cnt := cnt + 1
84 | }.otherwise {
85 | cnt := 0
86 | }
87 | }.otherwise {
88 | cnt := 0
89 | }
90 |
91 | val inp = FeatureMap(peak,resolution,32,32,3,0, "./data/weight.bin", mynet().x.weight_table)
92 | inp.points.valid := Delay(cnt === 3,1,init = False)
93 | inp.points.payload := layer1_in
94 |
95 | // 网络结构
96 | val l1 = Convolution2d(inp, 3, 4, 5, 2, 0, False, peak, resolution)
97 | val l2 = Relu(l1)
98 | val l3 = AvgPool2d(l2, 10, 10, 0, peak, resolution)
99 | val l4 = Convolution2d(l3, 4, 10, 1, 1, 0, False, peak, resolution)
100 | // 测试信号
101 | val sig = Reg(SFix(peak exp, -resolution exp)) simPublic()
102 | val sig2 = Reg(UInt(log2Up(10) bits)) simPublic()
103 | val plot_sig = sig.asBits.asSInt simPublic()
104 | // 输出结果
105 | val s = SearchMax
106 | val ans = s.apply(l4.points, sig, sig2) simPublic()
107 |
108 | // debug
109 | val plot1 = Vec(inp.points.payload.map(x => x.asBits.asSInt).toList) simPublic
110 | val plot2 = Vec(l2.points.payload.map(x => x.asBits.asSInt).toList) simPublic
111 | val plot3 = Vec(l3.points.payload.map(x => x.asBits.asSInt).toList) simPublic
112 | val plot4 = Vec(io.layer1_rgb.payload.map(x => x).toList) simPublic
113 |
114 | // 输出连线
115 | // 中间层
116 | // [0, 5]对应灰度值[0, 255]
117 | // RGB三个通道的值都等于灰度值
118 | io.layer1_rgb.payload := Vec(l2.points.payload.map{x =>
119 | val ret = (x.asBits.asSInt * 51 / (1 << resolution)).asUInt;
120 | when (x > 5)
121 | {
122 | ret := 255
123 | }
124 | ret(7 downto 0)
125 | }.toList)
126 | // 设置valid
127 | io.layer1_rgb.valid := l2.points.valid
128 | // val cnt1 = Reg(UInt(log2Up(180) bits)) init(0)
129 | // when(l2.points.valid) {
130 | // when(cnt1 < 14) {
131 | // cnt1 := cnt1 + 1
132 | // io.layer1_rgb.valid := True
133 | // }.elsewhen(cnt1 < 139) {
134 | // cnt1 := cnt1 + 1
135 | // io.layer1_rgb.valid := False
136 | // }.otherwise{
137 | // cnt1 := 0
138 | // io.layer1_rgb.valid := False
139 | // }
140 | // }.otherwise {
141 | // io.layer1_rgb.valid := False
142 | // }
143 |
144 | // 结果输出
145 | io.ans := ans
146 | }
147 |
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/Relu.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 伴随对象
6 | object Relu {
7 | def apply(input : FeatureMap) : FeatureMap = {
8 | val map = FeatureMap(input, 0)
9 | // 新建Relu层
10 | val layer = new Relu(
11 | input.peak,
12 | input.resolution,
13 | input.width
14 | )
15 | layer.io.input := input.points
16 | map.points := layer.io.output
17 | map
18 | }
19 | }
20 |
21 | // 定义Relu函数的类
22 |
23 | class Relu(
24 | peak : Int = 5,
25 | resolution: Int = 10,
26 | width: Int
27 | ) extends Component {
28 | val io = new Bundle {
29 | val input = in (Flow(
30 | Vec (SFix( peak exp, -resolution exp), width)
31 | ))
32 | val output = out (Flow(
33 | Vec (SFix( peak exp, -resolution exp), width)
34 | ))
35 | }
36 |
37 | val res = RegFlow(
38 | Vec (SFix( peak exp, -resolution exp), width)
39 | )
40 |
41 | // Relu函数的定义
42 | for (i <- 0 until width) {
43 | when (io.input.payload(i) >= 0) {
44 | res.payload(i) := io.input.payload(i)
45 | }.otherwise{
46 | res.payload(i) := 0
47 | }
48 | }
49 |
50 | res.valid := io.input.valid
51 | io.output := res
52 | }
--------------------------------------------------------------------------------
/spinalPro/src/main/scala/mylib/WeightMem.scala:
--------------------------------------------------------------------------------
1 | package mylib
2 | import spinal.core._
3 | import spinal.lib._
4 |
5 | // 定义存储权重的容器
6 |
7 | class WeightMem (
8 | weights : Array[Double],
9 | peak : Int = 5,
10 | resolution: Int = 10,
11 | channel_out : Int
12 | ) extends Component {
13 |
14 | // 计算存储深度
15 | val depth = weights.length / channel_out;
16 |
17 | val io = new Bundle {
18 | val address = in UInt ( log2Up(depth) bits )
19 | val weights_out = out (Vec(
20 | SFix( peak exp, -resolution exp), channel_out))
21 | }
22 |
23 | // 生成权重表
24 | def getWeightsTable = for(i <- 0 until depth) yield {
25 | Vec((0 until channel_out).map{x =>
26 | val ret = SFix(peak exp, -resolution exp)
27 | ret := weights(depth * (x + i/(depth)*(channel_out)) + (i % (depth)))
28 | ret
29 | })
30 | }
31 |
32 | // 将权重表写入ROM中
33 | val ROM = Mem(Vec(
34 | SFix( peak exp, -resolution exp), channel_out),
35 | initialContent = getWeightsTable
36 | )
37 |
38 | // 输出
39 | io.weights_out := ROM.readSync(io.address)
40 | }
--------------------------------------------------------------------------------
/spinalPro/task.md:
--------------------------------------------------------------------------------
1 | # 待完成的任务
2 |
3 | - 配置仿真环境,参考spinalHDL的官方文档 √
4 |
5 | - 确定归一化的方式 √
6 |
7 | - 规定读入读出的接口,并且书写相应的文档 √
8 |
9 | - 搞一个远程仓库 √
10 |
11 | - debug,输出其他层康康 精度问题 √
12 |
13 | 正确率: 389;1000
14 |
--------------------------------------------------------------------------------
/spinalPro/verilog/ClassificationNet.v_toplevel_convolutionBlock_2_core_layer_rom_ROM.bin:
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32 | 00000000000010110000100011010011000000000000001101111001111110011111111111110111010100101111110100000000000001111101010001000110
33 | 00000000000000110001010010001110000000000000010000010010010010011111111111111100011011111010011100000000000000110011000001110011
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50 | 11111111111011011000000100110011000000000000111110001010001001000000000000001001101110000011001100000000000011010001011100100100
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55 | 00000000000001101000101110010000000000000000011100101101011100110000000000000100010100001100100011111111111110110110111101111010
56 | 00000000000000010001111110001100000000000000001011111111001000111111111111111110100010001111010000000000000010001101100001100000
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59 | 11111111111111001000010001010100000000000000100000001011001001010000000000000101100001110100100011111111111110010000101110110111
60 | 00000000000000110010000110000011000000000000101101011001110110110000000000000100100110000110001111111111111101111011010010101011
61 | 00000000000000110001101010000000111111111111101100001011011010000000000000000000000001011001100000000000000011110111111000101100
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64 | 11111111111111000111011100011100111111111111111011111000001101110000000000001000000010010010001111111111111100101100100111010011
65 | 00000000000000110001011010000011000000000000010111100101110100000000000000001001101111101010011111111111111100011110101001111001
66 | 00000000000000001011000010010110111111111111100000101000011011011111111111111111000101010001100000000000000010010100011100011101
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68 | 11111111111110101000111101010011111111111111011010111101100111110000000000000010100001011001100111111111111111101010011110110001
69 | 00000000000000001110110010101111111111111111110001000110000001000000000000000110011101011011101111111111111100101000010001001011
70 | 00000000000001100001010010100011111111111111111011101110111101000000000000000111001100110110001011111111111101100001111000001111
71 | 00000000000000101110111101111100000000000000010010001001001110010000000000000001000001010000100111111111111111001001101100111100
72 | 00000000000000011010001111100000000000000000100100000111100000000000000000000000101100100111000011111111111110100000000101100011
73 | 00000000000000000100000100000111000000000000100000001101011011000000000000000110101001001110000111111111111100001001111011111010
74 | 00000000000011000101000000100011000000000000101111101001011011100000000000001100111110001000110011111111111100010110010010110111
75 | 00000000000011001001101001100111000000000001000000111011001110000000000000001111110110111010100111111111111110000001110100011101
76 |
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/spinalPro/verilog/ClassificationNet.v_toplevel_convolutionBlock_3_core_fmRAM.bin:
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1 | 00000000000000000000000000000000
2 | 00000000000000000000000000000000
3 | 00000000000000000000000000000000
4 | 00000000000000000000000000000000
5 | 00000000000000000000000000000000
6 | 00000000000000000000000000000000
7 | 00000000000000000000000000000000
8 | 00000000000000000000000000000000
9 |
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/spinalPro/verilog/ClassificationNet.v_toplevel_convolutionBlock_3_core_layer_rom_ROM.bin:
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3 | 00000000000010011011001110101101000000000001100010110011101010111111111111110111001111100100101111111111111100011101000010011111111111111101010100010001110001100000000000000101111010011011001011111111111000110111000001111010000000000000111110000111100010100000000000001010101001010010101100000000000111010110000110000101
4 | 00000000001001111110010100000011000000000001111101111110100100000000000000000001100001010001110011111111111011100011000001001101111111111110111000111011101010101111111111100111110111010011111111111111111100010111010001100100111111111101100100000100001011000000000000101110010001011001101000000000000010000100101001110000
5 |
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11 | 00000000000110011100110011011000111111111111101011001010001000011111111111111110111111010100011100000000000010100010110011101110
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70 | 00000000000001100001010010100011111111111111111011101110111101000000000000000111001100110110001011111111111101100001111000001111
71 | 00000000000000101110111101111100000000000000010010001001001110010000000000000001000001010000100111111111111111001001101100111100
72 | 00000000000000011010001111100000000000000000100100000111100000000000000000000000101100100111000011111111111110100000000101100011
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75 | 00000000000011001001101001100111000000000001000000111011001110000000000000001111110110111010100111111111111110000001110100011101
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/src/ClassificationNet.v_toplevel_convolutionBlock_3_core_fmRAM.bin:
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/src/ClassificationNet.v_toplevel_convolutionBlock_3_core_layer_rom_ROM.bin:
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/src/dir_parser.sv:
--------------------------------------------------------------------------------
1 | module dir_parser(
2 | input logic clk, rst_n,
3 | input logic rvalid,
4 | input logic [ 4:0] raddr,
5 | input logic [ 7:0] rdata,
6 |
7 | output logic fready,
8 | //output logic [31:0] file_cluster, file_size,
9 | output logic [ 7:0] fnamelen,
10 | output logic [ 7:0] fname [52],
11 | output logic [15:0] fcluster,
12 | output logic [31:0] fsize
13 | );
14 |
15 | initial begin fready=1'b0; fnamelen=8'h0; fcluster=16'h0; fsize=0; for(int i=0;i<52;i++)begin file_name[i]=8'h0; fname[i]=8'h0; end end
16 |
17 | logic isshort=1'b0, islongok=1'b0, islong=1'b0, longvalid=1'b0;
18 | logic [ 5:0] longno = 6'h0;
19 | logic [ 7:0] lastchar = 8'h0;
20 | logic [ 7:0] fdtnamelen=8'h0, sdtnamelen=8'h0;
21 | logic [ 7:0] file_namelen = 8'h0;
22 | logic [ 7:0] file_name [52];
23 | logic [15:0] file_first_cluster = 16'h0;
24 | logic [31:0] file_size = 0;
25 |
26 | wire [15:0] unicode = {rdata, lastchar};
27 |
28 | always @ (posedge clk or posedge rst_n) begin
29 | if(rst_n) begin
30 | fready=1'b0; fnamelen=8'h0; file_namelen=8'h0;
31 | for(int i=0;i<52;i++) begin file_name[i]=8'h0; fname[i]=8'h0; end
32 | fcluster=16'h0; fsize=0;
33 |
34 | {isshort, islongok, islong, longvalid} = 4'b0000;
35 | longno = 6'h0;
36 | lastchar = 8'h0;
37 | fdtnamelen = 8'h0; sdtnamelen=8'h0;
38 | file_first_cluster=16'h0; file_size=0;
39 | end else begin
40 | fready=1'b0; fnamelen=8'h0;
41 | for(int i=0;i<52;i++) fname[i]=8'h0;
42 | fcluster=16'h0; fsize=0;
43 |
44 | if(rvalid) begin
45 | case(raddr)
46 | 5'h1A : file_first_cluster[ 0+:8] = rdata;
47 | 5'h1B : file_first_cluster[ 8+:8] = rdata;
48 | 5'h1C : file_size[ 0+:8] = rdata;
49 | 5'h1D : file_size[ 8+:8] = rdata;
50 | 5'h1E : file_size[16+:8] = rdata;
51 | 5'h1F : file_size[24+:8] = rdata;
52 | endcase
53 |
54 | if(raddr==5'h0) begin
55 | {islongok, isshort} = 2'b00;
56 | fdtnamelen = 8'h0; sdtnamelen=8'h0;
57 |
58 | if(rdata!=8'hE5 && rdata!=8'h2E && rdata!=8'h00) begin
59 | if(islong && longno==6'h1)
60 | islongok = 1'b1;
61 | else
62 | isshort = 1'b1;
63 | end
64 |
65 | if(rdata[7]==1'b0 && ~islongok) begin
66 | if(rdata[6]) begin
67 | {islong,longvalid} = 2'b11;
68 | longno = rdata[5:0];
69 | end else if(islong) begin
70 | if(longno>6'h1 && (rdata[5:0]+6'h1==longno) ) begin
71 | islong = 1'b1;
72 | longno = rdata[5:0];
73 | end else begin
74 | islong = 1'b0;
75 | end
76 | end else
77 | islong = 1'b0;
78 | end else
79 | islong = 1'b0;
80 | end else if(raddr==5'hB) begin
81 | if(rdata!=8'h0F)
82 | islong = 1'b0;
83 | if(rdata!=8'h20)
84 | {isshort, islongok} = 2'b00;
85 | end else if(raddr==5'h1F) begin
86 | if(islongok && longvalid || isshort) begin
87 | fready = 1'b1;
88 | fnamelen = file_namelen;
89 | for(int i=0;i<52;i++) fname[i] = (i5'h0&&raddr<5'hB || raddr>=5'hE&&raddr<5'h1A || raddr>=5'h1C)begin
97 | if(raddr<5'hB ? raddr[0] : ~raddr[0]) begin
98 | lastchar = rdata;
99 | fdtnamelen++;
100 | end else begin
101 | if(unicode==16'h0000) begin
102 | file_namelen = fdtnamelen-8'd1 + (longno-8'd1)*8'd13;
103 | end else if(unicode!=16'hFFFF) begin
104 | if(unicode[15:8]==8'h0) begin
105 | file_name[fdtnamelen-8'd1+(longno-8'd1)*8'd13] = (unicode[7:0]>="a" && unicode[7:0]<="z") ? unicode[7:0]&8'b11011111 : unicode[7:0];
106 | end else begin
107 | longvalid = 1'b0;
108 | end
109 | end
110 | end
111 | end
112 | end
113 |
114 | if(isshort) begin
115 | if(raddr<5'h8) begin
116 | if(rdata!=8'h20) begin
117 | file_name[sdtnamelen] = rdata;
118 | sdtnamelen++;
119 | end
120 | end else if(raddr<5'hB) begin
121 | if(raddr==5'h8) begin
122 | file_name[sdtnamelen] = ".";
123 | sdtnamelen++;
124 | end
125 | if(rdata!=8'h20) begin
126 | file_name[sdtnamelen] = rdata;
127 | sdtnamelen++;
128 | end
129 | end else if(raddr==5'hB) begin
130 | file_namelen = sdtnamelen;
131 | end
132 | end
133 |
134 | end
135 | end
136 | end
137 |
138 |
139 | endmodule
--------------------------------------------------------------------------------
/src/dpy_scan.v:
--------------------------------------------------------------------------------
1 | module dpy_decode (
2 | input wire [3: 0] x,
3 | output reg [6: 0] z
4 | );
5 |
6 | always @(*)
7 | case (x)
8 | 4'b0000 : z = 7'b0111111;
9 | 4'b0001 : z = 7'b0000110;
10 | 4'b0010 : z = 7'b1011011;
11 | 4'b0011 : z = 7'b1001111;
12 | 4'b0100 : z = 7'b1100110;
13 | 4'b0101 : z = 7'b1101101;
14 | 4'b0110 : z = 7'b1111101;
15 | 4'b0111 : z = 7'b0000111;
16 | 4'b1000 : z = 7'b1111111;
17 | 4'b1001 : z = 7'b1101111;
18 | 4'b1010 : z = 7'b1110111;
19 | 4'b1011 : z = 7'b1111100;
20 | 4'b1100 : z = 7'b0111001;
21 | 4'b1101 : z = 7'b1011110;
22 | 4'b1110 : z = 7'b1111001;
23 | 4'b1111 : z = 7'b1110001;
24 | endcase
25 |
26 | endmodule
27 |
28 |
29 | module dpy_scan #(
30 | parameter SCAN_INTERVAL = 10_000
31 | )(
32 | input wire clk,
33 | input wire [31: 0] number, // 32-bit binary number to display
34 | input wire [7: 0] dp, // each bit represents to a dot
35 |
36 | output wire [7: 0] digit, // output to circuit
37 | output wire [7: 0] segment // output to circuit
38 | );
39 |
40 | reg [2: 0] scan_digit;
41 | wire [3: 0] scan_number;
42 |
43 | // scan current digit
44 | reg [31: 0] counter;
45 | always @(posedge clk) begin
46 | counter <= counter + 32'b1;
47 | if (counter == SCAN_INTERVAL) begin
48 | counter <= 'd0;
49 | scan_digit <= scan_digit + 'd1;
50 | end
51 | end
52 |
53 | assign scan_number = number[4 * scan_digit +: 4];
54 |
55 | // decode scanned number
56 | dpy_decode decode (
57 | .x (scan_number),
58 | .z (segment[6:0])
59 | );
60 |
61 | assign segment[7] = dp[scan_digit];
62 |
63 | // scan digit output
64 | assign digit = 1'b1 << scan_digit;
65 |
66 |
67 | endmodule
68 |
--------------------------------------------------------------------------------
/src/ram30728.sv:
--------------------------------------------------------------------------------
1 | module ram30728(
2 | input logic clk, rst_n,
3 | input logic wreq,
4 | input logic [7:0] wchar,
5 | output logic outvaid,
6 | output logic [7:0] outnum[7:0],
7 | output logic finish,
8 | input logic [11:0]raddr,
9 | output logic [23:0]rdata
10 | );
11 |
12 | reg [7:0]regbyte[3071:0];
13 | integer j;
14 | logic [9:0]numofblock;
15 | logic [11:0] add;
16 |
17 |
18 | initial
19 | begin
20 | add=0;
21 | finish=0;
22 | end
23 |
24 | always @(*)
25 | begin
26 | if(raddr<1024)begin
27 | rdata = {regbyte[raddr],regbyte[raddr+12'd1024],regbyte[raddr+12'd2048]};
28 | end
29 | else begin rdata=24'd0;end
30 | end
31 |
32 |
33 | always @(posedge clk or posedge rst_n)
34 | begin
35 | if(rst_n)begin
36 | for(j=0;j<3072;j=j+1)
37 | regbyte[j]<=8'b00000000;
38 | add<=0;
39 | numofblock<=0;
40 | finish<=0;
41 | end
42 | else begin
43 | if(finish==1)begin
44 | if(numofblock < 384)begin
45 | for(j=0;j<8;j=j+1)
46 | outnum[j]<=regbyte[j+numofblock*8];
47 | numofblock <= numofblock+1;
48 | outvaid<=1;
49 | end
50 | else begin
51 | numofblock <= numofblock;
52 | outvaid<=0;
53 | end
54 |
55 |
56 | end else begin
57 | if(wreq)
58 | begin
59 | if(add<3072)
60 | begin
61 | regbyte[add]<= wchar;
62 | add <=add+1;
63 | finish <= 0;
64 | end
65 | else begin
66 | add<=add;
67 | finish <= 1;
68 | end
69 | end
70 | end
71 | end
72 | end
73 |
74 |
75 | endmodule
--------------------------------------------------------------------------------
/src/ram_for_layer.sv:
--------------------------------------------------------------------------------
1 | module ram_for_layer(
2 | input logic vaild,
3 | input logic [11:0]raddr,
4 | input logic [7:0]indata[13:0],
5 | input logic clk,
6 | input logic rst_n,
7 | output logic [7:0]rdata,
8 | output logic finish
9 | );
10 |
11 | reg [7:0] savedata[195:0] ;
12 |
13 | integer j;
14 | always@ (*)
15 | begin
16 | if(raddr<195)
17 | rdata = savedata[raddr];
18 | else
19 | rdata=8'd0;
20 | end
21 |
22 | reg [4:0]state;
23 | initial
24 | begin
25 | state = 0;
26 |
27 | end
28 | always @ (posedge clk or posedge rst_n)
29 | begin
30 | if (rst_n)
31 | begin
32 | finish<=0;
33 | for (j=0; j<=195;j=j+1) begin
34 | savedata[j] <= 8'b00000000;
35 | end
36 | state <=0;
37 | end
38 | else
39 | begin
40 | if(vaild==1)begin
41 | case(state)
42 | 0:
43 | begin
44 | for (j=0; j<=13;j=j+1) begin
45 | savedata[j] <= indata[j];
46 | end
47 | state<= state +1;
48 | finish<=0;
49 | end
50 | 1:
51 | begin
52 | for (j=0; j<=13;j=j+1) begin
53 | savedata[j+14] <= indata[j];
54 | end
55 | state<= state +1;
56 | finish<=0;
57 | end
58 | 2:
59 | begin
60 | for (j=0; j<=13;j=j+1) begin
61 | savedata[j+28] <= indata[j];
62 | end
63 | state<= state +1;
64 | finish<=0;
65 | end
66 | 3:
67 | begin
68 | for (j=0; j<=13;j=j+1) begin
69 | savedata[j+42] <= indata[j];
70 | end
71 | state<= state +1;
72 | finish<=0;
73 | end
74 | 4:
75 | begin
76 | for (j=0; j<=13;j=j+1) begin
77 | savedata[j+56] <= indata[j];
78 | end
79 | state<= state +1;
80 | finish<=0;
81 | end
82 | 5:
83 | begin
84 | for (j=0; j<=13;j=j+1) begin
85 | savedata[j+70] <= indata[j];
86 | end
87 | state<= state +1;
88 | finish<=0;
89 | end
90 | 6:
91 | begin
92 | for (j=0; j<=13;j=j+1) begin
93 | savedata[j+84] <= indata[j];
94 | end
95 | state<= state +1;
96 | finish<=0;
97 | end
98 | 7:
99 | begin
100 | for (j=0; j<=13;j=j+1) begin
101 | savedata[j+98] <= indata[j];
102 | end
103 | state<= state +1;
104 | finish<=0;
105 | end
106 | 8:
107 | begin
108 | for (j=0; j<=13;j=j+1) begin
109 | savedata[j+112] <= indata[j];
110 | end
111 | state<= state +1;
112 | finish<=0;
113 | end
114 | 9:
115 | begin
116 | for (j=0; j<=13;j=j+1) begin
117 | savedata[j+126] <= indata[j];
118 | end
119 | state<= state +1;
120 | finish<=0;
121 | end
122 | 10:
123 | begin
124 | for (j=0; j<=13;j=j+1) begin
125 | savedata[j+140] <= indata[j];
126 | end
127 | state<= state +1;
128 | finish<=0;
129 | end
130 | 11:
131 | begin
132 | for (j=0; j<=13;j=j+1) begin
133 | savedata[j+154] <= indata[j];
134 | end
135 | state<= state +1;
136 | finish<=0;
137 | end
138 | 12:
139 | begin
140 | for (j=0; j<=13;j=j+1) begin
141 | savedata[j+168] <= indata[j];
142 | end
143 | state<= state +1;
144 | finish<=0;
145 | end
146 | 13:
147 | begin
148 | for (j=0; j<=13;j=j+1) begin
149 | savedata[j+182] <= indata[j];
150 | end
151 | state<= state +1;
152 | finish<=0;
153 | end
154 |
155 | 14:
156 | begin
157 | state<= 14;
158 | finish<=1;
159 | end
160 |
161 | endcase
162 | end
163 | end
164 |
165 | end
166 |
167 |
168 | endmodule
169 |
170 |
171 |
--------------------------------------------------------------------------------
/src/sd_spi_sector_reader.sv:
--------------------------------------------------------------------------------
1 | // this module can automatically initialize the sdcard and handle the read sector command from user
2 | module sd_spi_sector_reader #(
3 | parameter SPI_CLK_DIV = 50 // SD spi_clk freq = clk freq/(2*SPI_CLK_DIV)
4 | // modify SPI_CLK_DIV to change the SPI speed
5 | // for example, when clk=50MHz, SPI_CLK_DIV=50,then spi_clk=50MHz/(2*50)=500kHz
6 | // 500kHz is a typical SPI speed for SDcard
7 | )(
8 | input logic clk, rst_n,
9 | // user read sector command interface
10 | input logic start,
11 | input logic [31:0] sector_no,
12 | output logic done,
13 | // data readout
14 | output logic rvalid,
15 | output logic [ 8:0] raddr, // raddr from 0 to 511, because the sector size is 512
16 | output logic [ 7:0] rdata,
17 | // card status (for debug)
18 | output logic [ 1:0] sdcardtype,
19 | output logic [ 3:0] sdcardstate,
20 | // SDcard spi interface
21 | output logic spi_csn, spi_clk, spi_mosi,
22 | input logic spi_miso
23 | );
24 |
25 | localparam CMD8_VALID_RES = 8'hAA;
26 |
27 | enum logic [1:0] {NONE, SDv1, SDv2, SDHCv2} cardtype = NONE;
28 | enum logic [3:0] {RESET, CMD0, CMD8, CMD1, CMD8FAILED, ACMD41, CMD58, CMD16, IDLE, READING} cardstate = RESET;
29 |
30 | reg spistart=0;
31 | wire spidone;
32 | reg [47:0] cmd=0, acmd=0;
33 | wire [47:0] cmdres;
34 | reg [ 7:0] waitcycle=0, precycle=0, startcycle=0, cmdrcycle=0, acmdcycle=0, midcycle=0, recycle=0;
35 | wire [ 7:0] cmdrsp, acmdrsp, rwrsp;
36 | reg [31:0] target_sector = 0;
37 |
38 | initial done = 1'b0;
39 | initial begin rvalid = 1'b0; raddr = 9'h0; rdata = 8'h0; end
40 | assign sdcardtype = cardtype;
41 | assign sdcardstate = cardstate;
42 |
43 | always @ (posedge clk or posedge rst_n) begin
44 | if(rst_n) begin
45 | done = 1'b0;
46 | spistart=0; cmd=48'h00_00000000_00; acmd=48'h00_00000000_00; waitcycle= 64; precycle= 0; startcycle=0; cmdrcycle=0; acmdcycle=0; midcycle= 0;recycle=0;
47 | cardtype = NONE;
48 | cardstate = RESET;
49 | target_sector = 0;
50 | end else begin
51 | done = 1'b0;
52 | spistart=0; cmd=48'h00_00000000_00; acmd=48'h00_00000000_00; waitcycle= 64; precycle= 0; startcycle=0; cmdrcycle=0; acmdcycle=0; midcycle= 0;recycle=0;
53 | if(spidone) begin
54 | case(cardstate)
55 | RESET : cardstate = CMD0;
56 | CMD0 : if(cmdrsp==8'h01) cardstate = CMD8;
57 | CMD1 : if(cmdrsp==8'h00) cardstate = IDLE;
58 | CMD8 : if(cmdrsp==8'h01) begin // SDv2.0
59 | if(cmdres[0+:8]==CMD8_VALID_RES) // CMD8 success
60 | cardstate = ACMD41;
61 | else
62 | cardstate = CMD8FAILED;
63 | end else begin // SDv1
64 | cardstate = CMD1; // TODO: SDv1
65 | cardtype = SDv1;
66 | end
67 | ACMD41: if(cmdrsp==8'h01 && acmdrsp==8'h00) cardstate = CMD58;
68 | CMD58 : if(~cmdrsp[7]) begin // SDv2.0
69 | if((cmdres[3*8+:8]&8'hC0)==8'hC0) // done initialize, SDHCv2
70 | cardtype = SDHCv2;
71 | else // done initialize, SDv2
72 | cardtype = SDv2;
73 | cardstate = CMD16;
74 | end
75 | CMD16 : if(cmdrsp==8'h00) cardstate = IDLE;
76 | IDLE : if( (~cmdrsp[7]) && rwrsp==8'hFE) begin cardstate = READING; end
77 | READING : if( (~cmdrsp[7]) && rwrsp==8'hFE) begin cardstate = IDLE ; done=1'b1; end
78 | endcase
79 | end else begin
80 | case(cardstate)
81 | RESET : cardstate = CMD0;
82 | CMD0 : begin spistart=1; cmd=48'h40_00000000_95 ; acmd=48'h00_00000000_00; waitcycle=255; precycle=20; startcycle=0; cmdrcycle=0; acmdcycle=0; midcycle= 0;recycle=0; end
83 | CMD1 : begin spistart=1; cmd=48'h41_00000000_ff ; acmd=48'h00_00000000_00; waitcycle= 16; precycle= 0; startcycle=0; cmdrcycle=0; acmdcycle=0; midcycle= 0;recycle=0; end
84 | CMD8 : begin spistart=1; cmd=48'h48_000001aa_87 ; acmd=48'h00_00000000_00; waitcycle= 16; precycle= 0; startcycle=1; cmdrcycle=4; acmdcycle=0; midcycle= 0;recycle=0; end
85 | ACMD41 : begin spistart=1; cmd=48'h77_00000000_FF ; acmd=48'h69_40000000_FF; waitcycle= 16; precycle= 0; startcycle=1; cmdrcycle=0; acmdcycle=6; midcycle= 0;recycle=0; end
86 | CMD58 : begin spistart=1; cmd=48'h7a_00000000_FF ; acmd=48'h00_00000000_00; waitcycle= 16; precycle= 0; startcycle=1; cmdrcycle=4; acmdcycle=0; midcycle= 0;recycle=0; end
87 | CMD16 : begin spistart=1; cmd=48'h50_00000200_FF ; acmd=48'h00_00000000_00; waitcycle= 16; precycle= 0; startcycle=1; cmdrcycle=2; acmdcycle=0; midcycle= 0;recycle=0; end
88 | IDLE : if(start) begin
89 | target_sector = (cardtype==SDHCv2) ? sector_no : ( (cardtype==SDv2 || cardtype==SDv1) ? sector_no*512 : 0 );
90 | spistart=1; cmd={8'h51,target_sector,8'hFF}; acmd=48'h00_00000000_00; waitcycle= 6; precycle= 0; startcycle=0; cmdrcycle=4; acmdcycle=0; midcycle=99;recycle=2;
91 | end
92 | READING: begin
93 | spistart=1; cmd={8'h51,target_sector,8'hFF}; acmd=48'h00_00000000_00; waitcycle= 6; precycle= 0; startcycle=0; cmdrcycle=4; acmdcycle=0; midcycle=99;recycle=2;
94 | end
95 | endcase
96 | end
97 | end
98 | end
99 |
100 | logic rvalid_session;
101 | logic [15:0] rindex_session;
102 | logic [ 7:0] rdata_session;
103 |
104 | always @ (posedge clk or posedge rst_n) begin
105 | if(rst_n) begin
106 | rvalid = 1'b0;
107 | raddr = 9'h0;
108 | rdata = 8'h0;
109 | end else begin
110 | if(cardstate==READING && rvalid_session && (rindex_session>=16'd2 && rindex_session<16'd514)) begin
111 | rvalid = 1'b1;
112 | raddr = 16'd513 - rindex_session;
113 | rdata = rdata_session;
114 | end else begin
115 | rvalid = 1'b0;
116 | raddr = 9'h0;
117 | rdata = 8'h0;
118 | end
119 | end
120 | end
121 |
122 | spi_session spi_session_for_sd_reader (
123 | .clk ( clk ),
124 | .rst_n ( rst_n ),
125 | // control interface
126 | .start ( spistart ),
127 | .done ( spidone ),
128 | .clkdiv ( SPI_CLK_DIV ),
129 | .cmd ( cmd ),
130 | .acmd ( acmd ),
131 | // control interface (cycle time control parameters)
132 | .waitcycle ( waitcycle ),
133 | .precycle ( precycle ),
134 | .startcycle ( startcycle ),
135 | .cmdcycle ( 6 ),
136 | .cmdrcycle ( cmdrcycle ),
137 | .acmdcycle ( acmdcycle ),
138 | .acmdrcycle ( 0 ),
139 | .midcycle ( midcycle ),
140 | .stopcycle ( 255 ),
141 | .recycle ( recycle ),
142 | // cmd result interface
143 | .cmdrsp ( cmdrsp ),
144 | .acmdrsp ( acmdrsp ),
145 | .rwrsp ( rwrsp ),
146 | .cmdres ( cmdres ),
147 | // data readout
148 | .rvalid ( rvalid_session ),
149 | .rindex ( rindex_session ),
150 | .rdata ( rdata_session ),
151 |
152 | .csn ( spi_csn ),
153 | .sck ( spi_clk ),
154 | .mosi ( spi_mosi ),
155 | .miso ( spi_miso )
156 | );
157 |
158 | endmodule
--------------------------------------------------------------------------------
/src/spi_session.sv:
--------------------------------------------------------------------------------
1 | module spi_session(
2 | input logic clk, rst_n,
3 | // user command interface
4 | input logic start,
5 | output logic done,
6 | input logic [31:0] clkdiv, // next command spi sck = clk / (2*(clkdiv+1)), for example clk=50MHz, clkdiv=124, sck=50MHz/(2*125) = 200kHz
7 | input logic [47:0] cmd, acmd,
8 | input logic [ 7:0] waitcycle, precycle, startcycle, cmdcycle, cmdrcycle, acmdcycle, acmdrcycle, midcycle, stopcycle, recycle, // dummy clock byte cycles
9 |
10 | output logic [ 7:0] cmdrsp, acmdrsp, rwrsp,
11 | output logic [47:0] cmdres, acmdres,
12 |
13 | output logic rvalid,
14 | output logic [15:0] rindex,
15 | output logic [ 7:0] rdata,
16 | // spi interface
17 | output logic csn, sck, mosi,
18 | input logic miso
19 | );
20 |
21 | initial {cmdrsp, acmdrsp, rwrsp} = 0;
22 | initial {cmdres, acmdres} = 0;
23 | initial {csn, sck, mosi} = 3'b111;
24 |
25 | logic start_last=1'b0;
26 | logic [31:0] clkdivreg=0, cyccnt=0;
27 | logic [ 2:0] bitcnt=3'b0;
28 | logic highlow=1'b0;
29 | logic byteend, bytestart;
30 | logic scken=1'b0, chipselect=1'b0;
31 | logic [ 7:0] wbyte=8'h0, rbyte=8'h0;
32 | logic [47:0] cmdr=0, acmdr=0;
33 | logic [ 7:0] waitc=8'h0, prec=8'h0, startc=8'h0, cmdc=8'h0, cmdrwait=8'h0, cmdrc=8'h0, acmdc=8'h0, acmdrwait=8'h0, acmdrc=8'h0, midc=8'h0, stopc=8'h0, rec=8'h0, lastc=8'h0;
34 | logic [15:0] rwc = 16'h0;
35 | logic iscmdr=1'b0, isacmdr=1'b0, iscmdres=1'b0, isacmdres=1'b0,ismidc=1'b0, isrwc=1'b0;
36 |
37 | assign byteend = (cyccnt==0) && ({bitcnt,highlow}==4'h0) ;
38 | assign bytestart = (cyccnt==1) && ({bitcnt,highlow}==4'h0) ;
39 |
40 | always @ (posedge clk or posedge rst_n)
41 | if(rst_n) begin
42 | cyccnt = 0;
43 | {bitcnt,highlow} = 3'h0;
44 | {csn, sck, mosi} = 3'b111;
45 | rbyte = 8'h0;
46 | end else begin
47 | if(~start) begin
48 | cyccnt = 0;
49 | {bitcnt,highlow} = 3'h0;
50 | {csn, sck, mosi} = 3'b111;
51 | rbyte = 8'h0;
52 | end else if(cyccnt0)?8'h20:8'h0,cmdrcycle,acmdcycle,(acmdcycle>0)?8'h20:8'h0,acmdrcycle,midcycle,(midcycle>0)?16'd514:16'd0,stopcycle,recycle,8'h2 };
96 | {iscmdr, isacmdr,iscmdres,isacmdres,ismidc,isrwc} = 0;
97 | {chipselect,scken,wbyte} = {2'b00, 8'hff};
98 | end else if(bytestart) begin
99 | if(waitc>0) begin
100 | waitc--;
101 | {chipselect,scken,wbyte} = {2'b00, 8'hff};
102 | end else if(prec>0) begin
103 | prec--;
104 | {chipselect,scken,wbyte} = {2'b01, 8'hff};
105 | end else if(startc>0) begin
106 | startc--;
107 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
108 | end else if(cmdc>0) begin
109 | cmdc--;
110 | {chipselect,scken,wbyte} = {2'b11, cmdr[cmdc*8+:8]};
111 | end else if(cmdrwait>0) begin iscmdr = 1'b1;
112 | cmdrwait--;
113 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
114 | end else if(cmdrc>0) begin iscmdres = 1'b1;
115 | cmdrc--;
116 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
117 | end else if(acmdc>0) begin
118 | acmdc--;
119 | {chipselect,scken,wbyte} = {2'b11, acmdr[acmdc*8+:8]};
120 | end else if(acmdrwait>0) begin isacmdr = 1'b1;
121 | acmdrwait--;
122 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
123 | end else if(acmdrc>0) begin isacmdres = 1'b1;
124 | acmdrc--;
125 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
126 | end else if(midc>0) begin ismidc = 1'b1;
127 | midc--;
128 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
129 | end else if(rwc>0) begin isrwc = 1'b1;
130 | rwc--;
131 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
132 | end else if(stopc>0) begin
133 | stopc--;
134 | {chipselect,scken,wbyte} = {2'b11, 8'hff};
135 | end else if(rec>0) begin
136 | rec--;
137 | {chipselect,scken,wbyte} = {2'b01, 8'hff};
138 | end else if(lastc>0) begin
139 | lastc--;
140 | {chipselect,scken,wbyte} = {2'b00, 8'hff};
141 | end else begin
142 | {chipselect,scken,wbyte} = {2'b00, 8'hff};
143 | end
144 | end else if(byteend) begin
145 | if(iscmdr && ~rbyte[7]) begin
146 | cmdrsp = rbyte;
147 | cmdrwait = 0;
148 | end
149 | if( iscmdres) cmdres[cmdrc*8+:8] = rbyte;
150 | if(isacmdr && ~rbyte[7]) begin
151 | acmdrsp = rbyte;
152 | acmdrwait = 0;
153 | end
154 | if(isacmdres) acmdres[acmdrc*8+:8] = rbyte;
155 | if(ismidc && rbyte==8'hFE) begin
156 | rwrsp = rbyte;
157 | midc = 0;
158 | end
159 | if(isrwc) begin
160 | {rvalid, rdata} = {1'b1, rbyte};
161 | rindex = rwc;
162 | end
163 | {iscmdr, isacmdr,iscmdres,isacmdres,ismidc,isrwc} = 0;
164 | end
165 | end
166 |
167 | assign done = start && start_last && (lastc==0);
168 |
169 | endmodule
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/src/vga.v:
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1 | `timescale 1ns / 1ps
2 | //
3 | // WIDTH: bits in register hdata & vdata
4 | // HSIZE: horizontal size of visible field
5 | // HFP: horizontal front of pulse
6 | // HSP: horizontal stop of pulse
7 | // HMAX: horizontal max size of value
8 | // VSIZE: vertical size of visible field
9 | // VFP: vertical front of pulse
10 | // VSP: vertical stop of pulse
11 | // VMAX: vertical max size of value
12 | // HSPP: horizontal synchro pulse polarity (0 - negative, 1 - positive)
13 | // VSPP: vertical synchro pulse polarity (0 - negative, 1 - positive)
14 | //
15 | module vga
16 | #(parameter WIDTH = 0, HSIZE = 0, HFP = 0, HSP = 0, HMAX = 0, VSIZE = 0, VFP = 0, VSP = 0, VMAX = 0, HSPP = 0, VSPP = 0)
17 | (
18 | input wire clk,
19 | output wire hsync,
20 | output wire vsync,
21 | output reg [WIDTH - 1:0] hdata,
22 | output reg [WIDTH - 1:0] vdata,
23 | output wire data_enable
24 | );
25 |
26 | // hdata
27 | always @ (posedge clk)
28 | begin
29 | if (hdata == (HMAX - 1))
30 | hdata <= 0;
31 | else
32 | hdata <= hdata + 1;
33 | end
34 |
35 | // vdata
36 | always @ (posedge clk)
37 | begin
38 | if (hdata == (HMAX - 1))
39 | begin
40 | if (vdata == (VMAX - 1))
41 | vdata <= 0;
42 | else
43 | vdata <= vdata + 1;
44 | end
45 | end
46 |
47 | // hsync & vsync & blank
48 | assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;
49 | assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;
50 | assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));
51 |
52 | endmodule
53 |
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/最终答辩.pptx:
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https://raw.githubusercontent.com/liuch00/fpga_cnn/377f77932bf8ad5b50aff3503a11ef17eed98966/最终答辩.pptx
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