├── AXI_TDC_IP └── component.xml ├── LICENSE ├── README.md ├── TDC ├── Hierarchy ├── sim │ ├── controlTb.vhd │ ├── counterTb.vhd │ └── encoderTb.vhd └── src │ ├── ip │ ├── axi_bram_ctrl_0.xci │ ├── axi_gpio_0.xci │ └── blk_mem_gen_0.xci │ └── vhdl │ ├── AXITDC.vhd │ ├── TDCchannel.vhd │ ├── adderTreeLegacy.vhd │ ├── control.vhd │ ├── counter.vhd │ ├── delayLine.vhd │ ├── encoder.vhd │ ├── risingEdgeDetector.vhd │ └── sync.vhd ├── TDCsystem ├── constraints │ ├── ports.xdc │ └── timing.xdc └── src │ ├── TDCsystem.bd │ ├── TDCsystem_wrapper.vhd │ └── testUnit.vhd ├── code ├── PLclock ├── TDCgui3.mlapp └── TDCserver2.c ├── figs ├── GUI │ ├── calTab.PNG │ └── measTab.PNG └── TDCsystem │ ├── 2ch_layout.PNG │ ├── AXI_TDC │ ├── AXITDC.PNG │ ├── AXITDC_IP.PNG │ ├── TDCcore │ │ ├── TDCcore.PNG │ │ ├── control │ │ │ └── controlFSM.PNG │ │ ├── delayLine │ │ │ ├── 1bubble.PNG │ │ │ ├── bubblefree.PNG │ │ │ ├── delayLine.PNG │ │ │ └── resetbubble.PNG │ │ └── encoder │ │ │ └── adderTree.PNG │ └── timestamp.PNG │ ├── TDCsystem.PNG │ └── addressEditor.PNG └── packages └── MyPkg.vhd /AXI_TDC_IP/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ljthink/zynq_tdc/HEAD/AXI_TDC_IP/component.xml -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ljthink/zynq_tdc/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ljthink/zynq_tdc/HEAD/README.md -------------------------------------------------------------------------------- /TDC/Hierarchy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ljthink/zynq_tdc/HEAD/TDC/Hierarchy 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