├── .gitignore ├── Flickerfreertf.cs ├── Flickerfreertf.resx ├── FrmLionAsm.Designer.cs ├── FrmLionAsm.cs ├── FrmLionAsm.resx ├── HelperClasses.cs ├── Lionasm.csproj ├── Lionasm.sln ├── Program.cs ├── Properties ├── AssemblyInfo.cs ├── Resources.Designer.cs ├── Resources.resx ├── Settings.Designer.cs └── Settings.settings ├── README.md ├── Utils.cs ├── aparser.cs ├── files ├── 3_to_8.bdf ├── 3_to_8.bsf ├── 74251_l.bdf ├── 74251_l.bsf ├── ALU_LA2.bdf ├── ALU_LA4.bdf ├── BOOT.bin ├── LPLL2.cmp ├── LPLL2.ppf ├── LPLL2.vhd ├── LionCPU16r.vhd ├── LionSystem.dpf ├── LionSystem.qpf ├── LionSystem.qsf ├── LionSystem.qws ├── LionSystem.sdc ├── LionSystem.vhd ├── Lpll2.qip ├── SPI.vhd ├── UART.vhd ├── XY_Disp.vhd ├── freq_basic.xlsx ├── lionrom.asm ├── lionrom.bin ├── lionrom.mif ├── liontinyb.asm ├── regs.bdf └── video_640x480_M.vhd └── javag ├── Astro4S.java ├── JGOptimizer.exe ├── cyggcc_s-seh-1.dll ├── cygstdc++-6.dll ├── cygwin1.dll ├── galax.bin ├── galaxian.java ├── java_grinder.exe ├── make.txt ├── net └── mikekohn │ └── java_grinder │ ├── JavaGrinder.jar │ ├── Lionsys.class │ └── Lionsys.java ├── pacman.bin └── pacman.java /.gitignore: -------------------------------------------------------------------------------- 1 | obj/ 2 | bin/ 3 | liontinyb.mif 4 | *.suo 5 | -------------------------------------------------------------------------------- /Flickerfreertf.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Windows.Forms; 3 | 4 | namespace Lion_assembler 5 | { 6 | /// 7 | /// Summary description for Flickerfreertf. 8 | /// 9 | public class Flickerfreertf : RichTextBox 10 | { 11 | const short WM_PAINT = 0x00f; 12 | public Flickerfreertf() 13 | { 14 | } 15 | 16 | public static bool _Paint = true; 17 | protected override void WndProc(ref System.Windows.Forms.Message m) 18 | { 19 | // Code courtesy of Mark Mihevc 20 | // sometimes we want to eat the paint message so we don't have to see all the 21 | // flicker from when we select the text to change the color. 22 | if (m.Msg == WM_PAINT) 23 | { 24 | if (_Paint) 25 | base.WndProc(ref m); // if we decided to paint this control, just call the RichTextBox WndProc 26 | else 27 | m.Result = IntPtr.Zero; // not painting, must set this to IntPtr.Zero if not painting otherwise serious problems. 28 | } 29 | else 30 | base.WndProc(ref m); // message other than WM_PAINT, jsut do what you normally do. 31 | 32 | } 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /Flickerfreertf.resx: -------------------------------------------------------------------------------- 1 |  2 | 3 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | text/microsoft-resx 110 | 111 | 112 | 2.0 113 | 114 | 115 | System.Resources.ResXResourceReader, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 116 | 117 | 118 | System.Resources.ResXResourceWriter, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 119 | 120 | -------------------------------------------------------------------------------- /FrmLionAsm.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Drawing; 3 | using System.Windows.Forms; 4 | using System.Drawing.Printing; 5 | using System.IO; 6 | using Lion_assembler; 7 | using System.Threading.Tasks; 8 | 9 | 10 | namespace Lion_assembler 11 | { 12 | public partial class frmLionAsm : Form 13 | { 14 | public string fname = "File.asm"; 15 | int fstart = 0; 16 | aparser par; 17 | Boolean exith, changed = false; 18 | const int un = 2; 19 | string[] oldtext = new string[un]; 20 | 21 | private void MakeColorSyntaxForAll() 22 | { 23 | // Store current cursor position 24 | exith = true; 25 | Flickerfreertf._Paint = false; 26 | int CurrentSelectionStart = fftxtSource.SelectionStart; 27 | int CurrentSelectionLength = fftxtSource.SelectionLength; 28 | int pos = 0; 29 | int pos2 = fftxtSource.Text.Length - 1; 30 | fftxtSource.SelectAll(); 31 | fftxtSource.SelectionColor = Color.Black; 32 | int l = pos; 33 | char ch; 34 | Color c; 35 | string ctok = string.Empty; 36 | string st = fftxtSource.Text.ToUpper(); 37 | while (l < pos2) 38 | { 39 | //if ("ABCDEFGHIJKLMNOPQRSTVUWXYZ01234567890_.".IndexOf(fftxtSource.Text.ToUpper()[l]) != -1) 40 | ch = st[l]; 41 | if (ch == '.' || ch == '.' || (ch >= 'A' && ch <= 'Z') || (ch >= '0' && ch <= '9')) 42 | { 43 | ctok = ctok + ch; 44 | l++; 45 | } 46 | else 47 | { 48 | //ctok = ctok.ToUpper(); 49 | if (st[l] == ';') 50 | { 51 | int ss = l; 52 | fftxtSource.SelectionStart = ss; 53 | l++; 54 | while (l < pos2 && st[l] != '\n') l++; 55 | fftxtSource.SelectionLength = l - ss; 56 | fftxtSource.SelectionColor = Color.Green; 57 | } else 58 | if (ctok != string.Empty) 59 | { 60 | if (par.colorList.ContainsKey(ctok)) 61 | { 62 | c = (Color)par.colorList[ctok]; 63 | fftxtSource.Select(l - ctok.Length, ctok.Length); 64 | fftxtSource.SelectionColor = c; 65 | } 66 | //else if (ctok.Length == 2 && ctok[0] == 'A' && ctok[1] > 47 && ctok[1] < 56) 67 | //{ 68 | // fftxtSource.Select(l - ctok.Length, ctok.Length); 69 | // fftxtSource.SelectionColor = Color.DarkViolet ; 70 | //} 71 | ctok = string.Empty; 72 | } else 73 | if (st[l] == '\'') 74 | { 75 | int ss = l; 76 | fftxtSource.SelectionStart = ss; 77 | l++; 78 | while (l < pos2 && st[l] != '\'' && st[l] != '\n') l++; 79 | fftxtSource.SelectionLength = l - ss+1; 80 | fftxtSource.SelectionColor = Color.DarkRed; 81 | } 82 | else 83 | if (st[l] == '\"') 84 | { 85 | int ss = l; 86 | fftxtSource.SelectionStart = ss; 87 | l++; 88 | while (l < pos2 && st[l] != '\"' && st[l] != '\n') l++; 89 | fftxtSource.SelectionLength = l - ss+1; 90 | fftxtSource.SelectionColor = Color.DarkRed; 91 | } 92 | l++; 93 | } 94 | } 95 | if (ctok != string.Empty) 96 | { 97 | if (par.colorList.ContainsKey(ctok)) 98 | { 99 | c = (Color)par.colorList[ctok]; 100 | fftxtSource.Select(l - ctok.Length, ctok.Length); 101 | fftxtSource.SelectionColor = c; 102 | } 103 | ctok = string.Empty; 104 | } 105 | // Restore Cursor 106 | if (CurrentSelectionStart >= 0) 107 | fftxtSource.Select(CurrentSelectionStart, 108 | CurrentSelectionLength); 109 | Flickerfreertf._Paint = true; 110 | exith = false; 111 | } 112 | 113 | public void MakeColorSyntaxForCurrentLine() 114 | { 115 | // Store current cursor position 116 | 117 | if (exith || string.IsNullOrEmpty(fftxtSource.Text)) return; 118 | Flickerfreertf._Paint = false; 119 | int CurrentSelectionStart = fftxtSource.SelectionStart; 120 | int CurrentSelectionLength = fftxtSource.SelectionLength; 121 | string sot = fftxtSource.Text.ToUpper(); 122 | // find start of line 123 | int pos = CurrentSelectionStart; 124 | 125 | while ((pos > 0) && (sot[pos - 1] != '\n')) 126 | pos--; 127 | ; 128 | // find end of line 129 | int pos2 = CurrentSelectionStart; 130 | while ((pos2 < sot.Length) && (sot[pos2] != '\n')) pos2++; 131 | fftxtSource.SelectionStart = pos; 132 | fftxtSource.SelectionLength = pos2 - pos; 133 | string st = sot.Substring(pos, pos2 - pos).TrimStart(); 134 | if (pos < sot.Length && st.StartsWith(";")) 135 | { 136 | fftxtSource.SelectionColor = Color.Green; 137 | Flickerfreertf._Paint = true; 138 | if (CurrentSelectionStart >= 0) 139 | fftxtSource.Select(CurrentSelectionStart, 140 | CurrentSelectionLength); 141 | return; 142 | } 143 | else fftxtSource.SelectionColor = Color.Black; 144 | int l = pos; 145 | Color c; 146 | char ch; 147 | string ctok = string.Empty; 148 | while (l < pos2) 149 | { 150 | //if ("ABCDEFGHIJKLMNOPQRSTVUWXYZ01234567890_.".IndexOf(fftxtSource.Text.ToUpper()[l]) != -1) 151 | ch = sot[l]; 152 | if (ch == '.' || ch == '.' || (ch >= 'A' && ch <= 'Z') || (ch >= '0' && ch <= '9')) 153 | { 154 | ctok = ctok + ch; 155 | l++; 156 | } 157 | else 158 | { 159 | //ctok = ctok.ToUpper(); 160 | if (sot[l] == ';') 161 | { 162 | int ss = l; 163 | fftxtSource.SelectionStart = ss; 164 | l++; 165 | while (l < pos2 && sot[l] != '\n') l++; 166 | fftxtSource.SelectionLength = l - ss; 167 | fftxtSource.SelectionColor = Color.Green; 168 | } 169 | else 170 | if (ctok != string.Empty) 171 | { 172 | if (par.colorList.ContainsKey(ctok)) 173 | { 174 | c = (Color)par.colorList[ctok]; 175 | fftxtSource.Select(l - ctok.Length, ctok.Length); 176 | fftxtSource.SelectionColor = c; 177 | } 178 | //else if (ctok.Length == 2 && ctok[0] == 'A' && ctok[1] > 47 && ctok[1] < 56) 179 | // { 180 | // fftxtSource.Select(l - ctok.Length, ctok.Length); 181 | // fftxtSource.SelectionColor = Color.DeepSkyBlue; 182 | // } 183 | ctok = string.Empty; 184 | } 185 | else 186 | if (sot[l] == '\'') 187 | { 188 | int ss = l; 189 | fftxtSource.SelectionStart = ss; 190 | l++; 191 | while (l < pos2 && sot[l] != '\'' && sot[l] != '\n') l++; 192 | fftxtSource.SelectionLength = l - ss+1; 193 | fftxtSource.SelectionColor = Color.DarkRed; 194 | } 195 | else 196 | if (sot[l] == '\"') 197 | { 198 | int ss = l; 199 | fftxtSource.SelectionStart = ss; 200 | l++; 201 | while (l < pos2 && sot[l] != '\"' && sot[l] != '\n') l++; 202 | fftxtSource.SelectionLength = l - ss+1; 203 | fftxtSource.SelectionColor = Color.DarkRed; 204 | } 205 | l++; 206 | } 207 | } 208 | if (ctok != string.Empty) 209 | { 210 | if (par.colorList.ContainsKey(ctok)) 211 | { 212 | c = (Color)par.colorList[ctok]; 213 | fftxtSource.Select(l - ctok.Length, ctok.Length); 214 | fftxtSource.SelectionColor = c; 215 | } 216 | ctok = string.Empty; 217 | } 218 | // Restore Cursor 219 | if (CurrentSelectionStart >= 0) 220 | fftxtSource.Select(CurrentSelectionStart, 221 | CurrentSelectionLength); 222 | Flickerfreertf._Paint = true; 223 | } 224 | 225 | public void goto_line(int st) 226 | { 227 | int l, i, le; 228 | l = 0; 229 | i = 0; 230 | le = fftxtSource.Text.Length; 231 | do 232 | { 233 | if (i < le) i = fftxtSource.Text.IndexOf("\n", i + 1); 234 | else i = -1; 235 | l++; 236 | } while (l < st && i != -1); 237 | if (i < le && l == st) 238 | { 239 | fftxtSource.SelectionStart = i + 1; 240 | fftxtSource.SelectionLength = 1; 241 | } 242 | } 243 | 244 | int find_line(int st) 245 | { 246 | int l, i, le; 247 | l = 0; 248 | i = 0; 249 | le = fftxtSource.Text.Length; 250 | do 251 | { 252 | if (i < le) i = fftxtSource.Text.IndexOf("\n", i + 1); 253 | else i = -1; 254 | l++; 255 | } while (i < st && i != -1); 256 | return l; 257 | } 258 | 259 | public void MarkLine(int l, Color c) 260 | { 261 | exith = true; 262 | Flickerfreertf._Paint = false; 263 | goto_line(l); 264 | int pos = fftxtSource.SelectionStart; 265 | while ((pos > 0) && (fftxtSource.Text[pos - 1] != '\n')) pos--; 266 | // find end of line 267 | int pos2 = fftxtSource.SelectionStart; 268 | while ((pos2 < fftxtSource.Text.Length) && (fftxtSource.Text[pos2] != '\n')) pos2++; 269 | fftxtSource.SelectionStart = pos; 270 | fftxtSource.SelectionLength = pos2 - pos; 271 | fftxtSource.SelectionColor = c; 272 | Flickerfreertf._Paint = true; 273 | exith = false; 274 | } 275 | 276 | public frmLionAsm(string[] args) 277 | { 278 | 279 | InitializeComponent(); 280 | 281 | if (args.Length > 0) 282 | { 283 | fname = args[0]; 284 | changed = true; 285 | if (args.Length > 0) 286 | { 287 | fname = args[0]; string line, bufs; 288 | fftxtSource.Text = string.Empty; 289 | bufs = string.Empty; 290 | string temp = string.Empty; 291 | Directory.SetCurrentDirectory(Path.GetDirectoryName(fname)); 292 | using (StreamReader sr = new StreamReader(fname, System.Text.Encoding.GetEncoding(1253))) 293 | { 294 | while ((line = sr.ReadLine()) != null) 295 | { 296 | temp = temp + line + "\r\n"; 297 | } 298 | bufs = temp.Substring(0, temp.Length - 2); 299 | } 300 | fftxtSource.Text = bufs; 301 | 302 | changed = true; 303 | } 304 | } 305 | } 306 | 307 | private void Lionasm_Load(object sender, EventArgs e) 308 | { 309 | par = new aparser(this); 310 | try 311 | { 312 | fftxtSource.SuspendLayout(); 313 | } 314 | catch { } 315 | MakeColorSyntaxForAll(); 316 | try 317 | { 318 | fftxtSource.ResumeLayout(); 319 | } 320 | catch 321 | { 322 | } 323 | changed = false; 324 | comboBox1.Text = "COM3"; 325 | } 326 | 327 | 328 | 329 | private void openToolStripMenuItem1_Click(object sender, EventArgs e) 330 | { 331 | DialogResult d; 332 | string line, bufs; 333 | DialogResult res; 334 | exith = true; 335 | if (changed) res = MessageBox.Show("Text has changed and not saved, are you sure", "Open", MessageBoxButtons.YesNo, MessageBoxIcon.Warning); 336 | else res = DialogResult.Yes; 337 | if (res == DialogResult.Yes) 338 | { 339 | openFileDialog1.FileName = fname; // Path.GetFileName(fname); 340 | d = openFileDialog1.ShowDialog(); 341 | if (d == DialogResult.OK) 342 | { 343 | fname = openFileDialog1.FileName; 344 | Directory.SetCurrentDirectory(Path.GetDirectoryName(fname)); 345 | fftxtSource.Text = string.Empty; 346 | bufs = string.Empty; 347 | changed = false; 348 | string temp = string.Empty; 349 | Cursor.Current = Cursors.WaitCursor; 350 | using (StreamReader sr = new StreamReader(fname, System.Text.Encoding.GetEncoding(1253))) 351 | { 352 | while ((line = sr.ReadLine()) != null) 353 | { 354 | temp = temp + line + "\r\n"; 355 | } 356 | bufs = temp.Substring(0, temp.Length - 2); 357 | //fftxtSource.Text = fftxtSource.Text.Replace("\t", " "); 358 | } 359 | fftxtSource.Text = bufs; 360 | if (frmLionAsm.ActiveForm.Text != null) frmLionAsm.ActiveForm.Text = "Lion Assembler - " + fname; 361 | // oldtext[0] = fftxtSource.Text; 362 | try 363 | { 364 | fftxtSource.SuspendLayout(); 365 | } 366 | catch { } 367 | MakeColorSyntaxForAll(); 368 | try 369 | { 370 | fftxtSource.ResumeLayout(); 371 | } 372 | catch 373 | { 374 | } 375 | 376 | Cursor.Current = Cursors.Default; 377 | } 378 | } 379 | exith = false; 380 | } 381 | 382 | 383 | 384 | private void source_TextChanged(object sender, EventArgs e) 385 | { 386 | if (fftxtSource.UndoActionName == "Typing") 387 | { 388 | //fftxtSource.Undo(); 389 | //int i; 390 | //for (i = un - 1; i > 0; i--) 391 | //{ 392 | // oldtext[i] = oldtext[i - 1]; 393 | //} 394 | //oldtext[0] = fftxtSource.Text; 395 | //fftxtSource.Redo(); 396 | changed = true; 397 | MakeColorSyntaxForCurrentLine(); 398 | //SLine=fftxtSource 399 | } 400 | 401 | } 402 | 403 | private void closeToolStripMenuItem_Click(object sender, EventArgs e) 404 | { 405 | //SAVE 406 | DialogResult d; 407 | saveFileDialog1.FileName = fname; // Path.GetFileName(fname); 408 | d = saveFileDialog1.ShowDialog(); 409 | if (d == DialogResult.OK) 410 | { 411 | fname = saveFileDialog1.FileName; 412 | using (StreamWriter sw = new StreamWriter(fname, false, System.Text.Encoding.GetEncoding(1253))) 413 | { 414 | foreach (string cs in fftxtSource.Lines) 415 | { 416 | sw.WriteLine(cs); 417 | } 418 | } 419 | //changed = false; 420 | frmLionAsm.ActiveForm.Text = "frmLionAsm - " + fname; 421 | changed = false; 422 | } 423 | } 424 | 425 | private void exitToolStripMenuItem_Click(object sender, EventArgs e) 426 | { 427 | DialogResult res; 428 | if (changed) res = MessageBox.Show("Text has changed and not saved, are you sure", "Open", MessageBoxButtons.YesNo, MessageBoxIcon.Warning); 429 | else res = DialogResult.Yes; 430 | if (res == DialogResult.Yes) 431 | { 432 | changed = false; 433 | this.Close(); 434 | } 435 | } 436 | 437 | private void undoToolStripMenuItem_Click(object sender, EventArgs e) 438 | { 439 | //if (oldtext[0] != null && oldtext[0].Trim() != string.Empty && oldtext[0] != fftxtSource.Text) 440 | //{ 441 | // exith = true; 442 | // Flickerfreertf._Paint = false; 443 | // int ss = fftxtSource.SelectionStart; 444 | // fftxtSource.Text = oldtext[0]; 445 | // int i; 446 | // for (i = 0; i < un - 1; i++) 447 | // { 448 | // oldtext[i] = oldtext[i + 1]; 449 | // } 450 | // if (ss < fftxtSource.Text.Length) fftxtSource.SelectionStart = ss; 451 | // Flickerfreertf._Paint = true; 452 | // exith = false; 453 | // MakeColorSyntaxForAll(); 454 | //} 455 | } 456 | 457 | private void buildObjectToolStripMenuItem_Click(object sender, EventArgs e) 458 | { 459 | par.parse(); 460 | } 461 | 462 | private void VHDL_TextChanged(object sender, EventArgs e) 463 | { 464 | 465 | } 466 | 467 | private void openToolStripMenuItem_Click(object sender, EventArgs e) 468 | { 469 | DialogResult res; 470 | if (changed) res = MessageBox.Show("Text has changed and not saved, are you sure", "NEW", MessageBoxButtons.YesNo, MessageBoxIcon.Warning); 471 | else res = DialogResult.Yes; 472 | if (res == DialogResult.Yes) 473 | { 474 | fftxtSource.Text = " ORG 8192 ; RAM start"; 475 | MakeColorSyntaxForAll(); 476 | changed = false; 477 | 478 | } 479 | } 480 | 481 | private void source_SelectionChanged(object sender, EventArgs e) 482 | { 483 | SLine.Text = "Line:" + Convert.ToString(fftxtSource.GetLineFromCharIndex(fftxtSource.SelectionStart) + 1); 484 | } 485 | 486 | private void statusStrip1_ItemClicked(object sender, ToolStripItemClickedEventArgs e) 487 | { 488 | 489 | } 490 | 491 | private void printToolStripMenuItem_Click(object sender, EventArgs e) 492 | { 493 | 494 | } 495 | 496 | private void printDocument1_PrintPage(object sender, PrintPageEventArgs e) 497 | { 498 | 499 | } 500 | 501 | private void toolStripMenuItem1_Click(object sender, EventArgs e) 502 | { 503 | 504 | } 505 | 506 | private void menuStrip1_ItemClicked(object sender, ToolStripItemClickedEventArgs e) 507 | { 508 | 509 | } 510 | 511 | private void findToolStripMenuItem_Click(object sender, EventArgs e) 512 | { 513 | 514 | fftxtSource.Find(string.Empty); 515 | } 516 | 517 | private void source_KeyPress(object sender, KeyPressEventArgs e) 518 | { 519 | 520 | } 521 | 522 | private void btnFind_Click(object sender, EventArgs e) 523 | { 524 | try 525 | { 526 | fftxtSource.SelectionStart = fftxtSource.Find(txtSearch.Text, fstart, fftxtSource.TextLength - 1, 0); 527 | fftxtSource.SelectionLength = txtSearch.Text.Length - 1; 528 | fstart = fftxtSource.SelectionStart + 1; 529 | fftxtSource.ScrollToCaret(); 530 | } 531 | catch 532 | { 533 | fftxtSource.SelectionStart = 0; 534 | fftxtSource.SelectionLength = 0; 535 | fftxtSource.ScrollToCaret(); 536 | fstart = 1; 537 | } 538 | } 539 | 540 | private void btnU_Click(object sender, EventArgs e) 541 | { 542 | if (txtSearch.CanUndo == true) 543 | { 544 | // Undo the last operation. 545 | txtSearch.Undo(); 546 | // Clear the undo buffer to prevent last action from being redone. 547 | txtSearch.ClearUndo(); 548 | } 549 | } 550 | 551 | private void btnR_Click(object sender, EventArgs e) 552 | { 553 | fftxtSource.Redo(); 554 | } 555 | 556 | private void txtSearch_TextChanged(object sender, EventArgs e) 557 | { 558 | 559 | } 560 | 561 | private void txtSearch_KeyPress(object sender, KeyPressEventArgs e) 562 | { 563 | if (e.KeyChar == 13) 564 | { 565 | try 566 | { 567 | fftxtSource.SelectionStart = fftxtSource.Find(txtSearch.Text, fstart, fftxtSource.TextLength - 1, 0); 568 | fftxtSource.SelectionLength = txtSearch.Text.Length - 1; 569 | fstart = fftxtSource.SelectionStart + 1; 570 | fftxtSource.ScrollToCaret(); 571 | } 572 | catch 573 | { 574 | fftxtSource.SelectionStart = 0; 575 | fftxtSource.SelectionLength = 0; 576 | fftxtSource.ScrollToCaret(); 577 | fstart = 1; 578 | } 579 | } 580 | } 581 | 582 | private void Lionasm_FormClosing(object sender, FormClosingEventArgs e) 583 | { 584 | DialogResult res; 585 | if (changed) res = MessageBox.Show("Text has changed and not saved, are you sure", "Open", MessageBoxButtons.YesNo, MessageBoxIcon.Warning); 586 | else res = DialogResult.Yes; 587 | if (res == DialogResult.No) 588 | { 589 | e.Cancel = true; 590 | } 591 | } 592 | 593 | private void btnCopy_Click(object sender, EventArgs e) 594 | { 595 | VHDL.SelectAll(); 596 | VHDL.Refresh(); 597 | VHDL.Copy(); 598 | } 599 | 600 | private void btnAssemble_Click(object sender, EventArgs e) 601 | { 602 | errorbox.Text = "*** Assembling ***"; 603 | errorbox.Refresh(); 604 | par.parse(); 605 | errorbox.Text += " *** End ***"; 606 | } 607 | 608 | private void btnPaint_Click(object sender, EventArgs e) 609 | { 610 | Cursor.Current = Cursors.WaitCursor; 611 | try 612 | { 613 | fftxtSource.SuspendLayout(); 614 | } 615 | catch { } 616 | 617 | MakeColorSyntaxForAll(); 618 | 619 | try 620 | { 621 | fftxtSource.ResumeLayout(); 622 | } 623 | catch 624 | { 625 | } 626 | Cursor.Current = Cursors.Default; 627 | } 628 | 629 | private void SSend_Click(object sender, EventArgs e) 630 | { 631 | BinaryReader br = null; 632 | byte[] bt = new byte[2]; 633 | try 634 | { 635 | 636 | br = new BinaryReader(new FileStream(Path.GetFileNameWithoutExtension(fname) + ".bin", FileMode.Open)); 637 | } 638 | catch (IOException ex) 639 | { 640 | errorbox.Text += "Can't open Binary File! \r\n"; 641 | errorbox.Text += ex.Message + "\r\n"; 642 | return; 643 | } 644 | try 645 | { 646 | serialPort1.Open(); 647 | } 648 | catch (IOException ex) 649 | { 650 | errorbox.Text += "Can't open Serial Port \r\n"; 651 | errorbox.Text += ex.Message + "\r\n"; 652 | return; 653 | } 654 | serialPort1.Write("GCODE BTOP+2,"+BinSize.Text); 655 | bt[0] = 13; serialPort1.Write(bt, 0, 1); 656 | for (int j = 0; j < 16; j++) for (int i = 0; i < 200000; i++) { int k = i * 3; } 657 | for (int j=0;j 2 | 3 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | text/microsoft-resx 110 | 111 | 112 | 2.0 113 | 114 | 115 | System.Resources.ResXResourceReader, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 116 | 117 | 118 | System.Resources.ResXResourceWriter, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 119 | 120 | 121 | 17, 17 122 | 123 | 124 | 126, 17 125 | 126 | 127 | 256, 17 128 | 129 | 130 | 384, 17 131 | 132 | 133 | 494, 17 134 | 135 | 136 | 625, 17 137 | 138 | 139 | 744, 17 140 | 141 | 142 | 36 143 | 144 | -------------------------------------------------------------------------------- /HelperClasses.cs: -------------------------------------------------------------------------------- 1 | using System.Collections.Generic; 2 | 3 | namespace Lion_assembler 4 | { 5 | public class DasmSymbol 6 | { 7 | public string Name; 8 | public string HexValue; 9 | public string BinaryValue; 10 | public uint DecimalValue; 11 | public bool isLabel; 12 | } 13 | 14 | public class DasmRecord 15 | { 16 | public List SymbolsList = new List(); 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /Lionasm.csproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | Debug 5 | x86 6 | 8.0.30703 7 | 2.0 8 | {8989947A-CE20-492B-B865-1CD5F1C9A257} 9 | WinExe 10 | Properties 11 | Lion_assembler 12 | Lionasm 13 | v4.0 14 | Client 15 | 512 16 | true 17 | http://localhost/Lionasm/ 18 | true 19 | Web 20 | true 21 | Foreground 22 | 7 23 | Days 24 | false 25 | false 26 | true 27 | 0 28 | 1.0.0.%2a 29 | false 30 | true 31 | 32 | 33 | x86 34 | true 35 | full 36 | false 37 | bin\Debug\ 38 | TRACE;DEBUG;LOG 39 | prompt 40 | 4 41 | false 42 | 43 | 44 | x86 45 | pdbonly 46 | true 47 | bin\Release\ 48 | TRACE 49 | prompt 50 | 4 51 | false 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | Code 68 | 69 | 70 | Component 71 | 72 | 73 | Form 74 | 75 | 76 | frmLionAsm.cs 77 | 78 | 79 | 80 | 81 | 82 | 83 | Flickerfreertf.cs 84 | Designer 85 | 86 | 87 | frmLionAsm.cs 88 | Designer 89 | 90 | 91 | ResXFileCodeGenerator 92 | Resources.Designer.cs 93 | Designer 94 | 95 | 96 | True 97 | Resources.resx 98 | True 99 | 100 | 101 | SettingsSingleFileGenerator 102 | Settings.Designer.cs 103 | 104 | 105 | True 106 | Settings.settings 107 | True 108 | 109 | 110 | 111 | 112 | False 113 | Microsoft .NET Framework 4 Client Profile %28x86 and x64%29 114 | true 115 | 116 | 117 | False 118 | .NET Framework 3.5 SP1 Client Profile 119 | false 120 | 121 | 122 | False 123 | .NET Framework 3.5 SP1 124 | false 125 | 126 | 127 | False 128 | Windows Installer 3.1 129 | true 130 | 131 | 132 | 133 | 140 | -------------------------------------------------------------------------------- /Lionasm.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio 2012 4 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Lionasm", "Lionasm.csproj", "{8989947A-CE20-492B-B865-1CD5F1C9A257}" 5 | EndProject 6 | Global 7 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 8 | Debug|x86 = Debug|x86 9 | Release|x86 = Release|x86 10 | EndGlobalSection 11 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 12 | {8989947A-CE20-492B-B865-1CD5F1C9A257}.Debug|x86.ActiveCfg = Debug|x86 13 | {8989947A-CE20-492B-B865-1CD5F1C9A257}.Debug|x86.Build.0 = Debug|x86 14 | {8989947A-CE20-492B-B865-1CD5F1C9A257}.Release|x86.ActiveCfg = Release|x86 15 | {8989947A-CE20-492B-B865-1CD5F1C9A257}.Release|x86.Build.0 = Release|x86 16 | EndGlobalSection 17 | GlobalSection(SolutionProperties) = preSolution 18 | HideSolutionNode = FALSE 19 | EndGlobalSection 20 | EndGlobal 21 | -------------------------------------------------------------------------------- /Program.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Windows.Forms; 5 | 6 | namespace Lion_assembler 7 | { 8 | static class Program 9 | { 10 | /// 11 | /// The main entry point for the application. 12 | /// 13 | [STAThread] 14 | static void Main(string[] args) 15 | { 16 | Application.EnableVisualStyles(); 17 | Application.SetCompatibleTextRenderingDefault(false); 18 | Application.Run(new frmLionAsm(args)); 19 | } 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("Leonasm")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("Audio")] 12 | [assembly: AssemblyProduct("Leonasm")] 13 | [assembly: AssemblyCopyright("Copyright © Th. Liontakis 2015")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("d8c82b67-8905-45db-9e3f-571b3e0a2830")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /Properties/Resources.Designer.cs: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // 3 | // This code was generated by a tool. 4 | // Runtime Version:4.0.30319.1022 5 | // 6 | // Changes to this file may cause incorrect behavior and will be lost if 7 | // the code is regenerated. 8 | // 9 | //------------------------------------------------------------------------------ 10 | 11 | namespace Lion_assembler.Properties { 12 | using System; 13 | 14 | 15 | /// 16 | /// A strongly-typed resource class, for looking up localized strings, etc. 17 | /// 18 | // This class was auto-generated by the StronglyTypedResourceBuilder 19 | // class via a tool like ResGen or Visual Studio. 20 | // To add or remove a member, edit your .ResX file then rerun ResGen 21 | // with the /str option, or rebuild your VS project. 22 | [global::System.CodeDom.Compiler.GeneratedCodeAttribute("System.Resources.Tools.StronglyTypedResourceBuilder", "4.0.0.0")] 23 | [global::System.Diagnostics.DebuggerNonUserCodeAttribute()] 24 | [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()] 25 | internal class Resources { 26 | 27 | private static global::System.Resources.ResourceManager resourceMan; 28 | 29 | private static global::System.Globalization.CultureInfo resourceCulture; 30 | 31 | [global::System.Diagnostics.CodeAnalysis.SuppressMessageAttribute("Microsoft.Performance", "CA1811:AvoidUncalledPrivateCode")] 32 | internal Resources() { 33 | } 34 | 35 | /// 36 | /// Returns the cached ResourceManager instance used by this class. 37 | /// 38 | [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)] 39 | internal static global::System.Resources.ResourceManager ResourceManager { 40 | get { 41 | if (object.ReferenceEquals(resourceMan, null)) { 42 | global::System.Resources.ResourceManager temp = new global::System.Resources.ResourceManager("Lion_assembler.Properties.Resources", typeof(Resources).Assembly); 43 | resourceMan = temp; 44 | } 45 | return resourceMan; 46 | } 47 | } 48 | 49 | /// 50 | /// Overrides the current thread's CurrentUICulture property for all 51 | /// resource lookups using this strongly typed resource class. 52 | /// 53 | [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)] 54 | internal static global::System.Globalization.CultureInfo Culture { 55 | get { 56 | return resourceCulture; 57 | } 58 | set { 59 | resourceCulture = value; 60 | } 61 | } 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /Properties/Resources.resx: -------------------------------------------------------------------------------- 1 |  2 | 3 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | text/microsoft-resx 107 | 108 | 109 | 2.0 110 | 111 | 112 | System.Resources.ResXResourceReader, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 113 | 114 | 115 | System.Resources.ResXResourceWriter, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 116 | 117 | -------------------------------------------------------------------------------- /Properties/Settings.Designer.cs: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // 3 | // This code was generated by a tool. 4 | // Runtime Version:4.0.30319.1022 5 | // 6 | // Changes to this file may cause incorrect behavior and will be lost if 7 | // the code is regenerated. 8 | // 9 | //------------------------------------------------------------------------------ 10 | 11 | namespace Lion_assembler.Properties { 12 | 13 | 14 | [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()] 15 | [global::System.CodeDom.Compiler.GeneratedCodeAttribute("Microsoft.VisualStudio.Editors.SettingsDesigner.SettingsSingleFileGenerator", "10.0.0.0")] 16 | internal sealed partial class Settings : global::System.Configuration.ApplicationSettingsBase { 17 | 18 | private static Settings defaultInstance = ((Settings)(global::System.Configuration.ApplicationSettingsBase.Synchronized(new Settings()))); 19 | 20 | public static Settings Default { 21 | get { 22 | return defaultInstance; 23 | } 24 | } 25 | } 26 | } 27 | -------------------------------------------------------------------------------- /Properties/Settings.settings: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Lionasm 2 | ------- 3 | 4 | The Lion computer project schematics and VHDL sources & an assembler for the Lion 16-bit FPGA based CPU in C#. 5 | 6 | Lion CPU and Lion Computer which is a homebrew 16-bit computer based on this cpu, are made by Theodoulos Liontakis. 7 | 8 | The files folder contains the Lion cpu-computer project, (VHDL, schematic and assembly source files). 9 | 10 | Project Pages: 11 | http://users.sch.gr/tliontakis/index.php/my-projects/13-vhdl-cpu 12 | 13 | https://hackaday.io/project/162876-lion-fpga-cpucomputer 14 | 15 | Hardware design and software released under the Creative Commons License BY-NC-SA https://creativecommons.org/licenses/by-nc-sa/4.0/ 16 | -------------------------------------------------------------------------------- /Utils.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using System.Xml; 6 | using System.Xml.Serialization; 7 | using System.IO; 8 | 9 | namespace Lion_assembler 10 | { 11 | public static class Utils 12 | { 13 | private static string AppRunPath; 14 | private static string LogFileName; 15 | 16 | static Utils() 17 | { 18 | AppRunPath = AppDomain.CurrentDomain.BaseDirectory; 19 | LogFileName = "Log_" + System.Diagnostics.Process.GetCurrentProcess().ProcessName + "_#.txt"; 20 | } 21 | 22 | #if LOG 23 | public static void Log(string strToLog, params object[] args) 24 | { 25 | Console.WriteLine(strToLog, args); 26 | 27 | string mylogfname = LogFileName.Replace("#", DateTime.Now.ToString("yyyyMMdd")); 28 | 29 | using (StreamWriter f = File.AppendText(AppRunPath + @"\" + mylogfname)) 30 | { 31 | string timestamp = DateTime.Now.ToString("yyyyMMdd") + "|" + DateTime.Now.ToString("HH:mm:ss:fff"); 32 | f.WriteLine(string.Format("{0}|{1}", timestamp, args.Length > 0 ? string.Format(strToLog, args) : strToLog)); 33 | f.Close(); 34 | } 35 | } 36 | #endif 37 | 38 | /// 39 | /// write an object to xml file 40 | /// 41 | public static void WriteObjectToXML(object theObject) 42 | { 43 | string fname = theObject.ToString() + ".xml"; 44 | WriteObjectToXML(theObject, fname); 45 | } 46 | 47 | public static void WriteObjectToXML(object theObject, string fname) 48 | { 49 | try 50 | { 51 | if (string.IsNullOrEmpty(fname)) 52 | { 53 | fname = theObject.ToString() + ".xml"; 54 | } 55 | if (!Directory.Exists(Path.GetDirectoryName(fname))) 56 | { 57 | fname = Path.Combine(System.Windows.Forms.Application.StartupPath, fname); 58 | } 59 | XmlSerializer x = new XmlSerializer(theObject.GetType()); 60 | using (XmlTextWriter xmlwr = new XmlTextWriter(fname, Encoding.UTF8)) 61 | { 62 | xmlwr.Formatting = Formatting.Indented; 63 | var ns = new XmlSerializerNamespaces(); 64 | ns.Add(string.Empty, string.Empty); 65 | x.Serialize(xmlwr, theObject, ns); 66 | } 67 | } 68 | catch (Exception e) 69 | { 70 | #if LOG 71 | Log("EXCEPTION in WriteObjectToXML ( {0} ) : {1}" ,fname, e.Message); 72 | #endif 73 | } 74 | } 75 | } 76 | } 77 | -------------------------------------------------------------------------------- /files/3_to_8.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 112 208) 24 | (text "3_to_8" (rect 5 0 47 19)(font "Intel Clear" (font_size 8))) 25 | (text "inst" (rect 8 171 24 188)(font "Intel Clear" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "G1" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 30 | (text "G1" (rect 21 27 38 46)(font "Intel Clear" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "A" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 37 | (text "A" (rect 21 43 29 62)(font "Intel Clear" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "B" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 44 | (text "B" (rect 21 59 29 78)(font "Intel Clear" (font_size 8))) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "C" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 51 | (text "C" (rect 21 75 29 94)(font "Intel Clear" (font_size 8))) 52 | (line (pt 0 80)(pt 16 80)) 53 | ) 54 | (port 55 | (pt 96 32) 56 | (output) 57 | (text "Y0N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 58 | (text "Y0N" (rect 50 27 75 46)(font "Intel Clear" (font_size 8))) 59 | (line (pt 96 32)(pt 80 32)) 60 | ) 61 | (port 62 | (pt 96 48) 63 | (output) 64 | (text "Y1N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 65 | (text "Y1N" (rect 50 43 75 62)(font "Intel Clear" (font_size 8))) 66 | (line (pt 96 48)(pt 80 48)) 67 | ) 68 | (port 69 | (pt 96 64) 70 | (output) 71 | (text "Y2N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 72 | (text "Y2N" (rect 50 59 75 78)(font "Intel Clear" (font_size 8))) 73 | (line (pt 96 64)(pt 80 64)) 74 | ) 75 | (port 76 | (pt 96 80) 77 | (output) 78 | (text "Y3N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 79 | (text "Y3N" (rect 50 75 75 94)(font "Intel Clear" (font_size 8))) 80 | (line (pt 96 80)(pt 80 80)) 81 | ) 82 | (port 83 | (pt 96 96) 84 | (output) 85 | (text "Y4N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 86 | (text "Y4N" (rect 50 91 75 110)(font "Intel Clear" (font_size 8))) 87 | (line (pt 96 96)(pt 80 96)) 88 | ) 89 | (port 90 | (pt 96 112) 91 | (output) 92 | (text "Y5N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 93 | (text "Y5N" (rect 50 107 75 126)(font "Intel Clear" (font_size 8))) 94 | (line (pt 96 112)(pt 80 112)) 95 | ) 96 | (port 97 | (pt 96 128) 98 | (output) 99 | (text "Y6N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 100 | (text "Y6N" (rect 50 123 75 142)(font "Intel Clear" (font_size 8))) 101 | (line (pt 96 128)(pt 80 128)) 102 | ) 103 | (port 104 | (pt 96 144) 105 | (output) 106 | (text "Y7N" (rect 0 0 25 19)(font "Intel Clear" (font_size 8))) 107 | (text "Y7N" (rect 50 139 75 158)(font "Intel Clear" (font_size 8))) 108 | (line (pt 96 144)(pt 80 144)) 109 | ) 110 | (drawing 111 | (rectangle (rect 16 16 80 176)) 112 | ) 113 | ) 114 | -------------------------------------------------------------------------------- /files/74251_l.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 112 240) 24 | (text "74251_l" (rect 5 0 56 19)(font "Intel Clear" (font_size 8))) 25 | (text "inst" (rect 8 203 24 220)(font "Intel Clear" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "D0" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 30 | (text "D0" (rect 21 27 38 46)(font "Intel Clear" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "D1" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 37 | (text "D1" (rect 21 43 38 62)(font "Intel Clear" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "D2" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 44 | (text "D2" (rect 21 59 38 78)(font "Intel Clear" (font_size 8))) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "D3" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 51 | (text "D3" (rect 21 75 38 94)(font "Intel Clear" (font_size 8))) 52 | (line (pt 0 80)(pt 16 80)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "D4" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 58 | (text "D4" (rect 21 91 38 110)(font "Intel Clear" (font_size 8))) 59 | (line (pt 0 96)(pt 16 96)) 60 | ) 61 | (port 62 | (pt 0 112) 63 | (input) 64 | (text "D5" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 65 | (text "D5" (rect 21 107 38 126)(font "Intel Clear" (font_size 8))) 66 | (line (pt 0 112)(pt 16 112)) 67 | ) 68 | (port 69 | (pt 0 128) 70 | (input) 71 | (text "D6" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 72 | (text "D6" (rect 21 123 38 142)(font "Intel Clear" (font_size 8))) 73 | (line (pt 0 128)(pt 16 128)) 74 | ) 75 | (port 76 | (pt 0 144) 77 | (input) 78 | (text "D7" (rect 0 0 17 19)(font "Intel Clear" (font_size 8))) 79 | (text "D7" (rect 21 139 38 158)(font "Intel Clear" (font_size 8))) 80 | (line (pt 0 144)(pt 16 144)) 81 | ) 82 | (port 83 | (pt 0 160) 84 | (input) 85 | (text "A" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 86 | (text "A" (rect 21 155 29 174)(font "Intel Clear" (font_size 8))) 87 | (line (pt 0 160)(pt 16 160)) 88 | ) 89 | (port 90 | (pt 0 176) 91 | (input) 92 | (text "B" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 93 | (text "B" (rect 21 171 29 190)(font "Intel Clear" (font_size 8))) 94 | (line (pt 0 176)(pt 16 176)) 95 | ) 96 | (port 97 | (pt 0 192) 98 | (input) 99 | (text "C" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 100 | (text "C" (rect 21 187 29 206)(font "Intel Clear" (font_size 8))) 101 | (line (pt 0 192)(pt 16 192)) 102 | ) 103 | (port 104 | (pt 96 32) 105 | (output) 106 | (text "Y" (rect 0 0 8 19)(font "Intel Clear" (font_size 8))) 107 | (text "Y" (rect 67 27 75 46)(font "Intel Clear" (font_size 8))) 108 | (line (pt 96 32)(pt 80 32)) 109 | ) 110 | (drawing 111 | (rectangle (rect 16 16 80 208)) 112 | ) 113 | ) 114 | -------------------------------------------------------------------------------- /files/BOOT.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/files/BOOT.bin -------------------------------------------------------------------------------- /files/LPLL2.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2019 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and any partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details, at 14 | --https://fpgasoftware.intel.com/eula. 15 | 16 | 17 | component LPLL2 18 | PORT 19 | ( 20 | inclk0 : IN STD_LOGIC := '0'; 21 | c0 : OUT STD_LOGIC ; 22 | c1 : OUT STD_LOGIC 23 | ); 24 | end component; 25 | -------------------------------------------------------------------------------- /files/LPLL2.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /files/LPLL2.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ALTPLL% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altpll 5 | 6 | -- ============================================================ 7 | -- File Name: LPLL2.vhd 8 | -- Megafunction Name(s): 9 | -- altpll 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 18.1.1 Build 646 04/11/2019 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and any partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details, at 34 | --https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | LIBRARY ieee; 38 | USE ieee.std_logic_1164.all; 39 | 40 | LIBRARY altera_mf; 41 | USE altera_mf.all; 42 | 43 | ENTITY LPLL2 IS 44 | PORT 45 | ( 46 | inclk0 : IN STD_LOGIC := '0'; 47 | c0 : OUT STD_LOGIC ; 48 | c1 : OUT STD_LOGIC 49 | ); 50 | END LPLL2; 51 | 52 | 53 | ARCHITECTURE SYN OF lpll2 IS 54 | 55 | SIGNAL sub_wire0 : STD_LOGIC ; 56 | SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0); 57 | SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0); 58 | SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); 59 | SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0); 60 | SIGNAL sub_wire4 : STD_LOGIC ; 61 | SIGNAL sub_wire5 : STD_LOGIC ; 62 | 63 | 64 | 65 | COMPONENT altpll 66 | GENERIC ( 67 | bandwidth_type : STRING; 68 | clk0_divide_by : NATURAL; 69 | clk0_duty_cycle : NATURAL; 70 | clk0_multiply_by : NATURAL; 71 | clk0_phase_shift : STRING; 72 | clk1_divide_by : NATURAL; 73 | clk1_duty_cycle : NATURAL; 74 | clk1_multiply_by : NATURAL; 75 | clk1_phase_shift : STRING; 76 | compensate_clock : STRING; 77 | inclk0_input_frequency : NATURAL; 78 | intended_device_family : STRING; 79 | lpm_hint : STRING; 80 | lpm_type : STRING; 81 | operation_mode : STRING; 82 | pll_type : STRING; 83 | port_activeclock : STRING; 84 | port_areset : STRING; 85 | port_clkbad0 : STRING; 86 | port_clkbad1 : STRING; 87 | port_clkloss : STRING; 88 | port_clkswitch : STRING; 89 | port_configupdate : STRING; 90 | port_fbin : STRING; 91 | port_inclk0 : STRING; 92 | port_inclk1 : STRING; 93 | port_locked : STRING; 94 | port_pfdena : STRING; 95 | port_phasecounterselect : STRING; 96 | port_phasedone : STRING; 97 | port_phasestep : STRING; 98 | port_phaseupdown : STRING; 99 | port_pllena : STRING; 100 | port_scanaclr : STRING; 101 | port_scanclk : STRING; 102 | port_scanclkena : STRING; 103 | port_scandata : STRING; 104 | port_scandataout : STRING; 105 | port_scandone : STRING; 106 | port_scanread : STRING; 107 | port_scanwrite : STRING; 108 | port_clk0 : STRING; 109 | port_clk1 : STRING; 110 | port_clk2 : STRING; 111 | port_clk3 : STRING; 112 | port_clk4 : STRING; 113 | port_clk5 : STRING; 114 | port_clkena0 : STRING; 115 | port_clkena1 : STRING; 116 | port_clkena2 : STRING; 117 | port_clkena3 : STRING; 118 | port_clkena4 : STRING; 119 | port_clkena5 : STRING; 120 | port_extclk0 : STRING; 121 | port_extclk1 : STRING; 122 | port_extclk2 : STRING; 123 | port_extclk3 : STRING; 124 | width_clock : NATURAL 125 | ); 126 | PORT ( 127 | inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 128 | clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) 129 | ); 130 | END COMPONENT; 131 | 132 | BEGIN 133 | sub_wire2_bv(0 DOWNTO 0) <= "0"; 134 | sub_wire2 <= To_stdlogicvector(sub_wire2_bv); 135 | sub_wire0 <= inclk0; 136 | sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0; 137 | sub_wire5 <= sub_wire3(1); 138 | sub_wire4 <= sub_wire3(0); 139 | c0 <= sub_wire4; 140 | c1 <= sub_wire5; 141 | 142 | altpll_component : altpll 143 | GENERIC MAP ( 144 | bandwidth_type => "AUTO", 145 | clk0_divide_by => 1, 146 | clk0_duty_cycle => 50, 147 | clk0_multiply_by => 1, 148 | clk0_phase_shift => "0", 149 | clk1_divide_by => 1, 150 | clk1_duty_cycle => 50, 151 | clk1_multiply_by => 1, 152 | clk1_phase_shift => "10000", 153 | compensate_clock => "CLK0", 154 | inclk0_input_frequency => 20000, 155 | intended_device_family => "Cyclone IV E", 156 | lpm_hint => "CBX_MODULE_PREFIX=LPLL2", 157 | lpm_type => "altpll", 158 | operation_mode => "NORMAL", 159 | pll_type => "AUTO", 160 | port_activeclock => "PORT_UNUSED", 161 | port_areset => "PORT_UNUSED", 162 | port_clkbad0 => "PORT_UNUSED", 163 | port_clkbad1 => "PORT_UNUSED", 164 | port_clkloss => "PORT_UNUSED", 165 | port_clkswitch => "PORT_UNUSED", 166 | port_configupdate => "PORT_UNUSED", 167 | port_fbin => "PORT_UNUSED", 168 | port_inclk0 => "PORT_USED", 169 | port_inclk1 => "PORT_UNUSED", 170 | port_locked => "PORT_UNUSED", 171 | port_pfdena => "PORT_UNUSED", 172 | port_phasecounterselect => "PORT_UNUSED", 173 | port_phasedone => "PORT_UNUSED", 174 | port_phasestep => "PORT_UNUSED", 175 | port_phaseupdown => "PORT_UNUSED", 176 | port_pllena => "PORT_UNUSED", 177 | port_scanaclr => "PORT_UNUSED", 178 | port_scanclk => "PORT_UNUSED", 179 | port_scanclkena => "PORT_UNUSED", 180 | port_scandata => "PORT_UNUSED", 181 | port_scandataout => "PORT_UNUSED", 182 | port_scandone => "PORT_UNUSED", 183 | port_scanread => "PORT_UNUSED", 184 | port_scanwrite => "PORT_UNUSED", 185 | port_clk0 => "PORT_USED", 186 | port_clk1 => "PORT_USED", 187 | port_clk2 => "PORT_UNUSED", 188 | port_clk3 => "PORT_UNUSED", 189 | port_clk4 => "PORT_UNUSED", 190 | port_clk5 => "PORT_UNUSED", 191 | port_clkena0 => "PORT_UNUSED", 192 | port_clkena1 => "PORT_UNUSED", 193 | port_clkena2 => "PORT_UNUSED", 194 | port_clkena3 => "PORT_UNUSED", 195 | port_clkena4 => "PORT_UNUSED", 196 | port_clkena5 => "PORT_UNUSED", 197 | port_extclk0 => "PORT_UNUSED", 198 | port_extclk1 => "PORT_UNUSED", 199 | port_extclk2 => "PORT_UNUSED", 200 | port_extclk3 => "PORT_UNUSED", 201 | width_clock => 5 202 | ) 203 | PORT MAP ( 204 | inclk => sub_wire1, 205 | clk => sub_wire3 206 | ); 207 | 208 | 209 | 210 | END SYN; 211 | 212 | -- ============================================================ 213 | -- CNX file retrieval info 214 | -- ============================================================ 215 | -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 216 | -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 217 | -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 218 | -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 219 | -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Medium" 220 | -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 221 | -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 222 | -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 223 | -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 224 | -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 225 | -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 226 | -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 227 | -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 228 | -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 229 | -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 230 | -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" 231 | -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 232 | -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 233 | -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 234 | -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 235 | -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" 236 | -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" 237 | -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 238 | -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 239 | -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 240 | -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 241 | -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 242 | -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 243 | -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 244 | -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 245 | -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 246 | -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 247 | -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 248 | -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 249 | -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 250 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 251 | -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 252 | -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 253 | -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 254 | -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 255 | -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 256 | -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 257 | -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 258 | -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 259 | -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 260 | -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 261 | -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 262 | -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 263 | -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 264 | -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" 265 | -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000" 266 | -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 267 | -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 268 | -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 269 | -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 270 | -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 271 | -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 272 | -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 273 | -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000" 274 | -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 275 | -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 276 | -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" 277 | -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 278 | -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 279 | -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 280 | -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 281 | -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 282 | -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 283 | -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 284 | -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 285 | -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 286 | -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 287 | -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "LPLL2.mif" 288 | -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 289 | -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 290 | -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 291 | -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 292 | -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 293 | -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 294 | -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 295 | -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 296 | -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" 297 | -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 298 | -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 299 | -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 300 | -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 301 | -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 302 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 303 | -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" 304 | -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" 305 | -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 306 | -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 307 | -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 308 | -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 309 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 310 | -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 311 | -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 312 | -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 313 | -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 314 | -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 315 | -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" 316 | -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 317 | -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" 318 | -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "10000" 319 | -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 320 | -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 321 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 322 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 323 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 324 | -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 325 | -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 326 | -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 327 | -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 328 | -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 329 | -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 330 | -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 331 | -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 332 | -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 333 | -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 334 | -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 335 | -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 336 | -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 337 | -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 338 | -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 339 | -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 340 | -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 341 | -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 342 | -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 343 | -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 344 | -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 345 | -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 346 | -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 347 | -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 348 | -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 349 | -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 350 | -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 351 | -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 352 | -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 353 | -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 354 | -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 355 | -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 356 | -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 357 | -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 358 | -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 359 | -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 360 | -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 361 | -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 362 | -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 363 | -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 364 | -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 365 | -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 366 | -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 367 | -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 368 | -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" 369 | -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 370 | -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 371 | -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 372 | -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 373 | -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 374 | -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 375 | -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 376 | -- Retrieval info: GEN_FILE: TYPE_NORMAL LPLL2.vhd TRUE 377 | -- Retrieval info: GEN_FILE: TYPE_NORMAL LPLL2.ppf TRUE 378 | -- Retrieval info: GEN_FILE: TYPE_NORMAL LPLL2.inc TRUE 379 | -- Retrieval info: GEN_FILE: TYPE_NORMAL LPLL2.cmp TRUE 380 | -- Retrieval info: GEN_FILE: TYPE_NORMAL LPLL2.bsf TRUE 381 | -- Retrieval info: GEN_FILE: TYPE_NORMAL LPLL2_inst.vhd TRUE 382 | -- Retrieval info: LIB_FILE: altera_mf 383 | -- Retrieval info: CBX_MODULE_PREFIX: ON 384 | -------------------------------------------------------------------------------- /files/LionSystem.dpf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /files/LionSystem.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2019 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition 22 | # Date created = 00:20:37 June 21, 2019 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "18.1" 27 | DATE = "00:20:37 June 21, 2019" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "LionSystem" 32 | PROJECT_REVISION = "Lionsys_1" 33 | -------------------------------------------------------------------------------- /files/LionSystem.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2012 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 32-bit 20 | # Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition 21 | # Date created = 11:10:35 June 14, 2015 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # LionSystem_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | 40 | # Project-Wide Assignments 41 | # ======================== 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:50:00 MAY 06, 2015" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name SMART_RECOMPILE OFF 47 | 48 | # Pin & Location Assignments 49 | # ========================== 50 | 51 | # Classic Timing Assignments 52 | # ========================== 53 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 54 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 55 | set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS OFF 56 | 57 | # Analysis & Synthesis Assignments 58 | # ================================ 59 | set_global_assignment -name FAMILY "Cyclone V" 60 | set_global_assignment -name TOP_LEVEL_ENTITY LionSystem 61 | set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 62 | set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF 63 | 64 | # Fitter Assignments 65 | # ================== 66 | set_global_assignment -name DEVICE 5CEFA2F23I7 67 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 68 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 69 | 70 | # EDA Netlist Writer Assignments 71 | # ============================== 72 | set_global_assignment -name EDA_SIMULATION_TOOL "" 73 | 74 | # Power Estimation Assignments 75 | # ============================ 76 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 77 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 78 | 79 | # start EDA_TOOL_SETTINGS(eda_simulation) 80 | # --------------------------------------- 81 | 82 | # EDA Netlist Writer Assignments 83 | # ============================== 84 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation 85 | 86 | # end EDA_TOOL_SETTINGS(eda_simulation) 87 | # ------------------------------------- 88 | 89 | # ------------------------ 90 | # start ENTITY(LionSystem) 91 | 92 | # start DESIGN_PARTITION(Top) 93 | # --------------------------- 94 | 95 | # Incremental Compilation Assignments 96 | # =================================== 97 | 98 | # end DESIGN_PARTITION(Top) 99 | # ------------------------- 100 | 101 | # end ENTITY(LionSystem) 102 | # ---------------------- 103 | set_global_assignment -name OPTIMIZATION_MODE BALANCED 104 | set_global_assignment -name ALLOW_REGISTER_RETIMING ON 105 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 106 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 107 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 108 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 109 | set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP 110 | set_global_assignment -name ENABLE_OCT_DONE OFF 111 | set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF 112 | set_global_assignment -name ENABLE_NCE_PIN OFF 113 | set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF 114 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 115 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 116 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 117 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 118 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 119 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 120 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 121 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.2 122 | set_location_assignment PIN_B15 -to R 123 | set_location_assignment PIN_C15 -to G 124 | set_location_assignment PIN_A14 -to B 125 | set_location_assignment PIN_B16 -to HSYN 126 | set_location_assignment PIN_C16 -to VSYN 127 | set_location_assignment PIN_V18 -to Reset 128 | set_location_assignment PIN_AA13 -to HOLD 129 | set_location_assignment PIN_AB15 -to RD 130 | set_location_assignment PIN_M16 -to MISO 131 | set_location_assignment PIN_K22 -to MOSI 132 | set_location_assignment PIN_L17 -to SCLK 133 | set_location_assignment PIN_M22 -to SPICS 134 | set_location_assignment PIN_AA15 -to Rx 135 | set_location_assignment PIN_Y15 -to Tx 136 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS PROGRAMMING PIN" 137 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "COMPILER CONFIGURED" 138 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "COMPILER CONFIGURED" 139 | set_location_assignment PIN_Y14 -to Int 140 | set_location_assignment PIN_M9 -to iClock 141 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 142 | set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED 143 | set_global_assignment -name ENABLE_DRC_SETTINGS ON 144 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" 145 | set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END" 146 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ 147 | set_location_assignment PIN_L18 -to VSYN2 148 | set_location_assignment PIN_L19 -to HSYN2 149 | set_location_assignment PIN_N19 -to AUDIOB 150 | set_location_assignment PIN_AA1 -to KCLK 151 | set_location_assignment PIN_AA2 -to KDATA 152 | set_location_assignment PIN_N16 -to RTC_CLK 153 | set_location_assignment PIN_K21 -to RTC_DATA 154 | set_location_assignment PIN_K17 -to RTC_CE 155 | set_location_assignment PIN_N1 -to JOYST1[0] 156 | set_location_assignment PIN_W2 -to JOYST1[1] 157 | set_location_assignment PIN_Y3 -to JOYST1[2] 158 | set_location_assignment PIN_U1 -to JOYST1[3] 159 | set_location_assignment PIN_U2 -to JOYST1[4] 160 | set_location_assignment PIN_M21 -to NOISEO 161 | set_location_assignment PIN_M18 -to AUDIOA 162 | set_location_assignment PIN_M20 -to AUDIOC 163 | set_location_assignment PIN_A13 -to PG 164 | set_location_assignment PIN_D13 -to PR 165 | set_location_assignment PIN_C13 -to PB 166 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G 167 | set_location_assignment PIN_AA18 -to ADo[2] 168 | set_location_assignment PIN_AA17 -to ADo[3] 169 | set_location_assignment PIN_AA20 -to ADo[4] 170 | set_location_assignment PIN_AA19 -to ADo[5] 171 | set_location_assignment PIN_Y20 -to ADo[6] 172 | set_location_assignment PIN_Y19 -to ADo[7] 173 | set_location_assignment PIN_AB21 -to ADo[8] 174 | set_location_assignment PIN_AB20 -to ADo[9] 175 | set_location_assignment PIN_AA22 -to ADo[10] 176 | set_location_assignment PIN_AB22 -to ADo[11] 177 | set_location_assignment PIN_W22 -to ADo[12] 178 | set_location_assignment PIN_Y22 -to ADo[13] 179 | set_location_assignment PIN_Y21 -to ADo[14] 180 | set_location_assignment PIN_W21 -to ADo[15] 181 | set_location_assignment PIN_V20 -to A18o 182 | set_location_assignment PIN_V21 -to A17o 183 | set_location_assignment PIN_U22 -to A16o 184 | set_location_assignment PIN_G6 -to D[8] 185 | set_location_assignment PIN_H6 -to D[9] 186 | set_location_assignment PIN_G8 -to D[10] 187 | set_location_assignment PIN_H8 -to D[11] 188 | set_location_assignment PIN_F7 -to D[12] 189 | set_location_assignment PIN_E7 -to D[13] 190 | set_location_assignment PIN_D6 -to D[14] 191 | set_location_assignment PIN_C6 -to D[15] 192 | set_location_assignment PIN_U21 -to JOYST2[0] 193 | set_location_assignment PIN_U20 -to JOYST2[1] 194 | set_location_assignment PIN_R22 -to JOYST2[2] 195 | set_location_assignment PIN_T22 -to JOYST2[3] 196 | set_location_assignment PIN_P22 -to JOYST2[4] 197 | set_location_assignment PIN_B5 -to ASo 198 | set_location_assignment PIN_A5 -to DSo 199 | set_location_assignment PIN_Y16 -to Holdao 200 | set_location_assignment PIN_A7 -to IA[1] 201 | set_location_assignment PIN_A8 -to IA[0] 202 | set_location_assignment PIN_A9 -to IACK 203 | set_location_assignment PIN_A10 -to IOo 204 | set_location_assignment PIN_B10 -to Iv[1] 205 | set_location_assignment PIN_C9 -to Iv[0] 206 | set_location_assignment PIN_G10 -to RWo 207 | set_global_assignment -name OPTIMIZE_SSN "NORMAL COMPILATION" 208 | set_global_assignment -name VHDL_FILE XY_Disp.vhd 209 | set_global_assignment -name VHDL_FILE LionCPU16r.vhd 210 | set_global_assignment -name VHDL_FILE video_640x480_M.vhd 211 | set_global_assignment -name VHDL_FILE UART.vhd 212 | set_global_assignment -name VHDL_FILE SPI.vhd 213 | set_global_assignment -name VHDL_FILE LPLL2.vhd 214 | set_global_assignment -name BDF_FILE 3_to_8.bdf 215 | set_global_assignment -name BDF_FILE regs.bdf 216 | set_global_assignment -name BDF_FILE ALU_LA4.bdf 217 | set_global_assignment -name BDF_FILE 74251_l.bdf 218 | set_global_assignment -name VHDL_FILE LionSystem.vhd 219 | set_global_assignment -name SDC_FILE LionSystem.sdc 220 | set_global_assignment -name CDF_FILE output_files/LionSystem.cdf 221 | set_global_assignment -name CDF_FILE output_files/Chain1.cdf 222 | set_location_assignment PIN_E12 -to SPICS2 223 | set_location_assignment PIN_D12 -to SCLK2 224 | set_location_assignment PIN_B12 -to MOSI2 225 | set_location_assignment PIN_C11 -to LDAC 226 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 227 | set_global_assignment -name OPTIMIZATION_TECHNIQUE BALANCED 228 | set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO 229 | set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS" 230 | set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA 231 | set_location_assignment PIN_B11 -to MOSI3 232 | set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF 233 | set_global_assignment -name AUTO_RAM_RECOGNITION ON 234 | set_location_assignment PIN_A12 -to MOSI4 235 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MISO 236 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KCLK 237 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KDATA 238 | set_location_assignment PIN_Y17 -to ADo[1] 239 | set_location_assignment PIN_AB18 -to ADo[0] 240 | set_location_assignment PIN_B13 -to BRIB 241 | set_location_assignment PIN_A15 -to BRIG 242 | set_location_assignment PIN_F10 -to BRIR 243 | set_location_assignment PIN_C2 -to D[7] 244 | set_location_assignment PIN_C1 -to D[6] 245 | set_location_assignment PIN_D3 -to D[5] 246 | set_location_assignment PIN_E2 -to D[4] 247 | set_location_assignment PIN_G2 -to D[3] 248 | set_location_assignment PIN_G1 -to D[2] 249 | set_location_assignment PIN_L2 -to D[1] 250 | set_location_assignment PIN_L1 -to D[0] 251 | set_location_assignment PIN_N2 -to ER_SEL 252 | set_location_assignment PIN_D9 -to ERH 253 | set_location_assignment PIN_E9 -to ERL 254 | set_location_assignment PIN_W19 -to RW2 255 | set_instance_assignment -name CLAMPING_DIODE ON -to KCLK 256 | set_instance_assignment -name CLAMPING_DIODE ON -to KDATA 257 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to JOYST* 258 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /files/LionSystem.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/files/LionSystem.qws -------------------------------------------------------------------------------- /files/LionSystem.sdc: -------------------------------------------------------------------------------- 1 | ## Generated SDC file "LionSystem.sdc" 2 | 3 | ## Copyright (C) 2019 Intel Corporation. All rights reserved. 4 | ## Your use of Intel Corporation's design tools, logic functions 5 | ## and other software and tools, and any partner logic 6 | ## functions, and any output files from any of the foregoing 7 | ## (including device programming or simulation files), and any 8 | ## associated documentation or information are expressly subject 9 | ## to the terms and conditions of the Intel Program License 10 | ## Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | ## the Intel FPGA IP License Agreement, or other applicable license 12 | ## agreement, including, without limitation, that your use is for 13 | ## the sole purpose of programming logic devices manufactured by 14 | ## Intel and sold by Intel or its authorized distributors. Please 15 | ## refer to the applicable agreement for further details, at 16 | ## https://fpgasoftware.intel.com/eula. 17 | 18 | 19 | ## VENDOR "Altera" 20 | ## PROGRAM "Quartus Prime" 21 | ## VERSION "Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition" 22 | 23 | ## DATE "Wed Sep 25 00:26:06 2019" 24 | 25 | ## 26 | ## DEVICE "5CEFA2F23I7" 27 | ## 28 | 29 | 30 | #************************************************************** 31 | # Time Information 32 | #************************************************************** 33 | 34 | set_time_format -unit ns -decimal_places 3 35 | 36 | 37 | 38 | #************************************************************** 39 | # Create Clock 40 | #************************************************************** 41 | 42 | create_clock -name {iClock} -period 20.000 -waveform { 0.000 10.000 } [get_ports {iClock}] 43 | 44 | 45 | #************************************************************** 46 | # Create Generated Clock 47 | #************************************************************** 48 | 49 | create_generated_clock -name {CPLL|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {CPLL|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 12 -divide_by 2 -master_clock {iClock} [get_pins {CPLL|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}] 50 | create_generated_clock -name {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 6 -master_clock {CPLL|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] 51 | create_generated_clock -name {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 6 -phase 180/1 -master_clock {CPLL|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] 52 | 53 | 54 | #************************************************************** 55 | # Set Clock Latency 56 | #************************************************************** 57 | 58 | 59 | 60 | #************************************************************** 61 | # Set Clock Uncertainty 62 | #************************************************************** 63 | 64 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 65 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 66 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 67 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 68 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 69 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 70 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 71 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 72 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 73 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 74 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 75 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 76 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 77 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 78 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 79 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 80 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 81 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 82 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 83 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 84 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 85 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 86 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 87 | set_clock_uncertainty -rise_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 88 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 89 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 90 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 91 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 92 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 93 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 94 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 95 | set_clock_uncertainty -fall_from [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {CPLL|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 96 | 97 | 98 | #************************************************************** 99 | # Set Input Delay 100 | #************************************************************** 101 | 102 | 103 | 104 | #************************************************************** 105 | # Set Output Delay 106 | #************************************************************** 107 | 108 | 109 | 110 | #************************************************************** 111 | # Set Clock Groups 112 | #************************************************************** 113 | 114 | 115 | 116 | #************************************************************** 117 | # Set False Path 118 | #************************************************************** 119 | 120 | 121 | 122 | #************************************************************** 123 | # Set Multicycle Path 124 | #************************************************************** 125 | 126 | 127 | 128 | #************************************************************** 129 | # Set Maximum Delay 130 | #************************************************************** 131 | 132 | 133 | 134 | #************************************************************** 135 | # Set Minimum Delay 136 | #************************************************************** 137 | 138 | 139 | 140 | #************************************************************** 141 | # Set Input Transition 142 | #************************************************************** 143 | 144 | -------------------------------------------------------------------------------- /files/LionSystem.vhd: -------------------------------------------------------------------------------- 1 | -- Lion Computer 2 | -- Theodoulos Liontakis (C) 2015 3 | 4 | Library ieee; 5 | USE ieee.std_logic_1164.all; 6 | USE ieee.std_logic_unsigned.all ; 7 | USE ieee.numeric_std.all ; 8 | 9 | entity LionSystem is 10 | port 11 | ( 12 | D : INOUT Std_logic_vector(15 downto 0); 13 | ADo : OUT Std_logic_vector(15 downto 0); 14 | RWo,ASo,DSo : OUT Std_logic; 15 | RD,Reset,iClock,HOLD: IN Std_Logic; 16 | Int: IN Std_Logic; 17 | IOo,Holdao,A16o,A17o,A18o,ERH,ERL,ER_SEL,RW2 : OUT std_logic; 18 | Iv : IN std_logic_vector(1 downto 0); 19 | IACK: OUT std_logic; 20 | IA : OUT std_logic_vector(1 downto 0); 21 | R,G,B,VSYN,HSYN,VSYN2,HSYN2,BRIR,BRIG,BRIB : OUT std_Logic; 22 | PB, PG, PR : OUT std_Logic; 23 | Tx : OUT std_logic ; 24 | Rx : IN std_logic ; 25 | AUDIOA,AUDIOB,AUDIOC,NOISEO: OUT std_logic; 26 | SCLK,MOSI,SPICS: OUT std_logic; 27 | MISO: IN std_logic; 28 | JOYST1,JOYST2: IN std_logic_vector(4 downto 0); 29 | KCLK,KDATA:INOUT std_logic; 30 | RTC_CE,RTC_CLK:OUT std_logic; 31 | RTC_DATA:INOUT std_logic; 32 | SCLK2,MOSI2,MOSI3,MOSI4,SPICS2,LDAC: OUT std_logic 33 | ); 34 | end LionSystem; 35 | 36 | Architecture Behavior of LionSystem is 37 | 38 | Component LionCPU16 is 39 | port 40 | ( 41 | Di : IN Std_logic_vector(15 downto 0); 42 | DOo : OUT Std_logic_vector(15 downto 0); 43 | ADo : OUT Std_logic_vector(15 downto 0); 44 | RW, AS, DS: OUT Std_logic; 45 | RD, Reset, clock, Int,HOLD: IN Std_Logic; 46 | IO,HOLDA,A16o,A17o,A18o : OUT std_logic; 47 | I : IN std_logic_vector(1 downto 0); 48 | IACK: OUT std_logic; 49 | IA : OUT std_logic_vector(1 downto 0); 50 | BACS: OUT std_logic 51 | ); 52 | end Component; 53 | 54 | Component LPLL2 IS 55 | PORT 56 | ( 57 | inclk0 : IN STD_LOGIC := '0'; 58 | c0 : OUT STD_LOGIC ; 59 | c1 : OUT STD_LOGIC 60 | --c2 : OUT STD_LOGIC 61 | ); 62 | END Component; 63 | 64 | Component lfsr_II is 65 | port ( 66 | cout :out std_logic; -- Output 67 | clk :in std_logic; -- Input rlock 68 | reset :in std_logic; -- Input reset 69 | Vol :in std_logic_vector(7 downto 0) 70 | --bw :in std_logic_vector(15 downto 0) --band width 71 | ); 72 | end Component; 73 | 74 | Component VideoRGB80 is 75 | port 76 | ( 77 | sclk, vclk, EN : IN std_logic; 78 | R,G,B,BRI0,VSYN,HSYN,VSINT, HSINT : OUT std_logic; 79 | addr : OUT natural range 0 to 16383; 80 | Q : IN std_logic_vector(15 downto 0); 81 | hline: OUT std_logic_vector(15 downto 0) 82 | ); 83 | end Component; 84 | 85 | Component VideoRGB1 is 86 | port 87 | ( 88 | sclk,vclk, EN : IN std_logic; 89 | R,G,B,BRI,VSYN,HSYN,VSINT, HSINT : OUT std_logic; 90 | addr : OUT natural range 0 to 16383; 91 | Q : IN std_logic_vector(15 downto 0); 92 | hline: OUT std_logic_vector(15 downto 0) 93 | ); 94 | end Component; 95 | 96 | Component dual_port_ram_dual_clock is 97 | 98 | generic 99 | ( 100 | DATA_WIDTH : natural := 16; 101 | ADDR_WIDTH : natural := 14 102 | ); 103 | 104 | port 105 | ( 106 | clka,clkb: in std_logic; 107 | addr_a : in natural range 0 to 2**ADDR_WIDTH - 1; 108 | addr_b : in natural range 0 to 2**ADDR_WIDTH - 1; 109 | data_b : in std_logic_vector((DATA_WIDTH-1) downto 0); 110 | we_b : in std_logic := '1'; 111 | q_a : out std_logic_vector((DATA_WIDTH -1) downto 0); 112 | q_b : out std_logic_vector((DATA_WIDTH -1) downto 0); 113 | be : in std_logic_vector (1 downto 0) 114 | ); 115 | end Component; 116 | 117 | 118 | Component UART is 119 | port 120 | ( 121 | Tx : OUT std_logic ; 122 | Rx : IN std_logic ; 123 | clk, reset, r, w : IN std_logic ; 124 | data_ready, ready : OUT std_logic; 125 | data_in : IN std_logic_vector (7 downto 0); 126 | data_out :OUT std_logic_vector (7 downto 0) 127 | ); 128 | end Component; 129 | 130 | Component SoundI is 131 | port 132 | ( 133 | Audio: OUT std_logic; 134 | reset, clk, wr : IN std_logic; 135 | Q : IN std_logic_vector(15 downto 0); 136 | Vol : IN std_logic_vector(7 downto 0); 137 | harmonic : IN std_logic_vector(3 downto 0); 138 | count: OUT std_logic_vector(31 downto 0); 139 | play: OUT std_logic 140 | ); 141 | end Component; 142 | 143 | COMPONENT single_port_ram is 144 | port 145 | ( 146 | clk : in std_logic; 147 | addr : in natural range 0 to 65535; 148 | data : in std_logic_vector(15 downto 0); 149 | we : in std_logic := '1'; 150 | q : out std_logic_vector(15 downto 0) 151 | ); 152 | end COMPONENT; 153 | 154 | 155 | COMPONENT byte_enabled_simple_dual_port_ram is 156 | port ( 157 | clk : in std_logic; 158 | addr : in integer range 0 to 65535 ; 159 | data : in std_logic_vector(15 downto 0); 160 | we : in std_logic; 161 | q : out std_logic_vector(15 downto 0); 162 | be : in std_logic_vector (1 downto 0) 163 | ); 164 | end COMPONENT; 165 | 166 | COMPONENT SPI is 167 | port 168 | ( 169 | SCLK, MOSI : OUT std_logic ; 170 | MISO : IN std_logic ; 171 | clk, reset, w: IN std_logic ; 172 | ready : OUT std_logic; 173 | data_in : IN std_logic_vector (7 downto 0); 174 | data_out :OUT std_logic_vector (7 downto 0) 175 | ); 176 | end COMPONENT; 177 | 178 | COMPONENT VideoSp is 179 | generic 180 | ( 181 | DATA_LINE : natural := 1 182 | ); 183 | port 184 | ( 185 | sclk, vclk: IN std_logic; 186 | R,G,B,BRI,SPDET: OUT std_logic; 187 | reset, pbuffer, dbuffer : IN std_logic; 188 | spaddr: OUT natural range 0 to 2047; 189 | SPQ: IN std_logic_vector(15 downto 0) 190 | ); 191 | end COMPONENT; 192 | 193 | COMPONENT PS2KEYB is 194 | port 195 | ( 196 | Rx , kclk : IN std_logic ; 197 | clk, reset, r : IN std_logic ; 198 | data_ready : OUT std_logic; 199 | data_out :OUT std_logic_vector (7 downto 0) 200 | ); 201 | end COMPONENT; 202 | 203 | COMPONENT XY_Display_MCP4822 is 204 | port 205 | ( 206 | sclk: IN std_logic; 207 | reset: IN std_logic; 208 | addr: OUT natural range 0 to 2047; 209 | Q: IN std_logic_vector(15 downto 0); 210 | CS,SCK,SDI,SDI2,SDI3: OUT std_logic; 211 | LDAC: OUT std_logic:='1'; 212 | MODE: IN std_logic:='0' 213 | ); 214 | end COMPONENT; 215 | 216 | constant ZERO16 : std_logic_vector(15 downto 0):= (OTHERS => '0'); 217 | 218 | Signal pdelay: natural range 0 to 2047 :=0; 219 | Signal R0,B0,G0,BRI0,R1,G1,B1,BRI1,SR2,SG2,SB2,SBRI2,SPDET2,SR3,SG3,SB3,SBRI3,SPDET3,SR1,SB1,SG1,SBRI1,SPDET1: std_logic:='0'; 220 | Signal clock0,clock1,clock2,lfsr_clk:std_logic; 221 | Signal hsyn0,vsyn0,hsyn1,vsyn1,Vmod: std_logic:='0'; 222 | Signal vq: std_logic_vector (15 downto 0); 223 | Signal harm1,harm2,harm3 : std_logic_vector(3 downto 0):="0000"; 224 | Signal di,do,AD,qa,qro,aq,aq2,aq3,q16, hline,hline0,hline1: std_logic_vector(15 downto 0); 225 | Signal ncnt : std_logic_vector(15 downto 0); 226 | Signal count,count2,count3 : std_logic_vector(31 downto 0); 227 | Signal lfsr_bw : std_logic_vector(15 downto 0):="0010000000000000"; 228 | Signal WAud, WAud2,WAud3,BRI, PB0, PG0, PR0: std_logic:='1'; 229 | Signal HOLDA, A16,A17,A18,IO,nen1,nen2,nen3,ne1,ne2,ne3: std_logic:='0'; 230 | Signal rst, rst2, AS, DS, RW, Int_in,vint,vint0,vint1,hint,hint0,hint1,xyd: std_logic:='1'; 231 | Signal w1,spw1, spw2, spw3,xyw,xyen: std_logic:='0'; 232 | Signal SPQ1,spvq1,SPQ2,spvq2,SPQ3,spvq3,xyq1,xyq2: std_logic_vector(15 downto 0); 233 | Signal Ii : std_logic_vector(1 downto 0); 234 | Signal ad1,vad0,vad1 : natural range 0 to 16383; 235 | Signal spad1,spad3,spad5: natural range 0 to 2047; 236 | Signal xyadr : natural range 0 to 1023; 237 | Signal sr,sw,sdready,sready,kr,kready,ser2,sdready2, noise: std_Logic; 238 | Signal sdi,sdo,sdo2,kdo : std_logic_vector (7 downto 0); 239 | Signal Vol1,Vol2,Vol3,Voln : std_logic_vector (7 downto 0):="11111111"; 240 | SIGNAL Spi_in,Spi_out: STD_LOGIC_VECTOR (7 downto 0); 241 | Signal Spi_w, spi_rdy, play,play2,play3 : std_logic; 242 | Signal XYmode, BACS, HINT_EN :std_Logic:='0'; 243 | Signal BSEL: std_logic_vector (1 downto 0); 244 | Signal spb, sdb: std_logic_vector (7 downto 0):="00000000"; 245 | 246 | shared variable Di1:std_logic_vector(15 downto 0); 247 | 248 | begin 249 | CPU: LionCPU16 250 | PORT MAP ( Di,Do,AD,RW,AS,DS,RD,rst,clock0,Int_in,Hold,IO,Holda,A16,A17,A18,Ii,Iack,IA,BACS ) ; 251 | IRAM: byte_enabled_simple_dual_port_ram 252 | PORT MAP ( clock1, to_integer(unsigned(A16&AD(15 downto 1))), Do, RW or IO or DS, QA, BSEL ) ; 253 | VRAM: dual_port_ram_dual_clock 254 | GENERIC MAP (DATA_WIDTH => 16, ADDR_WIDTH => 14) 255 | PORT MAP ( clock0, clock1, ad1, to_integer(unsigned(AD(14 downto 1))), Do, w1, vq, q16,BSEL ); 256 | SPRAM: dual_port_ram_dual_clock 257 | GENERIC MAP (DATA_WIDTH => 16, ADDR_WIDTH => 11) 258 | PORT MAP ( clock0,clock1, spad1, to_integer(unsigned(AD(11 downto 1))), Do, spw1, spvq1, SPQ1, BSEL ); 259 | SPRAM2: dual_port_ram_dual_clock 260 | GENERIC MAP (DATA_WIDTH => 16, ADDR_WIDTH => 11) 261 | PORT MAP ( clock0,clock1, spad3, to_integer(unsigned(AD(11 downto 1))), Do, spw2, spvq2, SPQ2, BSEL ); 262 | SPRAM3: dual_port_ram_dual_clock 263 | GENERIC MAP (DATA_WIDTH => 16, ADDR_WIDTH => 11) 264 | PORT MAP ( clock0,clock1, spad5, to_integer(unsigned(AD(11 downto 1))), Do, spw3, spvq3, SPQ3, BSEL ); 265 | XYRAM: dual_port_ram_dual_clock 266 | GENERIC MAP (DATA_WIDTH => 16, ADDR_WIDTH => 11) 267 | PORT MAP ( clock0,clock1, xyadr, to_integer(unsigned(AD(11 downto 1))), Do, xyw, xyq1, xyq2, BSEL ); 268 | VIDEO0: videoRGB80 269 | PORT MAP ( clock1,clock0,Vmod,R0,G0,B0,BRI0,VSYN0,HSYN0,vint0,hint0,vad0,vq, hline0); 270 | VIDEO1: videoRGB1 271 | PORT MAP ( clock1,clock0,Vmod,R1,G1,B1,BRI1,VSYN1,HSYN1,vint1,hint1,vad1,vq, hline1); 272 | SPRTG1: VideoSp 273 | GENERIC MAP (DATA_LINE => 3) 274 | PORT MAP ( clock1, clock0,SR1,SG1,SB1,SBRI1,SPDET1,vint,spb(0),sdb(0),spad1,spvq1); 275 | SPRTG2: VideoSp 276 | GENERIC MAP (DATA_LINE => 2) 277 | PORT MAP ( clock1, clock0,SR2,SG2,SB2,SBRI2,SPDET2,vint,spb(1),sdb(1),spad3,spvq2); 278 | SPRTG3: VideoSp 279 | GENERIC MAP (DATA_LINE => 1) 280 | PORT MAP ( clock1, clock0,SR3,SG3,SB3,SBRI3,SPDET3,vint,spb(2),sdb(2),spad5,spvq3); 281 | Serial: UART 282 | PORT MAP ( Tx,Rx,clock0,rst,sr,sw,sdready,sready,sdi,sdo ); 283 | SoundC1: SoundI 284 | PORT MAP (AUDIOA,rst,clock1,Waud,aq,Vol1,harm1,count,play); 285 | SoundC2: SoundI 286 | PORT MAP (AUDIOB,rst,clock1,Waud2,aq2,Vol2,harm2,count2,play2); 287 | SoundC3: SoundI 288 | PORT MAP (AUDIOC,rst,clock1,Waud3,aq3,Vol3,harm3,count3,play3); 289 | MSPI: SPI 290 | PORT MAP ( SCLK,MOSI,MISO,clock1,rst,spi_w,spi_rdy,spi_in,spi_out); 291 | NOIZ:lfsr_II 292 | PORT MAP ( noise, lfsr_clk, rst, Voln); 293 | CPLL:LPLL2 294 | PORT MAP (iClock,Clock0,Clock1); 295 | PS2:PS2KEYB 296 | PORT MAP (KDATA,KCLK,clock1,rst,kr,kready,kdo); 297 | XYC:XY_Display_MCP4822 298 | PORT MAP (clock1,rst,xyadr,xyq1,SPICS2,SCLK2,MOSI2,MOSI3,MOSI4,LDAC,XYmode); 299 | rst2<=not reset when rising_edge(clock0); 300 | rst<=rst2 when rising_edge(clock0); 301 | 302 | HOLDAo<=HOLDA; 303 | Di<=Di1 when IO='1' else qa when A17='0' and A18='0' else D when AD(0)='1' else D(7 downto 0)&D(15 downto 8); 304 | A16o<=A16 when HOLDA='0' else 'Z'; 305 | A17o<=A17 when HOLDA='0' else 'Z'; 306 | A18o<=A18 when HOLDA='0' else 'Z'; 307 | ASo<=AS when HOLDA='0' else 'Z'; 308 | DSo<=DS when HOLDA='0' else 'Z'; 309 | IOo<=IO when HOLDA='0' else 'Z'; 310 | RWo<=RW when HOLDA='0' else 'Z'; 311 | RW2<=RW when HOLDA='0' else 'Z'; 312 | D<= Do when RW='0' and DS='0' AND HOLDA='0' else "ZZZZZZZZZZZZZZZZ"; 313 | ADo<= AD when AS='0' AND HOLDA='0' else "ZZZZZZZZZZZZZZZZ"; 314 | --IACK<=IAC; 315 | 316 | BSEL<= "01" when BACS='1' and AD(0)='1' else "10" when BACS='1' and AD(0)='0' else "11"; 317 | ERL<=not BSEL(0); -- external ram 318 | ERH<=not BSEL(1); -- external ram 319 | ER_SEL<=not (A17 OR A18); -- external ram 320 | 321 | nen1<='1' when (ne1='1') and (play='1') and (aq(12 downto 0)/="0000000000000") else '0'; 322 | nen2<='1' when (ne2='1') and (play2='1') and (aq2(12 downto 0)/="0000000000000") else '0'; 323 | nen3<='1' when (ne3='1') and (play3='1') and (aq3(12 downto 0)/="0000000000000") else '0'; 324 | NOISEO<=NOISE and (nen1 or nen2 or nen3); 325 | ncnt<=ncnt+1 when rising_edge(Clock0); 326 | Clock2<=ncnt(13); 327 | lfsr_clk<= AUDIOA when (nen1='1' and aq(12 downto 0)<=700) else AUDIOB when (nen2='1' and aq2(12 downto 0)<=700) 328 | else AUDIOC when(nen3='1' and aq3(12 downto 0)<=700) else clock2 329 | when (nen1='1' and aq(12 downto 0)>700) or (nen2='1' and aq2(12 downto 0)>700) or (nen3='1' and aq3(12 downto 0)>700) 330 | else '0'; 331 | 332 | --counter<=counter+1 when rising_edge(clock2); 333 | 334 | R<= SR1 when SPDET1='1' else SR2 when SPDET2='1' else SR3 when SPDET3='1' else R1 when Vmod='1' else R0; 335 | G<= SG1 when SPDET1='1' else SG2 when SPDET2='1' else SG3 when SPDET3='1' else G1 when Vmod='1' else G0; 336 | B<= SB1 when SPDET1='1' else SB2 when SPDET2='1' else SB3 when SPDET3='1' else B1 when Vmod='1' else B0; 337 | PR<= SR1 when SPDET1='1' else SR2 when SPDET2='1' else SR3 when SPDET3='1' else R1 when Vmod='1' else R0; 338 | PG<= SG1 when SPDET1='1' else SG2 when SPDET2='1' else SG3 when SPDET3='1' else G1 when Vmod='1' else G0; 339 | PB<= SB1 when SPDET1='1' else SB2 when SPDET2='1' else SB3 when SPDET3='1' else B1 when Vmod='1' else B0; 340 | BRI<= SBRI1 when SPDET1='1' else SBRI2 when SPDET2='1' else SBRI3 when SPDET3='1' else BRI1 when Vmod='1' else BRI0; 341 | BRIR<=BRI; 342 | BRIG<=BRI; 343 | BRIB<=BRI; 344 | 345 | ad1<=vad1 when Vmod='1' else vad0; 346 | HSYN<=HSYN1 when Vmod='1' else HSYN0; 347 | VSYN<=VSYN1 when Vmod='1' else VSYN0; 348 | HSYN2<=HSYN1 when Vmod='1' else HSYN0; 349 | VSYN2<=VSYN1 when Vmod='1' else VSYN0; 350 | VINT<=Vint1 when Vmod='1' else Vint0; 351 | hline<=hline1 when Vmod='1' else hline0; 352 | hint<=hint1 when Vmod='1' and HINT_EN='1' else hint0 when Vmod='0' and HINT_EN='1' else '1'; 353 | 354 | --pdelay<=0 when hsyn='0' and rising_edge(clock1) else pdelay+1 when rising_edge(clock1); 355 | --PB<=PB0 when pdelay>47*2 and vsyn='1' and hsyn='1' else '0'; 356 | --PG<=PG0 when pdelay>47*2 and vsyn='1' and hsyn='1' else '0'; 357 | --PR<=PR0 when pdelay>47*2 and vsyn='1' and hsyn='1' else '0'; 358 | 359 | RTC_DATA<='Z'; 360 | RTC_CLK<='0'; 361 | RTC_CE<='0'; 362 | 363 | w1<='1' when DS='0' and AS='0' and IO='1' and AD(15)='1' and RW='0' else '0'; 364 | spw1<='1' when DS='0' and AS='0' and IO='1' and AD(15 downto 12)="0100" and RW='0' else '0'; 365 | spw2<='1' when DS='0' and AS='0' and IO='1' and AD(15 downto 12)="0101" and RW='0' else '0'; 366 | spw3<='1' when DS='0' and AS='0' and IO='1' and AD(15 downto 12)="0110" and RW='0' else '0'; 367 | xyw<='1' when DS='0' and AS='0' and IO='1' and AD(15 downto 12)="0111" and RW='0' else '0'; 368 | 369 | -- Interrupts 370 | process (clock1,INT) 371 | begin 372 | if rising_edge(clock1) then 373 | if INT='0' then II<=Iv; elsif HINT='0' then II<="10"; else II<="11"; end if; 374 | Int_in<= INT and VINT and HINT; 375 | end if; 376 | end process; 377 | 378 | Vmod<='0' when rst='1' and rising_edge(clock1) else Do(0) when AD=24 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 379 | 380 | -- UART SKEYB SPI IO decoding 381 | sdi<=Do(7 downto 0) when AD=0 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 382 | sr<=Do(1) when AD=2 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 383 | kr<=Do(1) when AD=15 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 384 | sw<=Do(0) when AD=2 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 385 | spi_w<=Do(0) when AD=19 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 386 | SPICS<=Do(1) when AD=19 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 387 | spi_in<=Do(7 downto 0) when AD=18 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 388 | spb(2 downto 0)<=Do(2 downto 0) when AD=20 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 389 | sdb(2 downto 0)<=Do(5 downto 3) when AD=20 and IO='1' and AS='0' and DS='0' and RW='0' and rising_edge(clock1); 390 | 391 | --Sound IO decoding 392 | aq<=Do when AD=8 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 8 393 | aq2<=Do when AD=10 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 10 394 | aq3<=Do when AD=12 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 12 395 | Vol1<=Do(7 downto 0) when AD=25 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 25 396 | Vol2<=Do(7 downto 0) when AD=26 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 26 397 | Vol3<=Do(7 downto 0) when AD=27 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 27 398 | Voln<=Do(7 downto 0) when AD=28 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 28 399 | ne1<=Do(0) when AD=11 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- noise enable 400 | ne2<=Do(1) when AD=11 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- noise enable 401 | ne3<=Do(2) when AD=11 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- noise enable 402 | Waud<='0' when AD=8 and IO='1' and AS='0' and RW='0' and rising_edge(clock1) else '1' when rising_edge(clock1); 403 | Waud2<='0' when AD=10 and IO='1' and AS='0' and RW='0' and rising_edge(clock1) else '1' when rising_edge(clock1); 404 | Waud3<='0' when AD=12 and IO='1' and AS='0' and RW='0' and rising_edge(clock1) else '1' when rising_edge(clock1); 405 | HINT_EN<=Do(0) when AD=13 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); 406 | --lfsr_bw<=Do when AD=13 and IO='1' and AS='0' and RW='0' and rising_edge(clock1); 407 | --PR0<=Do(0) when AD=30 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); 408 | --PG0<=Do(1) when AD=30 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); 409 | --PB0<=Do(2) when AD=30 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); 410 | XYmode<=Do(0) when AD=30 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); 411 | harm1<=Do(3 downto 0) when AD=31 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 25 412 | harm2<=Do(3 downto 0) when AD=32 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 26 413 | harm3<=Do(3 downto 0) when AD=33 and IO='1' and RW='0' and AS='0' and DS='0' and rising_edge(clock1); -- port 27 414 | 415 | -- Read decoder 416 | process (clock0,RW,AS,IO) 417 | begin 418 | if rising_edge(clock0) and RW='1' and AS='0' AND IO='1' then 419 | if AD(15)='1' then Di1:=q16; --video 420 | elsif AD(14 downto 12)="100" then Di1:=SPQ1; 421 | elsif AD(14 downto 12)="101" then Di1:=SPQ2; 422 | elsif AD(14 downto 12)="110" then Di1:=SPQ3; 423 | elsif AD(14 downto 12)="111" then Di1:=xyq2; 424 | end if; 425 | if AD=4 then Di1:="00000000"&sdo; end if; -- serial1 426 | if AD=14 then Di1:="00000000"&kdo; end if; -- serial2 keyboard 427 | if AD=6 then Di1:="0000000000000" & kready & sdready & sready; end if; -- serial status 428 | if AD=16 then Di1:="00000000"&spi_out; end if; --spi 429 | if AD=17 then Di1:="000000000000000" & spi_rdy; end if; --spi 430 | if AD=9 then Di1:="0000000000000"& play3 & play2 & play; end if; -- audio status 431 | if AD=22 then Di1:="000"&JOYST2&"000"& JOYST1; end if; -- joysticks 432 | if AD=20 then Di1:=count(15 downto 0); end if; 433 | if AD=21 then Di1:=count(31 downto 16); end if; 434 | if AD=23 then Di1:="00000000000000"&Vsyn&hsyn; end if; -- VSYNCH HSYNCH STATUS 435 | if AD=24 then Di1:="000000000000000"&Vmod; end if; 436 | if AD=35 then Di1:=hline; end if; 437 | end if; 438 | end process; 439 | 440 | end Behavior; 441 | 442 | ---------------------------------------------- 443 | 444 | library ieee; 445 | use ieee.std_logic_1164.all; 446 | 447 | entity dual_port_ram_dual_clock is 448 | 449 | generic 450 | ( 451 | DATA_WIDTH : natural := 16; 452 | ADDR_WIDTH : natural := 14 453 | ); 454 | 455 | port 456 | ( 457 | clka,clkb: in std_logic; 458 | addr_a : in natural range 0 to 2**ADDR_WIDTH - 1; 459 | addr_b : in natural range 0 to 2**ADDR_WIDTH - 1; 460 | data_b : in std_logic_vector((DATA_WIDTH-1) downto 0); 461 | we_b : in std_logic := '1'; 462 | q_a : out std_logic_vector((DATA_WIDTH -1) downto 0); 463 | q_b : out std_logic_vector((DATA_WIDTH -1) downto 0); 464 | be : in std_logic_vector (1 downto 0) 465 | ); 466 | 467 | end dual_port_ram_dual_clock; 468 | 469 | architecture rtl of dual_port_ram_dual_clock is 470 | 471 | subtype word_t is std_logic_vector(7 downto 0); 472 | type memory_t is array(0 to 2**ADDR_WIDTH-1) of word_t; 473 | 474 | signal ram0,ram1 : memory_t; 475 | attribute ramstyle : string; 476 | attribute ramstyle of ram0 : signal is "no_rw_check"; 477 | attribute ramstyle of ram1 : signal is "no_rw_check"; 478 | begin 479 | process(clkb, we_b) 480 | variable b:word_t; 481 | begin 482 | if(rising_edge(clkb)) then 483 | if we_b='1' then 484 | if (be = "11") then 485 | b:=data_b(15 downto 8); 486 | elsif be = "10" then 487 | b:=data_b(7 downto 0); 488 | end if; 489 | if be(1)='1' then ram0(addr_b) <= b; end if; 490 | else 491 | q_b(15 downto 8) <= ram0(addr_b); 492 | end if; 493 | end if; 494 | end process; 495 | 496 | process(clkb, we_b) 497 | variable a:word_t; 498 | begin 499 | if(rising_edge(clkb)) then 500 | if we_b='1' then 501 | a:= data_b(7 downto 0); 502 | if be(0)='1' then ram1(addr_b) <= a; end if; 503 | else 504 | q_b(7 downto 0) <= ram1(addr_b); 505 | end if; 506 | end if; 507 | end process; 508 | 509 | process(clka) 510 | begin 511 | if(rising_edge(clka)) then 512 | q_a<= ram0(addr_a)&ram1(addr_a); 513 | end if; 514 | end process; 515 | end rtl; 516 | 517 | -------------------------------------------------------------------------------------------- 518 | -- changed for Lion 519 | -- Simple Dual-Port RAM with different read/write addresses and single read/write clock 520 | -- and with a control for writing single bytes into the memory word; byte enable 521 | 522 | library ieee; 523 | use ieee.std_logic_1164.all; 524 | library work; 525 | 526 | entity byte_enabled_simple_dual_port_ram is 527 | 528 | port ( 529 | clk : in std_logic; 530 | addr : in integer range 0 to 65535 ; 531 | data : in std_logic_vector(15 downto 0); 532 | we : in std_logic; 533 | q : out std_logic_vector(15 downto 0); 534 | be : in std_logic_vector (1 downto 0) 535 | ); 536 | end byte_enabled_simple_dual_port_ram; 537 | 538 | architecture rtl of byte_enabled_simple_dual_port_ram is 539 | -- build up 2D array to hold the memory 540 | type word_t is array (0 to 1) of std_logic_vector(7 downto 0); 541 | type ram_t is array (65535 downto 0) of word_t; 542 | -- declare the RAM 543 | signal ram : ram_t; 544 | attribute ram_init_file : string; 545 | attribute ram_init_file of ram : signal is ".\Lionasm\bin\Debug\lionrom.mif"; 546 | attribute ramstyle : string; 547 | attribute ramstyle of ram : signal is "no_rw_check"; 548 | signal q_local : word_t; 549 | 550 | begin -- rtl 551 | 552 | process(clk) 553 | begin 554 | if(rising_edge(clk)) then 555 | if(we = '0') and (addr>4095) then 556 | if (be = "11") then 557 | ram(addr)(0) <= data(15 downto 8); 558 | ram(addr)(1) <= data(7 downto 0); 559 | elsif be = "10" then 560 | ram(addr)(0) <= data(7 downto 0); 561 | elsif be = "01" then 562 | ram(addr)(1) <= data(7 downto 0); 563 | end if; 564 | end if; 565 | q <= ram(addr)(0)&ram(addr)(1); 566 | end if; 567 | end process; 568 | end rtl; 569 | 570 | 571 | 572 | 573 | ------------------------------------------------------- 574 | Library ieee; 575 | USE ieee.std_logic_1164.all; 576 | USE ieee.std_logic_unsigned.all ; 577 | USE ieee.numeric_std.all ; 578 | 579 | entity PS2KEYB is 580 | port 581 | ( 582 | Rx,Kclk : IN std_logic ; 583 | clk, reset, r : IN std_logic ; 584 | data_ready : OUT std_logic:='0'; 585 | data_out :OUT std_logic_vector (7 downto 0) 586 | ); 587 | end PS2KEYB; 588 | 589 | 590 | Architecture Behavior of PS2KEYB is 591 | 592 | constant rblen:natural:=16; 593 | type FIFO_r is array (0 to rblen-1) of std_logic_vector(9 downto 2); 594 | Signal rFIFO: FIFO_r; 595 | attribute ramstyle : string; 596 | attribute ramstyle of rFIFO : signal is "logic"; 597 | Signal inb: std_logic_vector(9 downto 1); 598 | Signal lastkey: std_logic_vector(7 downto 0):="00000000"; 599 | --Signal delay:natural range 0 to 65535:=0; 600 | signal dr: boolean:=false; 601 | signal rptr1, rptr2: natural range 0 to rblen := 0; 602 | signal rstate: natural range 0 to 15 :=0 ; 603 | Signal k0,k1,k2,k3,k4: std_logic:='1'; 604 | begin 605 | --Rx<=RXin when clk'EVENT and clk = '0'; 606 | 607 | process (clk,kclk,reset) 608 | 609 | variable ra:boolean :=false ; 610 | 611 | begin 612 | if (reset='1') then 613 | rptr1<=0; rptr2<=0; data_ready<='0'; rstate<=0; 614 | dr<=false; ra:=false; lastkey<="00000000"; 615 | elsif clk'EVENT and clk = '1' then 616 | if (k0='1') and ((k1 or k2 or k3 or k4)='0') then 617 | if rstate=0 and Rx='0' then 618 | rstate<=1; 619 | elsif rstate>0 and rstate<10 then 620 | inb(rstate)<=Rx; 621 | rstate<=rstate+1; 622 | elsif rstate=10 and Rx='1' then 623 | rstate<=0; 624 | if (lastkey/="11110000") and (inb(8 downto 1)/="11110000") and (inb(8 downto 1)/="11100000") then 625 | if (lastkey="11100000") then 626 | rFIFO(rptr2)<="1010"&inb(4 downto 1); 627 | else 628 | rFIFO(rptr2)<=inb(8 downto 1); 629 | end if; 630 | if rptr2+1"00000000"); 54 | elsif clk'EVENT and clk = '1' then 55 | rcounter<=rcounter+1; 56 | tcounter<=tcounter+1; 57 | rx1<=Rx; rx0<=rx1; 58 | if rcounter=divider or (rstate=0 and rx1='0' and rx0='0' and Rx='0') then 59 | if rstate=0 and Rx='0' and rx1='0' and rx0='0' then 60 | rcounter<=divider/2; 61 | rstate<=1; 62 | elsif rstate=1 then 63 | rstate<=rstate+1; 64 | rcounter<=1; 65 | elsif rstate>0 and rstate<10 then 66 | inb(rstate)<=Rx; 67 | rcounter<=1; 68 | rstate<=rstate+1; 69 | elsif rstate=10 then 70 | rcounter<=1; 71 | rstate<=0; 72 | rFIFO(rptr2)<=inb; 73 | if rptr2+11 and tstate<10 then 97 | TX<=outb(tstate); 98 | tcounter<=1; 99 | tstate<=tstate+1; 100 | elsif tstate=10 then 101 | Tx<='1'; 102 | tcounter<=1; 103 | tstate<=0; 104 | if tptr10 and rstate<10 then 202 | inb(rstate)<=Rx2; 203 | rcounter<=1; 204 | rstate<=rstate+1; 205 | elsif rstate=10 then 206 | rcounter<=1; 207 | rstate<=0; 208 | rFIFO(rptr2)<=inb; 209 | if rptr2+1 57 | I2CC<='1'; 58 | I2CC<='1'; I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; 59 | when 09 => 60 | I2CC<='1'; 61 | I2CC<='1'; I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; 62 | when 10 => 63 | I2CC<='1'; 64 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; --start 65 | when 11 => 66 | I2CC<='0'; 67 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; 68 | when 12=> 69 | I2CC<='1'; -- bit 1 70 | when 13=> 71 | I2CC<='0'; 72 | when 14 => 73 | I2CC<='1'; -- bit 2 74 | when 15 => 75 | I2CC<='0'; 76 | when 16 => 77 | I2CC<='1'; -- bit 3 78 | when 17 => 79 | I2CC<='0'; 80 | when 18 => 81 | I2CC<='1'; -- bit 4 82 | when 19 => 83 | I2CC<='0'; 84 | if mcnt>tslow/2 then I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; end if; 85 | when 20 => 86 | I2CC<='1'; -- bit 5 87 | when 21 => 88 | I2CC<='0'; 89 | --if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; 90 | when 22=> 91 | I2CC<='1'; -- bit 6 92 | when 23=> 93 | I2CC<='0'; 94 | when 24=> 95 | I2CC<='1'; -- bit 7 96 | when 25=> 97 | I2CC<='0'; 98 | when 26=> 99 | I2CC<='1'; -- bit 8 100 | when 27=> 101 | I2CC<='0'; 102 | -- if mcnt>tslow/2 then I2CD1<='Z'; I2CD2<='Z'; I2CD3<='Z'; end if; 103 | when 28=> 104 | I2CC<='1'; 105 | when 29=> 106 | I2CC<='1'; 107 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; --start 108 | when 30 => 109 | --I2CC<='1'; I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; 110 | when 31 => 111 | I2CC<='0'; 112 | if mcnt>tslow/2 then I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; end if; -- device code 113 | when 32=> 114 | I2CC<='1'; --bit 1 115 | when 33=> 116 | if mcnt>tslow/2 then I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; end if; -- device code 117 | I2CC<='0'; 118 | when 34 => 119 | I2CC<='1'; --bit 2 120 | when 35 => 121 | I2CC<='0'; 122 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; 123 | when 36 => 124 | I2CC<='1'; --bit 3 125 | when 37 => 126 | I2CC<='0'; 127 | when 38 => 128 | I2CC<='1'; --bit 4 129 | when 39 => 130 | I2CC<='0'; 131 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; -- address 132 | when 40 => 133 | I2CC<='1'; --bit 5 134 | when 41 => 135 | I2CC<='0'; 136 | if mcnt>tslow/2 then I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; end if; 137 | when 42 => 138 | I2CC<='1'; --bit 6 139 | when 43 => 140 | I2CC<='0'; 141 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; 142 | when 44 => 143 | I2CC<='1'; --bit 7 144 | when 45 => 145 | I2CC<='0'; 146 | if mcnt>tslow/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; -- Write 147 | when 46 => 148 | I2CC<='1'; --bit 8 149 | when 47 => 150 | if mcnt>tslow/2 then I2CD1<='Z'; I2CD2<='Z'; I2CD3<='Z'; end if; 151 | I2CC<='0'; 152 | when 48 => 153 | I2CC<='1'; 154 | if mcnt>tslow/2 then ACK1<=I2CD1; ACK2<=I2CD2; ACK3<=I2CD3; end if; 155 | when 49=> 156 | --I2CC<='0'; 157 | --if mcnt>tslow/2 then I2CD1<='1'; I2CD2<='1'; I2CD3<='1'; end if; 158 | when 50 => 159 | I2CC<='1'; 160 | turn<=1; state<=0; mcnt<=0; 161 | when others => 162 | end case; 163 | elsif turn=1 then --turn 164 | if mcnt 167 | case mcnt is 168 | when 0 => 169 | when 1 => 170 | z<=Q(7 downto 0); 171 | when 2 => 172 | caddr:=caddr+1; lx<=x; ly<=y; 173 | when 3 => 174 | when 4 => 175 | y<=Q(7 downto 0); 176 | x<=Q(15 downto 8); 177 | when 5 => 178 | caddr:=caddr+1; 179 | when others=> 180 | end case; 181 | I2CC<='1'; 182 | when 1 => 183 | I2CC<='0'; 184 | if mcnt>tfast/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; -- second byte 185 | when 2 => 186 | I2CC<='1'; --bit 1 187 | when 3 => 188 | I2CC<='0'; 189 | when 4 => 190 | I2CC<='1'; --bit 2 191 | when 5 => 192 | I2CC<='0'; 193 | when 6 => 194 | I2CC<='1'; --bit 3 195 | when 7 => 196 | I2CC<='0'; 197 | when 8 => 198 | I2CC<='1'; --bit 4 199 | when 9 => 200 | I2CC<='0'; 201 | when 10 => 202 | I2CC<='1'; --bit 5 203 | when 11 => 204 | I2CC<='0'; 205 | when 12 => 206 | I2CC<='1'; --bit 6 207 | when 13 => 208 | I2CC<='0'; 209 | if mcnt>tfast/2 then I2CD1<=z(7); I2CD2<=x(7); I2CD3<=y(7); end if; 210 | when 14 => 211 | I2CC<='1'; --bit 7 212 | when 15 => 213 | I2CC<='0'; 214 | if mcnt>tfast/2 then I2CD1<=z(6); I2CD2<=x(6); I2CD3<=y(6); end if; 215 | when 16 => 216 | I2CC<='1'; --bit 8 217 | when 17 => 218 | I2CC<='0'; 219 | if mcnt>tfast/2 then I2CD1<='Z'; I2CD2<='Z'; I2CD3<='Z'; end if; 220 | when 18 => 221 | I2CC<='1'; 222 | if mcnt>tfast/2 then ACK1<=I2CD1; ACK2<=I2CD2; ACK3<=I2CD3; end if; 223 | when 19 => 224 | I2CC<='0'; 225 | if mcnt>tfast/2 then I2CD1<=z(5); I2CD2<=x(5); I2CD3<=y(5); end if; 226 | when 20 => 227 | I2CC<='1'; --bit 1 228 | when 21 => 229 | I2CC<='0'; 230 | if mcnt>tfast/2 then I2CD1<=z(4); I2CD2<=x(4); I2CD3<=y(4); end if; 231 | when 22 => --bit 2 232 | I2CC<='1'; 233 | when 23 => 234 | I2CC<='0'; 235 | if mcnt>tfast/2 then I2CD1<=z(3); I2CD2<=x(3); I2CD3<=y(3); end if; 236 | when 24 => 237 | I2CC<='1'; --bit 3 238 | when 25 => 239 | I2CC<='0'; 240 | if mcnt>tfast/2 then I2CD1<=z(2); I2CD2<=x(2); I2CD3<=y(2); end if; 241 | when 26 => 242 | I2CC<='1'; --bit 4 243 | when 27 => 244 | I2CC<='0'; 245 | if mcnt>tfast/2 then I2CD1<=z(1); I2CD2<=x(1); I2CD3<=y(1); end if; 246 | when 28 => 247 | I2CC<='1'; --bit 5 248 | when 29 => 249 | I2CC<='0'; 250 | if mcnt>tfast/2 then I2CD1<=z(0); I2CD2<=x(0); I2CD3<=y(0); end if; 251 | when 30 => 252 | I2CC<='1'; --bit 6 253 | when 31 => 254 | I2CC<='0'; 255 | if mcnt>tfast/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; 256 | when 32 => 257 | I2CC<='1'; --bit 7 258 | when 33 => 259 | I2CC<='0'; 260 | if mcnt>tfast/2 then I2CD1<='0'; I2CD2<='0'; I2CD3<='0'; end if; 261 | when 34 => 262 | I2CC<='1'; --bit 8 263 | when 35 => 264 | I2CC<='0'; 265 | if mcnt>tfast/2 then I2CD1<='Z'; I2CD2<='Z'; I2CD3<='Z'; end if; 266 | when 36 => 267 | I2CC<='1'; 268 | ACK1<=I2CD1; ACK2<=I2CD2; ACK3<=I2CD3; 269 | when 37 => 270 | mcnt<=0; state<=0; turn<=1; 271 | when others => 272 | end case; 273 | end if; 274 | end if; --reset 275 | end if; 276 | end process; 277 | 278 | end; 279 | 280 | 281 | 282 | 283 | ----------------------------------------------------------------------------- 284 | -- XY Display controller for Lion Computer 285 | -- Theodoulos Liontakis (C) 2019 286 | 287 | Library ieee; 288 | USE ieee.std_logic_1164.all; 289 | USE ieee.std_logic_signed.all ; 290 | USE ieee.numeric_std.all ; 291 | 292 | entity XY_Display_TLC is 293 | port 294 | ( 295 | sclk: IN std_logic; 296 | reset: IN std_logic; 297 | addr: OUT natural range 0 to 1023; 298 | Q: IN std_logic_vector(15 downto 0); 299 | DACW,MUX: OUT std_logic; 300 | DACA: OUT std_logic_vector(1 downto 0); 301 | DACD: OUT std_logic_vector(7 downto 0) 302 | ); 303 | end XY_Display_TLC; 304 | 305 | 306 | Architecture Behavior of XY_Display_TLC is 307 | 308 | Signal turn: std_logic:='0'; 309 | Signal mcnt : natural range 0 to 2047:=0; 310 | Signal x,y,z: std_logic_vector(7 downto 0); 311 | Shared variable caddr,step,cnt: natural range 0 to 1023:=0; 312 | Shared variable e,lx,ly,cx,cy,dx,dy,maxd,sx,sy:integer range -2048 to 2047; 313 | Shared variable WR,WR2: std_logic:='1'; 314 | Shared variable restart: natural range 0 to 3:=0; 315 | begin 316 | 317 | addr<=caddr; 318 | DACW<=WR; 319 | 320 | process (sclk,reset) 321 | 322 | begin 323 | if rising_edge(sclk) then 324 | if (reset='1') then 325 | mcnt<=0; turn<='0'; 326 | caddr:=0; 327 | WR:='1'; x<="00000000"; y<="00000000"; 328 | MUX<='0'; cnt:=1; restart:=0; 329 | else 330 | case mcnt is 331 | when 0 => 332 | lx:=to_integer(unsigned(x)); 333 | ly:=to_integer(unsigned(y)); 334 | when 1 => 335 | z<=Q(7 downto 0); cnt:=1; 336 | when 2 => 337 | caddr:=caddr+1; step:=0; 338 | when 3 => 339 | DACA<="00"; DACD<=z; 340 | when 4 => 341 | y<=Q(7 downto 0); 342 | x<=Q(15 downto 8); 343 | when 5 => 344 | cx:=to_integer(unsigned(x)); cy:=to_integer(unsigned(y)); 345 | if cx>lx then dx:=cx-lx; else dx:=lx-cx; end if; 346 | if cy>ly then dy:=cy-ly; else dy:=ly-cy; end if; 347 | when 6 => 348 | WR:='0'; 349 | if cx>lx then sx:=1; elsif lx>cx then sx:=-1; else sx:=0; end if; 350 | if cy>ly then sy:=1; elsif ly>cy then sy:=-1; else sy:=0; end if; 351 | when 7 => 352 | WR:='1'; 353 | caddr:=caddr+1; 354 | if dx>=dy then maxd:=dx; e:=2*dy-dx; else maxd:=dy; e:=2*dx-dy; end if; 355 | if maxd>1 then restart:=2; end if; 356 | DACA<="10"; 357 | DACD<=x; 358 | when 8 => 359 | WR:='0'; 360 | when 9 => 361 | WR:='1'; 362 | DACA<="11"; DACD<=y; 363 | restart:=0; 364 | when 10 => 365 | WR:='0'; 366 | when 11 => 367 | WR:='1'; 368 | when 12 => 369 | restart:=1; 370 | when others=> 371 | case step is 372 | when 0 => 373 | if e>=0 then 374 | if dy>dx then 375 | lx:=lx+sx; 376 | e:=e-2*dy; 377 | else 378 | ly:=ly+sy; 379 | e:=e-2*dx; 380 | end if; 381 | else step:=step+1; end if; 382 | when 1 => 383 | if dy>dx then 384 | ly:=ly+sy; 385 | e:=e+2*dx; 386 | else 387 | lx:=lx+sx; 388 | e:=e+2*dy; 389 | end if; 390 | step:=step+1; 391 | DACA<="10"; 392 | DACD<=std_logic_vector(to_unsigned(lx,8)); 393 | when 2 => 394 | step:=step+1; 395 | WR:='0'; 396 | when 3 => 397 | WR:='1'; 398 | step:=step+1; 399 | DACA<="11"; DACD<=std_logic_vector(to_unsigned(ly,8)); 400 | when 4 => 401 | WR:='0'; 402 | step:=step+1; 403 | when 5 => 404 | WR:='1'; 405 | cnt:=cnt+1; 406 | step:=step+1; 407 | when 6 => 408 | step:=step+1; 409 | when 7 => 410 | step:=0; 411 | if cnt>maxd then restart:=1; end if; 412 | when others=> 413 | end case; 414 | end case; 415 | if restart=1 then mcnt<=0; restart:=0; elsif restart=2 then mcnt<=20; restart:=0; else mcnt<=mcnt+1; end if; 416 | end if; --reset 417 | end if; 418 | end process; 419 | 420 | end; 421 | 422 | ---------------------------------------------------------------------------------------- 423 | 424 | -- XY Display controller for Lion Computer 425 | -- Theodoulos Liontakis (C) 2019 426 | 427 | Library ieee; 428 | USE ieee.std_logic_1164.all; 429 | --USE ieee.std_logic_unsigned.all ; 430 | USE ieee.numeric_std.all ; 431 | 432 | entity XY_Display_TLC_i is 433 | port 434 | ( 435 | sclk: IN std_logic; 436 | reset: IN std_logic; 437 | addr: OUT natural range 0 to 1023; 438 | Q: IN std_logic_vector(15 downto 0); 439 | DACW,MUX: OUT std_logic; 440 | DACA: OUT std_logic_vector(1 downto 0); 441 | DACD: OUT std_logic_vector(7 downto 0) 442 | ); 443 | end XY_Display_TLC_i; 444 | 445 | 446 | Architecture Behavior of XY_Display_TLC_i is 447 | 448 | Signal turn: std_logic:='0'; 449 | Signal mcnt : natural range 0 to 2047:=0; 450 | Signal x,y,z,lx,ly: std_logic_vector(7 downto 0); 451 | Shared variable caddr: natural range 0 to 1023:=0; 452 | Shared variable WR,WR2: std_logic:='1'; 453 | begin 454 | 455 | addr<=caddr; 456 | DACW<=WR; 457 | 458 | process (sclk,reset) 459 | 460 | begin 461 | if rising_edge(sclk) then 462 | if (reset='1') then 463 | mcnt<=0; turn<='0'; 464 | caddr:=0; 465 | WR:='1'; 466 | MUX<='0'; 467 | else 468 | if mcnt<86 then mcnt<=mcnt+1; 469 | else mcnt<=0; end if; --TURN <= NOT TURN; 470 | case mcnt is 471 | when 0 => 472 | when 1 => 473 | z<=Q(7 downto 0); 474 | when 2 => 475 | caddr:=caddr+1; lx<=x; ly<=y; 476 | when 3 => 477 | when 4 => 478 | y<=Q(7 downto 0); 479 | x<=Q(15 downto 8); 480 | DACA<="00"; DACD<=z; 481 | when 5 => 482 | WR:='0'; 483 | when 6 => 484 | WR:='1'; 485 | DACA<="10"; 486 | DACD<=x; 487 | when 7 => 488 | WR:='0'; 489 | when 8 => 490 | WR:='1'; 491 | caddr:=caddr+1; 492 | DACA<="11"; DACD<=y; 493 | WR:='0'; 494 | when 9 => 495 | WR:='1'; 496 | when 51 => 497 | DACA<="00"; DACD<="00000000"; 498 | when 52 => 499 | WR:='0'; 500 | when 53 => 501 | when 54 => 502 | WR:='1'; 503 | when others=> 504 | -- if mcnt>11+maxd then mcnt<=0; end if; 505 | end case; 506 | end if; --reset 507 | end if; 508 | end process; 509 | 510 | end; 511 | 512 | ----------------------------------------------------------------------------- 513 | -- XY Display controller for Lion Computer 514 | -- Theodoulos Liontakis (C) 2019 MCP4822 515 | 516 | Library ieee; 517 | USE ieee.std_logic_1164.all; 518 | USE ieee.std_logic_signed.all ; 519 | USE ieee.numeric_std.all ; 520 | 521 | entity XY_Display_MCP4822 is 522 | port 523 | ( 524 | sclk: IN std_logic; 525 | reset: IN std_logic; 526 | addr: OUT natural range 0 to 2047; 527 | Q: IN std_logic_vector(15 downto 0); 528 | CS,SCK,SDI,SDI2,SDI3: OUT std_logic; 529 | LDAC: OUT std_logic:='0'; 530 | MODE: IN std_logic:='0' 531 | ); 532 | end XY_Display_MCP4822; 533 | 534 | 535 | Architecture Behavior of XY_Display_MCP4822 is 536 | 537 | Signal spi_rdy,spi_w: std_logic:='0'; 538 | Shared variable mcnt,cnt : natural range 0 to 2047:=0; 539 | Signal x,y: std_logic_vector(9 downto 0); 540 | Signal z: std_logic_vector(7 downto 0); 541 | Signal spi_in,spi_in2,spi_in3: std_logic_vector(15 downto 0); 542 | Shared variable caddr: natural range 0 to 2047:=0; 543 | Shared variable e,lx,ly,cx,cy,dx,dy,maxd,sx,sy:integer range -4096 to 4095; 544 | Shared variable restart: natural range 0 to 3:=0; 545 | Shared variable onetime,swait: std_logic:='0'; 546 | Shared variable lz: std_logic_vector(7 downto 0); 547 | 548 | Component SPI16_fast is 549 | port 550 | ( 551 | SCLK, MOSI,MOSI2,MOSI3: OUT std_logic ; 552 | clk, reset, w : IN std_logic ; 553 | ready : OUT std_logic; 554 | data_in,data_in2,data_in3 : IN std_logic_vector (15 downto 0) 555 | ); 556 | end Component; 557 | 558 | 559 | begin 560 | FSPI: spi16_fast 561 | PORT MAP ( SCK,SDI,SDI2,SDI3,sclk,reset,spi_w,spi_rdy,spi_in,spi_in2,spi_in3); 562 | 563 | addr<=caddr; 564 | 565 | process (sclk,reset) 566 | 567 | begin 568 | if rising_edge(sclk) then 569 | if (reset='1') then 570 | mcnt:=0; 571 | caddr:=0; swait:='0'; cs<='1'; onetime:='0'; 572 | x<="0000000000"; y<="0000000000"; Z<="00000000"; 573 | cnt:=0; restart:=0; cx:=0; cy:=0; 574 | y(0)<='0'; x(0)<='0'; 575 | else 576 | case mcnt is 577 | when 0 => 578 | lx:=cx; ly:=cy; lz:=z; 579 | z<=Q(7 downto 0); 580 | y(1)<=Q(8); x(1)<=Q(12); 581 | if caddr/=2047 then caddr:=caddr+1; else caddr:=0; end if; 582 | when 1 => 583 | swait:='0'; onetime:='0'; 584 | when 2 => 585 | y(9 downto 2)<=Q(7 downto 0); 586 | x(9 downto 2)<=Q(15 downto 8); 587 | when 3 => 588 | cx:=to_integer(unsigned(x)); cy:=to_integer(unsigned(y)); 589 | if z="00000000" then lx:=cx; ly:=cy; end if; 590 | when 4 => 591 | caddr:=caddr+1; 592 | if cx>lx then sx:=1; dx:=cx-lx; elsif lx>cx then sx:=-1; dx:=lx-cx; else sx:=0; dx:=lx-cx; end if; 593 | if cy>ly then sy:=1; dy:=cy-ly; elsif ly>cy then sy:=-1; dy:=ly-cy; else sy:=0; dy:=ly-cy; end if; 594 | when 5 => 595 | if dx>=dy then maxd:=dx; e:=2*dy-dx; else maxd:=dy; e:=2*dx-dy; end if; 596 | if maxd=0 then mcnt:=mcnt+2; cnt:=maxd; end if; 597 | when 6 => -- loop start 598 | if mode='0' then 599 | if e>=0 then 600 | swait:='1'; 601 | if dy>dx then 602 | lx:=lx+sx; 603 | e:=e-2*dy; 604 | else 605 | ly:=ly+sy; 606 | e:=e-2*dx; 607 | end if; 608 | else swait:='0'; end if; 609 | else 610 | if onetime='1' then 611 | lx:=cx; ly:=cy; 612 | end if; 613 | cnt:=maxd; 614 | end if; 615 | when 7 => 616 | if mode='0' then 617 | if dy>dx then 618 | ly:=ly+sy; 619 | e:=e+2*dx; 620 | else 621 | lx:=lx+sx; 622 | e:=e+2*dy; 623 | end if; 624 | end if; 625 | when 8 => 626 | cs<='0'; 627 | spi_in<="00110"&std_logic_vector(to_unsigned(ly,10))&"0"; 628 | spi_in2<="00110"&z&"000"; 629 | spi_in3<="00110"&std_logic_vector(to_unsigned(lx,10))&"0"; 630 | when 9 => 631 | spi_w<='1'; 632 | when 10 => 633 | when 11 => 634 | when 12 => 635 | spi_w<='0'; 636 | swait:=spi_rdy; 637 | when 13 => 638 | cnt:=cnt+1; 639 | when 14 => 640 | cs<='1'; 641 | if mode='0' then if cnt>=maxd then restart:=1; else restart:=2; end if; end if; 642 | when 15 => 643 | when 16 => 644 | if onetime='0' then restart:=2; onetime:='1'; else restart:=1; end if; 645 | when others=> 646 | end case; 647 | if restart=1 then mcnt:=0; cnt:=0; restart:=0; 648 | elsif restart=2 then mcnt:=6; restart:=0; 649 | elsif swait='0' then mcnt:=mcnt+1; end if; 650 | end if; --reset 651 | end if; 652 | end process; 653 | 654 | end; 655 | 656 | ---------------------------------------------------------------------------------------- 657 | 658 | -- triple SPI interface for mcp4822 659 | -- Theodoulos Liontakis (C) 2016,2019 660 | 661 | Library ieee; 662 | USE ieee.std_logic_1164.all; 663 | USE ieee.std_logic_unsigned.all ; 664 | USE ieee.numeric_std.all ; 665 | 666 | entity SPI16_fast is 667 | port 668 | ( 669 | SCLK, MOSI,MOSI2,MOSI3: OUT std_logic ; 670 | clk, reset, w : IN std_logic ; 671 | ready : OUT std_logic; 672 | data_in,data_in2,data_in3 : IN std_logic_vector (15 downto 0) 673 | ); 674 | end SPI16_fast; 675 | 676 | Architecture Behavior of SPI16_fast is 677 | 678 | constant divider:natural :=1; 679 | Signal rcounter :natural range 0 to 127; 680 | Signal state :natural range 0 to 15:=15; 681 | 682 | begin 683 | 684 | process (clk,reset,w) 685 | begin 686 | if (reset='1') then 687 | rcounter<=0; ready<='0'; 688 | SCLK<='0'; state<=15; 689 | elsif clk'EVENT and clk = '1' then 690 | if rcounter=divider or (w='1' and ready='0') then 691 | rcounter<=0; 692 | MOSI<=data_in(state); MOSI2<=data_in2(state); MOSI3<=data_in3(state); 693 | if state=15 and SCLK='0' and w='1' then 694 | ready<='1'; SCLK<='1'; 695 | elsif state=15 and SCLK='1' then 696 | state<=14; SCLK<='0'; 697 | elsif state=14 and SCLK='0' then 698 | SCLK<='1'; 699 | elsif state=14 and SCLK='1' then 700 | state<=13; SCLK<='0'; 701 | elsif state=13 and SCLK='0' then 702 | SCLK<='1'; 703 | elsif state=13 and SCLK='1' then 704 | state<=12; SCLK<='0'; 705 | elsif state=12 and SCLK='0' then 706 | SCLK<='1'; 707 | elsif state=12 and SCLK='1' then 708 | state<=11; SCLK<='0'; 709 | elsif state=11 and SCLK='0' then 710 | SCLK<='1'; 711 | elsif state=11 and SCLK='1' then 712 | state<=10; SCLK<='0'; 713 | elsif state=10 and SCLK='0' then 714 | SCLK<='1'; 715 | elsif state=10 and SCLK='1' then 716 | state<=9; SCLK<='0'; 717 | elsif state=9 and SCLK='0' then 718 | SCLK<='1'; 719 | elsif state=9 and SCLK='1' then 720 | state<=8; SCLK<='0'; 721 | elsif state=8 and SCLK='0' then 722 | SCLK<='1'; 723 | elsif state=8 and SCLK='1' then 724 | state<=7; SCLK<='0'; 725 | elsif state=7 and SCLK='0' then 726 | SCLK<='1'; 727 | elsif state=7 and SCLK='1' then 728 | state<=6; SCLK<='0'; 729 | elsif state=6 and SCLK='0' then 730 | SCLK<='1'; 731 | elsif state=6 and SCLK='1' then 732 | state<=5; SCLK<='0'; 733 | elsif state=5 and SCLK='0' then 734 | SCLK<='1'; 735 | elsif state=5 and SCLK='1' then 736 | state<=4; SCLK<='0'; 737 | elsif state=4 and SCLK='0' then 738 | SCLK<='1'; 739 | elsif state=4 and SCLK='1' then 740 | state<=3; SCLK<='0'; 741 | elsif state=3 and SCLK='0' then 742 | SCLK<='1'; 743 | elsif state=3 and SCLK='1' then 744 | state<=2; SCLK<='0'; 745 | elsif state=2 and SCLK='0' then 746 | SCLK<='1'; 747 | elsif state=2 and SCLK='1' then 748 | state<=1; SCLK<='0'; 749 | elsif state=1 and SCLK='0' then 750 | SCLK<='1'; 751 | elsif state=1 and SCLK='1' then 752 | state<=0; SCLK<='0'; 753 | elsif state=0 and SCLK='0' then 754 | SCLK<='1'; 755 | elsif state=0 and SCLK='1' then 756 | state<=15; SCLK<='0'; ready<='0'; 757 | else 758 | SCLK<='0'; 759 | ready<='0'; 760 | state<=15; 761 | end if; 762 | else 763 | rcounter<=rcounter+1; 764 | end if; 765 | end if; 766 | end process; 767 | end behavior; 768 | 769 | 770 | ----------------------------------------------------------------------------- 771 | -------------------------------------------------------------------------------- /files/freq_basic.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/files/freq_basic.xlsx -------------------------------------------------------------------------------- /files/lionrom.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/files/lionrom.bin -------------------------------------------------------------------------------- /files/video_640x480_M.vhd: -------------------------------------------------------------------------------- 1 | -- Color Video Controller + Sprites for Lion Computer 2 | -- Theodoulos Liontakis (C) 2016 - 2017 3 | 4 | -- 640x480 @60 Hz 5 | -- Vertical refresh 31.46875 kHz 6 | -- Pixel freq. 25.175 MHz (25 Mhz) 7 | 8 | --Scanline part Pixels Time [µs] 9 | --Visible area 640 25.422045680238 10 | --Front porch 16 0.63555114200596 11 | --Sync pulse 96 3.8133068520357 12 | --Back porch 48 1.9066534260179 13 | --Whole line 800 31.777557100298 14 | 15 | --Frame part Lines Time [ms] 16 | --Visible area 480 15.253227408143 17 | --Front porch 10 0.31777557100298 18 | --Sync pulse 2 0.063555114200596 19 | --Back porch 33 1.0486593843098 20 | --Whole frame 525 16.683217477656 21 | 22 | Library ieee; 23 | USE ieee.std_logic_1164.all; 24 | USE ieee.std_logic_unsigned.all ; 25 | USE ieee.numeric_std.all ; 26 | 27 | entity VideoRGB80 is 28 | port 29 | ( 30 | sclk, vclk, EN: IN std_logic; 31 | R,G,B,BRI0,VSYN,HSYN, VSINT, HSINT: OUT std_logic; 32 | addr : OUT natural range 0 to 16383; 33 | Q : IN std_logic_vector(15 downto 0); 34 | hline: OUT std_logic_vector(15 downto 0) 35 | ); 36 | end VideoRGB80; 37 | 38 | Architecture Behavior of VideoRGB80 is 39 | 40 | constant vbase: natural:= 0; 41 | constant ctbl: natural:= 12000+16384; 42 | constant l1:natural:=35; 43 | constant lno:natural:=240; 44 | constant p1:natural :=142; 45 | constant pno:natural:=640; 46 | constant cxno:natural:=80; 47 | constant p2:natural:=p1+pno; 48 | constant l2:natural:=l1+lno*2; 49 | 50 | Signal lines,pix: natural range 0 to 1023; 51 | Signal pixel, prc : natural range 0 to 1023; 52 | Signal addr2,addr3: natural range 0 to 16383; 53 | signal m8,p6: natural range 0 to 127; 54 | Signal vidc: boolean:=false; 55 | Signal FG,BG: std_logic_vector(3 downto 0); 56 | 57 | shared variable addr1:natural range 0 to 16383; 58 | 59 | begin 60 | 61 | addr<=addr1; 62 | vidc<=not vidc when rising_edge(vclk); 63 | HSYN<='0' when (pixel<96) else '1'; 64 | VSYN<='0' when lines<2 else '1'; 65 | VSINT<='0' when (lines=0) and (pixel<6) else '1'; 66 | HSINT<='0' when pixel<6 and lines>=l1 and lines<=l2 else '1'; 67 | hline<=std_logic_vector(to_unsigned(lines,16)); 68 | 69 | process (sclk,EN) 70 | variable m78: natural range 0 to 31; 71 | variable lin, p16, pd4, pm4: natural range 0 to 1023; 72 | 73 | begin 74 | if rising_edge(sclk) and EN='0' then 75 | if vidc then 76 | if pixel=799 then 77 | pixel<=0; pix<=0; p6<=0; prc<=0; 78 | if lines<524 then lines<=lines+1; else lines<=0; end if; 79 | if lines=l1-1 then m8<=0; addr2<=vbase/2; else 80 | if m8=15 then m8<=0; addr2<=addr2+pno/2; else m8<=m8+1; end if; 81 | end if; 82 | else 83 | pixel<=pixel+1; 84 | end if; 85 | if (p6=0) and (pixel>=p1-1) and (pixel=l1 and lines=p1 and pixel=l1) and (lines=p1) and (pixel=p1 and pixel=l1 and lines<=l2 else '1'; 174 | hline<=std_logic_vector(to_unsigned(lines,16)); 175 | 176 | process (sclk,EN) 177 | 178 | variable pixm4: natural range 0 to 1023; 179 | variable pix: natural range 0 to 1023; 180 | 181 | begin 182 | if rising_edge(sclk) and EN='1' then 183 | if vidc then 184 | if (lines>=l1 and lines=p1 and pixell2 then 193 | m8<=0; addr2<=vbase/2; 194 | else 195 | if m8=1 then m8<=0; addr2<=addr2+pno/4; else m8<=1; end if; 196 | end if; 197 | else 198 | pixel<=pixel+1; 199 | end if; 200 | 201 | else ------ vidc false --------------------------------------- 202 | 203 | if (lines>=l1) and (lines=p1) and (pixel BRGB<=Q(15 downto 12); --end if; --Q(12)&Q(13)&Q(14)&Q(15); 212 | when 1 => BRGB<=Q(11 downto 8); --end if; --Q(8)&Q(9)&Q(10)&Q(11); 213 | when 2 => BRGB<=Q(7 downto 4); --end if; -- Q(4)&Q(5)&Q(6)&Q(7); 214 | when 3 => BRGB<=Q(3 downto 0); --end if; --Q(0)&Q(1)&Q(2)&Q(3); 215 | when others=> 216 | end case; 217 | pixm4:=pix mod 4; 218 | -- sprites 219 | end if; 220 | end if; --falling 221 | end process; 222 | 223 | 224 | end; 225 | 226 | 227 | ----------------------------------------------------------------------------- 228 | -- Multicolor Sprites for Lion Computer 229 | -- Theodoulos Liontakis (C) 2018 230 | 231 | Library ieee; 232 | USE ieee.std_logic_1164.all; 233 | --USE ieee.std_logic_unsigned.all ; 234 | USE ieee.numeric_std.all ; 235 | 236 | entity VideoSp is 237 | generic 238 | ( 239 | DATA_LINE : natural := 1 240 | ); 241 | port 242 | ( 243 | sclk,vclk: IN std_logic; 244 | R,G,B,BRI,SPDET: OUT std_logic; 245 | reset, pbuffer, dbuffer : IN std_logic; 246 | spaddr: OUT natural range 0 to 2047; 247 | SPQ: IN std_logic_vector(15 downto 0) 248 | ); 249 | end VideoSp; 250 | 251 | 252 | Architecture Behavior of VideoSp is 253 | 254 | constant sp1: natural:= 0; 255 | constant sp2: natural:= 256/2; 256 | constant sd1: natural:= 512/2; 257 | constant sd2: natural:= 2304/2; 258 | constant l1:natural:=74; 259 | constant lno:natural:=240; 260 | constant p1:natural :=142; 261 | constant pno:natural:=320; 262 | constant maxd:natural:=16; 263 | constant spno:natural:=14; 264 | constant p2:natural:=p1+pno*2; 265 | constant l2:natural:=l1+lno*2; 266 | 267 | type sprite_dim is array (0 to spno*4+3) of natural range 0 to 511; 268 | type sprite_line_data is array (spno downto 0) of std_logic_vector(63 downto 0); 269 | type dist is array (0 to spno) of natural range 0 to 4095; 270 | type sprite_enable is array (0 to spno) of std_logic; 271 | 272 | shared variable addr1: natural range 0 to 2047; 273 | shared variable lines: natural range 0 to 1023; 274 | shared variable det: std_logic:='0'; 275 | Signal vidc: boolean:=false; 276 | Signal SX,SY: sprite_dim; 277 | Signal SEN:sprite_enable; 278 | Signal pixel : natural range 0 to 1023; 279 | Signal sldata: sprite_line_data; 280 | 281 | begin 282 | vidc<=not vidc when rising_edge(vclk); 283 | spaddr<=addr1; 284 | SPDET<=det; 285 | --pm4<=pixel mod 4; 286 | --pd4<=pixel / 4; 287 | 288 | process (sclk,reset) 289 | 290 | variable BRGB: std_logic_vector(3 downto 0); 291 | variable d1,d2:dist; 292 | variable p16,datab: natural range 0 to 2047; 293 | variable pixi, lin, pm4,pd4: natural range 0 to 1023; 294 | variable blvec:std_logic_vector(3 downto 0); 295 | 296 | begin 297 | if rising_edge(sclk) then 298 | if (reset='0') then 299 | pixel<=6; lines:=0; det:='0'; 300 | if dbuffer='0' then datab:=sd1; else datab:=sd2; end if; 301 | elsif vidc then 302 | if (lines>=l1 and lines=p1 and pixel 306 | BRGB:=SLData(0)(3+d1(0) downto d1(0)); 307 | when "0001" => 308 | BRGB:=SLData(1)(3+d1(1) downto d1(1)); 309 | when "0010" => 310 | BRGB:=SLData(2)(3+d1(2) downto d1(2)); 311 | when "0011" => 312 | BRGB:=SLData(3)(3+d1(3) downto d1(3)); 313 | when "0100" => 314 | BRGB:=SLData(4)(3+d1(4) downto d1(4)); 315 | when "0101" => 316 | BRGB:=SLData(5)(3+d1(5) downto d1(5)); 317 | when "0110" => 318 | BRGB:=SLData(6)(3+d1(6) downto d1(6)); 319 | when "0111" => 320 | BRGB:=SLData(7)(3+d1(7) downto d1(7)); 321 | when "1000" => 322 | BRGB:=SLData(8)(3+d1(8) downto d1(8)); 323 | when "1001" => 324 | BRGB:=SLData(9)(3+d1(9) downto d1(9)); 325 | when "1010" => 326 | BRGB:=SLData(10)(3+d1(10) downto d1(10)); 327 | when "1011" => 328 | BRGB:=SLData(11)(3+d1(11) downto d1(11)); 329 | when "1100" => 330 | BRGB:=SLData(12)(3+d1(12) downto d1(12)); 331 | when "1101" => 332 | BRGB:=SLData(13)(3+d1(13) downto d1(13)); 333 | when "1110" => 334 | BRGB:=SLData(14)(3+d1(14) downto d1(14)); 335 | when others => 336 | det:='0'; BRGB:="0000"; 337 | end case; 338 | BRI<=BRGB(3); R<=BRGB(2); G<=BRGB(1); B<=BRGB(0); 339 | else 340 | det:='0'; 341 | end if; 342 | 343 | if pixel=799 then 344 | pixel<=0; p16:=0; 345 | if lines<524 then lines:=lines+1; else lines:=0; end if; 346 | else 347 | pixel<=pixel+1; pixi:=(pixel-p1)/2; 348 | end if; 349 | --pm4:= pixel mod 4; pd4:=pixel/4; 350 | if (lines=DATA_LINE) and (pixel=l1 and lines 359 | SLData(pd4)(15 downto 0)<=SPQ(3 downto 0)&SPQ(7 downto 4)&SPQ(11 downto 8)&SPQ(15 downto 12); 360 | when 1 => 361 | SLData(pd4)(31 downto 16)<=SPQ(3 downto 0)&SPQ(7 downto 4)&SPQ(11 downto 8)&SPQ(15 downto 12); 362 | when 2 => 363 | SLData(pd4)(47 downto 32)<=SPQ(3 downto 0)&SPQ(7 downto 4)&SPQ(11 downto 8)&SPQ(15 downto 12); 364 | when others => 365 | SLData(pd4)(63 downto 48)<=SPQ(3 downto 0)&SPQ(7 downto 4)&SPQ(11 downto 8)&SPQ(15 downto 12); 366 | end case; 367 | end if; 368 | blvec:="1111"; 369 | else ------ vidc false --------------------------------------- 370 | lin:=(lines-l1)/2; 371 | d1(0):=(pixi-SX(0))*4; d2(0):=lin-SY(0); 372 | d1(1):=(pixi-SX(1))*4; d2(1):=lin-SY(1); 373 | d1(2):=(pixi-SX(2))*4; d2(2):=lin-SY(2); 374 | d1(3):=(pixi-SX(3))*4; d2(3):=lin-SY(3); 375 | d1(4):=(pixi-SX(4))*4; d2(4):=lin-SY(4); 376 | d1(5):=(pixi-SX(5))*4; d2(5):=lin-SY(5); 377 | d1(6):=(pixi-SX(6))*4; d2(6):=lin-SY(6); 378 | d1(7):=(pixi-SX(7))*4; d2(7):=lin-SY(7); 379 | d1(8):=(pixi-SX(8))*4; d2(8):=lin-SY(8); 380 | d1(9):=(pixi-SX(9))*4; d2(9):=lin-SY(9); 381 | d1(10):=(pixi-SX(10))*4; d2(10):=lin-SY(10); 382 | d1(11):=(pixi-SX(11))*4; d2(11):=lin-SY(11); 383 | d1(12):=(pixi-SX(12))*4; d2(12):=lin-SY(12); 384 | d1(13):=(pixi-SX(13))*4; d2(13):=lin-SY(13); 385 | d1(14):=(pixi-SX(14))*4; d2(14):=lin-SY(14); 386 | pm4:= pixel mod 4; pd4:=pixel/4; 387 | if (pixel<(spno*4+4)) then 388 | if (lines=DATA_LINE) then 389 | if pbuffer='0' then addr1:=(sp1+pixel); else addr1:=(sp2+pixel); end if; 390 | end if; 391 | if (lines>=l1) and (lines'0'); 455 | elsif Clk'EVENT AND Clk = '1' then 456 | if wr='0' then 457 | f:=Q; 458 | if (harmonic<9) then 459 | f2:=Q-std_logic_vector(shift_right(unsigned(Q),to_integer(unsigned(harmonic)))); 460 | -- f2:="000"&(Q(12 downto 0)-std_logic_vector(shift_right(unsigned(Q(12 downto 0)),to_integer(unsigned(harmonic))))); 461 | -- elsif (harmonic<15) then 462 | -- f2:="000"&(std_logic_vector(shift_right(unsigned(Q(12 downto 0)),1))+ 463 | -- std_logic_vector(shift_right(unsigned(Q(12 downto 0)),to_integer(unsigned(harmonic-6))))); 464 | else 465 | f2:=Q+std_logic_vector(shift_right(unsigned(Q),to_integer(unsigned(harmonic-8)))); 466 | -- f2:="000"&(Q(12 downto 0)-std_logic_vector(shift_right(unsigned(Q(12 downto 0)),2)) 467 | -- -std_logic_vector(shift_right(unsigned(Q(12 downto 0)),4))); 468 | end if; 469 | play<='1'; 470 | CASE f(15 downto 13) is 471 | when "000" => 472 | dur<=3125; -- 0.015 sec 473 | when "001" => 474 | dur<=6250; -- 0.031 sec 475 | when "010" => 476 | dur<=12500; -- 0.062 477 | when "011" => 478 | dur<=25000; -- 0.125 479 | when "100" => 480 | dur<=50000; -- 0.25 sec 481 | when "101" => 482 | dur<=100000; -- 0.5 sec 483 | when "110" => 484 | dur<=200000; -- 1 485 | when others => 486 | dur<=400000; -- 2 487 | end case; 488 | c1<=(others => '0'); 489 | else 490 | c1<=c1+1; 491 | if c3=0 and dur/=0 then dur<=dur-1; end if; 492 | end if; 493 | if (Aud='1' or Aud2='1') and c1(7 downto 0) '0'); c3<=0; c4<=(others => '0'); play<='0'; 503 | else 504 | 505 | if c2=f(12 downto 0) then 506 | if c2/="0000000000000" then temp<=not temp; end if; 507 | c2<=(others => '0'); 508 | end if; 509 | if vol > to_integer(unsigned(c2(7 downto 0))) then Aud<=temp; else Aud<='0'; end if; 510 | 511 | if c4=f2(12 downto 0) then 512 | if c4/="000000000000" and harmonic>0 then temp2<=not temp2; end if; 513 | c4<=(others => '0'); 514 | end if; 515 | if vol > to_integer(unsigned(c4(7 downto 0))) then Aud2<=temp2; else Aud2<='0'; end if; 516 | 517 | end if; 518 | if i=399 then i<=0; count<=count+'1'; else i<=i+1; end if; 519 | else 520 | end if; 521 | end if; 522 | end process ; 523 | end; 524 | 525 | 526 | 527 | ------------------------------------------------------- 528 | 529 | library ieee; 530 | use ieee.std_logic_1164.all; 531 | USE ieee.std_logic_unsigned.all ; 532 | USE ieee.numeric_std.all ; 533 | 534 | entity lfsr_II is 535 | port ( 536 | cout :out std_logic; -- Output of the counter 537 | clk :in std_logic; -- Input rlock 538 | reset :in std_logic; -- Input reset 539 | Vol :in std_logic_vector(7 downto 0) 540 | --bw :in std_logic_vector(15 downto 0) --band width 541 | ); 542 | end entity; 543 | 544 | architecture rtl of lfsr_II is 545 | signal count: std_logic_vector (19 downto 0); 546 | signal linear_feedback,temp: std_logic:='0'; 547 | begin 548 | linear_feedback <= not(count(19) xor count(2)); 549 | 550 | process (clk, reset) 551 | variable cnt: natural range 0 to 512*1024; 552 | begin 553 | if (reset = '1') then 554 | count <= (others=>'0'); cnt:=0; 555 | elsif (rising_edge(clk)) then 556 | count <= ( count(18) & count(17)& count(16) & count(15)& 557 | count(14) & count(13) & count(12) & count(11)& 558 | count(10) & count(9) & count(8) & count(7)& 559 | count(6) & count(5) & count(4) & count(3) 560 | & count(2) & count(1) & count(0) & linear_feedback); 561 | if vol > to_integer(unsigned(count(7 downto 0))) then temp<=count(19); else temp<='0'; end if; 562 | end if; 563 | end process; 564 | cout <=temp; -- count(19) when vol > to_integer(unsigned(count(7 downto 0))); 565 | end architecture; 566 | 567 | ----------------------------------------------------------------------------- 568 | 569 | ------------------------------------------------------- 570 | -- Design Name : lfsr 571 | -- File Name : lfsr.vhd 572 | -- Function : Linear feedback shift register 573 | -- Coder : Deepak Kumar Tala (Verilog) 574 | -- Translator : Alexander H Pham (VHDL) 575 | -- adapted to 1bit stream, 20bit counter, band width by Theodoulos Liontakis 576 | ------------------------------------------------------- 577 | library ieee; 578 | use ieee.std_logic_1164.all; 579 | USE ieee.std_logic_unsigned.all ; 580 | USE ieee.numeric_std.all ; 581 | 582 | entity lfsr is 583 | port ( 584 | cout :out std_logic; -- Output of the counter 585 | clk :in std_logic; -- Input rlock 586 | reset :in std_logic; -- Input reset 587 | Vol :in std_logic_vector(7 downto 0); 588 | bw :in std_logic_vector(15 downto 0) --band width 589 | ); 590 | end entity; 591 | 592 | architecture rtl of lfsr is 593 | signal count :std_logic_vector (19 downto 0); 594 | signal linear_feedback,temp :std_logic:='0'; 595 | begin 596 | linear_feedback <= not(count(19) xor count(2)); 597 | 598 | process (clk, reset) 599 | variable cnt: natural range 0 to 512*1024; 600 | begin 601 | if (reset = '1') then 602 | count <= (others=>'0'); cnt:=0; 603 | elsif (rising_edge(clk)) then 604 | cnt:=cnt+1; 605 | if cnt=to_integer(unsigned(bw&"111")) then 606 | count <= ( count(18) & count(17)& count(16) & count(15)& 607 | count(14) & count(13) & count(12) & count(11)& 608 | count(10) & count(9) & count(8) & count(7)& 609 | count(6) & count(5) & count(4) & count(3) 610 | & count(2) & count(1) & count(0) & linear_feedback); 611 | if vol > to_integer(unsigned(count(7 downto 0))) then temp<=count(19); else temp<='0'; end if; 612 | cnt:=0; 613 | end if; 614 | end if; 615 | end process; 616 | cout <=temp; -- count(19) when vol > to_integer(unsigned(count(7 downto 0))); 617 | end architecture; 618 | -------------------------------------------------------------------------------- /javag/JGOptimizer.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/JGOptimizer.exe -------------------------------------------------------------------------------- /javag/cyggcc_s-seh-1.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/cyggcc_s-seh-1.dll -------------------------------------------------------------------------------- /javag/cygstdc++-6.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/cygstdc++-6.dll -------------------------------------------------------------------------------- /javag/cygwin1.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/cygwin1.dll -------------------------------------------------------------------------------- /javag/galax.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/galax.bin -------------------------------------------------------------------------------- /javag/java_grinder.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/java_grinder.exe -------------------------------------------------------------------------------- /javag/make.txt: -------------------------------------------------------------------------------- 1 | 2 | To make the astro4.bin (or any other bin from an asm file) you needed to run Astro in Lion : 3 | 4 | javac astro4S.class 5 | java_grinder astro4S.class astro4S.asm Lionsys 6 | jgoptimizer astro4S.asm astro4.asm 7 | 8 | Then open astro4.asm with lionasm and compile 9 | 10 | The code produced is relalocatable and can be loaded and run from anyware in memory range btop (about 17000) to 48000-bin_file_size. 11 | The function btop always returns the first free andress after the basic program area. 12 | 13 | A convinient way to load a binary and execute it is: 14 | 15 | LCODE "astro4",btop 16 | RCODE btop 17 | 18 | -------------------------------------------------------------------------------- /javag/net/mikekohn/java_grinder/JavaGrinder.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/net/mikekohn/java_grinder/JavaGrinder.jar -------------------------------------------------------------------------------- /javag/net/mikekohn/java_grinder/Lionsys.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/net/mikekohn/java_grinder/Lionsys.class -------------------------------------------------------------------------------- /javag/net/mikekohn/java_grinder/Lionsys.java: -------------------------------------------------------------------------------- 1 | /** 2 | * Java Grinder 3 | * Author: Michael Kohn 4 | * Email: mike@mikekohn.net 5 | * Web: http://www.naken.cc/ 6 | * License: GPL 7 | * 8 | * Copyright 2014-2016 by Michael Kohn 9 | * 10 | */ 11 | 12 | /* 13 | * Lionsys Theodoulos Liontakis 14 | */ 15 | 16 | package net.mikekohn.java_grinder; 17 | 18 | abstract public class Lionsys 19 | { 20 | 21 | protected Lionsys() { } 22 | 23 | public static void cls() { } 24 | public static void beep() { } 25 | public static void color(byte foreground, byte background, byte border) { } 26 | public static void screen(byte mode) { } 27 | public static void width(byte w) { } 28 | public static void keyOn() { } 29 | public static void keyOff() { } 30 | public static void fillVRAM(int c, int len, int addr) { } 31 | public static void copyVRAM(int len, int source, int dest) { } 32 | public static void putChar(char c) { } 33 | public static void putChar(int y, int x, char c) { } 34 | public static void setCursor(byte column, byte line) { } 35 | } 36 | -------------------------------------------------------------------------------- /javag/pacman.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lliont/Lionasm/be03859065dd2e7e174902fe537e4c6dee5e4288/javag/pacman.bin --------------------------------------------------------------------------------