├── FPGA-cameral ├── FPGA-cameral.hw │ └── FPGA-cameral.lpr ├── FPGA-cameral.ip_user_files │ ├── README.txt │ ├── ip │ │ ├── blk_mem_gen_0 │ │ │ ├── blk_mem_gen_0.veo │ │ │ ├── blk_mem_gen_0.vho │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ └── blk_mem_gen_0_stub.vhdl │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0.veo │ │ │ ├── clk_wiz_0_stub.v │ │ │ └── clk_wiz_0_stub.vhdl │ ├── ipstatic │ │ ├── blk_mem_gen_v8_3_3 │ │ │ └── simulation │ │ │ │ └── blk_mem_gen_v8_3.v │ │ └── clk_wiz_v5_3_1 │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ └── mmcm_pll_drp_func_us_pll.vh │ ├── mem_init_files │ │ └── summary.log │ └── sim_scripts │ │ ├── blk_mem_gen_0 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── run.f │ │ │ └── summary.log │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── summary.log │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── summary.log │ │ │ ├── vhdl.prj │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ └── clk_wiz_0 │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ ├── modelsim │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ └── xsim │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vhdl.prj │ │ ├── vlog.prj │ │ └── xsim.ini ├── FPGA-cameral.runs │ ├── blk_mem_gen_0_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── blk_mem_gen_0.dcp │ │ ├── blk_mem_gen_0.tcl │ │ ├── blk_mem_gen_0.vds │ │ ├── blk_mem_gen_0_utilization_synth.pb │ │ ├── blk_mem_gen_0_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── clk_wiz_0_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ │ └── clk_wiz_0_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.tcl │ │ ├── clk_wiz_0.vds │ │ ├── clk_wiz_0_utilization_synth.pb │ │ ├── clk_wiz_0_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── camera_top.bit │ │ ├── camera_top.tcl │ │ ├── camera_top.vdi │ │ ├── camera_top_clock_utilization_routed.rpt │ │ ├── camera_top_control_sets_placed.rpt │ │ ├── camera_top_drc_opted.rpt │ │ ├── camera_top_drc_routed.pb │ │ ├── camera_top_drc_routed.rpt │ │ ├── camera_top_io_placed.rpt │ │ ├── camera_top_opt.dcp │ │ ├── camera_top_placed.dcp │ │ ├── camera_top_power_routed.rpt │ │ ├── camera_top_power_routed.rpx │ │ ├── camera_top_power_summary_routed.pb │ │ ├── camera_top_route_status.pb │ │ ├── camera_top_route_status.rpt │ │ ├── camera_top_routed.dcp │ │ ├── camera_top_timing_summary_routed.rpt │ │ ├── camera_top_timing_summary_routed.rpx │ │ ├── camera_top_utilization_placed.pb │ │ ├── camera_top_utilization_placed.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── camera_top_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── camera_top.dcp │ │ ├── camera_top.tcl │ │ ├── camera_top.vds │ │ ├── camera_top_utilization_synth.pb │ │ ├── camera_top_utilization_synth.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── FPGA-cameral.srcs │ └── sources_1 │ │ └── ip │ │ ├── blk_mem_gen_0 │ │ ├── blk_mem_gen_0.dcp │ │ ├── blk_mem_gen_0.veo │ │ ├── blk_mem_gen_0.vho │ │ ├── blk_mem_gen_0.xci │ │ ├── blk_mem_gen_0.xml │ │ ├── blk_mem_gen_0_ooc.xdc │ │ ├── blk_mem_gen_0_sim_netlist.v │ │ ├── blk_mem_gen_0_sim_netlist.vhdl │ │ ├── blk_mem_gen_0_stub.v │ │ ├── blk_mem_gen_0_stub.vhdl │ │ ├── blk_mem_gen_v8_3_3 │ │ │ ├── hdl │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ └── simulation │ │ │ │ └── blk_mem_gen_v8_3.v │ │ ├── doc │ │ │ └── blk_mem_gen_v8_3_changelog.txt │ │ ├── misc │ │ │ └── blk_mem_gen_v8_3.vhd │ │ ├── sim │ │ │ └── blk_mem_gen_0.v │ │ ├── summary.log │ │ └── synth │ │ │ └── blk_mem_gen_0.vhd │ │ └── clk_wiz_0 │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.v │ │ ├── clk_wiz_0.veo │ │ ├── clk_wiz_0.xci │ │ ├── clk_wiz_0.xdc │ │ ├── clk_wiz_0.xml │ │ ├── clk_wiz_0_board.xdc │ │ ├── clk_wiz_0_clk_wiz.v │ │ ├── clk_wiz_0_ooc.xdc │ │ ├── clk_wiz_0_sim_netlist.v │ │ ├── clk_wiz_0_sim_netlist.vhdl │ │ ├── clk_wiz_0_stub.v │ │ ├── clk_wiz_0_stub.vhdl │ │ ├── clk_wiz_v5_3_1 │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ └── mmcm_pll_drp_func_us_pll.vh │ │ └── doc │ │ └── clk_wiz_v5_3_changelog.txt └── FPGA-cameral.xpr ├── LICENSE ├── README resource ├── 图1.png ├── 图2.png ├── 图3.png ├── 图4.png ├── 图5.png ├── 图6.png ├── 图7.png ├── 图8.png ├── 图9.png ├── 手机.png ├── 板子.png └── 设计图.png ├── README.md ├── bit └── camera_top.bit ├── code ├── bluetooth.v ├── camera_get_pic.v ├── camera_init.v ├── camera_top.v ├── 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