├── LICENSE ├── README.md ├── docs ├── demo.gif ├── labft-arch.png └── systolic-arch.png ├── generator ├── .gitignore ├── RTL │ ├── dont_touch │ │ ├── generated │ │ │ ├── abcd_n_acc_n.sv │ │ │ ├── abcde_dot_nxn.sv │ │ │ ├── acc_nxn.sv │ │ │ ├── array.sv │ │ │ ├── dot_nxn.sv │ │ │ ├── e_n_acc_n.sv │ │ │ ├── labft.sv │ │ │ ├── n_acc_n.sv │ │ │ ├── top.sv │ │ │ └── wxyz_acc_nxn.sv │ │ ├── generic │ │ │ ├── 7series │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro_wrapper.sv │ │ │ │ └── mul.sv │ │ │ ├── add.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ └── ultrascale │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro_wrapper.sv │ │ │ │ └── mul.sv │ │ └── labft │ │ │ ├── acc_n.sv │ │ │ ├── e_move_nxn.sv │ │ │ ├── labft_error_detector.sv │ │ │ └── mac_n.sv │ └── import_me │ │ ├── abcd_n_acc_n.sv │ │ ├── abcde_dot_nxn.sv │ │ ├── acc_n.sv │ │ ├── acc_nxn.sv │ │ ├── add.sv │ │ ├── array.sv │ │ ├── dff.sv │ │ ├── dff_enbl.sv │ │ ├── dot_nxn.sv │ │ ├── dsp_macro.bd │ │ ├── dsp_macro_wrapper.sv │ │ ├── e_move_nxn.sv │ │ ├── e_n_acc_n.sv │ │ ├── fsm.sv │ │ ├── int8_pe.sv │ │ ├── int8_quad_mac.sv │ │ ├── labft.sv │ │ ├── labft_error_detector.sv │ │ ├── mac_n.sv │ │ ├── mul.sv │ │ ├── n_acc_n.sv │ │ ├── top.sv │ │ └── wxyz_acc_nxn.sv ├── __pycache__ │ ├── arrayGenerator.cpython-35.pyc │ ├── fileHandler.cpython-35.pyc │ ├── labftGenerator.cpython-35.pyc │ ├── settings.cpython-35.pyc │ └── topGenerator.cpython-35.pyc ├── arrayGenerator.py ├── arrayGenerator.pyc ├── fileHandler.py ├── fileHandler.pyc ├── labftGenerator.py ├── labftGenerator.pyc ├── main.py ├── settings.py ├── settings.pyc ├── topGenerator.py └── topGenerator.pyc └── validation ├── zynq_7000 ├── info.txt └── systolic_14x14_ip │ ├── rundir │ ├── post_place_clock_util.rpt │ ├── post_place_timing_summary.rpt │ ├── post_place_util.rpt │ ├── post_route_drc.rpt │ ├── post_route_power.rpt │ ├── post_route_status.rpt │ ├── post_route_timing_summary.rpt │ ├── post_route_util.rpt │ ├── post_synth_timing_summary.rpt │ └── post_synth_util.rpt │ ├── systolic_14x14_ip │ ├── systolic_14x14_ip.cache │ │ ├── ip │ │ │ └── 2018.1 │ │ │ │ ├── 80dcd78ae577ecfb.logs │ │ │ │ └── runme.log │ │ │ │ └── 80dcd78ae577ecfb │ │ │ │ ├── 80dcd78ae577ecfb.xci │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ └── webtalk_pa.xml │ ├── systolic_14x14_ip.hw │ │ └── systolic_14x14_ip.lpr │ ├── systolic_14x14_ip.ip_user_files │ │ ├── README.txt │ │ └── sim_scripts │ │ │ └── import_me │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ ├── systolic_14x14_ip.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── dont_touch.xdc │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── systolic_14x14_ip.srcs │ │ ├── constrs_1 │ │ │ └── new │ │ │ │ └── xdc.xdc │ │ └── sources_1 │ │ │ ├── bd │ │ │ └── import_me │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro.bxml │ │ │ │ ├── dsp_macro_ooc.xdc │ │ │ │ ├── hdl │ │ │ │ └── dsp_macro_wrapper.v │ │ │ │ ├── hw_handoff │ │ │ │ ├── dsp_macro.hwh │ │ │ │ └── dsp_macro_bd.tcl │ │ │ │ ├── ip │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ │ ├── sim │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ │ └── synth │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ ├── ipshared │ │ │ │ ├── 9743 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ │ ├── 442e │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ ├── a5f8 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ └── da55 │ │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── sim │ │ │ │ └── dsp_macro.v │ │ │ │ └── synth │ │ │ │ ├── dsp_macro.hwdef │ │ │ │ └── dsp_macro.v │ │ │ └── imports │ │ │ └── import_me │ │ │ ├── add.sv │ │ │ ├── array.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── dsp_macro_wrapper.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ ├── mul.sv │ │ │ └── top.sv │ └── systolic_14x14_ip.xpr │ └── tcl.tcl └── zynq_us+ ├── info.txt └── systolic_32x32_ip ├── rundir ├── post_place_clock_util.rpt ├── post_place_timing_summary.rpt ├── post_place_util.rpt ├── post_route_drc.rpt ├── post_route_power.rpt ├── post_route_status.rpt ├── post_route_timing_summary.rpt ├── post_route_util.rpt ├── post_synth_timing_summary.rpt └── post_synth_util.rpt ├── systolic_32x32_ip ├── systolic_32x32_ip.cache │ ├── ip │ │ └── 2018.1 │ │ │ ├── e16efbb83c6bac58.logs │ │ │ └── runme.log │ │ │ └── e16efbb83c6bac58 │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ └── e16efbb83c6bac58.xci │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ └── webtalk_pa.xml ├── systolic_32x32_ip.hw │ └── systolic_32x32_ip.lpr ├── systolic_32x32_ip.ip_user_files │ ├── README.txt │ └── sim_scripts │ │ └── import_me │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ ├── xcelium │ │ ├── README.txt │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vhdl.prj │ │ └── vlog.prj ├── systolic_32x32_ip.runs │ ├── .jobs │ │ └── vrs_config_1.xml │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── dont_touch.xdc │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── systolic_32x32_ip.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── xdc.xdc │ └── sources_1 │ │ ├── bd │ │ └── import_me │ │ │ ├── dsp_macro.bd │ │ │ ├── dsp_macro.bxml │ │ │ ├── dsp_macro_ooc.xdc │ │ │ ├── hdl │ │ │ └── dsp_macro_wrapper.v │ │ │ ├── hw_handoff │ │ │ ├── dsp_macro.hwh │ │ │ └── dsp_macro_bd.tcl │ │ │ ├── ip │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ ├── sim │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ └── synth │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ ├── ipshared │ │ │ ├── 9743 │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ ├── 442e │ │ │ │ └── hdl │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ ├── a5f8 │ │ │ │ └── hdl │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ └── da55 │ │ │ │ └── hdl │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ ├── sim │ │ │ └── dsp_macro.v │ │ │ └── synth │ │ │ ├── dsp_macro.hwdef │ │ │ └── dsp_macro.v │ │ └── imports │ │ └── import_me │ │ ├── add.sv │ │ ├── array.sv │ │ ├── dff.sv │ │ ├── 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