├── .gitattributes ├── .gitignore ├── LICENSE ├── README.md ├── docs ├── architecture.png ├── demo.gif └── testbench.png ├── example ├── info.txt ├── systolic_2x2_ip │ ├── component.xml │ ├── systolic_2x2_ip.cache │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── systolic_2x2_ip.hw │ │ └── systolic_2x2_ip.lpr │ ├── systolic_2x2_ip.ip_user_files │ │ ├── README.txt │ │ └── sim_scripts │ │ │ └── import_me │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ ├── systolic_2x2_ip.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ └── xsim │ │ │ ├── compile.sh │ │ │ ├── elaborate.sh │ │ │ ├── glbl.v │ │ │ ├── simulate.sh │ │ │ ├── tb_array.tcl │ │ │ ├── tb_array_behav.wdb │ │ │ ├── tb_array_vhdl.prj │ │ │ ├── tb_array_vlog.prj │ │ │ ├── webtalk.jou │ │ │ ├── webtalk_2249.backup.jou │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── tb_array_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── obj │ │ │ │ │ ├── xsim_0.lnx64.o │ │ │ │ │ ├── xsim_1.c │ │ │ │ │ └── xsim_1.lnx64.o │ │ │ │ ├── webtalk │ │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rlx │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimSettings.ini │ │ │ │ └── xsimk │ │ │ ├── xil_defaultlib │ │ │ │ ├── add.sdb │ │ │ │ ├── array.sdb │ │ │ │ ├── dff.sdb │ │ │ │ ├── dff_enbl.sdb │ │ │ │ ├── dsp_macro.sdb │ │ │ │ ├── dsp_macro_wrapper.sdb │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── int8_pe.sdb │ │ │ │ ├── int8_quad_mac.sdb │ │ │ │ ├── mul.sdb │ │ │ │ ├── tb_array.sdb │ │ │ │ └── xil_defaultlib.rlx │ │ │ └── xsim.svtype │ │ │ ├── xsim.ini │ │ │ ├── xsim.ini.bak │ │ │ ├── xvhdl.pb │ │ │ └── xvlog.pb │ ├── systolic_2x2_ip.srcs │ │ ├── sim_1 │ │ │ └── new │ │ │ │ ├── tb_array.sv │ │ │ │ └── tb_top.sv │ │ └── sources_1 │ │ │ ├── bd │ │ │ └── import_me │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro.bxml │ │ │ │ ├── dsp_macro_ooc.xdc │ │ │ │ ├── hdl │ │ │ │ └── dsp_macro_wrapper.v │ │ │ │ ├── hw_handoff │ │ │ │ ├── dsp_macro.hwh │ │ │ │ └── dsp_macro_bd.tcl │ │ │ │ ├── ip │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ │ └── sim │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ ├── ipshared │ │ │ │ ├── 9743 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ │ ├── 442e │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ ├── a5f8 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ └── da55 │ │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── sim │ │ │ │ └── dsp_macro.v │ │ │ │ └── synth │ │ │ │ ├── dsp_macro.hwdef │ │ │ │ └── dsp_macro.v │ │ │ └── imports │ │ │ └── import_me │ │ │ ├── add.sv │ │ │ ├── array.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── dsp_macro_wrapper.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ ├── mem.sv │ │ │ ├── mul.sv │ │ │ └── top.sv │ ├── systolic_2x2_ip.xpr │ ├── tb_array_behav.wcfg │ ├── tb_top_behav.wcfg │ └── xgui │ │ ├── systolic_2x2_ip_v1_0.tcl │ │ └── top_v1_0.tcl └── systolic_2x2_system.zip ├── generator ├── RTL │ ├── dont_touch │ │ ├── generated │ │ │ ├── array.sv │ │ │ └── top.sv │ │ └── generic │ │ │ ├── 7series │ │ │ ├── dsp_macro.bd │ │ │ ├── dsp_macro_wrapper.sv │ │ │ └── mul.sv │ │ │ ├── add.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ ├── mem.sv │ │ │ └── ultrascale │ │ │ ├── dsp_macro.bd │ │ │ ├── dsp_macro_wrapper.sv │ │ │ └── mul.sv │ └── import_me │ │ ├── add.sv │ │ ├── array.sv │ │ ├── dff.sv │ │ ├── dff_enbl.sv │ │ ├── dsp_macro.bd │ │ ├── dsp_macro_wrapper.sv │ │ ├── fsm.sv │ │ ├── int8_pe.sv │ │ ├── int8_quad_mac.sv │ │ ├── mem.sv │ │ ├── mul.sv │ │ └── top.sv ├── arrayGenerator.py ├── fileHandler.py ├── main.py ├── settings.py └── topGenerator.py └── validation ├── zynq_7000 ├── info.txt └── ooc │ ├── systolic_14x14_ip │ ├── rundir │ │ ├── post_place_clock_util.rpt │ │ ├── post_place_timing_summary.rpt │ │ ├── post_place_util.rpt │ │ ├── post_route_drc.rpt │ │ ├── post_route_power.rpt │ │ ├── post_route_status.rpt │ │ ├── post_route_timing_summary.rpt │ │ ├── post_route_util.rpt │ │ ├── post_synth_timing_summary.rpt │ │ └── post_synth_util.rpt │ ├── systolic_14x14_ip │ │ ├── systolic_14x14_ip.cache │ │ │ ├── ip │ │ │ │ └── 2018.1 │ │ │ │ │ └── 80dcd78ae577ecfb │ │ │ │ │ ├── 80dcd78ae577ecfb.xci │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ └── wt │ │ │ │ ├── gui_handlers.wdf │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ ├── project.wpc │ │ │ │ ├── synthesis.wdf │ │ │ │ └── webtalk_pa.xml │ │ ├── systolic_14x14_ip.hw │ │ │ └── systolic_14x14_ip.lpr │ │ ├── systolic_14x14_ip.ip_user_files │ │ │ ├── README.txt │ │ │ └── sim_scripts │ │ │ │ └── import_me │ │ │ │ ├── README.txt │ │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── compile.do │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── dsp_macro.udo │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── run.f │ │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── compile.do │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── dsp_macro.udo │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── compile.do │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── dsp_macro.udo │ │ │ │ ├── elaborate.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── compile.do │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── dsp_macro.udo │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── simulate.do │ │ │ │ ├── xcelium │ │ │ │ ├── README.txt │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── run.f │ │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── cmd.tcl │ │ │ │ ├── dsp_macro.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── vhdl.prj │ │ │ │ └── vlog.prj │ │ ├── systolic_14x14_ip.runs │ │ │ ├── .jobs │ │ │ │ └── vrs_config_1.xml │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ ├── .vivado.begin.rst │ │ │ │ ├── .vivado.end.rst │ │ │ │ ├── ISEWrap.js │ │ │ │ ├── ISEWrap.sh │ │ │ │ ├── __synthesis_is_complete__ │ │ │ │ ├── dont_touch.xdc │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ │ │ ├── gen_run.xml │ │ │ │ ├── htr.txt │ │ │ │ ├── project.wdf │ │ │ │ ├── rundef.js │ │ │ │ ├── runme.bat │ │ │ │ ├── runme.sh │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.pb │ │ ├── systolic_14x14_ip.srcs │ │ │ ├── constrs_1 │ │ │ │ └── new │ │ │ │ │ └── xdc.xdc │ │ │ └── sources_1 │ │ │ │ ├── bd │ │ │ │ └── import_me │ │ │ │ │ ├── dsp_macro.bd │ │ │ │ │ ├── dsp_macro.bxml │ │ │ │ │ ├── dsp_macro_ooc.xdc │ │ │ │ │ ├── hdl │ │ │ │ │ └── dsp_macro_wrapper.v │ │ │ │ │ ├── hw_handoff │ │ │ │ │ ├── dsp_macro.hwh │ │ │ │ │ └── dsp_macro_bd.tcl │ │ │ │ │ ├── ip │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ │ │ ├── sim │ │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ │ │ └── synth │ │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ │ ├── ipshared │ │ │ │ │ ├── 9743 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ │ │ ├── 442e │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ │ ├── a5f8 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ │ └── da55 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ │ ├── sim │ │ │ │ │ └── dsp_macro.v │ │ │ │ │ └── synth │ │ │ │ │ ├── dsp_macro.hwdef │ │ │ │ │ └── dsp_macro.v │ │ │ │ └── imports │ │ │ │ └── import_me │ │ │ │ ├── add.sv │ │ │ │ ├── array.sv │ │ │ │ ├── dff.sv │ │ │ │ ├── dff_enbl.sv │ │ │ │ ├── dsp_macro_wrapper.sv │ │ │ │ ├── fsm.sv │ │ │ │ ├── int8_pe.sv │ │ │ │ ├── int8_quad_mac.sv │ │ │ │ ├── mem.sv │ │ │ │ ├── mul.sv │ │ │ │ └── top.sv │ │ └── systolic_14x14_ip.xpr │ └── tcl.tcl │ └── systolic_8x8_ip │ ├── rundir │ ├── post_place_clock_util.rpt │ ├── post_place_timing_summary.rpt │ ├── post_place_util.rpt │ ├── post_route_drc.rpt │ ├── post_route_power.rpt │ ├── post_route_status.rpt │ ├── post_route_timing_summary.rpt │ ├── post_route_util.rpt │ ├── post_synth_timing_summary.rpt │ └── post_synth_util.rpt │ ├── systolic_8x8_ip │ ├── systolic_8x8_ip.cache │ │ ├── ip │ │ │ └── 2018.1 │ │ │ │ └── 80dcd78ae577ecfb │ │ │ │ ├── 80dcd78ae577ecfb.xci │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ └── webtalk_pa.xml │ ├── systolic_8x8_ip.hw │ │ └── systolic_8x8_ip.lpr │ ├── systolic_8x8_ip.ip_user_files │ │ ├── README.txt │ │ └── sim_scripts │ │ │ └── import_me │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ ├── systolic_8x8_ip.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── dont_touch.xdc │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── systolic_8x8_ip.srcs │ │ ├── constrs_1 │ │ │ └── new │ │ │ │ └── xdc.xdc │ │ └── sources_1 │ │ │ ├── bd │ │ │ └── import_me │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro.bxml │ │ │ │ ├── dsp_macro_ooc.xdc │ │ │ │ ├── hdl │ │ │ │ └── dsp_macro_wrapper.v │ │ │ │ ├── hw_handoff │ │ │ │ ├── dsp_macro.hwh │ │ │ │ └── dsp_macro_bd.tcl │ │ │ │ ├── ip │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ │ ├── sim │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ │ └── synth │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ ├── ipshared │ │ │ │ ├── 9743 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ │ ├── 442e │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ ├── a5f8 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ └── da55 │ │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── sim │ │ │ │ └── dsp_macro.v │ │ │ │ └── synth │ │ │ │ ├── dsp_macro.hwdef │ │ │ │ └── dsp_macro.v │ │ │ └── imports │ │ │ └── import_me │ │ │ ├── add.sv │ │ │ ├── array.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── dsp_macro_wrapper.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ ├── mem.sv │ │ │ ├── mul.sv │ │ │ └── top.sv │ └── systolic_8x8_ip.xpr │ └── tcl.tcl └── zynq_us+ ├── info.txt └── ooc ├── systolic_14x14_ip ├── rundir │ ├── post_place_clock_util.rpt │ ├── post_place_timing_summary.rpt │ ├── post_place_util.rpt │ ├── post_route_drc.rpt │ ├── post_route_power.rpt │ ├── post_route_status.rpt │ ├── post_route_timing_summary.rpt │ ├── post_route_util.rpt │ ├── post_synth_timing_summary.rpt │ └── post_synth_util.rpt ├── systolic_14x14_ip │ ├── systolic_14x14_ip.cache │ │ ├── ip │ │ │ └── 2018.1 │ │ │ │ └── e16efbb83c6bac58 │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ └── e16efbb83c6bac58.xci │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ └── webtalk_pa.xml │ ├── systolic_14x14_ip.hw │ │ └── systolic_14x14_ip.lpr │ ├── systolic_14x14_ip.ip_user_files │ │ ├── README.txt │ │ └── sim_scripts │ │ │ └── import_me │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ ├── systolic_14x14_ip.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── dont_touch.xdc │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── systolic_14x14_ip.srcs │ │ ├── constrs_1 │ │ │ └── new │ │ │ │ └── xdc.xdc │ │ └── sources_1 │ │ │ ├── bd │ │ │ └── import_me │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro.bxml │ │ │ │ ├── dsp_macro_ooc.xdc │ │ │ │ ├── hdl │ │ │ │ └── dsp_macro_wrapper.v │ │ │ │ ├── hw_handoff │ │ │ │ ├── dsp_macro.hwh │ │ │ │ └── dsp_macro_bd.tcl │ │ │ │ ├── ip │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ │ ├── sim │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ │ └── synth │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ ├── ipshared │ │ │ │ ├── 9743 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ │ ├── 442e │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ ├── a5f8 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ └── da55 │ │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── sim │ │ │ │ └── dsp_macro.v │ │ │ │ └── synth │ │ │ │ ├── dsp_macro.hwdef │ │ │ │ └── dsp_macro.v │ │ │ └── imports │ │ │ └── import_me │ │ │ ├── add.sv │ │ │ ├── array.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── dsp_macro_wrapper.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ ├── mem.sv │ │ │ ├── mul.sv │ │ │ └── top.sv │ └── systolic_14x14_ip.xpr └── tcl.tcl ├── systolic_32x32_ip ├── rundir │ ├── post_place_clock_util.rpt │ ├── post_place_timing_summary.rpt │ ├── post_place_util.rpt │ ├── post_route_drc.rpt │ ├── post_route_power.rpt │ ├── post_route_status.rpt │ ├── post_route_timing_summary.rpt │ ├── post_route_util.rpt │ ├── post_synth_timing_summary.rpt │ └── post_synth_util.rpt ├── systolic_32x32_ip │ ├── systolic_32x32_ip.cache │ │ ├── ip │ │ │ └── 2018.1 │ │ │ │ └── e16efbb83c6bac58 │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ └── e16efbb83c6bac58.xci │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ └── webtalk_pa.xml │ ├── systolic_32x32_ip.hw │ │ └── systolic_32x32_ip.lpr │ ├── systolic_32x32_ip.ip_user_files │ │ ├── README.txt │ │ └── sim_scripts │ │ │ └── import_me │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── dsp_macro.sh │ │ │ ├── dsp_macro.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── dsp_macro.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ ├── systolic_32x32_ip.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── dont_touch.xdc │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── systolic_32x32_ip.srcs │ │ ├── constrs_1 │ │ │ └── new │ │ │ │ └── xdc.xdc │ │ └── sources_1 │ │ │ ├── bd │ │ │ └── import_me │ │ │ │ ├── dsp_macro.bd │ │ │ │ ├── dsp_macro.bxml │ │ │ │ ├── dsp_macro_ooc.xdc │ │ │ │ ├── hdl │ │ │ │ └── dsp_macro_wrapper.v │ │ │ │ ├── hw_handoff │ │ │ │ ├── dsp_macro.hwh │ │ │ │ └── dsp_macro_bd.tcl │ │ │ │ ├── ip │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ │ ├── sim │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ │ └── synth │ │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ ├── ipshared │ │ │ │ ├── 9743 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ │ ├── 442e │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ ├── a5f8 │ │ │ │ │ └── hdl │ │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ └── da55 │ │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── sim │ │ │ │ └── dsp_macro.v │ │ │ │ └── synth │ │ │ │ ├── dsp_macro.hwdef │ │ │ │ └── dsp_macro.v │ │ │ └── imports │ │ │ └── import_me │ │ │ ├── add.sv │ │ │ ├── array.sv │ │ │ ├── dff.sv │ │ │ ├── dff_enbl.sv │ │ │ ├── dsp_macro_wrapper.sv │ │ │ ├── fsm.sv │ │ │ ├── int8_pe.sv │ │ │ ├── int8_quad_mac.sv │ │ │ ├── mem.sv │ │ │ ├── mul.sv │ │ │ └── top.sv │ └── systolic_32x32_ip.xpr └── tcl.tcl └── systolic_8x8_ip ├── rundir ├── post_place_clock_util.rpt ├── post_place_timing_summary.rpt ├── post_place_util.rpt ├── post_route_drc.rpt ├── post_route_power.rpt ├── post_route_status.rpt ├── post_route_timing_summary.rpt ├── post_route_util.rpt ├── post_synth_timing_summary.rpt └── post_synth_util.rpt ├── systolic_8x8_ip ├── systolic_8x8_ip.cache │ ├── ip │ │ └── 2018.1 │ │ │ └── e16efbb83c6bac58 │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ └── e16efbb83c6bac58.xci │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ └── webtalk_pa.xml ├── systolic_8x8_ip.hw │ └── systolic_8x8_ip.lpr ├── systolic_8x8_ip.ip_user_files │ ├── README.txt │ └── sim_scripts │ │ └── import_me │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── dsp_macro.sh │ │ ├── dsp_macro.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ ├── xcelium │ │ ├── README.txt │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── dsp_macro.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vhdl.prj │ │ └── vlog.prj ├── systolic_8x8_ip.runs │ ├── .jobs │ │ └── vrs_config_1.xml │ └── dsp_macro_xbip_dsp48_macro_0_0_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── dont_touch.xdc │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.tcl │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.vds │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── systolic_8x8_ip.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── xdc.xdc │ └── sources_1 │ │ ├── bd │ │ └── import_me │ │ │ ├── dsp_macro.bd │ │ │ ├── dsp_macro.bxml │ │ │ ├── dsp_macro_ooc.xdc │ │ │ ├── hdl │ │ │ └── dsp_macro_wrapper.v │ │ │ ├── hw_handoff │ │ │ ├── dsp_macro.hwh │ │ │ └── dsp_macro_bd.tcl │ │ │ ├── ip │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0 │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.dcp │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xci │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0.xml │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_sim_netlist.vhdl │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.v │ │ │ │ ├── dsp_macro_xbip_dsp48_macro_0_0_stub.vhdl │ │ │ │ ├── sim │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ │ └── synth │ │ │ │ └── dsp_macro_xbip_dsp48_macro_0_0.vhd │ │ │ ├── ipshared │ │ │ ├── 9743 │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_macro_v3_0_vh_rfs.vhd │ │ │ ├── 442e │ │ │ │ └── hdl │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ ├── a5f8 │ │ │ │ └── hdl │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ └── da55 │ │ │ │ └── hdl │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ ├── sim │ │ │ └── dsp_macro.v │ │ │ └── synth │ │ │ ├── dsp_macro.hwdef │ │ │ └── dsp_macro.v │ │ └── imports │ │ └── import_me │ │ ├── add.sv │ │ ├── array.sv │ │ ├── dff.sv │ │ ├── dff_enbl.sv │ │ ├── dsp_macro_wrapper.sv │ │ ├── fsm.sv │ │ ├── int8_pe.sv │ │ ├── int8_quad_mac.sv │ │ ├── mem.sv │ │ ├── mul.sv │ │ └── top.sv └── systolic_8x8_ip.xpr └── tcl.tcl /.gitattributes: -------------------------------------------------------------------------------- 1 | example/* linguist-vendored 2 | validation/* linguist-vendored 3 | *.zip filter=lfs diff=lfs merge=lfs -text 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 Fabiano Libano 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /docs/architecture.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/docs/architecture.png -------------------------------------------------------------------------------- /docs/demo.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/docs/demo.gif -------------------------------------------------------------------------------- /docs/testbench.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/docs/testbench.png -------------------------------------------------------------------------------- /example/info.txt: -------------------------------------------------------------------------------- 1 | ##### ./example/ ##### 2 | 3 | The 'systolic_2x2_ip' directory is the root of an example Vivado project for a 2x2 systolic array. 4 | The source files were generated by the scripts in 'generator'. 5 | The project also includes naive testbenches for 'array.sv' and 'top.sv', along with their respective '*.wfcg' files. 6 | 7 | The 'systolic_2x2_system.zip' file contains a directory that is the root of an example Vivado project. 8 | It includes 'systolic_2x2_ip' in it's IP catalog, and instantiates it in a block design along with a Zynq PS, an AXI DMA, and some other auxiliary blocks. An application is written inside SDK to demonstrate an use-case of 'systolic_2x2_ip', where input data is sent by the PS to the PL (via DMA), and output data is sent by the PL to the PS (via DMA). 9 | 10 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657268616e646c6572:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657277697a61726468616e646c6572:31:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 7 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 8 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:31:00:00 9 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:31:00:00 10 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:31:00:00 11 | eof:1366607394 12 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.hw/systolic_2x2_ip.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl -o dsp_macro_opt 2 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib dsp_macro_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dsp_macro_xbip_dsp48_macro_0_0.vhd,vhdl,xil_defaultlib,../../../../systolic_2x2_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd, 2 | dsp_macro.v,verilog,xil_defaultlib,../../../../systolic_2x2_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/xsim/vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl xil_defaultlib \ 2 | "../../../../systolic_2x2_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 3 | 4 | nosort 5 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.ip_user_files/sim_scripts/import_me/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../systolic_2x2_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # **************************************************************************** 3 | # Vivado (TM) v2018.1 (64-bit) 4 | # 5 | # Filename : compile.sh 6 | # Simulator : Xilinx Vivado Simulator 7 | # Description : Script for compiling the simulation design source files 8 | # 9 | # Generated by Vivado on Mon Sep 07 20:46:25 -03 2020 10 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 11 | # 12 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | # 14 | # usage: compile.sh 15 | # 16 | # **************************************************************************** 17 | ExecStep() 18 | { 19 | "$@" 20 | RETVAL=$? 21 | if [ $RETVAL -ne 0 ] 22 | then 23 | exit $RETVAL 24 | fi 25 | } 26 | echo "xvlog --incr --relax -L xil_defaultlib -prj tb_array_vlog.prj" 27 | ExecStep xvlog --incr --relax -L xil_defaultlib -prj tb_array_vlog.prj 2>&1 | tee compile.log 28 | echo "xvhdl --incr --relax -prj tb_array_vhdl.prj" 29 | ExecStep xvhdl --incr --relax -prj tb_array_vhdl.prj 2>&1 | tee -a compile.log 30 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/elaborate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # **************************************************************************** 3 | # Vivado (TM) v2018.1 (64-bit) 4 | # 5 | # Filename : elaborate.sh 6 | # Simulator : Xilinx Vivado Simulator 7 | # Description : Script for elaborating the compiled design 8 | # 9 | # Generated by Vivado on Mon Sep 07 20:46:30 -03 2020 10 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 11 | # 12 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | # 14 | # usage: elaborate.sh 15 | # 16 | # **************************************************************************** 17 | ExecStep() 18 | { 19 | "$@" 20 | RETVAL=$? 21 | if [ $RETVAL -ne 0 ] 22 | then 23 | exit $RETVAL 24 | fi 25 | } 26 | ExecStep xelab -wto 15bae719a2a04a96a751e15b4a9017b9 --incr --debug typical --relax --mt 8 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_array_behav xil_defaultlib.tb_array xil_defaultlib.glbl -log elaborate.log 27 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/simulate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # **************************************************************************** 3 | # Vivado (TM) v2018.1 (64-bit) 4 | # 5 | # Filename : simulate.sh 6 | # Simulator : Xilinx Vivado Simulator 7 | # Description : Script for simulating the design by launching the simulator 8 | # 9 | # Generated by Vivado on Mon Sep 07 20:46:57 -03 2020 10 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 11 | # 12 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | # 14 | # usage: simulate.sh 15 | # 16 | # **************************************************************************** 17 | ExecStep() 18 | { 19 | "$@" 20 | RETVAL=$? 21 | if [ $RETVAL -ne 0 ] 22 | then 23 | exit $RETVAL 24 | fi 25 | } 26 | ExecStep xsim tb_array_behav -key {Behavioral:sim_1:Functional:tb_array} -tclbatch tb_array.tcl -view /home/libano/vivado/systolic_2x2_ip/tb_array_behav.wcfg -log simulate.log 27 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/tb_array.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/tb_array_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/tb_array_behav.wdb -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/tb_array_vhdl.prj: -------------------------------------------------------------------------------- 1 | # compile vhdl design source files 2 | vhdl xil_defaultlib \ 3 | "../../../../systolic_2x2_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 4 | 5 | # Do not sort compile order 6 | nosort 7 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/tb_array_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib --include "/opt/Xilinx/Vivado/2018.1/data/xilinx_vip/include" \ 3 | "../../../../systolic_2x2_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 4 | 5 | sv xil_defaultlib --include "/opt/Xilinx/Vivado/2018.1/data/xilinx_vip/include" \ 6 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/add.sv" \ 7 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/array.sv" \ 8 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/dff.sv" \ 9 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/dff_enbl.sv" \ 10 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv" \ 11 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/int8_pe.sv" \ 12 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/int8_quad_mac.sv" \ 13 | "../../../../systolic_2x2_ip.srcs/sources_1/imports/import_me/mul.sv" \ 14 | "../../../../systolic_2x2_ip.srcs/sim_1/new/tb_array.sv" \ 15 | 16 | # compile glbl module 17 | verilog xil_defaultlib "glbl.v" 18 | 19 | # Do not sort compile order 20 | nosort 21 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 20:48:05 2020 6 | # Process ID: 2339 7 | # Current directory: /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/webtalk_2249.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 20:46:54 2020 6 | # Process ID: 2249 7 | # Current directory: /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/libano/vivado/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "15bae719a2a04a96a751e15b4a9017b9" --incr --debug "typical" --relax --mt "8" -L "xbip_dsp48_wrapper_v3_0_4" -L "xbip_utils_v3_0_9" -L "xbip_pipe_v3_0_5" -L "xbip_dsp48_macro_v3_0_16" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "tb_array_behav" "xil_defaultlib.tb_array" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/obj/xsim_0.lnx64.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/obj/xsim_0.lnx64.o -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/obj/xsim_1.lnx64.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/obj/xsim_1.lnx64.o -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/webtalk/.xsim_webtallk.info: -------------------------------------------------------------------------------- 1 | 1599522412 2 | 1599522483 3 | 3 4 | 1 5 | 15bae719a2a04a96a751e15b4a9017b9 6 | -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsim.reloc -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 4696659426500420847 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto 15bae719a2a04a96a751e15b4a9017b9 --incr --debug typical --relax --mt 8 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_array_behav xil_defaultlib.tb_array xil_defaultlib.glbl" , 6 | buildDate : "Apr 4 2018" , 7 | buildTime : "18:43:17" , 8 | linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_array_behav/xsimk\" \"xsim.dir/tb_array_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_array_behav/obj/xsim_1.lnx64.o\" \"/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/librdi_simulator_kernel.so\" \"/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/librdi_simbridge_kernel.so\"" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsim.rtti -------------------------------------------------------------------------------- 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/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsim.xdbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsim.xdbg -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.sim/sim_1/behav/xsim/xsim.dir/tb_array_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | SCOPE_NAME_COLUMN_WIDTH=231 23 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 24 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 25 | OBJECT_NAME_COLUMN_WIDTH=177 26 | OBJECT_VALUE_COLUMN_WIDTH=115 27 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 28 | PROCESS_NAME_COLUMN_WIDTH=75 29 | PROCESS_TYPE_COLUMN_WIDTH=75 30 | FRAME_INDEX_COLUMN_WIDTH=75 31 | FRAME_NAME_COLUMN_WIDTH=75 32 | FRAME_FILE_NAME_COLUMN_WIDTH=75 33 | FRAME_LINE_NUM_COLUMN_WIDTH=177 34 | LOCAL_NAME_COLUMN_WIDTH=115 35 | LOCAL_VALUE_COLUMN_WIDTH=75 36 | INPUT_LOCAL_FILTER=1 37 | OUTPUT_LOCAL_FILTER=1 38 | INOUT_LOCAL_FILTER=1 39 | INTERNAL_LOCAL_FILTER=1 40 | CONSTANT_LOCAL_FILTER=1 41 | VARIABLE_LOCAL_FILTER=1 42 | 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| create_clock -name CLK -period 10 [get_ports CLK] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/bd/import_me/hdl/dsp_macro_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | //Date : Mon Sep 7 20:46:20 2020 5 | //Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | //Command : generate_target dsp_macro_wrapper.bd 7 | //Design : dsp_macro_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module dsp_macro_wrapper 13 | (A, 14 | B, 15 | C, 16 | CLK, 17 | CLR, 18 | Z); 19 | input [24:0]A; 20 | input [24:0]B; 21 | input [17:0]C; 22 | input CLK; 23 | input CLR; 24 | output [42:0]Z; 25 | 26 | wire [24:0]A; 27 | wire [24:0]B; 28 | wire [17:0]C; 29 | wire CLK; 30 | wire CLR; 31 | wire [42:0]Z; 32 | 33 | dsp_macro dsp_macro_i 34 | (.A(A), 35 | .B(B), 36 | .C(C), 37 | .CLK(CLK), 38 | .CLR(CLR), 39 | .Z(Z)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/imports/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/imports/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/imports/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/imports/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /example/systolic_2x2_ip/systolic_2x2_ip.srcs/sources_1/imports/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /example/systolic_2x2_system.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:07462098c577667d55b812c90647a8f1fb79f42bc640dc8463310e68eda26265 3 | size 91779872 4 | -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/7series/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /generator/RTL/dont_touch/generic/ultrascale/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /generator/RTL/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /generator/RTL/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /generator/RTL/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /generator/RTL/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /generator/RTL/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /generator/RTL/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /generator/fileHandler.py: -------------------------------------------------------------------------------- 1 | from settings import * 2 | 3 | def deleteOldFiles(): 4 | print("\tDeleting Old Files...") 5 | 6 | #clean 'generated' directory 7 | for fileName in glob.glob(os.path.join(generatedPath, "*.*")): 8 | os.remove(fileName) 9 | #clean 'import_me' directory 10 | for fileName in glob.glob(os.path.join(importMePath, "*.*")): 11 | os.remove(fileName) 12 | 13 | def copyNewFiles(): 14 | print("\tCopying New Files...") 15 | 16 | #copy from 'generic' to 'import_me' 17 | for fileName in glob.glob(os.path.join(genericPath, "*.*")): 18 | shutil.copy(fileName, importMePath) 19 | if(is7Series): 20 | dspPath = genericPath + "7series" 21 | else: 22 | dspPath = genericPath + "ultrascale" 23 | for fileName in glob.glob(os.path.join(dspPath, "*.*")): 24 | shutil.copy(fileName, importMePath) 25 | 26 | #copy from 'generated' to 'import_me' 27 | for fileName in glob.glob(os.path.join(generatedPath, "*.*")): 28 | shutil.copy(fileName, importMePath) 29 | -------------------------------------------------------------------------------- /generator/main.py: -------------------------------------------------------------------------------- 1 | from settings import * 2 | from fileHandler import * 3 | from arrayGenerator import * 4 | from topGenerator import * 5 | 6 | print("############# Libano's Systolic Array Generator #############\n") 7 | 8 | #delete old files 9 | deleteOldFiles() 10 | #generate new .sv files 11 | generateArray() 12 | if(axiWrapper): 13 | generateTop() 14 | #copy new .sv files to './RTL/import_me' 15 | copyNewFiles() 16 | 17 | print("\n#############################################################") -------------------------------------------------------------------------------- /generator/settings.py: -------------------------------------------------------------------------------- 1 | #imports 2 | import os 3 | import sys 4 | import glob 5 | import shutil 6 | import math as m 7 | 8 | #globals 9 | genericPath = "./RTL/dont_touch/generic/" #DONT TOUCH 10 | generatedPath = "./RTL/dont_touch/generated/" #DONT TOUCH 11 | importMePath = "./RTL/import_me/" #DONT TOUCH 12 | parallelismLevel = 2*2 #DONT TOUCH 13 | inputBits = 8 #DONT TOUCH 14 | outputBits = 32 #(Accumulators) 15 | arraySize = 2 #(N in NxN) 16 | is7Series = False #{True = 7 Series (DSP48E1), False = UltraScale (DSP48E2)} 17 | axiWrapper = True #(AXI Wrapper 'top.sv') 18 | -------------------------------------------------------------------------------- /validation/zynq_7000/info.txt: -------------------------------------------------------------------------------- 1 | ##### ./validation/zynq_7000/ ##### 2 | 3 | The 'ooc' directory contains 'systolic_8x8_ip' and 'systolic_14x14_ip'. 4 | These subdirectories contain source/constraint files for an 8x8/14x14 systolic array, and a 'tcl.tcl' script that allows for OOC sythesis, placement and routing in Vivado's non-project mode. It showcases how fast the systolic array can run standalone (200MHz). 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/rundir/post_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 147678 : 5 | # of nets not needing routing.......... : 75784 : 6 | # of internally routed nets........ : 73423 : 7 | # of implicitly routed ports....... : 2361 : 8 | # of routable nets..................... : 71894 : 9 | # of fully routed nets............. : 71894 : 10 | # of nets with routing errors.......... : 0 : 11 | ------------------------------------------- : ----------- : 12 | 13 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/ip/2018.1/80dcd78ae577ecfb/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/ip/2018.1/80dcd78ae577ecfb/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/ip/2018.1/80dcd78ae577ecfb/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 19:03:08 2020 5 | // Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7z020clg400-3 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 5 | eof:3742494661 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.hw/systolic_14x14_ip.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl -o dsp_macro_opt 2 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib dsp_macro_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dsp_macro_xbip_dsp48_macro_0_0.vhd,vhdl,xil_defaultlib,../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd, 2 | dsp_macro.v,verilog,xil_defaultlib,../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl xil_defaultlib \ 2 | "../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 3 | 4 | nosort 5 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.xci 5 | # IP: The module: 'dsp_macro_xbip_dsp48_macro_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'dsp_macro_xbip_dsp48_macro_0_0'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.xci 12 | # IP: The module: 'dsp_macro_xbip_dsp48_macro_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'dsp_macro_xbip_dsp48_macro_0_0'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 10 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | set PATH=%SYSTEMROOT%\system32;%PATH% 11 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 12 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | if [ -z "$PATH" ]; then 10 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin 11 | else 12 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin:$PATH 13 | fi 14 | export PATH 15 | 16 | if [ -z "$LD_LIBRARY_PATH" ]; then 17 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64 18 | else 19 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH 20 | fi 21 | export LD_LIBRARY_PATH 22 | 23 | HD_PWD='/home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1' 24 | cd "$HD_PWD" 25 | 26 | HD_LOG=runme.log 27 | /bin/touch $HD_LOG 28 | 29 | ISEStep="./ISEWrap.sh" 30 | EAStep() 31 | { 32 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 33 | if [ $? -ne 0 ] 34 | then 35 | exit 36 | fi 37 | } 38 | 39 | EAStep vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 40 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 18:59:56 2020 6 | # Process ID: 29057 7 | # Current directory: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1 8 | # Command line: vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 9 | # Log file: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.vds 10 | # Journal file: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source dsp_macro_xbip_dsp48_macro_0_0.tcl -notrace 13 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/constrs_1/new/xdc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 5 [get_ports clk] 2 | set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports clk] 3 | create_clock -name clk2x -period 2.5 [get_ports clk2x] 4 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports clk2x] -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/dsp_macro_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name CLK -period 10 [get_ports CLK] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/hdl/dsp_macro_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | //Date : Mon Sep 7 18:59:51 2020 5 | //Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | //Command : generate_target dsp_macro_wrapper.bd 7 | //Design : dsp_macro_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module dsp_macro_wrapper 13 | (A, 14 | B, 15 | C, 16 | CLK, 17 | CLR, 18 | Z); 19 | input [24:0]A; 20 | input [24:0]B; 21 | input [17:0]C; 22 | input CLK; 23 | input CLR; 24 | output [42:0]Z; 25 | 26 | wire [24:0]A; 27 | wire [24:0]B; 28 | wire [17:0]C; 29 | wire CLK; 30 | wire CLR; 31 | wire [42:0]Z; 32 | 33 | dsp_macro dsp_macro_i 34 | (.A(A), 35 | .B(B), 36 | .C(C), 37 | .CLK(CLK), 38 | .CLR(CLR), 39 | .Z(Z)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 19:03:10 2020 5 | // Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7z020clg400-3 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module dsp_macro_xbip_dsp48_macro_0_0(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/rundir/post_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 43883 : 5 | # of nets not needing routing.......... : 22126 : 6 | # of internally routed nets........ : 20774 : 7 | # of implicitly routed ports....... : 1352 : 8 | # of routable nets..................... : 21757 : 9 | # of fully routed nets............. : 21757 : 10 | # of nets with routing errors.......... : 0 : 11 | ------------------------------------------- : ----------- : 12 | 13 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/ip/2018.1/80dcd78ae577ecfb/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/ip/2018.1/80dcd78ae577ecfb/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/ip/2018.1/80dcd78ae577ecfb/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 18:57:43 2020 5 | // Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7z020clg400-3 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 5 | eof:3742494661 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.hw/systolic_8x8_ip.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl -o dsp_macro_opt 2 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib dsp_macro_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dsp_macro_xbip_dsp48_macro_0_0.vhd,vhdl,xil_defaultlib,../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd, 2 | dsp_macro.v,verilog,xil_defaultlib,../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl xil_defaultlib \ 2 | "../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 3 | 4 | nosort 5 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.xci 5 | # IP: The module: 'dsp_macro_xbip_dsp48_macro_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'dsp_macro_xbip_dsp48_macro_0_0'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.xci 12 | # IP: The module: 'dsp_macro_xbip_dsp48_macro_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'dsp_macro_xbip_dsp48_macro_0_0'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 10 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | set PATH=%SYSTEMROOT%\system32;%PATH% 11 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 12 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | if [ -z "$PATH" ]; then 10 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin 11 | else 12 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin:$PATH 13 | fi 14 | export PATH 15 | 16 | if [ -z "$LD_LIBRARY_PATH" ]; then 17 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64 18 | else 19 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH 20 | fi 21 | export LD_LIBRARY_PATH 22 | 23 | HD_PWD='/home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1' 24 | cd "$HD_PWD" 25 | 26 | HD_LOG=runme.log 27 | /bin/touch $HD_LOG 28 | 29 | ISEStep="./ISEWrap.sh" 30 | EAStep() 31 | { 32 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 33 | if [ $? -ne 0 ] 34 | then 35 | exit 36 | fi 37 | } 38 | 39 | EAStep vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 40 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 18:54:29 2020 6 | # Process ID: 28673 7 | # Current directory: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1 8 | # Command line: vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 9 | # Log file: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.vds 10 | # Journal file: /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source dsp_macro_xbip_dsp48_macro_0_0.tcl -notrace 13 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/constrs_1/new/xdc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 5 [get_ports clk] 2 | set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports clk] 3 | create_clock -name clk2x -period 2.5 [get_ports clk2x] 4 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports clk2x] -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/dsp_macro_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name CLK -period 10 [get_ports CLK] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/hdl/dsp_macro_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | //Date : Mon Sep 7 18:54:24 2020 5 | //Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | //Command : generate_target dsp_macro_wrapper.bd 7 | //Design : dsp_macro_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module dsp_macro_wrapper 13 | (A, 14 | B, 15 | C, 16 | CLK, 17 | CLR, 18 | Z); 19 | input [24:0]A; 20 | input [24:0]B; 21 | input [17:0]C; 22 | input CLK; 23 | input CLR; 24 | output [42:0]Z; 25 | 26 | wire [24:0]A; 27 | wire [24:0]B; 28 | wire [17:0]C; 29 | wire CLK; 30 | wire CLR; 31 | wire [42:0]Z; 32 | 33 | dsp_macro dsp_macro_i 34 | (.A(A), 35 | .B(B), 36 | .C(C), 37 | .CLK(CLK), 38 | .CLR(CLR), 39 | .Z(Z)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 18:57:45 2020 5 | // Host : linux running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/libano/vivado/NON_PROJECT/zynq_7000/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7z020clg400-3 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module dsp_macro_xbip_dsp48_macro_0_0(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /validation/zynq_7000/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /validation/zynq_us+/info.txt: -------------------------------------------------------------------------------- 1 | ##### ./validation/zynq_us+/ ##### 2 | 3 | The 'ooc' directory contains 'systolic_8x8_ip', 'systolic_14x14_ip', and 'systolic_32x32_ip'. 4 | These subdirectories contain source/constraint files for an 8x8/14x14/32x32 systolic array, and a 'tcl.tcl' script that allows for OOC sythesis, placement and routing in Vivado's non-project mode. It showcases how fast the systolic array can run standalone (300MHz). 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/rundir/post_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 351513 : 5 | # of nets not needing routing.......... : 282170 : 6 | # of internally routed nets........ : 254330 : 7 | # of nets with no loads............ : 25480 : 8 | # of implicitly routed ports....... : 2360 : 9 | # of routable nets..................... : 69343 : 10 | # of nets with explicit gaps....... : 2 : 11 | # of fully routed nets............. : 69343 : 12 | # of nets with routing errors.......... : 0 : 13 | ------------------------------------------- : ----------- : 14 | 15 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 15:47:01 2020 5 | // Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xczu9eg-ffvb1156-3-e-es2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:33:00:00 5 | eof:1869811388 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:2 3 | eof: 4 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.hw/systolic_14x14_ip.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl -o dsp_macro_opt 2 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib dsp_macro_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dsp_macro_xbip_dsp48_macro_0_0.vhd,vhdl,xil_defaultlib,../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd, 2 | dsp_macro.v,verilog,xil_defaultlib,../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl xil_defaultlib \ 2 | "../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 3 | 4 | nosort 5 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.ip_user_files/sim_scripts/import_me/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../systolic_14x14_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 10 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | set PATH=%SYSTEMROOT%\system32;%PATH% 11 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 12 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | if [ -z "$PATH" ]; then 10 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin 11 | else 12 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin:$PATH 13 | fi 14 | export PATH 15 | 16 | if [ -z "$LD_LIBRARY_PATH" ]; then 17 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64 18 | else 19 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH 20 | fi 21 | export LD_LIBRARY_PATH 22 | 23 | HD_PWD='/home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1' 24 | cd "$HD_PWD" 25 | 26 | HD_LOG=runme.log 27 | /bin/touch $HD_LOG 28 | 29 | ISEStep="./ISEWrap.sh" 30 | EAStep() 31 | { 32 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 33 | if [ $? -ne 0 ] 34 | then 35 | exit 36 | fi 37 | } 38 | 39 | EAStep vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 40 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 15:45:14 2020 6 | # Process ID: 7369 7 | # Current directory: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1 8 | # Command line: vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 9 | # Log file: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.vds 10 | # Journal file: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source dsp_macro_xbip_dsp48_macro_0_0.tcl -notrace 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/constrs_1/new/xdc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 3.333 [get_ports clk] 2 | set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports clk] 3 | create_clock -name clk2x -period 1.666 [get_ports clk2x] 4 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports clk2x] -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/dsp_macro_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name CLK -period 10 [get_ports CLK] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/hdl/dsp_macro_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | //Date : Mon Sep 7 15:45:10 2020 5 | //Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | //Command : generate_target dsp_macro_wrapper.bd 7 | //Design : dsp_macro_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module dsp_macro_wrapper 13 | (A, 14 | B, 15 | C, 16 | CLK, 17 | CLR, 18 | Z); 19 | input [24:0]A; 20 | input [24:0]B; 21 | input [17:0]C; 22 | input CLK; 23 | input CLR; 24 | output [42:0]Z; 25 | 26 | wire [24:0]A; 27 | wire [24:0]B; 28 | wire [17:0]C; 29 | wire CLK; 30 | wire CLR; 31 | wire [42:0]Z; 32 | 33 | dsp_macro dsp_macro_i 34 | (.A(A), 35 | .B(B), 36 | .C(C), 37 | .CLK(CLK), 38 | .CLR(CLR), 39 | .Z(Z)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 15:47:02 2020 5 | // Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xczu9eg-ffvb1156-3-e-es2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module dsp_macro_xbip_dsp48_macro_0_0(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_14x14_ip/systolic_14x14_ip/systolic_14x14_ip.srcs/sources_1/imports/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/rundir/post_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 1868196 : 5 | # of nets not needing routing.......... : 1495259 : 6 | # of internally routed nets........ : 1356755 : 7 | # of nets with no loads............ : 133120 : 8 | # of implicitly routed ports....... : 5384 : 9 | # of routable nets..................... : 372937 : 10 | # of nets with explicit gaps....... : 2 : 11 | # of fully routed nets............. : 372937 : 12 | # of nets with routing errors.......... : 0 : 13 | ------------------------------------------- : ----------- : 14 | 15 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 15:59:28 2020 5 | // Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xczu9eg-ffvb1156-3-e-es2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.cache/wt/gui_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:31:00:00 7 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:35:00:00 8 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:32:00:00 9 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:31:00:00 10 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:31:00:00 11 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 12 | eof:2249691896 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00 4 | eof:2073860705 5 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:2 3 | eof: 4 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.hw/systolic_32x32_ip.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl -o dsp_macro_opt 2 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib dsp_macro_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dsp_macro_xbip_dsp48_macro_0_0.vhd,vhdl,xil_defaultlib,../../../../systolic_32x32_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd, 2 | dsp_macro.v,verilog,xil_defaultlib,../../../../systolic_32x32_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/xsim/vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl xil_defaultlib \ 2 | "../../../../systolic_32x32_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 3 | 4 | nosort 5 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.ip_user_files/sim_scripts/import_me/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../systolic_32x32_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- 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/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 10 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | set PATH=%SYSTEMROOT%\system32;%PATH% 11 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 12 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | if [ -z "$PATH" ]; then 10 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin 11 | else 12 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin:$PATH 13 | fi 14 | export PATH 15 | 16 | if [ -z "$LD_LIBRARY_PATH" ]; then 17 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64 18 | else 19 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH 20 | fi 21 | export LD_LIBRARY_PATH 22 | 23 | HD_PWD='/home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1' 24 | cd "$HD_PWD" 25 | 26 | HD_LOG=runme.log 27 | /bin/touch $HD_LOG 28 | 29 | ISEStep="./ISEWrap.sh" 30 | EAStep() 31 | { 32 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 33 | if [ $? -ne 0 ] 34 | then 35 | exit 36 | fi 37 | } 38 | 39 | EAStep vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 40 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 15:57:41 2020 6 | # Process ID: 7668 7 | # Current directory: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1 8 | # Command line: vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 9 | # Log file: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.vds 10 | # Journal file: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source dsp_macro_xbip_dsp48_macro_0_0.tcl -notrace 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/constrs_1/new/xdc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 3.333 [get_ports clk] 2 | set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports clk] 3 | create_clock -name clk2x -period 1.666 [get_ports clk2x] 4 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports clk2x] -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/dsp_macro_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name CLK -period 10 [get_ports CLK] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/hdl/dsp_macro_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | //Date : Mon Sep 7 15:57:38 2020 5 | //Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | //Command : generate_target dsp_macro_wrapper.bd 7 | //Design : dsp_macro_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module dsp_macro_wrapper 13 | (A, 14 | B, 15 | C, 16 | CLK, 17 | CLR, 18 | Z); 19 | input [24:0]A; 20 | input [24:0]B; 21 | input [17:0]C; 22 | input CLK; 23 | input CLR; 24 | output [42:0]Z; 25 | 26 | wire [24:0]A; 27 | wire [24:0]B; 28 | wire [17:0]C; 29 | wire CLK; 30 | wire CLR; 31 | wire [42:0]Z; 32 | 33 | dsp_macro dsp_macro_i 34 | (.A(A), 35 | .B(B), 36 | .C(C), 37 | .CLK(CLK), 38 | .CLR(CLR), 39 | .Z(Z)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 15:59:29 2020 5 | // Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xczu9eg-ffvb1156-3-e-es2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module dsp_macro_xbip_dsp48_macro_0_0(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/imports/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/imports/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/imports/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/imports/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_32x32_ip/systolic_32x32_ip/systolic_32x32_ip.srcs/sources_1/imports/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/rundir/post_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 110651 : 5 | # of nets not needing routing.......... : 89517 : 6 | # of internally routed nets........ : 79845 : 7 | # of nets with no loads............ : 8320 : 8 | # of implicitly routed ports....... : 1352 : 9 | # of routable nets..................... : 21134 : 10 | # of nets with explicit gaps....... : 2 : 11 | # of fully routed nets............. : 21134 : 12 | # of nets with routing errors.......... : 0 : 13 | ------------------------------------------- : ----------- : 14 | 15 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/ip/2018.1/e16efbb83c6bac58/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 15:27:27 2020 5 | // Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xczu9eg-ffvb1156-3-e-es2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 5 | eof:3742494661 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:2 3 | eof: 4 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.hw/systolic_8x8_ip.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dsp_macro xil_defaultlib.glbl -o dsp_macro_opt 2 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib dsp_macro_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {dsp_macro.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/dsp_macro.udo -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+dsp_macro -L xilinx_vip -L xbip_dsp48_wrapper_v3_0_4 -L xbip_utils_v3_0_9 -L xbip_pipe_v3_0_5 -L xbip_dsp48_macro_v3_0_16 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dsp_macro xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {dsp_macro.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dsp_macro_xbip_dsp48_macro_0_0.vhd,vhdl,xil_defaultlib,../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd, 2 | dsp_macro.v,verilog,xil_defaultlib,../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl xil_defaultlib \ 2 | "../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/sim/dsp_macro_xbip_dsp48_macro_0_0.vhd" \ 3 | 4 | nosort 5 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.ip_user_files/sim_scripts/import_me/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../systolic_8x8_ip.srcs/sources_1/bd/import_me/sim/dsp_macro.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.xci 5 | # IP: The module: 'dsp_macro_xbip_dsp48_macro_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'dsp_macro_xbip_dsp48_macro_0_0'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.xci 12 | # IP: The module: 'dsp_macro_xbip_dsp48_macro_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'dsp_macro_xbip_dsp48_macro_0_0'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0_utilization_synth.pb -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 10 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | set PATH=%SYSTEMROOT%\system32;%PATH% 11 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 12 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | if [ -z "$PATH" ]; then 10 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin 11 | else 12 | PATH=/opt/Xilinx/SDK/2018.1/bin:/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2018.1/bin:$PATH 13 | fi 14 | export PATH 15 | 16 | if [ -z "$LD_LIBRARY_PATH" ]; then 17 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64 18 | else 19 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2018.1/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH 20 | fi 21 | export LD_LIBRARY_PATH 22 | 23 | HD_PWD='/home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1' 24 | cd "$HD_PWD" 25 | 26 | HD_LOG=runme.log 27 | /bin/touch $HD_LOG 28 | 29 | ISEStep="./ISEWrap.sh" 30 | EAStep() 31 | { 32 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 33 | if [ $? -ne 0 ] 34 | then 35 | exit 36 | fi 37 | } 38 | 39 | EAStep vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 40 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Mon Sep 7 15:25:37 2020 6 | # Process ID: 7011 7 | # Current directory: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1 8 | # Command line: vivado -log dsp_macro_xbip_dsp48_macro_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dsp_macro_xbip_dsp48_macro_0_0.tcl 9 | # Log file: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/dsp_macro_xbip_dsp48_macro_0_0.vds 10 | # Journal file: /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source dsp_macro_xbip_dsp48_macro_0_0.tcl -notrace 13 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.runs/dsp_macro_xbip_dsp48_macro_0_0_synth_1/vivado.pb -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/constrs_1/new/xdc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 3.333 [get_ports clk] 2 | set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports clk] 3 | create_clock -name clk2x -period 1.666 [get_ports clk2x] 4 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports clk2x] -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/dsp_macro_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name CLK -period 10 [get_ports CLK] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/hdl/dsp_macro_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | //Date : Mon Sep 7 15:25:33 2020 5 | //Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | //Command : generate_target dsp_macro_wrapper.bd 7 | //Design : dsp_macro_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module dsp_macro_wrapper 13 | (A, 14 | B, 15 | C, 16 | CLK, 17 | CLR, 18 | Z); 19 | input [24:0]A; 20 | input [24:0]B; 21 | input [17:0]C; 22 | input CLK; 23 | input CLR; 24 | output [42:0]Z; 25 | 26 | wire [24:0]A; 27 | wire [24:0]B; 28 | wire [17:0]C; 29 | wire CLK; 30 | wire CLR; 31 | wire [42:0]Z; 32 | 33 | dsp_macro dsp_macro_i 34 | (.A(A), 35 | .B(B), 36 | .C(C), 37 | .CLK(CLK), 38 | .CLR(CLR), 39 | .Z(Z)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0.dcp -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 4 | // Date : Mon Sep 7 15:27:28 2020 5 | // Host : Shears running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/flibano/vivado/vivado/NON_PROJECT_MODE/zynq_us+/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/ip/dsp_macro_xbip_dsp48_macro_0_0/dsp_macro_xbip_dsp48_macro_0_0_stub.v 8 | // Design : dsp_macro_xbip_dsp48_macro_0_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xczu9eg-ffvb1156-3-e-es2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "xbip_dsp48_macro_v3_0_16,Vivado 2018.1" *) 17 | module dsp_macro_xbip_dsp48_macro_0_0(CLK, SCLR, A, B, D, P) 18 | /* synthesis syn_black_box black_box_pad_pin="CLK,SCLR,A[24:0],B[17:0],D[24:0],P[42:0]" */; 19 | input CLK; 20 | input SCLR; 21 | input [24:0]A; 22 | input [17:0]B; 23 | input [24:0]D; 24 | output [42:0]P; 25 | endmodule 26 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lllibano/SystolicArray/32ded2736b09e3f85dfce3f6c16c5c65a2c7fb1a/validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/bd/import_me/synth/dsp_macro.hwdef -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/add.sv: -------------------------------------------------------------------------------- 1 | module add 2 | #( 3 | parameter aBits = 16, 4 | parameter bBits = 32, 5 | parameter signExtension = bBits-aBits, 6 | parameter zBits = 33 7 | ) 8 | ( 9 | input logic [aBits-1:0] a, 10 | input logic [bBits-1:0] b, 11 | input logic carryIn, 12 | output logic [zBits-1:0] z 13 | ); 14 | 15 | logic [bBits-1:0] a_signExtended; 16 | assign a_signExtended = (a[aBits-1]) ? {{signExtension{1'b1}}, a}:{{signExtension{1'b0}}, a}; 17 | 18 | assign z = a_signExtended+b+carryIn; 19 | 20 | endmodule -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/dff.sv: -------------------------------------------------------------------------------- 1 | module dff 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic rst, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(rst) begin 14 | q <= {bits{1'b0}}; 15 | end 16 | else begin 17 | q <= d; 18 | end 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/dff_enbl.sv: -------------------------------------------------------------------------------- 1 | module dff_enbl 2 | #( 3 | parameter bits = 8 4 | ) 5 | ( 6 | input logic clk, 7 | input logic enbl, 8 | input logic [bits-1:0] d, 9 | output logic [bits-1:0] q 10 | ); 11 | 12 | always_ff @ (posedge clk) begin 13 | if(enbl) begin 14 | q <= d; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/dsp_macro_wrapper.sv: -------------------------------------------------------------------------------- 1 | module dsp_macro_wrapper 2 | ( 3 | input logic [24:0] A, 4 | input logic [24:0] B, 5 | input logic [17:0] C, 6 | input logic CLK, 7 | input logic CLR, 8 | output logic [42:0] Z 9 | ); 10 | 11 | dsp_macro dsp_macro(.A(A), .B(B), .C(C), .CLK(CLK), .CLR(CLR), .Z(Z)); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/int8_pe.sv: -------------------------------------------------------------------------------- 1 | module int8_pe 2 | #( 3 | parameter inputBits = 8, 4 | parameter outputBits = 32 5 | ) 6 | ( 7 | input logic clk, 8 | input logic rst, 9 | input logic clk2x, 10 | input logic [inputBits-1:0] a, 11 | input logic [inputBits-1:0] b, 12 | input logic [inputBits-1:0] c, 13 | input logic [inputBits-1:0] d, 14 | input logic [inputBits-1:0] e, 15 | input logic e_enable, 16 | input logic [outputBits-1:0] s, 17 | input logic [outputBits-1:0] t, 18 | input logic [outputBits-1:0] u, 19 | input logic [outputBits-1:0] v, 20 | output logic [inputBits-1:0] a_out, 21 | output logic [inputBits-1:0] b_out, 22 | output logic [inputBits-1:0] c_out, 23 | output logic [inputBits-1:0] d_out, 24 | output logic [inputBits-1:0] e_out, 25 | output logic [outputBits-1:0] w, 26 | output logic [outputBits-1:0] x, 27 | output logic [outputBits-1:0] y, 28 | output logic [outputBits-1:0] z 29 | ); 30 | 31 | logic [inputBits-1:0] e_in; 32 | 33 | dff #(inputBits) dff_a(clk, rst, a, a_out); 34 | dff #(inputBits) dff_b(clk, rst, b, b_out); 35 | dff #(inputBits) dff_c(clk, rst, c, c_out); 36 | dff #(inputBits) dff_d(clk, rst, d, d_out); 37 | assign e_in = (e_enable) ? e:e_out; 38 | dff #(inputBits) dff_e(clk, rst, e_in, e_out); 39 | int8_quad_mac #(inputBits, inputBits, inputBits, inputBits, inputBits, outputBits) int8_quad_mac(clk, rst, clk2x, a_out, b_out, c_out, d_out, e_out, s, t, u, v, w, x, y, z); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /validation/zynq_us+/ooc/systolic_8x8_ip/systolic_8x8_ip/systolic_8x8_ip.srcs/sources_1/imports/import_me/mem.sv: -------------------------------------------------------------------------------- 1 | module mem 2 | #( 3 | parameter bits = 8, 4 | parameter words = (2*2), 5 | parameter address = $clog2(words) //ceil(log2(words)) 6 | ) 7 | ( 8 | input logic clk, 9 | input logic w_enbl, 10 | input logic [address-1:0] w_addr, 11 | input logic [bits-1:0] w_data, 12 | input logic [address-1:0] r_addr, 13 | output logic [bits-1:0] r_data 14 | ); 15 | 16 | (* ram_style = "block" *) logic [bits-1:0] memory [words-1:0]; 17 | 18 | always @ (posedge clk) begin 19 | if(w_enbl) 20 | memory[w_addr] <= w_data; 21 | r_data <= memory[r_addr]; 22 | end 23 | 24 | endmodule 25 | --------------------------------------------------------------------------------