├── .gitignore ├── README.md ├── demo ├── app │ ├── board.h │ ├── main.c │ ├── stm32_it.c │ ├── stm32_it.h │ └── stm32f10x_conf.h ├── demo.uvgui.Administrator ├── demo.uvopt ├── demo.uvproj └── fwlib │ ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F10x │ │ │ ├── Include │ │ │ ├── stm32f10x.h │ │ │ └── system_stm32f10x.h │ │ │ ├── Release_Notes.html │ │ │ └── Source │ │ │ └── Templates │ │ │ ├── TASKING │ │ │ └── cstart_thumb2.asm │ │ │ ├── TrueSTUDIO │ │ │ ├── startup_stm32f10x_cl.s │ │ │ ├── startup_stm32f10x_hd.s │ │ │ ├── startup_stm32f10x_hd_vl.s │ │ │ ├── startup_stm32f10x_ld.s │ │ │ ├── startup_stm32f10x_ld_vl.s │ │ │ ├── startup_stm32f10x_md.s │ │ │ ├── startup_stm32f10x_md_vl.s │ │ │ └── startup_stm32f10x_xl.s │ │ │ ├── arm │ │ │ ├── startup_stm32f10x_cl.s │ │ │ ├── startup_stm32f10x_hd.s │ │ │ ├── startup_stm32f10x_hd_vl.s │ │ │ ├── startup_stm32f10x_ld.s │ │ │ ├── startup_stm32f10x_ld_vl.s │ │ │ ├── startup_stm32f10x_md.s │ │ │ ├── startup_stm32f10x_md_vl.s │ │ │ └── startup_stm32f10x_xl.s │ │ │ ├── gcc_ride7 │ │ │ ├── startup_stm32f10x_cl.s │ │ │ ├── startup_stm32f10x_hd.s │ │ │ ├── startup_stm32f10x_hd_vl.s │ │ │ ├── startup_stm32f10x_ld.s │ │ │ ├── startup_stm32f10x_ld_vl.s │ │ │ ├── startup_stm32f10x_md.s │ │ │ ├── startup_stm32f10x_md_vl.s │ │ │ └── startup_stm32f10x_xl.s │ │ │ ├── iar │ │ │ ├── startup_stm32f10x_cl.s │ │ │ ├── startup_stm32f10x_hd.s │ │ │ ├── startup_stm32f10x_hd_vl.s │ │ │ ├── startup_stm32f10x_ld.s │ │ │ ├── startup_stm32f10x_ld_vl.s │ │ │ ├── startup_stm32f10x_md.s │ │ │ ├── startup_stm32f10x_md_vl.s │ │ │ └── startup_stm32f10x_xl.s │ │ │ └── system_stm32f10x.c │ ├── Include │ │ ├── arm_common_tables.h │ │ ├── arm_math.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm3.h │ │ ├── core_cm4.h │ │ ├── core_cm4_simd.h │ │ ├── core_cmFunc.h │ │ ├── core_cmInstr.h │ │ ├── core_sc000.h │ │ └── core_sc300.h │ └── RTOS │ │ └── cmsis_os.h │ └── STM32F10x_StdPeriph_Driver │ ├── inc │ ├── misc.h │ ├── stm32f10x_adc.h │ ├── stm32f10x_bkp.h │ ├── stm32f10x_can.h │ ├── stm32f10x_cec.h │ ├── stm32f10x_crc.h │ ├── stm32f10x_dac.h │ ├── stm32f10x_dbgmcu.h │ ├── stm32f10x_dma.h │ ├── stm32f10x_exti.h │ ├── stm32f10x_flash.h │ ├── stm32f10x_fsmc.h │ ├── stm32f10x_gpio.h │ ├── stm32f10x_i2c.h │ ├── stm32f10x_iwdg.h │ ├── stm32f10x_pwr.h │ ├── stm32f10x_rcc.h │ ├── stm32f10x_rtc.h │ ├── stm32f10x_sdio.h │ ├── stm32f10x_spi.h │ ├── stm32f10x_tim.h │ ├── stm32f10x_usart.h │ └── stm32f10x_wwdg.h │ └── src │ ├── misc.c │ ├── stm32f10x_adc.c │ ├── stm32f10x_bkp.c │ ├── stm32f10x_can.c │ ├── stm32f10x_cec.c │ ├── stm32f10x_crc.c │ ├── stm32f10x_dac.c │ ├── stm32f10x_dbgmcu.c │ ├── stm32f10x_dma.c │ ├── stm32f10x_exti.c │ ├── stm32f10x_flash.c │ ├── stm32f10x_fsmc.c │ ├── stm32f10x_gpio.c │ ├── stm32f10x_i2c.c │ ├── stm32f10x_iwdg.c │ ├── stm32f10x_pwr.c │ ├── stm32f10x_rcc.c │ ├── stm32f10x_rtc.c │ ├── stm32f10x_sdio.c │ ├── stm32f10x_spi.c │ ├── stm32f10x_tim.c │ ├── stm32f10x_usart.c │ └── stm32f10x_wwdg.c └── smarttimer ├── smarttimer.c └── smarttimer.h /.gitignore: -------------------------------------------------------------------------------- 1 | demo/Objects 2 | demo/Listings 3 | demo/Jlink*.* 4 | smarttimer/*.swp 5 | tags 6 | cscope.out 7 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## 1．SmartTimer能干什么？ 2 | 3 | 4 | 简单说来，**SmartTimer**是一个轻量级的基于STM32的定时器调度器，在单片机”裸跑”的情况下，可以很方便的实现异步编程。 5 | 6 | 它可以应用在对实时性要求没那么高的场合，比如说一个空气检测装置，每200ms收集一次甲醛数据，这个任务显然对实时性要求没那么高，如果时间上相差几毫秒，甚至几十毫秒也没关系，那么使用SmartTimer非常适合；而如果开发一个四轴飞行器，无论是对陀螺仪数据的采集、计算，以及对4个电机的控制，在时间的控制上都需要非常精确。那么这种场合下SmartTimer无法胜任，你需要一个带有抢占优先级机制的实时系统。 7 | 8 | 不同的场景，选择不同的工具和架构才是最合理的，**SmartTimer**只能做它力所能及的事情。 9 | 10 | 虽然**SmartTimer**是基于STM32开发的，但是它可以很方便的移植到其他的单片机上。 11 | 12 | 13 | ## 2. SmartTimer的一般用法 14 | 15 | ### 2.1 Runlater 16 | 17 | 在单片机编程中，想实现在”xxx毫秒后调用xxx函数”的功能，一般有3种方法： 18 | 19 | 1. 用阻塞的，非精确的方式，就是用for(i=0;i<0xffff;i++);这种循环等待的方式，来非精确的延迟一段时间，然后再顺序执行下面的程序； 20 | 2. 利用硬件定时器实现异步的精确延时，把XXX函数在定时器中断里执行； 21 | 3. 同样是利用硬件定时器，但是只在定时器中断里设置标志位，在系统的主While循环中检测这个标志位，当检测到标志置位后，去运行XXX函数。 22 | 23 | 从理论上来说，以上3种方式中，第3种采用定时器设定标志位的方法最好。因为首先主程序不用阻塞，在等待的时间里，MCU完全可以去做其他的事情，其次在定时器中断里不用占用太多的时间，节约中断资源。但这种方式有个缺点，就是实现起来相对麻烦一些。因为如果你要有N个runlater的需求，那么就得设置N个标志位，还要考虑定时器的分配、设定。在程序主While循环里也会遍布N个查询标志位的if语句。如果N足够多，其实大于5个，就会比较头疼。这样会使主While循环看起来很乱。这样的实现不够简洁、优雅。 24 | 25 | **SmartTimer**首先解决的就是这个问题，它可以优雅地延迟调用某函数。 26 | 27 | ### 2.2 Runloop 28 | 29 | 在定时器编程方面还有另一个典型需求，就是“每隔xxx毫秒运行一次XXX函数,一共运行XXX次”。这个实现起来和runlater差不多，就是加一个运行次数的技术标志。我就不再赘述了。还是那句话： 30 | 31 | **SmartTimer**可以优雅的实现Runloop功能。 32 | 33 | ### 2.3 Delay 34 | 并不是说非阻塞就一定比阻塞好，因为在某些场景下，必须得用到阻塞，使单片机停下来等待某个事件。那么SmartTimer也可以提供这个功能。 35 | 36 | ## 3. SmartTimer的高级用法 37 | 所谓的高级用法，并不是说SmartTimer有隐藏模式，能开启黑科技。而是说，如果你能转变思路，举一反三地话，可以利用SmartTimer提供的简单功能实现更加优化、合理的系统结构。 38 | 39 | 传统的单片机裸跑一般采用状态机模式，就是在主While循环里设定一些标志位或是设定好程序进行的步骤，根据事件的进程来跳转程序。简单的说来，这是一种顺序执行的程序结构。其灵活性和实时性并不高，尤其是当需要处理的业务越来越多，越来越复杂时，状态机会臃肿不堪，一不留神（其实是一定以及肯定）就会深埋bug于其中，调试解决BUG时也会异常痛苦。 40 | 41 | 42 | 如果你能转换一下思路，不再把业务逻辑中各个模块的关系看成基于因果（顺序），而是基于时间，模块间如果需要确定次序可以采用标志位进行同步。那么恭喜你，你已经有了采用实时系统的思想，可以尝试使用RT-thread等操作系统来完成你的项目了。但是，使用操作系统有几个问题，第一是当单片机资源有限的时候，使用操作系统恐怕不太合适；第二是学习操作系统本身有一定的难度，至少你需要花费一定的时间；第三如果你的项目复杂度没有那么高，使用操作系统有点大材小用。 43 | 44 | 那么，请允许我没羞没臊的说一句，其实利用**SmartTimer**中的Runloop功能可以简单的实现基于时间的主程序框架。 45 | 46 | ## 4.关于Demo 47 | 与源码一起提供的，还有一个Demo程序。这个Demo比较简单，主要是为了测试SmartTimer的功能。Demo程序基本可以体现Runlater，Runloop，Delay功能。同时也能基本体现基于时间的编程思想（单片机裸跑程序框架）。 48 | 49 | ## 5.SmartTimer的使用 50 | SmartTimer.h中声明的公开函数并不多，总共有8个： 51 | 52 | ```C 53 | void stim_init ( void ); 54 | 55 | void stim_tick (void); 56 | 57 | void stim_mainloop ( void ); 58 | 59 | int8_t stim_loop ( uint16_t delayms, void (*callback)(void), uint16_t times); 60 | 61 | int8_t stim_runlater ( uint16_t delayms, void (*callback)(void)); 62 | 63 | void stim_delay ( uint16_t delayms); 64 | 65 | void stim_kill_event(int8_t id); 66 | 67 | void stim_remove_event(int8_t id); 68 | ``` 69 | 70 | 下面我将逐一介绍 71 | ### 5.1 必要的前提 72 | SmartTimer能够工作的必要条件是: 73 | 74 | - **A.** 设置Systick的定时中断（也可以是其他的硬件定时器TIMx,我选择的是比较简单的Systick），我默认设置为1ms中断一次，使用者可以根据自己的情况来更改。Systick时钟的设置在stim_init函数中，该函数必须在主程序初始化阶段调用一次。 75 | - **B.** 在定时器中断函数中调用stim_tick()；可以说，这个函数是**SmartTimer**的引擎，如A步骤所述，默认情况下，每1ms，定时器中断会调用一次stim_tick(); 76 | - **C.** 在主While循环中执行stim_mainloop()，这个函数主要有两个作用，一是执行定时结束后的回调函数；二是回收使用完毕的timer事件的资源。 77 | 78 | ### 5.2 开始使用SmartTimer 79 | 做好以上的搭建工作后，就可以开始使用**SmartTimer**了。 80 | 81 | 82 | 83 | > int8_t stim_runlater ( uint16_t delayms, void (*callback)(void))； 84 | 85 | 该函数接受两个参数，返回定时事件的id。参数delayms传入延迟多长时间，注意这里的单位是根据之前A步骤里，你设置的时间滴答来确定的(默认单位是1ms)；第二个参数是回调函数的函数指针，目前只支持没有参数，且无返回值的回调函数，未来会考虑加入带参数和返回值的回调。 86 | 举例： 87 | 88 | ``timer_runlater(100,ledflash); //100豪秒(100*1ms=100ms)后,执行void ledflash(void)函数`` 89 | 90 | 如果在stim_init（）中，设置的时钟滴答为10ms执行一次，那么传入同样的参数，意义就会改变： 91 | 92 | ``timer_runlater(100,ledflash); //1秒(100*10ms=1000ms=1S)后,执行void ledflash(void)函数`` 93 | 94 | 95 | 96 | > int8_t stim_loop ( uint16_t delayms, void (*callback)(void), uint16_t times); 97 | 98 | 这个函数的参数意义同runlater差不多，我就不详细说明了。 该函数接收3个参数，delayms为延迟时间，callback为回调函数指针，times是循环次数。 举例(以1ms滴答为例)： 99 | 100 | ``timer_runloop(50,ledflash,5); // 每50ms，执行一次ledflash()，总共执行5次`` 101 | ``timer_runloop(80,ledflash, TIMER_LOOP_FOREVER); // 每80ms，执行一次ledflash(),无限循环。`` 102 | 103 | 104 | 105 | 106 | > void timer_delay ( uint16_t delayms); //延迟xx ms 107 | 108 | 这个函数会阻塞主程序，并延迟一段时间。 109 | 110 | > void stim_kill_event(int8_t id); 111 | > 112 | > void stim_remove_event(int8_t id); 113 | 114 | 这两个函数，可以将之前设定的定时事件取消。比如之前用stim_loop无限循环了一个事件，当获取某个指令后，需要取消这个任务，则可以用这两个函数取消事件调度。这两个函数的区别是： 115 | 116 | ``void stim_kill_event(int8_t id); //直接取消事件，忽略未处理完成的调度任务。`` 117 | ``void stim_remove_event(int8_t id);//将已经完成计时的调度任务处理完毕之后，再取消事件`` 118 | 119 | ### 5.3 注意事项 120 | SmartTimer可接受的Timer event数量是有上限的，这个上限由smarttimer.h中的宏定义 121 | 122 | ``#define TIMEREVENT_MAX_SIZE 20`` 123 | 124 | 来决定的。默认为20个，你可以根据实际情况增加或减少。但不可多于128个 125 | 126 | -------------------------------------------------------------------------------- /demo/app/board.h: -------------------------------------------------------------------------------- 1 | #ifndef __BOARD_H__ 2 | #define __BOARD_H__ 3 | 4 | #include 5 | 6 | #define SYS_LEDPORT GPIOC 7 | #define SYS_LEDCTRL GPIO_Pin_10 8 | 9 | #endif 10 | 11 | -------------------------------------------------------------------------------- /demo/app/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lmooml/SmartTimer/8f81d89a6c34fb115080b3b8707d705c24bcfec4/demo/app/main.c -------------------------------------------------------------------------------- /demo/app/stm32_it.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32_it.c 4 | * @author MCD Application Team 5 | * @version V4.0.0 6 | * @date 21-January-2013 7 | * @brief Main Interrupt Service Routines. 8 | * This file provides template for all exceptions handler and peripherals 9 | * interrupt service routine. 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© COPYRIGHT 2013 STMicroelectronics

14 | * 15 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 16 | * You may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.st.com/software_license_agreement_liberty_v2 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | * 27 | ****************************************************************************** 28 | */ 29 | 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32_it.h" 33 | #include "smarttimer.h" 34 | #include 35 | 36 | 37 | 38 | /* Private typedef -----------------------------------------------------------*/ 39 | /* Private define ------------------------------------------------------------*/ 40 | /* Private macro -------------------------------------------------------------*/ 41 | /* Private variables ---------------------------------------------------------*/ 42 | /* Private function prototypes -----------------------------------------------*/ 43 | /* Private functions ---------------------------------------------------------*/ 44 | 45 | /******************************************************************************/ 46 | /* Cortex-M Processor Exceptions Handlers */ 47 | /******************************************************************************/ 48 | 49 | /******************************************************************************* 50 | * Function Name : NMI_Handler 51 | * Description : This function handles NMI exception. 52 | * Input : None 53 | * Output : None 54 | * Return : None 55 | *******************************************************************************/ 56 | void NMI_Handler(void) 57 | { 58 | } 59 | 60 | /******************************************************************************* 61 | * Function Name : HardFault_Handler 62 | * Description : This function handles Hard Fault exception. 63 | * Input : None 64 | * Output : None 65 | * Return : None 66 | *******************************************************************************/ 67 | void HardFault_Handler(void) 68 | { 69 | /* Go to infinite loop when Hard Fault exception occurs */ 70 | printf("HardFault!!"); 71 | while (1) 72 | { 73 | } 74 | } 75 | 76 | /******************************************************************************* 77 | * Function Name : MemManage_Handler 78 | * Description : This function handles Memory Manage exception. 79 | * Input : None 80 | * Output : None 81 | * Return : None 82 | *******************************************************************************/ 83 | void MemManage_Handler(void) 84 | { 85 | /* Go to infinite loop when Memory Manage exception occurs */ 86 | while (1) 87 | { 88 | } 89 | } 90 | 91 | /******************************************************************************* 92 | * Function Name : BusFault_Handler 93 | * Description : This function handles Bus Fault exception. 94 | * Input : None 95 | * Output : None 96 | * Return : None 97 | *******************************************************************************/ 98 | void BusFault_Handler(void) 99 | { 100 | /* Go to infinite loop when Bus Fault exception occurs */ 101 | while (1) 102 | { 103 | } 104 | } 105 | 106 | /******************************************************************************* 107 | * Function Name : UsageFault_Handler 108 | * Description : This function handles Usage Fault exception. 109 | * Input : None 110 | * Output : None 111 | * Return : None 112 | *******************************************************************************/ 113 | void UsageFault_Handler(void) 114 | { 115 | /* Go to infinite loop when Usage Fault exception occurs */ 116 | while (1) 117 | { 118 | } 119 | } 120 | 121 | /******************************************************************************* 122 | * Function Name : SVC_Handler 123 | * Description : This function handles SVCall exception. 124 | * Input : None 125 | * Output : None 126 | * Return : None 127 | *******************************************************************************/ 128 | void SVC_Handler(void) 129 | { 130 | } 131 | 132 | /******************************************************************************* 133 | * Function Name : DebugMon_Handler 134 | * Description : This function handles Debug Monitor exception. 135 | * Input : None 136 | * Output : None 137 | * Return : None 138 | *******************************************************************************/ 139 | void DebugMon_Handler(void) 140 | { 141 | } 142 | 143 | /******************************************************************************* 144 | * Function Name : PendSV_Handler 145 | * Description : This function handles PendSVC exception. 146 | * Input : None 147 | * Output : None 148 | * Return : None 149 | *******************************************************************************/ 150 | void PendSV_Handler(void) 151 | { 152 | } 153 | 154 | /******************************************************************************* 155 | * Function Name : SysTick_Handler 156 | * Description : This function handles SysTick Handler. 157 | * Input : None 158 | * Output : None 159 | * Return : None 160 | *******************************************************************************/ 161 | void SysTick_Handler(void) 162 | { 163 | 164 | stim_tick(); 165 | } 166 | 167 | /******************************************************************************/ 168 | /* STM32 Peripherals Interrupt Handlers */ 169 | /******************************************************************************* 170 | * Function Name : USB_IRQHandler 171 | * Description : This function handles USB Low Priority interrupts 172 | * requests. 173 | * Input : None 174 | * Output : None 175 | * Return : None 176 | *******************************************************************************/ 177 | #if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined(STM32F37X) 178 | void USB_LP_IRQHandler(void) 179 | #else 180 | void USB_LP_CAN1_RX0_IRQHandler(void) 181 | #endif 182 | { 183 | // USB_Istr(); 184 | } 185 | 186 | #if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) 187 | 188 | /******************************************************************************* 189 | * Function Name : USB_FS_WKUP_IRQHandler 190 | * Description : This function handles USB WakeUp interrupt request. 191 | * Input : None 192 | * Output : None 193 | * Return : None 194 | *******************************************************************************/ 195 | void USB_FS_WKUP_IRQHandler(void) 196 | { 197 | EXTI_ClearITPendingBit(EXTI_Line18); 198 | } 199 | #endif 200 | /******************************************************************************* 201 | * Function Name : EXTI_IRQHandler 202 | * Description : This function handles External lines interrupt request. 203 | * Input : None 204 | * Output : None 205 | * Return : None 206 | *******************************************************************************/ 207 | #if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) 208 | void EXTI0_IRQHandler(void) 209 | #elif defined (STM32F37X) 210 | void EXTI2_TS_IRQHandler(void) 211 | #else 212 | void EXTI9_5_IRQHandler(void) 213 | #endif 214 | { 215 | 216 | } 217 | 218 | void EXTI4_IRQHandler(void) 219 | { 220 | 221 | 222 | } 223 | /******************************************************************************* 224 | * Function Name : USBWakeUp_IRQHandler 225 | * Description : This function handles USB WakeUp interrupt request. 226 | * Input : None 227 | * Output : None 228 | * Return : None 229 | *******************************************************************************/ 230 | void USBWakeUp_IRQHandler(void) 231 | { 232 | 233 | } 234 | 235 | /******************************************************************************/ 236 | /* STM32 Peripherals Interrupt Handlers */ 237 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ 238 | /* available peripheral interrupt handler's name please refer to the startup */ 239 | /* file (startup_stm32xxx.s). */ 240 | /******************************************************************************/ 241 | 242 | /******************************************************************************* 243 | * Function Name : PPP_IRQHandler 244 | * Description : This function handles PPP interrupt request. 245 | * Input : None 246 | * Output : None 247 | * Return : None 248 | *******************************************************************************/ 249 | /*void PPP_IRQHandler(void) 250 | { 251 | }*/ 252 | 253 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 254 | 255 | -------------------------------------------------------------------------------- /demo/app/stm32_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32_it.h 4 | * @author MCD Application Team 5 | * @version V4.0.0 6 | * @date 21-January-2013 7 | * @brief This file contains the headers of the interrupt handlers. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32_IT_H 31 | #define __STM32_IT_H 32 | 33 | /* Includes ------------------------------------------------------------------*/ 34 | #include "stm32f10x.h" 35 | 36 | /* Exported types ------------------------------------------------------------*/ 37 | /* Exported constants --------------------------------------------------------*/ 38 | /* Exported macro ------------------------------------------------------------*/ 39 | /* Exported functions ------------------------------------------------------- */ 40 | 41 | void NMI_Handler(void); 42 | void HardFault_Handler(void); 43 | void MemManage_Handler(void); 44 | void BusFault_Handler(void); 45 | void UsageFault_Handler(void); 46 | void SVC_Handler(void); 47 | void DebugMon_Handler(void); 48 | void PendSV_Handler(void); 49 | void SysTick_Handler(void); 50 | void USB_LP_CAN1_RX0_IRQHandler(void); 51 | void EXTI9_5_IRQHandler(void); 52 | void USBWakeUp_IRQHandler(void); 53 | void EXTI4_IRQHandler(void); 54 | 55 | #endif /* __STM32_IT_H */ 56 | 57 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 58 | 59 | 60 | -------------------------------------------------------------------------------- /demo/app/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_conf.h 4 | * @author MCD Application Team 5 | * @version V4.0.0 6 | * @date 21-January-2013 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_CONF_H 31 | #define __STM32F10x_CONF_H 32 | 33 | /* Includes ------------------------------------------------------------------*/ 34 | /* Uncomment the line below to enable peripheral header file inclusion */ 35 | 36 | #include "stm32f10x_gpio.h" 37 | //#include "stm32f10x_pwr.h" 38 | #include "stm32f10x_rcc.h" 39 | #include "stm32f10x_usart.h" 40 | 41 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 42 | 43 | /* Exported types ------------------------------------------------------------*/ 44 | /* Exported constants --------------------------------------------------------*/ 45 | /* Uncomment the line below to expanse the "assert_param" macro in the 46 | Standard Peripheral Library drivers code */ 47 | /* #define USE_FULL_ASSERT 1 */ 48 | 49 | /* Exported macro ------------------------------------------------------------*/ 50 | #ifdef USE_FULL_ASSERT 51 | 52 | /******************************************************************************* 53 | * Macro Name : assert_param 54 | * Description : The assert_param macro is used for function's parameters check. 55 | * Input : - expr: If expr is false, it calls assert_failed function 56 | * which reports the name of the source file and the source 57 | * line number of the call that failed. 58 | * If expr is true, it returns no value. 59 | * Return : None 60 | *******************************************************************************/ 61 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 62 | /* Exported functions ------------------------------------------------------- */ 63 | void assert_failed(uint8_t* file, uint32_t line); 64 | #else 65 | #define assert_param(expr) ((void)0) 66 | #endif /* USE_FULL_ASSERT */ 67 | 68 | #endif /* __STM32F10x_CONF_H */ 69 | 70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 71 | -------------------------------------------------------------------------------- /demo/demo.uvopt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | *.c 10 | *.s*; *.src; *.a* 11 | *.obj 12 | *.lib 13 | *.txt; *.h; *.inc 14 | *.plm 15 | *.cpp 16 | 0 17 | 18 | 19 | 20 | 0 21 | 0 22 | 23 | 24 | 25 | Demo 26 | 0x4 27 | ARM-ADS 28 | 29 | 8000000 30 | 31 | 0 32 | 1 33 | 1 34 | 0 35 | 0 36 | 37 | 38 | 1 39 | 65535 40 | 0 41 | 0 42 | 0 43 | 44 | 45 | 79 46 | 66 47 | 8 48 | .\Listings\ 49 | 50 | 51 | 1 52 | 1 53 | 1 54 | 0 55 | 1 56 | 1 57 | 0 58 | 1 59 | 0 60 | 0 61 | 0 62 | 0 63 | 64 | 65 | 1 66 | 1 67 | 1 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 75 | 76 | 1 77 | 0 78 | 1 79 | 80 | 0 81 | 82 | 1 83 | 0 84 | 1 85 | 1 86 | 1 87 | 1 88 | 1 89 | 1 90 | 1 91 | 1 92 | 1 93 | 1 94 | 1 95 | 1 96 | 0 97 | 1 98 | 1 99 | 1 100 | 1 101 | 0 102 | 0 103 | 0 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | BIN\UL2CM3.DLL 115 | 116 | 117 | 118 | 0 119 | ARMRTXEVENTFLAGS 120 | -L70 -Z18 -C0 -M0 -T1 121 | 122 | 123 | 0 124 | DLGDARM 125 | (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 126 | 127 | 128 | 0 129 | ARMDBGFLAGS 130 | -T0 131 | 132 | 133 | 0 134 | UL2CM3 135 | UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL040000) 136 | 137 | 138 | 139 | 140 | 141 | 0 142 | 1 143 | sysled_id 144 | 145 | 146 | 1 147 | 1 148 | list_manager 149 | 150 | 151 | 152 | 0 153 | 154 | 155 | 0 156 | 0 157 | 1 158 | 0 159 | 1 160 | 0 161 | 0 162 | 1 163 | 0 164 | 0 165 | 0 166 | 0 167 | 0 168 | 0 169 | 0 170 | 0 171 | 0 172 | 0 173 | 0 174 | 0 175 | 0 176 | 0 177 | 0 178 | 0 179 | 180 | 181 | 182 | 0 183 | 184 | 185 | 0 186 | 187 | 188 | System Viewer\NVIC 189 | 35905 190 | 191 | 192 | 193 | 194 | 195 | 196 | app 197 | 1 198 | 0 199 | 0 200 | 0 201 | 202 | 1 203 | 1 204 | 1 205 | 0 206 | 0 207 | 0 208 | .\app\main.c 209 | main.c 210 | 0 211 | 0 212 | 213 | 214 | 1 215 | 2 216 | 1 217 | 0 218 | 0 219 | 0 220 | .\app\stm32_it.c 221 | stm32_it.c 222 | 0 223 | 0 224 | 225 | 226 | 1 227 | 3 228 | 1 229 | 1 230 | 0 231 | 0 232 | ..\smarttimer\smarttimer.c 233 | smarttimer.c 234 | 0 235 | 0 236 | 237 | 238 | 239 | 240 | fwlib 241 | 0 242 | 0 243 | 0 244 | 0 245 | 246 | 2 247 | 4 248 | 1 249 | 0 250 | 0 251 | 0 252 | .\fwlib\STM32F10x_StdPeriph_Driver\src\misc.c 253 | misc.c 254 | 0 255 | 0 256 | 257 | 258 | 2 259 | 5 260 | 1 261 | 0 262 | 0 263 | 0 264 | .\fwlib\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c 265 | stm32f10x_gpio.c 266 | 0 267 | 0 268 | 269 | 270 | 2 271 | 6 272 | 1 273 | 0 274 | 0 275 | 0 276 | .\fwlib\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c 277 | stm32f10x_rcc.c 278 | 0 279 | 0 280 | 281 | 282 | 2 283 | 7 284 | 1 285 | 0 286 | 0 287 | 0 288 | .\fwlib\CMSIS\Device\ST\STM32F10x\Source\Templates\system_stm32f10x.c 289 | system_stm32f10x.c 290 | 0 291 | 0 292 | 293 | 294 | 2 295 | 8 296 | 2 297 | 0 298 | 0 299 | 0 300 | .\fwlib\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s 301 | startup_stm32f10x_hd.s 302 | 0 303 | 0 304 | 305 | 306 | 2 307 | 9 308 | 1 309 | 0 310 | 0 311 | 0 312 | .\fwlib\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c 313 | stm32f10x_usart.c 314 | 0 315 | 0 316 | 317 | 318 | 319 | 320 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lmooml/SmartTimer/8f81d89a6c34fb115080b3b8707d705c24bcfec4/demo/fwlib/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 09-March-2012 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32f10x_system 33 | * @{ 34 | */ 35 | 36 | /** 37 | * @brief Define to prevent recursive inclusion 38 | */ 39 | #ifndef __SYSTEM_STM32F10X_H 40 | #define __SYSTEM_STM32F10X_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** @addtogroup STM32F10x_System_Includes 47 | * @{ 48 | */ 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | 55 | /** @addtogroup STM32F10x_System_Exported_types 56 | * @{ 57 | */ 58 | 59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32F10x_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32F10x_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32F10x_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /*__SYSTEM_STM32F10X_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 105 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm: -------------------------------------------------------------------------------- 1 | 2 | 3 | ;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, 4 | ;; we will only use 16-bit Thumb intructions. 5 | 6 | .extern _lc_ub_stack ; usr/sys mode stack pointer 7 | .extern _lc_ue_stack ; symbol required by debugger 8 | .extern _lc_ub_table ; ROM to RAM copy table 9 | .extern main 10 | .extern _Exit 11 | .extern exit 12 | .weak exit 13 | .global __get_argcv 14 | .weak __get_argcv 15 | .extern __argcvbuf 16 | .weak __argcvbuf 17 | ;;.extern __init_hardware 18 | .extern SystemInit 19 | 20 | .if @defined('__PROF_ENABLE__') 21 | .extern __prof_init 22 | .endif 23 | .if @defined('__POSIX__') 24 | .extern posix_main 25 | .extern _posix_boot_stack_top 26 | .endif 27 | 28 | .global _START 29 | 30 | .section .text.cstart 31 | 32 | .thumb 33 | _START: 34 | ;; anticipate possible ROM/RAM remapping 35 | ;; by loading the 'real' program address 36 | ldr r1,=_Next 37 | bx r1 38 | _Next: 39 | ;; initialize the stack pointer 40 | ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table 41 | mov sp,r1 42 | 43 | ;; call a user function which initializes function. 44 | bl SystemInit 45 | 46 | ;; copy initialized sections from ROM to RAM 47 | ;; and clear uninitialized data sections in RAM 48 | 49 | ldr r3,=_lc_ub_table 50 | movs r0,#0 51 | cploop: 52 | ldr r4,[r3,#0] ; load type 53 | ldr r5,[r3,#4] ; dst address 54 | ldr r6,[r3,#8] ; src address 55 | ldr r7,[r3,#12] ; size 56 | 57 | cmp r4,#1 58 | beq copy 59 | cmp r4,#2 60 | beq clear 61 | b done 62 | 63 | copy: 64 | subs r7,r7,#1 65 | ldrb r1,[r6,r7] 66 | strb r1,[r5,r7] 67 | bne copy 68 | 69 | adds r3,r3,#16 70 | b cploop 71 | 72 | clear: 73 | subs r7,r7,#1 74 | strb r0,[r5,r7] 75 | bne clear 76 | 77 | adds r3,r3,#16 78 | b cploop 79 | 80 | done: 81 | 82 | .if @defined('__POSIX__') 83 | 84 | ;; posix stack buffer for system upbringing 85 | ldr r0,=_posix_boot_stack_top 86 | ldr r0, [r0] 87 | mov sp,r0 88 | 89 | .else 90 | 91 | ;; load r10 with end of USR/SYS stack, which is 92 | ;; needed in case stack overflow checking is on 93 | ;; NOTE: use 16-bit instructions only, for ARMv6M 94 | ldr r0,=_lc_ue_stack 95 | mov r10,r0 96 | 97 | .endif 98 | 99 | .if @defined('__PROF_ENABLE__') 100 | bl __prof_init 101 | .endif 102 | 103 | .if @defined('__POSIX__') 104 | ;; call posix_main with no arguments 105 | bl posix_main 106 | .else 107 | ;; retrieve argc and argv (default argv[0]==NULL & argc==0) 108 | bl __get_argcv 109 | ldr r1,=__argcvbuf 110 | ;; call main 111 | bl main 112 | .endif 113 | 114 | ;; call exit using the return value from main() 115 | ;; Note. Calling exit will also run all functions 116 | ;; that were supplied through atexit(). 117 | bl exit 118 | 119 | __get_argcv: ; weak definition 120 | movs r0,#0 121 | bx lr 122 | 123 | .ltorg 124 | .endsec 125 | 126 | .calls '_START', ' ' 127 | .calls '_START','__init_vector_table' 128 | .if @defined('__PROF_ENABLE__') 129 | .calls '_START','__prof_init' 130 | .endif 131 | .if @defined('__POSIX__') 132 | .calls '_START','posix_main' 133 | .else 134 | .calls '_START','__get_argcv' 135 | .calls '_START','main' 136 | .endif 137 | .calls '_START','exit' 138 | .calls '_START','',0 139 | 140 | .end 141 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_ld.s 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 09-March-2012 7 | * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address. 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2012 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m3 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .equ BootRAM, 0xF108F85F 58 | /** 59 | * @brief This is the code that gets called when the processor first 60 | * starts execution following a reset event. Only the absolutely 61 | * necessary set is performed, after which the application 62 | * supplied main() routine is called. 63 | * @param None 64 | * @retval : None 65 | */ 66 | 67 | .section .text.Reset_Handler 68 | .weak Reset_Handler 69 | .type Reset_Handler, %function 70 | Reset_Handler: 71 | 72 | /* Copy the data segment initializers from flash to SRAM */ 73 | movs r1, #0 74 | b LoopCopyDataInit 75 | 76 | CopyDataInit: 77 | ldr r3, =_sidata 78 | ldr r3, [r3, r1] 79 | str r3, [r0, r1] 80 | adds r1, r1, #4 81 | 82 | LoopCopyDataInit: 83 | ldr r0, =_sdata 84 | ldr r3, =_edata 85 | adds r2, r0, r1 86 | cmp r2, r3 87 | bcc CopyDataInit 88 | ldr r2, =_sbss 89 | b LoopFillZerobss 90 | /* Zero fill the bss segment. */ 91 | FillZerobss: 92 | movs r3, #0 93 | str r3, [r2], #4 94 | 95 | LoopFillZerobss: 96 | ldr r3, = _ebss 97 | cmp r2, r3 98 | bcc FillZerobss 99 | 100 | /* Call the clock system intitialization function.*/ 101 | bl SystemInit 102 | /* Call static constructors */ 103 | bl __libc_init_array 104 | /* Call the application's entry point.*/ 105 | bl main 106 | bx lr 107 | .size Reset_Handler, .-Reset_Handler 108 | 109 | /** 110 | * @brief This is the code that gets called when the processor receives an 111 | * unexpected interrupt. This simply enters an infinite loop, preserving 112 | * the system state for examination by a debugger. 113 | * 114 | * @param None 115 | * @retval : None 116 | */ 117 | .section .text.Default_Handler,"ax",%progbits 118 | Default_Handler: 119 | Infinite_Loop: 120 | b Infinite_Loop 121 | .size Default_Handler, .-Default_Handler 122 | /****************************************************************************** 123 | * 124 | * The minimal vector table for a Cortex M3. Note that the proper constructs 125 | * must be placed on this to ensure that it ends up at physical address 126 | * 0x0000.0000. 127 | * 128 | ******************************************************************************/ 129 | .section .isr_vector,"a",%progbits 130 | .type g_pfnVectors, %object 131 | .size g_pfnVectors, .-g_pfnVectors 132 | 133 | 134 | g_pfnVectors: 135 | .word _estack 136 | .word Reset_Handler 137 | .word NMI_Handler 138 | .word HardFault_Handler 139 | .word MemManage_Handler 140 | .word BusFault_Handler 141 | .word UsageFault_Handler 142 | .word 0 143 | .word 0 144 | .word 0 145 | .word 0 146 | .word SVC_Handler 147 | .word DebugMon_Handler 148 | .word 0 149 | .word PendSV_Handler 150 | .word SysTick_Handler 151 | .word WWDG_IRQHandler 152 | .word PVD_IRQHandler 153 | .word TAMPER_IRQHandler 154 | .word RTC_IRQHandler 155 | .word FLASH_IRQHandler 156 | .word RCC_IRQHandler 157 | .word EXTI0_IRQHandler 158 | .word EXTI1_IRQHandler 159 | .word EXTI2_IRQHandler 160 | .word EXTI3_IRQHandler 161 | .word EXTI4_IRQHandler 162 | .word DMA1_Channel1_IRQHandler 163 | .word DMA1_Channel2_IRQHandler 164 | .word DMA1_Channel3_IRQHandler 165 | .word DMA1_Channel4_IRQHandler 166 | .word DMA1_Channel5_IRQHandler 167 | .word DMA1_Channel6_IRQHandler 168 | .word DMA1_Channel7_IRQHandler 169 | .word ADC1_2_IRQHandler 170 | .word USB_HP_CAN1_TX_IRQHandler 171 | .word USB_LP_CAN1_RX0_IRQHandler 172 | .word CAN1_RX1_IRQHandler 173 | .word CAN1_SCE_IRQHandler 174 | .word EXTI9_5_IRQHandler 175 | .word TIM1_BRK_IRQHandler 176 | .word TIM1_UP_IRQHandler 177 | .word TIM1_TRG_COM_IRQHandler 178 | .word TIM1_CC_IRQHandler 179 | .word TIM2_IRQHandler 180 | .word TIM3_IRQHandler 181 | .word 0 182 | .word I2C1_EV_IRQHandler 183 | .word I2C1_ER_IRQHandler 184 | .word 0 185 | .word 0 186 | .word SPI1_IRQHandler 187 | .word 0 188 | .word USART1_IRQHandler 189 | .word USART2_IRQHandler 190 | .word 0 191 | .word EXTI15_10_IRQHandler 192 | .word RTCAlarm_IRQHandler 193 | .word USBWakeUp_IRQHandler 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word 0 198 | .word 0 199 | .word 0 200 | .word 0 201 | .word BootRAM /* @0x108. This is for boot in RAM mode for 202 | STM32F10x Low Density devices.*/ 203 | 204 | /******************************************************************************* 205 | * 206 | * Provide weak aliases for each Exception handler to the Default_Handler. 207 | * As they are weak aliases, any function with the same name will override 208 | * this definition. 209 | * 210 | *******************************************************************************/ 211 | 212 | .weak NMI_Handler 213 | .thumb_set NMI_Handler,Default_Handler 214 | 215 | .weak HardFault_Handler 216 | .thumb_set HardFault_Handler,Default_Handler 217 | 218 | .weak MemManage_Handler 219 | .thumb_set MemManage_Handler,Default_Handler 220 | 221 | .weak BusFault_Handler 222 | .thumb_set BusFault_Handler,Default_Handler 223 | 224 | .weak UsageFault_Handler 225 | .thumb_set UsageFault_Handler,Default_Handler 226 | 227 | .weak SVC_Handler 228 | .thumb_set SVC_Handler,Default_Handler 229 | 230 | .weak DebugMon_Handler 231 | .thumb_set DebugMon_Handler,Default_Handler 232 | 233 | .weak PendSV_Handler 234 | .thumb_set PendSV_Handler,Default_Handler 235 | 236 | .weak SysTick_Handler 237 | .thumb_set SysTick_Handler,Default_Handler 238 | 239 | .weak WWDG_IRQHandler 240 | .thumb_set WWDG_IRQHandler,Default_Handler 241 | 242 | .weak PVD_IRQHandler 243 | .thumb_set PVD_IRQHandler,Default_Handler 244 | 245 | .weak TAMPER_IRQHandler 246 | .thumb_set TAMPER_IRQHandler,Default_Handler 247 | 248 | .weak RTC_IRQHandler 249 | .thumb_set RTC_IRQHandler,Default_Handler 250 | 251 | .weak FLASH_IRQHandler 252 | .thumb_set FLASH_IRQHandler,Default_Handler 253 | 254 | .weak RCC_IRQHandler 255 | .thumb_set RCC_IRQHandler,Default_Handler 256 | 257 | .weak EXTI0_IRQHandler 258 | .thumb_set EXTI0_IRQHandler,Default_Handler 259 | 260 | .weak EXTI1_IRQHandler 261 | .thumb_set EXTI1_IRQHandler,Default_Handler 262 | 263 | .weak EXTI2_IRQHandler 264 | .thumb_set EXTI2_IRQHandler,Default_Handler 265 | 266 | .weak EXTI3_IRQHandler 267 | .thumb_set EXTI3_IRQHandler,Default_Handler 268 | 269 | .weak EXTI4_IRQHandler 270 | .thumb_set EXTI4_IRQHandler,Default_Handler 271 | 272 | .weak DMA1_Channel1_IRQHandler 273 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 274 | 275 | .weak DMA1_Channel2_IRQHandler 276 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 277 | 278 | .weak DMA1_Channel3_IRQHandler 279 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 280 | 281 | .weak DMA1_Channel4_IRQHandler 282 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 283 | 284 | .weak DMA1_Channel5_IRQHandler 285 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 286 | 287 | .weak DMA1_Channel6_IRQHandler 288 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 289 | 290 | .weak DMA1_Channel7_IRQHandler 291 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 292 | 293 | .weak ADC1_2_IRQHandler 294 | .thumb_set ADC1_2_IRQHandler,Default_Handler 295 | 296 | .weak USB_HP_CAN1_TX_IRQHandler 297 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 298 | 299 | .weak USB_LP_CAN1_RX0_IRQHandler 300 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 301 | 302 | .weak CAN1_RX1_IRQHandler 303 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 304 | 305 | .weak CAN1_SCE_IRQHandler 306 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 307 | 308 | .weak EXTI9_5_IRQHandler 309 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 310 | 311 | .weak TIM1_BRK_IRQHandler 312 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 313 | 314 | .weak TIM1_UP_IRQHandler 315 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 316 | 317 | .weak TIM1_TRG_COM_IRQHandler 318 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 319 | 320 | .weak TIM1_CC_IRQHandler 321 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 322 | 323 | .weak TIM2_IRQHandler 324 | .thumb_set TIM2_IRQHandler,Default_Handler 325 | 326 | .weak TIM3_IRQHandler 327 | .thumb_set TIM3_IRQHandler,Default_Handler 328 | 329 | .weak I2C1_EV_IRQHandler 330 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 331 | 332 | .weak I2C1_ER_IRQHandler 333 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 334 | 335 | .weak SPI1_IRQHandler 336 | .thumb_set SPI1_IRQHandler,Default_Handler 337 | 338 | .weak USART1_IRQHandler 339 | .thumb_set USART1_IRQHandler,Default_Handler 340 | 341 | .weak USART2_IRQHandler 342 | .thumb_set USART2_IRQHandler,Default_Handler 343 | 344 | .weak EXTI15_10_IRQHandler 345 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 346 | 347 | .weak RTCAlarm_IRQHandler 348 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 349 | 350 | .weak USBWakeUp_IRQHandler 351 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 352 | 353 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 354 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_ld_vl.s 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 09-March-2012 7 | * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2012 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m3 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .equ BootRAM, 0xF108F85F 58 | /** 59 | * @brief This is the code that gets called when the processor first 60 | * starts execution following a reset event. Only the absolutely 61 | * necessary set is performed, after which the application 62 | * supplied main() routine is called. 63 | * @param None 64 | * @retval : None 65 | */ 66 | 67 | .section .text.Reset_Handler 68 | .weak Reset_Handler 69 | .type Reset_Handler, %function 70 | Reset_Handler: 71 | 72 | /* Copy the data segment initializers from flash to SRAM */ 73 | movs r1, #0 74 | b LoopCopyDataInit 75 | 76 | CopyDataInit: 77 | ldr r3, =_sidata 78 | ldr r3, [r3, r1] 79 | str r3, [r0, r1] 80 | adds r1, r1, #4 81 | 82 | LoopCopyDataInit: 83 | ldr r0, =_sdata 84 | ldr r3, =_edata 85 | adds r2, r0, r1 86 | cmp r2, r3 87 | bcc CopyDataInit 88 | ldr r2, =_sbss 89 | b LoopFillZerobss 90 | /* Zero fill the bss segment. */ 91 | FillZerobss: 92 | movs r3, #0 93 | str r3, [r2], #4 94 | 95 | LoopFillZerobss: 96 | ldr r3, = _ebss 97 | cmp r2, r3 98 | bcc FillZerobss 99 | 100 | /* Call the clock system intitialization function.*/ 101 | bl SystemInit 102 | /* Call static constructors */ 103 | bl __libc_init_array 104 | /* Call the application's entry point.*/ 105 | bl main 106 | bx lr 107 | .size Reset_Handler, .-Reset_Handler 108 | 109 | /** 110 | * @brief This is the code that gets called when the processor receives an 111 | * unexpected interrupt. This simply enters an infinite loop, preserving 112 | * the system state for examination by a debugger. 113 | * 114 | * @param None 115 | * @retval : None 116 | */ 117 | .section .text.Default_Handler,"ax",%progbits 118 | Default_Handler: 119 | Infinite_Loop: 120 | b Infinite_Loop 121 | .size Default_Handler, .-Default_Handler 122 | /****************************************************************************** 123 | * 124 | * The minimal vector table for a Cortex M3. Note that the proper constructs 125 | * must be placed on this to ensure that it ends up at physical address 126 | * 0x0000.0000. 127 | * 128 | ******************************************************************************/ 129 | .section .isr_vector,"a",%progbits 130 | .type g_pfnVectors, %object 131 | .size g_pfnVectors, .-g_pfnVectors 132 | 133 | 134 | g_pfnVectors: 135 | .word _estack 136 | .word Reset_Handler 137 | .word NMI_Handler 138 | .word HardFault_Handler 139 | .word MemManage_Handler 140 | .word BusFault_Handler 141 | .word UsageFault_Handler 142 | .word 0 143 | .word 0 144 | .word 0 145 | .word 0 146 | .word SVC_Handler 147 | .word DebugMon_Handler 148 | .word 0 149 | .word PendSV_Handler 150 | .word SysTick_Handler 151 | .word WWDG_IRQHandler 152 | .word PVD_IRQHandler 153 | .word TAMPER_IRQHandler 154 | .word RTC_IRQHandler 155 | .word FLASH_IRQHandler 156 | .word RCC_IRQHandler 157 | .word EXTI0_IRQHandler 158 | .word EXTI1_IRQHandler 159 | .word EXTI2_IRQHandler 160 | .word EXTI3_IRQHandler 161 | .word EXTI4_IRQHandler 162 | .word DMA1_Channel1_IRQHandler 163 | .word DMA1_Channel2_IRQHandler 164 | .word DMA1_Channel3_IRQHandler 165 | .word DMA1_Channel4_IRQHandler 166 | .word DMA1_Channel5_IRQHandler 167 | .word DMA1_Channel6_IRQHandler 168 | .word DMA1_Channel7_IRQHandler 169 | .word ADC1_IRQHandler 170 | .word 0 171 | .word 0 172 | .word 0 173 | .word 0 174 | .word EXTI9_5_IRQHandler 175 | .word TIM1_BRK_TIM15_IRQHandler 176 | .word TIM1_UP_TIM16_IRQHandler 177 | .word TIM1_TRG_COM_TIM17_IRQHandler 178 | .word TIM1_CC_IRQHandler 179 | .word TIM2_IRQHandler 180 | .word TIM3_IRQHandler 181 | .word 0 182 | .word I2C1_EV_IRQHandler 183 | .word I2C1_ER_IRQHandler 184 | .word 0 185 | .word 0 186 | .word SPI1_IRQHandler 187 | .word 0 188 | .word USART1_IRQHandler 189 | .word USART2_IRQHandler 190 | .word 0 191 | .word EXTI15_10_IRQHandler 192 | .word RTCAlarm_IRQHandler 193 | .word CEC_IRQHandler 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word 0 198 | .word 0 199 | .word 0 200 | .word 0 201 | .word 0 202 | .word 0 203 | .word 0 204 | .word 0 205 | .word TIM6_DAC_IRQHandler 206 | .word TIM7_IRQHandler 207 | .word 0 208 | .word 0 209 | .word 0 210 | .word 0 211 | .word 0 212 | .word 0 213 | .word 0 214 | .word 0 215 | .word 0 216 | .word 0 217 | .word 0 218 | .word 0 219 | .word 0 220 | .word 0 221 | .word 0 222 | .word 0 223 | .word 0 224 | .word 0 225 | .word 0 226 | .word 0 227 | .word 0 228 | .word 0 229 | .word 0 230 | .word 0 231 | .word 0 232 | .word 0 233 | .word 0 234 | .word 0 235 | .word 0 236 | .word 0 237 | .word 0 238 | .word 0 239 | .word 0 240 | .word 0 241 | .word 0 242 | .word 0 243 | .word 0 244 | .word 0 245 | .word 0 246 | .word 0 247 | .word 0 248 | .word 0 249 | .word 0 250 | .word BootRAM /* @0x01CC. This is for boot in RAM mode for 251 | STM32F10x Medium Value Line Density devices. */ 252 | 253 | /******************************************************************************* 254 | * 255 | * Provide weak aliases for each Exception handler to the Default_Handler. 256 | * As they are weak aliases, any function with the same name will override 257 | * this definition. 258 | * 259 | *******************************************************************************/ 260 | 261 | 262 | .weak NMI_Handler 263 | .thumb_set NMI_Handler,Default_Handler 264 | 265 | .weak HardFault_Handler 266 | .thumb_set HardFault_Handler,Default_Handler 267 | 268 | .weak MemManage_Handler 269 | .thumb_set MemManage_Handler,Default_Handler 270 | 271 | .weak BusFault_Handler 272 | .thumb_set BusFault_Handler,Default_Handler 273 | 274 | .weak UsageFault_Handler 275 | .thumb_set UsageFault_Handler,Default_Handler 276 | 277 | .weak SVC_Handler 278 | .thumb_set SVC_Handler,Default_Handler 279 | 280 | .weak DebugMon_Handler 281 | .thumb_set DebugMon_Handler,Default_Handler 282 | 283 | .weak PendSV_Handler 284 | .thumb_set PendSV_Handler,Default_Handler 285 | 286 | .weak SysTick_Handler 287 | .thumb_set SysTick_Handler,Default_Handler 288 | 289 | .weak WWDG_IRQHandler 290 | .thumb_set WWDG_IRQHandler,Default_Handler 291 | 292 | .weak PVD_IRQHandler 293 | .thumb_set PVD_IRQHandler,Default_Handler 294 | 295 | .weak TAMPER_IRQHandler 296 | .thumb_set TAMPER_IRQHandler,Default_Handler 297 | 298 | .weak RTC_IRQHandler 299 | .thumb_set RTC_IRQHandler,Default_Handler 300 | 301 | .weak FLASH_IRQHandler 302 | .thumb_set FLASH_IRQHandler,Default_Handler 303 | 304 | .weak RCC_IRQHandler 305 | .thumb_set RCC_IRQHandler,Default_Handler 306 | 307 | .weak EXTI0_IRQHandler 308 | .thumb_set EXTI0_IRQHandler,Default_Handler 309 | 310 | .weak EXTI1_IRQHandler 311 | .thumb_set EXTI1_IRQHandler,Default_Handler 312 | 313 | .weak EXTI2_IRQHandler 314 | .thumb_set EXTI2_IRQHandler,Default_Handler 315 | 316 | .weak EXTI3_IRQHandler 317 | .thumb_set EXTI3_IRQHandler,Default_Handler 318 | 319 | .weak EXTI4_IRQHandler 320 | .thumb_set EXTI4_IRQHandler,Default_Handler 321 | 322 | .weak DMA1_Channel1_IRQHandler 323 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 324 | 325 | .weak DMA1_Channel2_IRQHandler 326 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 327 | 328 | .weak DMA1_Channel3_IRQHandler 329 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 330 | 331 | .weak DMA1_Channel4_IRQHandler 332 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 333 | 334 | .weak DMA1_Channel5_IRQHandler 335 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 336 | 337 | .weak DMA1_Channel6_IRQHandler 338 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 339 | 340 | .weak DMA1_Channel7_IRQHandler 341 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 342 | 343 | .weak ADC1_IRQHandler 344 | .thumb_set ADC1_IRQHandler,Default_Handler 345 | 346 | .weak EXTI9_5_IRQHandler 347 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 348 | 349 | .weak TIM1_BRK_TIM15_IRQHandler 350 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler 351 | 352 | .weak TIM1_UP_TIM16_IRQHandler 353 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler 354 | 355 | .weak TIM1_TRG_COM_TIM17_IRQHandler 356 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler 357 | 358 | .weak TIM1_CC_IRQHandler 359 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 360 | 361 | .weak TIM2_IRQHandler 362 | .thumb_set TIM2_IRQHandler,Default_Handler 363 | 364 | .weak TIM3_IRQHandler 365 | .thumb_set TIM3_IRQHandler,Default_Handler 366 | 367 | .weak I2C1_EV_IRQHandler 368 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 369 | 370 | .weak I2C1_ER_IRQHandler 371 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 372 | 373 | .weak SPI1_IRQHandler 374 | .thumb_set SPI1_IRQHandler,Default_Handler 375 | 376 | .weak USART1_IRQHandler 377 | .thumb_set USART1_IRQHandler,Default_Handler 378 | 379 | .weak USART2_IRQHandler 380 | .thumb_set USART2_IRQHandler,Default_Handler 381 | 382 | .weak EXTI15_10_IRQHandler 383 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 384 | 385 | .weak RTCAlarm_IRQHandler 386 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 387 | 388 | .weak CEC_IRQHandler 389 | .thumb_set CEC_IRQHandler,Default_Handler 390 | 391 | .weak TIM6_DAC_IRQHandler 392 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 393 | 394 | .weak TIM7_IRQHandler 395 | .thumb_set TIM7_IRQHandler,Default_Handler 396 | 397 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 398 | 399 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_md.s 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 09-March-2012 7 | * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2012 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m3 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .equ BootRAM, 0xF108F85F 58 | /** 59 | * @brief This is the code that gets called when the processor first 60 | * starts execution following a reset event. Only the absolutely 61 | * necessary set is performed, after which the application 62 | * supplied main() routine is called. 63 | * @param None 64 | * @retval : None 65 | */ 66 | 67 | .section .text.Reset_Handler 68 | .weak Reset_Handler 69 | .type Reset_Handler, %function 70 | Reset_Handler: 71 | 72 | /* Copy the data segment initializers from flash to SRAM */ 73 | movs r1, #0 74 | b LoopCopyDataInit 75 | 76 | CopyDataInit: 77 | ldr r3, =_sidata 78 | ldr r3, [r3, r1] 79 | str r3, [r0, r1] 80 | adds r1, r1, #4 81 | 82 | LoopCopyDataInit: 83 | ldr r0, =_sdata 84 | ldr r3, =_edata 85 | adds r2, r0, r1 86 | cmp r2, r3 87 | bcc CopyDataInit 88 | ldr r2, =_sbss 89 | b LoopFillZerobss 90 | /* Zero fill the bss segment. */ 91 | FillZerobss: 92 | movs r3, #0 93 | str r3, [r2], #4 94 | 95 | LoopFillZerobss: 96 | ldr r3, = _ebss 97 | cmp r2, r3 98 | bcc FillZerobss 99 | 100 | /* Call the clock system intitialization function.*/ 101 | bl SystemInit 102 | /* Call static constructors */ 103 | bl __libc_init_array 104 | /* Call the application's entry point.*/ 105 | bl main 106 | bx lr 107 | .size Reset_Handler, .-Reset_Handler 108 | 109 | /** 110 | * @brief This is the code that gets called when the processor receives an 111 | * unexpected interrupt. This simply enters an infinite loop, preserving 112 | * the system state for examination by a debugger. 113 | * 114 | * @param None 115 | * @retval : None 116 | */ 117 | .section .text.Default_Handler,"ax",%progbits 118 | Default_Handler: 119 | Infinite_Loop: 120 | b Infinite_Loop 121 | .size Default_Handler, .-Default_Handler 122 | /****************************************************************************** 123 | * 124 | * The minimal vector table for a Cortex M3. Note that the proper constructs 125 | * must be placed on this to ensure that it ends up at physical address 126 | * 0x0000.0000. 127 | * 128 | ******************************************************************************/ 129 | .section .isr_vector,"a",%progbits 130 | .type g_pfnVectors, %object 131 | .size g_pfnVectors, .-g_pfnVectors 132 | 133 | 134 | g_pfnVectors: 135 | .word _estack 136 | .word Reset_Handler 137 | .word NMI_Handler 138 | .word HardFault_Handler 139 | .word MemManage_Handler 140 | .word BusFault_Handler 141 | .word UsageFault_Handler 142 | .word 0 143 | .word 0 144 | .word 0 145 | .word 0 146 | .word SVC_Handler 147 | .word DebugMon_Handler 148 | .word 0 149 | .word PendSV_Handler 150 | .word SysTick_Handler 151 | .word WWDG_IRQHandler 152 | .word PVD_IRQHandler 153 | .word TAMPER_IRQHandler 154 | .word RTC_IRQHandler 155 | .word FLASH_IRQHandler 156 | .word RCC_IRQHandler 157 | .word EXTI0_IRQHandler 158 | .word EXTI1_IRQHandler 159 | .word EXTI2_IRQHandler 160 | .word EXTI3_IRQHandler 161 | .word EXTI4_IRQHandler 162 | .word DMA1_Channel1_IRQHandler 163 | .word DMA1_Channel2_IRQHandler 164 | .word DMA1_Channel3_IRQHandler 165 | .word DMA1_Channel4_IRQHandler 166 | .word DMA1_Channel5_IRQHandler 167 | .word DMA1_Channel6_IRQHandler 168 | .word DMA1_Channel7_IRQHandler 169 | .word ADC1_2_IRQHandler 170 | .word USB_HP_CAN1_TX_IRQHandler 171 | .word USB_LP_CAN1_RX0_IRQHandler 172 | .word CAN1_RX1_IRQHandler 173 | .word CAN1_SCE_IRQHandler 174 | .word EXTI9_5_IRQHandler 175 | .word TIM1_BRK_IRQHandler 176 | .word TIM1_UP_IRQHandler 177 | .word TIM1_TRG_COM_IRQHandler 178 | .word TIM1_CC_IRQHandler 179 | .word TIM2_IRQHandler 180 | .word TIM3_IRQHandler 181 | .word TIM4_IRQHandler 182 | .word I2C1_EV_IRQHandler 183 | .word I2C1_ER_IRQHandler 184 | .word I2C2_EV_IRQHandler 185 | .word I2C2_ER_IRQHandler 186 | .word SPI1_IRQHandler 187 | .word SPI2_IRQHandler 188 | .word USART1_IRQHandler 189 | .word USART2_IRQHandler 190 | .word USART3_IRQHandler 191 | .word EXTI15_10_IRQHandler 192 | .word RTCAlarm_IRQHandler 193 | .word USBWakeUp_IRQHandler 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word 0 198 | .word 0 199 | .word 0 200 | .word 0 201 | .word BootRAM /* @0x108. This is for boot in RAM mode for 202 | STM32F10x Medium Density devices. */ 203 | 204 | /******************************************************************************* 205 | * 206 | * Provide weak aliases for each Exception handler to the Default_Handler. 207 | * As they are weak aliases, any function with the same name will override 208 | * this definition. 209 | * 210 | *******************************************************************************/ 211 | 212 | .weak NMI_Handler 213 | .thumb_set NMI_Handler,Default_Handler 214 | 215 | .weak HardFault_Handler 216 | .thumb_set HardFault_Handler,Default_Handler 217 | 218 | .weak MemManage_Handler 219 | .thumb_set MemManage_Handler,Default_Handler 220 | 221 | .weak BusFault_Handler 222 | .thumb_set BusFault_Handler,Default_Handler 223 | 224 | .weak UsageFault_Handler 225 | .thumb_set UsageFault_Handler,Default_Handler 226 | 227 | .weak SVC_Handler 228 | .thumb_set SVC_Handler,Default_Handler 229 | 230 | .weak DebugMon_Handler 231 | .thumb_set DebugMon_Handler,Default_Handler 232 | 233 | .weak PendSV_Handler 234 | .thumb_set PendSV_Handler,Default_Handler 235 | 236 | .weak SysTick_Handler 237 | .thumb_set SysTick_Handler,Default_Handler 238 | 239 | .weak WWDG_IRQHandler 240 | .thumb_set WWDG_IRQHandler,Default_Handler 241 | 242 | .weak PVD_IRQHandler 243 | .thumb_set PVD_IRQHandler,Default_Handler 244 | 245 | .weak TAMPER_IRQHandler 246 | .thumb_set TAMPER_IRQHandler,Default_Handler 247 | 248 | .weak RTC_IRQHandler 249 | .thumb_set RTC_IRQHandler,Default_Handler 250 | 251 | .weak FLASH_IRQHandler 252 | .thumb_set FLASH_IRQHandler,Default_Handler 253 | 254 | .weak RCC_IRQHandler 255 | .thumb_set RCC_IRQHandler,Default_Handler 256 | 257 | .weak EXTI0_IRQHandler 258 | .thumb_set EXTI0_IRQHandler,Default_Handler 259 | 260 | .weak EXTI1_IRQHandler 261 | .thumb_set EXTI1_IRQHandler,Default_Handler 262 | 263 | .weak EXTI2_IRQHandler 264 | .thumb_set EXTI2_IRQHandler,Default_Handler 265 | 266 | .weak EXTI3_IRQHandler 267 | .thumb_set EXTI3_IRQHandler,Default_Handler 268 | 269 | .weak EXTI4_IRQHandler 270 | .thumb_set EXTI4_IRQHandler,Default_Handler 271 | 272 | .weak DMA1_Channel1_IRQHandler 273 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 274 | 275 | .weak DMA1_Channel2_IRQHandler 276 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 277 | 278 | .weak DMA1_Channel3_IRQHandler 279 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 280 | 281 | .weak DMA1_Channel4_IRQHandler 282 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 283 | 284 | .weak DMA1_Channel5_IRQHandler 285 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 286 | 287 | .weak DMA1_Channel6_IRQHandler 288 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 289 | 290 | .weak DMA1_Channel7_IRQHandler 291 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 292 | 293 | .weak ADC1_2_IRQHandler 294 | .thumb_set ADC1_2_IRQHandler,Default_Handler 295 | 296 | .weak USB_HP_CAN1_TX_IRQHandler 297 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 298 | 299 | .weak USB_LP_CAN1_RX0_IRQHandler 300 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 301 | 302 | .weak CAN1_RX1_IRQHandler 303 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 304 | 305 | .weak CAN1_SCE_IRQHandler 306 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 307 | 308 | .weak EXTI9_5_IRQHandler 309 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 310 | 311 | .weak TIM1_BRK_IRQHandler 312 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 313 | 314 | .weak TIM1_UP_IRQHandler 315 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 316 | 317 | .weak TIM1_TRG_COM_IRQHandler 318 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 319 | 320 | .weak TIM1_CC_IRQHandler 321 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 322 | 323 | .weak TIM2_IRQHandler 324 | .thumb_set TIM2_IRQHandler,Default_Handler 325 | 326 | .weak TIM3_IRQHandler 327 | .thumb_set TIM3_IRQHandler,Default_Handler 328 | 329 | .weak TIM4_IRQHandler 330 | .thumb_set TIM4_IRQHandler,Default_Handler 331 | 332 | .weak I2C1_EV_IRQHandler 333 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 334 | 335 | .weak I2C1_ER_IRQHandler 336 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 337 | 338 | .weak I2C2_EV_IRQHandler 339 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 340 | 341 | .weak I2C2_ER_IRQHandler 342 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 343 | 344 | .weak SPI1_IRQHandler 345 | .thumb_set SPI1_IRQHandler,Default_Handler 346 | 347 | .weak SPI2_IRQHandler 348 | .thumb_set SPI2_IRQHandler,Default_Handler 349 | 350 | .weak USART1_IRQHandler 351 | .thumb_set USART1_IRQHandler,Default_Handler 352 | 353 | .weak USART2_IRQHandler 354 | .thumb_set USART2_IRQHandler,Default_Handler 355 | 356 | .weak USART3_IRQHandler 357 | .thumb_set USART3_IRQHandler,Default_Handler 358 | 359 | .weak EXTI15_10_IRQHandler 360 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 361 | 362 | .weak RTCAlarm_IRQHandler 363 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 364 | 365 | .weak USBWakeUp_IRQHandler 366 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 367 | 368 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 369 | 370 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_ld.s 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 09-March-2012 7 | * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2012 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m3 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .equ BootRAM, 0xF108F85F 58 | /** 59 | * @brief This is the code that gets called when the processor first 60 | * starts execution following a reset event. Only the absolutely 61 | * necessary set is performed, after which the application 62 | * supplied main() routine is called. 63 | * @param None 64 | * @retval : None 65 | */ 66 | 67 | .section .text.Reset_Handler 68 | .weak Reset_Handler 69 | .type Reset_Handler, %function 70 | Reset_Handler: 71 | 72 | /* Copy the data segment initializers from flash to SRAM */ 73 | movs r1, #0 74 | b LoopCopyDataInit 75 | 76 | CopyDataInit: 77 | ldr r3, =_sidata 78 | ldr r3, [r3, r1] 79 | str r3, [r0, r1] 80 | adds r1, r1, #4 81 | 82 | LoopCopyDataInit: 83 | ldr r0, =_sdata 84 | ldr r3, =_edata 85 | adds r2, r0, r1 86 | cmp r2, r3 87 | bcc CopyDataInit 88 | ldr r2, =_sbss 89 | b LoopFillZerobss 90 | /* Zero fill the bss segment. */ 91 | FillZerobss: 92 | movs r3, #0 93 | str r3, [r2], #4 94 | 95 | LoopFillZerobss: 96 | ldr r3, = _ebss 97 | cmp r2, r3 98 | bcc FillZerobss 99 | /* Call the clock system intitialization function.*/ 100 | bl SystemInit 101 | /* Call the application's entry point.*/ 102 | bl main 103 | bx lr 104 | .size Reset_Handler, .-Reset_Handler 105 | 106 | /** 107 | * @brief This is the code that gets called when the processor receives an 108 | * unexpected interrupt. This simply enters an infinite loop, preserving 109 | * the system state for examination by a debugger. 110 | * @param None 111 | * @retval None 112 | */ 113 | .section .text.Default_Handler,"ax",%progbits 114 | Default_Handler: 115 | Infinite_Loop: 116 | b Infinite_Loop 117 | .size Default_Handler, .-Default_Handler 118 | /****************************************************************************** 119 | * 120 | * The minimal vector table for a Cortex M3. Note that the proper constructs 121 | * must be placed on this to ensure that it ends up at physical address 122 | * 0x0000.0000. 123 | * 124 | ******************************************************************************/ 125 | .section .isr_vector,"a",%progbits 126 | .type g_pfnVectors, %object 127 | .size g_pfnVectors, .-g_pfnVectors 128 | 129 | 130 | g_pfnVectors: 131 | .word _estack 132 | .word Reset_Handler 133 | .word NMI_Handler 134 | .word HardFault_Handler 135 | .word MemManage_Handler 136 | .word BusFault_Handler 137 | .word UsageFault_Handler 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word SVC_Handler 143 | .word DebugMon_Handler 144 | .word 0 145 | .word PendSV_Handler 146 | .word SysTick_Handler 147 | .word WWDG_IRQHandler 148 | .word PVD_IRQHandler 149 | .word TAMPER_IRQHandler 150 | .word RTC_IRQHandler 151 | .word FLASH_IRQHandler 152 | .word RCC_IRQHandler 153 | .word EXTI0_IRQHandler 154 | .word EXTI1_IRQHandler 155 | .word EXTI2_IRQHandler 156 | .word EXTI3_IRQHandler 157 | .word EXTI4_IRQHandler 158 | .word DMA1_Channel1_IRQHandler 159 | .word DMA1_Channel2_IRQHandler 160 | .word DMA1_Channel3_IRQHandler 161 | .word DMA1_Channel4_IRQHandler 162 | .word DMA1_Channel5_IRQHandler 163 | .word DMA1_Channel6_IRQHandler 164 | .word DMA1_Channel7_IRQHandler 165 | .word ADC1_2_IRQHandler 166 | .word USB_HP_CAN1_TX_IRQHandler 167 | .word USB_LP_CAN1_RX0_IRQHandler 168 | .word CAN1_RX1_IRQHandler 169 | .word CAN1_SCE_IRQHandler 170 | .word EXTI9_5_IRQHandler 171 | .word TIM1_BRK_IRQHandler 172 | .word TIM1_UP_IRQHandler 173 | .word TIM1_TRG_COM_IRQHandler 174 | .word TIM1_CC_IRQHandler 175 | .word TIM2_IRQHandler 176 | .word TIM3_IRQHandler 177 | .word 0 178 | .word I2C1_EV_IRQHandler 179 | .word I2C1_ER_IRQHandler 180 | .word 0 181 | .word 0 182 | .word SPI1_IRQHandler 183 | .word 0 184 | .word USART1_IRQHandler 185 | .word USART2_IRQHandler 186 | .word 0 187 | .word EXTI15_10_IRQHandler 188 | .word RTCAlarm_IRQHandler 189 | .word USBWakeUp_IRQHandler 190 | .word 0 191 | .word 0 192 | .word 0 193 | .word 0 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word BootRAM /* @0x108. This is for boot in RAM mode for 198 | STM32F10x Low Density devices.*/ 199 | 200 | /******************************************************************************* 201 | * 202 | * Provide weak aliases for each Exception handler to the Default_Handler. 203 | * As they are weak aliases, any function with the same name will override 204 | * this definition. 205 | * 206 | *******************************************************************************/ 207 | 208 | .weak NMI_Handler 209 | .thumb_set NMI_Handler,Default_Handler 210 | 211 | .weak HardFault_Handler 212 | .thumb_set HardFault_Handler,Default_Handler 213 | 214 | .weak MemManage_Handler 215 | .thumb_set MemManage_Handler,Default_Handler 216 | 217 | .weak BusFault_Handler 218 | .thumb_set BusFault_Handler,Default_Handler 219 | 220 | .weak UsageFault_Handler 221 | .thumb_set UsageFault_Handler,Default_Handler 222 | 223 | .weak SVC_Handler 224 | .thumb_set SVC_Handler,Default_Handler 225 | 226 | .weak DebugMon_Handler 227 | .thumb_set DebugMon_Handler,Default_Handler 228 | 229 | .weak PendSV_Handler 230 | .thumb_set PendSV_Handler,Default_Handler 231 | 232 | .weak SysTick_Handler 233 | .thumb_set SysTick_Handler,Default_Handler 234 | 235 | .weak WWDG_IRQHandler 236 | .thumb_set WWDG_IRQHandler,Default_Handler 237 | 238 | .weak PVD_IRQHandler 239 | .thumb_set PVD_IRQHandler,Default_Handler 240 | 241 | .weak TAMPER_IRQHandler 242 | .thumb_set TAMPER_IRQHandler,Default_Handler 243 | 244 | .weak RTC_IRQHandler 245 | .thumb_set RTC_IRQHandler,Default_Handler 246 | 247 | .weak FLASH_IRQHandler 248 | .thumb_set FLASH_IRQHandler,Default_Handler 249 | 250 | .weak RCC_IRQHandler 251 | .thumb_set RCC_IRQHandler,Default_Handler 252 | 253 | .weak EXTI0_IRQHandler 254 | .thumb_set EXTI0_IRQHandler,Default_Handler 255 | 256 | .weak EXTI1_IRQHandler 257 | .thumb_set EXTI1_IRQHandler,Default_Handler 258 | 259 | .weak EXTI2_IRQHandler 260 | .thumb_set EXTI2_IRQHandler,Default_Handler 261 | 262 | .weak EXTI3_IRQHandler 263 | .thumb_set EXTI3_IRQHandler,Default_Handler 264 | 265 | .weak EXTI4_IRQHandler 266 | .thumb_set EXTI4_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel1_IRQHandler 269 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel2_IRQHandler 272 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel3_IRQHandler 275 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel4_IRQHandler 278 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel5_IRQHandler 281 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 282 | 283 | .weak DMA1_Channel6_IRQHandler 284 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 285 | 286 | .weak DMA1_Channel7_IRQHandler 287 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 288 | 289 | .weak ADC1_2_IRQHandler 290 | .thumb_set ADC1_2_IRQHandler,Default_Handler 291 | 292 | .weak USB_HP_CAN1_TX_IRQHandler 293 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 294 | 295 | .weak USB_LP_CAN1_RX0_IRQHandler 296 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 297 | 298 | .weak CAN1_RX1_IRQHandler 299 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 300 | 301 | .weak CAN1_SCE_IRQHandler 302 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 303 | 304 | .weak EXTI9_5_IRQHandler 305 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_BRK_IRQHandler 308 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_UP_IRQHandler 311 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 312 | 313 | .weak TIM1_TRG_COM_IRQHandler 314 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 315 | 316 | .weak TIM1_CC_IRQHandler 317 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 318 | 319 | .weak TIM2_IRQHandler 320 | .thumb_set TIM2_IRQHandler,Default_Handler 321 | 322 | .weak TIM3_IRQHandler 323 | .thumb_set TIM3_IRQHandler,Default_Handler 324 | 325 | .weak I2C1_EV_IRQHandler 326 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 327 | 328 | .weak I2C1_ER_IRQHandler 329 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 330 | 331 | .weak SPI1_IRQHandler 332 | .thumb_set SPI1_IRQHandler,Default_Handler 333 | 334 | .weak USART1_IRQHandler 335 | .thumb_set USART1_IRQHandler,Default_Handler 336 | 337 | .weak USART2_IRQHandler 338 | .thumb_set USART2_IRQHandler,Default_Handler 339 | 340 | .weak EXTI15_10_IRQHandler 341 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 342 | 343 | .weak RTCAlarm_IRQHandler 344 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 345 | 346 | .weak USBWakeUp_IRQHandler 347 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 348 | 349 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 350 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_md.s 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 09-March-2012 7 | * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2012 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m3 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .equ BootRAM, 0xF108F85F 58 | /** 59 | * @brief This is the code that gets called when the processor first 60 | * starts execution following a reset event. Only the absolutely 61 | * necessary set is performed, after which the application 62 | * supplied main() routine is called. 63 | * @param None 64 | * @retval : None 65 | */ 66 | 67 | .section .text.Reset_Handler 68 | .weak Reset_Handler 69 | .type Reset_Handler, %function 70 | Reset_Handler: 71 | 72 | /* Copy the data segment initializers from flash to SRAM */ 73 | movs r1, #0 74 | b LoopCopyDataInit 75 | 76 | CopyDataInit: 77 | ldr r3, =_sidata 78 | ldr r3, [r3, r1] 79 | str r3, [r0, r1] 80 | adds r1, r1, #4 81 | 82 | LoopCopyDataInit: 83 | ldr r0, =_sdata 84 | ldr r3, =_edata 85 | adds r2, r0, r1 86 | cmp r2, r3 87 | bcc CopyDataInit 88 | ldr r2, =_sbss 89 | b LoopFillZerobss 90 | /* Zero fill the bss segment. */ 91 | FillZerobss: 92 | movs r3, #0 93 | str r3, [r2], #4 94 | 95 | LoopFillZerobss: 96 | ldr r3, = _ebss 97 | cmp r2, r3 98 | bcc FillZerobss 99 | /* Call the clock system intitialization function.*/ 100 | bl SystemInit 101 | /* Call the application's entry point.*/ 102 | bl main 103 | bx lr 104 | .size Reset_Handler, .-Reset_Handler 105 | 106 | /** 107 | * @brief This is the code that gets called when the processor receives an 108 | * unexpected interrupt. This simply enters an infinite loop, preserving 109 | * the system state for examination by a debugger. 110 | * @param None 111 | * @retval None 112 | */ 113 | .section .text.Default_Handler,"ax",%progbits 114 | Default_Handler: 115 | Infinite_Loop: 116 | b Infinite_Loop 117 | .size Default_Handler, .-Default_Handler 118 | /****************************************************************************** 119 | * 120 | * The minimal vector table for a Cortex M3. Note that the proper constructs 121 | * must be placed on this to ensure that it ends up at physical address 122 | * 0x0000.0000. 123 | * 124 | ******************************************************************************/ 125 | .section .isr_vector,"a",%progbits 126 | .type g_pfnVectors, %object 127 | .size g_pfnVectors, .-g_pfnVectors 128 | 129 | 130 | g_pfnVectors: 131 | .word _estack 132 | .word Reset_Handler 133 | .word NMI_Handler 134 | .word HardFault_Handler 135 | .word MemManage_Handler 136 | .word BusFault_Handler 137 | .word UsageFault_Handler 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word SVC_Handler 143 | .word DebugMon_Handler 144 | .word 0 145 | .word PendSV_Handler 146 | .word SysTick_Handler 147 | .word WWDG_IRQHandler 148 | .word PVD_IRQHandler 149 | .word TAMPER_IRQHandler 150 | .word RTC_IRQHandler 151 | .word FLASH_IRQHandler 152 | .word RCC_IRQHandler 153 | .word EXTI0_IRQHandler 154 | .word EXTI1_IRQHandler 155 | .word EXTI2_IRQHandler 156 | .word EXTI3_IRQHandler 157 | .word EXTI4_IRQHandler 158 | .word DMA1_Channel1_IRQHandler 159 | .word DMA1_Channel2_IRQHandler 160 | .word DMA1_Channel3_IRQHandler 161 | .word DMA1_Channel4_IRQHandler 162 | .word DMA1_Channel5_IRQHandler 163 | .word DMA1_Channel6_IRQHandler 164 | .word DMA1_Channel7_IRQHandler 165 | .word ADC1_2_IRQHandler 166 | .word USB_HP_CAN1_TX_IRQHandler 167 | .word USB_LP_CAN1_RX0_IRQHandler 168 | .word CAN1_RX1_IRQHandler 169 | .word CAN1_SCE_IRQHandler 170 | .word EXTI9_5_IRQHandler 171 | .word TIM1_BRK_IRQHandler 172 | .word TIM1_UP_IRQHandler 173 | .word TIM1_TRG_COM_IRQHandler 174 | .word TIM1_CC_IRQHandler 175 | .word TIM2_IRQHandler 176 | .word TIM3_IRQHandler 177 | .word TIM4_IRQHandler 178 | .word I2C1_EV_IRQHandler 179 | .word I2C1_ER_IRQHandler 180 | .word I2C2_EV_IRQHandler 181 | .word I2C2_ER_IRQHandler 182 | .word SPI1_IRQHandler 183 | .word SPI2_IRQHandler 184 | .word USART1_IRQHandler 185 | .word USART2_IRQHandler 186 | .word USART3_IRQHandler 187 | .word EXTI15_10_IRQHandler 188 | .word RTCAlarm_IRQHandler 189 | .word USBWakeUp_IRQHandler 190 | .word 0 191 | .word 0 192 | .word 0 193 | .word 0 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word BootRAM /* @0x108. This is for boot in RAM mode for 198 | STM32F10x Medium Density devices. */ 199 | 200 | /******************************************************************************* 201 | * 202 | * Provide weak aliases for each Exception handler to the Default_Handler. 203 | * As they are weak aliases, any function with the same name will override 204 | * this definition. 205 | * 206 | *******************************************************************************/ 207 | 208 | .weak NMI_Handler 209 | .thumb_set NMI_Handler,Default_Handler 210 | 211 | .weak HardFault_Handler 212 | .thumb_set HardFault_Handler,Default_Handler 213 | 214 | .weak MemManage_Handler 215 | .thumb_set MemManage_Handler,Default_Handler 216 | 217 | .weak BusFault_Handler 218 | .thumb_set BusFault_Handler,Default_Handler 219 | 220 | .weak UsageFault_Handler 221 | .thumb_set UsageFault_Handler,Default_Handler 222 | 223 | .weak SVC_Handler 224 | .thumb_set SVC_Handler,Default_Handler 225 | 226 | .weak DebugMon_Handler 227 | .thumb_set DebugMon_Handler,Default_Handler 228 | 229 | .weak PendSV_Handler 230 | .thumb_set PendSV_Handler,Default_Handler 231 | 232 | .weak SysTick_Handler 233 | .thumb_set SysTick_Handler,Default_Handler 234 | 235 | .weak WWDG_IRQHandler 236 | .thumb_set WWDG_IRQHandler,Default_Handler 237 | 238 | .weak PVD_IRQHandler 239 | .thumb_set PVD_IRQHandler,Default_Handler 240 | 241 | .weak TAMPER_IRQHandler 242 | .thumb_set TAMPER_IRQHandler,Default_Handler 243 | 244 | .weak RTC_IRQHandler 245 | .thumb_set RTC_IRQHandler,Default_Handler 246 | 247 | .weak FLASH_IRQHandler 248 | .thumb_set FLASH_IRQHandler,Default_Handler 249 | 250 | .weak RCC_IRQHandler 251 | .thumb_set RCC_IRQHandler,Default_Handler 252 | 253 | .weak EXTI0_IRQHandler 254 | .thumb_set EXTI0_IRQHandler,Default_Handler 255 | 256 | .weak EXTI1_IRQHandler 257 | .thumb_set EXTI1_IRQHandler,Default_Handler 258 | 259 | .weak EXTI2_IRQHandler 260 | .thumb_set EXTI2_IRQHandler,Default_Handler 261 | 262 | .weak EXTI3_IRQHandler 263 | .thumb_set EXTI3_IRQHandler,Default_Handler 264 | 265 | .weak EXTI4_IRQHandler 266 | .thumb_set EXTI4_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel1_IRQHandler 269 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel2_IRQHandler 272 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel3_IRQHandler 275 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel4_IRQHandler 278 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel5_IRQHandler 281 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 282 | 283 | .weak DMA1_Channel6_IRQHandler 284 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 285 | 286 | .weak DMA1_Channel7_IRQHandler 287 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 288 | 289 | .weak ADC1_2_IRQHandler 290 | .thumb_set ADC1_2_IRQHandler,Default_Handler 291 | 292 | .weak USB_HP_CAN1_TX_IRQHandler 293 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 294 | 295 | .weak USB_LP_CAN1_RX0_IRQHandler 296 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 297 | 298 | .weak CAN1_RX1_IRQHandler 299 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 300 | 301 | .weak CAN1_SCE_IRQHandler 302 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 303 | 304 | .weak EXTI9_5_IRQHandler 305 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_BRK_IRQHandler 308 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_UP_IRQHandler 311 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 312 | 313 | .weak TIM1_TRG_COM_IRQHandler 314 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 315 | 316 | .weak TIM1_CC_IRQHandler 317 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 318 | 319 | .weak TIM2_IRQHandler 320 | .thumb_set TIM2_IRQHandler,Default_Handler 321 | 322 | .weak TIM3_IRQHandler 323 | .thumb_set TIM3_IRQHandler,Default_Handler 324 | 325 | .weak TIM4_IRQHandler 326 | .thumb_set TIM4_IRQHandler,Default_Handler 327 | 328 | .weak I2C1_EV_IRQHandler 329 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 330 | 331 | .weak I2C1_ER_IRQHandler 332 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 333 | 334 | .weak I2C2_EV_IRQHandler 335 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 336 | 337 | .weak I2C2_ER_IRQHandler 338 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 339 | 340 | .weak SPI1_IRQHandler 341 | .thumb_set SPI1_IRQHandler,Default_Handler 342 | 343 | .weak SPI2_IRQHandler 344 | .thumb_set SPI2_IRQHandler,Default_Handler 345 | 346 | .weak USART1_IRQHandler 347 | .thumb_set USART1_IRQHandler,Default_Handler 348 | 349 | .weak USART2_IRQHandler 350 | .thumb_set USART2_IRQHandler,Default_Handler 351 | 352 | .weak USART3_IRQHandler 353 | .thumb_set USART3_IRQHandler,Default_Handler 354 | 355 | .weak EXTI15_10_IRQHandler 356 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 357 | 358 | .weak RTCAlarm_IRQHandler 359 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 360 | 361 | .weak USBWakeUp_IRQHandler 362 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 363 | 364 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 365 | -------------------------------------------------------------------------------- /demo/fwlib/CMSIS/Include/arm_common_tables.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 11. November 2010 5 | * $Revision: V1.0.2 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_common_tables.h 9 | * 10 | * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 11 | * 12 | * Target Processor: Cortex-M4/Cortex-M3 13 | * 14 | * Version 1.0.2 2010/11/11 15 | * Documentation updated. 16 | * 17 | * Version 1.0.1 2010/10/05 18 | * Production release and review comments incorporated. 19 | * 20 | * Version 1.0.0 2010/09/20 21 | * Production release and review comments incorporated. 22 | * -------------------------------------------------------------------- */ 23 | 24 | #ifndef _ARM_COMMON_TABLES_H 25 | #define _ARM_COMMON_TABLES_H 26 | 27 | #include "arm_math.h" 28 | 29 | extern const uint16_t armBitRevTable[1024]; 30 | extern const q15_t armRecipTableQ15[64]; 31 | extern const q31_t armRecipTableQ31[64]; 32 | extern const q31_t realCoefAQ31[1024]; 33 | extern const q31_t realCoefBQ31[1024]; 34 | extern const float32_t twiddleCoef[6144]; 35 | extern const q31_t twiddleCoefQ31[6144]; 36 | extern const q15_t twiddleCoefQ15[6144]; 37 | 38 | #endif /* ARM_COMMON_TABLES_H */ 39 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __MISC_H 31 | #define __MISC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup MISC 45 | * @{ 46 | */ 47 | 48 | /** @defgroup MISC_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @brief NVIC Init Structure definition 54 | */ 55 | 56 | typedef struct 57 | { 58 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 59 | This parameter can be a value of @ref IRQn_Type 60 | (For the complete STM32 Devices IRQ Channels list, please 61 | refer to stm32f10x.h file) */ 62 | 63 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 64 | specified in NVIC_IRQChannel. This parameter can be a value 65 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 66 | 67 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 68 | in NVIC_IRQChannel. This parameter can be a value 69 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 70 | 71 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 72 | will be enabled or disabled. 73 | This parameter can be set either to ENABLE or DISABLE */ 74 | } NVIC_InitTypeDef; 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | /** @defgroup NVIC_Priority_Table 81 | * @{ 82 | */ 83 | 84 | /** 85 | @code 86 | The table below gives the allowed values of the pre-emption priority and subpriority according 87 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function 88 | ============================================================================================================================ 89 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 90 | ============================================================================================================================ 91 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority 92 | | | | 4 bits for subpriority 93 | ---------------------------------------------------------------------------------------------------------------------------- 94 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority 95 | | | | 3 bits for subpriority 96 | ---------------------------------------------------------------------------------------------------------------------------- 97 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 98 | | | | 2 bits for subpriority 99 | ---------------------------------------------------------------------------------------------------------------------------- 100 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 101 | | | | 1 bits for subpriority 102 | ---------------------------------------------------------------------------------------------------------------------------- 103 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority 104 | | | | 0 bits for subpriority 105 | ============================================================================================================================ 106 | @endcode 107 | */ 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup MISC_Exported_Constants 114 | * @{ 115 | */ 116 | 117 | /** @defgroup Vector_Table_Base 118 | * @{ 119 | */ 120 | 121 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 122 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 123 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 124 | ((VECTTAB) == NVIC_VectTab_FLASH)) 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @defgroup System_Low_Power 130 | * @{ 131 | */ 132 | 133 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 134 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 135 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 136 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 137 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 138 | ((LP) == NVIC_LP_SLEEPONEXIT)) 139 | /** 140 | * @} 141 | */ 142 | 143 | /** @defgroup Preemption_Priority_Group 144 | * @{ 145 | */ 146 | 147 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 148 | 4 bits for subpriority */ 149 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 150 | 3 bits for subpriority */ 151 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 152 | 2 bits for subpriority */ 153 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 154 | 1 bits for subpriority */ 155 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 156 | 0 bits for subpriority */ 157 | 158 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 159 | ((GROUP) == NVIC_PriorityGroup_1) || \ 160 | ((GROUP) == NVIC_PriorityGroup_2) || \ 161 | ((GROUP) == NVIC_PriorityGroup_3) || \ 162 | ((GROUP) == NVIC_PriorityGroup_4)) 163 | 164 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 165 | 166 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 167 | 168 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @defgroup SysTick_clock_source 175 | * @{ 176 | */ 177 | 178 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 179 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 180 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 181 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /** @defgroup MISC_Exported_Macros 191 | * @{ 192 | */ 193 | 194 | /** 195 | * @} 196 | */ 197 | 198 | /** @defgroup MISC_Exported_Functions 199 | * @{ 200 | */ 201 | 202 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 203 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 204 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 205 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 206 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 207 | 208 | #ifdef __cplusplus 209 | } 210 | #endif 211 | 212 | #endif /* __MISC_H */ 213 | 214 | /** 215 | * @} 216 | */ 217 | 218 | /** 219 | * @} 220 | */ 221 | 222 | /** 223 | * @} 224 | */ 225 | 226 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 227 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the BKP firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_BKP_H 31 | #define __STM32F10x_BKP_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup BKP 45 | * @{ 46 | */ 47 | 48 | /** @defgroup BKP_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup BKP_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | /** @defgroup Tamper_Pin_active_level 61 | * @{ 62 | */ 63 | 64 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 65 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 66 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ 67 | ((LEVEL) == BKP_TamperPinLevel_Low)) 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 73 | * @{ 74 | */ 75 | 76 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 77 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 78 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 79 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 80 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ 81 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ 82 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ 83 | ((SOURCE) == BKP_RTCOutputSource_Second)) 84 | /** 85 | * @} 86 | */ 87 | 88 | /** @defgroup Data_Backup_Register 89 | * @{ 90 | */ 91 | 92 | #define BKP_DR1 ((uint16_t)0x0004) 93 | #define BKP_DR2 ((uint16_t)0x0008) 94 | #define BKP_DR3 ((uint16_t)0x000C) 95 | #define BKP_DR4 ((uint16_t)0x0010) 96 | #define BKP_DR5 ((uint16_t)0x0014) 97 | #define BKP_DR6 ((uint16_t)0x0018) 98 | #define BKP_DR7 ((uint16_t)0x001C) 99 | #define BKP_DR8 ((uint16_t)0x0020) 100 | #define BKP_DR9 ((uint16_t)0x0024) 101 | #define BKP_DR10 ((uint16_t)0x0028) 102 | #define BKP_DR11 ((uint16_t)0x0040) 103 | #define BKP_DR12 ((uint16_t)0x0044) 104 | #define BKP_DR13 ((uint16_t)0x0048) 105 | #define BKP_DR14 ((uint16_t)0x004C) 106 | #define BKP_DR15 ((uint16_t)0x0050) 107 | #define BKP_DR16 ((uint16_t)0x0054) 108 | #define BKP_DR17 ((uint16_t)0x0058) 109 | #define BKP_DR18 ((uint16_t)0x005C) 110 | #define BKP_DR19 ((uint16_t)0x0060) 111 | #define BKP_DR20 ((uint16_t)0x0064) 112 | #define BKP_DR21 ((uint16_t)0x0068) 113 | #define BKP_DR22 ((uint16_t)0x006C) 114 | #define BKP_DR23 ((uint16_t)0x0070) 115 | #define BKP_DR24 ((uint16_t)0x0074) 116 | #define BKP_DR25 ((uint16_t)0x0078) 117 | #define BKP_DR26 ((uint16_t)0x007C) 118 | #define BKP_DR27 ((uint16_t)0x0080) 119 | #define BKP_DR28 ((uint16_t)0x0084) 120 | #define BKP_DR29 ((uint16_t)0x0088) 121 | #define BKP_DR30 ((uint16_t)0x008C) 122 | #define BKP_DR31 ((uint16_t)0x0090) 123 | #define BKP_DR32 ((uint16_t)0x0094) 124 | #define BKP_DR33 ((uint16_t)0x0098) 125 | #define BKP_DR34 ((uint16_t)0x009C) 126 | #define BKP_DR35 ((uint16_t)0x00A0) 127 | #define BKP_DR36 ((uint16_t)0x00A4) 128 | #define BKP_DR37 ((uint16_t)0x00A8) 129 | #define BKP_DR38 ((uint16_t)0x00AC) 130 | #define BKP_DR39 ((uint16_t)0x00B0) 131 | #define BKP_DR40 ((uint16_t)0x00B4) 132 | #define BKP_DR41 ((uint16_t)0x00B8) 133 | #define BKP_DR42 ((uint16_t)0x00BC) 134 | 135 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ 136 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ 137 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ 138 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ 139 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ 140 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ 141 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ 142 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ 143 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ 144 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ 145 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ 146 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ 147 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ 148 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) 149 | 150 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 151 | /** 152 | * @} 153 | */ 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | /** @defgroup BKP_Exported_Macros 160 | * @{ 161 | */ 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /** @defgroup BKP_Exported_Functions 168 | * @{ 169 | */ 170 | 171 | void BKP_DeInit(void); 172 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 173 | void BKP_TamperPinCmd(FunctionalState NewState); 174 | void BKP_ITConfig(FunctionalState NewState); 175 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 176 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 177 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 178 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 179 | FlagStatus BKP_GetFlagStatus(void); 180 | void BKP_ClearFlag(void); 181 | ITStatus BKP_GetITStatus(void); 182 | void BKP_ClearITPendingBit(void); 183 | 184 | #ifdef __cplusplus 185 | } 186 | #endif 187 | 188 | #endif /* __STM32F10x_BKP_H */ 189 | /** 190 | * @} 191 | */ 192 | 193 | /** 194 | * @} 195 | */ 196 | 197 | /** 198 | * @} 199 | */ 200 | 201 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 202 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_CEC_H 31 | #define __STM32F10x_CEC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CEC 45 | * @{ 46 | */ 47 | 48 | 49 | /** @defgroup CEC_Exported_Types 50 | * @{ 51 | */ 52 | 53 | /** 54 | * @brief CEC Init structure definition 55 | */ 56 | typedef struct 57 | { 58 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 59 | This parameter can be a value of @ref CEC_BitTiming_Mode */ 60 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 61 | This parameter can be a value of @ref CEC_BitPeriod_Mode */ 62 | }CEC_InitTypeDef; 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup CEC_Exported_Constants 69 | * @{ 70 | */ 71 | 72 | /** @defgroup CEC_BitTiming_Mode 73 | * @{ 74 | */ 75 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ 76 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ 77 | 78 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ 79 | ((MODE) == CEC_BitTimingErrFreeMode)) 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @defgroup CEC_BitPeriod_Mode 85 | * @{ 86 | */ 87 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ 88 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ 89 | 90 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ 91 | ((MODE) == CEC_BitPeriodFlexibleMode)) 92 | /** 93 | * @} 94 | */ 95 | 96 | 97 | /** @defgroup CEC_interrupts_definition 98 | * @{ 99 | */ 100 | #define CEC_IT_TERR CEC_CSR_TERR 101 | #define CEC_IT_TBTRF CEC_CSR_TBTRF 102 | #define CEC_IT_RERR CEC_CSR_RERR 103 | #define CEC_IT_RBTF CEC_CSR_RBTF 104 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ 105 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) 106 | /** 107 | * @} 108 | */ 109 | 110 | 111 | /** @defgroup CEC_Own_Address 112 | * @{ 113 | */ 114 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @defgroup CEC_Prescaler 120 | * @{ 121 | */ 122 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) 123 | 124 | /** 125 | * @} 126 | */ 127 | 128 | /** @defgroup CEC_flags_definition 129 | * @{ 130 | */ 131 | 132 | /** 133 | * @brief ESR register flags 134 | */ 135 | #define CEC_FLAG_BTE ((uint32_t)0x10010000) 136 | #define CEC_FLAG_BPE ((uint32_t)0x10020000) 137 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) 138 | #define CEC_FLAG_SBE ((uint32_t)0x10080000) 139 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000) 140 | #define CEC_FLAG_LINE ((uint32_t)0x10200000) 141 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) 142 | 143 | /** 144 | * @brief CSR register flags 145 | */ 146 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002) 147 | #define CEC_FLAG_TERR ((uint32_t)0x00000004) 148 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) 149 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010) 150 | #define CEC_FLAG_REOM ((uint32_t)0x00000020) 151 | #define CEC_FLAG_RERR ((uint32_t)0x00000040) 152 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080) 153 | 154 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) 155 | 156 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ 157 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ 158 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ 159 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ 160 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ 161 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ 162 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /** 169 | * @} 170 | */ 171 | 172 | /** @defgroup CEC_Exported_Macros 173 | * @{ 174 | */ 175 | 176 | /** 177 | * @} 178 | */ 179 | 180 | /** @defgroup CEC_Exported_Functions 181 | * @{ 182 | */ 183 | void CEC_DeInit(void); 184 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 185 | void CEC_Cmd(FunctionalState NewState); 186 | void CEC_ITConfig(FunctionalState NewState); 187 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 188 | void CEC_SetPrescaler(uint16_t CEC_Prescaler); 189 | void CEC_SendDataByte(uint8_t Data); 190 | uint8_t CEC_ReceiveDataByte(void); 191 | void CEC_StartOfMessage(void); 192 | void CEC_EndOfMessageCmd(FunctionalState NewState); 193 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); 194 | void CEC_ClearFlag(uint32_t CEC_FLAG); 195 | ITStatus CEC_GetITStatus(uint8_t CEC_IT); 196 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 197 | 198 | #ifdef __cplusplus 199 | } 200 | #endif 201 | 202 | #endif /* __STM32F10x_CEC_H */ 203 | 204 | /** 205 | * @} 206 | */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 217 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_CRC_H 31 | #define __STM32F10x_CRC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CRC 45 | * @{ 46 | */ 47 | 48 | /** @defgroup CRC_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup CRC_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @} 62 | */ 63 | 64 | /** @defgroup CRC_Exported_Macros 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @defgroup CRC_Exported_Functions 73 | * @{ 74 | */ 75 | 76 | void CRC_ResetDR(void); 77 | uint32_t CRC_CalcCRC(uint32_t Data); 78 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 79 | uint32_t CRC_GetCRC(void); 80 | void CRC_SetIDRegister(uint8_t IDValue); 81 | uint8_t CRC_GetIDRegister(void); 82 | 83 | #ifdef __cplusplus 84 | } 85 | #endif 86 | 87 | #endif /* __STM32F10x_CRC_H */ 88 | /** 89 | * @} 90 | */ 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** 97 | * @} 98 | */ 99 | 100 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 101 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the DBGMCU 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_DBGMCU_H 31 | #define __STM32F10x_DBGMCU_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup DBGMCU 45 | * @{ 46 | */ 47 | 48 | /** @defgroup DBGMCU_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup DBGMCU_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 61 | #define DBGMCU_STOP ((uint32_t)0x00000002) 62 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 63 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 64 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 65 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) 66 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) 67 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) 68 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) 69 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) 70 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 71 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 72 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) 73 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) 74 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) 75 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) 76 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 77 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) 78 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) 79 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) 80 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) 81 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) 82 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) 83 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) 84 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) 85 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) 86 | 87 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) 88 | /** 89 | * @} 90 | */ 91 | 92 | /** @defgroup DBGMCU_Exported_Macros 93 | * @{ 94 | */ 95 | 96 | /** 97 | * @} 98 | */ 99 | 100 | /** @defgroup DBGMCU_Exported_Functions 101 | * @{ 102 | */ 103 | 104 | uint32_t DBGMCU_GetREVID(void); 105 | uint32_t DBGMCU_GetDEVID(void); 106 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 107 | 108 | #ifdef __cplusplus 109 | } 110 | #endif 111 | 112 | #endif /* __STM32F10x_DBGMCU_H */ 113 | /** 114 | * @} 115 | */ 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 126 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the EXTI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_EXTI_H 31 | #define __STM32F10x_EXTI_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup EXTI 45 | * @{ 46 | */ 47 | 48 | /** @defgroup EXTI_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @brief EXTI mode enumeration 54 | */ 55 | 56 | typedef enum 57 | { 58 | EXTI_Mode_Interrupt = 0x00, 59 | EXTI_Mode_Event = 0x04 60 | }EXTIMode_TypeDef; 61 | 62 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 63 | 64 | /** 65 | * @brief EXTI Trigger enumeration 66 | */ 67 | 68 | typedef enum 69 | { 70 | EXTI_Trigger_Rising = 0x08, 71 | EXTI_Trigger_Falling = 0x0C, 72 | EXTI_Trigger_Rising_Falling = 0x10 73 | }EXTITrigger_TypeDef; 74 | 75 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 76 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 77 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 78 | /** 79 | * @brief EXTI Init Structure definition 80 | */ 81 | 82 | typedef struct 83 | { 84 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 85 | This parameter can be any combination of @ref EXTI_Lines */ 86 | 87 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 88 | This parameter can be a value of @ref EXTIMode_TypeDef */ 89 | 90 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 91 | This parameter can be a value of @ref EXTITrigger_TypeDef */ 92 | 93 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 94 | This parameter can be set either to ENABLE or DISABLE */ 95 | }EXTI_InitTypeDef; 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** @defgroup EXTI_Exported_Constants 102 | * @{ 103 | */ 104 | 105 | /** @defgroup EXTI_Lines 106 | * @{ 107 | */ 108 | 109 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ 110 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ 111 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ 112 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ 113 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ 114 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ 115 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ 116 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ 117 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ 118 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ 119 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ 120 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ 121 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ 122 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ 123 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ 124 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ 125 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ 126 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 127 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS 128 | Wakeup from suspend event */ 129 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 130 | 131 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) 132 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 133 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 134 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 135 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 136 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 137 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 138 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 139 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 140 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 141 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) 142 | 143 | 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** @defgroup EXTI_Exported_Macros 153 | * @{ 154 | */ 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /** @defgroup EXTI_Exported_Functions 161 | * @{ 162 | */ 163 | 164 | void EXTI_DeInit(void); 165 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 166 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 167 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 168 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 169 | void EXTI_ClearFlag(uint32_t EXTI_Line); 170 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 171 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 172 | 173 | #ifdef __cplusplus 174 | } 175 | #endif 176 | 177 | #endif /* __STM32F10x_EXTI_H */ 178 | /** 179 | * @} 180 | */ 181 | 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 191 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_IWDG_H 31 | #define __STM32F10x_IWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup IWDG 45 | * @{ 46 | */ 47 | 48 | /** @defgroup IWDG_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup IWDG_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | /** @defgroup IWDG_WriteAccess 61 | * @{ 62 | */ 63 | 64 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 65 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 66 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 67 | ((ACCESS) == IWDG_WriteAccess_Disable)) 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @defgroup IWDG_prescaler 73 | * @{ 74 | */ 75 | 76 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 77 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 78 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 79 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 80 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 81 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 82 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 83 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 84 | ((PRESCALER) == IWDG_Prescaler_8) || \ 85 | ((PRESCALER) == IWDG_Prescaler_16) || \ 86 | ((PRESCALER) == IWDG_Prescaler_32) || \ 87 | ((PRESCALER) == IWDG_Prescaler_64) || \ 88 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 89 | ((PRESCALER) == IWDG_Prescaler_256)) 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup IWDG_Flag 95 | * @{ 96 | */ 97 | 98 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 99 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 100 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 101 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | /** @defgroup IWDG_Exported_Macros 111 | * @{ 112 | */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /** @defgroup IWDG_Exported_Functions 119 | * @{ 120 | */ 121 | 122 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 123 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 124 | void IWDG_SetReload(uint16_t Reload); 125 | void IWDG_ReloadCounter(void); 126 | void IWDG_Enable(void); 127 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 128 | 129 | #ifdef __cplusplus 130 | } 131 | #endif 132 | 133 | #endif /* __STM32F10x_IWDG_H */ 134 | /** 135 | * @} 136 | */ 137 | 138 | /** 139 | * @} 140 | */ 141 | 142 | /** 143 | * @} 144 | */ 145 | 146 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 147 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_PWR_H 31 | #define __STM32F10x_PWR_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup PWR 45 | * @{ 46 | */ 47 | 48 | /** @defgroup PWR_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup PWR_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | /** @defgroup PVD_detection_level 61 | * @{ 62 | */ 63 | 64 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 65 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 66 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 67 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 68 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 69 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 70 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 71 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 72 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ 73 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ 74 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ 75 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) 76 | /** 77 | * @} 78 | */ 79 | 80 | /** @defgroup Regulator_state_is_STOP_mode 81 | * @{ 82 | */ 83 | 84 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 85 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 86 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 87 | ((REGULATOR) == PWR_Regulator_LowPower)) 88 | /** 89 | * @} 90 | */ 91 | 92 | /** @defgroup STOP_mode_entry 93 | * @{ 94 | */ 95 | 96 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 97 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 98 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** @defgroup PWR_Flag 105 | * @{ 106 | */ 107 | 108 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 109 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 110 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 111 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 112 | ((FLAG) == PWR_FLAG_PVDO)) 113 | 114 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 115 | /** 116 | * @} 117 | */ 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup PWR_Exported_Macros 124 | * @{ 125 | */ 126 | 127 | /** 128 | * @} 129 | */ 130 | 131 | /** @defgroup PWR_Exported_Functions 132 | * @{ 133 | */ 134 | 135 | void PWR_DeInit(void); 136 | void PWR_BackupAccessCmd(FunctionalState NewState); 137 | void PWR_PVDCmd(FunctionalState NewState); 138 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 139 | void PWR_WakeUpPinCmd(FunctionalState NewState); 140 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 141 | void PWR_EnterSTANDBYMode(void); 142 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 143 | void PWR_ClearFlag(uint32_t PWR_FLAG); 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif 148 | 149 | #endif /* __STM32F10x_PWR_H */ 150 | /** 151 | * @} 152 | */ 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 163 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the RTC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_RTC_H 31 | #define __STM32F10x_RTC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup RTC 45 | * @{ 46 | */ 47 | 48 | /** @defgroup RTC_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup RTC_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | /** @defgroup RTC_interrupts_define 61 | * @{ 62 | */ 63 | 64 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ 65 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ 66 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ 67 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) 68 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ 69 | ((IT) == RTC_IT_SEC)) 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup RTC_interrupts_flags 75 | * @{ 76 | */ 77 | 78 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ 79 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ 80 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ 81 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ 82 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ 83 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) 84 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ 85 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ 86 | ((FLAG) == RTC_FLAG_SEC)) 87 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** 94 | * @} 95 | */ 96 | 97 | /** @defgroup RTC_Exported_Macros 98 | * @{ 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | 105 | /** @defgroup RTC_Exported_Functions 106 | * @{ 107 | */ 108 | 109 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 110 | void RTC_EnterConfigMode(void); 111 | void RTC_ExitConfigMode(void); 112 | uint32_t RTC_GetCounter(void); 113 | void RTC_SetCounter(uint32_t CounterValue); 114 | void RTC_SetPrescaler(uint32_t PrescalerValue); 115 | void RTC_SetAlarm(uint32_t AlarmValue); 116 | uint32_t RTC_GetDivider(void); 117 | void RTC_WaitForLastTask(void); 118 | void RTC_WaitForSynchro(void); 119 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 120 | void RTC_ClearFlag(uint16_t RTC_FLAG); 121 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 122 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 123 | 124 | #ifdef __cplusplus 125 | } 126 | #endif 127 | 128 | #endif /* __STM32F10x_RTC_H */ 129 | /** 130 | * @} 131 | */ 132 | 133 | /** 134 | * @} 135 | */ 136 | 137 | /** 138 | * @} 139 | */ 140 | 141 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 142 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.h 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file contains all the functions prototypes for the WWDG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F10x_WWDG_H 31 | #define __STM32F10x_WWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f10x.h" 39 | 40 | /** @addtogroup STM32F10x_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup WWDG 45 | * @{ 46 | */ 47 | 48 | /** @defgroup WWDG_Exported_Types 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup WWDG_Exported_Constants 57 | * @{ 58 | */ 59 | 60 | /** @defgroup WWDG_Prescaler 61 | * @{ 62 | */ 63 | 64 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 65 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 66 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 67 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 68 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 69 | ((PRESCALER) == WWDG_Prescaler_2) || \ 70 | ((PRESCALER) == WWDG_Prescaler_4) || \ 71 | ((PRESCALER) == WWDG_Prescaler_8)) 72 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 73 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @defgroup WWDG_Exported_Macros 84 | * @{ 85 | */ 86 | /** 87 | * @} 88 | */ 89 | 90 | /** @defgroup WWDG_Exported_Functions 91 | * @{ 92 | */ 93 | 94 | void WWDG_DeInit(void); 95 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 96 | void WWDG_SetWindowValue(uint8_t WindowValue); 97 | void WWDG_EnableIT(void); 98 | void WWDG_SetCounter(uint8_t Counter); 99 | void WWDG_Enable(uint8_t Counter); 100 | FlagStatus WWDG_GetFlagStatus(void); 101 | void WWDG_ClearFlag(void); 102 | 103 | #ifdef __cplusplus 104 | } 105 | #endif 106 | 107 | #endif /* __STM32F10x_WWDG_H */ 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 122 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "misc.h" 31 | 32 | /** @addtogroup STM32F10x_StdPeriph_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup MISC 37 | * @brief MISC driver modules 38 | * @{ 39 | */ 40 | 41 | /** @defgroup MISC_Private_TypesDefinitions 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup MISC_Private_Defines 50 | * @{ 51 | */ 52 | 53 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup MISC_Private_Macros 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup MISC_Private_Variables 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup MISC_Private_FunctionPrototypes 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @defgroup MISC_Private_Functions 83 | * @{ 84 | */ 85 | 86 | /** 87 | * @brief Configures the priority grouping: pre-emption priority and subpriority. 88 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 89 | * This parameter can be one of the following values: 90 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority 91 | * 4 bits for subpriority 92 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority 93 | * 3 bits for subpriority 94 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority 95 | * 2 bits for subpriority 96 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority 97 | * 1 bits for subpriority 98 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority 99 | * 0 bits for subpriority 100 | * @retval None 101 | */ 102 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 103 | { 104 | /* Check the parameters */ 105 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 106 | 107 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 108 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 109 | } 110 | 111 | /** 112 | * @brief Initializes the NVIC peripheral according to the specified 113 | * parameters in the NVIC_InitStruct. 114 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 115 | * the configuration information for the specified NVIC peripheral. 116 | * @retval None 117 | */ 118 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 119 | { 120 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 121 | 122 | /* Check the parameters */ 123 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 124 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 125 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 126 | 127 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 128 | { 129 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 130 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 131 | tmppre = (0x4 - tmppriority); 132 | tmpsub = tmpsub >> tmppriority; 133 | 134 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 135 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 136 | tmppriority = tmppriority << 0x04; 137 | 138 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 139 | 140 | /* Enable the Selected IRQ Channels --------------------------------------*/ 141 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 143 | } 144 | else 145 | { 146 | /* Disable the Selected IRQ Channels -------------------------------------*/ 147 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 148 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 149 | } 150 | } 151 | 152 | /** 153 | * @brief Sets the vector table location and Offset. 154 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 155 | * This parameter can be one of the following values: 156 | * @arg NVIC_VectTab_RAM 157 | * @arg NVIC_VectTab_FLASH 158 | * @param Offset: Vector Table base offset field. This value must be a multiple 159 | * of 0x200. 160 | * @retval None 161 | */ 162 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 163 | { 164 | /* Check the parameters */ 165 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 166 | assert_param(IS_NVIC_OFFSET(Offset)); 167 | 168 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 169 | } 170 | 171 | /** 172 | * @brief Selects the condition for the system to enter low power mode. 173 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 174 | * This parameter can be one of the following values: 175 | * @arg NVIC_LP_SEVONPEND 176 | * @arg NVIC_LP_SLEEPDEEP 177 | * @arg NVIC_LP_SLEEPONEXIT 178 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 179 | * @retval None 180 | */ 181 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 182 | { 183 | /* Check the parameters */ 184 | assert_param(IS_NVIC_LP(LowPowerMode)); 185 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 186 | 187 | if (NewState != DISABLE) 188 | { 189 | SCB->SCR |= LowPowerMode; 190 | } 191 | else 192 | { 193 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 194 | } 195 | } 196 | 197 | /** 198 | * @brief Configures the SysTick clock source. 199 | * @param SysTick_CLKSource: specifies the SysTick clock source. 200 | * This parameter can be one of the following values: 201 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 202 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 203 | * @retval None 204 | */ 205 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 206 | { 207 | /* Check the parameters */ 208 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 209 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 210 | { 211 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 212 | } 213 | else 214 | { 215 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 216 | } 217 | } 218 | 219 | /** 220 | * @} 221 | */ 222 | 223 | /** 224 | * @} 225 | */ 226 | 227 | /** 228 | * @} 229 | */ 230 | 231 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 232 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the BKP firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_bkp.h" 30 | #include "stm32f10x_rcc.h" 31 | 32 | /** @addtogroup STM32F10x_StdPeriph_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup BKP 37 | * @brief BKP driver modules 38 | * @{ 39 | */ 40 | 41 | /** @defgroup BKP_Private_TypesDefinitions 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup BKP_Private_Defines 50 | * @{ 51 | */ 52 | 53 | /* ------------ BKP registers bit address in the alias region --------------- */ 54 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE) 55 | 56 | /* --- CR Register ----*/ 57 | 58 | /* Alias word address of TPAL bit */ 59 | #define CR_OFFSET (BKP_OFFSET + 0x30) 60 | #define TPAL_BitNumber 0x01 61 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 62 | 63 | /* Alias word address of TPE bit */ 64 | #define TPE_BitNumber 0x00 65 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) 66 | 67 | /* --- CSR Register ---*/ 68 | 69 | /* Alias word address of TPIE bit */ 70 | #define CSR_OFFSET (BKP_OFFSET + 0x34) 71 | #define TPIE_BitNumber 0x02 72 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) 73 | 74 | /* Alias word address of TIF bit */ 75 | #define TIF_BitNumber 0x09 76 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) 77 | 78 | /* Alias word address of TEF bit */ 79 | #define TEF_BitNumber 0x08 80 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) 81 | 82 | /* ---------------------- BKP registers bit mask ------------------------ */ 83 | 84 | /* RTCCR register bit mask */ 85 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80) 86 | #define RTCCR_MASK ((uint16_t)0xFC7F) 87 | 88 | /** 89 | * @} 90 | */ 91 | 92 | 93 | /** @defgroup BKP_Private_Macros 94 | * @{ 95 | */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** @defgroup BKP_Private_Variables 102 | * @{ 103 | */ 104 | 105 | /** 106 | * @} 107 | */ 108 | 109 | /** @defgroup BKP_Private_FunctionPrototypes 110 | * @{ 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** @defgroup BKP_Private_Functions 118 | * @{ 119 | */ 120 | 121 | /** 122 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 123 | * @param None 124 | * @retval None 125 | */ 126 | void BKP_DeInit(void) 127 | { 128 | RCC_BackupResetCmd(ENABLE); 129 | RCC_BackupResetCmd(DISABLE); 130 | } 131 | 132 | /** 133 | * @brief Configures the Tamper Pin active level. 134 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 135 | * This parameter can be one of the following values: 136 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level 137 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level 138 | * @retval None 139 | */ 140 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 141 | { 142 | /* Check the parameters */ 143 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); 144 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; 145 | } 146 | 147 | /** 148 | * @brief Enables or disables the Tamper Pin activation. 149 | * @param NewState: new state of the Tamper Pin activation. 150 | * This parameter can be: ENABLE or DISABLE. 151 | * @retval None 152 | */ 153 | void BKP_TamperPinCmd(FunctionalState NewState) 154 | { 155 | /* Check the parameters */ 156 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 157 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; 158 | } 159 | 160 | /** 161 | * @brief Enables or disables the Tamper Pin Interrupt. 162 | * @param NewState: new state of the Tamper Pin Interrupt. 163 | * This parameter can be: ENABLE or DISABLE. 164 | * @retval None 165 | */ 166 | void BKP_ITConfig(FunctionalState NewState) 167 | { 168 | /* Check the parameters */ 169 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 170 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; 171 | } 172 | 173 | /** 174 | * @brief Select the RTC output source to output on the Tamper pin. 175 | * @param BKP_RTCOutputSource: specifies the RTC output source. 176 | * This parameter can be one of the following values: 177 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. 178 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency 179 | * divided by 64 on the Tamper pin. 180 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on 181 | * the Tamper pin. 182 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on 183 | * the Tamper pin. 184 | * @retval None 185 | */ 186 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 187 | { 188 | uint16_t tmpreg = 0; 189 | /* Check the parameters */ 190 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); 191 | tmpreg = BKP->RTCCR; 192 | /* Clear CCO, ASOE and ASOS bits */ 193 | tmpreg &= RTCCR_MASK; 194 | 195 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ 196 | tmpreg |= BKP_RTCOutputSource; 197 | /* Store the new value */ 198 | BKP->RTCCR = tmpreg; 199 | } 200 | 201 | /** 202 | * @brief Sets RTC Clock Calibration value. 203 | * @param CalibrationValue: specifies the RTC Clock Calibration value. 204 | * This parameter must be a number between 0 and 0x7F. 205 | * @retval None 206 | */ 207 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 208 | { 209 | uint16_t tmpreg = 0; 210 | /* Check the parameters */ 211 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); 212 | tmpreg = BKP->RTCCR; 213 | /* Clear CAL[6:0] bits */ 214 | tmpreg &= RTCCR_CAL_MASK; 215 | /* Set CAL[6:0] bits according to CalibrationValue value */ 216 | tmpreg |= CalibrationValue; 217 | /* Store the new value */ 218 | BKP->RTCCR = tmpreg; 219 | } 220 | 221 | /** 222 | * @brief Writes user data to the specified Data Backup Register. 223 | * @param BKP_DR: specifies the Data Backup Register. 224 | * This parameter can be BKP_DRx where x:[1, 42] 225 | * @param Data: data to write 226 | * @retval None 227 | */ 228 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 229 | { 230 | __IO uint32_t tmp = 0; 231 | 232 | /* Check the parameters */ 233 | assert_param(IS_BKP_DR(BKP_DR)); 234 | 235 | tmp = (uint32_t)BKP_BASE; 236 | tmp += BKP_DR; 237 | 238 | *(__IO uint32_t *) tmp = Data; 239 | } 240 | 241 | /** 242 | * @brief Reads data from the specified Data Backup Register. 243 | * @param BKP_DR: specifies the Data Backup Register. 244 | * This parameter can be BKP_DRx where x:[1, 42] 245 | * @retval The content of the specified Data Backup Register 246 | */ 247 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 248 | { 249 | __IO uint32_t tmp = 0; 250 | 251 | /* Check the parameters */ 252 | assert_param(IS_BKP_DR(BKP_DR)); 253 | 254 | tmp = (uint32_t)BKP_BASE; 255 | tmp += BKP_DR; 256 | 257 | return (*(__IO uint16_t *) tmp); 258 | } 259 | 260 | /** 261 | * @brief Checks whether the Tamper Pin Event flag is set or not. 262 | * @param None 263 | * @retval The new state of the Tamper Pin Event flag (SET or RESET). 264 | */ 265 | FlagStatus BKP_GetFlagStatus(void) 266 | { 267 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); 268 | } 269 | 270 | /** 271 | * @brief Clears Tamper Pin Event pending flag. 272 | * @param None 273 | * @retval None 274 | */ 275 | void BKP_ClearFlag(void) 276 | { 277 | /* Set CTE bit to clear Tamper Pin Event flag */ 278 | BKP->CSR |= BKP_CSR_CTE; 279 | } 280 | 281 | /** 282 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 283 | * @param None 284 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET). 285 | */ 286 | ITStatus BKP_GetITStatus(void) 287 | { 288 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); 289 | } 290 | 291 | /** 292 | * @brief Clears Tamper Pin Interrupt pending bit. 293 | * @param None 294 | * @retval None 295 | */ 296 | void BKP_ClearITPendingBit(void) 297 | { 298 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ 299 | BKP->CSR |= BKP_CSR_CTI; 300 | } 301 | 302 | /** 303 | * @} 304 | */ 305 | 306 | /** 307 | * @} 308 | */ 309 | 310 | /** 311 | * @} 312 | */ 313 | 314 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 315 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the CRC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_crc.h" 30 | 31 | /** @addtogroup STM32F10x_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup CRC 36 | * @brief CRC driver modules 37 | * @{ 38 | */ 39 | 40 | /** @defgroup CRC_Private_TypesDefinitions 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | /** @defgroup CRC_Private_Defines 49 | * @{ 50 | */ 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup CRC_Private_Macros 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @} 62 | */ 63 | 64 | /** @defgroup CRC_Private_Variables 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @defgroup CRC_Private_FunctionPrototypes 73 | * @{ 74 | */ 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | /** @defgroup CRC_Private_Functions 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @brief Resets the CRC Data register (DR). 86 | * @param None 87 | * @retval None 88 | */ 89 | void CRC_ResetDR(void) 90 | { 91 | /* Reset CRC generator */ 92 | CRC->CR = CRC_CR_RESET; 93 | } 94 | 95 | /** 96 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 97 | * @param Data: data word(32-bit) to compute its CRC 98 | * @retval 32-bit CRC 99 | */ 100 | uint32_t CRC_CalcCRC(uint32_t Data) 101 | { 102 | CRC->DR = Data; 103 | 104 | return (CRC->DR); 105 | } 106 | 107 | /** 108 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 109 | * @param pBuffer: pointer to the buffer containing the data to be computed 110 | * @param BufferLength: length of the buffer to be computed 111 | * @retval 32-bit CRC 112 | */ 113 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 114 | { 115 | uint32_t index = 0; 116 | 117 | for(index = 0; index < BufferLength; index++) 118 | { 119 | CRC->DR = pBuffer[index]; 120 | } 121 | return (CRC->DR); 122 | } 123 | 124 | /** 125 | * @brief Returns the current CRC value. 126 | * @param None 127 | * @retval 32-bit CRC 128 | */ 129 | uint32_t CRC_GetCRC(void) 130 | { 131 | return (CRC->DR); 132 | } 133 | 134 | /** 135 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 136 | * @param IDValue: 8-bit value to be stored in the ID register 137 | * @retval None 138 | */ 139 | void CRC_SetIDRegister(uint8_t IDValue) 140 | { 141 | CRC->IDR = IDValue; 142 | } 143 | 144 | /** 145 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 146 | * @param None 147 | * @retval 8-bit value of the ID register 148 | */ 149 | uint8_t CRC_GetIDRegister(void) 150 | { 151 | return (CRC->IDR); 152 | } 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /** 163 | * @} 164 | */ 165 | 166 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 167 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the DBGMCU firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_dbgmcu.h" 30 | 31 | /** @addtogroup STM32F10x_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup DBGMCU 36 | * @brief DBGMCU driver modules 37 | * @{ 38 | */ 39 | 40 | /** @defgroup DBGMCU_Private_TypesDefinitions 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | /** @defgroup DBGMCU_Private_Defines 49 | * @{ 50 | */ 51 | 52 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 53 | /** 54 | * @} 55 | */ 56 | 57 | /** @defgroup DBGMCU_Private_Macros 58 | * @{ 59 | */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup DBGMCU_Private_Variables 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup DBGMCU_Private_FunctionPrototypes 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @defgroup DBGMCU_Private_Functions 82 | * @{ 83 | */ 84 | 85 | /** 86 | * @brief Returns the device revision identifier. 87 | * @param None 88 | * @retval Device revision identifier 89 | */ 90 | uint32_t DBGMCU_GetREVID(void) 91 | { 92 | return(DBGMCU->IDCODE >> 16); 93 | } 94 | 95 | /** 96 | * @brief Returns the device identifier. 97 | * @param None 98 | * @retval Device identifier 99 | */ 100 | uint32_t DBGMCU_GetDEVID(void) 101 | { 102 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 103 | } 104 | 105 | /** 106 | * @brief Configures the specified peripheral and low power mode behavior 107 | * when the MCU under Debug mode. 108 | * @param DBGMCU_Periph: specifies the peripheral and low power mode. 109 | * This parameter can be any combination of the following values: 110 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode 111 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 112 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 113 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 114 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 115 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 116 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted 117 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 118 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted 119 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted 120 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted 121 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted 122 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted 123 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 124 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted 125 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted 126 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 127 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 128 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 129 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 130 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted 131 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted 132 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted 133 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted 134 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted 135 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 136 | * @param NewState: new state of the specified peripheral in Debug mode. 137 | * This parameter can be: ENABLE or DISABLE. 138 | * @retval None 139 | */ 140 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 141 | { 142 | /* Check the parameters */ 143 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 144 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 145 | 146 | if (NewState != DISABLE) 147 | { 148 | DBGMCU->CR |= DBGMCU_Periph; 149 | } 150 | else 151 | { 152 | DBGMCU->CR &= ~DBGMCU_Periph; 153 | } 154 | } 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /** 161 | * @} 162 | */ 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 169 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the EXTI firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_exti.h" 30 | 31 | /** @addtogroup STM32F10x_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup EXTI 36 | * @brief EXTI driver modules 37 | * @{ 38 | */ 39 | 40 | /** @defgroup EXTI_Private_TypesDefinitions 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | /** @defgroup EXTI_Private_Defines 49 | * @{ 50 | */ 51 | 52 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup EXTI_Private_Macros 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup EXTI_Private_Variables 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup EXTI_Private_FunctionPrototypes 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @defgroup EXTI_Private_Functions 83 | * @{ 84 | */ 85 | 86 | /** 87 | * @brief Deinitializes the EXTI peripheral registers to their default reset values. 88 | * @param None 89 | * @retval None 90 | */ 91 | void EXTI_DeInit(void) 92 | { 93 | EXTI->IMR = 0x00000000; 94 | EXTI->EMR = 0x00000000; 95 | EXTI->RTSR = 0x00000000; 96 | EXTI->FTSR = 0x00000000; 97 | EXTI->PR = 0x000FFFFF; 98 | } 99 | 100 | /** 101 | * @brief Initializes the EXTI peripheral according to the specified 102 | * parameters in the EXTI_InitStruct. 103 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure 104 | * that contains the configuration information for the EXTI peripheral. 105 | * @retval None 106 | */ 107 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) 108 | { 109 | uint32_t tmp = 0; 110 | 111 | /* Check the parameters */ 112 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); 113 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); 114 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); 115 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); 116 | 117 | tmp = (uint32_t)EXTI_BASE; 118 | 119 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 120 | { 121 | /* Clear EXTI line configuration */ 122 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 123 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 124 | 125 | tmp += EXTI_InitStruct->EXTI_Mode; 126 | 127 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 128 | 129 | /* Clear Rising Falling edge configuration */ 130 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 131 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 132 | 133 | /* Select the trigger for the selected external interrupts */ 134 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 135 | { 136 | /* Rising Falling edge */ 137 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 138 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 139 | } 140 | else 141 | { 142 | tmp = (uint32_t)EXTI_BASE; 143 | tmp += EXTI_InitStruct->EXTI_Trigger; 144 | 145 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 146 | } 147 | } 148 | else 149 | { 150 | tmp += EXTI_InitStruct->EXTI_Mode; 151 | 152 | /* Disable the selected external lines */ 153 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 154 | } 155 | } 156 | 157 | /** 158 | * @brief Fills each EXTI_InitStruct member with its reset value. 159 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will 160 | * be initialized. 161 | * @retval None 162 | */ 163 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) 164 | { 165 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 166 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 167 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 168 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 169 | } 170 | 171 | /** 172 | * @brief Generates a Software interrupt. 173 | * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. 174 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 175 | * @retval None 176 | */ 177 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 178 | { 179 | /* Check the parameters */ 180 | assert_param(IS_EXTI_LINE(EXTI_Line)); 181 | 182 | EXTI->SWIER |= EXTI_Line; 183 | } 184 | 185 | /** 186 | * @brief Checks whether the specified EXTI line flag is set or not. 187 | * @param EXTI_Line: specifies the EXTI line flag to check. 188 | * This parameter can be: 189 | * @arg EXTI_Linex: External interrupt line x where x(0..19) 190 | * @retval The new state of EXTI_Line (SET or RESET). 191 | */ 192 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 193 | { 194 | FlagStatus bitstatus = RESET; 195 | /* Check the parameters */ 196 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 197 | 198 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 199 | { 200 | bitstatus = SET; 201 | } 202 | else 203 | { 204 | bitstatus = RESET; 205 | } 206 | return bitstatus; 207 | } 208 | 209 | /** 210 | * @brief Clears the EXTI's line pending flags. 211 | * @param EXTI_Line: specifies the EXTI lines flags to clear. 212 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 213 | * @retval None 214 | */ 215 | void EXTI_ClearFlag(uint32_t EXTI_Line) 216 | { 217 | /* Check the parameters */ 218 | assert_param(IS_EXTI_LINE(EXTI_Line)); 219 | 220 | EXTI->PR = EXTI_Line; 221 | } 222 | 223 | /** 224 | * @brief Checks whether the specified EXTI line is asserted or not. 225 | * @param EXTI_Line: specifies the EXTI line to check. 226 | * This parameter can be: 227 | * @arg EXTI_Linex: External interrupt line x where x(0..19) 228 | * @retval The new state of EXTI_Line (SET or RESET). 229 | */ 230 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 231 | { 232 | ITStatus bitstatus = RESET; 233 | uint32_t enablestatus = 0; 234 | /* Check the parameters */ 235 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 236 | 237 | enablestatus = EXTI->IMR & EXTI_Line; 238 | if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 239 | { 240 | bitstatus = SET; 241 | } 242 | else 243 | { 244 | bitstatus = RESET; 245 | } 246 | return bitstatus; 247 | } 248 | 249 | /** 250 | * @brief Clears the EXTI's line pending bits. 251 | * @param EXTI_Line: specifies the EXTI lines to clear. 252 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 253 | * @retval None 254 | */ 255 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 256 | { 257 | /* Check the parameters */ 258 | assert_param(IS_EXTI_LINE(EXTI_Line)); 259 | 260 | EXTI->PR = EXTI_Line; 261 | } 262 | 263 | /** 264 | * @} 265 | */ 266 | 267 | /** 268 | * @} 269 | */ 270 | 271 | /** 272 | * @} 273 | */ 274 | 275 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 276 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lmooml/SmartTimer/8f81d89a6c34fb115080b3b8707d705c24bcfec4/demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lmooml/SmartTimer/8f81d89a6c34fb115080b3b8707d705c24bcfec4/demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the IWDG firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_iwdg.h" 30 | 31 | /** @addtogroup STM32F10x_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup IWDG 36 | * @brief IWDG driver modules 37 | * @{ 38 | */ 39 | 40 | /** @defgroup IWDG_Private_TypesDefinitions 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | /** @defgroup IWDG_Private_Defines 49 | * @{ 50 | */ 51 | 52 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 53 | 54 | /* KR register bit mask */ 55 | #define KR_KEY_Reload ((uint16_t)0xAAAA) 56 | #define KR_KEY_Enable ((uint16_t)0xCCCC) 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /** @defgroup IWDG_Private_Macros 63 | * @{ 64 | */ 65 | 66 | /** 67 | * @} 68 | */ 69 | 70 | /** @defgroup IWDG_Private_Variables 71 | * @{ 72 | */ 73 | 74 | /** 75 | * @} 76 | */ 77 | 78 | /** @defgroup IWDG_Private_FunctionPrototypes 79 | * @{ 80 | */ 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup IWDG_Private_Functions 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 92 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 93 | * This parameter can be one of the following values: 94 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 95 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 96 | * @retval None 97 | */ 98 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 99 | { 100 | /* Check the parameters */ 101 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 102 | IWDG->KR = IWDG_WriteAccess; 103 | } 104 | 105 | /** 106 | * @brief Sets IWDG Prescaler value. 107 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 108 | * This parameter can be one of the following values: 109 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 110 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 111 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 112 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 113 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 114 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 115 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 116 | * @retval None 117 | */ 118 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 119 | { 120 | /* Check the parameters */ 121 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 122 | IWDG->PR = IWDG_Prescaler; 123 | } 124 | 125 | /** 126 | * @brief Sets IWDG Reload value. 127 | * @param Reload: specifies the IWDG Reload value. 128 | * This parameter must be a number between 0 and 0x0FFF. 129 | * @retval None 130 | */ 131 | void IWDG_SetReload(uint16_t Reload) 132 | { 133 | /* Check the parameters */ 134 | assert_param(IS_IWDG_RELOAD(Reload)); 135 | IWDG->RLR = Reload; 136 | } 137 | 138 | /** 139 | * @brief Reloads IWDG counter with value defined in the reload register 140 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 141 | * @param None 142 | * @retval None 143 | */ 144 | void IWDG_ReloadCounter(void) 145 | { 146 | IWDG->KR = KR_KEY_Reload; 147 | } 148 | 149 | /** 150 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 151 | * @param None 152 | * @retval None 153 | */ 154 | void IWDG_Enable(void) 155 | { 156 | IWDG->KR = KR_KEY_Enable; 157 | } 158 | 159 | /** 160 | * @brief Checks whether the specified IWDG flag is set or not. 161 | * @param IWDG_FLAG: specifies the flag to check. 162 | * This parameter can be one of the following values: 163 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 164 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 165 | * @retval The new state of IWDG_FLAG (SET or RESET). 166 | */ 167 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 168 | { 169 | FlagStatus bitstatus = RESET; 170 | /* Check the parameters */ 171 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 172 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 173 | { 174 | bitstatus = SET; 175 | } 176 | else 177 | { 178 | bitstatus = RESET; 179 | } 180 | /* Return the flag status */ 181 | return bitstatus; 182 | } 183 | 184 | /** 185 | * @} 186 | */ 187 | 188 | /** 189 | * @} 190 | */ 191 | 192 | /** 193 | * @} 194 | */ 195 | 196 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 197 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the PWR firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_pwr.h" 30 | #include "stm32f10x_rcc.h" 31 | 32 | /** @addtogroup STM32F10x_StdPeriph_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup PWR 37 | * @brief PWR driver modules 38 | * @{ 39 | */ 40 | 41 | /** @defgroup PWR_Private_TypesDefinitions 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup PWR_Private_Defines 50 | * @{ 51 | */ 52 | 53 | /* --------- PWR registers bit address in the alias region ---------- */ 54 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 55 | 56 | /* --- CR Register ---*/ 57 | 58 | /* Alias word address of DBP bit */ 59 | #define CR_OFFSET (PWR_OFFSET + 0x00) 60 | #define DBP_BitNumber 0x08 61 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 62 | 63 | /* Alias word address of PVDE bit */ 64 | #define PVDE_BitNumber 0x04 65 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 66 | 67 | /* --- CSR Register ---*/ 68 | 69 | /* Alias word address of EWUP bit */ 70 | #define CSR_OFFSET (PWR_OFFSET + 0x04) 71 | #define EWUP_BitNumber 0x08 72 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 73 | 74 | /* ------------------ PWR registers bit mask ------------------------ */ 75 | 76 | /* CR register bit mask */ 77 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) 78 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) 79 | 80 | 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup PWR_Private_Macros 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup PWR_Private_Variables 94 | * @{ 95 | */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** @defgroup PWR_Private_FunctionPrototypes 102 | * @{ 103 | */ 104 | 105 | /** 106 | * @} 107 | */ 108 | 109 | /** @defgroup PWR_Private_Functions 110 | * @{ 111 | */ 112 | 113 | /** 114 | * @brief Deinitializes the PWR peripheral registers to their default reset values. 115 | * @param None 116 | * @retval None 117 | */ 118 | void PWR_DeInit(void) 119 | { 120 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 121 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 122 | } 123 | 124 | /** 125 | * @brief Enables or disables access to the RTC and backup registers. 126 | * @param NewState: new state of the access to the RTC and backup registers. 127 | * This parameter can be: ENABLE or DISABLE. 128 | * @retval None 129 | */ 130 | void PWR_BackupAccessCmd(FunctionalState NewState) 131 | { 132 | /* Check the parameters */ 133 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 134 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 135 | } 136 | 137 | /** 138 | * @brief Enables or disables the Power Voltage Detector(PVD). 139 | * @param NewState: new state of the PVD. 140 | * This parameter can be: ENABLE or DISABLE. 141 | * @retval None 142 | */ 143 | void PWR_PVDCmd(FunctionalState NewState) 144 | { 145 | /* Check the parameters */ 146 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 147 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 148 | } 149 | 150 | /** 151 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 152 | * @param PWR_PVDLevel: specifies the PVD detection level 153 | * This parameter can be one of the following values: 154 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 155 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 156 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 157 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 158 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 159 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 160 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 161 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 162 | * @retval None 163 | */ 164 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 165 | { 166 | uint32_t tmpreg = 0; 167 | /* Check the parameters */ 168 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 169 | tmpreg = PWR->CR; 170 | /* Clear PLS[7:5] bits */ 171 | tmpreg &= CR_PLS_MASK; 172 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 173 | tmpreg |= PWR_PVDLevel; 174 | /* Store the new value */ 175 | PWR->CR = tmpreg; 176 | } 177 | 178 | /** 179 | * @brief Enables or disables the WakeUp Pin functionality. 180 | * @param NewState: new state of the WakeUp Pin functionality. 181 | * This parameter can be: ENABLE or DISABLE. 182 | * @retval None 183 | */ 184 | void PWR_WakeUpPinCmd(FunctionalState NewState) 185 | { 186 | /* Check the parameters */ 187 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 188 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 189 | } 190 | 191 | /** 192 | * @brief Enters STOP mode. 193 | * @param PWR_Regulator: specifies the regulator state in STOP mode. 194 | * This parameter can be one of the following values: 195 | * @arg PWR_Regulator_ON: STOP mode with regulator ON 196 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 197 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 198 | * This parameter can be one of the following values: 199 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 200 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 201 | * @retval None 202 | */ 203 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 204 | { 205 | uint32_t tmpreg = 0; 206 | /* Check the parameters */ 207 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 208 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 209 | 210 | /* Select the regulator state in STOP mode ---------------------------------*/ 211 | tmpreg = PWR->CR; 212 | /* Clear PDDS and LPDS bits */ 213 | tmpreg &= CR_DS_MASK; 214 | /* Set LPDS bit according to PWR_Regulator value */ 215 | tmpreg |= PWR_Regulator; 216 | /* Store the new value */ 217 | PWR->CR = tmpreg; 218 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 219 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 220 | 221 | /* Select STOP mode entry --------------------------------------------------*/ 222 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 223 | { 224 | /* Request Wait For Interrupt */ 225 | __WFI(); 226 | } 227 | else 228 | { 229 | /* Request Wait For Event */ 230 | __WFE(); 231 | } 232 | 233 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ 234 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 235 | } 236 | 237 | /** 238 | * @brief Enters STANDBY mode. 239 | * @param None 240 | * @retval None 241 | */ 242 | void PWR_EnterSTANDBYMode(void) 243 | { 244 | /* Clear Wake-up flag */ 245 | PWR->CR |= PWR_CR_CWUF; 246 | /* Select STANDBY mode */ 247 | PWR->CR |= PWR_CR_PDDS; 248 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 249 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 250 | /* This option is used to ensure that store operations are completed */ 251 | #if defined ( __CC_ARM ) 252 | __force_stores(); 253 | #endif 254 | /* Request Wait For Interrupt */ 255 | __WFI(); 256 | } 257 | 258 | /** 259 | * @brief Checks whether the specified PWR flag is set or not. 260 | * @param PWR_FLAG: specifies the flag to check. 261 | * This parameter can be one of the following values: 262 | * @arg PWR_FLAG_WU: Wake Up flag 263 | * @arg PWR_FLAG_SB: StandBy flag 264 | * @arg PWR_FLAG_PVDO: PVD Output 265 | * @retval The new state of PWR_FLAG (SET or RESET). 266 | */ 267 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 268 | { 269 | FlagStatus bitstatus = RESET; 270 | /* Check the parameters */ 271 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 272 | 273 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 274 | { 275 | bitstatus = SET; 276 | } 277 | else 278 | { 279 | bitstatus = RESET; 280 | } 281 | /* Return the flag status */ 282 | return bitstatus; 283 | } 284 | 285 | /** 286 | * @brief Clears the PWR's pending flags. 287 | * @param PWR_FLAG: specifies the flag to clear. 288 | * This parameter can be one of the following values: 289 | * @arg PWR_FLAG_WU: Wake Up flag 290 | * @arg PWR_FLAG_SB: StandBy flag 291 | * @retval None 292 | */ 293 | void PWR_ClearFlag(uint32_t PWR_FLAG) 294 | { 295 | /* Check the parameters */ 296 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 297 | 298 | PWR->CR |= PWR_FLAG << 2; 299 | } 300 | 301 | /** 302 | * @} 303 | */ 304 | 305 | /** 306 | * @} 307 | */ 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 314 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the RTC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_rtc.h" 30 | 31 | /** @addtogroup STM32F10x_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup RTC 36 | * @brief RTC driver modules 37 | * @{ 38 | */ 39 | 40 | /** @defgroup RTC_Private_TypesDefinitions 41 | * @{ 42 | */ 43 | /** 44 | * @} 45 | */ 46 | 47 | /** @defgroup RTC_Private_Defines 48 | * @{ 49 | */ 50 | #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ 51 | #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ 52 | 53 | /** 54 | * @} 55 | */ 56 | 57 | /** @defgroup RTC_Private_Macros 58 | * @{ 59 | */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup RTC_Private_Variables 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup RTC_Private_FunctionPrototypes 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @defgroup RTC_Private_Functions 82 | * @{ 83 | */ 84 | 85 | /** 86 | * @brief Enables or disables the specified RTC interrupts. 87 | * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. 88 | * This parameter can be any combination of the following values: 89 | * @arg RTC_IT_OW: Overflow interrupt 90 | * @arg RTC_IT_ALR: Alarm interrupt 91 | * @arg RTC_IT_SEC: Second interrupt 92 | * @param NewState: new state of the specified RTC interrupts. 93 | * This parameter can be: ENABLE or DISABLE. 94 | * @retval None 95 | */ 96 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) 97 | { 98 | /* Check the parameters */ 99 | assert_param(IS_RTC_IT(RTC_IT)); 100 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 101 | 102 | if (NewState != DISABLE) 103 | { 104 | RTC->CRH |= RTC_IT; 105 | } 106 | else 107 | { 108 | RTC->CRH &= (uint16_t)~RTC_IT; 109 | } 110 | } 111 | 112 | /** 113 | * @brief Enters the RTC configuration mode. 114 | * @param None 115 | * @retval None 116 | */ 117 | void RTC_EnterConfigMode(void) 118 | { 119 | /* Set the CNF flag to enter in the Configuration Mode */ 120 | RTC->CRL |= RTC_CRL_CNF; 121 | } 122 | 123 | /** 124 | * @brief Exits from the RTC configuration mode. 125 | * @param None 126 | * @retval None 127 | */ 128 | void RTC_ExitConfigMode(void) 129 | { 130 | /* Reset the CNF flag to exit from the Configuration Mode */ 131 | RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 132 | } 133 | 134 | /** 135 | * @brief Gets the RTC counter value. 136 | * @param None 137 | * @retval RTC counter value. 138 | */ 139 | uint32_t RTC_GetCounter(void) 140 | { 141 | uint16_t high1 = 0, high2 = 0, low = 0; 142 | 143 | high1 = RTC->CNTH; 144 | low = RTC->CNTL; 145 | high2 = RTC->CNTH; 146 | 147 | if (high1 != high2) 148 | { /* In this case the counter roll over during reading of CNTL and CNTH registers, 149 | read again CNTL register then return the counter value */ 150 | return (((uint32_t) high2 << 16 ) | RTC->CNTL); 151 | } 152 | else 153 | { /* No counter roll over during reading of CNTL and CNTH registers, counter 154 | value is equal to first value of CNTL and CNTH */ 155 | return (((uint32_t) high1 << 16 ) | low); 156 | } 157 | } 158 | 159 | /** 160 | * @brief Sets the RTC counter value. 161 | * @param CounterValue: RTC counter new value. 162 | * @retval None 163 | */ 164 | void RTC_SetCounter(uint32_t CounterValue) 165 | { 166 | RTC_EnterConfigMode(); 167 | /* Set RTC COUNTER MSB word */ 168 | RTC->CNTH = CounterValue >> 16; 169 | /* Set RTC COUNTER LSB word */ 170 | RTC->CNTL = (CounterValue & RTC_LSB_MASK); 171 | RTC_ExitConfigMode(); 172 | } 173 | 174 | /** 175 | * @brief Sets the RTC prescaler value. 176 | * @param PrescalerValue: RTC prescaler new value. 177 | * @retval None 178 | */ 179 | void RTC_SetPrescaler(uint32_t PrescalerValue) 180 | { 181 | /* Check the parameters */ 182 | assert_param(IS_RTC_PRESCALER(PrescalerValue)); 183 | 184 | RTC_EnterConfigMode(); 185 | /* Set RTC PRESCALER MSB word */ 186 | RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; 187 | /* Set RTC PRESCALER LSB word */ 188 | RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); 189 | RTC_ExitConfigMode(); 190 | } 191 | 192 | /** 193 | * @brief Sets the RTC alarm value. 194 | * @param AlarmValue: RTC alarm new value. 195 | * @retval None 196 | */ 197 | void RTC_SetAlarm(uint32_t AlarmValue) 198 | { 199 | RTC_EnterConfigMode(); 200 | /* Set the ALARM MSB word */ 201 | RTC->ALRH = AlarmValue >> 16; 202 | /* Set the ALARM LSB word */ 203 | RTC->ALRL = (AlarmValue & RTC_LSB_MASK); 204 | RTC_ExitConfigMode(); 205 | } 206 | 207 | /** 208 | * @brief Gets the RTC divider value. 209 | * @param None 210 | * @retval RTC Divider value. 211 | */ 212 | uint32_t RTC_GetDivider(void) 213 | { 214 | uint32_t tmp = 0x00; 215 | tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; 216 | tmp |= RTC->DIVL; 217 | return tmp; 218 | } 219 | 220 | /** 221 | * @brief Waits until last write operation on RTC registers has finished. 222 | * @note This function must be called before any write to RTC registers. 223 | * @param None 224 | * @retval None 225 | */ 226 | void RTC_WaitForLastTask(void) 227 | { 228 | /* Loop until RTOFF flag is set */ 229 | while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) 230 | { 231 | } 232 | } 233 | 234 | /** 235 | * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) 236 | * are synchronized with RTC APB clock. 237 | * @note This function must be called before any read operation after an APB reset 238 | * or an APB clock stop. 239 | * @param None 240 | * @retval None 241 | */ 242 | void RTC_WaitForSynchro(void) 243 | { 244 | /* Clear RSF flag */ 245 | RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; 246 | /* Loop until RSF flag is set */ 247 | while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) 248 | { 249 | } 250 | } 251 | 252 | /** 253 | * @brief Checks whether the specified RTC flag is set or not. 254 | * @param RTC_FLAG: specifies the flag to check. 255 | * This parameter can be one the following values: 256 | * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag 257 | * @arg RTC_FLAG_RSF: Registers Synchronized flag 258 | * @arg RTC_FLAG_OW: Overflow flag 259 | * @arg RTC_FLAG_ALR: Alarm flag 260 | * @arg RTC_FLAG_SEC: Second flag 261 | * @retval The new state of RTC_FLAG (SET or RESET). 262 | */ 263 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) 264 | { 265 | FlagStatus bitstatus = RESET; 266 | 267 | /* Check the parameters */ 268 | assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 269 | 270 | if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) 271 | { 272 | bitstatus = SET; 273 | } 274 | else 275 | { 276 | bitstatus = RESET; 277 | } 278 | return bitstatus; 279 | } 280 | 281 | /** 282 | * @brief Clears the RTC's pending flags. 283 | * @param RTC_FLAG: specifies the flag to clear. 284 | * This parameter can be any combination of the following values: 285 | * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after 286 | * an APB reset or an APB Clock stop. 287 | * @arg RTC_FLAG_OW: Overflow flag 288 | * @arg RTC_FLAG_ALR: Alarm flag 289 | * @arg RTC_FLAG_SEC: Second flag 290 | * @retval None 291 | */ 292 | void RTC_ClearFlag(uint16_t RTC_FLAG) 293 | { 294 | /* Check the parameters */ 295 | assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 296 | 297 | /* Clear the corresponding RTC flag */ 298 | RTC->CRL &= (uint16_t)~RTC_FLAG; 299 | } 300 | 301 | /** 302 | * @brief Checks whether the specified RTC interrupt has occurred or not. 303 | * @param RTC_IT: specifies the RTC interrupts sources to check. 304 | * This parameter can be one of the following values: 305 | * @arg RTC_IT_OW: Overflow interrupt 306 | * @arg RTC_IT_ALR: Alarm interrupt 307 | * @arg RTC_IT_SEC: Second interrupt 308 | * @retval The new state of the RTC_IT (SET or RESET). 309 | */ 310 | ITStatus RTC_GetITStatus(uint16_t RTC_IT) 311 | { 312 | ITStatus bitstatus = RESET; 313 | /* Check the parameters */ 314 | assert_param(IS_RTC_GET_IT(RTC_IT)); 315 | 316 | bitstatus = (ITStatus)(RTC->CRL & RTC_IT); 317 | if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) 318 | { 319 | bitstatus = SET; 320 | } 321 | else 322 | { 323 | bitstatus = RESET; 324 | } 325 | return bitstatus; 326 | } 327 | 328 | /** 329 | * @brief Clears the RTC's interrupt pending bits. 330 | * @param RTC_IT: specifies the interrupt pending bit to clear. 331 | * This parameter can be any combination of the following values: 332 | * @arg RTC_IT_OW: Overflow interrupt 333 | * @arg RTC_IT_ALR: Alarm interrupt 334 | * @arg RTC_IT_SEC: Second interrupt 335 | * @retval None 336 | */ 337 | void RTC_ClearITPendingBit(uint16_t RTC_IT) 338 | { 339 | /* Check the parameters */ 340 | assert_param(IS_RTC_IT(RTC_IT)); 341 | 342 | /* Clear the corresponding RTC pending bit */ 343 | RTC->CRL &= (uint16_t)~RTC_IT; 344 | } 345 | 346 | /** 347 | * @} 348 | */ 349 | 350 | /** 351 | * @} 352 | */ 353 | 354 | /** 355 | * @} 356 | */ 357 | 358 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 359 | -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lmooml/SmartTimer/8f81d89a6c34fb115080b3b8707d705c24bcfec4/demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c -------------------------------------------------------------------------------- /demo/fwlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.c 4 | * @author MCD Application Team 5 | * @version V3.6.1 6 | * @date 05-March-2012 7 | * @brief This file provides all the WWDG firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f10x_wwdg.h" 30 | #include "stm32f10x_rcc.h" 31 | 32 | /** @addtogroup STM32F10x_StdPeriph_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup WWDG 37 | * @brief WWDG driver modules 38 | * @{ 39 | */ 40 | 41 | /** @defgroup WWDG_Private_TypesDefinitions 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup WWDG_Private_Defines 50 | * @{ 51 | */ 52 | 53 | /* ----------- WWDG registers bit address in the alias region ----------- */ 54 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) 55 | 56 | /* Alias word address of EWI bit */ 57 | #define CFR_OFFSET (WWDG_OFFSET + 0x04) 58 | #define EWI_BitNumber 0x09 59 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) 60 | 61 | /* --------------------- WWDG registers bit mask ------------------------ */ 62 | 63 | /* CR register bit mask */ 64 | #define CR_WDGA_Set ((uint32_t)0x00000080) 65 | 66 | /* CFR register bit mask */ 67 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 68 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80) 69 | #define BIT_Mask ((uint8_t)0x7F) 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup WWDG_Private_Macros 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @defgroup WWDG_Private_Variables 84 | * @{ 85 | */ 86 | 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @defgroup WWDG_Private_FunctionPrototypes 92 | * @{ 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @defgroup WWDG_Private_Functions 100 | * @{ 101 | */ 102 | 103 | /** 104 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 105 | * @param None 106 | * @retval None 107 | */ 108 | void WWDG_DeInit(void) 109 | { 110 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 111 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 112 | } 113 | 114 | /** 115 | * @brief Sets the WWDG Prescaler. 116 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 117 | * This parameter can be one of the following values: 118 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 119 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 120 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 121 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 122 | * @retval None 123 | */ 124 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 125 | { 126 | uint32_t tmpreg = 0; 127 | /* Check the parameters */ 128 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 129 | /* Clear WDGTB[1:0] bits */ 130 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask; 131 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 132 | tmpreg |= WWDG_Prescaler; 133 | /* Store the new value */ 134 | WWDG->CFR = tmpreg; 135 | } 136 | 137 | /** 138 | * @brief Sets the WWDG window value. 139 | * @param WindowValue: specifies the window value to be compared to the downcounter. 140 | * This parameter value must be lower than 0x80. 141 | * @retval None 142 | */ 143 | void WWDG_SetWindowValue(uint8_t WindowValue) 144 | { 145 | __IO uint32_t tmpreg = 0; 146 | 147 | /* Check the parameters */ 148 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 149 | /* Clear W[6:0] bits */ 150 | 151 | tmpreg = WWDG->CFR & CFR_W_Mask; 152 | 153 | /* Set W[6:0] bits according to WindowValue value */ 154 | tmpreg |= WindowValue & (uint32_t) BIT_Mask; 155 | 156 | /* Store the new value */ 157 | WWDG->CFR = tmpreg; 158 | } 159 | 160 | /** 161 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 162 | * @param None 163 | * @retval None 164 | */ 165 | void WWDG_EnableIT(void) 166 | { 167 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; 168 | } 169 | 170 | /** 171 | * @brief Sets the WWDG counter value. 172 | * @param Counter: specifies the watchdog counter value. 173 | * This parameter must be a number between 0x40 and 0x7F. 174 | * @retval None 175 | */ 176 | void WWDG_SetCounter(uint8_t Counter) 177 | { 178 | /* Check the parameters */ 179 | assert_param(IS_WWDG_COUNTER(Counter)); 180 | /* Write to T[6:0] bits to configure the counter value, no need to do 181 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 182 | WWDG->CR = Counter & BIT_Mask; 183 | } 184 | 185 | /** 186 | * @brief Enables WWDG and load the counter value. 187 | * @param Counter: specifies the watchdog counter value. 188 | * This parameter must be a number between 0x40 and 0x7F. 189 | * @retval None 190 | */ 191 | void WWDG_Enable(uint8_t Counter) 192 | { 193 | /* Check the parameters */ 194 | assert_param(IS_WWDG_COUNTER(Counter)); 195 | WWDG->CR = CR_WDGA_Set | Counter; 196 | } 197 | 198 | /** 199 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 200 | * @param None 201 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) 202 | */ 203 | FlagStatus WWDG_GetFlagStatus(void) 204 | { 205 | return (FlagStatus)(WWDG->SR); 206 | } 207 | 208 | /** 209 | * @brief Clears Early Wakeup interrupt flag. 210 | * @param None 211 | * @retval None 212 | */ 213 | void WWDG_ClearFlag(void) 214 | { 215 | WWDG->SR = (uint32_t)RESET; 216 | } 217 | 218 | /** 219 | * @} 220 | */ 221 | 222 | /** 223 | * @} 224 | */ 225 | 226 | /** 227 | * @} 228 | */ 229 | 230 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 231 | -------------------------------------------------------------------------------- /smarttimer/smarttimer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lmooml/SmartTimer/8f81d89a6c34fb115080b3b8707d705c24bcfec4/smarttimer/smarttimer.h --------------------------------------------------------------------------------