├── .clang-format ├── .dockerignore ├── .github ├── ISSUE_TEMPLATE │ ├── bug_report.md │ └── feature_request.md ├── PULL_REQUEST_TEMPLATE.md ├── PULL_REQUEST_TEMPLATE │ └── pull_request_template.md ├── dependabot.yml ├── labeler.yml └── workflows │ ├── build.yml │ ├── cell_lib_test.yml │ ├── doc_dependencies.sh │ ├── docker.yml │ ├── format.yaml │ ├── install_dependencies_build_centos7p9.sh │ ├── install_dependencies_build_centos9.sh │ ├── install_dependencies_build_ubuntu.sh │ ├── install_dependencies_run_ubuntu.sh │ ├── labeler.yml │ └── patch_updater.yml ├── .gitignore ├── .gitmodules ├── .readthedocs.yml ├── CMakeLists.txt ├── Dockerfile ├── LICENSE ├── Makefile ├── README.md ├── VERSION.md ├── cmake ├── modules │ ├── AutoClangFormat.cmake │ ├── FilesToDirs.cmake │ ├── FindReadline.cmake │ ├── OpenfpgaInstaller.cmake │ ├── OpenfpgaPackaging.cmake │ ├── SupportCcache.cmake │ └── SwigLib.cmake └── toolchains │ └── mingw-linux-cross-compile-to-windows.cmake ├── dev └── check-format.sh ├── docker ├── Dockerfile.base ├── Dockerfile.clang-11 ├── Dockerfile.clang-12 ├── Dockerfile.clang-13 ├── Dockerfile.clang-14 ├── Dockerfile.env ├── Dockerfile.gcc-10 ├── Dockerfile.gcc-11 ├── Dockerfile.gcc-12 ├── Dockerfile.gcc-9 └── Dockerfile.master ├── docs ├── .gitignore ├── Makefile ├── make.bat ├── requirements.txt └── source │ ├── VERSION.md │ ├── appendix │ ├── acknowledge.rst │ ├── contact.rst │ ├── figures │ │ ├── darpa_logo.png │ │ ├── google_logo.png │ │ ├── lnis_logo.png │ │ ├── quicklogic_logo.png │ │ ├── rapidflex_logo.png │ │ ├── rapidsilicon_logo.png │ │ └── uofu_logo.png │ ├── index.rst │ ├── reference.rst │ └── z_reference.bib │ ├── conf.py │ ├── dev_manual │ ├── back_compatible.rst │ ├── ci.rst │ ├── contributor_guidelines │ │ ├── general_rules.rst │ │ ├── index.rst │ │ └── naming_convention.rst │ ├── index.rst │ ├── regression_tests.rst │ ├── tcl_api.rst │ └── version_number.rst │ ├── index.rst │ ├── manual │ ├── arch_lang │ │ ├── addon_vpr_syntax.rst │ │ ├── annotate_vpr_arch.rst │ │ ├── circuit_library.rst │ │ ├── circuit_model_examples.rst │ │ ├── config_protocol.rst │ │ ├── direct_interconnect.rst │ │ ├── fabric_key.rst │ │ ├── figures │ │ │ ├── Buffer.png │ │ │ ├── FF.png │ │ │ ├── Inverter_1.png │ │ │ ├── Tapered_inverter.png │ │ │ ├── ccff_fpga.png │ │ │ ├── concat_pass_wire.svg │ │ │ ├── concat_wire.svg │ │ │ ├── config_chain.svg │ │ │ ├── config_chain_config_enable.svg │ │ │ ├── config_chain_scan_capable.svg │ │ │ ├── config_latch.png │ │ │ ├── ecb.png │ │ │ ├── ecb_allowed_direct_connection.png │ │ │ ├── ecb_allowed_direct_connection_inner_tile_example.png │ │ │ ├── ecb_allowed_direct_connection_inter_tile_example.png │ │ │ ├── ecb_forbid_direct_connection_example.png │ │ │ ├── fabric_key_motivation.png │ │ │ ├── frac_lut3_example.svg │ │ │ ├── frame_config_protocol.png │ │ │ ├── frame_config_protocol_example.png │ │ │ ├── full_adder_1bit_circuit_model.svg │ │ │ ├── global_inout_ports.png │ │ │ ├── global_input_ports.png │ │ │ ├── global_tile_ports.png │ │ │ ├── gpin_ports.png │ │ │ ├── gpio_ports.png │ │ │ ├── gpout_ports.png │ │ │ ├── iopad.png │ │ │ ├── lut_arith_example.svg │ │ │ ├── lut_intermediate_buffer_example.svg │ │ │ ├── meas_edge.png │ │ │ ├── memory_bank.png │ │ │ ├── memory_bank_decoder.svg │ │ │ ├── memory_bank_flatten.svg │ │ │ ├── memory_bank_shift_register.svg │ │ │ ├── multi_mode_dpram128x8_memory_circuit_model.svg │ │ │ ├── multi_mode_ff_circuit_model.svg │ │ │ ├── multi_mode_mult8x8_circuit_model.svg │ │ │ ├── multi_region_config_chains.png │ │ │ ├── mux.png │ │ │ ├── mux1lvl.png │ │ │ ├── native_frac_lut.svg │ │ │ ├── opin2all_sides.svg │ │ │ ├── pass-gate.png │ │ │ ├── pass_transistor.png │ │ │ ├── perimeter_cb.png │ │ │ ├── point2point_example.png │ │ │ ├── point2point_truthtable.png │ │ │ ├── shrink_boundary.png │ │ │ ├── single_lut3_example.svg │ │ │ ├── single_mode_dpram128x8_memory_circuit_model.svg │ │ │ ├── single_mode_mult8x8_circuit_model.svg │ │ │ ├── sram_blwl.png │ │ │ ├── sram_blwlr.svg │ │ │ ├── std_frac_lut.svg │ │ │ ├── stdcellmux.png │ │ │ ├── subtile_port_merge.png │ │ │ ├── thru_channel.png │ │ │ ├── vanilla_config_protocol.png │ │ │ └── wire.png │ │ ├── generality.rst │ │ ├── index.rst │ │ ├── simulation_setting.rst │ │ └── technology_library.rst │ ├── file_formats │ │ ├── architecture_bitstream.rst │ │ ├── bitstream_distribution_file.rst │ │ ├── bitstream_setting.rst │ │ ├── bus_group_file.rst │ │ ├── clock_network.rst │ │ ├── fabric_bitstream.rst │ │ ├── fabric_hierarchy_file.rst │ │ ├── fabric_key.rst │ │ ├── fabric_pin_physical_location_file.rst │ │ ├── figures │ │ │ ├── fpga_core_wrapper.png │ │ │ ├── prog_clk_network_example_2x2.png │ │ │ ├── prog_clk_network_example_2x2_perimeter_cb.png │ │ │ ├── tile_style_bottom_left.png │ │ │ └── tile_style_top_left.png │ │ ├── index.rst │ │ ├── io_info_file.rst │ │ ├── io_mapping_file.rst │ │ ├── io_naming_file.rst │ │ ├── module_naming_file.rst │ │ ├── pcf_file.rst │ │ ├── pin_constraints_file.rst │ │ ├── pin_table_file.rst │ │ ├── reference_file.rst │ │ ├── repack_design_constraints.rst │ │ ├── tile_config_file.rst │ │ └── unique_blocks.rst │ ├── fpga_bitstream │ │ ├── fabric_dependent_bitstream.rst │ │ ├── generic_bitstream.rst │ │ └── index.rst │ ├── fpga_spice │ │ ├── command_line_usage.rst │ │ ├── customize_subckt.rst │ │ ├── file_organization.rst │ │ ├── index.rst │ │ └── spice_simulation.rst │ ├── fpga_verilog │ │ ├── fabric_netlist.rst │ │ ├── figures │ │ │ ├── fabric_netlist_hierarchy.png │ │ │ ├── full_testbench_block_diagram.svg │ │ │ ├── full_testbench_waveform.svg │ │ │ ├── generic_fabric.png │ │ │ ├── mock_fpga_wrapper.png │ │ │ ├── preconfig_module.png │ │ │ └── verilog_testbench_hierarchy.svg │ │ ├── index.rst │ │ ├── mock_fpga_wrapper.rst │ │ └── testbench.rst │ ├── index.rst │ ├── openfpga_flow │ │ ├── index.rst │ │ ├── run_fpga_flow.rst │ │ └── run_fpga_task.rst │ ├── openfpga_shell │ │ ├── index.rst │ │ ├── launch_openfpga_shell.rst │ │ ├── openfpga_commands │ │ │ ├── basic_commands.rst │ │ │ ├── figures │ │ │ │ ├── group_config_block_hierarchy.png │ │ │ │ └── group_config_block_overview.png │ │ │ ├── fpga_bitstream_commands.rst │ │ │ ├── fpga_sdc_commands.rst │ │ │ ├── fpga_verilog_commands.rst │ │ │ ├── index.rst │ │ │ ├── setup_commands.rst │ │ │ └── vpr_commands.rst │ │ └── openfpga_script.rst │ └── utilities │ │ ├── fabric_key_assistant.rst │ │ ├── index.rst │ │ └── module_rename_assistant.rst │ ├── overview │ ├── figures │ │ ├── OpenFPGA_logo.pdf │ │ ├── OpenFPGA_logo.png │ │ ├── fpga_sdc_motivation.png │ │ ├── fpga_verilog_motivation.svg │ │ ├── openfpga_arch_lang_coverage.png │ │ ├── openfpga_framework.svg │ │ └── openfpga_motivation.png │ ├── index.rst │ ├── motivation.rst │ └── tech_highlights.rst │ └── tutorials │ ├── arch_modeling │ ├── figures │ │ ├── ADDF_Example_Spypad.svg │ │ ├── Control_Waveforms.pdf │ │ ├── Control_Waveforms.svg │ │ ├── Control_Waveforms2.svg │ │ ├── Control_Waveforms3.svg │ │ ├── Control_Waves.png │ │ ├── Control_Waves2.png │ │ ├── Custom_Waveforms.pdf │ │ ├── Custom_Waveforms.svg │ │ ├── Custom_Waveforms2.svg │ │ ├── Custom_Waves.png │ │ ├── Custom_Waves2.png │ │ ├── Error_log.png │ │ ├── gpout_ports.png │ │ ├── gpout_ports_example.png │ │ ├── k4n4_arch.png │ │ ├── lut6_Example_Spypad.svg │ │ ├── modified_arch_file.png │ │ ├── modified_user_defined_templates_file.png │ │ ├── spyadder_waveform.png │ │ └── spypad_waveforms.png │ ├── index.rst │ ├── open_cell_libraries_tutorial.rst │ ├── quick_start.rst │ ├── spypads_tutorial.rst │ └── user_defined_temp_tutorial.rst │ ├── design_flow │ ├── figures │ │ ├── Layout_Diagram.png │ │ ├── fpga_asap_10x10_final.png │ │ └── fpga_asap_10x10_floorplan.png │ ├── generate_fabric.rst │ ├── index.rst │ ├── verilog2gds2.rst │ └── verilog2verification.rst │ ├── getting_started │ ├── centos7p9_dependencies.sh │ ├── centos9_dependencies.sh │ ├── compile.rst │ ├── doc_dependencies.sh │ ├── figures │ │ └── openfpga_tools.svg │ ├── index.rst │ ├── shell_shortcuts.rst │ ├── tools.rst │ ├── ubuntu_dependencies.sh │ └── ubuntu_regtest_dependencies.sh │ └── index.rst ├── libs ├── CMakeLists.txt ├── libarchopenfpga │ ├── CMakeLists.txt │ ├── arch │ │ ├── sample_arch.xml │ │ └── sample_simulation_setting.xml │ ├── src │ │ ├── arch_direct.cpp │ │ ├── arch_direct.h │ │ ├── arch_direct_fwd.h │ │ ├── bitstream_setting.cpp │ │ ├── bitstream_setting.h │ │ ├── bitstream_setting_fwd.h │ │ ├── bitstream_setting_xml_constants.h │ │ ├── check_circuit_library.cpp │ │ ├── check_circuit_library.h │ │ ├── circuit_library.cpp │ │ ├── circuit_library.h │ │ ├── circuit_library_fwd.h │ │ ├── circuit_types.h │ │ ├── config_protocol.cpp │ │ ├── config_protocol.h │ │ ├── config_protocol_xml_constants.h │ │ ├── openfpga_arch.h │ │ ├── openfpga_arch_linker.cpp │ │ ├── openfpga_arch_linker.h │ │ ├── pb_type_annotation.cpp │ │ ├── pb_type_annotation.h │ │ ├── ql_memory_bank_config_setting.cpp │ │ ├── ql_memory_bank_config_setting.h │ │ ├── read_xml_bitstream_setting.cpp │ │ ├── read_xml_bitstream_setting.h │ │ ├── read_xml_circuit_library.cpp │ │ ├── read_xml_circuit_library.h │ │ ├── read_xml_config_protocol.cpp │ │ ├── read_xml_config_protocol.h │ │ ├── read_xml_openfpga_arch.cpp │ │ ├── read_xml_openfpga_arch.h │ │ ├── read_xml_openfpga_arch_utils.cpp │ │ ├── read_xml_openfpga_arch_utils.h │ │ ├── read_xml_pb_type_annotation.cpp │ │ ├── read_xml_pb_type_annotation.h │ │ ├── read_xml_routing_circuit.cpp │ │ ├── read_xml_routing_circuit.h │ │ ├── read_xml_simulation_setting.cpp │ │ ├── read_xml_simulation_setting.h │ │ ├── read_xml_technology_library.cpp │ │ ├── read_xml_technology_library.h │ │ ├── read_xml_tile_annotation.cpp │ │ ├── read_xml_tile_annotation.h │ │ ├── simulation_setting.cpp │ │ ├── simulation_setting.h │ │ ├── simulation_setting_fwd.h │ │ ├── technology_library.cpp │ │ ├── technology_library.h │ │ ├── technology_library_fwd.h │ │ ├── tile_annotation.cpp │ │ ├── tile_annotation.h │ │ ├── tile_annotation_fwd.h │ │ ├── write_xml_bitstream_setting.cpp │ │ ├── write_xml_bitstream_setting.h │ │ ├── write_xml_circuit_library.cpp │ │ ├── write_xml_circuit_library.h │ │ ├── write_xml_config_protocol.cpp │ │ ├── write_xml_config_protocol.h │ │ ├── write_xml_openfpga_arch.cpp │ │ ├── write_xml_openfpga_arch.h │ │ ├── write_xml_pb_type_annotation.cpp │ │ ├── write_xml_pb_type_annotation.h │ │ ├── write_xml_routing_circuit.cpp │ │ ├── write_xml_routing_circuit.h │ │ ├── write_xml_simulation_setting.cpp │ │ ├── write_xml_simulation_setting.h │ │ ├── write_xml_technology_library.cpp │ │ ├── write_xml_technology_library.h │ │ ├── write_xml_tile_annotation.cpp │ │ ├── write_xml_tile_annotation.h │ │ ├── write_xml_utils.cpp │ │ └── write_xml_utils.h │ └── test │ │ ├── read_arch_openfpga.cpp │ │ ├── read_bitstream_setting_openfpga.cpp │ │ └── read_simulation_setting_openfpga.cpp ├── libbusgroup │ ├── CMakeLists.txt │ ├── example │ │ └── bus_group_example.xml │ ├── src │ │ ├── bus_group.cpp │ │ ├── bus_group.h │ │ ├── bus_group_fwd.h │ │ ├── bus_group_xml_constants.h │ │ ├── read_xml_bus_group.cpp │ │ ├── read_xml_bus_group.h │ │ ├── write_xml_bus_group.cpp │ │ └── write_xml_bus_group.h │ └── test │ │ └── xml_io_bus_group.cpp ├── libclkarchopenfpga │ ├── CMakeLists.txt │ ├── arch │ │ ├── example.xml │ │ └── example_internal_drivers.xml │ ├── src │ │ ├── base │ │ │ ├── clock_network.cpp │ │ │ ├── clock_network.h │ │ │ ├── clock_network_fwd.h │ │ │ ├── rr_clock_spatial_lookup.cpp │ │ │ └── rr_clock_spatial_lookup.h │ │ ├── io │ │ │ ├── clock_network_xml_constants.h │ │ │ ├── read_xml_clock_network.cpp │ │ │ ├── read_xml_clock_network.h │ │ │ ├── write_xml_clock_network.cpp │ │ │ └── write_xml_clock_network.h │ │ └── utils │ │ │ ├── clock_network_utils.cpp │ │ │ └── clock_network_utils.h │ └── test │ │ └── xml_io_clock_network.cpp ├── libfabrickey │ ├── CMakeLists.txt │ ├── key_examples │ │ └── key_example.xml │ ├── src │ │ ├── base │ │ │ ├── fabric_key.cpp │ │ │ ├── fabric_key.h │ │ │ └── fabric_key_fwd.h │ │ ├── io │ │ │ ├── fabric_key_xml_constants.h │ │ │ ├── read_xml_fabric_key.cpp │ │ │ ├── read_xml_fabric_key.h │ │ │ ├── write_xml_fabric_key.cpp │ │ │ └── write_xml_fabric_key.h │ │ └── utils │ │ │ ├── check_fabric_key.cpp │ │ │ └── check_fabric_key.h │ └── test │ │ ├── fabric_key_assistant.cpp │ │ └── test_fabric_key.cpp ├── libfpgabitstream │ ├── CMakeLists.txt │ ├── bitstream_example │ │ └── arch_bitstream_example.xml │ ├── src │ │ ├── bitstream_manager.cpp │ │ ├── bitstream_manager.h │ │ ├── bitstream_manager_fwd.h │ │ ├── bitstream_manager_utils.cpp │ │ ├── bitstream_manager_utils.h │ │ ├── read_xml_arch_bitstream.cpp │ │ ├── read_xml_arch_bitstream.h │ │ ├── report_arch_bitstream_distribution.cpp │ │ ├── report_arch_bitstream_distribution.h │ │ ├── write_xml_arch_bitstream.cpp │ │ └── write_xml_arch_bitstream.h │ └── test │ │ └── test_arch_bitstream.cpp ├── libini │ ├── CMakeLists.txt │ └── src │ │ └── ini.h ├── libnamemanager │ ├── CMakeLists.txt │ ├── example │ │ ├── example.xml │ │ ├── example_module_names.xml │ │ └── example_module_names_expect_errors.xml │ ├── src │ │ ├── base │ │ │ ├── io_name_map.cpp │ │ │ ├── io_name_map.h │ │ │ ├── module_name_map.cpp │ │ │ └── module_name_map.h │ │ └── io │ │ │ ├── io_name_map_xml_constants.h │ │ │ ├── module_name_map_xml_constants.h │ │ │ ├── read_xml_io_name_map.cpp │ │ │ ├── read_xml_io_name_map.h │ │ │ ├── read_xml_module_name_map.cpp │ │ │ ├── read_xml_module_name_map.h │ │ │ ├── write_xml_io_name_map.cpp │ │ │ ├── write_xml_io_name_map.h │ │ │ ├── write_xml_module_name_map.cpp │ │ │ └── write_xml_module_name_map.h │ └── test │ │ ├── module_rename_assistant.cpp │ │ ├── xml_io_io_name_map.cpp │ │ └── xml_io_module_name_map.cpp ├── libopenfpgacapnproto │ ├── CMakeLists.txt │ ├── README.md │ └── gen │ │ ├── README.gen.md │ │ ├── unique_blocks.xsd │ │ └── unique_blocks_uxsdcxx.capnp ├── libopenfpgashell │ ├── CMakeLists.txt │ ├── src │ │ ├── command.cpp │ │ ├── command.h │ │ ├── command_context.cpp │ │ ├── command_context.h │ │ ├── command_echo.cpp │ │ ├── command_echo.h │ │ ├── command_exit_codes.h │ │ ├── command_fwd.h │ │ ├── command_parser.cpp │ │ ├── command_parser.h │ │ ├── shell.h │ │ ├── shell.tpp │ │ └── shell_fwd.h │ ├── test │ │ ├── test_command_parser.cpp │ │ └── test_shell.cpp │ └── test_script │ │ └── test.openfpga ├── libopenfpgautil │ ├── CMakeLists.txt │ ├── cmake │ │ └── modules │ │ │ └── configure_version.cmake │ └── src │ │ ├── openfpga_bits_parser.cpp │ │ ├── openfpga_bits_parser.h │ │ ├── openfpga_decode.cpp │ │ ├── openfpga_decode.h │ │ ├── openfpga_digest.cpp │ │ ├── openfpga_digest.h │ │ ├── openfpga_pb_parser.cpp │ │ ├── openfpga_pb_parser.h │ │ ├── openfpga_port.cpp │ │ ├── openfpga_port.h │ │ ├── openfpga_port_parser.cpp │ │ ├── openfpga_port_parser.h │ │ ├── openfpga_reserved_words.h │ │ ├── openfpga_scale.cpp │ │ ├── openfpga_scale.h │ │ ├── openfpga_side_manager.cpp │ │ ├── openfpga_side_manager.h │ │ ├── openfpga_tokenizer.cpp │ │ ├── openfpga_tokenizer.h │ │ ├── openfpga_version.cpp.in │ │ ├── openfpga_version.h │ │ ├── openfpga_wildcard_string.cpp │ │ └── openfpga_wildcard_string.h ├── libpcf │ ├── CMakeLists.txt │ ├── example │ │ ├── and2.blif │ │ ├── fabric_io_location.xml │ │ ├── fpga_io_nets.xml │ │ ├── pin_table.xml │ │ └── repack_design_constraint_example.xml │ ├── src │ │ ├── base │ │ │ ├── io_location_map.cpp │ │ │ ├── io_location_map.h │ │ │ ├── io_net_place.cpp │ │ │ ├── io_net_place.h │ │ │ ├── io_pin_table.cpp │ │ │ ├── io_pin_table.h │ │ │ ├── io_pin_table_fwd.h │ │ │ ├── pcf2place.cpp │ │ │ ├── pcf2place.h │ │ │ ├── pcf_data.cpp │ │ │ ├── pcf_data.h │ │ │ ├── pcf_data_fwd.h │ │ │ ├── pin_constraints.cpp │ │ │ ├── pin_constraints.h │ │ │ ├── pin_constraints_fwd.h │ │ │ ├── repack_design_constraints.cpp │ │ │ ├── repack_design_constraints.h │ │ │ └── repack_design_constraints_fwd.h │ │ └── io │ │ │ ├── blif_head_reader.cpp │ │ │ ├── blif_head_reader.h │ │ │ ├── pcf_reader.cpp │ │ │ ├── pcf_reader.h │ │ │ ├── pcf_writer.cpp │ │ │ ├── pcf_writer.h │ │ │ ├── rapidcsv.h │ │ │ ├── read_csv_io_pin_table.cpp │ │ │ ├── read_csv_io_pin_table.h │ │ │ ├── read_xml_io_location_map.cpp │ │ │ ├── read_xml_io_location_map.h │ │ │ ├── read_xml_pin_constraints.cpp │ │ │ ├── read_xml_pin_constraints.h │ │ │ ├── read_xml_repack_design_constraints.cpp │ │ │ ├── read_xml_repack_design_constraints.h │ │ │ ├── write_csv_io_pin_table.cpp │ │ │ ├── write_csv_io_pin_table.h │ │ │ ├── write_xml_pin_constraints.cpp │ │ │ ├── write_xml_pin_constraints.h │ │ │ ├── write_xml_repack_design_constraints.cpp │ │ │ └── write_xml_repack_design_constraints.h │ └── test │ │ ├── test_blif_head_reader.cpp │ │ ├── test_csv_io_pin_table.cpp │ │ ├── test_pcf.cpp │ │ ├── test_pcf2place.cpp │ │ ├── test_repack_design_constraints.cpp │ │ ├── test_xml_io_location_map.cpp │ │ └── test_xml_pcf.cpp └── libtileconfig │ ├── CMakeLists.txt │ ├── example │ └── tile_config_example.xml │ ├── src │ ├── base │ │ ├── tile_config.cpp │ │ └── tile_config.h │ └── io │ │ ├── read_xml_tile_config.cpp │ │ ├── read_xml_tile_config.h │ │ ├── tile_config_xml_constants.h │ │ ├── write_xml_tile_config.cpp │ │ └── write_xml_tile_config.h │ └── test │ └── xml_io_tile_config.cpp ├── openfpga.sh ├── openfpga ├── CMakeLists.txt └── src │ ├── annotation │ ├── annotate_bitstream_setting.cpp │ ├── annotate_bitstream_setting.h │ ├── annotate_clustering.cpp │ ├── annotate_clustering.h │ ├── annotate_pb_graph.cpp │ ├── annotate_pb_graph.h │ ├── annotate_pb_types.cpp │ ├── annotate_pb_types.h │ ├── annotate_physical_tiles.cpp │ ├── annotate_physical_tiles.h │ ├── annotate_placement.cpp │ ├── annotate_placement.h │ ├── annotate_rr_graph.cpp │ ├── annotate_rr_graph.h │ ├── annotate_simulation_setting.cpp │ ├── annotate_simulation_setting.h │ ├── append_clock_rr_graph.cpp │ ├── append_clock_rr_graph.h │ ├── check_netlist_naming_conflict.cpp │ ├── check_netlist_naming_conflict.h │ ├── check_netlist_naming_conflict_template.h │ ├── check_pb_graph_annotation.cpp │ ├── check_pb_graph_annotation.h │ ├── check_pb_type_annotation.cpp │ ├── check_pb_type_annotation.h │ ├── device_rr_gsb.cpp │ ├── device_rr_gsb.h │ ├── fabric_tile.cpp │ ├── fabric_tile.h │ ├── fabric_tile_fwd.h │ ├── openfpga_annotate_routing.cpp │ ├── openfpga_annotate_routing.h │ ├── read_unique_blocks_bin.cpp │ ├── read_unique_blocks_bin.h │ ├── read_unique_blocks_xml.cpp │ ├── read_unique_blocks_xml.h │ ├── route_clock_rr_graph.cpp │ ├── route_clock_rr_graph.h │ ├── rr_gsb_writer_option.cpp │ ├── rr_gsb_writer_option.h │ ├── vpr_bitstream_annotation.cpp │ ├── vpr_bitstream_annotation.h │ ├── vpr_clustering_annotation.cpp │ ├── vpr_clustering_annotation.h │ ├── vpr_device_annotation.cpp │ ├── vpr_device_annotation.h │ ├── vpr_netlist_annotation.cpp │ ├── vpr_netlist_annotation.h │ ├── vpr_placement_annotation.cpp │ ├── vpr_placement_annotation.h │ ├── vpr_routing_annotation.cpp │ ├── vpr_routing_annotation.h │ ├── write_unique_blocks_bin.cpp │ ├── write_unique_blocks_bin.h │ ├── write_unique_blocks_xml.cpp │ ├── write_unique_blocks_xml.h │ ├── write_xml_device_rr_gsb.cpp │ └── write_xml_device_rr_gsb.h │ ├── base │ ├── basic_command.cpp │ ├── basic_command.h │ ├── io_map.cpp │ ├── io_map.h │ ├── io_map_fwd.h │ ├── netlist_manager.cpp │ ├── netlist_manager.h │ ├── netlist_manager_fwd.h │ ├── openfpga_basic.cpp │ ├── openfpga_basic.h │ ├── openfpga_bitstream_command.cpp │ ├── openfpga_bitstream_command.h │ ├── openfpga_bitstream_command_template.h │ ├── openfpga_bitstream_template.h │ ├── openfpga_build_fabric_template.h │ ├── openfpga_context.h │ ├── openfpga_flow_manager.cpp │ ├── openfpga_flow_manager.h │ ├── openfpga_interconnect_types.h │ ├── openfpga_link_arch_template.h │ ├── openfpga_lut_truth_table_fixup.cpp │ ├── openfpga_lut_truth_table_fixup.h │ ├── openfpga_lut_truth_table_fixup_template.h │ ├── openfpga_naming.cpp │ ├── openfpga_naming.h │ ├── openfpga_pb_pin_fixup.cpp │ ├── openfpga_pb_pin_fixup.h │ ├── openfpga_pb_pin_fixup_template.h │ ├── openfpga_pcf2place_template.h │ ├── openfpga_read_arch_template.h │ ├── openfpga_repack_template.h │ ├── openfpga_sdc_command.cpp │ ├── openfpga_sdc_command.h │ ├── openfpga_sdc_command_template.h │ ├── openfpga_sdc_template.h │ ├── openfpga_setup_command.cpp │ ├── openfpga_setup_command.h │ ├── openfpga_setup_command_template.h │ ├── openfpga_shell.cpp │ ├── openfpga_shell.h │ ├── openfpga_spice_command.cpp │ ├── openfpga_spice_command.h │ ├── openfpga_spice_command_template.h │ ├── openfpga_spice_template.h │ ├── openfpga_title.cpp │ ├── openfpga_title.h │ ├── openfpga_verilog_command.cpp │ ├── openfpga_verilog_command.h │ ├── openfpga_verilog_command_template.h │ ├── openfpga_verilog_template.h │ └── openfpga_write_gsb_template.h │ ├── ctag_src.sh │ ├── fabric │ ├── build_decoder_modules.cpp │ ├── build_decoder_modules.h │ ├── build_device_module.cpp │ ├── build_device_module.h │ ├── build_essential_modules.cpp │ ├── build_essential_modules.h │ ├── build_fabric_global_port_info.cpp │ ├── build_fabric_global_port_info.h │ ├── build_fabric_io_location_map.cpp │ ├── build_fabric_io_location_map.h │ ├── build_fabric_tile.cpp │ ├── build_fabric_tile.h │ ├── build_fpga_core_wrapper_module.cpp │ ├── build_fpga_core_wrapper_module.h │ ├── build_grid_module_duplicated_pins.cpp │ ├── build_grid_module_duplicated_pins.h │ ├── build_grid_module_utils.cpp │ ├── build_grid_module_utils.h │ ├── build_grid_modules.cpp │ ├── build_grid_modules.h │ ├── build_lut_modules.cpp │ ├── build_lut_modules.h │ ├── build_memory_modules.cpp │ ├── build_memory_modules.h │ ├── build_module_graph_utils.cpp │ ├── build_module_graph_utils.h │ ├── build_mux_modules.cpp │ ├── build_mux_modules.h │ ├── build_routing_module_utils.cpp │ ├── build_routing_module_utils.h │ ├── build_routing_modules.cpp │ ├── build_routing_modules.h │ ├── build_tile_modules.cpp │ ├── build_tile_modules.h │ ├── build_top_module.cpp │ ├── build_top_module.h │ ├── build_top_module_child_fine_grained_instance.cpp │ ├── build_top_module_child_fine_grained_instance.h │ ├── build_top_module_child_tile_instance.cpp │ ├── build_top_module_child_tile_instance.h │ ├── build_top_module_connection.cpp │ ├── build_top_module_connection.h │ ├── build_top_module_directs.cpp │ ├── build_top_module_directs.h │ ├── build_top_module_memory.cpp │ ├── build_top_module_memory.h │ ├── build_top_module_memory_bank.cpp │ ├── build_top_module_memory_bank.h │ ├── build_top_module_memory_utils.h │ ├── build_top_module_utils.cpp │ ├── build_top_module_utils.h │ ├── build_wire_modules.cpp │ ├── build_wire_modules.h │ ├── fabric_global_port_info.cpp │ ├── fabric_global_port_info.h │ ├── fabric_global_port_info_fwd.h │ ├── fabric_hierarchy_writer.cpp │ ├── fabric_hierarchy_writer.h │ ├── fabric_key_writer.cpp │ ├── fabric_key_writer.h │ ├── fabric_pin_physical_location_xml_constants.h │ ├── memory_bank_shift_register_banks.cpp │ ├── memory_bank_shift_register_banks.h │ ├── module_manager.cpp │ ├── module_manager.h │ ├── module_manager_fwd.h │ ├── rename_modules.cpp │ ├── rename_modules.h │ ├── write_xml_fabric_pin_physical_location.cpp │ └── write_xml_fabric_pin_physical_location.h │ ├── fpga_bitstream │ ├── bitstream_writer_options.cpp │ ├── bitstream_writer_options.h │ ├── build_device_bitstream.cpp │ ├── build_device_bitstream.h │ ├── build_fabric_bitstream.cpp │ ├── build_fabric_bitstream.h │ ├── build_fabric_bitstream_memory_bank.cpp │ ├── build_fabric_bitstream_memory_bank.h │ ├── build_grid_bitstream.cpp │ ├── build_grid_bitstream.h │ ├── build_io_mapping_info.cpp │ ├── build_io_mapping_info.h │ ├── build_mux_bitstream.cpp │ ├── build_mux_bitstream.h │ ├── build_routing_bitstream.cpp │ ├── build_routing_bitstream.h │ ├── extract_device_non_fabric_bitstream.cpp │ ├── extract_device_non_fabric_bitstream.h │ ├── fabric_bitstream.cpp │ ├── fabric_bitstream.h │ ├── fabric_bitstream_fwd.h │ ├── fast_configuration.cpp │ ├── fast_configuration.h │ ├── memory_bank_flatten_fabric_bitstream.cpp │ ├── memory_bank_flatten_fabric_bitstream.h │ ├── memory_bank_shift_register_fabric_bitstream.cpp │ ├── memory_bank_shift_register_fabric_bitstream.h │ ├── memory_bank_shift_register_fabric_bitstream_fwd.h │ ├── mux_bitstream_constants.h │ ├── overwrite_bitstream.cpp │ ├── overwrite_bitstream.h │ ├── report_bitstream_distribution.cpp │ ├── report_bitstream_distribution.h │ ├── report_fabric_bitstream_distribution.cpp │ ├── report_fabric_bitstream_distribution.h │ ├── write_text_fabric_bitstream.cpp │ ├── write_text_fabric_bitstream.h │ ├── write_xml_fabric_bitstream.cpp │ ├── write_xml_fabric_bitstream.h │ ├── write_xml_io_mapping.cpp │ └── write_xml_io_mapping.h │ ├── fpga_sdc │ ├── analysis_sdc_grid_writer.cpp │ ├── analysis_sdc_grid_writer.h │ ├── analysis_sdc_option.cpp │ ├── analysis_sdc_option.h │ ├── analysis_sdc_routing_writer.cpp │ ├── analysis_sdc_routing_writer.h │ ├── analysis_sdc_writer.cpp │ ├── analysis_sdc_writer.h │ ├── analysis_sdc_writer_utils.cpp │ ├── analysis_sdc_writer_utils.h │ ├── configuration_chain_sdc_writer.cpp │ ├── configuration_chain_sdc_writer.h │ ├── configure_port_sdc_writer.cpp │ ├── configure_port_sdc_writer.h │ ├── pnr_sdc_global_port.cpp │ ├── pnr_sdc_global_port.h │ ├── pnr_sdc_grid_writer.cpp │ ├── pnr_sdc_grid_writer.h │ ├── pnr_sdc_option.cpp │ ├── pnr_sdc_option.h │ ├── pnr_sdc_routing_writer.cpp │ ├── pnr_sdc_routing_writer.h │ ├── pnr_sdc_writer.cpp │ ├── pnr_sdc_writer.h │ ├── sdc_hierarchy_writer.cpp │ ├── sdc_hierarchy_writer.h │ ├── sdc_memory_utils.cpp │ ├── sdc_memory_utils.h │ ├── sdc_mux_utils.cpp │ ├── sdc_mux_utils.h │ ├── sdc_writer_naming.h │ ├── sdc_writer_utils.cpp │ └── sdc_writer_utils.h │ ├── fpga_spice │ ├── fabric_spice_options.cpp │ ├── fabric_spice_options.h │ ├── spice_api.cpp │ ├── spice_api.h │ ├── spice_auxiliary_netlists.cpp │ ├── spice_auxiliary_netlists.h │ ├── spice_buffer.cpp │ ├── spice_buffer.h │ ├── spice_constants.h │ ├── spice_essential_gates.cpp │ ├── spice_essential_gates.h │ ├── spice_grid.cpp │ ├── spice_grid.h │ ├── spice_logic_gate.cpp │ ├── spice_logic_gate.h │ ├── spice_lut.cpp │ ├── spice_lut.h │ ├── spice_memory.cpp │ ├── spice_memory.h │ ├── spice_mux.cpp │ ├── spice_mux.h │ ├── spice_passgate.cpp │ ├── spice_passgate.h │ ├── spice_routing.cpp │ ├── spice_routing.h │ ├── spice_subckt_writer.cpp │ ├── spice_subckt_writer.h │ ├── spice_submodule.cpp │ ├── spice_submodule.h │ ├── spice_top_module.cpp │ ├── spice_top_module.h │ ├── spice_transistor_wrapper.cpp │ ├── spice_transistor_wrapper.h │ ├── spice_wire.cpp │ ├── spice_wire.h │ ├── spice_writer_utils.cpp │ └── spice_writer_utils.h │ ├── fpga_verilog │ ├── fabric_verilog_options.cpp │ ├── fabric_verilog_options.h │ ├── verilog_api.cpp │ ├── verilog_api.h │ ├── verilog_auxiliary_netlists.cpp │ ├── verilog_auxiliary_netlists.h │ ├── verilog_constants.h │ ├── verilog_decoders.cpp │ ├── verilog_decoders.h │ ├── verilog_essential_gates.cpp │ ├── verilog_essential_gates.h │ ├── verilog_formal_random_top_testbench.cpp │ ├── verilog_formal_random_top_testbench.h │ ├── verilog_grid.cpp │ ├── verilog_grid.h │ ├── verilog_lut.cpp │ ├── verilog_lut.h │ ├── verilog_memory.cpp │ ├── verilog_memory.h │ ├── verilog_mock_fpga_wrapper.cpp │ ├── verilog_mock_fpga_wrapper.h │ ├── verilog_module_writer.cpp │ ├── verilog_module_writer.h │ ├── verilog_mux.cpp │ ├── verilog_mux.h │ ├── verilog_port_types.h │ ├── verilog_preconfig_top_module.cpp │ ├── verilog_preconfig_top_module.h │ ├── verilog_preconfig_top_module_utils.cpp │ ├── verilog_preconfig_top_module_utils.h │ ├── verilog_routing.cpp │ ├── verilog_routing.h │ ├── verilog_shift_register_banks.cpp │ ├── verilog_shift_register_banks.h │ ├── verilog_simulation_info_writer.cpp │ ├── verilog_simulation_info_writer.h │ ├── verilog_submodule.cpp │ ├── verilog_submodule.h │ ├── verilog_submodule_utils.cpp │ ├── verilog_submodule_utils.h │ ├── verilog_template_testbench.cpp │ ├── verilog_template_testbench.h │ ├── verilog_testbench_io_connection.cpp │ ├── verilog_testbench_io_connection.h │ ├── verilog_testbench_options.cpp │ ├── verilog_testbench_options.h │ ├── verilog_testbench_utils.cpp │ ├── verilog_testbench_utils.h │ ├── verilog_tile.cpp │ ├── verilog_tile.h │ ├── verilog_top_module.cpp │ ├── verilog_top_module.h │ ├── verilog_top_testbench.cpp │ ├── verilog_top_testbench.h │ ├── verilog_top_testbench_constants.h │ ├── verilog_top_testbench_memory_bank.cpp │ ├── verilog_top_testbench_memory_bank.h │ ├── verilog_wire.cpp │ ├── verilog_wire.h │ ├── verilog_writer_utils.cpp │ └── verilog_writer_utils.h │ ├── main.cpp │ ├── mux_lib │ ├── decoder_library.cpp │ ├── decoder_library.h │ ├── decoder_library_fwd.h │ ├── mux_graph.cpp │ ├── mux_graph.h │ ├── mux_graph_fwd.h │ ├── mux_library.cpp │ ├── mux_library.h │ ├── mux_library_builder.cpp │ ├── mux_library_builder.h │ └── mux_library_fwd.h │ ├── openfpga_shell.i │ ├── repack │ ├── build_physical_lb_rr_graph.cpp │ ├── build_physical_lb_rr_graph.h │ ├── build_physical_truth_table.cpp │ ├── build_physical_truth_table.h │ ├── check_lb_rr_graph.cpp │ ├── check_lb_rr_graph.h │ ├── lb_router.cpp │ ├── lb_router.h │ ├── lb_router_utils.cpp │ ├── lb_router_utils.h │ ├── lb_rr_graph.cpp │ ├── lb_rr_graph.h │ ├── lb_rr_graph_fwd.h │ ├── lb_rr_graph_utils.cpp │ ├── lb_rr_graph_utils.h │ ├── physical_pb.cpp │ ├── physical_pb.h │ ├── physical_pb_fwd.h │ ├── repack.cpp │ ├── repack.h │ ├── repack_option.cpp │ └── repack_option.h │ ├── tile_direct │ ├── build_tile_direct.cpp │ ├── build_tile_direct.h │ ├── tile_direct.cpp │ ├── tile_direct.h │ └── tile_direct_fwd.h │ ├── utils │ ├── check_config_protocol.cpp │ ├── check_config_protocol.h │ ├── check_tile_annotation.cpp │ ├── check_tile_annotation.h │ ├── circuit_library_utils.cpp │ ├── circuit_library_utils.h │ ├── decoder_library_utils.cpp │ ├── decoder_library_utils.h │ ├── device_rr_gsb_utils.cpp │ ├── device_rr_gsb_utils.h │ ├── fabric_bitstream_utils.cpp │ ├── fabric_bitstream_utils.h │ ├── fabric_global_port_info_utils.cpp │ ├── fabric_global_port_info_utils.h │ ├── lut_utils.cpp │ ├── lut_utils.h │ ├── memory_bank_utils.cpp │ ├── memory_bank_utils.h │ ├── memory_utils.cpp │ ├── memory_utils.h │ ├── module_manager_memory_utils.cpp │ ├── module_manager_memory_utils.h │ ├── module_manager_utils.cpp │ ├── module_manager_utils.h │ ├── mux_utils.cpp │ ├── mux_utils.h │ ├── openfpga_atom_netlist_utils.cpp │ ├── openfpga_atom_netlist_utils.h │ ├── openfpga_clustered_netlist_utils.cpp │ ├── openfpga_clustered_netlist_utils.h │ ├── openfpga_device_grid_utils.cpp │ ├── openfpga_device_grid_utils.h │ ├── openfpga_physical_tile_utils.cpp │ ├── openfpga_physical_tile_utils.h │ ├── openfpga_rr_graph_support.cpp │ ├── openfpga_rr_graph_support.h │ ├── pb_graph_utils.cpp │ ├── pb_graph_utils.h │ ├── pb_type_utils.cpp │ ├── pb_type_utils.h │ ├── physical_pb_utils.cpp │ ├── physical_pb_utils.h │ ├── report_reference.cpp │ ├── report_reference.h │ ├── rr_gsb_utils.cpp │ ├── rr_gsb_utils.h │ ├── simulation_utils.cpp │ └── simulation_utils.h │ └── vpr_wrapper │ ├── vpr_command.cpp │ ├── vpr_command.h │ ├── vpr_main.cpp │ └── vpr_main.h ├── openfpga_flow ├── .gitignore ├── arch_bitstreams │ ├── and2_k4_N4_tileable_40nm.place │ └── and2_k4_N4_tileable_40nm_bitstream.xml ├── benchmarks │ ├── MCNC_Verilog │ │ ├── alu4 │ │ │ └── alu4.v │ │ ├── apex2 │ │ │ └── apex2.v │ │ ├── apex4 │ │ │ └── apex4.v │ │ ├── bigkey │ │ │ └── bigkey.v │ │ ├── clma │ │ │ └── clma.v │ │ ├── des │ │ │ └── des.v │ │ ├── diffeq │ │ │ └── diffeq.v │ │ ├── dsip │ │ │ └── dsip.v │ │ ├── elliptic │ │ │ └── elliptic.v │ │ ├── ex1010 │ │ │ └── ex1010.v │ │ ├── ex5p │ │ │ └── ex5p.v │ │ ├── frisc │ │ │ └── frisc.v │ │ ├── misex3 │ │ │ └── misex3.v │ │ ├── pdc │ │ │ └── pdc.v │ │ ├── s298 │ │ │ └── s298.v │ │ ├── s38417 │ │ │ └── s38417.v │ │ ├── s38584 │ │ │ └── s38584.v │ │ ├── seq │ │ │ └── seq.v │ │ ├── spla │ │ │ └── spla.v │ │ └── tseng │ │ │ └── tseng.v │ ├── iwls2005 │ │ ├── ac97_ctrl │ │ │ └── rtl │ │ │ │ ├── ac97_cra.v │ │ │ │ ├── ac97_defines.v │ │ │ │ ├── ac97_dma_if.v │ │ │ │ ├── ac97_dma_req.v │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ ├── ac97_int.v │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ ├── ac97_prc.v │ │ │ │ ├── ac97_rf.v │ │ │ │ ├── ac97_rst.v │ │ │ │ ├── ac97_sin.v │ │ │ │ ├── ac97_soc.v │ │ │ │ ├── ac97_sout.v │ │ │ │ ├── ac97_top.v │ │ │ │ └── ac97_wb_if.v │ │ ├── aes_core │ │ │ └── rtl │ │ │ │ ├── aes_cipher_top.v │ │ │ │ ├── aes_inv_cipher_top.v │ │ │ │ ├── aes_inv_sbox.v │ │ │ │ ├── aes_key_expand_128.v │ │ │ │ ├── aes_rcon.v │ │ │ │ ├── aes_sbox.v │ │ │ │ └── timescale.v │ │ ├── des │ │ │ ├── README.txt │ │ │ ├── area_opt │ │ │ │ └── rtl │ │ │ │ │ ├── crp.v │ │ │ │ │ ├── des.v │ │ │ │ │ ├── des3.v │ │ │ │ │ ├── key_sel.v │ │ │ │ │ ├── key_sel3.v │ │ │ │ │ ├── sbox1.v │ │ │ │ │ ├── sbox2.v │ │ │ │ │ ├── sbox3.v │ │ │ │ │ ├── sbox4.v │ │ │ │ │ ├── sbox5.v │ │ │ │ │ ├── sbox6.v │ │ │ │ │ ├── sbox7.v │ │ │ │ │ └── sbox8.v │ │ │ └── perf_opt │ │ │ │ └── rtl │ │ │ │ ├── crp.v │ │ │ │ ├── des.v │ │ │ │ ├── des3.v │ │ │ │ ├── key_sel.v │ │ │ │ ├── key_sel3.v │ │ │ │ ├── sbox1.v │ │ │ │ ├── sbox2.v │ │ │ │ ├── sbox3.v │ │ │ │ ├── sbox4.v │ │ │ │ ├── sbox5.v │ │ │ │ ├── sbox6.v │ │ │ │ ├── sbox7.v │ │ │ │ └── sbox8.v │ │ ├── ethernet │ │ │ ├── rtl │ │ │ │ ├── eth_clockgen.v │ │ │ │ ├── eth_crc.v │ │ │ │ ├── eth_defines.v │ │ │ │ ├── eth_fifo.v │ │ │ │ ├── eth_maccontrol.v │ │ │ │ ├── eth_macstatus.v │ │ │ │ ├── eth_miim.v │ │ │ │ ├── eth_outputcontrol.v │ │ │ │ ├── eth_random.v │ │ │ │ ├── eth_receivecontrol.v │ │ │ │ ├── eth_register.v │ │ │ │ ├── eth_registers.v │ │ │ │ ├── eth_rxaddrcheck.v │ │ │ │ ├── eth_rxcounters.v │ │ │ │ ├── eth_rxethmac.v │ │ │ │ ├── eth_rxstatem.v │ │ │ │ ├── eth_shiftreg.v │ │ │ │ ├── eth_spram_256x32.v │ │ │ │ ├── eth_top.v │ │ │ │ ├── eth_transmitcontrol.v │ │ │ │ ├── eth_txcounters.v │ │ │ │ ├── eth_txethmac.v │ │ │ │ ├── eth_txstatem.v │ │ │ │ ├── eth_wishbone.v │ │ │ │ ├── timescale.v │ │ │ │ └── xilinx_dist_ram_16x32.v │ │ │ └── testbench │ │ │ │ └── eth_cop.v │ │ ├── fpu │ │ │ └── rtl │ │ │ │ ├── except.v │ │ │ │ ├── fpu.v │ │ │ │ ├── post_norm.v │ │ │ │ ├── pre_norm.v │ │ │ │ ├── pre_norm_fmul.v │ │ │ │ └── primitives.v │ │ ├── i2c │ │ │ └── rtl │ │ │ │ ├── i2c_master_bit_ctrl.v │ │ │ │ ├── i2c_master_byte_ctrl.v │ │ │ │ ├── i2c_master_defines.v │ │ │ │ ├── i2c_master_top.v │ │ │ │ └── timescale.v │ │ ├── mem_ctrl │ │ │ └── rtl │ │ │ │ ├── mc_adr_sel.v │ │ │ │ ├── mc_cs_rf.v │ │ │ │ ├── mc_defines.v │ │ │ │ ├── mc_dp.v │ │ │ │ ├── mc_incn_r.v │ │ │ │ ├── mc_mem_if.v │ │ │ │ ├── mc_obct.v │ │ │ │ ├── mc_obct_top.v │ │ │ │ ├── mc_rd_fifo.v │ │ │ │ ├── mc_refresh.v │ │ │ │ ├── mc_rf.v │ │ │ │ ├── mc_timing.v │ │ │ │ ├── mc_top.v │ │ │ │ └── mc_wb_if.v │ │ ├── pci │ │ │ └── rtl │ │ │ │ ├── bus_commands.v │ │ │ │ ├── pci_async_reset_flop.v │ │ │ │ ├── pci_bridge32.v │ │ │ │ ├── pci_cbe_en_crit.v │ │ │ │ ├── pci_conf_cyc_addr_dec.v │ │ │ │ ├── pci_conf_space.v │ │ │ │ ├── pci_constants.v │ │ │ │ ├── pci_cur_out_reg.v │ │ │ │ ├── pci_delayed_sync.v │ │ │ │ ├── pci_delayed_write_reg.v │ │ │ │ ├── pci_frame_crit.v │ │ │ │ ├── pci_frame_en_crit.v │ │ │ │ ├── pci_frame_load_crit.v │ │ │ │ ├── pci_in_reg.v │ │ │ │ ├── pci_io_mux.v │ │ │ │ ├── pci_io_mux_ad_en_crit.v │ │ │ │ ├── pci_io_mux_ad_load_crit.v │ │ │ │ ├── pci_irdy_out_crit.v │ │ │ │ ├── pci_mas_ad_en_crit.v │ │ │ │ ├── pci_mas_ad_load_crit.v │ │ │ │ ├── pci_mas_ch_state_crit.v │ │ │ │ ├── pci_master32_sm.v │ │ │ │ ├── pci_master32_sm_if.v │ │ │ │ ├── pci_out_reg.v │ │ │ │ ├── pci_par_crit.v │ │ │ │ ├── pci_parity_check.v │ │ │ │ ├── pci_pci_decoder.v │ │ │ │ ├── pci_pci_tpram.v │ │ │ │ ├── pci_pcir_fifo_control.v │ │ │ │ ├── pci_pciw_fifo_control.v │ │ │ │ ├── pci_pciw_pcir_fifos.v │ │ │ │ ├── pci_perr_crit.v │ │ │ │ ├── pci_perr_en_crit.v │ │ │ │ ├── pci_ram_16x40d.v │ │ │ │ ├── pci_rst_int.v │ │ │ │ ├── pci_serr_crit.v │ │ │ │ ├── pci_serr_en_crit.v │ │ │ │ ├── pci_spoci_ctrl.v │ │ │ │ ├── pci_sync_module.v │ │ │ │ ├── pci_synchronizer_flop.v │ │ │ │ ├── pci_target32_clk_en.v │ │ │ │ ├── pci_target32_devs_crit.v │ │ │ │ ├── pci_target32_interface.v │ │ │ │ ├── pci_target32_sm.v │ │ │ │ ├── pci_target32_stop_crit.v │ │ │ │ ├── pci_target32_trdy_crit.v │ │ │ │ ├── pci_target_unit.v │ │ │ │ ├── pci_user_constants.v │ │ │ │ ├── pci_wb_addr_mux.v │ │ │ │ ├── pci_wb_decoder.v │ │ │ │ ├── pci_wb_master.v │ │ │ │ ├── pci_wb_slave.v │ │ │ │ ├── pci_wb_slave_unit.v │ │ │ │ ├── pci_wb_tpram.v │ │ │ │ ├── pci_wbr_fifo_control.v │ │ │ │ ├── pci_wbs_wbb3_2_wbb2.v │ │ │ │ ├── pci_wbw_fifo_control.v │ │ │ │ ├── pci_wbw_wbr_fifos.v │ │ │ │ └── timescale.v │ │ ├── sasc │ │ │ └── rtl │ │ │ │ ├── sasc_brg.v │ │ │ │ ├── sasc_fifo4.v │ │ │ │ ├── sasc_top.v │ │ │ │ └── timescale.v │ │ ├── simple_spi │ │ │ └── rtl │ │ │ │ ├── fifo4.v │ │ │ │ └── simple_spi_top.v │ │ ├── spi │ │ │ └── rtl │ │ │ │ ├── spi_clgen.v │ │ │ │ ├── spi_defines.v │ │ │ │ ├── spi_shift.v │ │ │ │ ├── spi_top.v │ │ │ │ └── timescale.v │ │ ├── ss_pcm │ │ │ └── rtl │ │ │ │ ├── pcm_slv_top.v │ │ │ │ └── timescale.v │ │ ├── steppermotordrive │ │ │ └── rtl │ │ │ │ └── StepperMotorDrive.vhd │ │ ├── systemcaes │ │ │ └── rtl │ │ │ │ ├── aes.v │ │ │ │ ├── byte_mixcolum.v │ │ │ │ ├── keysched.v │ │ │ │ ├── mixcolum.v │ │ │ │ ├── sbox.v │ │ │ │ ├── subbytes.v │ │ │ │ ├── timescale.v │ │ │ │ └── word_mixcolum.v │ │ ├── systemcdes │ │ │ └── rtl │ │ │ │ ├── des.v │ │ │ │ ├── desround.v │ │ │ │ ├── key_gen.v │ │ │ │ ├── s1.v │ │ │ │ ├── s2.v │ │ │ │ ├── s3.v │ │ │ │ ├── s4.v │ │ │ │ ├── s5.v │ │ │ │ ├── s6.v │ │ │ │ ├── s7.v │ │ │ │ └── s8.v │ │ ├── tv80 │ │ │ └── rtl │ │ │ │ ├── tv80_alu.v │ │ │ │ ├── tv80_core.v │ │ │ │ ├── tv80_mcode.v │ │ │ │ ├── tv80_reg.v │ │ │ │ └── tv80s.v │ │ ├── usb_funct │ │ │ └── rtl │ │ │ │ ├── usbf_crc16.v │ │ │ │ ├── usbf_crc5.v │ │ │ │ ├── usbf_defines.v │ │ │ │ ├── usbf_ep_rf.v │ │ │ │ ├── usbf_ep_rf_dummy.v │ │ │ │ ├── usbf_idma.v │ │ │ │ ├── usbf_mem_arb.v │ │ │ │ ├── usbf_pa.v │ │ │ │ ├── usbf_pd.v │ │ │ │ ├── usbf_pe.v │ │ │ │ ├── usbf_pl.v │ │ │ │ ├── usbf_rf.v │ │ │ │ ├── usbf_top.v │ │ │ │ ├── usbf_utmi_if.v │ │ │ │ ├── usbf_utmi_ls.v │ │ │ │ └── usbf_wb.v │ │ ├── usb_phy │ │ │ └── rtl │ │ │ │ ├── timescale.v │ │ │ │ ├── usb_phy.v │ │ │ │ ├── usb_rx_phy.v │ │ │ │ └── usb_tx_phy.v │ │ ├── vga_lcd │ │ │ └── rtl │ │ │ │ ├── generic_dpram.v │ │ │ │ ├── generic_spram.v │ │ │ │ ├── timescale.v │ │ │ │ ├── vga_clkgen.v │ │ │ │ ├── vga_colproc.v │ │ │ │ ├── vga_csm_pb.v │ │ │ │ ├── vga_cur_cregs.v │ │ │ │ ├── vga_curproc.v │ │ │ │ ├── vga_defines.v │ │ │ │ ├── vga_enh_top.v │ │ │ │ ├── vga_fifo.v │ │ │ │ ├── vga_fifo_dc.v │ │ │ │ ├── vga_pgen.v │ │ │ │ ├── vga_tgen.v │ │ │ │ ├── vga_vtim.v │ │ │ │ ├── vga_wb_master.v │ │ │ │ └── vga_wb_slave.v │ │ ├── wb_conmax │ │ │ └── rtl │ │ │ │ ├── wb_conmax_arb.v │ │ │ │ ├── wb_conmax_defines.v │ │ │ │ ├── wb_conmax_master_if.v │ │ │ │ ├── wb_conmax_msel.v │ │ │ │ ├── wb_conmax_pri_dec.v │ │ │ │ ├── wb_conmax_pri_enc.v │ │ │ │ ├── wb_conmax_rf.v │ │ │ │ ├── wb_conmax_slave_if.v │ │ │ │ └── wb_conmax_top.v │ │ └── wb_dma │ │ │ └── rtl │ │ │ ├── wb_dma_ch_arb.v │ │ │ ├── wb_dma_ch_pri_enc.v │ │ │ ├── wb_dma_ch_rf.v │ │ │ ├── wb_dma_ch_sel.v │ │ │ ├── wb_dma_de.v │ │ │ ├── wb_dma_defines.v │ │ │ ├── wb_dma_inc30r.v │ │ │ ├── wb_dma_pri_enc_sub.v │ │ │ ├── wb_dma_rf.v │ │ │ ├── wb_dma_top.v │ │ │ ├── wb_dma_wb_if.v │ │ │ ├── wb_dma_wb_mast.v │ │ │ └── wb_dma_wb_slv.v │ ├── mcnc_big20 │ │ ├── alu4 │ │ │ ├── alu4.act │ │ │ ├── alu4.blif │ │ │ └── alu4.v │ │ ├── apex2 │ │ │ ├── apex2.act │ │ │ ├── apex2.blif │ │ │ └── apex2.v │ │ ├── apex4 │ │ │ ├── apex4.act │ │ │ ├── apex4.blif │ │ │ └── apex4.v │ │ ├── bigkey │ │ │ ├── bigkey.act │ │ │ ├── bigkey.blif │ │ │ └── bigkey.v │ │ ├── clma │ │ │ ├── clma.act │ │ │ ├── clma.blif │ │ │ └── clma.v │ │ ├── des │ │ │ ├── des.act │ │ │ ├── des.blif │ │ │ └── des.v │ │ ├── diffeq │ │ │ ├── diffeq.act │ │ │ ├── diffeq.blif │ │ │ └── diffeq.v │ │ ├── dsip │ │ │ ├── dsip.act │ │ │ ├── dsip.blif │ │ │ └── dsip.v │ │ ├── elliptic │ │ │ ├── elliptic.act │ │ │ ├── elliptic.blif │ │ │ └── elliptic.v │ │ ├── ex1010 │ │ │ ├── ex1010.act │ │ │ ├── ex1010.blif │ │ │ └── ex1010.v │ │ ├── ex5p │ │ │ ├── ex5p.act │ │ │ ├── ex5p.blif │ │ │ └── ex5p.v │ │ ├── frisc │ │ │ ├── frisc.act │ │ │ ├── frisc.blif │ │ │ └── frisc.v │ │ ├── misex3 │ │ │ ├── misex3.act │ │ │ ├── misex3.blif │ │ │ └── misex3.v │ │ ├── pdc │ │ │ ├── pdc.act │ │ │ ├── pdc.blif │ │ │ └── pdc.v │ │ ├── s298 │ │ │ ├── s298.act │ │ │ ├── s298.blif │ │ │ └── s298.v │ │ ├── s38417 │ │ │ ├── s38417.act │ │ │ ├── s38417.blif │ │ │ └── s38417.v │ │ ├── s38584 │ │ │ ├── s38584.act │ │ │ ├── s38584.blif │ │ │ └── s38584.v │ │ ├── seq │ │ │ ├── seq.act │ │ │ ├── seq.blif │ │ │ └── seq.v │ │ ├── spla │ │ │ ├── spla.act │ │ │ ├── spla.blif │ │ │ └── spla.v │ │ └── tseng │ │ │ ├── tseng.act │ │ │ ├── tseng.blif │ │ │ └── tseng.v │ ├── micro_benchmark │ │ ├── FIR_filter │ │ │ ├── FIR_filter_firBlock_left_ace_out_debug.act │ │ │ ├── FIR_filter_firBlock_left_debug.blif │ │ │ └── FIR_filter_firBlock_left_output_verilog_debug.v │ │ ├── FSM_three_code │ │ │ ├── FSM_hour.v │ │ │ ├── FSM_minute.v │ │ │ ├── FSM_second.v │ │ │ ├── FSM_three_tb.v │ │ │ └── FSM_top.v │ │ ├── RISC_posedge_clk │ │ │ ├── rtl │ │ │ │ ├── ALU.v │ │ │ │ ├── Controller.v │ │ │ │ ├── IR.v │ │ │ │ ├── Memory.v │ │ │ │ ├── Mux_31.v │ │ │ │ ├── Mux_51.v │ │ │ │ ├── PC.v │ │ │ │ ├── RISC_core_mem_top.v │ │ │ │ ├── RISC_core_top.v │ │ │ │ ├── Reg_1bit.v │ │ │ │ └── Reg_8bit.v │ │ │ └── testbench │ │ │ │ └── RISC_testbench.v │ │ ├── SAPone │ │ │ ├── rtl │ │ │ │ ├── ACC.v │ │ │ │ ├── ADDSUB.v │ │ │ │ ├── BRegister.v │ │ │ │ ├── Controller.v │ │ │ │ ├── IR.v │ │ │ │ ├── MAR.v │ │ │ │ ├── OutputRegister.v │ │ │ │ ├── PC.v │ │ │ │ ├── ROM.v │ │ │ │ └── SAPone.v │ │ │ └── testbench │ │ │ │ └── testSAPone.v │ │ ├── adder │ │ │ ├── adder_16 │ │ │ │ └── adder_16.v │ │ │ ├── adder_4 │ │ │ │ └── adder_4.v │ │ │ ├── adder_6 │ │ │ │ └── adder_6.v │ │ │ └── adder_8 │ │ │ │ ├── adder_8.act │ │ │ │ ├── adder_8.eblif │ │ │ │ ├── adder_8.v │ │ │ │ └── adder_8_out.v │ │ ├── and2 │ │ │ ├── and2.act │ │ │ ├── and2.blif │ │ │ ├── and2.eblif │ │ │ ├── and2.sv │ │ │ ├── and2.v │ │ │ ├── and2_frac_lut4_arith.eblif │ │ │ └── and2_verific.blif │ │ ├── and2_latch │ │ │ ├── and2_latch.act │ │ │ ├── and2_latch.blif │ │ │ ├── and2_latch.sv │ │ │ ├── and2_latch.v │ │ │ └── and2_latch_verific.blif │ │ ├── and2_latch_2clock │ │ │ └── and2_latch_2clock.v │ │ ├── and2_or2 │ │ │ ├── and2_or2.act │ │ │ ├── and2_or2.blif │ │ │ └── and2_or2.v │ │ ├── and2_pipelined │ │ │ ├── and2_pipelined.act │ │ │ ├── and2_pipelined.blif │ │ │ └── and2_pipelined.v │ │ ├── and4 │ │ │ └── and4.v │ │ ├── asyn_spram_4x1 │ │ │ ├── asyn_spram_4x1.act │ │ │ ├── asyn_spram_4x1.blif │ │ │ └── asyn_spram_4x1.v │ │ ├── blinking │ │ │ └── blinking.v │ │ ├── clk_cond │ │ │ └── clk_cond.v │ │ ├── clk_divider │ │ │ └── clk_divider.v │ │ ├── clk_gate │ │ │ ├── clk_gate.blif │ │ │ └── clk_gate.v │ │ ├── clk_on_lut │ │ │ └── clk_on_lut.v │ │ ├── config_loader │ │ │ ├── bitstream_loader.v │ │ │ └── configuration_manager.v │ │ ├── counters │ │ │ ├── counter_128bit_async_reset │ │ │ │ ├── counter.v │ │ │ │ └── counter_tb.v │ │ │ ├── counter_128bit_async_resetb │ │ │ │ ├── counter.v │ │ │ │ └── counter_tb.v │ │ │ ├── counter_4bit_2clock │ │ │ │ ├── counter_4bit_2clock.v │ │ │ │ └── counter_4bit_2clock_tb.v │ │ │ ├── counter_8bit_async_reset │ │ │ │ ├── counter.v │ │ │ │ └── counter_tb.v │ │ │ ├── counter_8bit_async_resetb │ │ │ │ ├── counter.v │ │ │ │ └── counter_tb.v │ │ │ ├── counter_8bit_negedge_async_reset │ │ │ │ ├── counter.v │ │ │ │ └── counter_tb.v │ │ │ └── counter_8bit_sync_reset │ │ │ │ ├── counter.v │ │ │ │ └── counter_tb.v │ │ ├── discrete_dffn │ │ │ ├── discrete_dffn.blif │ │ │ └── discrete_dffn.v │ │ ├── dual_port_ram_16k │ │ │ └── dual_port_ram_16k.v │ │ ├── dual_port_ram_1k │ │ │ └── dual_port_ram_1k.v │ │ ├── fifo │ │ │ └── rtl │ │ │ │ ├── fifo.v │ │ │ │ └── sync_dual_port_ram.v │ │ ├── mac │ │ │ ├── mac_12 │ │ │ │ └── mac_12.v │ │ │ ├── mac_16 │ │ │ │ └── mac_16.v │ │ │ ├── mac_18 │ │ │ │ └── mac_18.v │ │ │ ├── mac_2 │ │ │ │ └── mac_2.v │ │ │ ├── mac_20 │ │ │ │ └── mac_20.v │ │ │ ├── mac_32 │ │ │ │ └── mac_32.v │ │ │ ├── mac_36 │ │ │ │ └── mac_36.v │ │ │ ├── mac_4 │ │ │ │ └── mac_4.v │ │ │ ├── mac_6 │ │ │ │ └── mac_6.v │ │ │ ├── mac_8 │ │ │ │ └── mac_8.v │ │ │ ├── mac_8_9 │ │ │ │ └── mac_8_9.v │ │ │ └── mac_9 │ │ │ │ └── mac_9.v │ │ ├── mult │ │ │ ├── dual_mult8_mix_regin │ │ │ │ └── dual_mult8_mix_regin.v │ │ │ ├── mult16 │ │ │ │ └── mult16.v │ │ │ ├── mult8 │ │ │ │ └── mult8.v │ │ │ ├── mult8_ram8 │ │ │ │ ├── dual_port_ram_1k.v │ │ │ │ └── mult8_ram8.v │ │ │ ├── mult_2_pipelined │ │ │ │ └── mult_2_pipelined.v │ │ │ └── two_mult8_ram32 │ │ │ │ ├── dual_port_ram_16k.v │ │ │ │ └── two_mult8_ram32.v │ │ ├── multi_driver │ │ │ └── multi_driver.v │ │ ├── or2 │ │ │ ├── or2.act │ │ │ ├── or2.blif │ │ │ ├── or2.v │ │ │ ├── or2_load_bitstream.blif │ │ │ └── or2_verific.blif │ │ ├── pipelined_8bit_adder │ │ │ ├── pipelined_8bit_adder.act │ │ │ ├── pipelined_8bit_adder.blif │ │ │ ├── pipelined_8bit_adder.v │ │ │ └── pipelined_8bit_adder_formal_random_top_tb.v │ │ ├── pwm │ │ │ └── pwm_cnt8 │ │ │ │ └── pwm_cnt8.v │ │ ├── routing_test │ │ │ ├── routing_test.act │ │ │ ├── routing_test.blif │ │ │ └── routing_test.v │ │ ├── rst_and_clk_on_lut │ │ │ └── rst_and_clk_on_lut.v │ │ ├── rst_cond │ │ │ └── rst_cond.v │ │ ├── rst_on_lut │ │ │ └── rst_on_lut.v │ │ ├── rst_on_lut_4bit │ │ │ └── rst_on_lut_4bit.v │ │ ├── rst_on_lut_8bit │ │ │ └── rst_on_lut_8bit.v │ │ ├── signal_gen │ │ │ ├── clock_divider.v │ │ │ ├── pulse_generator.v │ │ │ └── reset_generator.v │ │ ├── syn_spram_4x1 │ │ │ ├── syn_spram_4x1.act │ │ │ ├── syn_spram_4x1.blif │ │ │ └── syn_spram_4x1.v │ │ ├── test_mode_low │ │ │ ├── test_mode_low.act │ │ │ ├── test_mode_low.blif │ │ │ └── test_mode_low.v │ │ ├── test_modes │ │ │ ├── k4_N4 │ │ │ │ ├── K4N4_test_modes.act │ │ │ │ ├── K4N4_test_modes.blif │ │ │ │ └── K4N4_test_modes.v │ │ │ └── k6_N10 │ │ │ │ ├── K6N10_test_modes.act │ │ │ │ ├── K6N10_test_modes.blif │ │ │ │ └── K6N10_test_modes.v │ │ └── two_dff_inv_rst │ │ │ ├── two_dff_inv_rst.blif │ │ │ └── two_dff_inv_rst.v │ ├── quicklogic_tests │ │ ├── Simon_bit_serial_top_module │ │ │ └── rtl │ │ │ │ ├── Simon_bit_serial_datapath_FPGA.v │ │ │ │ ├── Simon_bit_serial_key_expansion_FPGA.v │ │ │ │ └── Simon_bit_serial_top_module.v │ │ ├── ULPSH_fabric │ │ │ └── rtl │ │ │ │ └── src │ │ │ │ ├── CM_FIFO_1x.v │ │ │ │ ├── CM_FIFO_autodrain.v │ │ │ │ ├── FFEControlMemory_4k.v │ │ │ │ ├── FFEDataMemoryMux.v │ │ │ │ ├── FFE_ALU.v │ │ │ │ ├── FFE_Control.v │ │ │ │ ├── MicroOpCodesDecode.v │ │ │ │ ├── SMEMemoryMux.v │ │ │ │ ├── SMMemory.v │ │ │ │ ├── SPI_slave.v │ │ │ │ ├── SensorHubDefines.v │ │ │ │ ├── SensorManager.v │ │ │ │ ├── StateMachine.v │ │ │ │ ├── SystemClockControl.v │ │ │ │ ├── TLC.v │ │ │ │ ├── ULPSH_fabric.v │ │ │ │ ├── hard_macros_ql │ │ │ │ ├── Aurora │ │ │ │ │ ├── primitive_macros.v │ │ │ │ │ └── qlprim.v │ │ │ │ ├── clock_buffer_ql.v │ │ │ │ └── dff_pre_clr_ql.v │ │ │ │ ├── ring_osc_adjust.v │ │ │ │ └── ulpsh_rtl_defines.v │ │ ├── bin2bcd │ │ │ ├── bin2bcd.v │ │ │ └── bin2bcd_tb.v │ │ ├── cavlc_top │ │ │ └── rtl │ │ │ │ ├── cavlc_fsm.v │ │ │ │ ├── cavlc_len_gen.v │ │ │ │ ├── cavlc_read_levels.v │ │ │ │ ├── cavlc_read_run_befores.v │ │ │ │ ├── cavlc_read_total_coeffs.v │ │ │ │ ├── cavlc_read_total_zeros.v │ │ │ │ ├── cavlc_top.v │ │ │ │ └── defines.v │ │ ├── cf_fft_256_8 │ │ │ └── rtl │ │ │ │ └── cf_fft_256_8.v │ │ ├── counter │ │ │ ├── counter.v │ │ │ └── counter_tb.v │ │ ├── counter120bitx5 │ │ │ └── rtl │ │ │ │ └── counter_5_120_13.v │ │ ├── counter_16bit │ │ │ └── rtl │ │ │ │ └── counter_16bit.v │ │ ├── dct_mac │ │ │ └── rtl │ │ │ │ ├── dct.v │ │ │ │ ├── dct_cos_table.v │ │ │ │ ├── dct_mac.v │ │ │ │ ├── dct_syn.v │ │ │ │ ├── dctu.v │ │ │ │ ├── dctub.v │ │ │ │ ├── fdct.v │ │ │ │ └── zigzag.v │ │ ├── des_perf │ │ │ └── rtl │ │ │ │ └── des_perf.v │ │ ├── diffeq_f_systemC │ │ │ └── rtl │ │ │ │ └── diffeq2.v │ │ ├── i2c_master_top │ │ │ └── rtl │ │ │ │ ├── StateMachine.v │ │ │ │ ├── i2c_master_bit_ctrl.v │ │ │ │ ├── i2c_master_byte_ctrl.v │ │ │ │ ├── i2c_master_defines.v │ │ │ │ └── i2c_master_top.v │ │ ├── iir │ │ │ └── rtl │ │ │ │ └── iir.v │ │ ├── io_reg │ │ │ ├── io_reg.v │ │ │ └── io_reg_tb.v │ │ ├── io_tc1 │ │ │ └── rtl │ │ │ │ ├── demux.v │ │ │ │ ├── io_tc1.v │ │ │ │ └── mux.v │ │ ├── jpeg_qnr │ │ │ └── rtl │ │ │ │ ├── div_su.v │ │ │ │ ├── div_uu.v │ │ │ │ └── jpeg_qnr.v │ │ ├── multi_enc_decx2x4 │ │ │ └── rtl │ │ │ │ ├── TOP_multi_enc_decx2x4.v │ │ │ │ ├── decoder.v │ │ │ │ ├── encoder.v │ │ │ │ └── topenc_decx2.v │ │ ├── rs_decoder │ │ │ └── rtl │ │ │ │ └── rs_decoder.v │ │ ├── rs_decoder_1 │ │ │ └── rtl │ │ │ │ └── rs_decoder_1.v │ │ ├── sdc_controller │ │ │ └── rtl │ │ │ │ ├── bistable_domain_cross.v │ │ │ │ ├── edge_detect.v │ │ │ │ ├── generic_dpram.v │ │ │ │ ├── generic_fifo_dc_gray.v │ │ │ │ ├── monostable_domain_cross.v │ │ │ │ ├── sd_clock_divider.v │ │ │ │ ├── sd_cmd_master.v │ │ │ │ ├── sd_cmd_serial_host.v │ │ │ │ ├── sd_controller_wb.v │ │ │ │ ├── sd_crc_16.v │ │ │ │ ├── sd_crc_7.v │ │ │ │ ├── sd_data_master.v │ │ │ │ ├── sd_data_serial_host.v │ │ │ │ ├── sd_data_xfer_trig.v │ │ │ │ ├── sd_defines.v │ │ │ │ ├── sd_fifo_filler.v │ │ │ │ └── sdc_controller.v │ │ ├── sha256 │ │ │ └── rtl │ │ │ │ ├── sha1.v │ │ │ │ └── sha256.v │ │ ├── shift_reg_8192 │ │ │ └── rtl │ │ │ │ └── shift_reg_8192.v │ │ ├── simon_bit_serial │ │ │ ├── README.txt │ │ │ ├── rtl │ │ │ │ ├── Simon_bit_serial_datapath_FPGA.v │ │ │ │ ├── Simon_bit_serial_key_expansion_FPGA.v │ │ │ │ └── Simon_bit_serial_top_module_FPGA.v │ │ │ └── testbench │ │ │ │ └── Simon_bit_serial_testbench.v │ │ └── unsigned_mult_80 │ │ │ └── rtl │ │ │ └── unsigned_mult_80.v │ └── vtr_benchmark │ │ ├── LU32PEEng.v │ │ ├── LU64PEEng.v │ │ ├── LU8PEEng.v │ │ ├── arm_core.v │ │ ├── bgm.v │ │ ├── blob_merge.v │ │ ├── boundtop.v │ │ ├── ch_intrinsics.v │ │ ├── diffeq1.v │ │ ├── diffeq2.v │ │ ├── matmul_8x8_fp16.v │ │ ├── mcml.v │ │ ├── mkDelayWorker32B.v │ │ ├── mkPktMerge.v │ │ ├── mkSMAdapter4B.v │ │ ├── or1200.v │ │ ├── raygentop.v │ │ ├── sha.v │ │ ├── spree.v │ │ ├── stereovision0.v │ │ ├── stereovision1.v │ │ ├── stereovision2.v │ │ ├── stereovision3.v │ │ ├── tpu.16x16.int8.v │ │ └── tpu.32x32.int8.v ├── docs │ └── KeyExampleTasks.txt ├── fabric_keys │ ├── k4_N4_1x1_qlbanksr_multi_chain_sample_key.xml │ ├── k4_N4_2x2_multi_region_qlbank_sample_key.xml │ ├── k4_N4_2x2_multi_region_qlbanksr_sample_key.xml │ ├── k4_N4_2x2_multi_region_sample_key.xml │ ├── k4_N4_2x2_qlbank_sample_key.xml │ ├── k4_N4_2x2_sample_key.xml │ └── k4_N4_2x2_sample_subkey.xml ├── misc │ ├── formality_template.tcl │ ├── fpgaflow_default_tool_path.conf │ ├── fpgaflow_default_tool_path_timing.conf │ ├── modelsim_proc.tcl │ ├── modelsim_runsim.tcl │ ├── qlf_yosys.ys │ ├── ys_tmpl_rewrite_flow.ys │ ├── ys_tmpl_yosys_sv_vpr_flow.ys │ ├── ys_tmpl_yosys_vpr_adder_dsp_flow.ys │ ├── ys_tmpl_yosys_vpr_adder_flow.ys │ ├── ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys │ ├── ys_tmpl_yosys_vpr_bram_dsp_flow.ys │ ├── ys_tmpl_yosys_vpr_bram_flow.ys │ ├── ys_tmpl_yosys_vpr_cnt_flow.ys │ ├── ys_tmpl_yosys_vpr_cnt_flow_with_rewrite.ys │ ├── ys_tmpl_yosys_vpr_dff_flow.ys │ ├── ys_tmpl_yosys_vpr_dsp_flow.ys │ ├── ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys │ ├── ys_tmpl_yosys_vpr_flow.ys │ └── ys_tmpl_yosys_vpr_flow_with_rewrite.ys ├── openfpga_arch │ ├── README.md │ ├── k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml │ ├── k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTile4ClkPin_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTileClkMergeSubtilePort_registerable_io_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTileClk_cc_openfpga.xml │ ├── k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml │ ├── k4_N4_40nm_IoSubtile_cc_openfpga.xml │ ├── k4_N4_40nm_Ntwk1clk2lvl_cc_openfpga.xml │ ├── k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml │ ├── k4_N4_40nm_bank_openfpga.xml │ ├── k4_N4_40nm_bank_use_both_set_reset_openfpga.xml │ ├── k4_N4_40nm_bank_use_reset_openfpga.xml │ ├── k4_N4_40nm_bank_use_resetb_openfpga.xml │ ├── k4_N4_40nm_bank_use_set_openfpga.xml │ ├── k4_N4_40nm_bank_use_setb_openfpga.xml │ ├── k4_N4_40nm_cc_abspath_openfpga.xml │ ├── k4_N4_40nm_cc_cfgdscffio_openfpga.xml │ ├── k4_N4_40nm_cc_cfgscff_openfpga.xml │ ├── k4_N4_40nm_cc_openfpga.xml │ ├── k4_N4_40nm_cc_use_both_set_reset_openfpga.xml │ ├── k4_N4_40nm_cc_use_reset_openfpga.xml │ ├── k4_N4_40nm_cc_use_resetb_openfpga.xml │ ├── k4_N4_40nm_cc_use_set_openfpga.xml │ ├── k4_N4_40nm_cc_use_setb_openfpga.xml │ ├── k4_N4_40nm_cnt8_cc_openfpga.xml │ ├── k4_N4_40nm_dsp8reg_cc_openfpga.xml │ ├── k4_N4_40nm_fixed_sim_openfpga.xml │ ├── k4_N4_40nm_frame_ccff_openfpga.xml │ ├── k4_N4_40nm_frame_const_input_gnd_openfpga.xml │ ├── k4_N4_40nm_frame_no_const_input_openfpga.xml │ ├── k4_N4_40nm_frame_openfpga.xml │ ├── k4_N4_40nm_frame_scff_openfpga.xml │ ├── k4_N4_40nm_frame_use_both_set_reset_openfpga.xml │ ├── k4_N4_40nm_frame_use_reset_openfpga.xml │ ├── k4_N4_40nm_frame_use_resetb_openfpga.xml │ ├── k4_N4_40nm_frame_use_set_openfpga.xml │ ├── k4_N4_40nm_frame_use_setb_openfpga.xml │ ├── k4_N4_40nm_multi_region_bank_openfpga.xml │ ├── k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml │ ├── k4_N4_40nm_multi_region_cc2clk_openfpga.xml │ ├── k4_N4_40nm_multi_region_cc3clk_openfpga.xml │ ├── k4_N4_40nm_multi_region_cc_openfpga.xml │ ├── k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml │ ├── k4_N4_40nm_multi_region_frame_openfpga.xml │ ├── k4_N4_40nm_multi_region_frame_use_both_set_reset_openfpga.xml │ ├── k4_N4_40nm_multi_region_qlbank_openfpga.xml │ ├── k4_N4_40nm_multi_region_qlbanksr_openfpga.xml │ ├── k4_N4_40nm_powergate_frame_openfpga.xml │ ├── k4_N4_40nm_qlbank_openfpga.xml │ ├── k4_N4_40nm_qlbank_wlr_openfpga.xml │ ├── k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml │ ├── k4_N4_40nm_qlbankflatten_openfpga.xml │ ├── k4_N4_40nm_qlbankflatten_wlr_openfpga.xml │ ├── k4_N4_40nm_qlbanksr_multi_chain_openfpga.xml │ ├── k4_N4_40nm_qlbanksr_openfpga.xml │ ├── k4_N4_40nm_qlbanksr_wlr_openfpga.xml │ ├── k4_N4_40nm_standalone_openfpga.xml │ ├── k4_N4_ecb_40nm_cc_openfpga.xml │ ├── k4_N4_frac_dsp16_40nm_cc_openfpga.xml │ ├── k4_N4_no_local_routing_40nm_frame_openfpga.xml │ ├── k4_N5_pattern_local_routing_40nm_frame_openfpga.xml │ ├── k4_fracNative_N4_40nm_cc_openfpga.xml │ ├── k4_frac_N4_40nm_cc_openfpga.xml │ ├── k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml │ ├── k4_frac_N4_adder_chain_40nm_cc_openfpga.xml │ ├── k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml │ ├── k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml │ ├── k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml │ ├── k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml │ ├── k4_frac_N4_fracff2edge_40nm_cc_BinModeBits_openfpga.xml │ ├── k4_frac_N4_fracff2edge_40nm_cc_HexModeBits_openfpga.xml │ ├── k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml │ ├── k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml │ ├── k4_frac_N4_fracff_40nm_cc_openfpga.xml │ ├── k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml │ ├── k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml │ ├── k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml │ ├── k4_frac_N4_lutram_40nm_cc_openfpga.xml │ ├── k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadder_register_scan_chain_dsp8_mem16K_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadder_register_scan_chain_dsp8_mem1K_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_regin_caravel_io_skywater130nm_fdhd_cc_openfpga.xml │ ├── k6_N10_40nm_openfpga.xml │ ├── k6_N10_intermediate_buffer_40nm_openfpga.xml │ ├── k6_frac_N10_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml │ ├── k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml │ ├── k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml │ ├── k6_frac_N10_adder_column_chain_40nm_openfpga.xml │ ├── k6_frac_N10_adder_register_chain_40nm_openfpga.xml │ ├── k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml │ ├── k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml │ ├── k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml │ ├── k6_frac_N10_behavioral_40nm_openfpga.xml │ ├── k6_frac_N10_local_encoder_40nm_openfpga.xml │ ├── k6_frac_N10_spyio_40nm_openfpga.xml │ ├── k6_frac_N10_stdcell_mux_40nm_openfpga.xml │ ├── k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml │ ├── k6_frac_N10_tree_mux_40nm_openfpga.xml │ ├── k6_frac_N8_40nm_openfpga.xml │ ├── k6_frac_N8_debuf_mux_40nm_openfpga.xml │ ├── k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml │ ├── k6_frac_N8_local_encoder_40nm_openfpga.xml │ ├── k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml │ ├── k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml │ ├── k6_frac_N8_stdcell_mux_40nm_openfpga.xml │ └── k6_frac_N8_tree_mux_40nm_openfpga.xml ├── openfpga_cell_library │ ├── Makefile │ ├── spice │ │ ├── adder.sp │ │ ├── ff.sp │ │ ├── gate.sp │ │ ├── io.sp │ │ └── sram.sp │ ├── spice_testbench │ │ └── ff_tb.sp │ ├── verilog │ │ ├── adder.v │ │ ├── aib.v │ │ ├── buf4.v │ │ ├── cnt8.v │ │ ├── dff.v │ │ ├── dpram.v │ │ ├── dpram16k.v │ │ ├── dpram1k.v │ │ ├── dpram8k.v │ │ ├── dpram_2048x8.v │ │ ├── frac_lut4_arith.v │ │ ├── frac_mem_32k.v │ │ ├── frac_mult_16x16.v │ │ ├── frac_mult_16x16_regin.v │ │ ├── frac_mult_36x36.v │ │ ├── gpio.v │ │ ├── inv.v │ │ ├── latch.v │ │ ├── lut6.v │ │ ├── mult_32x32.v │ │ ├── mult_36x36.v │ │ ├── mult_8x8.v │ │ ├── mux2.v │ │ ├── or2.v │ │ ├── spram_4x1.v │ │ ├── sram.v │ │ └── tap_buf4.v │ ├── verilog_sources.f │ └── verilog_testbench │ │ ├── dpram_tb.v │ │ ├── ff_tb.v │ │ ├── mux_tb.v │ │ └── sram_tb.v ├── openfpga_shell_scripts │ ├── auto_bus_group_example_script.openfpga │ ├── behavioral_verilog_example_script.openfpga │ ├── behavioral_verilog_le_example_script.openfpga │ ├── bitstream_setting_example_script.openfpga │ ├── bitstream_setting_pbPinFixup_example_script.openfpga │ ├── configuration_chain_example_script.openfpga │ ├── custom_fabric_netlist_example_script.openfpga │ ├── duplicated_grid_pin_example_script.openfpga │ ├── example_clkntwk_bitstream_setting_script.openfpga │ ├── example_clkntwk_full_tb_script.openfpga │ ├── example_clkntwk_int_driver_no_ace_script.openfpga │ ├── example_clkntwk_no_ace_script.openfpga │ ├── example_clkntwk_pb_pin_fixup_no_ace_script.openfpga │ ├── example_clkntwk_script.openfpga │ ├── example_script.openfpga │ ├── example_without_ace_script.openfpga │ ├── external_file_for_source_example_script.openfpga │ ├── fast_configuration_example_script.openfpga │ ├── fix_device_const_undriven_net_example_script.openfpga │ ├── fix_device_example_script.openfpga │ ├── fix_device_global_tile_clock_bitstream_setting_example_script.openfpga │ ├── fix_device_global_tile_clock_example_script.openfpga │ ├── fix_device_pbPinFixup_example_script.openfpga │ ├── fix_device_route_chan_width_example_script.openfpga │ ├── fix_heterogeneous_device_example_script.openfpga │ ├── fix_heterogeneous_device_pbPinFixup_example_script.openfpga │ ├── fix_heterogeneous_device_pbPinFixup_le_example_script.openfpga │ ├── fix_heterogeneous_device_pbPinFixup_pcf_example_script.openfpga │ ├── fix_pins_example_script.openfpga │ ├── flatten_routing_example_script.openfpga │ ├── fpga_core_example_script.openfpga │ ├── full_testbench_bus_group_example_script.openfpga │ ├── full_testbench_bus_group_le_example_script.openfpga │ ├── full_testbench_example_script.openfpga │ ├── full_testbench_example_without_ace_script.openfpga │ ├── full_testbench_without_self_checking_example_script.openfpga │ ├── generate_bitstream_example_script.openfpga │ ├── generate_bitstream_fix_device_example_script.openfpga │ ├── generate_bitstream_fpga_core_example_script.openfpga │ ├── generate_bitstream_global_tile_multiclock_example_script.openfpga │ ├── generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga │ ├── generate_fabric_example_script.openfpga │ ├── generate_fabric_key_example_script.openfpga │ ├── generate_secure_fabric_example_script.openfpga │ ├── generate_secure_fabric_from_key_example_script.openfpga │ ├── generate_spice_example_script.openfpga │ ├── generate_testbench_example_script.openfpga │ ├── global_tile_clock_example_script.openfpga │ ├── global_tile_clock_full_testbench_example_script.openfpga │ ├── global_tile_clock_full_testbench_fix_routeW_example_script.openfpga │ ├── global_tile_clock_options_full_testbench_example_script.openfpga │ ├── global_tile_clock_pbPinFixup_example_script.openfpga │ ├── global_tile_multiclock_example_script.openfpga │ ├── group_config_block_full_testbench_example_script.openfpga │ ├── group_config_block_preconfig_testbench_example_script.openfpga │ ├── group_tile_clkntwk_preconfig_testbench_example_script.openfpga │ ├── group_tile_clkntwk_preconfig_testbench_le_example_script.openfpga │ ├── group_tile_full_testbench_example_script.openfpga │ ├── group_tile_preconfig_testbench_example_script.openfpga │ ├── group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga │ ├── ignore_global_nets_on_pins_example_script.openfpga │ ├── implicit_verilog_example_script.openfpga │ ├── iverilog_example_script.openfpga │ ├── iwls_benchmark_example_script.openfpga │ ├── le_example_clkntwk_script.openfpga │ ├── le_example_script.openfpga │ ├── le_example_without_ace_script.openfpga │ ├── load_external_arch_bitstream_example_script.openfpga │ ├── local_clk_gen_example_script.openfpga │ ├── mcnc_example_script.openfpga │ ├── mock_wrapper_example_script.openfpga │ ├── module_rename_full_testbench_example_script.openfpga │ ├── module_rename_preconfig_testbench_example_script.openfpga │ ├── module_rename_write_fabric_hie_example_script.openfpga │ ├── no_time_stamp_example_script.openfpga │ ├── pbPinFixup_example_script.openfpga │ ├── pin_constrain_example_script.openfpga │ ├── preconfig_fabric_example_script.openfpga │ ├── preconfigured_testbench_bus_group_example_script.openfpga │ ├── preconfigured_testbench_bus_group_le_example_script.openfpga │ ├── preconfigured_testbench_no_time_stamp_example_script.openfpga │ ├── preconfigured_testbench_relative_path_example_script.openfpga │ ├── preconfigured_testbench_without_self_checking_example_script.openfpga │ ├── preload_rr_graph_example_script.openfpga │ ├── quicklogic_flow_example_script.openfpga │ ├── read_unique_blocks_full_flow_example_script.openfpga │ ├── read_write_unique_blocks_full_flow_example_script.openfpga │ ├── rename_scripts.sh │ ├── report_bitstream_distribution_example_script.openfpga │ ├── report_reference_example_script.openfpga │ ├── sdc_time_unit_example_script.openfpga │ ├── skywater_tapeout_example_script.openfpga │ ├── source_file_example_script.openfpga │ ├── source_string_example_script.openfpga │ ├── test_pcf.openfpga │ ├── verilog_default_net_type_example_script.openfpga │ ├── verilog_default_net_type_le_example_script.openfpga │ ├── vpr_standalone_example_script.openfpga │ ├── vtr_benchmark_example_script.openfpga │ ├── wire_lut_example_script.openfpga │ ├── write_full_testbench_dont_care_bits_example_script.openfpga │ ├── write_full_testbench_example_script.openfpga │ ├── write_full_testbench_fpga_core_example_script.openfpga │ ├── write_full_testbench_fpga_core_le_example_script.openfpga │ ├── write_full_testbench_le_example_script.openfpga │ ├── write_full_testbench_relative_path_example_script.openfpga │ ├── write_full_testbench_simulator_support_example_script.openfpga │ ├── write_gsb_example_script.openfpga │ ├── write_io_mapping_example_script.openfpga │ ├── write_testbench_template_example_script.openfpga │ └── write_unique_blocks_full_flow_example_script.openfpga ├── openfpga_simulation_settings │ ├── auto_shift_register_sim_openfpga.xml │ ├── auto_sim_openfpga.xml │ ├── fixed_4clock_sim_openfpga.xml │ ├── fixed_8clock_sim_openfpga.xml │ ├── fixed_shift_register_sim_openfpga.xml │ └── fixed_sim_openfpga.xml ├── openfpga_yosys_techlib │ ├── k4_N4_tileable_cnt8_40nm_cell_sim.v │ ├── k4_N4_tileable_frac_dsp16_40nm_cell_sim.v │ ├── k4_N4_tileable_frac_dsp16_40nm_dsp_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem16K_nonLR_caravel_io_skywater130nm_bram.txt │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem16K_nonLR_caravel_io_skywater130nm_bram_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem16K_nonLR_caravel_io_skywater130nm_cell_sim.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem16K_nonLR_caravel_io_skywater130nm_dsp_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_nonLR_caravel_io_skywater130nm_bram.txt │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_nonLR_caravel_io_skywater130nm_bram_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_nonLR_caravel_io_skywater130nm_cell_sim.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_nonLR_caravel_io_skywater130nm_dsp_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_regin_nonLR_caravel_io_skywater130nm_cell_sim.v │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v │ ├── k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt │ ├── k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v │ ├── k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v │ ├── openfpga_adders_dsp8_sim.v │ ├── openfpga_adders_sim.v │ ├── openfpga_arith_map.v │ ├── openfpga_brams.txt │ ├── openfpga_brams_map.v │ ├── openfpga_brams_sim.v │ ├── openfpga_dff_map.v │ └── openfpga_dff_sim.v ├── regression_test_scripts │ ├── basic_reg_test.sh │ ├── basic_reg_yosys_only_test.sh │ ├── fpga_bitstream_reg_test.sh │ ├── fpga_sdc_reg_test.sh │ ├── fpga_spice_reg_test.sh │ ├── fpga_verilog_reg_test.sh │ ├── iwls_benchmark_reg_test.sh │ ├── micro_benchmark_reg_test.sh │ ├── quicklogic_reg_test.sh │ ├── tcl_reg_test.sh │ └── vtr_benchmark_reg_test.sh ├── scripts │ ├── arch_file_updater.py │ ├── check_qor.py │ ├── io_sequence_visualizer.py │ ├── pro_blif.pl │ ├── run_ci_tests.py │ ├── run_formality.py │ ├── run_fpga_flow.py │ ├── run_fpga_task.conf │ ├── run_fpga_task.py │ ├── run_modelsim.py │ ├── swig_pkg_mkIndex_gen.tcl │ └── swig_tcl_example.tcl ├── tasks │ ├── .gitignore │ ├── README.md │ ├── basic_tests │ │ ├── bus_group │ │ │ ├── auto_gen_bus_group │ │ │ │ └── config │ │ │ │ │ ├── bus_group_gen.py │ │ │ │ │ ├── counter8_bus_group_task.yaml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── full_testbench_explicit_mapping │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── full_testbench_explicit_mapping_little_endian │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── full_testbench_implicit_mapping │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── preconfig_testbench_explicit_mapping │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── preconfig_testbench_explicit_mapping_little_endian │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ └── preconfig_testbench_implicit_mapping │ │ │ │ └── config │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ └── task.conf │ │ ├── clock_network │ │ │ ├── homo_1clock_1reset_1layer_2entry │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── pin_constraints_rstn.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_dec │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_disable_unused_spines │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_intermediate_driver │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer_int_driver_clk.xml │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer_int_driver_rst.xml │ │ │ │ │ ├── pin_constraints_clk_cond.xml │ │ │ │ │ ├── pin_constraints_rst_cond.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ ├── vpr_constraint_clk_cond.xml │ │ │ │ │ └── vpr_constraint_rst_cond.xml │ │ │ ├── homo_1clock_1reset_2layer_internal_driver │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer_int_driver_clk.xml │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer_int_driver_rst.xml │ │ │ │ │ ├── pin_constraints_clk_cond.xml │ │ │ │ │ ├── pin_constraints_rst_cond.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ ├── vpr_constraint_clk_cond.xml │ │ │ │ │ └── vpr_constraint_rst_cond.xml │ │ │ ├── homo_1clock_1reset_2layer_on_lut │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_clk.xml │ │ │ │ │ ├── pin_constraints_rst.xml │ │ │ │ │ ├── pin_constraints_rst_and_clk.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_on_lut_pb_pin_fixup │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_clk.xml │ │ │ │ │ ├── pin_constraints_rst.xml │ │ │ │ │ ├── pin_constraints_rst_and_clk.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_clk.xml │ │ │ │ │ ├── pin_constraints_rst.xml │ │ │ │ │ ├── pin_constraints_rst_and_clk.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_syntax │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_2layer_y_entry │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_2layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_3layer_2entry │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_3layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_1reset_3layer_2entry_disable_unused │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_1rst_3layer.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_2layer │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ ├── dummy_pin_constraints.xml │ │ │ │ │ ├── dummy_repack_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_1clock_2layer_full_tb │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_2clock_2layer │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_2clk_2layer.xml │ │ │ │ │ ├── pin_constraints.xml │ │ │ │ │ ├── repack_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_2clock_2layer_disable_unused │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_2clk_2layer.xml │ │ │ │ │ ├── pin_constraints.xml │ │ │ │ │ ├── repack_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── homo_2clock_2layer_disable_unused_tree │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_2clk_2layer.xml │ │ │ │ │ ├── pin_constraints.xml │ │ │ │ │ ├── repack_constraints.xml │ │ │ │ │ └── task.conf │ │ │ └── homo_2clock_2layer_little_endian │ │ │ │ └── config │ │ │ │ ├── clk_arch_2clk_2layer.xml │ │ │ │ ├── pin_constraints.xml │ │ │ │ ├── repack_constraints.xml │ │ │ │ └── task.conf │ │ ├── custom_fabric_netlist_location │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── explicit_multi_verilog_files │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── fabric_key │ │ │ ├── generate_multi_region_vanilla_key │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── generate_random_key │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── generate_random_key_ql_memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── generate_vanilla_key │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key_cc_fpga │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key_multi_region_cc_fpga │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key_multi_region_qlbank_fpga │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key_multi_region_qlbanksr_fpga │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key_qlbank_fpga │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── load_external_key_qlbanksr_multi_chain_fpga │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── load_external_subkey_cc_fpga │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── fixed_device_support │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── fixed_simulation_settings │ │ │ ├── fixed_operating_clock_freq │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fixed_operating_clock_freq_no_ace │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ └── fixed_shift_register_clock_freq │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── full_testbench │ │ │ ├── configuration_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_config_enable_scff │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_le │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_no_time_stamp │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_use_reset │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_use_resetb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_use_set │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_use_set_reset │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_use_setb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_ccff │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_scff │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_use_reset │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_use_resetb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_use_set │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_use_set_reset │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame_use_setb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fast_configuration_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fast_configuration_chain_use_set │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fast_configuration_frame │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fast_configuration_frame_use_set │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fast_memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fast_memory_bank_use_set │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── flatten_memory │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fpga_core_wrapper │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fpga_core_wrapper_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fpga_core_wrapper_naming_rules │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── wrapper_io_naming.xml │ │ │ ├── fpga_core_wrapper_naming_rules_use_core_tb │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── wrapper_io_naming.xml │ │ │ ├── full_testbench_without_self_checking │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── memory_bank_use_reset │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── memory_bank_use_resetb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── memory_bank_use_set │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── memory_bank_use_set_reset │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── memory_bank_use_setb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_configuration_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_configuration_chain_2clk │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_configuration_chain_2clk_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_configuration_chain_3clk │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_configuration_frame │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_ql_memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_region_ql_memory_bank_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_flatten │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_flatten_defined_wl │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_flatten_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_flatten_use_wlr │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_shift_register │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_shift_register_multi_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_shift_register_multi_chain_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_shift_register_use_wlr │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_shift_register_vcs │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── ql_memory_bank_use_wlr │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── smart_fast_configuration_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── smart_fast_configuration_frame │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── smart_fast_memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── smart_fast_multi_region_configuration_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── smart_fast_multi_region_configuration_frame │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── smart_fast_multi_region_memory_bank │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── generate_fabric │ │ │ ├── config │ │ │ │ └── task.conf │ │ │ └── design_variables.yml │ │ ├── generate_template_testbench │ │ │ └── config │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ ├── mac4_bus_group.xml │ │ │ │ ├── pin_constraints_dummy.xml │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ └── task.conf │ │ ├── generate_testbench │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── global_tile_ports │ │ │ ├── global_tile_4clock │ │ │ │ └── config │ │ │ │ │ ├── and2_latch_pin_constraints.xml │ │ │ │ │ ├── counter_2clock_pin_constraints.xml │ │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── global_tile_4clock_pin │ │ │ │ └── config │ │ │ │ │ ├── and2_latch_pin_constraints.xml │ │ │ │ │ ├── and2_latch_repack_pin_constraints.xml │ │ │ │ │ ├── counter_2clock_pin_constraints.xml │ │ │ │ │ ├── counter_2clock_repack_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── global_tile_clock │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── global_tile_clock_subtile │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── global_tile_clock_subtile_port_merge │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── global_tile_clock_subtile_port_merge_fabric_tile_group_config │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ └── global_tile_reset │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── group_config_block │ │ │ ├── group_config_block_hetero_fabric_tile │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── group_config_block_hetero_fabric_tile_Lshape │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── group_config_block_homo_Lshape_full_testbench │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── group_config_block_homo_fabric_tile │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── group_config_block_homo_fabric_tile_Lshape │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── group_config_block_homo_fabric_tile_core_wrapper │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── group_config_block_homo_fabric_tile_global_tile_clock_io_subtile │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ └── group_config_block_homo_full_testbench │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── io_constraints │ │ │ ├── empty_pcf │ │ │ │ └── config │ │ │ │ │ ├── and2.pcf │ │ │ │ │ ├── fpga_io_location.xml │ │ │ │ │ ├── pinmap_k4_N4_tileable_40nm.csv │ │ │ │ │ └── task.conf │ │ │ ├── example_pcf │ │ │ │ └── config │ │ │ │ │ ├── and2.pcf │ │ │ │ │ ├── fpga_io_location.xml │ │ │ │ │ ├── pinmap_k4_N4_tileable_40nm.csv │ │ │ │ │ └── task.conf │ │ │ ├── fix_pins │ │ │ │ └── config │ │ │ │ │ ├── and2_fix_pins.place │ │ │ │ │ └── task.conf │ │ │ ├── pcf_ql_style │ │ │ │ └── config │ │ │ │ │ ├── and2.pcf │ │ │ │ │ ├── fpga_io_location.xml │ │ │ │ │ ├── pinmap_k4_N4_tileable_40nm.csv │ │ │ │ │ └── task.conf │ │ │ └── pcf_reduce_error │ │ │ │ └── config │ │ │ │ ├── and2.pcf │ │ │ │ ├── fpga_io_location.xml │ │ │ │ ├── pinmap_k4_N4_tileable_40nm.csv │ │ │ │ └── task.conf │ │ ├── k4_series │ │ │ ├── k4n4_L124 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_adder │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_bram │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_chandistr │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_chandistr_segdist │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_clk_gen │ │ │ │ └── config │ │ │ │ │ ├── dffn_pin_constraints.xml │ │ │ │ │ ├── dffn_repack_design_constraints.xml │ │ │ │ │ ├── pin_constraints.xml │ │ │ │ │ ├── repack_design_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_custom_io_loc │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_custom_io_loc_center │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_custom_io_loc_center_height_odd │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_custom_io_loc_center_width_odd │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_ecb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_ecb_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_frac_lut │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_frac_mult │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_fracff │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_fracff2edge │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_fracff_little_endian │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_lutram │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_no_local_routing │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_rstOnLut │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── repack_design_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_rstOnLut_strong │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── repack_design_constraints.xml │ │ │ │ │ └── task.conf │ │ │ ├── k4n4_rst_gen │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints.xml │ │ │ │ │ ├── repack_design_constraints.xml │ │ │ │ │ ├── rst_on_lut_pc.xml │ │ │ │ │ ├── rst_on_lut_repack_dc.xml │ │ │ │ │ └── task.conf │ │ │ └── k4n5_pattern_local_routing │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── mock_wrapper │ │ │ ├── mock_wrapper_bgf │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── mock_wrapper_explicit_port_mapping │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── mock_wrapper_fpga_core │ │ │ │ └── config │ │ │ │ │ ├── counter8_bus_group.xml │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── wrapper_io_naming.xml │ │ │ ├── mock_wrapper_implicit_port_mapping │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── mock_wrapper_pcf │ │ │ │ └── config │ │ │ │ ├── and2_latch_pin_constraints.xml │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ └── task.conf │ │ ├── mode_bit_format │ │ │ ├── bin_format_big_endian │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ └── hex_format_big_endian │ │ │ │ └── config │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ └── task.conf │ │ ├── module_naming │ │ │ ├── fabric_tile_clkntwk_io_subtile_using_index │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── renaming_rules │ │ │ │ └── config │ │ │ │ │ ├── module_names.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── renaming_rules_on_indexed_names │ │ │ │ └── config │ │ │ │ │ ├── module_names.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── renaming_rules_strong │ │ │ │ └── config │ │ │ │ │ ├── module_names.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ └── using_index │ │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── no_time_stamp │ │ │ ├── device_1x1 │ │ │ │ ├── config │ │ │ │ │ └── task.conf │ │ │ │ └── golden_outputs_no_time_stamp │ │ │ │ │ ├── and2_formal_random_top_tb.v │ │ │ │ │ ├── and2_fpga_top_analysis.sdc │ │ │ │ │ ├── and2_include_netlists.v │ │ │ │ │ ├── and2_top_formal_verification.v │ │ │ │ │ ├── bitstream_distribution.xml │ │ │ │ │ ├── cbx_1__0_.sdc │ │ │ │ │ ├── cbx_1__1_.sdc │ │ │ │ │ ├── cby_0__1_.sdc │ │ │ │ │ ├── cby_1__1_.sdc │ │ │ │ │ ├── ccff_timing.sdc │ │ │ │ │ ├── disable_configurable_memory_outputs.sdc │ │ │ │ │ ├── disable_configure_ports.sdc │ │ │ │ │ ├── disable_routing_multiplexer_outputs.sdc │ │ │ │ │ ├── disable_sb_outputs.sdc │ │ │ │ │ ├── fabric_bitstream.bit │ │ │ │ │ ├── fabric_bitstream.xml │ │ │ │ │ ├── fabric_independent_bitstream.xml │ │ │ │ │ ├── fabric_io_location.xml │ │ │ │ │ ├── fabric_netlists.v │ │ │ │ │ ├── fabric_pin_phy_loc.xml │ │ │ │ │ ├── fpga_defines.v │ │ │ │ │ ├── fpga_top.v │ │ │ │ │ ├── global_ports.sdc │ │ │ │ │ ├── gsb_xml │ │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ │ ├── cby_0__0_.xml │ │ │ │ │ ├── cby_0__1_.xml │ │ │ │ │ ├── cby_0__2_.xml │ │ │ │ │ ├── cby_1__0_.xml │ │ │ │ │ ├── cby_1__1_.xml │ │ │ │ │ ├── cby_1__2_.xml │ │ │ │ │ ├── sb_0__0_.xml │ │ │ │ │ ├── sb_0__1_.xml │ │ │ │ │ ├── sb_1__0_.xml │ │ │ │ │ └── sb_1__1_.xml │ │ │ │ │ ├── gsb_xml_no_rr_info │ │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ │ ├── cby_0__0_.xml │ │ │ │ │ ├── cby_0__1_.xml │ │ │ │ │ ├── cby_0__2_.xml │ │ │ │ │ ├── cby_1__0_.xml │ │ │ │ │ ├── cby_1__1_.xml │ │ │ │ │ ├── cby_1__2_.xml │ │ │ │ │ ├── sb_0__0_.xml │ │ │ │ │ ├── sb_0__1_.xml │ │ │ │ │ ├── sb_1__0_.xml │ │ │ │ │ └── sb_1__1_.xml │ │ │ │ │ ├── lb │ │ │ │ │ ├── grid_clb.v │ │ │ │ │ ├── grid_io_bottom.v │ │ │ │ │ ├── grid_io_left.v │ │ │ │ │ ├── grid_io_right.v │ │ │ │ │ ├── grid_io_top.v │ │ │ │ │ ├── logical_tile_clb_mode_clb_.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v │ │ │ │ │ ├── logical_tile_io_mode_io_.v │ │ │ │ │ └── logical_tile_io_mode_physical__iopad.v │ │ │ │ │ ├── logical_tile_clb_mode_clb_.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc │ │ │ │ │ ├── logical_tile_io_mode_io_.sdc │ │ │ │ │ ├── mux_modules.yaml │ │ │ │ │ ├── pin_mapping.xml │ │ │ │ │ ├── routing │ │ │ │ │ ├── cbx_1__0_.v │ │ │ │ │ ├── cbx_1__1_.v │ │ │ │ │ ├── cby_0__1_.v │ │ │ │ │ ├── cby_1__1_.v │ │ │ │ │ ├── sb_0__0_.v │ │ │ │ │ ├── sb_0__1_.v │ │ │ │ │ ├── sb_1__0_.v │ │ │ │ │ └── sb_1__1_.v │ │ │ │ │ ├── sb_0__0_.sdc │ │ │ │ │ ├── sb_0__1_.sdc │ │ │ │ │ ├── sb_1__0_.sdc │ │ │ │ │ ├── sb_1__1_.sdc │ │ │ │ │ └── sub_module │ │ │ │ │ ├── arch_encoder.v │ │ │ │ │ ├── inv_buf_passgate.v │ │ │ │ │ ├── local_encoder.v │ │ │ │ │ ├── luts.v │ │ │ │ │ ├── memories.v │ │ │ │ │ ├── mux_primitives.v │ │ │ │ │ ├── muxes.v │ │ │ │ │ ├── shift_register_banks.v │ │ │ │ │ ├── user_defined_templates.v │ │ │ │ │ └── wires.v │ │ │ ├── device_4x4 │ │ │ │ ├── config │ │ │ │ │ └── task.conf │ │ │ │ └── golden_outputs_no_time_stamp │ │ │ │ │ ├── and2_formal_random_top_tb.v │ │ │ │ │ ├── and2_fpga_top_analysis.sdc │ │ │ │ │ ├── and2_include_netlists.v │ │ │ │ │ ├── and2_top_formal_verification.v │ │ │ │ │ ├── bitstream_distribution.xml │ │ │ │ │ ├── cbx_1__0_.sdc │ │ │ │ │ ├── cbx_1__1_.sdc │ │ │ │ │ ├── cbx_1__4_.sdc │ │ │ │ │ ├── cby_0__1_.sdc │ │ │ │ │ ├── cby_1__1_.sdc │ │ │ │ │ ├── cby_4__1_.sdc │ │ │ │ │ ├── ccff_timing.sdc │ │ │ │ │ ├── disable_configurable_memory_outputs.sdc │ │ │ │ │ ├── disable_configure_ports.sdc │ │ │ │ │ ├── disable_routing_multiplexer_outputs.sdc │ │ │ │ │ ├── disable_sb_outputs.sdc │ │ │ │ │ ├── fabric_bitstream.bit │ │ │ │ │ ├── fabric_bitstream.xml │ │ │ │ │ ├── fabric_independent_bitstream.xml │ │ │ │ │ ├── fabric_io_location.xml │ │ │ │ │ ├── fabric_netlists.v │ │ │ │ │ ├── fabric_pin_phy_loc.xml │ │ │ │ │ ├── fpga_defines.v │ │ │ │ │ ├── fpga_top.v │ │ │ │ │ ├── global_ports.sdc │ │ │ │ │ ├── gsb_xml │ │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ │ ├── cbx_0__2_.xml │ │ │ │ │ ├── cbx_0__3_.xml │ │ │ │ │ ├── cbx_0__4_.xml │ │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ │ ├── cbx_1__2_.xml │ │ │ │ │ ├── cbx_1__3_.xml │ │ │ │ │ ├── cbx_1__4_.xml │ │ │ │ │ ├── cbx_2__0_.xml │ │ │ │ │ ├── cbx_2__1_.xml │ │ │ │ │ ├── cbx_2__2_.xml │ │ │ │ │ ├── cbx_2__3_.xml │ │ │ │ │ ├── cbx_2__4_.xml │ │ │ │ │ ├── cbx_3__0_.xml │ │ │ │ │ ├── cbx_3__1_.xml │ │ │ │ │ ├── cbx_3__2_.xml │ │ │ │ │ ├── cbx_3__3_.xml │ │ │ │ │ ├── cbx_3__4_.xml │ │ │ │ │ ├── cbx_4__0_.xml │ │ │ │ │ ├── cbx_4__1_.xml │ │ │ │ │ ├── cbx_4__2_.xml │ │ │ │ │ ├── cbx_4__3_.xml │ │ │ │ │ ├── cbx_4__4_.xml │ │ │ │ │ ├── cby_0__0_.xml │ │ │ │ │ ├── cby_0__1_.xml │ │ │ │ │ ├── cby_0__2_.xml │ │ │ │ │ ├── cby_0__3_.xml │ │ │ │ │ ├── cby_0__4_.xml │ │ │ │ │ ├── cby_0__5_.xml │ │ │ │ │ ├── cby_1__0_.xml │ │ │ │ │ ├── cby_1__1_.xml │ │ │ │ │ ├── cby_1__2_.xml │ │ │ │ │ ├── cby_1__3_.xml │ │ │ │ │ ├── cby_1__4_.xml │ │ │ │ │ ├── cby_1__5_.xml │ │ │ │ │ ├── cby_2__0_.xml │ │ │ │ │ ├── cby_2__1_.xml │ │ │ │ │ ├── cby_2__2_.xml │ │ │ │ │ ├── cby_2__3_.xml │ │ │ │ │ ├── cby_2__4_.xml │ │ │ │ │ ├── cby_2__5_.xml │ │ │ │ │ ├── cby_3__0_.xml │ │ │ │ │ ├── cby_3__1_.xml │ │ │ │ │ ├── cby_3__2_.xml │ │ │ │ │ ├── cby_3__3_.xml │ │ │ │ │ ├── cby_3__4_.xml │ │ │ │ │ ├── cby_3__5_.xml │ │ │ │ │ ├── cby_4__0_.xml │ │ │ │ │ ├── cby_4__1_.xml │ │ │ │ │ ├── cby_4__2_.xml │ │ │ │ │ ├── cby_4__3_.xml │ │ │ │ │ ├── cby_4__4_.xml │ │ │ │ │ ├── cby_4__5_.xml │ │ │ │ │ ├── sb_0__0_.xml │ │ │ │ │ ├── sb_0__1_.xml │ │ │ │ │ ├── sb_0__2_.xml │ │ │ │ │ ├── sb_0__3_.xml │ │ │ │ │ ├── sb_0__4_.xml │ │ │ │ │ ├── sb_1__0_.xml │ │ │ │ │ ├── sb_1__1_.xml │ │ │ │ │ ├── sb_1__2_.xml │ │ │ │ │ ├── sb_1__3_.xml │ │ │ │ │ ├── sb_1__4_.xml │ │ │ │ │ ├── sb_2__0_.xml │ │ │ │ │ ├── sb_2__1_.xml │ │ │ │ │ ├── sb_2__2_.xml │ │ │ │ │ ├── sb_2__3_.xml │ │ │ │ │ ├── sb_2__4_.xml │ │ │ │ │ ├── sb_3__0_.xml │ │ │ │ │ ├── sb_3__1_.xml │ │ │ │ │ ├── sb_3__2_.xml │ │ │ │ │ ├── sb_3__3_.xml │ │ │ │ │ ├── sb_3__4_.xml │ │ │ │ │ ├── sb_4__0_.xml │ │ │ │ │ ├── sb_4__1_.xml │ │ │ │ │ ├── sb_4__2_.xml │ │ │ │ │ ├── sb_4__3_.xml │ │ │ │ │ └── sb_4__4_.xml │ │ │ │ │ ├── gsb_xml_no_rr_info │ │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ │ ├── cbx_0__2_.xml │ │ │ │ │ ├── cbx_0__3_.xml │ │ │ │ │ ├── cbx_0__4_.xml │ │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ │ ├── cbx_1__2_.xml │ │ │ │ │ ├── cbx_1__3_.xml │ │ │ │ │ ├── cbx_1__4_.xml │ │ │ │ │ ├── cbx_2__0_.xml │ │ │ │ │ ├── cbx_2__1_.xml │ │ │ │ │ ├── cbx_2__2_.xml │ │ │ │ │ ├── cbx_2__3_.xml │ │ │ │ │ ├── cbx_2__4_.xml │ │ │ │ │ ├── cbx_3__0_.xml │ │ │ │ │ ├── cbx_3__1_.xml │ │ │ │ │ ├── cbx_3__2_.xml │ │ │ │ │ ├── cbx_3__3_.xml │ │ │ │ │ ├── cbx_3__4_.xml │ │ │ │ │ ├── cbx_4__0_.xml │ │ │ │ │ ├── cbx_4__1_.xml │ │ │ │ │ ├── cbx_4__2_.xml │ │ │ │ │ ├── cbx_4__3_.xml │ │ │ │ │ ├── cbx_4__4_.xml │ │ │ │ │ ├── cby_0__0_.xml │ │ │ │ │ ├── cby_0__1_.xml │ │ │ │ │ ├── cby_0__2_.xml │ │ │ │ │ ├── cby_0__3_.xml │ │ │ │ │ ├── cby_0__4_.xml │ │ │ │ │ ├── cby_0__5_.xml │ │ │ │ │ ├── cby_1__0_.xml │ │ │ │ │ ├── cby_1__1_.xml │ │ │ │ │ ├── cby_1__2_.xml │ │ │ │ │ ├── cby_1__3_.xml │ │ │ │ │ ├── cby_1__4_.xml │ │ │ │ │ ├── cby_1__5_.xml │ │ │ │ │ ├── cby_2__0_.xml │ │ │ │ │ ├── cby_2__1_.xml │ │ │ │ │ ├── cby_2__2_.xml │ │ │ │ │ ├── cby_2__3_.xml │ │ │ │ │ ├── cby_2__4_.xml │ │ │ │ │ ├── cby_2__5_.xml │ │ │ │ │ ├── cby_3__0_.xml │ │ │ │ │ ├── cby_3__1_.xml │ │ │ │ │ ├── cby_3__2_.xml │ │ │ │ │ ├── cby_3__3_.xml │ │ │ │ │ ├── cby_3__4_.xml │ │ │ │ │ ├── cby_3__5_.xml │ │ │ │ │ ├── cby_4__0_.xml │ │ │ │ │ ├── cby_4__1_.xml │ │ │ │ │ ├── cby_4__2_.xml │ │ │ │ │ ├── cby_4__3_.xml │ │ │ │ │ ├── cby_4__4_.xml │ │ │ │ │ ├── cby_4__5_.xml │ │ │ │ │ ├── sb_0__0_.xml │ │ │ │ │ ├── sb_0__1_.xml │ │ │ │ │ ├── sb_0__2_.xml │ │ │ │ │ ├── sb_0__3_.xml │ │ │ │ │ ├── sb_0__4_.xml │ │ │ │ │ ├── sb_1__0_.xml │ │ │ │ │ ├── sb_1__1_.xml │ │ │ │ │ ├── sb_1__2_.xml │ │ │ │ │ ├── sb_1__3_.xml │ │ │ │ │ ├── sb_1__4_.xml │ │ │ │ │ ├── sb_2__0_.xml │ │ │ │ │ ├── sb_2__1_.xml │ │ │ │ │ ├── sb_2__2_.xml │ │ │ │ │ ├── sb_2__3_.xml │ │ │ │ │ ├── sb_2__4_.xml │ │ │ │ │ ├── sb_3__0_.xml │ │ │ │ │ ├── sb_3__1_.xml │ │ │ │ │ ├── sb_3__2_.xml │ │ │ │ │ ├── sb_3__3_.xml │ │ │ │ │ ├── sb_3__4_.xml │ │ │ │ │ ├── sb_4__0_.xml │ │ │ │ │ ├── sb_4__1_.xml │ │ │ │ │ ├── sb_4__2_.xml │ │ │ │ │ ├── sb_4__3_.xml │ │ │ │ │ └── sb_4__4_.xml │ │ │ │ │ ├── lb │ │ │ │ │ ├── grid_clb.v │ │ │ │ │ ├── grid_io_bottom.v │ │ │ │ │ ├── grid_io_left.v │ │ │ │ │ ├── grid_io_right.v │ │ │ │ │ ├── grid_io_top.v │ │ │ │ │ ├── logical_tile_clb_mode_clb_.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v │ │ │ │ │ ├── logical_tile_io_mode_io_.v │ │ │ │ │ └── logical_tile_io_mode_physical__iopad.v │ │ │ │ │ ├── logical_tile_clb_mode_clb_.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc │ │ │ │ │ ├── logical_tile_io_mode_io_.sdc │ │ │ │ │ ├── mux_modules.yaml │ │ │ │ │ ├── pin_mapping.xml │ │ │ │ │ ├── routing │ │ │ │ │ ├── cbx_1__0_.v │ │ │ │ │ ├── cbx_1__1_.v │ │ │ │ │ ├── cbx_1__4_.v │ │ │ │ │ ├── cby_0__1_.v │ │ │ │ │ ├── cby_1__1_.v │ │ │ │ │ ├── cby_4__1_.v │ │ │ │ │ ├── sb_0__0_.v │ │ │ │ │ ├── sb_0__1_.v │ │ │ │ │ ├── sb_0__4_.v │ │ │ │ │ ├── sb_1__0_.v │ │ │ │ │ ├── sb_1__1_.v │ │ │ │ │ ├── sb_1__4_.v │ │ │ │ │ ├── sb_4__0_.v │ │ │ │ │ ├── sb_4__1_.v │ │ │ │ │ └── sb_4__4_.v │ │ │ │ │ ├── sb_0__0_.sdc │ │ │ │ │ ├── sb_0__1_.sdc │ │ │ │ │ ├── sb_0__4_.sdc │ │ │ │ │ ├── sb_1__0_.sdc │ │ │ │ │ ├── sb_1__1_.sdc │ │ │ │ │ ├── sb_1__4_.sdc │ │ │ │ │ ├── sb_4__0_.sdc │ │ │ │ │ ├── sb_4__1_.sdc │ │ │ │ │ ├── sb_4__4_.sdc │ │ │ │ │ └── sub_module │ │ │ │ │ ├── arch_encoder.v │ │ │ │ │ ├── inv_buf_passgate.v │ │ │ │ │ ├── local_encoder.v │ │ │ │ │ ├── luts.v │ │ │ │ │ ├── memories.v │ │ │ │ │ ├── mux_primitives.v │ │ │ │ │ ├── muxes.v │ │ │ │ │ ├── shift_register_banks.v │ │ │ │ │ ├── user_defined_templates.v │ │ │ │ │ └── wires.v │ │ │ ├── dump_waveform │ │ │ │ ├── config │ │ │ │ │ └── task.conf │ │ │ │ └── golden_outputs_no_time_stamp │ │ │ │ │ ├── and2_formal_random_top_tb.v │ │ │ │ │ ├── and2_fpga_top_analysis.sdc │ │ │ │ │ ├── and2_include_netlists.v │ │ │ │ │ ├── and2_top_formal_verification.v │ │ │ │ │ ├── bitstream_distribution.xml │ │ │ │ │ ├── cbx_1__0_.sdc │ │ │ │ │ ├── cbx_1__1_.sdc │ │ │ │ │ ├── cby_0__1_.sdc │ │ │ │ │ ├── cby_1__1_.sdc │ │ │ │ │ ├── ccff_timing.sdc │ │ │ │ │ ├── disable_configurable_memory_outputs.sdc │ │ │ │ │ ├── disable_configure_ports.sdc │ │ │ │ │ ├── disable_routing_multiplexer_outputs.sdc │ │ │ │ │ ├── disable_sb_outputs.sdc │ │ │ │ │ ├── fabric_bitstream.bit │ │ │ │ │ ├── fabric_bitstream.xml │ │ │ │ │ ├── fabric_independent_bitstream.xml │ │ │ │ │ ├── fabric_io_location.xml │ │ │ │ │ ├── fabric_netlists.v │ │ │ │ │ ├── fabric_pin_phy_loc.xml │ │ │ │ │ ├── fpga_defines.v │ │ │ │ │ ├── fpga_top.v │ │ │ │ │ ├── global_ports.sdc │ │ │ │ │ ├── gsb_xml │ │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ │ ├── cby_0__0_.xml │ │ │ │ │ ├── cby_0__1_.xml │ │ │ │ │ ├── cby_0__2_.xml │ │ │ │ │ ├── cby_1__0_.xml │ │ │ │ │ ├── cby_1__1_.xml │ │ │ │ │ ├── cby_1__2_.xml │ │ │ │ │ ├── sb_0__0_.xml │ │ │ │ │ ├── sb_0__1_.xml │ │ │ │ │ ├── sb_1__0_.xml │ │ │ │ │ └── sb_1__1_.xml │ │ │ │ │ ├── gsb_xml_no_rr_info │ │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ │ ├── cby_0__0_.xml │ │ │ │ │ ├── cby_0__1_.xml │ │ │ │ │ ├── cby_0__2_.xml │ │ │ │ │ ├── cby_1__0_.xml │ │ │ │ │ ├── cby_1__1_.xml │ │ │ │ │ ├── cby_1__2_.xml │ │ │ │ │ ├── sb_0__0_.xml │ │ │ │ │ ├── sb_0__1_.xml │ │ │ │ │ ├── sb_1__0_.xml │ │ │ │ │ └── sb_1__1_.xml │ │ │ │ │ ├── lb │ │ │ │ │ ├── grid_clb.v │ │ │ │ │ ├── grid_io_bottom.v │ │ │ │ │ ├── grid_io_left.v │ │ │ │ │ ├── grid_io_right.v │ │ │ │ │ ├── grid_io_top.v │ │ │ │ │ ├── logical_tile_clb_mode_clb_.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v │ │ │ │ │ ├── logical_tile_io_mode_io_.v │ │ │ │ │ └── logical_tile_io_mode_physical__iopad.v │ │ │ │ │ ├── logical_tile_clb_mode_clb_.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc │ │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc │ │ │ │ │ ├── logical_tile_io_mode_io_.sdc │ │ │ │ │ ├── mux_modules.yaml │ │ │ │ │ ├── pin_mapping.xml │ │ │ │ │ ├── routing │ │ │ │ │ ├── cbx_1__0_.v │ │ │ │ │ ├── cbx_1__1_.v │ │ │ │ │ ├── cby_0__1_.v │ │ │ │ │ ├── cby_1__1_.v │ │ │ │ │ ├── sb_0__0_.v │ │ │ │ │ ├── sb_0__1_.v │ │ │ │ │ ├── sb_1__0_.v │ │ │ │ │ └── sb_1__1_.v │ │ │ │ │ ├── sb_0__0_.sdc │ │ │ │ │ ├── sb_0__1_.sdc │ │ │ │ │ ├── sb_1__0_.sdc │ │ │ │ │ ├── sb_1__1_.sdc │ │ │ │ │ └── sub_module │ │ │ │ │ ├── arch_encoder.v │ │ │ │ │ ├── inv_buf_passgate.v │ │ │ │ │ ├── local_encoder.v │ │ │ │ │ ├── luts.v │ │ │ │ │ ├── memories.v │ │ │ │ │ ├── mux_primitives.v │ │ │ │ │ ├── muxes.v │ │ │ │ │ ├── shift_register_banks.v │ │ │ │ │ ├── user_defined_templates.v │ │ │ │ │ └── wires.v │ │ │ └── no_cout_in_gsb │ │ │ │ ├── config │ │ │ │ └── task.conf │ │ │ │ └── golden_outputs_no_time_stamp │ │ │ │ ├── and2_formal_random_top_tb.v │ │ │ │ ├── and2_fpga_top_analysis.sdc │ │ │ │ ├── and2_include_netlists.v │ │ │ │ ├── and2_top_formal_verification.v │ │ │ │ ├── bitstream_distribution.xml │ │ │ │ ├── cbx_1__0_.sdc │ │ │ │ ├── cbx_1__1_.sdc │ │ │ │ ├── cbx_1__2_.sdc │ │ │ │ ├── cby_0__1_.sdc │ │ │ │ ├── cby_1__1_.sdc │ │ │ │ ├── cby_2__1_.sdc │ │ │ │ ├── ccff_timing.sdc │ │ │ │ ├── disable_configurable_memory_outputs.sdc │ │ │ │ ├── disable_configure_ports.sdc │ │ │ │ ├── disable_routing_multiplexer_outputs.sdc │ │ │ │ ├── disable_sb_outputs.sdc │ │ │ │ ├── fabric_bitstream.bit │ │ │ │ ├── fabric_bitstream.xml │ │ │ │ ├── fabric_independent_bitstream.xml │ │ │ │ ├── fabric_io_location.xml │ │ │ │ ├── fabric_netlists.v │ │ │ │ ├── fabric_pin_phy_loc.xml │ │ │ │ ├── fpga_defines.v │ │ │ │ ├── fpga_top.v │ │ │ │ ├── global_ports.sdc │ │ │ │ ├── gsb_xml │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ ├── cbx_0__2_.xml │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ ├── cbx_1__2_.xml │ │ │ │ ├── cbx_2__0_.xml │ │ │ │ ├── cbx_2__1_.xml │ │ │ │ ├── cbx_2__2_.xml │ │ │ │ ├── cby_0__0_.xml │ │ │ │ ├── cby_0__1_.xml │ │ │ │ ├── cby_0__2_.xml │ │ │ │ ├── cby_0__3_.xml │ │ │ │ ├── cby_1__0_.xml │ │ │ │ ├── cby_1__1_.xml │ │ │ │ ├── cby_1__2_.xml │ │ │ │ ├── cby_1__3_.xml │ │ │ │ ├── cby_2__0_.xml │ │ │ │ ├── cby_2__1_.xml │ │ │ │ ├── cby_2__2_.xml │ │ │ │ ├── cby_2__3_.xml │ │ │ │ ├── sb_0__0_.xml │ │ │ │ ├── sb_0__1_.xml │ │ │ │ ├── sb_0__2_.xml │ │ │ │ ├── sb_1__0_.xml │ │ │ │ ├── sb_1__1_.xml │ │ │ │ ├── sb_1__2_.xml │ │ │ │ ├── sb_2__0_.xml │ │ │ │ ├── sb_2__1_.xml │ │ │ │ └── sb_2__2_.xml │ │ │ │ ├── gsb_xml_no_rr_info │ │ │ │ ├── cbx_0__0_.xml │ │ │ │ ├── cbx_0__1_.xml │ │ │ │ ├── cbx_0__2_.xml │ │ │ │ ├── cbx_1__0_.xml │ │ │ │ ├── cbx_1__1_.xml │ │ │ │ ├── cbx_1__2_.xml │ │ │ │ ├── cbx_2__0_.xml │ │ │ │ ├── cbx_2__1_.xml │ │ │ │ ├── cbx_2__2_.xml │ │ │ │ ├── cby_0__0_.xml │ │ │ │ ├── cby_0__1_.xml │ │ │ │ ├── cby_0__2_.xml │ │ │ │ ├── cby_0__3_.xml │ │ │ │ ├── cby_1__0_.xml │ │ │ │ ├── cby_1__1_.xml │ │ │ │ ├── cby_1__2_.xml │ │ │ │ ├── cby_1__3_.xml │ │ │ │ ├── cby_2__0_.xml │ │ │ │ ├── cby_2__1_.xml │ │ │ │ ├── cby_2__2_.xml │ │ │ │ ├── cby_2__3_.xml │ │ │ │ ├── sb_0__0_.xml │ │ │ │ ├── sb_0__1_.xml │ │ │ │ ├── sb_0__2_.xml │ │ │ │ ├── sb_1__0_.xml │ │ │ │ ├── sb_1__1_.xml │ │ │ │ ├── sb_1__2_.xml │ │ │ │ ├── sb_2__0_.xml │ │ │ │ ├── sb_2__1_.xml │ │ │ │ └── sb_2__2_.xml │ │ │ │ ├── lb │ │ │ │ ├── grid_clb.v │ │ │ │ ├── grid_io_bottom.v │ │ │ │ ├── grid_io_left.v │ │ │ │ ├── grid_io_right.v │ │ │ │ ├── grid_io_top.v │ │ │ │ ├── logical_tile_clb_mode_clb_.v │ │ │ │ ├── logical_tile_clb_mode_default__fle.v │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric.v │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v │ │ │ │ ├── logical_tile_io_mode_io_.v │ │ │ │ └── logical_tile_io_mode_physical__iopad.v │ │ │ │ ├── logical_tile_clb_mode_clb_.sdc │ │ │ │ ├── logical_tile_clb_mode_default__fle.sdc │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.sdc │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc │ │ │ │ ├── logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc │ │ │ │ ├── logical_tile_io_mode_io_.sdc │ │ │ │ ├── mux_modules.yaml │ │ │ │ ├── pin_mapping.xml │ │ │ │ ├── routing │ │ │ │ ├── cbx_1__0_.v │ │ │ │ ├── cbx_1__1_.v │ │ │ │ ├── cbx_1__2_.v │ │ │ │ ├── cby_0__1_.v │ │ │ │ ├── cby_1__1_.v │ │ │ │ ├── cby_2__1_.v │ │ │ │ ├── sb_0__0_.v │ │ │ │ ├── sb_0__1_.v │ │ │ │ ├── sb_0__2_.v │ │ │ │ ├── sb_1__0_.v │ │ │ │ ├── sb_1__1_.v │ │ │ │ ├── sb_1__2_.v │ │ │ │ ├── sb_2__0_.v │ │ │ │ ├── sb_2__1_.v │ │ │ │ └── sb_2__2_.v │ │ │ │ ├── sb_0__0_.sdc │ │ │ │ ├── sb_0__1_.sdc │ │ │ │ ├── sb_0__2_.sdc │ │ │ │ ├── sb_1__0_.sdc │ │ │ │ ├── sb_1__1_.sdc │ │ │ │ ├── sb_1__2_.sdc │ │ │ │ ├── sb_2__0_.sdc │ │ │ │ ├── sb_2__1_.sdc │ │ │ │ ├── sb_2__2_.sdc │ │ │ │ └── sub_module │ │ │ │ ├── arch_encoder.v │ │ │ │ ├── inv_buf_passgate.v │ │ │ │ ├── local_encoder.v │ │ │ │ ├── luts.v │ │ │ │ ├── memories.v │ │ │ │ ├── mux_primitives.v │ │ │ │ ├── muxes.v │ │ │ │ ├── shift_register_banks.v │ │ │ │ ├── user_defined_templates.v │ │ │ │ └── wires.v │ │ ├── preconfig_testbench │ │ │ ├── configuration_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_config_done_io │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_le │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_chain_no_time_stamp │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── configuration_frame │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── flatten_memory │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fpga_core_wrapper │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fpga_core_wrapper_naming_rules │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── wrapper_io_naming.xml │ │ │ ├── fpga_core_wrapper_naming_rules_use_core_tb │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── wrapper_io_naming.xml │ │ │ ├── memory_bank │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── preconfigured_testbench_without_self_checking │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── preload_rr_graph │ │ │ ├── preload_rr_graph_bin │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── preload_rr_graph_xml │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── preload_unique_blocks │ │ │ ├── read_bin_write_xml │ │ │ │ ├── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ │ └── read_unique_block.bin │ │ │ ├── read_unique_blocks_bin │ │ │ │ ├── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ │ └── read_unique_block.bin │ │ │ ├── read_unique_blocks_full_flow │ │ │ │ ├── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ │ └── read_unique_block.xml │ │ │ ├── read_write_unique_blocks │ │ │ │ ├── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ │ └── read_unique_block.xml │ │ │ ├── read_write_unique_blocks_bin │ │ │ │ ├── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ │ └── read_unique_block.bin │ │ │ ├── write_bin_unique_blocks_full_flow │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ └── write_unique_blocks_full_flow │ │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── report_reference │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── source_command │ │ │ ├── source_file │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── source_string │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── systemverilog │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── tile_organization │ │ │ ├── bottom_right_custom_pins │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fabric_tile_clkntwk_io_subtile │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── fabric_tile_clkntwk_io_subtile_little_endian │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── fabric_tile_clkntwk_registerable_io_subtile │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── fabric_tile_global_tile_clock_io_subtile │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── fabric_tile_perimeter_cb_global_tile_clock │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── fabric_tile_perimeter_cb_pb_pin_fixup │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── hetero_fabric_tile │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_2x2_preconfig │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_4x4_preconfig │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_adder_chain │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_bl │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_clkntwk │ │ │ │ └── config │ │ │ │ │ ├── clk_arch_1clk_2layer.xml │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_ecb_2x2_preconfig │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_global_tile_clock │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── homo_fabric_tile_preconfig │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── io_subtile │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── io_subtile_strong │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── perimeter_cb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── tileable_io │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── top_left_custom_pins │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── top_right_custom_pins │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── verific_test │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── vpr_standalone │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── write_fabric_hierarchy │ │ │ └── module_filter │ │ │ │ └── config │ │ │ │ ├── module_names.xml │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── write_fabric_pin_phy_loc │ │ │ ├── write_fabric_pin_phy_loc_default │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── write_fabric_pin_phy_loc_for_tiles │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ ├── write_fabric_pin_phy_loc_show_invalid_sides │ │ │ │ └── config │ │ │ │ │ ├── task.conf │ │ │ │ │ └── tile_config.xml │ │ │ └── write_fabric_pin_phy_loc_wildcards │ │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── write_gsb │ │ │ ├── write_gsb_to_xml │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_compress_routing │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_cbx │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_cbx_cby │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_cby │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_rr_info │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_sb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_sb_cbx │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_exclude_sb_cby │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_include_sb_cbx_cby │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_include_single_cbx │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_include_single_cby │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_gsb_to_xml_include_single_sb │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── write_unique_gsb_to_xml │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── write_unique_gsb_to_xml_compress_routing │ │ │ │ └── config │ │ │ │ └── task.conf │ │ └── yosys_only │ │ │ └── config │ │ │ └── task.conf │ ├── benchmark_sweep │ │ ├── counter128 │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── counter8 │ │ │ └── config │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ ├── pin_constraints_rst.xml │ │ │ │ └── task.conf │ │ ├── counter8_full_testbench │ │ │ └── config │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ ├── pin_constraints_resetb.xml │ │ │ │ ├── pin_constraints_rst.xml │ │ │ │ └── task.conf │ │ ├── fsm │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── iwls2005 │ │ │ └── config │ │ │ │ ├── iwls_benchmark_golden_results.csv │ │ │ │ ├── metric_checklist.csv │ │ │ │ └── task.conf │ │ ├── mac_units │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── mcnc_big20 │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── sapone │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── signal_gen │ │ │ └── config │ │ │ │ └── task.conf │ │ └── vtr_benchmarks │ │ │ └── config │ │ │ ├── metric_checklist.csv │ │ │ ├── task.conf │ │ │ └── vtr_benchmark_golden_results.csv │ ├── compilation_verification │ │ └── config │ │ │ └── task.conf │ ├── fpga_bitstream │ │ ├── dont_care_bits │ │ │ ├── ql_memory_bank_flatten │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── ql_memory_bank_shift_register │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── extract_dsp_mode_bit │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ ├── filter_value0 │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── filter_value1 │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── force_clock_tap_routing │ │ │ └── config │ │ │ │ ├── bitstream_setting.xml │ │ │ │ ├── clk_arch_2clk_2layer.xml │ │ │ │ ├── pin_constraints.xml │ │ │ │ ├── repack_constraints.xml │ │ │ │ └── task.conf │ │ ├── generate_bitstream │ │ │ ├── configuration_chain │ │ │ │ ├── device_48x48 │ │ │ │ │ └── config │ │ │ │ │ │ └── task.conf │ │ │ │ ├── device_96x96 │ │ │ │ │ └── config │ │ │ │ │ │ └── task.conf │ │ │ │ └── device_auto │ │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── fpga_core_wrapper │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── ql_memory_bank_shift_register │ │ │ │ ├── device_48x48 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ │ ├── device_72x72 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ │ └── device_auto │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── load_external_architecture_bitstream │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── overload_default_mode_bit │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ ├── overload_dsp_mode_bit │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ ├── overload_eblif_param │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ ├── overload_mux_default_path │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ ├── overwrite_bitstream │ │ │ └── device_4x4 │ │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ ├── test.openfpga │ │ │ │ └── test.py │ │ ├── path_only │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── repack_ignore_nets │ │ │ └── config │ │ │ │ ├── pin_constraints.xml │ │ │ │ ├── repack_design_constraints.xml │ │ │ │ ├── rst_on_lut_pc.xml │ │ │ │ ├── rst_on_lut_repack_dc.xml │ │ │ │ └── task.conf │ │ ├── repack_wire_lut │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── repack_wire_lut_strong │ │ │ └── config │ │ │ │ ├── pin_constraints.xml │ │ │ │ └── task.conf │ │ ├── report_bitstream_distribution │ │ │ ├── custom_depth │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── default_depth │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── trim_path │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ ├── value_only │ │ │ └── config │ │ │ │ ├── task.conf │ │ │ │ └── tile_config.xml │ │ └── write_io_mapping │ │ │ └── config │ │ │ └── task.conf │ ├── fpga_sdc │ │ └── sdc_time_unit │ │ │ ├── sdc_time_unit_Ms │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_as │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_default │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_fs │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_ks │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_ms │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_ns │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── sdc_time_unit_ps │ │ │ └── config │ │ │ │ └── task.conf │ │ │ └── sdc_time_unit_us │ │ │ └── config │ │ │ └── task.conf │ ├── fpga_spice │ │ └── generate_spice │ │ │ └── config │ │ │ └── task.conf │ ├── fpga_verilog │ │ ├── adder │ │ │ ├── hard_adder │ │ │ │ └── config │ │ │ │ │ ├── dummy_pin_constraints.xml │ │ │ │ │ └── task.conf │ │ │ └── soft_adder │ │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ ├── bram │ │ │ ├── dpram1k │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── wide_dpram1k │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── depopulate_crossbar │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── dsp │ │ │ ├── dual_mult_8x8_chain_dpram16k_negz │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── mult_8x8_chain_dpram16k │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── mult_8x8_chain_dpram16k_negz │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── mult_8x8_chain_dpram16k_supertile │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── mult_8x8_chain_dpram16k_supertile_negz │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_mode_mult_16x16 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_mode_regin_mult_16x16 │ │ │ │ └── config │ │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ │ └── task.conf │ │ │ ├── single_mode_mult_8x8 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── single_mode_mult_8x8_reg │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── wide_multi_mode_mult_16x16 │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── duplicated_grid_pin │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── fabric_chain │ │ │ ├── adder_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── register_chain │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── scan_chain │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── flatten_routing │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── fully_connected_output_crossbar │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── io │ │ │ ├── aib │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── embedded_io │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── multi_io_capacity │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── reduced_io │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── registerable_io │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── soc_io │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── lut_design │ │ │ ├── frac_lut4 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── frac_lut4_and_switch │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── frac_lut4_arith │ │ │ │ └── config │ │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ │ └── task.conf │ │ │ ├── frac_lut6 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── frac_native_lut4 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── intermediate_buffer │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── single_mode │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── mux_design │ │ │ ├── const_input_gnd │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── debuf_mux │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── inbuf_only_mux │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── local_encoder │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── no_const_input │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── outbuf_only_mux │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── stdcell_mux2 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── stdcell_mux2_last_stage │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ ├── stdcell_mux2_last_stage_size2 │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── tree_structure │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── power_gated_design │ │ │ └── power_gated_inverter │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── rr_concat_wire │ │ │ └── config │ │ │ │ ├── bus_group_gen.py │ │ │ │ ├── counter8_bus_group_task.yaml │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ └── task.conf │ │ ├── spypad │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── thru_channel │ │ │ ├── thru_narrow_tile │ │ │ │ └── config │ │ │ │ │ └── task.conf │ │ │ └── thru_wide_tile │ │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── untileable │ │ │ └── config │ │ │ │ └── task.conf │ │ └── verilog_netlist_formats │ │ │ ├── behavioral_verilog │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── behavioral_verilog_default_nettype_wire │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── behavioral_verilog_little_endian │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── embed_bitstream_modelsim │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── embed_bitstream_none │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── explicit_port_mapping_default_nettype_wire │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── explicit_port_mapping_default_nettype_wire_little_endian │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── implicit_verilog │ │ │ └── config │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ └── task.conf │ │ │ ├── implicit_verilog_default_nettype_wire │ │ │ └── config │ │ │ │ ├── pin_constraints_reset.xml │ │ │ │ └── task.conf │ │ │ ├── preconfig_testbench_use_relative_path │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── synthesizable_verilog │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── synthesizable_verilog_little_endian │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── undriven_input_bit0 │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── undriven_input_bit1 │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── undriven_input_bus0 │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── undriven_input_bus1 │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── undriven_input_none │ │ │ └── config │ │ │ │ └── task.conf │ │ │ ├── undriven_input_none_force │ │ │ └── config │ │ │ │ └── task.conf │ │ │ └── use_relative_path │ │ │ └── config │ │ │ └── task.conf │ ├── quicklogic_tests │ │ ├── counter_5clock_test │ │ │ └── config │ │ │ │ ├── pin_constraints.xml │ │ │ │ ├── repack_pin_constraints.xml │ │ │ │ └── task.conf │ │ ├── flow_test │ │ │ └── config │ │ │ │ └── task.conf │ │ ├── lut_adder_test │ │ │ └── config │ │ │ │ ├── bitstream_annotation.xml │ │ │ │ └── task.conf │ │ └── sdc_controller_test │ │ │ └── config │ │ │ ├── pin_constraints.xml │ │ │ ├── repack_pin_constraints.xml │ │ │ └── task.conf │ └── template_tasks │ │ ├── fabric_netlist_gen_template │ │ ├── arch │ │ │ ├── openfpga_arch.xml │ │ │ └── vpr_arch.xml │ │ ├── config │ │ │ └── task.conf │ │ ├── example_script.openfpga │ │ └── micro_benchmark │ │ │ ├── and2 │ │ │ ├── and2.act │ │ │ ├── and2.blif │ │ │ ├── and2.eblif │ │ │ ├── and2.v │ │ │ ├── and2_frac_lut4_arith.eblif │ │ │ └── and2_verific.blif │ │ │ └── blinking │ │ │ └── blinking.v │ │ ├── fabric_verification_template │ │ ├── arch │ │ │ ├── openfpga_arch.xml │ │ │ └── vpr_arch.xml │ │ ├── config │ │ │ └── task.conf │ │ ├── example_script.openfpga │ │ └── micro_benchmark │ │ │ ├── and2 │ │ │ ├── and2.act │ │ │ ├── and2.blif │ │ │ ├── and2.eblif │ │ │ ├── and2.v │ │ │ ├── and2_frac_lut4_arith.eblif │ │ │ └── and2_verific.blif │ │ │ ├── blinking │ │ │ └── blinking.v │ │ │ └── mult8 │ │ │ └── mult8.v │ │ ├── frac-lut-arch-explore_template │ │ ├── config │ │ │ └── task.conf │ │ ├── k6_N10_tileable.xml │ │ ├── k6_frac_N10_tileable.xml │ │ ├── openfpga_arch.xml │ │ └── vtr_benchmark_template_script.openfpga │ │ └── vtr_benchmarks_template │ │ ├── config │ │ └── task.conf │ │ ├── k6_N10_tileable_dpram8K_dsp36_40nm.xml │ │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml │ │ └── vtr_benchmark_template_script.openfpga ├── tech │ ├── PTM_130nm │ │ ├── 130nm.pm │ │ ├── 130nm.xml │ │ └── readme.txt │ ├── PTM_22nm │ │ ├── 22nm.pm │ │ ├── 22nm.xml │ │ └── readme.txt │ ├── PTM_45nm │ │ ├── 45nm.pm │ │ ├── 45nm.xml │ │ └── readme.txt │ └── winbond90nm │ │ └── winbond90nm_power_properties.xml └── vpr_arch │ ├── Makefile │ ├── README.md │ ├── k4_N4_ecb_tileable_TileOrgzBl_40nm.xml │ ├── k4_N4_tileableIO_40nm.xml │ ├── k4_N4_tileableL_40nm.xml │ ├── k4_N4_tileable_40nm.xml │ ├── k4_N4_tileable_GlobalTile4Clk_40nm.xml │ ├── k4_N4_tileable_GlobalTile8Clk_40nm.xml │ ├── k4_N4_tileable_GlobalTileClk_40nm.xml │ ├── k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml │ ├── k4_N4_tileable_IoSubtile_40nm.xml │ ├── k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml │ ├── k4_N4_tileable_Ntwk1clk2lvl_40nm.xml │ ├── k4_N4_tileable_Ntwk2clk2lvl_40nm.xml │ ├── k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml │ ├── k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml │ ├── k4_N4_tileable_TileOrgzBr_40nm.xml │ ├── k4_N4_tileable_TileOrgzTl_40nm.xml │ ├── k4_N4_tileable_TileOrgzTr_40nm.xml │ ├── k4_N4_tileable_cnt8_40nm.xml │ ├── k4_N4_tileable_customIoLoc_40nm.xml │ ├── k4_N4_tileable_dsp8reg_40nm.xml │ ├── k4_N4_tileable_frac_dsp16_40nm.xml │ ├── k4_N4_tileable_full_output_crossbar_40nm.xml │ ├── k4_N4_tileable_no_local_routing_40nm.xml │ ├── k4_N5_tileable_pattern_local_routing_40nm.xml │ ├── k4_fracNative_N4_tileable_40nm.xml │ ├── k4_frac_N1_tileable_fracff_40nm.xml │ ├── k4_frac_N4_40nm.xml │ ├── k4_frac_N4_tileable_40nm.xml │ ├── k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml │ ├── k4_frac_N4_tileable_adder_chain_40nm.xml │ ├── k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml │ ├── k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml │ ├── k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml │ ├── k4_frac_N4_tileable_adder_chain_mem1K_L124_ChanWidth0p8_40nm.xml │ ├── k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml │ ├── k4_frac_N4_tileable_fracff2edge_40nm.xml │ ├── k4_frac_N4_tileable_fracff_40nm.xml │ ├── k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml │ ├── k4_frac_N4_tileable_fracff_localClkGen_40nm.xml │ ├── k4_frac_N4_tileable_fracff_localRstGen_40nm.xml │ ├── k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml │ ├── k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml │ ├── k4_frac_N4_tileable_lutram_40nm.xml │ ├── k4_frac_N8_tileableL_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem16K_negz_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_negz_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_supertile_negz_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_supertile_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_regin_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml │ ├── k4_frac_N8_tileable_reset_softadder_register_scan_chain_wide_frac_dsp16_nonLR_caravel_io_skywater130nm.xml │ ├── k6_N10_40nm.xml │ ├── k6_N10_tileable_40nm.xml │ ├── k6_frac_N10_40nm.xml │ ├── k6_frac_N10_adder_chain_40nm.xml │ ├── k6_frac_N10_adder_chain_mem16K_40nm.xml │ ├── k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml │ ├── k6_frac_N10_tileable_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_mem1K_40nm.xml │ ├── k6_frac_N10_tileable_adder_chain_wide_mem1K_40nm.xml │ ├── k6_frac_N10_tileable_adder_register_chain_40nm.xml │ ├── k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml │ ├── k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml │ ├── 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