├── .gitignore ├── .gitlab-ci.yml ├── .koji ├── CHANGELOG.rst ├── LICENSES ├── CC0-1.0.txt └── GPL-2.0.txt ├── Manifest.py ├── README.md ├── common.mk ├── distribution ├── .gitignore ├── Makefile ├── general-cores.spec └── rpmbuild.mk ├── doc ├── Makefile ├── drawings │ ├── vic_state.eps │ └── vic_state.pdf ├── fixinfo ├── gc_fsm_watchdog │ ├── Makefile │ ├── README.txt │ ├── cern-title.tex │ ├── fig │ │ ├── Makefile │ │ ├── cern-logo.svg │ │ ├── conn.svg │ │ ├── implem.svg │ │ └── ohwr-logo.svg │ ├── gc_fsm_watchdog.bib │ └── gc_fsm_watchdog.tex ├── gc_glitch_filt │ ├── Makefile │ ├── README.txt │ ├── cern-title.tex │ ├── fig │ │ ├── Makefile │ │ ├── cern-logo.svg │ │ ├── implem.svg │ │ └── ohwr-logo.svg │ ├── gc_glitch_filt.bib │ └── gc_glitch_filt.tex ├── gc_i2c_slave │ ├── Makefile │ ├── README.txt │ ├── cern-title.tex │ ├── fig │ │ ├── Makefile │ │ ├── cern-logo.svg │ │ ├── fsm-and-scl.svg │ │ ├── fsm-diag.svg │ │ ├── i2c-bitlevel.svg │ │ ├── i2c-bus.svg │ │ ├── i2c-ports.svg │ │ ├── i2c-slave-bd.svg │ │ ├── i2c-transf.svg │ │ └── ohwr-logo.svg │ ├── gc_i2c_slave.bib │ └── gc_i2c_slave.tex ├── general-cores.in ├── infofilter ├── wb_gpio_port_regs.in ├── wb_i2c_bridge │ ├── Makefile │ ├── README.txt │ ├── cern-title.tex │ ├── fig │ │ ├── Makefile │ │ ├── cern-logo.svg │ │ ├── fsm.svg │ │ ├── i2c-ports.svg │ │ ├── ohwr-logo.svg │ │ ├── sys.svg │ │ ├── sysmon-rd-fsm.svg │ │ ├── sysmon-rd.svg │ │ ├── sysmon-wr-fsm.svg │ │ ├── sysmon-wr.svg │ │ └── writemregs.svg │ ├── wb_i2c_bridge.bib │ └── wb_i2c_bridge.tex ├── wb_onewire_master.pdf ├── wb_spi.pdf ├── wb_vic_regs.in ├── wb_xil_multiboot │ ├── Makefile │ ├── README.txt │ ├── cern-title.tex │ ├── fig │ │ ├── Makefile │ │ ├── cern-logo.svg │ │ ├── fsm.svg │ │ ├── inst-clkcross.svg │ │ ├── multiboot-bd.svg │ │ ├── multiboot.svg │ │ ├── multiple-spi.svg │ │ ├── ohwr-logo.svg │ │ └── spi-mode.svg │ ├── multiboot-regs.tex │ ├── xwb_xil_multiboot.bib │ └── xwb_xil_multiboot.tex └── wishbone.md ├── modules ├── axi │ ├── Manifest.py │ ├── axi4_pkg.vhd │ ├── axi4lite32_axi4full64_bridge │ │ ├── Manifest.py │ │ └── axi4lite32_axi4full64_bridge.vhd │ ├── axi4lite_wb_bridge │ │ ├── Manifest.py │ │ └── xaxi4lite_wb_bridge.vhd │ └── z7_axi_gpio_expander │ │ ├── Manifest.py │ │ └── axi_gpio_expander.vhd ├── common │ ├── Manifest.py │ ├── gc_arbitrated_mux.vhd │ ├── gc_async_counter_diff.vhd │ ├── gc_async_signals_input_stage.vhd │ ├── gc_bicolor_led_ctrl.vhd │ ├── gc_big_adder.vhd │ ├── gc_big_adder2.vhd │ ├── gc_comparator.vhd │ ├── gc_crc_gen.vhd │ ├── gc_dec_8b10b.vhd │ ├── gc_delay_gen.vhd │ ├── gc_delay_line.vhd │ ├── gc_ds182x_interface.vhd │ ├── gc_ds182x_readout │ │ ├── README.md │ │ └── gc_ds182x_readout.vhd │ ├── gc_dual_pi_controller.vhd │ ├── gc_dyn_extend_pulse.vhd │ ├── gc_dyn_glitch_filt.vhd │ ├── gc_edge_detect.vhd │ ├── gc_enc_8b10b.vhd │ ├── gc_ext_pulse_sync.vhd │ ├── gc_extend_pulse.vhd │ ├── gc_frequency_meter.vhd │ ├── gc_fsm_watchdog.vhd │ ├── gc_glitch_filt.vhd │ ├── gc_i2c_slave.vhd │ ├── gc_moving_average.vhd │ ├── gc_multichannel_frequency_meter.vhd │ ├── gc_negedge.vhd │ ├── gc_posedge.vhd │ ├── gc_prio_encoder.vhd │ ├── gc_pulse_synchronizer.vhd │ ├── gc_pulse_synchronizer2.vhd │ ├── gc_reset.vhd │ ├── gc_reset_multi_aasd.vhd │ ├── gc_rr_arbiter.vhd │ ├── gc_serial_dac.vhd │ ├── gc_sfp_i2c_adapter.vhd │ ├── gc_simple_spi_master.vhd │ ├── gc_single_reset_gen.vhd │ ├── gc_sync.vhd │ ├── gc_sync_ffs.vhd │ ├── gc_sync_register.vhd │ ├── gc_sync_word_rd.vhd │ ├── gc_sync_word_wr.vhd │ ├── gc_word_packer.vhd │ ├── gencores_pkg.vhd │ └── matrix_pkg.vhd ├── genrams │ ├── .gitignore │ ├── Manifest.py │ ├── altera │ │ ├── Manifest.py │ │ ├── altera_async_fifo.vhd │ │ ├── altera_sync_fifo.vhd │ │ ├── gc_shiftreg.vhd │ │ ├── generic_dpram.vhd │ │ ├── generic_dpram_mixed.vhd │ │ ├── generic_simple_dpram.vhd │ │ └── generic_spram.vhd │ ├── cheby │ │ ├── Manifest.py │ │ ├── cheby_dpssram.vhd │ │ └── cheby_pkg.vhd │ ├── common │ │ ├── Manifest.py │ │ ├── generic_rom.vhd │ │ ├── generic_shiftreg_fifo.vhd │ │ ├── inferred_async_fifo.vhd │ │ ├── inferred_async_fifo_dual_rst.vhd │ │ ├── inferred_async_fwft_fifo.vhd │ │ └── inferred_sync_fifo.vhd │ ├── generic │ │ ├── Manifest.py │ │ ├── generic_async_fifo.vhd │ │ ├── generic_async_fifo_dual_rst.vhd │ │ └── generic_sync_fifo.vhd │ ├── genram_pkg.vhd │ ├── memory_loader_pkg.vhd │ └── xilinx │ │ ├── Manifest.py │ │ ├── gc_shiftreg.vhd │ │ ├── generic_dpram.vhd │ │ ├── generic_dpram_dualclock.vhd │ │ ├── generic_dpram_sameclock.vhd │ │ ├── generic_dpram_split.vhd │ │ ├── generic_simple_dpram.vhd │ │ ├── generic_spram.vhd │ │ ├── series7 │ │ ├── Manifest.py │ │ ├── generic_async_fifo.vhd │ │ ├── generic_async_fifo_dual_rst.vhd │ │ ├── generic_sync_fifo.vhd │ │ ├── s7_fifo_pkg.vhd │ │ └── s7_hwfifo_wrapper.vhd │ │ └── virtex6 │ │ ├── Manifest.py │ │ ├── generic_async_fifo.vhd │ │ ├── generic_async_fifo_dual_rst.vhd │ │ ├── generic_sync_fifo.vhd │ │ ├── v6_fifo_pkg.vhd │ │ └── v6_hwfifo_wrapper.vhd └── wishbone │ ├── Manifest.py │ ├── wb16_to_wb32 │ ├── Manifest.py │ └── wb16_to_wb32.vhd │ ├── wb_async_bridge │ ├── Manifest.py │ ├── wb_async_bridge.vhd │ └── xwb_async_bridge.vhd │ ├── wb_axi4lite_bridge │ ├── Manifest.py │ ├── wb_axi4lite_bridge.vhd │ └── xwb_axi4lite_bridge.vhd │ ├── wb_bus_fanout │ ├── Manifest.py │ └── xwb_bus_fanout.vhd │ ├── wb_clock_crossing │ ├── Manifest.py │ ├── xwb_clock_bridge.vhd │ └── xwb_clock_crossing.vhd │ ├── wb_conmax │ ├── Manifest.py │ ├── wb_conmax_arb.vhd │ ├── wb_conmax_master_if.vhd │ ├── wb_conmax_msel.vhd │ ├── wb_conmax_pri_dec.vhd │ ├── wb_conmax_pri_enc.vhd │ ├── wb_conmax_rf.vhd │ ├── wb_conmax_slave_if.vhd │ ├── wb_conmax_top.vhd │ ├── wbconmax_pkg.vhd │ └── xwb_conmax.vhd │ ├── wb_crossbar │ ├── Manifest.py │ ├── sdb_rom.vhd │ ├── xwb_crossbar.vhd │ └── xwb_sdb_crossbar.vhd │ ├── wb_dma │ ├── Manifest.py │ ├── xwb_dma.vhd │ └── xwb_streamer.vhd │ ├── wb_dpram │ ├── Manifest.py │ ├── xwb_dpram.vhd │ └── xwb_dpram_mixed.vhd │ ├── wb_ds182x_readout │ ├── Manifest.py │ ├── wb_ds182x_regs.cheby │ ├── wb_ds182x_regs.vhd │ └── xwb_ds182x_readout.vhd │ ├── wb_fine_pulse_gen │ ├── Manifest.py │ ├── fine_pulse_gen_kintex7.vhd │ ├── fine_pulse_gen_kintex7_shared.vhd │ ├── fine_pulse_gen_kintexultrascale.vhd │ ├── fine_pulse_gen_kintexultrascale_shared.vhd │ ├── fine_pulse_gen_wb.vhd │ ├── fine_pulse_gen_wb.wb │ ├── fine_pulse_gen_wbgen2_pkg.vhd │ └── xwb_fine_pulse_gen.vhd │ ├── wb_gpio_port │ ├── Manifest.py │ ├── wb_gpio_port.vhd │ └── xwb_gpio_port.vhd │ ├── wb_i2c_bridge │ ├── Manifest.py │ └── wb_i2c_bridge.vhd │ ├── wb_i2c_master │ ├── Manifest.py │ ├── i2c_master_bit_ctrl.vhd │ ├── i2c_master_byte_ctrl.vhd │ ├── i2c_master_top.vhd │ ├── wb_i2c_master.vhd │ └── xwb_i2c_master.vhd │ ├── wb_indirect │ ├── Manifest.py │ ├── wb_indirect_regs.cheby │ ├── wb_indirect_regs.vhd │ └── xwb_indirect.vhd │ ├── wb_irq │ ├── Manifest.py │ ├── irqm_core.vhd │ ├── msidemo │ │ ├── Makefile │ │ ├── crt0.S │ │ ├── display.c │ │ ├── display.h │ │ ├── eca-msi.sh │ │ ├── irq.c │ │ ├── irq.h │ │ ├── linker.ld │ │ └── main.c │ ├── wb_irq_lm32.vhd │ ├── wb_irq_master.vhd │ ├── wb_irq_pkg.vhd │ ├── wb_irq_slave.vhd │ └── wb_irq_timer.vhd │ ├── wb_lm32 │ ├── Manifest.py │ ├── README.txt │ ├── gen_lmcores.py │ ├── generated │ │ ├── lm32_allprofiles.v │ │ └── xwb_lm32.vhd │ ├── lm32.profiles │ ├── platform │ │ ├── altera │ │ │ └── jtag_tap.v │ │ ├── generic │ │ │ ├── jtag_tap.v │ │ │ └── lm32_multiplier.v │ │ ├── kintex7 │ │ │ ├── jtag_tap.v │ │ │ └── lm32_multiplier.v │ │ ├── spartan6 │ │ │ ├── jtag_tap.v │ │ │ └── lm32_multiplier.v │ │ └── virtex6 │ │ │ └── jtag_tap.v │ └── src │ │ ├── jtag_cores.v │ │ ├── lm32_adder.v │ │ ├── lm32_addsub.v │ │ ├── lm32_cpu.v │ │ ├── lm32_dcache.v │ │ ├── lm32_debug.v │ │ ├── lm32_decoder.v │ │ ├── lm32_dp_ram.v │ │ ├── lm32_dp_ram.vhd │ │ ├── lm32_functions.v │ │ ├── lm32_icache.v │ │ ├── lm32_include.v │ │ ├── lm32_instruction_unit.v │ │ ├── lm32_interrupt.v │ │ ├── lm32_jtag.v │ │ ├── lm32_load_store_unit.v │ │ ├── lm32_logic_op.v │ │ ├── lm32_mc_arithmetic.v │ │ ├── lm32_ram.v │ │ ├── lm32_ram.vhd │ │ ├── lm32_shifter.v │ │ └── lm32_top.v │ ├── wb_metadata │ ├── Manifest.py │ └── xwb_metadata.vhd │ ├── wb_onewire_master │ ├── Manifest.py │ ├── sockit_owm.v │ ├── wb_onewire_master.vhd │ └── xwb_onewire_master.vhd │ ├── wb_register │ ├── Manifest.py │ ├── wb_skidpad.vhd │ ├── xwb_register.vhd │ └── xwb_register_link.vhd │ ├── wb_remapper │ ├── Manifest.py │ └── xwb_remapper.vhd │ ├── wb_serial_lcd │ ├── Manifest.py │ └── wb_serial_lcd.vhd │ ├── wb_simple_pwm │ ├── Manifest.py │ ├── simple_pwm_wb.vhd │ ├── simple_pwm_wb.wb │ ├── simple_pwm_wbgen2_pkg.vhd │ ├── wb_simple_pwm.vhd │ └── xwb_simple_pwm.vhd │ ├── wb_simple_timer │ ├── Manifest.py │ ├── wb_tics.vhd │ └── xwb_tics.vhd │ ├── wb_slave_adapter │ ├── Manifest.py │ └── wb_slave_adapter.vhd │ ├── wb_spi │ ├── Manifest.py │ ├── spi_clgen.v │ ├── spi_defines.v │ ├── spi_shift.v │ ├── spi_top.v │ ├── timescale.v │ ├── wb_spi.vhd │ └── xwb_spi.vhd │ ├── wb_spi_bidir │ ├── Manifest.py │ ├── bench │ │ ├── spi_slave_model.v │ │ ├── tb_spi_top.v │ │ ├── timescale.v │ │ └── wb_master_model.v │ ├── spi_bidir_clgen.v │ ├── spi_bidir_defines.v │ ├── spi_bidir_shift.v │ ├── spi_bidir_top.v │ ├── spi_top.wcfg │ ├── spi_top.xml │ ├── timescale.v │ ├── wb_spi.pdf │ ├── wb_spi_bidir.vhd │ └── xwb_spi_bidir.vhd │ ├── wb_spi_flash │ ├── Manifest.py │ └── wb_spi_flash.vhd │ ├── wb_split │ ├── Manifest.py │ └── xwb_split.vhd │ ├── wb_uart │ ├── Manifest.py │ ├── build_wb.sh │ ├── simple_uart_pkg.vhd │ ├── simple_uart_wb.vhd │ ├── simple_uart_wb.wb │ ├── uart_async_rx.vhd │ ├── uart_async_tx.vhd │ ├── uart_baud_gen.vhd │ ├── uart_wb_slave.vhd │ ├── wb_simple_uart.vhd │ └── xwb_simple_uart.vhd │ ├── wb_vic │ ├── Manifest.py │ ├── wb_vic.vhd │ ├── wb_vic_regs.cheby │ ├── wb_vic_regs.vhd │ └── xwb_vic.vhd │ ├── wb_xc7_fw_update │ ├── Manifest.py │ ├── wb_xc7_fw_update_regs.cheby │ ├── wb_xc7_fw_update_regs.vhd │ └── xwb_xc7_fw_update.vhd │ ├── wbgen2 │ ├── Manifest.py │ ├── wbgen2_dpssram.vhd │ ├── wbgen2_eic.vhd │ ├── wbgen2_fifo_async.vhd │ ├── wbgen2_fifo_sync.vhd │ └── wbgen2_pkg.vhd │ ├── wbgenplus │ ├── Manifest.py │ └── wbgenplus_pkg.vhd │ └── wishbone_pkg.vhd ├── platform ├── Manifest.py ├── altera │ ├── Manifest.py │ ├── flash │ │ ├── Manifest.py │ │ ├── altera_flash_pkg.vhd │ │ ├── altera_spi.vhd │ │ └── flash_top.vhd │ ├── networks │ │ ├── .gitignore │ │ ├── Manifest.py │ │ ├── altera_networks_pkg.vhd │ │ ├── arria2gx.tcl │ │ ├── arria2gx │ │ │ ├── dual_region.txt │ │ │ ├── global_region.txt │ │ │ └── single_region.txt │ │ ├── arria2gx_networks.qip │ │ ├── arria5.tcl │ │ ├── arria5 │ │ │ ├── dual_region.txt │ │ │ ├── global_region.txt │ │ │ └── single_region.txt │ │ └── arria5_networks.qip │ └── wb_pcie │ │ ├── .gitignore │ │ ├── Manifest.py │ │ ├── arria2.tcl │ │ ├── arria2_pcie.qip │ │ ├── arria2_pcie_hip.txt │ │ ├── arria2_pcie_reconf.txt │ │ ├── arria5.tcl │ │ ├── arria5_pcie.qip │ │ ├── arria5_pcie_hip.txt │ │ ├── arria5_pcie_reconf.txt │ │ ├── pcie_32to64.vhd │ │ ├── pcie_64to32.vhd │ │ ├── pcie_altera.vhd │ │ ├── pcie_tlp.vhd │ │ ├── pcie_wb.vhd │ │ └── pcie_wb_pkg.vhd └── xilinx │ ├── Manifest.py │ ├── wb_xil_multiboot │ ├── Manifest.py │ ├── multiboot_fsm.vhd │ ├── multiboot_regs.vhd │ ├── multiboot_regs.wb │ ├── spi_master.vhd │ └── xwb_xil_multiboot.vhd │ └── wb_xilinx_fpga_loader │ ├── Manifest.py │ ├── build_wb.sh │ ├── wb_xilinx_fpga_loader.vhd │ ├── xloader_registers_pkg.vhd │ ├── xloader_wb.vhd │ ├── xloader_wb.wb │ └── xwb_xilinx_fpga_loader.vhd ├── sim ├── gc_fsm_watchdog │ ├── run.do │ ├── tb_gc_fsm_watchdog.vhd │ └── wave.do ├── if_wb_link.svh ├── if_wb_master.svh ├── if_wb_slave.svh ├── if_wishbone_accessor.svh ├── if_wishbone_defs.svh ├── if_wishbone_types.svh ├── onewire_slave_model.v ├── regs │ └── xloader_regs.vh ├── simdrv_defs.svh ├── vhd_wishbone_master.svh ├── vhdl │ ├── Manifest.py │ ├── sim_wishbone.vhd │ └── sim_wishbone16.vhd └── wb_i2c_bridge │ ├── i2c_bus_model.vhd │ ├── i2c_master_bit_ctrl.vhd │ ├── i2c_master_byte_ctrl.vhd │ ├── run.do │ ├── tb_gc_i2c_slave.vhd │ ├── tb_wb_i2c_bridge.vhd │ ├── wave-i2cs.do │ └── wave.do ├── software ├── .gitignore ├── Makefile ├── dkms.conf ├── dkms.mk ├── htvic │ ├── Makefile │ ├── README.rst │ └── drivers │ │ ├── Kbuild │ │ ├── Makefile │ │ ├── htvic.c │ │ ├── htvic.h │ │ └── htvic_regs.h ├── i2c-ocores │ ├── .gitignore │ ├── Documentation │ │ └── i2c │ │ │ └── busses │ │ │ └── i2c-ocores │ ├── Makefile │ ├── README │ ├── drivers │ │ └── i2c │ │ │ └── busses │ │ │ ├── Kbuild │ │ │ ├── Makefile │ │ │ └── i2c-ocores.c │ └── include │ │ └── linux │ │ └── platform_data │ │ └── i2c-ocores.h └── spi-ocores │ ├── .gitignore │ ├── Makefile │ ├── drivers │ └── spi │ │ ├── Kbuild │ │ ├── Makefile │ │ └── spi-ocores.c │ └── include │ └── linux │ └── platform_data │ └── spi-ocores.h ├── syn └── gsi_pexaria2a │ └── wishbone_demo │ ├── Manifest.py │ ├── wishbone_demo.qpf │ └── wishbone_demo.qsf ├── testbench ├── axi │ └── z7_axi_gpio_expander │ │ ├── Manifest.py │ │ ├── gpio.cheby │ │ ├── gpio_axi.vhd │ │ ├── run.do │ │ ├── sim_top_ps_gpio.vhd │ │ └── wave.do ├── common │ ├── gc_bicolor_led_ctrl │ │ ├── .gitignore │ │ ├── Manifest.py │ │ ├── gc_bicolor_led_ctrl_tb.vhd │ │ ├── run.do │ │ └── wave.do │ ├── gc_comparator │ │ ├── .gitignore │ │ ├── Manifest.py │ │ ├── gc_comparator_tb.gtkwave │ │ ├── gc_comparator_tb.vhd │ │ └── run_tb.sh │ ├── gc_ds182x_readout │ │ ├── Manifest.py │ │ └── gc_ds182x_readout_tb.vhd │ └── gc_moving_average │ │ ├── .gitignore │ │ ├── Manifest.py │ │ └── gc_moving_average_tb.vhd └── wishbone │ ├── gc_sync_word_wr │ ├── run.do │ ├── tb_gc_sync_word_wr.vhd │ └── wave.do │ ├── include │ └── wb_fine_pulse_gen_regs.vh │ ├── lm32_testsys │ ├── Manifest.py │ ├── lm32_test_system.vhd │ ├── main.sv │ ├── run.do │ ├── sw │ │ ├── Makefile │ │ ├── board.h │ │ ├── genraminit.c │ │ ├── gpio.h │ │ ├── inttypes.h │ │ ├── main.c │ │ ├── main.ram │ │ ├── target │ │ │ └── lm32 │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.c │ │ │ │ └── ram.ld │ │ ├── uart.c │ │ ├── uart.h │ │ ├── wb_uart.h │ │ └── wb_vuart.h │ └── wave.do │ ├── wb16_to_wb32 │ ├── tb.gtkw │ └── tb_wb16_to_wb32.vhd │ ├── wb_fine_pulse_gen │ ├── Manifest.py │ ├── main.sv │ └── run.do │ ├── wb_gpio_port │ ├── .gitignore │ ├── Manifest.py │ ├── main.sv │ ├── run.do │ └── wave.do │ ├── wb_indirect │ ├── Manifest.py │ ├── tb_indirect.gtkw │ └── tb_wb_indirect.vhd │ ├── wb_simple_pwm │ ├── Manifest.py │ ├── main.sv │ ├── run.do │ └── wave.do │ ├── wb_spi │ ├── Manifest.py │ ├── run.do │ └── tb_spi.vhd │ ├── wb_uart │ ├── Manifest.py │ ├── main.sv │ ├── run.do │ └── wave.do │ └── wb_xilinx_fpga_loader │ ├── Manifest.py │ ├── SIM_CONFIG_S6_SERIAL.v │ ├── glbl.v │ ├── main.sv │ ├── run.do │ ├── sample_bitstream │ ├── Manifest.py │ ├── crc_gen.vhd │ └── test.xise │ └── wave.do ├── tools ├── gen_buildinfo.py ├── gen_sourceid.py ├── mem_init_gen.py └── sdb_desc_gen.tcl └── top └── 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