├── .gitattributes
├── CORE
├── core_cm3.c
├── core_cm3.h
├── startup_stm32f10x_hd.s
├── stm32f10x.h
├── stm32f10x_conf.h
├── system_stm32f10x.c
└── system_stm32f10x.h
├── FreeRTOS
├── croutine.c
├── event_groups.c
├── include
│ ├── FreeRTOS.h
│ ├── FreeRTOSConfig.h
│ ├── StackMacros.h
│ ├── croutine.h
│ ├── deprecated_definitions.h
│ ├── event_groups.h
│ ├── list.h
│ ├── mpu_prototypes.h
│ ├── mpu_wrappers.h
│ ├── portable.h
│ ├── projdefs.h
│ ├── queue.h
│ ├── semphr.h
│ ├── stdint.readme
│ ├── task.h
│ └── timers.h
├── list.c
├── portable
│ ├── Keil
│ │ └── See-also-the-RVDS-directory.txt
│ ├── MemMang
│ │ ├── ReadMe.url
│ │ ├── heap_1.c
│ │ ├── heap_2.c
│ │ ├── heap_3.c
│ │ ├── heap_4.c
│ │ └── heap_5.c
│ ├── RVDS
│ │ ├── ARM7_LPC21xx
│ │ │ ├── port.c
│ │ │ ├── portASM.s
│ │ │ ├── portmacro.h
│ │ │ └── portmacro.inc
│ │ ├── ARM_CA9
│ │ │ ├── port.c
│ │ │ ├── portASM.s
│ │ │ ├── portmacro.h
│ │ │ └── portmacro.inc
│ │ ├── ARM_CM0
│ │ │ ├── port.c
│ │ │ └── portmacro.h
│ │ ├── ARM_CM3
│ │ │ ├── port.c
│ │ │ └── portmacro.h
│ │ ├── ARM_CM4F
│ │ │ ├── port.c
│ │ │ └── portmacro.h
│ │ ├── ARM_CM4_MPU
│ │ │ ├── port.c
│ │ │ └── portmacro.h
│ │ └── ARM_CM7
│ │ │ ├── ReadMe.txt
│ │ │ └── r0p1
│ │ │ ├── port.c
│ │ │ └── portmacro.h
│ └── readme.txt
├── queue.c
├── readme.txt
├── tasks.c
└── timers.c
├── HARDWARE
├── ADC
│ ├── adc.c
│ └── adc.h
├── BEEP
│ ├── BEEP.c
│ └── BEEP.h
├── LCD
│ ├── FONT.H
│ ├── lcd.c
│ └── lcd.h
├── MTR_GPIO
│ ├── MTR_GPIO.c
│ └── MTR_GPIO.h
├── TIMER
│ ├── timer.c
│ └── timer.h
├── inc
│ ├── FONT.H
│ ├── adc.h
│ ├── bh1750.h
│ ├── control.h
│ ├── delay.h
│ ├── dht11.h
│ ├── lcd.h
│ ├── led.h
│ ├── mqtt.h
│ ├── stm32f10x_it.h
│ ├── timer3.h
│ ├── timer4.h
│ ├── usart1.h
│ ├── usart2.h
│ └── wifi.h
└── scr
│ ├── adc.c
│ ├── bh1750.c
│ ├── control.c
│ ├── delay.c
│ ├── dht11.c
│ ├── lcd.c
│ ├── led.c
│ ├── mqtt.c
│ ├── stm32f10x_adc.c
│ ├── stm32f10x_it.c
│ ├── timer3.c
│ ├── timer4.c
│ ├── usart1.c
│ ├── usart2.c
│ └── wifi.c
├── OBJ
├── MQTT_ONENET_ESP8266_STM32_FREERTOS_工程.dep
├── adc.crf
├── adc.d
├── adc.o
├── beep.crf
├── beep.d
├── beep.o
├── bh1750.crf
├── bh1750.d
├── bh1750.o
├── control.crf
├── control.d
├── control.o
├── core_cm3.crf
├── core_cm3.d
├── core_cm3.o
├── croutine.crf
├── croutine.d
├── croutine.o
├── delay.crf
├── delay.d
├── delay.o
├── dht11.crf
├── dht11.d
├── dht11.o
├── event_groups.crf
├── event_groups.d
├── event_groups.o
├── heap_4.crf
├── heap_4.d
├── heap_4.o
├── lcd.crf
├── lcd.d
├── lcd.o
├── led.crf
├── led.d
├── led.o
├── list.crf
├── list.d
├── list.o
├── main.crf
├── main.d
├── main.o
├── misc.crf
├── misc.d
├── misc.o
├── mqtt.crf
├── mqtt.d
├── mqtt.o
├── mtr_gpio.crf
├── mtr_gpio.d
├── mtr_gpio.o
├── port.crf
├── port.d
├── port.o
├── queue.crf
├── queue.d
├── queue.o
├── startup_stm32f10x_hd.d
├── startup_stm32f10x_hd.o
├── stm32f10x_adc.crf
├── stm32f10x_adc.d
├── stm32f10x_adc.o
├── stm32f10x_gpio.crf
├── stm32f10x_gpio.d
├── stm32f10x_gpio.o
├── stm32f10x_it.crf
├── stm32f10x_it.d
├── stm32f10x_it.o
├── stm32f10x_rcc.crf
├── stm32f10x_rcc.d
├── stm32f10x_rcc.o
├── stm32f10x_tim.crf
├── stm32f10x_tim.d
├── stm32f10x_tim.o
├── stm32f10x_usart.crf
├── stm32f10x_usart.d
├── stm32f10x_usart.o
├── sys.crf
├── sys.d
├── sys.o
├── system_stm32f10x.crf
├── system_stm32f10x.d
├── system_stm32f10x.o
├── tasks.crf
├── tasks.d
├── tasks.o
├── timer.crf
├── timer.d
├── timer.o
├── timer3.crf
├── timer3.d
├── timer3.o
├── timer4.crf
├── timer4.d
├── timer4.o
├── timers.crf
├── timers.d
├── timers.o
├── usart1.crf
├── usart1.d
├── usart1.o
├── usart2.crf
├── usart2.d
├── usart2.o
├── wifi.crf
├── wifi.d
├── wifi.o
├── 工程文件.axf
├── 工程文件.build_log.htm
├── 工程文件.hex
├── 工程文件.htm
└── 工程文件.lnp
├── README.md
├── STLIB
├── inc
│ ├── misc.h
│ ├── stm32f10x_adc.h
│ ├── stm32f10x_bkp.h
│ ├── stm32f10x_can.h
│ ├── stm32f10x_cec.h
│ ├── stm32f10x_crc.h
│ ├── stm32f10x_dac.h
│ ├── stm32f10x_dbgmcu.h
│ ├── stm32f10x_dma.h
│ ├── stm32f10x_exti.h
│ ├── stm32f10x_flash.h
│ ├── stm32f10x_fsmc.h
│ ├── stm32f10x_gpio.h
│ ├── stm32f10x_i2c.h
│ ├── stm32f10x_iwdg.h
│ ├── stm32f10x_pwr.h
│ ├── stm32f10x_rcc.h
│ ├── stm32f10x_rtc.h
│ ├── stm32f10x_sdio.h
│ ├── stm32f10x_spi.h
│ ├── stm32f10x_tim.h
│ ├── stm32f10x_usart.h
│ └── stm32f10x_wwdg.h
└── src
│ ├── misc.c
│ ├── stm32f10x_adc.c
│ ├── stm32f10x_bkp.c
│ ├── stm32f10x_can.c
│ ├── stm32f10x_cec.c
│ ├── stm32f10x_crc.c
│ ├── stm32f10x_dac.c
│ ├── stm32f10x_dbgmcu.c
│ ├── stm32f10x_dma.c
│ ├── stm32f10x_exti.c
│ ├── stm32f10x_flash.c
│ ├── stm32f10x_fsmc.c
│ ├── stm32f10x_gpio.c
│ ├── stm32f10x_i2c.c
│ ├── stm32f10x_iwdg.c
│ ├── stm32f10x_pwr.c
│ ├── stm32f10x_rcc.c
│ ├── stm32f10x_rtc.c
│ ├── stm32f10x_sdio.c
│ ├── stm32f10x_spi.c
│ ├── stm32f10x_tim.c
│ ├── stm32f10x_usart.c
│ └── stm32f10x_wwdg.c
├── SYS
├── sys.c
└── sys.h
├── USER
├── DebugConfig
│ └── _____STM32F103RC_1.0.0.dbgconf
├── MQTT_ONENET_ESP8266_STM32_FREERTOS.uvguix.heniec
├── MQTT_ONENET_ESP8266_STM32_FREERTOS.uvoptx
├── MQTT_ONENET_ESP8266_STM32_FREERTOS.uvprojx
├── main.c
├── startup_stm32f10x_hd.lst
└── 工程文件.map
└── images
├── app.png
├── code_process.png
├── data_stream.png
├── file.png
└── uart.png
/.gitattributes:
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1 | # Auto detect text files and perform LF normalization
2 | * text=auto
3 |
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/CORE/stm32f10x.h:
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/CORE/stm32f10x_conf.h:
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1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CONF_H
24 | #define __STM32F10x_CONF_H
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
28 | #include "stm32f10x_adc.h"
29 | #include "stm32f10x_bkp.h"
30 | #include "stm32f10x_can.h"
31 | #include "stm32f10x_cec.h"
32 | #include "stm32f10x_crc.h"
33 | #include "stm32f10x_dac.h"
34 | #include "stm32f10x_dbgmcu.h"
35 | #include "stm32f10x_dma.h"
36 | #include "stm32f10x_exti.h"
37 | #include "stm32f10x_flash.h"
38 | #include "stm32f10x_fsmc.h"
39 | #include "stm32f10x_gpio.h"
40 | #include "stm32f10x_i2c.h"
41 | #include "stm32f10x_iwdg.h"
42 | #include "stm32f10x_pwr.h"
43 | #include "stm32f10x_rcc.h"
44 | #include "stm32f10x_rtc.h"
45 | #include "stm32f10x_sdio.h"
46 | #include "stm32f10x_spi.h"
47 | #include "stm32f10x_tim.h"
48 | #include "stm32f10x_usart.h"
49 | #include "stm32f10x_wwdg.h"
50 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
51 |
52 | /* Exported types ------------------------------------------------------------*/
53 | /* Exported constants --------------------------------------------------------*/
54 | /* Uncomment the line below to expanse the "assert_param" macro in the
55 | Standard Peripheral Library drivers code */
56 | /* #define USE_FULL_ASSERT 1 */
57 |
58 | /* Exported macro ------------------------------------------------------------*/
59 | #ifdef USE_FULL_ASSERT
60 |
61 | /**
62 | * @brief The assert_param macro is used for function's parameters check.
63 | * @param expr: If expr is false, it calls assert_failed function which reports
64 | * the name of the source file and the source line number of the call
65 | * that failed. If expr is true, it returns no value.
66 | * @retval None
67 | */
68 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
69 | /* Exported functions ------------------------------------------------------- */
70 | void assert_failed(uint8_t* file, uint32_t line);
71 | #else
72 | #define assert_param(expr) ((void)0)
73 | #endif /* USE_FULL_ASSERT */
74 |
75 | #endif /* __STM32F10x_CONF_H */
76 |
77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
78 |
--------------------------------------------------------------------------------
/CORE/system_stm32f10x.h:
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1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /** @addtogroup CMSIS
23 | * @{
24 | */
25 |
26 | /** @addtogroup stm32f10x_system
27 | * @{
28 | */
29 |
30 | /**
31 | * @brief Define to prevent recursive inclusion
32 | */
33 | #ifndef __SYSTEM_STM32F10X_H
34 | #define __SYSTEM_STM32F10X_H
35 |
36 | #ifdef __cplusplus
37 | extern "C" {
38 | #endif
39 |
40 | /** @addtogroup STM32F10x_System_Includes
41 | * @{
42 | */
43 |
44 | /**
45 | * @}
46 | */
47 |
48 |
49 | /** @addtogroup STM32F10x_System_Exported_types
50 | * @{
51 | */
52 |
53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @addtogroup STM32F10x_System_Exported_Constants
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @addtogroup STM32F10x_System_Exported_Macros
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @addtogroup STM32F10x_System_Exported_Functions
76 | * @{
77 | */
78 |
79 | extern void SystemInit(void);
80 | extern void SystemCoreClockUpdate(void);
81 | /**
82 | * @}
83 | */
84 |
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 |
89 | #endif /*__SYSTEM_STM32F10X_H */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
99 |
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/FreeRTOS/include/FreeRTOSConfig.h:
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/FreeRTOS/include/stdint.readme:
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1 |
2 | #ifndef FREERTOS_STDINT
3 | #define FREERTOS_STDINT
4 |
5 | /*******************************************************************************
6 | * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions
7 | * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be
8 | * built using compilers that do not provide their own stdint.h definition.
9 | *
10 | * To use this file:
11 | *
12 | * 1) Copy this file into the directory that contains your FreeRTOSConfig.h
13 | * header file, as that directory will already be in the compilers include
14 | * path.
15 | *
16 | * 2) Rename the copied file stdint.h.
17 | *
18 | */
19 |
20 | typedef signed char int8_t;
21 | typedef unsigned char uint8_t;
22 | typedef short int16_t;
23 | typedef unsigned short uint16_t;
24 | typedef long int32_t;
25 | typedef unsigned long uint32_t;
26 |
27 | #endif /* FREERTOS_STDINT */
28 |
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/FreeRTOS/portable/Keil/See-also-the-RVDS-directory.txt:
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1 | Nothing to see here.
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/FreeRTOS/portable/MemMang/ReadMe.url:
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1 | [{000214A0-0000-0000-C000-000000000046}]
2 | Prop3=19,2
3 | [InternetShortcut]
4 | URL=http://www.freertos.org/a00111.html
5 | IDList=
6 |
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/FreeRTOS/portable/MemMang/heap_3.c:
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1 | /*
2 | FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
3 | All rights reserved
4 |
5 | VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
6 |
7 | This file is part of the FreeRTOS distribution.
8 |
9 | FreeRTOS is free software; you can redistribute it and/or modify it under
10 | the terms of the GNU General Public License (version 2) as published by the
11 | Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
12 |
13 | ***************************************************************************
14 | >>! NOTE: The modification to the GPL is included to allow you to !<<
15 | >>! distribute a combined work that includes FreeRTOS without being !<<
16 | >>! obliged to provide the source code for proprietary components !<<
17 | >>! outside of the FreeRTOS kernel. !<<
18 | ***************************************************************************
19 |
20 | FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
21 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
22 | FOR A PARTICULAR PURPOSE. Full license text is available on the following
23 | link: http://www.freertos.org/a00114.html
24 |
25 | ***************************************************************************
26 | * *
27 | * FreeRTOS provides completely free yet professionally developed, *
28 | * robust, strictly quality controlled, supported, and cross *
29 | * platform software that is more than just the market leader, it *
30 | * is the industry's de facto standard. *
31 | * *
32 | * Help yourself get started quickly while simultaneously helping *
33 | * to support the FreeRTOS project by purchasing a FreeRTOS *
34 | * tutorial book, reference manual, or both: *
35 | * http://www.FreeRTOS.org/Documentation *
36 | * *
37 | ***************************************************************************
38 |
39 | http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
40 | the FAQ page "My application does not run, what could be wrong?". Have you
41 | defined configASSERT()?
42 |
43 | http://www.FreeRTOS.org/support - In return for receiving this top quality
44 | embedded software for free we request you assist our global community by
45 | participating in the support forum.
46 |
47 | http://www.FreeRTOS.org/training - Investing in training allows your team to
48 | be as productive as possible as early as possible. Now you can receive
49 | FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
50 | Ltd, and the world's leading authority on the world's leading RTOS.
51 |
52 | http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
53 | including FreeRTOS+Trace - an indispensable productivity tool, a DOS
54 | compatible FAT file system, and our tiny thread aware UDP/IP stack.
55 |
56 | http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
57 | Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
58 |
59 | http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
60 | Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
61 | licenses offer ticketed support, indemnification and commercial middleware.
62 |
63 | http://www.SafeRTOS.com - High Integrity Systems also provide a safety
64 | engineered and independently SIL3 certified version for use in safety and
65 | mission critical applications that require provable dependability.
66 |
67 | 1 tab == 4 spaces!
68 | */
69 |
70 |
71 | /*
72 | * Implementation of pvPortMalloc() and vPortFree() that relies on the
73 | * compilers own malloc() and free() implementations.
74 | *
75 | * This file can only be used if the linker is configured to to generate
76 | * a heap memory area.
77 | *
78 | * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
79 | * memory management pages of http://www.FreeRTOS.org for more information.
80 | */
81 |
82 | #include
83 |
84 | /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
85 | all the API functions to use the MPU wrappers. That should only be done when
86 | task.h is included from an application file. */
87 | #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
88 |
89 | #include "FreeRTOS.h"
90 | #include "task.h"
91 |
92 | #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
93 |
94 | #if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
95 | #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
96 | #endif
97 |
98 | /*-----------------------------------------------------------*/
99 |
100 | void *pvPortMalloc( size_t xWantedSize )
101 | {
102 | void *pvReturn;
103 |
104 | vTaskSuspendAll();
105 | {
106 | pvReturn = malloc( xWantedSize );
107 | traceMALLOC( pvReturn, xWantedSize );
108 | }
109 | ( void ) xTaskResumeAll();
110 |
111 | #if( configUSE_MALLOC_FAILED_HOOK == 1 )
112 | {
113 | if( pvReturn == NULL )
114 | {
115 | extern void vApplicationMallocFailedHook( void );
116 | vApplicationMallocFailedHook();
117 | }
118 | }
119 | #endif
120 |
121 | return pvReturn;
122 | }
123 | /*-----------------------------------------------------------*/
124 |
125 | void vPortFree( void *pv )
126 | {
127 | if( pv )
128 | {
129 | vTaskSuspendAll();
130 | {
131 | free( pv );
132 | traceFREE( pv, 0 );
133 | }
134 | ( void ) xTaskResumeAll();
135 | }
136 | }
137 |
138 |
139 |
140 |
--------------------------------------------------------------------------------
/FreeRTOS/portable/RVDS/ARM7_LPC21xx/portASM.s:
--------------------------------------------------------------------------------
1 | ;/*
2 | ; FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
3 | ; All rights reserved
4 | ;
5 | ;
6 | ; ***************************************************************************
7 | ; * *
8 | ; * FreeRTOS tutorial books are available in pdf and paperback. *
9 | ; * Complete, revised, and edited pdf reference manuals are also *
10 | ; * available. *
11 | ; * *
12 | ; * Purchasing FreeRTOS documentation will not only help you, by *
13 | ; * ensuring you get running as quickly as possible and with an *
14 | ; * in-depth knowledge of how to use FreeRTOS, it will also help *
15 | ; * the FreeRTOS project to continue with its mission of providing *
16 | ; * professional grade, cross platform, de facto standard solutions *
17 | ; * for microcontrollers - completely free of charge! *
18 | ; * *
19 | ; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
20 | ; * *
21 | ; * Thank you for using FreeRTOS, and thank you for your support! *
22 | ; * *
23 | ; ***************************************************************************
24 | ;
25 | ;
26 | ; This file is part of the FreeRTOS distribution.
27 | ;
28 | ; FreeRTOS is free software; you can redistribute it and/or modify it under
29 | ; the terms of the GNU General Public License (version 2) as published by the
30 | ; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
31 | ; >>>NOTE<<< The modification to the GPL is included to allow you to
32 | ; distribute a combined work that includes FreeRTOS without being obliged to
33 | ; provide the source code for proprietary components outside of the FreeRTOS
34 | ; kernel. FreeRTOS is distributed in the hope that it will be useful, but
35 | ; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
36 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
37 | ; more details. You should have received a copy of the GNU General Public
38 | ; License and the FreeRTOS license exception along with FreeRTOS; if not it
39 | ; can be viewed here: http://www.freertos.org/a00114.html and also obtained
40 | ; by writing to Richard Barry, contact details for whom are available on the
41 | ; FreeRTOS WEB site.
42 | ;
43 | ; 1 tab == 4 spaces!
44 | ;
45 | ; http://www.FreeRTOS.org - Documentation, latest information, license and
46 | ; contact details.
47 | ;
48 | ; http://www.SafeRTOS.com - A version that is certified for use in safety
49 | ; critical systems.
50 | ;
51 | ; http://www.OpenRTOS.com - Commercial support, development, porting,
52 | ; licensing and training services.
53 | ;*/
54 |
55 | INCLUDE portmacro.inc
56 |
57 | IMPORT vTaskSwitchContext
58 | IMPORT xTaskIncrementTick
59 |
60 | EXPORT vPortYieldProcessor
61 | EXPORT vPortStartFirstTask
62 | EXPORT vPreemptiveTick
63 | EXPORT vPortYield
64 |
65 |
66 | VICVECTADDR EQU 0xFFFFF030
67 | T0IR EQU 0xE0004000
68 | T0MATCHBIT EQU 0x00000001
69 |
70 | ARM
71 | AREA PORT_ASM, CODE, READONLY
72 |
73 |
74 |
75 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
76 | ; Starting the first task is done by just restoring the context
77 | ; setup by pxPortInitialiseStack
78 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
79 | vPortStartFirstTask
80 |
81 | PRESERVE8
82 |
83 | portRESTORE_CONTEXT
84 |
85 | vPortYield
86 |
87 | PRESERVE8
88 |
89 | SVC 0
90 | bx lr
91 |
92 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
93 | ; Interrupt service routine for the SWI interrupt. The vector table is
94 | ; configured in the startup.s file.
95 | ;
96 | ; vPortYieldProcessor() is used to manually force a context switch. The
97 | ; SWI interrupt is generated by a call to taskYIELD() or portYIELD().
98 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
99 |
100 | vPortYieldProcessor
101 |
102 | PRESERVE8
103 |
104 | ; Within an IRQ ISR the link register has an offset from the true return
105 | ; address, but an SWI ISR does not. Add the offset manually so the same
106 | ; ISR return code can be used in both cases.
107 | ADD LR, LR, #4
108 |
109 | ; Perform the context switch.
110 | portSAVE_CONTEXT ; Save current task context
111 | LDR R0, =vTaskSwitchContext ; Get the address of the context switch function
112 | MOV LR, PC ; Store the return address
113 | BX R0 ; Call the contedxt switch function
114 | portRESTORE_CONTEXT ; restore the context of the selected task
115 |
116 |
117 |
118 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
119 | ; Interrupt service routine for preemptive scheduler tick timer
120 | ; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h
121 | ;
122 | ; Uses timer 0 of LPC21XX Family
123 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
124 |
125 | vPreemptiveTick
126 |
127 | PRESERVE8
128 |
129 | portSAVE_CONTEXT ; Save the context of the current task.
130 |
131 | LDR R0, =xTaskIncrementTick ; Increment the tick count.
132 | MOV LR, PC ; This may make a delayed task ready
133 | BX R0 ; to run.
134 |
135 | CMP R0, #0
136 | BEQ SkipContextSwitch
137 | LDR R0, =vTaskSwitchContext ; Find the highest priority task that
138 | MOV LR, PC ; is ready to run.
139 | BX R0
140 | SkipContextSwitch
141 | MOV R0, #T0MATCHBIT ; Clear the timer event
142 | LDR R1, =T0IR
143 | STR R0, [R1]
144 |
145 | LDR R0, =VICVECTADDR ; Acknowledge the interrupt
146 | STR R0,[R0]
147 |
148 | portRESTORE_CONTEXT ; Restore the context of the highest
149 | ; priority task that is ready to run.
150 | END
151 |
152 |
--------------------------------------------------------------------------------
/FreeRTOS/portable/RVDS/ARM7_LPC21xx/portmacro.inc:
--------------------------------------------------------------------------------
1 | ;/*
2 | ; FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
3 | ; All rights reserved
4 | ;
5 | ;
6 | ; ***************************************************************************
7 | ; * *
8 | ; * FreeRTOS tutorial books are available in pdf and paperback. *
9 | ; * Complete, revised, and edited pdf reference manuals are also *
10 | ; * available. *
11 | ; * *
12 | ; * Purchasing FreeRTOS documentation will not only help you, by *
13 | ; * ensuring you get running as quickly as possible and with an *
14 | ; * in-depth knowledge of how to use FreeRTOS, it will also help *
15 | ; * the FreeRTOS project to continue with its mission of providing *
16 | ; * professional grade, cross platform, de facto standard solutions *
17 | ; * for microcontrollers - completely free of charge! *
18 | ; * *
19 | ; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
20 | ; * *
21 | ; * Thank you for using FreeRTOS, and thank you for your support! *
22 | ; * *
23 | ; ***************************************************************************
24 | ;
25 | ;
26 | ; This file is part of the FreeRTOS distribution.
27 | ;
28 | ; FreeRTOS is free software; you can redistribute it and/or modify it under
29 | ; the terms of the GNU General Public License (version 2) as published by the
30 | ; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
31 | ; >>>NOTE<<< The modification to the GPL is included to allow you to
32 | ; distribute a combined work that includes FreeRTOS without being obliged to
33 | ; provide the source code for proprietary components outside of the FreeRTOS
34 | ; kernel. FreeRTOS is distributed in the hope that it will be useful, but
35 | ; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
36 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
37 | ; more details. You should have received a copy of the GNU General Public
38 | ; License and the FreeRTOS license exception along with FreeRTOS; if not it
39 | ; can be viewed here: http://www.freertos.org/a00114.html and also obtained
40 | ; by writing to Richard Barry, contact details for whom are available on the
41 | ; FreeRTOS WEB site.
42 | ;
43 | ; 1 tab == 4 spaces!
44 | ;
45 | ; http://www.FreeRTOS.org - Documentation, latest information, license and
46 | ; contact details.
47 | ;
48 | ; http://www.SafeRTOS.com - A version that is certified for use in safety
49 | ; critical systems.
50 | ;
51 | ; http://www.OpenRTOS.com - Commercial support, development, porting,
52 | ; licensing and training services.
53 | ;*/
54 |
55 | IMPORT ulCriticalNesting ;
56 | IMPORT pxCurrentTCB ;
57 |
58 |
59 | MACRO
60 | portRESTORE_CONTEXT
61 |
62 |
63 | LDR R0, =pxCurrentTCB ; Set the LR to the task stack. The location was...
64 | LDR R0, [R0] ; ... stored in pxCurrentTCB
65 | LDR LR, [R0]
66 |
67 | LDR R0, =ulCriticalNesting ; The critical nesting depth is the first item on...
68 | LDMFD LR!, {R1} ; ...the stack. Load it into the ulCriticalNesting var.
69 | STR R1, [R0] ;
70 |
71 | LDMFD LR!, {R0} ; Get the SPSR from the stack.
72 | MSR SPSR_cxsf, R0 ;
73 |
74 | LDMFD LR, {R0-R14}^ ; Restore all system mode registers for the task.
75 | NOP ;
76 |
77 | LDR LR, [LR, #+60] ; Restore the return address
78 |
79 | ; And return - correcting the offset in the LR to obtain ...
80 | SUBS PC, LR, #4 ; ...the correct address.
81 |
82 | MEND
83 |
84 | ; /**********************************************************************/
85 |
86 | MACRO
87 | portSAVE_CONTEXT
88 |
89 |
90 | STMDB SP!, {R0} ; Store R0 first as we need to use it.
91 |
92 | STMDB SP,{SP}^ ; Set R0 to point to the task stack pointer.
93 | NOP ;
94 | SUB SP, SP, #4 ;
95 | LDMIA SP!,{R0} ;
96 |
97 | STMDB R0!, {LR} ; Push the return address onto the stack.
98 | MOV LR, R0 ; Now we have saved LR we can use it instead of R0.
99 | LDMIA SP!, {R0} ; Pop R0 so we can save it onto the system mode stack.
100 |
101 | STMDB LR,{R0-LR}^ ; Push all the system mode registers onto the task stack.
102 | NOP ;
103 | SUB LR, LR, #60 ;
104 |
105 | MRS R0, SPSR ; Push the SPSR onto the task stack.
106 | STMDB LR!, {R0} ;
107 |
108 | LDR R0, =ulCriticalNesting ;
109 | LDR R0, [R0] ;
110 | STMDB LR!, {R0} ;
111 |
112 | LDR R0, =pxCurrentTCB ; Store the new top of stack for the task.
113 | LDR R1, [R0] ;
114 | STR LR, [R1] ;
115 |
116 | MEND
117 |
118 | END
119 |
--------------------------------------------------------------------------------
/FreeRTOS/portable/RVDS/ARM_CA9/portASM.s:
--------------------------------------------------------------------------------
1 | ;/*
2 | ; FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
3 | ; All rights reserved
4 | ;
5 | ;
6 | ; ***************************************************************************
7 | ; * *
8 | ; * FreeRTOS tutorial books are available in pdf and paperback. *
9 | ; * Complete, revised, and edited pdf reference manuals are also *
10 | ; * available. *
11 | ; * *
12 | ; * Purchasing FreeRTOS documentation will not only help you, by *
13 | ; * ensuring you get running as quickly as possible and with an *
14 | ; * in-depth knowledge of how to use FreeRTOS, it will also help *
15 | ; * the FreeRTOS project to continue with its mission of providing *
16 | ; * professional grade, cross platform, de facto standard solutions *
17 | ; * for microcontrollers - completely free of charge! *
18 | ; * *
19 | ; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
20 | ; * *
21 | ; * Thank you for using FreeRTOS, and thank you for your support! *
22 | ; * *
23 | ; ***************************************************************************
24 | ;
25 | ;
26 | ; This file is part of the FreeRTOS distribution.
27 | ;
28 | ; FreeRTOS is free software; you can redistribute it and/or modify it under
29 | ; the terms of the GNU General Public License (version 2) as published by the
30 | ; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
31 | ; >>>NOTE<<< The modification to the GPL is included to allow you to
32 | ; distribute a combined work that includes FreeRTOS without being obliged to
33 | ; provide the source code for proprietary components outside of the FreeRTOS
34 | ; kernel. FreeRTOS is distributed in the hope that it will be useful, but
35 | ; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
36 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
37 | ; more details. You should have received a copy of the GNU General Public
38 | ; License and the FreeRTOS license exception along with FreeRTOS; if not it
39 | ; can be viewed here: http://www.freertos.org/a00114.html and also obtained
40 | ; by writing to Richard Barry, contact details for whom are available on the
41 | ; FreeRTOS WEB site.
42 | ;
43 | ; 1 tab == 4 spaces!
44 | ;
45 | ; http://www.FreeRTOS.org - Documentation, latest information, license and
46 | ; contact details.
47 | ;
48 | ; http://www.SafeRTOS.com - A version that is certified for use in safety
49 | ; critical systems.
50 | ;
51 | ; http://www.OpenRTOS.com - Commercial support, development, porting,
52 | ; licensing and training services.
53 | ;*/
54 |
55 | INCLUDE portmacro.inc
56 |
57 | IMPORT vApplicationIRQHandler
58 | IMPORT vTaskSwitchContext
59 | IMPORT ulPortYieldRequired
60 | IMPORT ulPortInterruptNesting
61 | IMPORT vTaskSwitchContext
62 | IMPORT ulICCIAR
63 | IMPORT ulICCEOIR
64 |
65 | EXPORT FreeRTOS_SWI_Handler
66 | EXPORT FreeRTOS_IRQ_Handler
67 | EXPORT vPortRestoreTaskContext
68 |
69 | ARM
70 | AREA PORT_ASM, CODE, READONLY
71 |
72 |
73 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
74 | ; SVC handler is used to yield a task.
75 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
76 | FreeRTOS_SWI_Handler
77 |
78 | PRESERVE8
79 |
80 | ; Save the context of the current task and select a new task to run.
81 | portSAVE_CONTEXT
82 | LDR R0, =vTaskSwitchContext
83 | BLX R0
84 | portRESTORE_CONTEXT
85 |
86 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
87 | ; vPortRestoreTaskContext is used to start the scheduler.
88 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
89 | vPortRestoreTaskContext
90 | ; Switch to system mode
91 | CPS #SYS_MODE
92 | portRESTORE_CONTEXT
93 |
94 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
95 | ; PL390 GIC interrupt handler
96 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
97 | FreeRTOS_IRQ_Handler
98 |
99 | ; Return to the interrupted instruction.
100 | SUB lr, lr, #4
101 |
102 | ; Push the return address and SPSR
103 | PUSH {lr}
104 | MRS lr, SPSR
105 | PUSH {lr}
106 |
107 | ; Change to supervisor mode to allow reentry.
108 | CPS #SVC_MODE
109 |
110 | ; Push used registers.
111 | PUSH {r0-r4, r12}
112 |
113 | ; Increment nesting count. r3 holds the address of ulPortInterruptNesting
114 | ; for future use. r1 holds the original ulPortInterruptNesting value for
115 | ; future use.
116 | LDR r3, =ulPortInterruptNesting
117 | LDR r1, [r3]
118 | ADD r4, r1, #1
119 | STR r4, [r3]
120 |
121 | ; Read value from the interrupt acknowledge register, which is stored in r0
122 | ; for future parameter and interrupt clearing use.
123 | LDR r2, =ulICCIAR
124 | LDR r0, [r2]
125 |
126 | ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
127 | ; future use.
128 | MOV r2, sp
129 | AND r2, r2, #4
130 | SUB sp, sp, r2
131 |
132 | ; Call the interrupt handler
133 | PUSH {r0-r3, lr}
134 | LDR r1, =vApplicationIRQHandler
135 | BLX r1
136 | POP {r0-r3, lr}
137 | ADD sp, sp, r2
138 |
139 | CPSID i
140 |
141 | ; Write the value read from ICCIAR to ICCEOIR
142 | LDR r4, =ulICCEOIR
143 | STR r0, [r4]
144 |
145 | ; Restore the old nesting count
146 | STR r1, [r3]
147 |
148 | ; A context switch is never performed if the nesting count is not 0
149 | CMP r1, #0
150 | BNE exit_without_switch
151 |
152 | ; Did the interrupt request a context switch? r1 holds the address of
153 | ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
154 | ; use.
155 | LDR r1, =ulPortYieldRequired
156 | LDR r0, [r1]
157 | CMP r0, #0
158 | BNE switch_before_exit
159 |
160 | exit_without_switch
161 | ; No context switch. Restore used registers, LR_irq and SPSR before
162 | ; returning.
163 | POP {r0-r4, r12}
164 | CPS #IRQ_MODE
165 | POP {LR}
166 | MSR SPSR_cxsf, LR
167 | POP {LR}
168 | MOVS PC, LR
169 |
170 | switch_before_exit
171 | ; A context swtich is to be performed. Clear the context switch pending
172 | ; flag.
173 | MOV r0, #0
174 | STR r0, [r1]
175 |
176 | ; Restore used registers, LR-irq and SPSR before saving the context
177 | ; to the task stack.
178 | POP {r0-r4, r12}
179 | CPS #IRQ_MODE
180 | POP {LR}
181 | MSR SPSR_cxsf, LR
182 | POP {LR}
183 | portSAVE_CONTEXT
184 |
185 | ; Call the function that selects the new task to execute.
186 | ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
187 | ; instructions, or 8 byte aligned stack allocated data. LR does not need
188 | ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
189 | LDR r0, =vTaskSwitchContext
190 | BLX r0
191 |
192 | ; Restore the context of, and branch to, the task selected to execute next.
193 | portRESTORE_CONTEXT
194 |
195 |
196 | END
197 |
198 |
199 |
200 |
201 |
--------------------------------------------------------------------------------
/FreeRTOS/portable/RVDS/ARM_CA9/portmacro.inc:
--------------------------------------------------------------------------------
1 | ;/*
2 | ; FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
3 | ; All rights reserved
4 | ;
5 | ;
6 | ; ***************************************************************************
7 | ; * *
8 | ; * FreeRTOS tutorial books are available in pdf and paperback. *
9 | ; * Complete, revised, and edited pdf reference manuals are also *
10 | ; * available. *
11 | ; * *
12 | ; * Purchasing FreeRTOS documentation will not only help you, by *
13 | ; * ensuring you get running as quickly as possible and with an *
14 | ; * in-depth knowledge of how to use FreeRTOS, it will also help *
15 | ; * the FreeRTOS project to continue with its mission of providing *
16 | ; * professional grade, cross platform, de facto standard solutions *
17 | ; * for microcontrollers - completely free of charge! *
18 | ; * *
19 | ; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
20 | ; * *
21 | ; * Thank you for using FreeRTOS, and thank you for your support! *
22 | ; * *
23 | ; ***************************************************************************
24 | ;
25 | ;
26 | ; This file is part of the FreeRTOS distribution.
27 | ;
28 | ; FreeRTOS is free software; you can redistribute it and/or modify it under
29 | ; the terms of the GNU General Public License (version 2) as published by the
30 | ; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
31 | ; >>>NOTE<<< The modification to the GPL is included to allow you to
32 | ; distribute a combined work that includes FreeRTOS without being obliged to
33 | ; provide the source code for proprietary components outside of the FreeRTOS
34 | ; kernel. FreeRTOS is distributed in the hope that it will be useful, but
35 | ; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
36 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
37 | ; more details. You should have received a copy of the GNU General Public
38 | ; License and the FreeRTOS license exception along with FreeRTOS; if not it
39 | ; can be viewed here: http://www.freertos.org/a00114.html and also obtained
40 | ; by writing to Richard Barry, contact details for whom are available on the
41 | ; FreeRTOS WEB site.
42 | ;
43 | ; 1 tab == 4 spaces!
44 | ;
45 | ; http://www.FreeRTOS.org - Documentation, latest information, license and
46 | ; contact details.
47 | ;
48 | ; http://www.SafeRTOS.com - A version that is certified for use in safety
49 | ; critical systems.
50 | ;
51 | ; http://www.OpenRTOS.com - Commercial support, development, porting,
52 | ; licensing and training services.
53 | ;*/
54 |
55 | SYS_MODE EQU 0x1f
56 | SVC_MODE EQU 0x13
57 | IRQ_MODE EQU 0x12
58 |
59 | IMPORT ulCriticalNesting
60 | IMPORT pxCurrentTCB
61 | IMPORT ulPortTaskHasFPUContext
62 | IMPORT ulAsmAPIPriorityMask
63 | IMPORT ulICCPMR
64 |
65 |
66 | MACRO
67 | portSAVE_CONTEXT
68 |
69 | ; Save the LR and SPSR onto the system mode stack before switching to
70 | ; system mode to save the remaining system mode registers
71 | SRSDB sp!, #SYS_MODE
72 | CPS #SYS_MODE
73 | PUSH {R0-R12, R14}
74 |
75 | ; Push the critical nesting count
76 | LDR R2, =ulCriticalNesting
77 | LDR R1, [R2]
78 | PUSH {R1}
79 |
80 | ; Does the task have a floating point context that needs saving? If
81 | ; ulPortTaskHasFPUContext is 0 then no.
82 | LDR R2, =ulPortTaskHasFPUContext
83 | LDR R3, [R2]
84 | CMP R3, #0
85 |
86 | ; Save the floating point context, if any
87 | FMRXNE R1, FPSCR
88 | VPUSHNE {D0-D15}
89 | VPUSHNE {D16-D31}
90 | PUSHNE {R1}
91 |
92 | ; Save ulPortTaskHasFPUContext itself
93 | PUSH {R3}
94 |
95 | ; Save the stack pointer in the TCB
96 | LDR R0, =pxCurrentTCB
97 | LDR R1, [R0]
98 | STR SP, [R1]
99 |
100 | MEND
101 |
102 | ; /**********************************************************************/
103 |
104 | MACRO
105 | portRESTORE_CONTEXT
106 |
107 | ; Set the SP to point to the stack of the task being restored.
108 | LDR R0, =pxCurrentTCB
109 | LDR R1, [R0]
110 | LDR SP, [R1]
111 |
112 | ; Is there a floating point context to restore? If the restored
113 | ; ulPortTaskHasFPUContext is zero then no.
114 | LDR R0, =ulPortTaskHasFPUContext
115 | POP {R1}
116 | STR R1, [R0]
117 | CMP R1, #0
118 |
119 | ; Restore the floating point context, if any
120 | POPNE {R0}
121 | VPOPNE {D16-D31}
122 | VPOPNE {D0-D15}
123 | VMSRNE FPSCR, R0
124 |
125 | ; Restore the critical section nesting depth
126 | LDR R0, =ulCriticalNesting
127 | POP {R1}
128 | STR R1, [R0]
129 |
130 | ; Ensure the priority mask is correct for the critical nesting depth
131 | LDR R2, =ulICCPMR
132 | CMP R1, #0
133 | MOVEQ R4, #255
134 | LDRNE R4, =ulAsmAPIPriorityMask
135 | STR R4, [r2]
136 |
137 | ; Restore all system mode registers other than the SP (which is already
138 | ; being used)
139 | POP {R0-R12, R14}
140 |
141 | ; Return to the task code, loading CPSR on the way.
142 | RFEIA sp!
143 |
144 | MEND
145 |
146 | END
147 |
148 |
--------------------------------------------------------------------------------
/FreeRTOS/portable/RVDS/ARM_CM0/portmacro.h:
--------------------------------------------------------------------------------
1 | /*
2 | FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
3 | All rights reserved
4 |
5 | VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
6 |
7 | This file is part of the FreeRTOS distribution.
8 |
9 | FreeRTOS is free software; you can redistribute it and/or modify it under
10 | the terms of the GNU General Public License (version 2) as published by the
11 | Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
12 |
13 | ***************************************************************************
14 | >>! NOTE: The modification to the GPL is included to allow you to !<<
15 | >>! distribute a combined work that includes FreeRTOS without being !<<
16 | >>! obliged to provide the source code for proprietary components !<<
17 | >>! outside of the FreeRTOS kernel. !<<
18 | ***************************************************************************
19 |
20 | FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
21 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
22 | FOR A PARTICULAR PURPOSE. Full license text is available on the following
23 | link: http://www.freertos.org/a00114.html
24 |
25 | ***************************************************************************
26 | * *
27 | * FreeRTOS provides completely free yet professionally developed, *
28 | * robust, strictly quality controlled, supported, and cross *
29 | * platform software that is more than just the market leader, it *
30 | * is the industry's de facto standard. *
31 | * *
32 | * Help yourself get started quickly while simultaneously helping *
33 | * to support the FreeRTOS project by purchasing a FreeRTOS *
34 | * tutorial book, reference manual, or both: *
35 | * http://www.FreeRTOS.org/Documentation *
36 | * *
37 | ***************************************************************************
38 |
39 | http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
40 | the FAQ page "My application does not run, what could be wrong?". Have you
41 | defined configASSERT()?
42 |
43 | http://www.FreeRTOS.org/support - In return for receiving this top quality
44 | embedded software for free we request you assist our global community by
45 | participating in the support forum.
46 |
47 | http://www.FreeRTOS.org/training - Investing in training allows your team to
48 | be as productive as possible as early as possible. Now you can receive
49 | FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
50 | Ltd, and the world's leading authority on the world's leading RTOS.
51 |
52 | http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
53 | including FreeRTOS+Trace - an indispensable productivity tool, a DOS
54 | compatible FAT file system, and our tiny thread aware UDP/IP stack.
55 |
56 | http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
57 | Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
58 |
59 | http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
60 | Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
61 | licenses offer ticketed support, indemnification and commercial middleware.
62 |
63 | http://www.SafeRTOS.com - High Integrity Systems also provide a safety
64 | engineered and independently SIL3 certified version for use in safety and
65 | mission critical applications that require provable dependability.
66 |
67 | 1 tab == 4 spaces!
68 | */
69 |
70 |
71 | #ifndef PORTMACRO_H
72 | #define PORTMACRO_H
73 |
74 | #ifdef __cplusplus
75 | extern "C" {
76 | #endif
77 |
78 | /*-----------------------------------------------------------
79 | * Port specific definitions.
80 | *
81 | * The settings in this file configure FreeRTOS correctly for the
82 | * given hardware and compiler.
83 | *
84 | * These settings should not be altered.
85 | *-----------------------------------------------------------
86 | */
87 |
88 | /* Type definitions. */
89 | #define portCHAR char
90 | #define portFLOAT float
91 | #define portDOUBLE double
92 | #define portLONG long
93 | #define portSHORT short
94 | #define portSTACK_TYPE uint32_t
95 | #define portBASE_TYPE long
96 |
97 | typedef portSTACK_TYPE StackType_t;
98 | typedef long BaseType_t;
99 | typedef unsigned long UBaseType_t;
100 |
101 | #if( configUSE_16_BIT_TICKS == 1 )
102 | typedef uint16_t TickType_t;
103 | #define portMAX_DELAY ( TickType_t ) 0xffff
104 | #else
105 | typedef uint32_t TickType_t;
106 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
107 |
108 | /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
109 | not need to be guarded with a critical section. */
110 | #define portTICK_TYPE_IS_ATOMIC 1
111 | #endif
112 | /*-----------------------------------------------------------*/
113 |
114 | /* Architecture specifics. */
115 | #define portSTACK_GROWTH ( -1 )
116 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
117 | #define portBYTE_ALIGNMENT 8
118 | /*-----------------------------------------------------------*/
119 |
120 |
121 | /* Scheduler utilities. */
122 | extern void vPortYield( void );
123 | #define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
124 | #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
125 | #define portYIELD() vPortYield()
126 | #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
127 | #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
128 | /*-----------------------------------------------------------*/
129 |
130 | /* Critical section management. */
131 | extern void vPortEnterCritical( void );
132 | extern void vPortExitCritical( void );
133 | extern uint32_t ulSetInterruptMaskFromISR( void );
134 | extern void vClearInterruptMaskFromISR( uint32_t ulMask );
135 |
136 | #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
137 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
138 | #define portDISABLE_INTERRUPTS() __disable_irq()
139 | #define portENABLE_INTERRUPTS() __enable_irq()
140 | #define portENTER_CRITICAL() vPortEnterCritical()
141 | #define portEXIT_CRITICAL() vPortExitCritical()
142 |
143 | /*-----------------------------------------------------------*/
144 |
145 | /* Task function macros as described on the FreeRTOS.org WEB site. */
146 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
147 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
148 |
149 | #define portNOP()
150 |
151 | #ifdef __cplusplus
152 | }
153 | #endif
154 |
155 | #endif /* PORTMACRO_H */
156 |
157 |
--------------------------------------------------------------------------------
/FreeRTOS/portable/RVDS/ARM_CM7/ReadMe.txt:
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1 | There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
2 | The best option depends on the revision of the ARM Cortex-M7 core in use. The
3 | revision is specified by an 'r' number, and a 'p' number, so will look something
4 | like 'r0p1'. Check the documentation for the microcontroller in use to find the
5 | revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
6 | the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
7 | with all core revisions.
8 |
9 | The first option is to use the ARM Cortex-M4F port, and the second option is to
10 | use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
11 |
12 | If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
13 | used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
14 | the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.
15 |
16 | If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
17 | Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1
18 | directory.
--------------------------------------------------------------------------------
/FreeRTOS/portable/readme.txt:
--------------------------------------------------------------------------------
1 | Each real time kernel port consists of three files that contain the core kernel
2 | components and are common to every port, and one or more files that are
3 | specific to a particular microcontroller and/or compiler.
4 |
5 |
6 | + The FreeRTOS/Source/Portable/MemMang directory contains the five sample
7 | memory allocators as described on the http://www.FreeRTOS.org WEB site.
8 |
9 | + The other directories each contain files specific to a particular
10 | microcontroller or compiler, where the directory name denotes the compiler
11 | specific files the directory contains.
12 |
13 |
14 |
15 | For example, if you are interested in the [compiler] port for the [architecture]
16 | microcontroller, then the port specific files are contained in
17 | FreeRTOS/Source/Portable/[compiler]/[architecture] directory. If this is the
18 | only port you are interested in then all the other directories can be
19 | ignored.
20 |
21 |
--------------------------------------------------------------------------------
/FreeRTOS/readme.txt:
--------------------------------------------------------------------------------
1 | Each real time kernel port consists of three files that contain the core kernel
2 | components and are common to every port, and one or more files that are
3 | specific to a particular microcontroller and or compiler.
4 |
5 | + The FreeRTOS/Source directory contains the three files that are common to
6 | every port - list.c, queue.c and tasks.c. The kernel is contained within these
7 | three files. croutine.c implements the optional co-routine functionality - which
8 | is normally only used on very memory limited systems.
9 |
10 | + The FreeRTOS/Source/Portable directory contains the files that are specific to
11 | a particular microcontroller and or compiler.
12 |
13 | + The FreeRTOS/Source/include directory contains the real time kernel header
14 | files.
15 |
16 | See the readme file in the FreeRTOS/Source/Portable directory for more
17 | information.
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/HARDWARE/ADC/adc.c:
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/HARDWARE/ADC/adc.h:
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1 | #ifndef __ADC_H
2 | #define __ADC_H
3 | #include "sys.h"
4 |
5 | void Adc_Init(void);
6 | u16 Get_Adc(u8 ch);
7 | u16 Get_Adc_Average(u8 ch,u8 times);
8 |
9 | #endif
10 |
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/HARDWARE/BEEP/BEEP.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/BEEP/BEEP.c
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/HARDWARE/BEEP/BEEP.h:
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/HARDWARE/LCD/FONT.H:
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/HARDWARE/LCD/lcd.c:
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/HARDWARE/LCD/lcd.h:
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/HARDWARE/MTR_GPIO/MTR_GPIO.c:
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/HARDWARE/TIMER/timer.c:
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/HARDWARE/TIMER/timer.h:
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/HARDWARE/inc/FONT.H:
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/HARDWARE/inc/adc.h:
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1 | #ifndef __ADC_H
2 | #define __ADC_H
3 | #include "sys.h"
4 |
5 | void Adc_Init(void);
6 | u16 Get_Adc(u8 ch);
7 | u16 Get_Adc_Average(u8 ch,u8 times);
8 |
9 | #endif
10 |
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/HARDWARE/inc/bh1750.h:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/inc/bh1750.h
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/HARDWARE/inc/control.h:
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1 |
2 | #ifndef __CONTROL_H
3 | #define __CONTROL_H
4 |
5 | void send_data(const char *laber, char *flag);
6 |
7 | #endif
8 |
9 |
10 |
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/HARDWARE/inc/delay.h:
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1 | #ifndef __DELAY_H
2 | #define __DELAY_H
3 | #include "sys.h"
4 |
5 | void delay_init(void);
6 | void delay_ms(u32 nms);
7 | void delay_us(u32 nus);
8 | void delay_xms(u32 nms);
9 | #endif
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
51 |
52 |
53 |
54 |
55 |
56 |
57 |
58 |
59 |
60 |
61 |
62 |
63 |
64 |
65 |
66 |
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/HARDWARE/inc/dht11.h:
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/HARDWARE/inc/lcd.h:
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/HARDWARE/inc/led.h:
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/HARDWARE/inc/mqtt.h:
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/HARDWARE/inc/stm32f10x_it.h:
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/HARDWARE/inc/timer3.h:
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1 |
2 | #ifndef _TIMER3_H
3 | #define _TIMER3_H
4 |
5 | void TIM3_ENABLE_30S(void);
6 | void TIM3_ENABLE_2S(void);
7 |
8 | #endif
9 |
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/HARDWARE/inc/timer4.h:
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/HARDWARE/inc/usart1.h:
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/HARDWARE/inc/usart2.h:
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/HARDWARE/inc/wifi.h:
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/HARDWARE/scr/adc.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/adc.c
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/HARDWARE/scr/bh1750.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/bh1750.c
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/HARDWARE/scr/control.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/control.c
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/HARDWARE/scr/delay.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/delay.c
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/HARDWARE/scr/dht11.c:
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/HARDWARE/scr/lcd.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/lcd.c
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/HARDWARE/scr/led.c:
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/HARDWARE/scr/mqtt.c:
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/HARDWARE/scr/stm32f10x_it.c:
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/HARDWARE/scr/timer3.c:
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/HARDWARE/scr/timer4.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/timer4.c
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/HARDWARE/scr/usart1.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/usart1.c
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/HARDWARE/scr/usart2.c:
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/HARDWARE/scr/wifi.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/HARDWARE/scr/wifi.c
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/OBJ/MQTT_ONENET_ESP8266_STM32_FREERTOS_工程.dep:
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/OBJ/adc.crf:
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/OBJ/adc.d:
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1 | ..\obj\adc.o: ..\HARDWARE\ADC\adc.c
2 | ..\obj\adc.o: ..\HARDWARE\ADC\adc.h
3 | ..\obj\adc.o: ..\SYS\sys.h
4 | ..\obj\adc.o: ..\CORE\stm32f10x.h
5 | ..\obj\adc.o: ..\CORE\core_cm3.h
6 | ..\obj\adc.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
7 | ..\obj\adc.o: ..\CORE\system_stm32f10x.h
8 | ..\obj\adc.o: ..\CORE\stm32f10x_conf.h
9 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_adc.h
10 | ..\obj\adc.o: ..\CORE\stm32f10x.h
11 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_bkp.h
12 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_can.h
13 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_cec.h
14 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_crc.h
15 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_dac.h
16 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
17 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_dma.h
18 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_exti.h
19 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_flash.h
20 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_fsmc.h
21 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_gpio.h
22 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_i2c.h
23 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_iwdg.h
24 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_pwr.h
25 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_rcc.h
26 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_rtc.h
27 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_sdio.h
28 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_spi.h
29 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_tim.h
30 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_usart.h
31 | ..\obj\adc.o: ..\STLIB\inc\stm32f10x_wwdg.h
32 | ..\obj\adc.o: ..\STLIB\inc\misc.h
33 | ..\obj\adc.o: ..\HARDWARE\inc\delay.h
34 |
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/OBJ/adc.o:
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/OBJ/beep.crf:
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/OBJ/beep.d:
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1 | ..\obj\beep.o: ..\HARDWARE\BEEP\BEEP.c
2 | ..\obj\beep.o: ..\CORE\stm32f10x.h
3 | ..\obj\beep.o: ..\CORE\core_cm3.h
4 | ..\obj\beep.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
5 | ..\obj\beep.o: ..\CORE\system_stm32f10x.h
6 | ..\obj\beep.o: ..\CORE\stm32f10x_conf.h
7 | ..\obj\beep.o: ..\STLIB\inc\stm32f10x_adc.h
8 | ..\obj\beep.o: ..\CORE\stm32f10x.h
9 | ..\obj\beep.o: ..\STLIB\inc\stm32f10x_bkp.h
10 | ..\obj\beep.o: ..\STLIB\inc\stm32f10x_can.h
11 | ..\obj\beep.o: ..\STLIB\inc\stm32f10x_cec.h
12 | ..\obj\beep.o: ..\STLIB\inc\stm32f10x_crc.h
13 | ..\obj\beep.o: ..\STLIB\inc\stm32f10x_dac.h
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22 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_iwdg.h
23 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_pwr.h
24 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_rcc.h
25 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_rtc.h
26 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_sdio.h
27 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_spi.h
28 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_tim.h
29 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_usart.h
30 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\stm32f10x_wwdg.h
31 | ..\obj\stm32f10x_adc.o: ..\STLIB\inc\misc.h
32 |
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1 | ..\obj\stm32f10x_gpio.o: ..\STLIB\src\stm32f10x_gpio.c
2 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_gpio.h
3 | ..\obj\stm32f10x_gpio.o: ..\CORE\stm32f10x.h
4 | ..\obj\stm32f10x_gpio.o: ..\CORE\core_cm3.h
5 | ..\obj\stm32f10x_gpio.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
6 | ..\obj\stm32f10x_gpio.o: ..\CORE\system_stm32f10x.h
7 | ..\obj\stm32f10x_gpio.o: ..\CORE\stm32f10x_conf.h
8 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_adc.h
9 | ..\obj\stm32f10x_gpio.o: ..\CORE\stm32f10x.h
10 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_bkp.h
11 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_can.h
12 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_cec.h
13 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_crc.h
14 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_dac.h
15 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
16 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_dma.h
17 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_exti.h
18 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_flash.h
19 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_fsmc.h
20 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_gpio.h
21 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_i2c.h
22 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_iwdg.h
23 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_pwr.h
24 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_rcc.h
25 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_rtc.h
26 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_sdio.h
27 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_spi.h
28 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_tim.h
29 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_usart.h
30 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\stm32f10x_wwdg.h
31 | ..\obj\stm32f10x_gpio.o: ..\STLIB\inc\misc.h
32 |
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3 | ..\obj\stm32f10x_it.o: ..\CORE\core_cm3.h
4 | ..\obj\stm32f10x_it.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
5 | ..\obj\stm32f10x_it.o: ..\CORE\system_stm32f10x.h
6 | ..\obj\stm32f10x_it.o: ..\CORE\stm32f10x_conf.h
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8 | ..\obj\stm32f10x_it.o: ..\CORE\stm32f10x.h
9 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_bkp.h
10 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_can.h
11 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_cec.h
12 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_crc.h
13 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_dac.h
14 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
15 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_dma.h
16 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_exti.h
17 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_flash.h
18 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_fsmc.h
19 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_gpio.h
20 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_i2c.h
21 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_iwdg.h
22 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_pwr.h
23 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_rcc.h
24 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_rtc.h
25 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_sdio.h
26 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_spi.h
27 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_tim.h
28 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_usart.h
29 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\stm32f10x_wwdg.h
30 | ..\obj\stm32f10x_it.o: ..\STLIB\inc\misc.h
31 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\FreeRTOS.h
32 | ..\obj\stm32f10x_it.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stddef.h
33 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\FreeRTOSConfig.h
34 | ..\obj\stm32f10x_it.o: ..\SYS\sys.h
35 | ..\obj\stm32f10x_it.o: ..\HARDWARE\inc\usart1.h
36 | ..\obj\stm32f10x_it.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdio.h
37 | ..\obj\stm32f10x_it.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdarg.h
38 | ..\obj\stm32f10x_it.o: D:\STM.32\ARM\ARMCC\Bin\..\include\string.h
39 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\projdefs.h
40 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\portable.h
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42 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\portable\RVDS\ARM_CM3\portmacro.h
43 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\mpu_wrappers.h
44 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\task.h
45 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\list.h
46 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\event_groups.h
47 | ..\obj\stm32f10x_it.o: ..\FreeRTOS\include\timers.h
48 | ..\obj\stm32f10x_it.o: ..\HARDWARE\inc\stm32f10x_it.h
49 | ..\obj\stm32f10x_it.o: ..\HARDWARE\inc\usart2.h
50 | ..\obj\stm32f10x_it.o: ..\HARDWARE\inc\timer3.h
51 | ..\obj\stm32f10x_it.o: ..\HARDWARE\inc\mqtt.h
52 | ..\obj\stm32f10x_it.o: ..\HARDWARE\inc\dht11.h
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3 | ..\obj\stm32f10x_rcc.o: ..\CORE\stm32f10x.h
4 | ..\obj\stm32f10x_rcc.o: ..\CORE\core_cm3.h
5 | ..\obj\stm32f10x_rcc.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
6 | ..\obj\stm32f10x_rcc.o: ..\CORE\system_stm32f10x.h
7 | ..\obj\stm32f10x_rcc.o: ..\CORE\stm32f10x_conf.h
8 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_adc.h
9 | ..\obj\stm32f10x_rcc.o: ..\CORE\stm32f10x.h
10 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_bkp.h
11 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_can.h
12 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_cec.h
13 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_crc.h
14 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_dac.h
15 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
16 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_dma.h
17 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_exti.h
18 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_flash.h
19 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_fsmc.h
20 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_gpio.h
21 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_i2c.h
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25 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_rtc.h
26 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_sdio.h
27 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\stm32f10x_spi.h
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31 | ..\obj\stm32f10x_rcc.o: ..\STLIB\inc\misc.h
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3 | ..\obj\stm32f10x_tim.o: ..\CORE\stm32f10x.h
4 | ..\obj\stm32f10x_tim.o: ..\CORE\core_cm3.h
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6 | ..\obj\stm32f10x_tim.o: ..\CORE\system_stm32f10x.h
7 | ..\obj\stm32f10x_tim.o: ..\CORE\stm32f10x_conf.h
8 | ..\obj\stm32f10x_tim.o: ..\STLIB\inc\stm32f10x_adc.h
9 | ..\obj\stm32f10x_tim.o: ..\CORE\stm32f10x.h
10 | ..\obj\stm32f10x_tim.o: ..\STLIB\inc\stm32f10x_bkp.h
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19 | ..\obj\stm32f10x_tim.o: ..\STLIB\inc\stm32f10x_fsmc.h
20 | ..\obj\stm32f10x_tim.o: ..\STLIB\inc\stm32f10x_gpio.h
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26 | ..\obj\stm32f10x_tim.o: ..\STLIB\inc\stm32f10x_sdio.h
27 | ..\obj\stm32f10x_tim.o: ..\STLIB\inc\stm32f10x_spi.h
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36 | ..\obj\timers.o: ..\HARDWARE\inc\usart1.h
37 | ..\obj\timers.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdio.h
38 | ..\obj\timers.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdarg.h
39 | ..\obj\timers.o: D:\STM.32\ARM\ARMCC\Bin\..\include\string.h
40 | ..\obj\timers.o: ..\FreeRTOS\include\projdefs.h
41 | ..\obj\timers.o: ..\FreeRTOS\include\portable.h
42 | ..\obj\timers.o: ..\FreeRTOS\include\deprecated_definitions.h
43 | ..\obj\timers.o: ..\FreeRTOS\portable\RVDS\ARM_CM3\portmacro.h
44 | ..\obj\timers.o: ..\FreeRTOS\include\mpu_wrappers.h
45 | ..\obj\timers.o: ..\FreeRTOS\include\task.h
46 | ..\obj\timers.o: ..\FreeRTOS\include\list.h
47 | ..\obj\timers.o: ..\FreeRTOS\include\queue.h
48 | ..\obj\timers.o: ..\FreeRTOS\include\timers.h
49 |
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1 | ..\obj\usart1.o: ..\HARDWARE\scr\usart1.c
2 | ..\obj\usart1.o: ..\CORE\stm32f10x.h
3 | ..\obj\usart1.o: ..\CORE\core_cm3.h
4 | ..\obj\usart1.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
5 | ..\obj\usart1.o: ..\CORE\system_stm32f10x.h
6 | ..\obj\usart1.o: ..\CORE\stm32f10x_conf.h
7 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_adc.h
8 | ..\obj\usart1.o: ..\CORE\stm32f10x.h
9 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_bkp.h
10 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_can.h
11 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_cec.h
12 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_crc.h
13 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_dac.h
14 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
15 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_dma.h
16 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_exti.h
17 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_flash.h
18 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_fsmc.h
19 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_gpio.h
20 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_i2c.h
21 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_iwdg.h
22 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_pwr.h
23 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_rcc.h
24 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_rtc.h
25 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_sdio.h
26 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_spi.h
27 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_tim.h
28 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_usart.h
29 | ..\obj\usart1.o: ..\STLIB\inc\stm32f10x_wwdg.h
30 | ..\obj\usart1.o: ..\STLIB\inc\misc.h
31 | ..\obj\usart1.o: ..\HARDWARE\inc\usart1.h
32 | ..\obj\usart1.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdio.h
33 | ..\obj\usart1.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdarg.h
34 | ..\obj\usart1.o: D:\STM.32\ARM\ARMCC\Bin\..\include\string.h
35 |
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1 | ..\obj\usart2.o: ..\HARDWARE\scr\usart2.c
2 | ..\obj\usart2.o: ..\CORE\stm32f10x.h
3 | ..\obj\usart2.o: ..\CORE\core_cm3.h
4 | ..\obj\usart2.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
5 | ..\obj\usart2.o: ..\CORE\system_stm32f10x.h
6 | ..\obj\usart2.o: ..\CORE\stm32f10x_conf.h
7 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_adc.h
8 | ..\obj\usart2.o: ..\CORE\stm32f10x.h
9 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_bkp.h
10 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_can.h
11 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_cec.h
12 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_crc.h
13 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_dac.h
14 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
15 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_dma.h
16 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_exti.h
17 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_flash.h
18 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_fsmc.h
19 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_gpio.h
20 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_i2c.h
21 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_iwdg.h
22 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_pwr.h
23 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_rcc.h
24 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_rtc.h
25 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_sdio.h
26 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_spi.h
27 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_tim.h
28 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_usart.h
29 | ..\obj\usart2.o: ..\STLIB\inc\stm32f10x_wwdg.h
30 | ..\obj\usart2.o: ..\STLIB\inc\misc.h
31 | ..\obj\usart2.o: ..\HARDWARE\inc\usart2.h
32 | ..\obj\usart2.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdio.h
33 | ..\obj\usart2.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdarg.h
34 | ..\obj\usart2.o: D:\STM.32\ARM\ARMCC\Bin\..\include\string.h
35 |
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1 | ..\obj\wifi.o: ..\HARDWARE\scr\wifi.c
2 | ..\obj\wifi.o: ..\CORE\stm32f10x.h
3 | ..\obj\wifi.o: ..\CORE\core_cm3.h
4 | ..\obj\wifi.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdint.h
5 | ..\obj\wifi.o: ..\CORE\system_stm32f10x.h
6 | ..\obj\wifi.o: ..\CORE\stm32f10x_conf.h
7 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_adc.h
8 | ..\obj\wifi.o: ..\CORE\stm32f10x.h
9 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_bkp.h
10 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_can.h
11 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_cec.h
12 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_crc.h
13 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_dac.h
14 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_dbgmcu.h
15 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_dma.h
16 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_exti.h
17 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_flash.h
18 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_fsmc.h
19 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_gpio.h
20 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_i2c.h
21 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_iwdg.h
22 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_pwr.h
23 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_rcc.h
24 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_rtc.h
25 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_sdio.h
26 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_spi.h
27 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_tim.h
28 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_usart.h
29 | ..\obj\wifi.o: ..\STLIB\inc\stm32f10x_wwdg.h
30 | ..\obj\wifi.o: ..\STLIB\inc\misc.h
31 | ..\obj\wifi.o: ..\HARDWARE\inc\wifi.h
32 | ..\obj\wifi.o: ..\HARDWARE\inc\usart2.h
33 | ..\obj\wifi.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdio.h
34 | ..\obj\wifi.o: D:\STM.32\ARM\ARMCC\Bin\..\include\stdarg.h
35 | ..\obj\wifi.o: D:\STM.32\ARM\ARMCC\Bin\..\include\string.h
36 | ..\obj\wifi.o: ..\HARDWARE\inc\delay.h
37 | ..\obj\wifi.o: ..\SYS\sys.h
38 | ..\obj\wifi.o: ..\HARDWARE\inc\usart1.h
39 |
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/README.md:
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1 | /************************室内安防系统************************/
2 |
3 | /***************功能说明***************/
4 |
5 | 1：下位机
6 | 红外槽型光耦：可选择打开或者关闭、检测是否有人室内盗窃 并提供报警（选做：检测有多少人）
7 | MQ2气体：检测是否燃气泄漏并提供报警
8 | DHT11温湿度传感器：监测温湿度状况
9 | 光敏电阻/BH1750：检测光照状况、如果业主离开房屋，打开系统开关，如果发生异常情况，如开灯等也能说明有人，此时也可以报警
10 | //震动传感器：检测地震、提供报警（暂时不做此功能）
11 | LED1(DS1)/LED2(DS0)：模拟报警
12 | 高电平蜂鸣器：
13 | esp01s:
14 |
15 | 2：上位机
16 | 火宅检测显示（有&无）
17 | 系统开关控制（开启可表示业主离开房屋，然后安防报警系统开启）
18 | 报警状态显示（正在报警&无警报）
19 | 温湿度显示
20 | 光照强度显示
21 | 烟雾数值显示
22 | 室内是否有人显示（有人&无人）
23 |
24 | 3：LCD显示屏
25 | 烟雾数值
26 | 温湿度
27 | 光照强度显示
28 | 室内是否有人
29 |
30 | /***************硬件环境***************/
31 | 1：STM32F103RCT6
32 | 2：DHT11温湿度传感器
33 | 3：BH1750（GY30）光照强度传感器
34 | 4：MQ2烟雾传感器
35 | 5：高电平触发蜂鸣器
36 | 6：LCD屏幕
37 | 7：ESP8266-01S无线模块
38 |
39 |
40 | /***************接线说明***************/
41 | 1：ESP8266-01S（5根线）
42 | RX PA2
43 | TX PA3
44 | 复位 PA4
45 | VCC 3V3
46 | GND GND
47 |
48 | 2：DHT11（3根线）
49 | DATA PA6
50 | VCC 3V3
51 | GND GND
52 |
53 | 3：BH1750（5根线）
54 | SCL PC12
55 | SDA PC11
56 | ADDR GND
57 | VCC 5V
58 | GND GND
59 |
60 | 4：MQ2（三根线）
61 | AO PA0
62 | VCC 5V
63 | GND GND
64 |
65 | 5：蜂鸣器
66 | IO PA5
67 | VCC 5V
68 | GND GND
69 | 6:LCD
70 |
71 | 7：LED
72 | LED1 PD2
73 | LED2 PA8
74 |
75 |
76 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_cec.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_cec.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the CEC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CEC_H
25 | #define __STM32F10x_CEC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup CEC
39 | * @{
40 | */
41 |
42 |
43 | /** @defgroup CEC_Exported_Types
44 | * @{
45 | */
46 |
47 | /**
48 | * @brief CEC Init structure definition
49 | */
50 | typedef struct
51 | {
52 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
53 | This parameter can be a value of @ref CEC_BitTiming_Mode */
54 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
55 | This parameter can be a value of @ref CEC_BitPeriod_Mode */
56 | }CEC_InitTypeDef;
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /** @defgroup CEC_Exported_Constants
63 | * @{
64 | */
65 |
66 | /** @defgroup CEC_BitTiming_Mode
67 | * @{
68 | */
69 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
70 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
71 |
72 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
73 | ((MODE) == CEC_BitTimingErrFreeMode))
74 | /**
75 | * @}
76 | */
77 |
78 | /** @defgroup CEC_BitPeriod_Mode
79 | * @{
80 | */
81 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
82 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
83 |
84 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
85 | ((MODE) == CEC_BitPeriodFlexibleMode))
86 | /**
87 | * @}
88 | */
89 |
90 |
91 | /** @defgroup CEC_interrupts_definition
92 | * @{
93 | */
94 | #define CEC_IT_TERR CEC_CSR_TERR
95 | #define CEC_IT_TBTRF CEC_CSR_TBTRF
96 | #define CEC_IT_RERR CEC_CSR_RERR
97 | #define CEC_IT_RBTF CEC_CSR_RBTF
98 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
99 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
100 | /**
101 | * @}
102 | */
103 |
104 |
105 | /** @defgroup CEC_Own_Address
106 | * @{
107 | */
108 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
109 | /**
110 | * @}
111 | */
112 |
113 | /** @defgroup CEC_Prescaler
114 | * @{
115 | */
116 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
117 |
118 | /**
119 | * @}
120 | */
121 |
122 | /** @defgroup CEC_flags_definition
123 | * @{
124 | */
125 |
126 | /**
127 | * @brief ESR register flags
128 | */
129 | #define CEC_FLAG_BTE ((uint32_t)0x10010000)
130 | #define CEC_FLAG_BPE ((uint32_t)0x10020000)
131 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
132 | #define CEC_FLAG_SBE ((uint32_t)0x10080000)
133 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000)
134 | #define CEC_FLAG_LINE ((uint32_t)0x10200000)
135 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
136 |
137 | /**
138 | * @brief CSR register flags
139 | */
140 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002)
141 | #define CEC_FLAG_TERR ((uint32_t)0x00000004)
142 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
143 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010)
144 | #define CEC_FLAG_REOM ((uint32_t)0x00000020)
145 | #define CEC_FLAG_RERR ((uint32_t)0x00000040)
146 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080)
147 |
148 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
149 |
150 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
151 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
152 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
153 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
154 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
155 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
156 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /** @defgroup CEC_Exported_Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /** @defgroup CEC_Exported_Functions
175 | * @{
176 | */
177 | void CEC_DeInit(void);
178 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
179 | void CEC_Cmd(FunctionalState NewState);
180 | void CEC_ITConfig(FunctionalState NewState);
181 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
182 | void CEC_SetPrescaler(uint16_t CEC_Prescaler);
183 | void CEC_SendDataByte(uint8_t Data);
184 | uint8_t CEC_ReceiveDataByte(void);
185 | void CEC_StartOfMessage(void);
186 | void CEC_EndOfMessageCmd(FunctionalState NewState);
187 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
188 | void CEC_ClearFlag(uint32_t CEC_FLAG);
189 | ITStatus CEC_GetITStatus(uint8_t CEC_IT);
190 | void CEC_ClearITPendingBit(uint16_t CEC_IT);
191 |
192 | #ifdef __cplusplus
193 | }
194 | #endif
195 |
196 | #endif /* __STM32F10x_CEC_H */
197 |
198 | /**
199 | * @}
200 | */
201 |
202 | /**
203 | * @}
204 | */
205 |
206 | /**
207 | * @}
208 | */
209 |
210 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
211 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CRC_H
25 | #define __STM32F10x_CRC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup CRC
39 | * @{
40 | */
41 |
42 | /** @defgroup CRC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup CRC_Exported_Constants
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup CRC_Exported_Macros
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup CRC_Exported_Functions
67 | * @{
68 | */
69 |
70 | void CRC_ResetDR(void);
71 | uint32_t CRC_CalcCRC(uint32_t Data);
72 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
73 | uint32_t CRC_GetCRC(void);
74 | void CRC_SetIDRegister(uint8_t IDValue);
75 | uint8_t CRC_GetIDRegister(void);
76 |
77 | #ifdef __cplusplus
78 | }
79 | #endif
80 |
81 | #endif /* __STM32F10x_CRC_H */
82 | /**
83 | * @}
84 | */
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
95 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the DBGMCU
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_DBGMCU_H
25 | #define __STM32F10x_DBGMCU_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup DBGMCU
39 | * @{
40 | */
41 |
42 | /** @defgroup DBGMCU_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup DBGMCU_Exported_Constants
51 | * @{
52 | */
53 |
54 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
55 | #define DBGMCU_STOP ((uint32_t)0x00000002)
56 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
57 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
58 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
59 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
60 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
61 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
62 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
63 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
64 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
65 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
66 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
67 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
68 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
69 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
70 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
71 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
72 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
73 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
74 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
75 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
76 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
77 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
78 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
79 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
80 |
81 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup DBGMCU_Exported_Macros
87 | * @{
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup DBGMCU_Exported_Functions
95 | * @{
96 | */
97 |
98 | uint32_t DBGMCU_GetREVID(void);
99 | uint32_t DBGMCU_GetDEVID(void);
100 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
101 |
102 | #ifdef __cplusplus
103 | }
104 | #endif
105 |
106 | #endif /* __STM32F10x_DBGMCU_H */
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
120 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_exti.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the EXTI firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_EXTI_H
25 | #define __STM32F10x_EXTI_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup EXTI
39 | * @{
40 | */
41 |
42 | /** @defgroup EXTI_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief EXTI mode enumeration
48 | */
49 |
50 | typedef enum
51 | {
52 | EXTI_Mode_Interrupt = 0x00,
53 | EXTI_Mode_Event = 0x04
54 | }EXTIMode_TypeDef;
55 |
56 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
57 |
58 | /**
59 | * @brief EXTI Trigger enumeration
60 | */
61 |
62 | typedef enum
63 | {
64 | EXTI_Trigger_Rising = 0x08,
65 | EXTI_Trigger_Falling = 0x0C,
66 | EXTI_Trigger_Rising_Falling = 0x10
67 | }EXTITrigger_TypeDef;
68 |
69 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
70 | ((TRIGGER) == EXTI_Trigger_Falling) || \
71 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
72 | /**
73 | * @brief EXTI Init Structure definition
74 | */
75 |
76 | typedef struct
77 | {
78 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
79 | This parameter can be any combination of @ref EXTI_Lines */
80 |
81 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
82 | This parameter can be a value of @ref EXTIMode_TypeDef */
83 |
84 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
85 | This parameter can be a value of @ref EXTIMode_TypeDef */
86 |
87 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
88 | This parameter can be set either to ENABLE or DISABLE */
89 | }EXTI_InitTypeDef;
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup EXTI_Exported_Constants
96 | * @{
97 | */
98 |
99 | /** @defgroup EXTI_Lines
100 | * @{
101 | */
102 |
103 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
104 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
105 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
106 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
107 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
108 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
109 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
110 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
111 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
112 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
113 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
114 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
115 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
116 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
117 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
118 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
119 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
120 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
121 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
122 | Wakeup from suspend event */
123 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
124 |
125 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
126 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
127 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
128 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
129 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
130 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
131 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
132 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
133 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
134 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
135 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
136 |
137 |
138 | /**
139 | * @}
140 | */
141 |
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup EXTI_Exported_Macros
147 | * @{
148 | */
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /** @defgroup EXTI_Exported_Functions
155 | * @{
156 | */
157 |
158 | void EXTI_DeInit(void);
159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
162 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
163 | void EXTI_ClearFlag(uint32_t EXTI_Line);
164 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
165 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
166 |
167 | #ifdef __cplusplus
168 | }
169 | #endif
170 |
171 | #endif /* __STM32F10x_EXTI_H */
172 | /**
173 | * @}
174 | */
175 |
176 | /**
177 | * @}
178 | */
179 |
180 | /**
181 | * @}
182 | */
183 |
184 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
185 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_IWDG_H
25 | #define __STM32F10x_IWDG_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup IWDG
39 | * @{
40 | */
41 |
42 | /** @defgroup IWDG_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup IWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup IWDG_WriteAccess
55 | * @{
56 | */
57 |
58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
61 | ((ACCESS) == IWDG_WriteAccess_Disable))
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup IWDG_prescaler
67 | * @{
68 | */
69 |
70 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
71 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
72 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
73 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
74 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
75 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
76 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
77 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
78 | ((PRESCALER) == IWDG_Prescaler_8) || \
79 | ((PRESCALER) == IWDG_Prescaler_16) || \
80 | ((PRESCALER) == IWDG_Prescaler_32) || \
81 | ((PRESCALER) == IWDG_Prescaler_64) || \
82 | ((PRESCALER) == IWDG_Prescaler_128)|| \
83 | ((PRESCALER) == IWDG_Prescaler_256))
84 | /**
85 | * @}
86 | */
87 |
88 | /** @defgroup IWDG_Flag
89 | * @{
90 | */
91 |
92 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
93 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
94 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
95 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
96 | /**
97 | * @}
98 | */
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | /** @defgroup IWDG_Exported_Macros
105 | * @{
106 | */
107 |
108 | /**
109 | * @}
110 | */
111 |
112 | /** @defgroup IWDG_Exported_Functions
113 | * @{
114 | */
115 |
116 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
117 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
118 | void IWDG_SetReload(uint16_t Reload);
119 | void IWDG_ReloadCounter(void);
120 | void IWDG_Enable(void);
121 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
122 |
123 | #ifdef __cplusplus
124 | }
125 | #endif
126 |
127 | #endif /* __STM32F10x_IWDG_H */
128 | /**
129 | * @}
130 | */
131 |
132 | /**
133 | * @}
134 | */
135 |
136 | /**
137 | * @}
138 | */
139 |
140 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
141 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_PWR_H
25 | #define __STM32F10x_PWR_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup PWR
39 | * @{
40 | */
41 |
42 | /** @defgroup PWR_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup PWR_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup PVD_detection_level
55 | * @{
56 | */
57 |
58 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
59 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
60 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
61 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
62 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
63 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
64 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
65 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
67 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
68 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
69 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup Regulator_state_is_STOP_mode
75 | * @{
76 | */
77 |
78 | #define PWR_Regulator_ON ((uint32_t)0x00000000)
79 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001)
80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
81 | ((REGULATOR) == PWR_Regulator_LowPower))
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup STOP_mode_entry
87 | * @{
88 | */
89 |
90 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
91 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup PWR_Flag
99 | * @{
100 | */
101 |
102 | #define PWR_FLAG_WU ((uint32_t)0x00000001)
103 | #define PWR_FLAG_SB ((uint32_t)0x00000002)
104 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
106 | ((FLAG) == PWR_FLAG_PVDO))
107 |
108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
109 | /**
110 | * @}
111 | */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /** @defgroup PWR_Exported_Macros
118 | * @{
119 | */
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /** @defgroup PWR_Exported_Functions
126 | * @{
127 | */
128 |
129 | void PWR_DeInit(void);
130 | void PWR_BackupAccessCmd(FunctionalState NewState);
131 | void PWR_PVDCmd(FunctionalState NewState);
132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
133 | void PWR_WakeUpPinCmd(FunctionalState NewState);
134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
135 | void PWR_EnterSTANDBYMode(void);
136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
137 | void PWR_ClearFlag(uint32_t PWR_FLAG);
138 |
139 | #ifdef __cplusplus
140 | }
141 | #endif
142 |
143 | #endif /* __STM32F10x_PWR_H */
144 | /**
145 | * @}
146 | */
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
157 |
--------------------------------------------------------------------------------
/STLIB/inc/stm32f10x_rtc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rtc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the RTC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_RTC_H
25 | #define __STM32F10x_RTC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup RTC
39 | * @{
40 | */
41 |
42 | /** @defgroup RTC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup RTC_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup RTC_interrupts_define
55 | * @{
56 | */
57 |
58 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
59 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
60 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
61 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
62 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
63 | ((IT) == RTC_IT_SEC))
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup RTC_interrupts_flags
69 | * @{
70 | */
71 |
72 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
73 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
74 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
75 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
76 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
77 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
78 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
79 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
80 | ((FLAG) == RTC_FLAG_SEC))
81 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @defgroup RTC_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @defgroup RTC_Exported_Functions
100 | * @{
101 | */
102 |
103 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
104 | void RTC_EnterConfigMode(void);
105 | void RTC_ExitConfigMode(void);
106 | uint32_t RTC_GetCounter(void);
107 | void RTC_SetCounter(uint32_t CounterValue);
108 | void RTC_SetPrescaler(uint32_t PrescalerValue);
109 | void RTC_SetAlarm(uint32_t AlarmValue);
110 | uint32_t RTC_GetDivider(void);
111 | void RTC_WaitForLastTask(void);
112 | void RTC_WaitForSynchro(void);
113 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
114 | void RTC_ClearFlag(uint16_t RTC_FLAG);
115 | ITStatus RTC_GetITStatus(uint16_t RTC_IT);
116 | void RTC_ClearITPendingBit(uint16_t RTC_IT);
117 |
118 | #ifdef __cplusplus
119 | }
120 | #endif
121 |
122 | #endif /* __STM32F10x_RTC_H */
123 | /**
124 | * @}
125 | */
126 |
127 | /**
128 | * @}
129 | */
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
136 |
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/STLIB/inc/stm32f10x_wwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the WWDG firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_WWDG_H
25 | #define __STM32F10x_WWDG_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup WWDG
39 | * @{
40 | */
41 |
42 | /** @defgroup WWDG_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup WWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup WWDG_Prescaler
55 | * @{
56 | */
57 |
58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
63 | ((PRESCALER) == WWDG_Prescaler_2) || \
64 | ((PRESCALER) == WWDG_Prescaler_4) || \
65 | ((PRESCALER) == WWDG_Prescaler_8))
66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup WWDG_Exported_Macros
78 | * @{
79 | */
80 | /**
81 | * @}
82 | */
83 |
84 | /** @defgroup WWDG_Exported_Functions
85 | * @{
86 | */
87 |
88 | void WWDG_DeInit(void);
89 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
90 | void WWDG_SetWindowValue(uint8_t WindowValue);
91 | void WWDG_EnableIT(void);
92 | void WWDG_SetCounter(uint8_t Counter);
93 | void WWDG_Enable(uint8_t Counter);
94 | FlagStatus WWDG_GetFlagStatus(void);
95 | void WWDG_ClearFlag(void);
96 |
97 | #ifdef __cplusplus
98 | }
99 | #endif
100 |
101 | #endif /* __STM32F10x_WWDG_H */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
116 |
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/STLIB/src/stm32f10x_crc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the CRC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_crc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup CRC
30 | * @brief CRC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup CRC_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup CRC_Private_Defines
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup CRC_Private_Macros
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup CRC_Private_Variables
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup CRC_Private_FunctionPrototypes
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup CRC_Private_Functions
75 | * @{
76 | */
77 |
78 | /**
79 | * @brief Resets the CRC Data register (DR).
80 | * @param None
81 | * @retval None
82 | */
83 | void CRC_ResetDR(void)
84 | {
85 | /* Reset CRC generator */
86 | CRC->CR = CRC_CR_RESET;
87 | }
88 |
89 | /**
90 | * @brief Computes the 32-bit CRC of a given data word(32-bit).
91 | * @param Data: data word(32-bit) to compute its CRC
92 | * @retval 32-bit CRC
93 | */
94 | uint32_t CRC_CalcCRC(uint32_t Data)
95 | {
96 | CRC->DR = Data;
97 |
98 | return (CRC->DR);
99 | }
100 |
101 | /**
102 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
103 | * @param pBuffer: pointer to the buffer containing the data to be computed
104 | * @param BufferLength: length of the buffer to be computed
105 | * @retval 32-bit CRC
106 | */
107 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
108 | {
109 | uint32_t index = 0;
110 |
111 | for(index = 0; index < BufferLength; index++)
112 | {
113 | CRC->DR = pBuffer[index];
114 | }
115 | return (CRC->DR);
116 | }
117 |
118 | /**
119 | * @brief Returns the current CRC value.
120 | * @param None
121 | * @retval 32-bit CRC
122 | */
123 | uint32_t CRC_GetCRC(void)
124 | {
125 | return (CRC->DR);
126 | }
127 |
128 | /**
129 | * @brief Stores a 8-bit data in the Independent Data(ID) register.
130 | * @param IDValue: 8-bit value to be stored in the ID register
131 | * @retval None
132 | */
133 | void CRC_SetIDRegister(uint8_t IDValue)
134 | {
135 | CRC->IDR = IDValue;
136 | }
137 |
138 | /**
139 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register
140 | * @param None
141 | * @retval 8-bit value of the ID register
142 | */
143 | uint8_t CRC_GetIDRegister(void)
144 | {
145 | return (CRC->IDR);
146 | }
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
161 |
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/STLIB/src/stm32f10x_dbgmcu.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the DBGMCU firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_dbgmcu.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup DBGMCU
30 | * @brief DBGMCU driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup DBGMCU_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup DBGMCU_Private_Defines
43 | * @{
44 | */
45 |
46 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
47 | /**
48 | * @}
49 | */
50 |
51 | /** @defgroup DBGMCU_Private_Macros
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @defgroup DBGMCU_Private_Variables
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup DBGMCU_Private_FunctionPrototypes
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup DBGMCU_Private_Functions
76 | * @{
77 | */
78 |
79 | /**
80 | * @brief Returns the device revision identifier.
81 | * @param None
82 | * @retval Device revision identifier
83 | */
84 | uint32_t DBGMCU_GetREVID(void)
85 | {
86 | return(DBGMCU->IDCODE >> 16);
87 | }
88 |
89 | /**
90 | * @brief Returns the device identifier.
91 | * @param None
92 | * @retval Device identifier
93 | */
94 | uint32_t DBGMCU_GetDEVID(void)
95 | {
96 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
97 | }
98 |
99 | /**
100 | * @brief Configures the specified peripheral and low power mode behavior
101 | * when the MCU under Debug mode.
102 | * @param DBGMCU_Periph: specifies the peripheral and low power mode.
103 | * This parameter can be any combination of the following values:
104 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
105 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
106 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
107 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
108 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
109 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
110 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
111 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
112 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
113 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
114 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
115 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
116 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
117 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
118 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
119 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
120 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
121 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
122 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
123 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
124 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
125 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
126 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
127 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
128 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
129 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
130 | * @param NewState: new state of the specified peripheral in Debug mode.
131 | * This parameter can be: ENABLE or DISABLE.
132 | * @retval None
133 | */
134 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
135 | {
136 | /* Check the parameters */
137 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
138 | assert_param(IS_FUNCTIONAL_STATE(NewState));
139 |
140 | if (NewState != DISABLE)
141 | {
142 | DBGMCU->CR |= DBGMCU_Periph;
143 | }
144 | else
145 | {
146 | DBGMCU->CR &= ~DBGMCU_Periph;
147 | }
148 | }
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /**
155 | * @}
156 | */
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
163 |
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/STLIB/src/stm32f10x_flash.c:
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/STLIB/src/stm32f10x_i2c.c:
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https://raw.githubusercontent.com/longgang/STM32_MQTT_ONENET_ESP8266_FREERTOS-main/f2c42f3f13687857502ff784fbb897255474c555/STLIB/src/stm32f10x_i2c.c
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/STLIB/src/stm32f10x_iwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the IWDG firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_iwdg.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup IWDG
30 | * @brief IWDG driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup IWDG_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup IWDG_Private_Defines
43 | * @{
44 | */
45 |
46 | /* ---------------------- IWDG registers bit mask ----------------------------*/
47 |
48 | /* KR register bit mask */
49 | #define KR_KEY_Reload ((uint16_t)0xAAAA)
50 | #define KR_KEY_Enable ((uint16_t)0xCCCC)
51 |
52 | /**
53 | * @}
54 | */
55 |
56 | /** @defgroup IWDG_Private_Macros
57 | * @{
58 | */
59 |
60 | /**
61 | * @}
62 | */
63 |
64 | /** @defgroup IWDG_Private_Variables
65 | * @{
66 | */
67 |
68 | /**
69 | * @}
70 | */
71 |
72 | /** @defgroup IWDG_Private_FunctionPrototypes
73 | * @{
74 | */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 | /** @defgroup IWDG_Private_Functions
81 | * @{
82 | */
83 |
84 | /**
85 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
86 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
87 | * This parameter can be one of the following values:
88 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
89 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
90 | * @retval None
91 | */
92 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
93 | {
94 | /* Check the parameters */
95 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
96 | IWDG->KR = IWDG_WriteAccess;
97 | }
98 |
99 | /**
100 | * @brief Sets IWDG Prescaler value.
101 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
102 | * This parameter can be one of the following values:
103 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
104 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
105 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
106 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
107 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
108 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
109 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
110 | * @retval None
111 | */
112 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
113 | {
114 | /* Check the parameters */
115 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
116 | IWDG->PR = IWDG_Prescaler;
117 | }
118 |
119 | /**
120 | * @brief Sets IWDG Reload value.
121 | * @param Reload: specifies the IWDG Reload value.
122 | * This parameter must be a number between 0 and 0x0FFF.
123 | * @retval None
124 | */
125 | void IWDG_SetReload(uint16_t Reload)
126 | {
127 | /* Check the parameters */
128 | assert_param(IS_IWDG_RELOAD(Reload));
129 | IWDG->RLR = Reload;
130 | }
131 |
132 | /**
133 | * @brief Reloads IWDG counter with value defined in the reload register
134 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
135 | * @param None
136 | * @retval None
137 | */
138 | void IWDG_ReloadCounter(void)
139 | {
140 | IWDG->KR = KR_KEY_Reload;
141 | }
142 |
143 | /**
144 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
145 | * @param None
146 | * @retval None
147 | */
148 | void IWDG_Enable(void)
149 | {
150 | IWDG->KR = KR_KEY_Enable;
151 | }
152 |
153 | /**
154 | * @brief Checks whether the specified IWDG flag is set or not.
155 | * @param IWDG_FLAG: specifies the flag to check.
156 | * This parameter can be one of the following values:
157 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
158 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
159 | * @retval The new state of IWDG_FLAG (SET or RESET).
160 | */
161 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
162 | {
163 | FlagStatus bitstatus = RESET;
164 | /* Check the parameters */
165 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
166 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
167 | {
168 | bitstatus = SET;
169 | }
170 | else
171 | {
172 | bitstatus = RESET;
173 | }
174 | /* Return the flag status */
175 | return bitstatus;
176 | }
177 |
178 | /**
179 | * @}
180 | */
181 |
182 | /**
183 | * @}
184 | */
185 |
186 | /**
187 | * @}
188 | */
189 |
190 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
191 |
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/STLIB/src/stm32f10x_usart.c:
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/STLIB/src/stm32f10x_wwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the WWDG firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_wwdg.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup WWDG
31 | * @brief WWDG driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup WWDG_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup WWDG_Private_Defines
44 | * @{
45 | */
46 |
47 | /* ----------- WWDG registers bit address in the alias region ----------- */
48 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
49 |
50 | /* Alias word address of EWI bit */
51 | #define CFR_OFFSET (WWDG_OFFSET + 0x04)
52 | #define EWI_BitNumber 0x09
53 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
54 |
55 | /* --------------------- WWDG registers bit mask ------------------------ */
56 |
57 | /* CR register bit mask */
58 | #define CR_WDGA_Set ((uint32_t)0x00000080)
59 |
60 | /* CFR register bit mask */
61 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
62 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80)
63 | #define BIT_Mask ((uint8_t)0x7F)
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /** @defgroup WWDG_Private_Macros
70 | * @{
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup WWDG_Private_Variables
78 | * @{
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /** @defgroup WWDG_Private_FunctionPrototypes
86 | * @{
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /** @defgroup WWDG_Private_Functions
94 | * @{
95 | */
96 |
97 | /**
98 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
99 | * @param None
100 | * @retval None
101 | */
102 | void WWDG_DeInit(void)
103 | {
104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
106 | }
107 |
108 | /**
109 | * @brief Sets the WWDG Prescaler.
110 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
111 | * This parameter can be one of the following values:
112 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
113 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
114 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
115 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
116 | * @retval None
117 | */
118 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
119 | {
120 | uint32_t tmpreg = 0;
121 | /* Check the parameters */
122 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
123 | /* Clear WDGTB[1:0] bits */
124 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
125 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
126 | tmpreg |= WWDG_Prescaler;
127 | /* Store the new value */
128 | WWDG->CFR = tmpreg;
129 | }
130 |
131 | /**
132 | * @brief Sets the WWDG window value.
133 | * @param WindowValue: specifies the window value to be compared to the downcounter.
134 | * This parameter value must be lower than 0x80.
135 | * @retval None
136 | */
137 | void WWDG_SetWindowValue(uint8_t WindowValue)
138 | {
139 | __IO uint32_t tmpreg = 0;
140 |
141 | /* Check the parameters */
142 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
143 | /* Clear W[6:0] bits */
144 |
145 | tmpreg = WWDG->CFR & CFR_W_Mask;
146 |
147 | /* Set W[6:0] bits according to WindowValue value */
148 | tmpreg |= WindowValue & (uint32_t) BIT_Mask;
149 |
150 | /* Store the new value */
151 | WWDG->CFR = tmpreg;
152 | }
153 |
154 | /**
155 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
156 | * @param None
157 | * @retval None
158 | */
159 | void WWDG_EnableIT(void)
160 | {
161 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
162 | }
163 |
164 | /**
165 | * @brief Sets the WWDG counter value.
166 | * @param Counter: specifies the watchdog counter value.
167 | * This parameter must be a number between 0x40 and 0x7F.
168 | * @retval None
169 | */
170 | void WWDG_SetCounter(uint8_t Counter)
171 | {
172 | /* Check the parameters */
173 | assert_param(IS_WWDG_COUNTER(Counter));
174 | /* Write to T[6:0] bits to configure the counter value, no need to do
175 | a read-modify-write; writing a 0 to WDGA bit does nothing */
176 | WWDG->CR = Counter & BIT_Mask;
177 | }
178 |
179 | /**
180 | * @brief Enables WWDG and load the counter value.
181 | * @param Counter: specifies the watchdog counter value.
182 | * This parameter must be a number between 0x40 and 0x7F.
183 | * @retval None
184 | */
185 | void WWDG_Enable(uint8_t Counter)
186 | {
187 | /* Check the parameters */
188 | assert_param(IS_WWDG_COUNTER(Counter));
189 | WWDG->CR = CR_WDGA_Set | Counter;
190 | }
191 |
192 | /**
193 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
194 | * @param None
195 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
196 | */
197 | FlagStatus WWDG_GetFlagStatus(void)
198 | {
199 | return (FlagStatus)(WWDG->SR);
200 | }
201 |
202 | /**
203 | * @brief Clears Early Wakeup interrupt flag.
204 | * @param None
205 | * @retval None
206 | */
207 | void WWDG_ClearFlag(void)
208 | {
209 | WWDG->SR = (uint32_t)RESET;
210 | }
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /**
217 | * @}
218 | */
219 |
220 | /**
221 | * @}
222 | */
223 |
224 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
225 |
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/SYS/sys.c:
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/USER/DebugConfig/_____STM32F103RC_1.0.0.dbgconf:
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1 | // <<< Use Configuration Wizard in Context Menu >>>
2 | // Debug MCU Configuration
3 | // DBG_SLEEP
4 | // Debug Sleep Mode
5 | // 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
6 | // 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
7 | // DBG_STOP
8 | // Debug Stop Mode
9 | // 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10 | // 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11 | // DBG_STANDBY
12 | // Debug Standby Mode
13 | // 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14 | // 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15 | // DBG_IWDG_STOP
16 | // Debug independent watchdog stopped when core is halted
17 | // 0: The watchdog counter clock continues even if the core is halted
18 | // 1: The watchdog counter clock is stopped when the core is halted
19 | // DBG_WWDG_STOP
20 | // Debug window watchdog stopped when core is halted
21 | // 0: The window watchdog counter clock continues even if the core is halted
22 | // 1: The window watchdog counter clock is stopped when the core is halted
23 | // DBG_TIM1_STOP
24 | // Timer 1 counter stopped when core is halted
25 | // 0: The clock of the involved Timer Counter is fed even if the core is halted
26 | // 1: The clock of the involved Timer counter is stopped when the core is halted
27 | // DBG_TIM2_STOP
28 | // Timer 2 counter stopped when core is halted
29 | // 0: The clock of the involved Timer Counter is fed even if the core is halted
30 | // 1: The clock of the involved Timer counter is stopped when the core is halted
31 | // DBG_TIM3_STOP
32 | // Timer 3 counter stopped when core is halted
33 | // 0: The clock of the involved Timer Counter is fed even if the core is halted
34 | // 1: The clock of the involved Timer counter is stopped when the core is halted
35 | // DBG_TIM4_STOP
36 | // Timer 4 counter stopped when core is halted
37 | // 0: The clock of the involved Timer Counter is fed even if the core is halted
38 | // 1: The clock of the involved Timer counter is stopped when the core is halted
39 | // DBG_CAN1_STOP
40 | // Debug CAN1 stopped when Core is halted
41 | // 0: Same behavior as in normal mode
42 | // 1: CAN1 receive registers are frozen
43 | // DBG_I2C1_SMBUS_TIMEOUT
44 | // I2C1 SMBUS timeout mode stopped when Core is halted
45 | // 0: Same behavior as in normal mode
46 | // 1: The SMBUS timeout is frozen
47 | // DBG_I2C2_SMBUS_TIMEOUT
48 | // I2C2 SMBUS timeout mode stopped when Core is halted
49 | // 0: Same behavior as in normal mode
50 | // 1: The SMBUS timeout is frozen
51 | // DBG_TIM8_STOP
52 | // Timer 8 counter stopped when core is halted
53 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55 | // DBG_TIM5_STOP
56 | // Timer 5 counter stopped when core is halted
57 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59 | // DBG_TIM6_STOP
60 | // Timer 6 counter stopped when core is halted
61 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63 | // DBG_TIM7_STOP
64 | // Timer 7 counter stopped when core is halted
65 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67 | // DBG_CAN2_STOP
68 | // Debug CAN2 stopped when Core is halted
69 | // 0: Same behavior as in normal mode
70 | // 1: CAN2 receive registers are frozen
71 | // DBG_TIM12_STOP
72 | // Timer 12 counter stopped when core is halted
73 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75 | // DBG_TIM13_STOP
76 | // Timer 13 counter stopped when core is halted
77 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79 | // DBG_TIM14_STOP
80 | // Timer 14 counter stopped when core is halted
81 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83 | // DBG_TIM9_STOP
84 | // Timer 9 counter stopped when core is halted
85 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87 | // DBG_TIM10_STOP
88 | // Timer 10 counter stopped when core is halted
89 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91 | // DBG_TIM11_STOP
92 | // Timer 11 counter stopped when core is halted
93 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95 | //
96 | DbgMCU_CR = 0x00000007;
97 | // <<< end of configuration section >>>
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