├── LICENSE
├── README.md
├── simulation
├── CPUTest.v
├── DataMemory_Test.v
├── InstructionMemory_Test.v
└── RegisterFile_Test.v
└── sources
├── ALU_16bit.v
├── ALU_1bit.v
├── ALU_Control.v
├── Adder_16bit.v
├── CPU.v
├── ControlUnit.v
├── DataMemory.v
├── DataPath.v
├── InstructionMemory.v
├── RegisterFile.v
├── SltiFunction.v
├── dataMemory.mem
├── instrMemory.mem
├── modFunction.v
├── mux2ne1.v
└── mux8ne1.v
/LICENSE:
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571 | Program specifies that a certain numbered version of the GNU General
572 | Public License "or any later version" applies to it, you have the
573 | option of following the terms and conditions either of that numbered
574 | version or of any later version published by the Free Software
575 | Foundation. If the Program does not specify a version number of the
576 | GNU General Public License, you may choose any version ever published
577 | by the Free Software Foundation.
578 |
579 | If the Program specifies that a proxy can decide which future
580 | versions of the GNU General Public License can be used, that proxy's
581 | public statement of acceptance of a version permanently authorizes you
582 | to choose that version for the Program.
583 |
584 | Later license versions may give you additional or different
585 | permissions. However, no additional obligations are imposed on any
586 | author or copyright holder as a result of your choosing to follow a
587 | later version.
588 |
589 | 15. Disclaimer of Warranty.
590 |
591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
599 |
600 | 16. Limitation of Liability.
601 |
602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
610 | SUCH DAMAGES.
611 |
612 | 17. Interpretation of Sections 15 and 16.
613 |
614 | If the disclaimer of warranty and limitation of liability provided
615 | above cannot be given local legal effect according to their terms,
616 | reviewing courts shall apply local law that most closely approximates
617 | an absolute waiver of all civil liability in connection with the
618 | Program, unless a warranty or assumption of liability accompanies a
619 | copy of the Program in return for a fee.
620 |
621 | END OF TERMS AND CONDITIONS
622 |
623 | How to Apply These Terms to Your New Programs
624 |
625 | If you develop a new program, and you want it to be of the greatest
626 | possible use to the public, the best way to achieve this is to make it
627 | free software which everyone can redistribute and change under these terms.
628 |
629 | To do so, attach the following notices to the program. It is safest
630 | to attach them to the start of each source file to most effectively
631 | state the exclusion of warranty; and each file should have at least
632 | the "copyright" line and a pointer to where the full notice is found.
633 |
634 |
635 | Copyright (C)
636 |
637 | This program is free software: you can redistribute it and/or modify
638 | it under the terms of the GNU General Public License as published by
639 | the Free Software Foundation, either version 3 of the License, or
640 | (at your option) any later version.
641 |
642 | This program is distributed in the hope that it will be useful,
643 | but WITHOUT ANY WARRANTY; without even the implied warranty of
644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
645 | GNU General Public License for more details.
646 |
647 | You should have received a copy of the GNU General Public License
648 | along with this program. If not, see .
649 |
650 | Also add information on how to contact you by electronic and paper mail.
651 |
652 | If the program does terminal interaction, make it output a short
653 | notice like this when it starts in an interactive mode:
654 |
655 | Copyright (C)
656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
657 | This is free software, and you are welcome to redistribute it
658 | under certain conditions; type `show c' for details.
659 |
660 | The hypothetical commands `show w' and `show c' should show the appropriate
661 | parts of the General Public License. Of course, your program's commands
662 | might be different; for a GUI interface, you would use an "about box".
663 |
664 | You should also get your employer (if you work as a programmer) or school,
665 | if any, to sign a "copyright disclaimer" for the program, if necessary.
666 | For more information on this, and how to apply and follow the GNU GPL, see
667 | .
668 |
669 | The GNU General Public License does not permit incorporating your program
670 | into proprietary programs. If your program is a subroutine library, you
671 | may consider it more useful to permit linking proprietary applications with
672 | the library. If this is what you want to do, use the GNU Lesser General
673 | Public License instead of this License. But first, please read
674 | .
675 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # 16bitCPU-Verilog
2 | 16 bit CPU created in Vivado with Verilog, this was a project in Architecture of Computers subject, FIEK.
3 |
4 | ## Language
5 | Project is developed in Verilog.
6 |
7 |
8 | ## Confidential
9 | This project is developed from the authors below with full rights, u can take it use it but at least leave credit for us!
10 |
11 | ## Authors
12 | [Lorent Sinani](https://github.com/lorentsinani)
13 |
14 | [Era Kadiri](https://github.com/EraKadiri)
15 |
16 | [Meriton Kryeziu](https://github.com/meritonkryeziu0)
17 |
18 | [Lorik Mustafa](https://github.com/lorikmustafa)
19 |
20 | [Aridon Krasniqi](https://github.com/aridonkrasniqii)
21 |
--------------------------------------------------------------------------------
/simulation/CPUTest.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 09:03:35 PM
7 | // Design Name:
8 | // Module Name: CPUTest
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module CPUTest();
24 |
25 | reg Clock;
26 |
27 | initial
28 | begin
29 | #0 Clock = 1'b0; //#5 Clock = 1'b0;
30 | #100 Clock = 1'b0; // #10 Clock = 1'b1;
31 | end
32 |
33 | always
34 | begin
35 | #5 Clock = ~Clock;
36 | end
37 |
38 | CPU cpu(Clock);
39 | endmodule
40 |
--------------------------------------------------------------------------------
/simulation/DataMemory_Test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 09:05:06 PM
7 | // Design Name:
8 | // Module Name: DataMemory_Test
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module DataMemory_Test();
24 | reg Clock, MemWrite, MemRead;
25 | reg[15:0] Adresa;
26 | reg[15:0] WriteData;
27 | wire[15:0] ReadData;
28 |
29 | initial
30 | begin
31 | #0 Clock=1'b0;
32 | #5 MemWrite=1'b1; Adresa=16'b0000000000001001; WriteData=16'b0011001100110011; MemRead=1'b0;
33 | #5 Clock=1'b1;
34 | #5 Clock=1'b0;MemWrite=1'b0;
35 | #5 MemRead=1'b1; Adresa=16'b0000000000001001;
36 | #5 $stop;
37 | end
38 |
39 | DataMemory DM(Adresa, WriteData, Clock, MemWrite, MemRead, ReadData);
40 | endmodule
41 |
42 |
--------------------------------------------------------------------------------
/simulation/InstructionMemory_Test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 09:06:23 PM
7 | // Design Name:
8 | // Module Name: InstructionMemory_Test
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module InstructionMemory_Test();
24 | reg[15:0] PC;
25 | wire[15:0] Instruction;
26 | initial
27 | begin
28 | #0 PC=16'd10;
29 | #5 PC=16'd12;
30 | #5 PC=16'd14;
31 | #5 PC=16'd16;
32 | #5 PC=16'd18;
33 | #5 $stop;
34 | end
35 | InstructionMemory IM(PC,Instruction);
36 | endmodule
37 |
--------------------------------------------------------------------------------
/simulation/RegisterFile_Test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 09:06:23 PM
7 | // Design Name:
8 | // Module Name: RegisterFile_Test
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module RegisterFile_Test();
24 | reg[3:0] RS, RT, RD;
25 | reg RegWrite, Clock;
26 | reg[15:0] WriteData;
27 | wire[15:0] ReadRS, ReadRT;
28 | initial
29 | begin
30 | #0 Clock=1'b0;
31 | #5 RD=4'd8; WriteData = 16'd5; RegWrite=1'b1;
32 | #5 Clock=1'b1;
33 | #5 Clock=1'b0;RegWrite = 1'b1;
34 | #5 RD=4'd9; WriteData = 16'd7; RegWrite=1'b1;
35 | #5 Clock=1'b1;
36 | #5 Clock=1'b0; RegWrite=0;
37 | #5 RS=4'd8; RT=4'd9;
38 | #5 $stop;
39 | end
40 | RegisterFile RF(RS, RT, RD, WriteData, ReadRS, ReadRT, RegWrite, Clock);
41 | endmodule
42 |
--------------------------------------------------------------------------------
/sources/ALU_16bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/21/2022 03:34:26 PM
7 | // Design Name:
8 | // Module Name: ALU_16bit
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module ALU_16bit(
24 | input [15:0] A,
25 | input [15:0] B,
26 | input [2:0] Operation,
27 | input BNegate,
28 | output Zero,
29 | output Overflow,
30 | output CarryOut,
31 | output [15:0] Result
32 | );
33 |
34 | wire [14:0] COUT;
35 | //ALU_1bit ALU0(A, B, Cin, Bnegate, Less, operation, Result[0], COUT[0]);
36 | ALU_1bit ALU0( A[0], B[0], 0 , BNegate, Result[15], Operation, Result[0], COUT[0]);
37 | ALU_1bit ALU1( A[1], B[1], COUT[0], BNegate, 0 , Operation, Result[1], COUT[1]);
38 | ALU_1bit ALU2( A[2], B[2], COUT[1], BNegate, 0 , Operation, Result[2], COUT[2]);
39 | ALU_1bit ALU3( A[3], B[3], COUT[2], BNegate, 0 , Operation, Result[3], COUT[3]);
40 | ALU_1bit ALU4( A[4], B[4], COUT[3], BNegate, 0 , Operation, Result[4], COUT[4]);
41 | ALU_1bit ALU5( A[5], B[5], COUT[4], BNegate, 0 , Operation, Result[5], COUT[5]);
42 | ALU_1bit ALU6( A[6], B[6], COUT[5], BNegate, 0 , Operation, Result[6], COUT[6]);
43 | ALU_1bit ALU7( A[7], B[7], COUT[6], BNegate, 0 , Operation, Result[7], COUT[7]);
44 | ALU_1bit ALU8( A[8], B[8], COUT[7], BNegate, 0 , Operation, Result[8], COUT[8]);
45 | ALU_1bit ALU9( A[9], B[9], COUT[8], BNegate, 0 , Operation, Result[9], COUT[9]);
46 | ALU_1bit ALU10(A[10], B[10], COUT[9], BNegate, 0 , Operation, Result[10], COUT[10]);
47 | ALU_1bit ALU11(A[11], B[11], COUT[10], BNegate, 0 , Operation, Result[11], COUT[11]);
48 | ALU_1bit ALU12(A[12], B[12], COUT[11], BNegate, 0 , Operation, Result[12], COUT[12]);
49 | ALU_1bit ALU13(A[13], B[13], COUT[12], BNegate, 0 , Operation, Result[13], COUT[13]);
50 | ALU_1bit ALU14(A[14], B[14], COUT[13], BNegate, 0 , Operation, Result[14], COUT[14]);
51 | ALU_1bit ALU15(A[15], B[15], COUT[14], BNegate, 0 , Operation, Result[15], CarryOut);
52 |
53 | assign Zero = ~(Result[0] | Result[1] |
54 | Result[2] | Result[3] |
55 | Result[4] | Result[5] |
56 | Result[6] | Result[7] |
57 | Result[8] | Result[9] |
58 | Result[10] | Result[11] |
59 | Result[12] | Result[13] |
60 | Result[14] | Result[15]
61 | );
62 |
63 | assign Overflow = COUT[14] ^ CarryOut;
64 |
65 | endmodule
66 |
--------------------------------------------------------------------------------
/sources/ALU_1bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/22/2022 04:41:23 PM
7 | // Design Name:
8 | // Module Name: ALU_1bit
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module ALU_1bit(
22 | input A,
23 | input B,
24 | input CIN,
25 | input Bnegate,
26 | input Less,
27 | input [2:0] Operation,
28 | output Result,
29 | output COUT
30 | );
31 |
32 | wire JoA, JoB, mB, And, Or, AddnSub, Xor, Ori, Addi, Slti, Mod, Less;//telat edhe per instruksione tjera
33 |
34 | assign JoA = ~A;
35 | assign JoB = ~B;
36 |
37 | mux2ne1 muxB(B, JoB, Bnegate, mB);
38 | SltiFunction sltiFunc(A, B, Slti);
39 | modFunction modFunc(A, B, Mod);
40 | //Nese deshirojm qe me i be assign telat sipas opcode qe na vjen atehere eshte si me poshte
41 | // always @(A or B or Operation)
42 | // begin
43 | // case(Operation)
44 | // 3'b000: assign Andi = A & mb; //AND
45 | // 3'b001: assign Slti = ; //todo
46 | // 3'b010: assign Ori = A | mB
47 | // 3'b011: assign Xor = (JoA & B) | (A & JoB); //XOR
48 | // 3'b100: assign AddnSub = A + mb;
49 | // 3'b101: assign Addi = A + mb;//
50 | // 3'b111: assign Mod = ; //todo
51 | // endcase
52 | // end
53 |
54 | assign And = A & mB;
55 | //assign Sub = A + mB;
56 | assign Or = A | mB;
57 |
58 | assign Andi = A & mB;
59 | assign Xor = (JoA & B) | (A & JoB); // Xor = A ^ mB
60 | //assign AddnSub = A + mB;
61 | //assign Addi = A + mB; //njejt si addnsub veqse dallohet ne hyrje a i vjen reg apo imm
62 |
63 | Adder_1bit AddiFunc(A, mB, CIN, Addi, COUT);
64 | Adder_1bit Adder(A, mB, CIN, AddnSub, COUT);
65 |
66 | mux8ne1 muxAlu(Andi, Slti, Ori, Xor, AddnSub, Addi, Mod, Less, Operation, Result); //mux8ne1
67 | endmodule
68 |
--------------------------------------------------------------------------------
/sources/ALU_Control.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 08:45:44 PM
7 | // Design Name:
8 | // Module Name: ALU_Control
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module ALU_Control(
24 | input [2:0] opcode,
25 | input [1:0] ALUOp,
26 | input [3:0] Funct,
27 | output reg [3:0] Operacioni
28 | );
29 | always @(ALUOp)
30 | begin
31 | case(ALUOp)
32 | 2'b00:
33 | begin
34 | assign Operacioni = 4'b0100; //add
35 | end
36 | 2'b01:
37 | begin
38 | assign Operacioni = 4'b1100; //sub
39 | end
40 | 2'b10: //varet nga funct
41 | begin
42 | case(Funct)
43 | 4'b1101:
44 | begin
45 | assign Operacioni = 4'b0011; //xor
46 | end
47 | 4'b0000:
48 | begin
49 | assign Operacioni = 4'b0100; //add
50 | end
51 | 4'b0001:
52 | begin
53 | assign Operacioni = 4'b1100; //sub
54 | end
55 | 4'b0010:
56 | begin
57 | assign Operacioni = 4'b0111; // MOD
58 | end
59 | endcase
60 | end
61 |
62 | 2'b11: //ne baze te opcode
63 | begin
64 | case(opcode)
65 | 3'b100:
66 | begin
67 | assign Operacioni = 4'b0001; // SLTI
68 | end
69 | 3'b011:
70 | begin
71 | assign Operacioni = 4'b0101; //ADDI
72 | end
73 | 3'b010:
74 | begin
75 | assign Operacioni = 4'b0010; //ORI
76 | end
77 | 3'b001:
78 | begin
79 | assign Operacioni = 4'b0000; //ANDI
80 | end
81 | endcase
82 | end
83 | endcase
84 | end
85 | endmodule
--------------------------------------------------------------------------------
/sources/Adder_16bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/21/2022 12:31:36 PM
7 | // Design Name:
8 | // Module Name: Adder_16bit
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module Adder_16bit(
22 | input [15:0] A,
23 | input [15:0] B,
24 | output CarryOut,
25 | output [15:0] Result
26 | );
27 | wire [14:0] COUT;
28 | Adder_1bit adder16bit_0(A[0], B[0], 0, Result[0], COUT[0]);
29 | Adder_1bit adder16bit_1(A[1], B[1], COUT[0], Result[1], COUT[1]);
30 | Adder_1bit adder16bit_2(A[2], B[2], COUT[1], Result[2], COUT[2]);
31 | Adder_1bit adder16bit_3(A[3], B[3], COUT[2], Result[3], COUT[3]);
32 | Adder_1bit adder16bit_4(A[4], B[4], COUT[3], Result[4], COUT[4]);
33 | Adder_1bit adder16bit_5(A[5], B[5], COUT[4], Result[5], COUT[5]);
34 | Adder_1bit adder16bit_6(A[6], B[6], COUT[5], Result[6], COUT[6]);
35 | Adder_1bit adder16bit_7(A[7], B[7], COUT[6], Result[7], COUT[7]);
36 | Adder_1bit adder16bit_8(A[8], B[8], COUT[7], Result[8], COUT[8]);
37 | Adder_1bit adder16bit_9(A[9], B[9], COUT[8], Result[9], COUT[9]);
38 | Adder_1bit adder16bit_10(A[10], B[10], COUT[9], Result[10], COUT[10]);
39 | Adder_1bit adder16bit_11(A[11], B[11], COUT[10], Result[11], COUT[11]);
40 | Adder_1bit adder16bit_12(A[12], B[12], COUT[11], Result[12], COUT[12]);
41 | Adder_1bit adder16bit_13(A[13], B[13], COUT[12], Result[13], COUT[13]);
42 | Adder_1bit adder16bit_14(A[14], B[14], COUT[13], Result[14], COUT[14]);
43 | Adder_1bit adder16bit_15(A[15], B[15], COUT[14], Result[15], CarryOut);
44 | endmodule
45 |
--------------------------------------------------------------------------------
/sources/CPU.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 08:31:49 PM
7 | // Design Name:
8 | // Module Name: CPU
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module CPU(input Clock);
24 |
25 | reg[15:0] PC_Initial;
26 | reg[15:0] PCPlus4;
27 | reg[15:0] PC;
28 | reg[15:0] PC_CURRENT;
29 | reg[15:0] PC_BEQ;
30 | reg[15:0] PC_JUMP;
31 | wire[15:0] Instruction;
32 | wire[15:0] BEQPC;
33 | wire[15:0] JUMPPC;
34 |
35 | initial
36 | begin
37 | assign PC_Initial = 16'd0;
38 | end
39 |
40 | always@(posedge Clock)
41 | begin
42 | assign PC = (Jump) ? JUMPPC : BEQPC; //BEQ EDHE BNE NKET RAST ISHIN KON NJEJT NKOD
43 | end
44 |
45 | InstructionMemory IM(PC, Instruction);
46 |
47 | DataPath DP(Clock, PC, RegDst,
48 | Jump,
49 | Branch,
50 | MemRead,
51 | MemWrite,
52 | MemToReg,
53 | ALUSrc,
54 | RegWrite,
55 | ALUOp,
56 | Instruction, BEQPC, JUMPPC);
57 |
58 | ControlUnit CU(Instruction[15:10],RegDst,
59 | Jump,
60 | Branch,
61 | MemRead,
62 | MemWrite,
63 | MemToReg,
64 | ALUSrc,
65 | RegWrite,
66 | ALUOp);
67 |
68 | endmodule
69 |
--------------------------------------------------------------------------------
/sources/ControlUnit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/23/2022 03:53:46 PM
7 | // Design Name:
8 | // Module Name: ControlUnit
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module ControlUnit(
24 | input [2:0] OPCODE,
25 | output reg RegDst,
26 | output reg ALUSrc,
27 | output reg MemToReg,
28 | output reg RegWrite,
29 | output reg MemRead,
30 | output reg MemWrite,
31 | output reg [1:0] ALUOp,
32 | output reg Branch
33 | );
34 | always @(OPCODE)
35 | begin
36 |
37 | case(OPCODE)
38 | 3'b111: //BNE
39 | begin
40 | assign RegDst = 1'b0;
41 | assign ALUSrc = 1'b0;
42 | assign MemToReg = 1'b0;
43 | assign RegWrite = 1'b0;
44 | assign MemRead = 1'b0;
45 | assign MemWrite = 1'b0;
46 | assign ALUOp = 2'b01;
47 | assign Branch = 1'b1;
48 | end
49 |
50 | 3'b000: //XOR || SUB || MOD
51 | begin
52 | assign RegDst = 1'b1;
53 | assign ALUSrc = 1'b0;
54 | assign MemToReg = 1'b0;
55 | assign RegWrite = 1'b1;
56 | assign MemRead = 1'b0;
57 | assign MemWrite = 1'b0;
58 | assign ALUOp = 2'b10;
59 | assign Branch = 1'b0;
60 | end
61 |
62 | 3'b001: //ANDI
63 | begin
64 | assign RegDst = 1'b0;
65 | assign ALUSrc = 1'b1;
66 | assign MemToReg = 1'b0;
67 | assign RegWrite = 1'b1;
68 | assign MemRead = 1'b0;
69 | assign MemWrite = 1'b0;
70 | assign ALUOp = 2'b11;
71 | assign Branch = 1'b0;
72 | end
73 |
74 | 3'b100: //SLTI
75 | begin
76 | assign RegDst = 1'b0;
77 | assign ALUSrc = 1'b1;
78 | assign MemToReg = 1'b0;
79 | assign RegWrite = 1'b1;
80 | assign MemRead = 1'b0;
81 | assign MemWrite = 1'b0;
82 | assign ALUOp = 2'b11;
83 | assign Branch = 1'b0;
84 | end
85 |
86 | 3'b011: //ADDI
87 | begin
88 | assign RegDst = 1'b0;
89 | assign ALUSrc = 1'b1;
90 | assign MemToReg = 1'b0;
91 | assign RegWrite = 1'b1;
92 | assign MemRead = 1'b0;
93 | assign MemWrite = 1'b0;
94 | assign ALUOp = 2'b11;
95 | assign Branch = 1'b0;
96 | end
97 |
98 | 3'b010: //ORI
99 | begin
100 | assign RegDst = 1'b0;
101 | assign ALUSrc = 1'b1;
102 | assign MemToReg = 1'b0;
103 | assign RegWrite = 1'b1;
104 | assign MemRead = 1'b0;
105 | assign MemWrite = 1'b0;
106 | assign ALUOp = 2'b11;
107 | assign Branch = 1'b0;
108 | end
109 |
110 | 3'b101: //LW
111 | begin
112 | assign RegDst = 1'b0;
113 | assign ALUSrc = 1'b1;
114 | assign MemToReg = 1'b1;
115 | assign RegWrite = 1'b1;
116 | assign MemRead = 1'b1;
117 | assign MemWrite = 1'b0;
118 | assign ALUOp = 2'b00;
119 | assign Branch = 1'b0;
120 | end
121 |
122 | 3'b110: //SW
123 | begin
124 | assign RegDst = 1'b0;
125 | assign ALUSrc = 1'b1;
126 | assign MemToReg = 1'b0;
127 | assign RegWrite = 1'b0;
128 | assign MemRead = 1'b0;
129 | assign MemWrite = 1'b1;
130 | assign ALUOp = 2'b00;
131 | assign Branch = 1'b0;
132 | end
133 |
134 | endcase
135 |
136 | end
137 | endmodule
--------------------------------------------------------------------------------
/sources/DataMemory.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/23/2022 06:23:23 PM
7 | // Design Name:
8 | // Module Name: DataMemory
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module DataMemory(input[15:0] Adresa, input[15:0] WriteData,
22 | input Clock, input MemWrite, input MemRead, output[15:0] ReadData);
23 | reg[7:0] dMem[127:0];
24 |
25 | initial $readmemb("dataMemory.mem", dMem);
26 |
27 | always @(posedge Clock)
28 | begin
29 |
30 | if(MemWrite)
31 | begin
32 | dMem[Adresa] <= WriteData[15:8];
33 | dMem[Adresa+1] <= WriteData[7:0];
34 | end
35 |
36 | end
37 |
38 | always @(negedge Clock)
39 | begin
40 | $writememb("dataMemory.mem", dMem);
41 | end
42 | assign ReadData = {dMem[Adresa],dMem[Adresa+1]};
43 | endmodule
44 |
--------------------------------------------------------------------------------
/sources/DataPath.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/22/2022 10:27:13 AM
7 | // Design Name:
8 | // Module Name: DataPath
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module DataPath(
22 | input Clock,
23 | input RegDst, Branch, MemRead,
24 | MemWrite, RegWrite, MemToReg, ALUSrc,
25 | input [1:0] ALUOp,
26 | output [2:0] opcode
27 | );
28 |
29 |
30 | reg[15:0] pc_initial;
31 | wire [15:0] pc_next, pc4, pcbne;
32 | wire [15:0] instruction, instr;
33 | wire [2:0] mux_regfile;
34 | wire[15:0] readData1, readData2, writeData,
35 | mux_ALU, ALU_Out, Zgjerimi, memToMux,
36 | shifter2beq, branchAdderToMux, beqAddress, jumpAddress;
37 | wire[3:0] ALUCtrl;
38 | wire zerof, overflow, carryout;
39 | wire andMuxBranch;
40 |
41 | initial
42 | begin
43 | pc_initial = 16'd10;
44 | end
45 |
46 | always@(posedge Clock)
47 | begin
48 | pc_initial <= pc_next;
49 |
50 | end
51 |
52 |
53 | assign pc4 = pc_initial + 2;
54 |
55 |
56 | assign shifter2beq = {{8{instruction[6]}}, instruction[6:0], 1'b0};
57 |
58 | InstructionMemory IM(pc_initial, instruction);
59 |
60 |
61 | assign mux_regfile = (RegDst == 1'b1) ? instruction[6:4] : instruction[9:7];
62 |
63 |
64 | assign Zgjerimi = {{9{instruction[6]}}, instruction[6:0]};
65 |
66 |
67 |
68 | RegisterFile RF(instruction[12:10], instruction[9:7], mux_regfile, writeData, RegWrite, Clock, readData1, readData2 );
69 |
70 |
71 | assign mux_ALU = (ALUSrc == 1'b1) ? Zgjerimi : readData2;
72 |
73 |
74 | ALU_Control AC(ALUOp, instr[3:0], instruction[15:13], ALUCtrl);
75 |
76 | // [15:0] A, [15:0] B, [2:0] Operation, BNegate, Zero, Overflow, CarryOut, [15:0] Result
77 | ALU_16bit ALU(readData1, mux_ALU, ALUCtrl[2:0], ALUCtrl[3], zerof, overflow, carryout, ALU_Out);
78 |
79 |
80 | DataMemory DM(ALU_Out, MemWrite, MemRead, Clock, memToMux);
81 |
82 |
83 | assign writeData = (MemToReg == 1'b1) ? memToMux : ALU_Out;
84 |
85 |
86 | assign andMuxBranch = ~(zerof & Branch);
87 |
88 |
89 | assign beqAddress = pc4 + shifter2beq;
90 |
91 |
92 | assign pc_next = (andMuxBranch == 1'b1) ? beqAddress : pc4;
93 |
94 | assign opcode = instruction[15:13];
95 |
96 | endmodule
97 |
--------------------------------------------------------------------------------
/sources/InstructionMemory.v:
--------------------------------------------------------------------------------
1 | mescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/24/2022 08:35:58 PM
7 | // Design Name:
8 | // Module Name: InstructionMemory
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module InstructionMemory(input[15:0] PC, output[15:0] Instruction);
24 |
25 | reg[7:0] iMem[127:0];
26 |
27 | initial $readmemb("instrMemory.mem", iMem);
28 |
29 | assign Instruction = {iMem[PC], iMem[PC+1]};
30 |
31 | endmodule
32 |
--------------------------------------------------------------------------------
/sources/RegisterFile.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/12/2022 05:26:23 PM
7 | // Design Name:
8 | // Module Name: RegisterFile
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module RegisterFile(
22 | input[2:0] RS,
23 | input[2:0] RT,
24 | input[2:0] RD,
25 | input[15:0] WriteData,
26 | output[15:0] ReadRS,
27 | output[15:0] ReadRT,
28 | input RegWrite,
29 | input Clock);
30 |
31 | reg [15:0] Registers[7:0];
32 |
33 | always @(posedge Clock)
34 | begin
35 |
36 | if(RegWrite)
37 | begin
38 | Registers[RD] <= WriteData;
39 | end
40 |
41 | end
42 |
43 | assign ReadRS = Registers[RS];
44 | assign ReadRT = Registers[RT];
45 | endmodule
46 |
47 |
--------------------------------------------------------------------------------
/sources/SltiFunction.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/26/2022 02:44:08 PM
7 | // Design Name:
8 | // Module Name: SltiFunction
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module SltiFunction(
24 | input rs, // A
25 | input immediate, // mB
26 | output rt // slti
27 | );
28 |
29 | assign rt = (rs < immediate) ? 1 : 0;
30 | endmodule
31 |
--------------------------------------------------------------------------------
/sources/dataMemory.mem:
--------------------------------------------------------------------------------
1 |
2 |
--------------------------------------------------------------------------------
/sources/instrMemory.mem:
--------------------------------------------------------------------------------
1 | 00000000
2 | 00000000
3 | 00000000
4 | 00000000
5 | 00000000
6 | 00000000
7 | 00000000
8 | 00000000 // 8421
9 | 00000000
10 | 00000000 //#OPCODE RS RT RD FUNCT (R-Format)
11 | 0000_0000 // add $r1, $zero, $zero 000 000 000 001 _0000
12 | 0001_0000 #OPCODE RS RT IMMEDIATE (I-Format)
13 | 1010_0101 // lw $r2, 4($r1) 101 001 010 000_0100
14 | 0000_0100
15 | 0000_1001 // xor $r1, $r2, $r3 000 010 011 001 1101
16 | 1001_1101
17 | 1110_1000 // bne $r2, $zero, kercimi 1110_1000 0000_0001 111 010 000 0000001 kcen per 1 000_0001
18 | 0000_0001
19 | 0010_0101 // andi $r3, $r1, 5 001 001 011 0000101
20 | 1000_0101
21 | 1100_1001 // kercimi: sw $r3, 4($r2) 110 010 011 0000100
22 | 1000_0100
23 | 0110_1100 // addi $r4, $r3, 4 011 011 001 0000101
24 | 1000_0101
25 | 1001_0110 // slti $r5, $r4, 2 100 101 100 0000010
26 | 0000_0010
27 | 0001_0110 // mod $r6 $r5, $r4 000 101 100 110 0010
28 | 0110_0010
29 | 00000000
30 | 00000000
31 | 00000000
32 | 00000000
33 | 00000000
34 | 00000000
35 | 00000000
36 | 00000000
37 | 00000000
38 | 00000000
39 | 00000000
40 | 00000000
41 | 00000000
42 | 00000000
43 | 00000000
44 | 00000000
45 | 00000000
46 | 00000000
47 | 00000000
48 | 00000000
49 | 00000000
50 | 00000000
51 | 00000000
52 | 00000000
53 | 00000000
54 | 00000000
55 | 00000000
56 | 00000000
57 | 00000000
58 | 00000000
59 | 00000000
60 | 00000000
61 | 00000000
62 | 00000000
63 | 00000000
64 | 00000000
65 | 00000000
66 | 00000000
67 | 00000000
68 | 00000000
69 | 00000000
70 | 00000000
71 | 00000000
72 | 00000000
73 | 00000000
74 | 00000000
75 | 00000000
76 | 00000000
77 | 00000000
78 | 00000000
79 | 00000000
80 | 00000000
81 | 00000000
82 | 00000000
83 | 00000000
84 | 00000000
85 | 00000000
86 | 00000000
87 | 00000000
88 | 00000000
89 | 00000000
90 | 00000000
91 | 00000000
92 | 00000000
93 | 00000000
94 | 00000000
95 | 00000000
96 | 00000000
97 | 00000000
98 | 00000000
99 | 00000000
100 | 00000000
101 | 00000000
102 | 00000000
103 | 00000000
104 | 00000000
105 | 00000000
106 | 00000000
107 | 00000000
108 | 00000000
109 | 00000000
110 | 00000000
111 | 00000000
112 | 00000000
113 | 00000000
114 | 00000000
115 | 00000000
116 | 00000000
117 | 00000000
118 | 00000000
119 | 00000000
120 | 00000000
121 | 00000000
122 | 00000000
123 | 00000000
124 | 00000000
125 | 00000000
126 | 00000000
127 | 00000000
128 | 00000000
--------------------------------------------------------------------------------
/sources/modFunction.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/26/2022 03:39:09 PM
7 | // Design Name:
8 | // Module Name: modFunction
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 | //vetem per mod pozitiv
23 | module modFunction(
24 | input Hyrja1, //A
25 | input Hyrja2, //B
26 | output Dalja //MOD
27 | );
28 |
29 | //Hyrja1 % Hyrja 2 = Dalja
30 | integer num2, num1;
31 |
32 | initial
33 | begin
34 | num2 = Hyrja2;
35 | num1 = Hyrja1;
36 | while(num2 < num1)
37 | begin
38 | assign num2 = num2 + Hyrja2;
39 | end
40 | assign num2 = num2 - Hyrja2;
41 | end
42 |
43 | assign Dalja = num1 - num2;
44 |
45 | endmodule
46 |
--------------------------------------------------------------------------------
/sources/mux2ne1.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/17/2022 02:49:58 PM
7 | // Design Name:
8 | // Module Name: mux2ne1
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 | module mux2ne1(
23 | input Hyrja0, //B
24 | input Hyrja1, // JOB
25 | input S, // Bnegate
26 | output Dalja // mB
27 | );
28 |
29 | assign Dalja = S ? Hyrja1 : Hyrja0;
30 |
31 | endmodule
--------------------------------------------------------------------------------
/sources/mux8ne1.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 05/22/2022 02:52:35 PM
7 | // Design Name:
8 | // Module Name: mux8ne1
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module mux8ne1(
24 | input Hyrja0,
25 | input Hyrja1,
26 | input Hyrja2,
27 | input Hyrja3,
28 | input Hyrja4,
29 | input Hyrja5,
30 | input Hyrja6,
31 | input Hyrja7,
32 | input [2:0] S,
33 | output Dalja
34 | );
35 |
36 | // s 000 h0 ANDI
37 | // s 001 h1 SLTI
38 | // s 010 h2 ORI
39 | // s 011 h3 XOR
40 | // s 100 h4 SUB/ ADD
41 | // s 101 h5 ADDI
42 | // s 111 h6 Mod
43 | // s 110 h7 LESS
44 |
45 | assign Dalja = S[2] ? (S[1] ? (S[0] ? Hyrja7 : Hyrja6) : (S[0] ? Hyrja5 : Hyrja4)) : (S[1] ? (S[0] ? Hyrja3 : Hyrja2): (S[0] ? Hyrja1: Hyrja0));
46 |
47 | endmodule
48 |
--------------------------------------------------------------------------------