├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── common ├── Makefrag ├── load_card.sh ├── make_bitstream.tcl ├── rocketchip_wrapper.v └── zynq_rocketchip.tcl ├── rocket-chip └── zedboard ├── Makefile ├── build_image.sh ├── soft_config ├── skeleton.dtsi ├── zedboard_devicetree.dts ├── zynq-7000.dtsi └── zynq_zed.h └── src ├── constrs └── base.xdc ├── tcl ├── build_fsbl.tcl ├── export_hardware.tcl └── zedboard_bd.tcl └── verilog ├── Top.DefaultFPGAConfig.v └── clocking.vh /.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | *.Xil 4 | 5 | zedboard/zedboard_rocketchip 6 | zedboard/src/tcl/zedboard_rocketchip.tcl 7 | zedboard/src/tcl/make_bitstream.tcl 8 | zedboard/src/verilog/rocketchip_wrapper.v 9 | zedboard/deliver_output 10 | zedboard/soft_build 11 | 12 | zybo/zybo_rocketchip 13 | zybo/src/tcl/zybo_rocketchip.tcl 14 | zybo/src/tcl/make_bitstream.tcl 15 | zybo/src/verilog/rocketchip_wrapper.v 16 | zybo/deliver_output 17 | zybo/soft_build 18 | 19 | zc706/zc706_rocketchip 20 | zc706/src/tcl/zc706_rocketchip.tcl 21 | zc706/src/tcl/make_bitstream.tcl 22 | zc706/src/verilog/rocketchip_wrapper.v 23 | zc706/deliver_output 24 | zc706/soft_build 25 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "common/u-boot-xlnx"] 2 | path = common/u-boot-xlnx 3 | url = https://github.com/Xilinx/u-boot-xlnx.git 4 | branch = master-next 5 | [submodule "common/linux-xlnx"] 6 | path = common/linux-xlnx 7 | url = https://github.com/Xilinx/linux-xlnx.git 8 | branch = master-next 9 | [submodule "zedboard/fpga-images-zedboard"] 10 | path = zedboard/fpga-images-zedboard 11 | url = https://github.com/lowrisc/lowrisc-images-zedboard.git 12 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2014, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Rocket Chip on Zynq FPGAs 2 | ========================= 3 | 4 | This repository contains the files needed to run the RISC-V [rocket chip](https://github.com/ucb-bar/rocket-chip) on 5 | various Zynq FPGA boards ([Zybo](http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO), [Zedboard](http://zedboard.org/product/zedboard), [ZC706](http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm)) with Vivado 2014.4. Efforts have been made to not only automate the process of generating files for these boards, but to also reduce duplication as well as the size of this repo. Prebuilt images are available in git submodules, and they are only shallowly cloned if requested. 6 | 7 | 8 | ###How to use this README 9 | 10 | This README contains 3 major sets of instructions: 11 | 12 | 1) [Quick Instructions](#quickinst): This is the simplest way to get started - you'll download the relevant prebuilt images for your board and learn how to run binaries on the RISC-V Rocket Core. These instructions require only that you have a compatible board - neither Vivado nor the RISC-V Toolchain are necessary. 13 | 14 | 2) [Pushing Your Rocket Modifications to the FPGA](#bitstream): These instructions walk through what we believe is the common case - a user wanting to utilize a custom-generated Rocket Core. 15 | 16 | 3) [Building Everything from Scratch](#fromscratch): Here, we discuss how to build the full stack from scratch. It is unlikely that you'll need to use these instructions, unless you are intending to make changes to the configuration of the Zynq ARM Core or `u-boot`. 17 | 18 | Finally, the bottom of the README contains a set of [Appendices](#appendices), which document some common operations that we believe are useful or provides more depth on commands described elsewhere in the documentation. 19 | 20 | To guide you through the rest of the documentation, we have provide both a [Table of Contents](#toc) and an [Overview](#overview). 21 | 22 | 23 | ### Table of Contents 24 | + [Overview of System Stack](#overview) 25 | + [1 - Quick Instructions](#quickinst) 26 | + [2 - Pushing Your Rocket Modifications to the FPGA](#bitstream) 27 | + [Setting Up Your Workspace](#workspace) 28 | + [Configuring Rocket Chip](#configRC) 29 | + [Propagating Changes to the Vivado Project](#propRC) 30 | + [Repacking `boot.bin`](#repack) 31 | + [3 - Building Everything from Scratch](#fromscratch) 32 | + [Project Setup](#setup) 33 | + [Generating a Bitstream](#bitstream) 34 | + [Building the FSBL](#fsbl) 35 | + [Building u-boot for the Zynq ARM Core](#u-boot) 36 | + [Creating `boot.bin`](#boot.bin) 37 | + [Building linux for the ARM PS](#arm-linux) 38 | + [Building riscv-linux](#riscv-linux) 39 | + [Booting Up and Interacting with the RISC-V Rocket Core](#booting) 40 | + [Appendices](#appendices) 41 | + [Connecting to the Board](#connecting) 42 | + [Getting Files On & Off the Board](#transferring) 43 | + [Working with Vivado](#vivado) 44 | + [Changing the Processor's Clockrate](#clockrate) 45 | + [Contents of the SD Card](#sdcard) 46 | + [Building fesvr-zynq](#fesvr) 47 | + [Acknowledgements](#ack) 48 | 49 | 50 | 51 | ### Overview of System Stack 52 | Our system will allow you to run a RISC-V binary on a rocket core instantiated on a supported Zynq FPGA. This section will outline the stack of all of the parts involved and by proxy, outline the rest of the documentation. Going top-down from the RISC-V binary to the development system: 53 | 54 | **Target Application** (RISC-V binary) 55 | will run on top of whatever kernel the rocket chip is running. Compiled by [riscv-gcc](https://github.com/ucb-bar/riscv-gcc) or [riscv-llvm](https://github.com/ucb-bar/riscv-llvm). 56 | 57 | **RISC-V Kernel** ([proxy kernel](https://github.com/ucb-bar/riscv-pk) or [RISC-V Linux](https://github.com/ucb-bar/riscv-linux)) 58 | runs on top of the rocket chip. The proxy kernel is extremely lightweight and designed to be used with a single binary linked against Newlib while RISC-V Linux is appropriate for everything else. 59 | 60 | **Rocket Chip** ([rocket core](https://github.com/ucb-bar/rocket) with L1 instruction and data caches) 61 | is instantiated on the FPGA. Many of its structures will typically map to various hard blocks including BRAMs and DSP slices. It communicates to the host ARM core on the Zynq via AXI. 62 | 63 | **Front-end Server** ([riscv-fesvr](https://github.com/ucb-bar/riscv-fesvr)) 64 | runs on the host ARM core and provides an interface to the rocket chip running on the FPGA (connected via AXI). 65 | 66 | **Zynq ARM Core** (actually dual Cortex A9) 67 | runs Linux and simplifies interfacing with the FPGA. 68 | 69 | **FPGA Board** (Zybo, Zedboard, or ZC706) 70 | contains the Zynq FPGA and several I/O devices. At power on, the contents of the SD card are used to configure the FPGA and boot Linux on the ARM core. 71 | 72 | **External Communication** (TTY over serial on USB or telnet/ssh over ethernet) 73 | allows the development system to communicate with the FPGA board. 74 | 75 | **Development System** (PC with SD card reader) 76 | generates the images to configure the FPGA. 77 | 78 | 79 | 80 | 1) Quick Instructions 81 | ------------------ 82 | _Using prebuilt images, run hello world and/or linux on rocket_ 83 | 84 | First, enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). From there, run the following to download all of the necessary images: 85 | 86 | $ make fetch-images 87 | 88 | If you'd also like to try riscv-linux on rocket, run the following: 89 | 90 | $ make fetch-riscv-linux 91 | 92 | Next, insert the SD card on the development system and copy over the images: 93 | 94 | $ make load-sd SD=path_to_mounted_sdcard 95 | 96 | Finally, eject the SD card, insert it into the board and power the board on. Connect to the board with an ethernet cable (password is _root_) and run hello world: 97 | 98 | $ ssh root@192.168.1.5 99 | root@zynq:~# ./fesvr-zynq pk hello 100 | hello! 101 | 102 | Awesome! You can now run RISC-V binaries on Rocket. If you'd like to boot linux on the Rocket core, see _[Booting Up and Interacting with the RISC-V Rocket Core](#booting)_. 103 | 104 | 105 | 106 | 2) Pushing Your Rocket Modifications to the FPGA 107 | ------------------------- 108 | 109 | #### Setting Up Your Workspace 110 | _Requires: Vivado 2014.4 and its settings64.sh sourced_ 111 | 112 | If you don't already have a copy of the rocket chip, get a new one: 113 | 114 | $ git clone https://github.com/ucb-bar/rocket-chip.git 115 | 116 | Move `fpga-zynq` (this repo) to be within rocket-chip: 117 | 118 | $ mv path_to_fpga-zynq/fpga-zynq rocket-chip/ 119 | 120 | _Note:_ If you like, you can have fpga-zynq and rocket-chip have any relative position as long as you change the symlink `fpga-zynq/rocket-chip` to point to rocket-chip (by default it is .., its parent directory). 121 | 122 | Enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). Generate a Vivado project for the board: 123 | 124 | $ make project 125 | 126 | #### Configuring Rocket Chip 127 | 128 | The verilog for the rocket chip is generated by [Chisel](https://chisel.eecs.berkeley.edu) and thus is not intended to be edited by humans. To change the rocket chip, you should modify its chisel code and regenerate the verilog. For information on changing rocket chip, consult its [documentation](https://github.com/ucb-bar/rocket-chip). 129 | 130 | #### Propagating Changes to the Vivado Project 131 | _Requires: JVM that can run Scala_ 132 | 133 | After making changes within `rocket-chip`, to run the rocket chip generator and copy the newly generated verilog back into the board's source, run: 134 | 135 | $ make rocket 136 | 137 | The rocket chip will be configured by the configuration named `CONFIG` in the board's `Makefile`. If you wish to use a different configuration, you will need to change your vivado project to be aware of the new verilog source or regenerate the project because configuration names are included in the filename (e.g. _Top.DefaultConfig.v_). 138 | 139 | #### Repacking `boot.bin` 140 | 141 | Once you have changed the design, you will need to generate a new bitstream and that will need to be packaged in `boot.bin`. `boot.bin` also contains the binaries needed for startup (`FSBL.elf` and `u-boot.elf`) but these can be reused. From within the board's directory (_zybo_ in this example), to repack `boot.bin`: 142 | 143 | $ make fpga-images-zybo/boot.bin 144 | 145 | If you have modified the verilog for your project but not generated a new bitstream, `make` should generate a new bitstream automatically. To use the new `boot.bin`, copy it to the SD card, insert the SD card into the board, and power on the board. 146 | 147 | 148 | 149 | 3) Building Everything from Scratch 150 | ----------------------- 151 | This section describes how to build the entire project from scratch. Most likely, you will not need to perform all of these steps, however we keep them here for reference. Various other sections of this README may selectively refer to these sections. This section assumes that you've just pulled this repository and have sourced the settings file for Vivado 2014.4. 152 | 153 | For ease of exposition, we will be describing all of the commands assuming that we are working with the `zybo`. Replacing references to the `zybo` with `zedboard` or `zc706` will allow you to use these instructions for those boards. 154 | 155 | From here on, `$REPO` will refer to the location of the `fpga-zynq` repository. 156 | 157 | ### 3.1) Project Setup 158 | 159 | First, we need to generate a Vivado project from the source files that are present in a particular board's directory. 160 | 161 | $ cd $REPO/zybo 162 | $ make project 163 | 164 | ### 3.2) Generating a Bitstream 165 | 166 | Next, let's open up the project in the Vivado GUI: 167 | 168 | $ make vivado 169 | # OR 170 | $ cd zybo_rocketchip 171 | $ vivado zybo_rocketchip.xpr 172 | 173 | If you wish to make any modifications to the project, you may now do so. Once you've finished, let's move on: 174 | 175 | Inside Vivado, select _Open Block Design_ followed by _system.bd_ in the dropdown. This will open a block diagram for the Zynq PS Configuration and is necessary for correct FSBL generation. 176 | 177 | Next, select _Generate Bitstream_. Vivado will now step through the usual Synthesis/Implementation steps. Upon completion, if you're interested in only the bitstream, you can stop here; the file you want is in: 178 | 179 | `$REPO/zybo/zybo_rocketchip/zybo_rocketchip.runs/impl_1/rocketchip_wrapper.bit` 180 | 181 | Otherwise, let's continue on to select _Open Implemented Design_. This is again necessary to properly export the description of our Hardware for the Xilinx SDK to use. 182 | 183 | At this point, select _File -> Export -> Export Hardware_. This will create the following directory: 184 | 185 | `$REPO/zybo/zybo_rocketchip/zybo_rocketchip.sdk` 186 | 187 | This directory contains a variety of files that provide information about the hardware to the SDK. Let's continue on to building the FSBL. 188 | 189 | 190 | ### 3.3) Building the FSBL 191 | 192 | This step assumes that you have just generated the bitstream. Inside the Vivado GUI, select "Launch SDK". This will open up the Xilinx SDK preconfigured with the description of our hardware. In order to generate the FSBL, do the following: 193 | 194 | 1) Select _File -> New -> Application Project_ 195 | 196 | 2) In the new window, type "FSBL" as the Project name, and ensure that the rest of the properties are correctly set (disregarding the greyed out _Location_ field): 197 | 198 | 199 | 200 | 3) Select _Next_, at which point you should be given a set of options. Select _Zynq FSBL_ and _Finish_. 201 | 202 | 4) The SDK will proceed to automatically compile the FSBL. You can see the progress in the Console. 203 | 204 | 5) Once the build is finished, we need to build u-boot before returning to the SDK in order to create our BOOT.bin. 205 | 206 | ### 3.4) Building u-boot for the Zynq ARM Core 207 | 208 | Returning to the command line, do the following from the directory corresponding to your board: 209 | 210 | $ make arm-uboot 211 | 212 | This target performs a variety of commands. It will first pull the u-boot source from the Xilinx repositories (see the submodule in `$REPO/common/u-boot-xlnx`), patch it with the necessary files found in `$REPO/zybo/soft_config/`, compile u-boot, and place the resulting u-boot.elf file in `$REPO/zybo/soft_build/u-boot.elf`. 213 | 214 | ### 3.5) Creating `boot.bin` 215 | 216 | At this point, we have built up all of the necessary components to create our `boot.bin` file. Returning to the Xilinx SDK, select _Xilinx Tools -> Create Zynq Boot Image_. 217 | 218 | First, you should fill in the _Output BIF file path_ with `$REPO/zybo/deliver_output`. If this directory has not already been created, you may go ahead and create it (this is where we will place all of the items that we will ultimately transfer to the SD card). See the below for a sample path. Performing this step will also fill in the _Output path_ field, which specifies the location of the `BOOT.bin` file that we desire. 219 | 220 | Next, we will add the individual files that make up `BOOT.bin`. Order is important, so follow these steps exactly: 221 | 222 | 1) Select _Add_ and in the window that opens, click _Browse_ and specify the following location: 223 | 224 | `$REPO/zybo/zybo_rocketchip/zybo_rocketchip.sdk/FSBL/Debug/FSBL.elf` 225 | 226 | Once you have done so select the dropdown next to _Partition type_ and select _bootloader_. You must perform this step **after** selecting the path, else the SDK will change it back to _datafile_, and your `BOOT.bin` will not work. 227 | 228 | At the conclusion of this step, the _Add partition_ window will look something like: 229 | 230 | 231 | 232 | Click _OK_to return to the previous window. 233 | 234 | 2) Once more, click _Add_. In the new _Add partition_ window, click _Browse_ and specify the following location: 235 | 236 | `$REPO/zybo/zybo_rocketchip/zybo_rocketchip.runs/impl_1/rocketchip_wrapper.bit` 237 | 238 | Ensure that _Partition type_ is set to datafile and click _OK_. 239 | 240 | 3) Click _Add_ a final time. Click _Browse_ and this time select our compiled `u-boot.elf`: 241 | 242 | `$REPO/zybo/soft_build/u-boot.elf` 243 | 244 | Again, ensure that _Partition type_ is set to datafile and click _OK_. 245 | 246 | 4) At this point, the window should match the following (click the image to zoom in): 247 | 248 | 249 | 250 | Select _Create Image_. This will produce a `BOOT.bin` file in the `$REPO/zybo/deliver_output` directory. 251 | 252 | If you make modifications to the project in the future, you can avoid having to perform this step manually and 253 | instead may reuse the output.bif file that the SDK generates the first time you use _Create Zynq Boot Image._ 254 | Use the following make target to do so: 255 | 256 | $ make deliver_output/boot.bin 257 | 258 | ### 3.6) Building linux for the ARM PS 259 | 260 | As part of our bootstrapping process, we need to boot linux on the ARM core in the Zynq. We can build this copy of linux like so (again assuming that we are in `$REPO/zybo`): 261 | 262 | $ make arm-linux 263 | 264 | We additionally need to produce the `devicetree.dtb` file that linux will use to setup peripherals of the ARM core. We can produce this like so: 265 | 266 | $ make arm-dtb 267 | 268 | At this point, the `$REPO/zybo/deliver_output` directory contains the following files: 269 | 270 | * `BOOT.bin` - (the filename is case insensitive, you may see `boot.bin`). This contains the FSBL, the bitstream with Rocket, and u-boot. 271 | * `uImage` - Linux for the ARM PS 272 | * `devicetree.dtb` - Contains information about the ARM core's peripherals for linux. 273 | 274 | The only remaining file that we are missing at this point is `uramdisk.image.gz`, the root filesystem for linux on the ARM Core. You can obtain it like so (it will be placed in `$REPO/zybo/deliver_output`): 275 | 276 | $ make fetch-ramdisk 277 | 278 | Now, take the four files in `deliver_output/`, and place them on the root of the SD card that we will insert into the Zybo. The layout of your SD card should match the following: 279 | 280 | SD_ROOT/ 281 | |-> boot.bin 282 | |-> devicetree.dtb 283 | |-> uImage 284 | |-> uramdisk.image.gz 285 | 286 | At this point, you have performed the necessary steps to run binaries on Rocket. See [Section 3.8](#booting) for how to do so. If you are interested in running riscv-linux on Rocket, continue on to Section 3.7: 287 | 288 | ### 3.7) Building/Obtaining riscv-linux 289 | 290 | There are two options to obtain riscv-linux: 291 | 292 | #### Method 1) Build from Source 293 | 294 | Note: If you are working with the Zybo, you should not build `riscv-linux` from source. The Zybo cannot fit an FPU and thus uses a modified version of the kernel that ignores FPU instructions. Software floating point emulation support is planned but not yet available. The binary for this build can be obtained using Method 2 below. 295 | 296 | To build [riscv-linux](http://github.com/ucb-bar/riscv-linux) for Rocket, follow the instructions [here](https://github.com/ucb-bar/riscv-tools#linuxman). Upon completing the linked tutorial, you should have two files: `vmlinux` and `root.bin`. You should place them on your SD card in a directory called `riscv`. 297 | 298 | #### Method 2) Download the Pre-Built Binary and Root FS 299 | 300 | Run the following from within `$REPO/zybo`. 301 | 302 | $ make fetch-riscv-linux-deliver 303 | 304 | Then, copy the `$REPO/zybo/deliver_output/riscv` directory to the root of your SD Card. 305 | 306 | #### Continuing: 307 | 308 | After performing either of these steps, your SD card layout should match the following: 309 | 310 | SD_ROOT/ 311 | |-> riscv/ 312 | |-> root.bin 313 | |-> vmlinux 314 | |-> boot.bin 315 | |-> devicetree.dtb 316 | |-> uImage 317 | |-> uramdisk.image.gz 318 | 319 | 320 | ### 3.8) Booting Up and Interacting with the RISC-V Rocket Core 321 | 322 | First, insert the SD card and follow the instructions in [Appendix A](#connecting) 323 | to connect to your board. You can login to the board with username _root_ and 324 | password _root_. Once you're at the prompt, you can run a basic hello world 325 | program on rocket like so: 326 | 327 | root@zynq:~# ./fesvr-zynq pk hello 328 | hello! 329 | 330 | If you've downloaded the necessary files to boot riscv-linux, you may now do so. 331 | First however, you should mount the SD card using the instructions in [Appendix B](#mountsd). 332 | Then, to boot riscv-linux, run: 333 | 334 | root@zynq:~# ./fesvr-zynq +disk=/sdcard/riscv/root.bin /sdcard/riscv/vmlinux 335 | 336 | Once you hit enter, you'll see the linux boot messages scroll by, and you'll be 337 | presented with a busybox prompt from riscv-linux running on rocket! 338 | 339 | Appendices 340 | ------------ 341 | 342 | ###A) Connecting to the Board 343 | 344 | ####Serial-USB 345 | On the Zybo and Zedboard a single serial-USB cable is needed but on the ZC706 you will also need a USB type A to type B cable (and possibly some drivers). To connect: 346 | 347 | $ screen /dev/tty.usbmodem1411 115200,cs8,-parenb,-cstopb 348 | 349 | _Note:_ The numbers following `tty.usbmodem` may vary slightly. On the Zybo, 350 | replace `usbmodem` with `usbserial-` and on the ZC706, replace it with 351 | `SLAB_USBtoUART`. 352 | 353 | ####Ethernet 354 | The board has an IP of 192.168.1.5 and can be accessed by username/password of root/root on telnet and ssh. For example: 355 | 356 | $ ssh root@192.168.1.5 357 | 358 | _Note:_ Make sure your development system ethernet interface is configured to be on the 192.168.1.x subnet. The default configuration intends for the board to be directly attached to the development system (single cable). If you want to place the board on a larger network, we recommend changing the root password to something stronger and changing the IP configuration to mesh well with your network. 359 | 360 | 361 | ###B) Getting Files On & Off the Board 362 | 363 | ####Copying Files over Ethernet 364 | The easiest way to get a file onto the board is to copy it with scp over ethernet: 365 | 366 | $ scp file root@192.168.1.5:~/ 367 | 368 | _Note:_ Linux is running out of a RAMdisk, so to make a file available after a reboot, copy it to the SD card or modify the RAMdisk. 369 | 370 | #### Mounting the SD Card on the Board 371 | You can mount the SD card on the board by: 372 | 373 | root@zynq:~# mkdir /sdcard 374 | root@zynq:~# mount /dev/mmcblk0p1 /sdcard 375 | 376 | When you are done, don't forget to unmount it: 377 | 378 | root@zynq:~# umount /sdcard 379 | 380 | ####Changing the RAMDisk 381 | _Requires: [u-boot](http://www.denx.de/wiki/U-Boot/) and sudo_ 382 | 383 | The RAMDisk (`uramdisk.image.gz`) that holds Linux for the ARM cores is a gzipped cpio archive with a u-boot header for the board. To open the RAMdisk: 384 | 385 | $ make ramdisk-open 386 | 387 | When changing or adding files, be sure to keep track of owners, groups, and permissions. When you are done, to package it back up: 388 | 389 | $ make ramdisk-close 390 | 391 | A useful application of this is to add your SSH public key to `.ssh/authorized_keys` so you can have passwordless login to the board. 392 | 393 | _Note:_ Since these ramdisk operations use sudo on files, they may not work on a network mounted filesystem. To get around this limitation, it is easiest to just copy it to a local filesystem when modifying the ramdisk. 394 | 395 | 396 | ###C) Working with Vivado 397 | 398 | _Requires: Vivado 2014.4 and its settings64.sh sourced_ 399 | 400 | First, enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). To generate a bitstream, you will need a Vivado project. You should only need to generate it once, but the automation this repo provides makes it easy to generate again if you delete the project. To generate a Vivado project from scratch: 401 | 402 | $ make project 403 | 404 | To generate a bitstream from the command-line: 405 | 406 | $ make bitstream 407 | 408 | To launch Vivado in GUI mode: 409 | 410 | $ make vivado 411 | 412 | 413 | ###D) Changing the Processor's Clockrate 414 | You can change the clockrate for the rocket chip by changing `RC_CLK_MULT` and `RC_CLK_DIVIDE` within a board's `src/verilog/clocking.vh`. After that change, you will need to generate a new bitstream (and `boot.bin`). 415 | 416 | _Note:_ Although rarely needed, it is possible to change the input clockrate to the FPGA by changing it within the block design, `src/constrs/base.xdc`, and `ZYNQ_CLK_PERIOD` within `src/verilog/clocking.vh`. This will also require regenerating `FSBL.elf`, the bitstream, and of course `boot.bin`. 417 | 418 | 419 | ###E) Contents of the SD Card 420 | The SD card is used by the board to configure the FPGA and boot up the ARM core. All of these files are available within a board's fpga-images submodule, but they can also be built from scratch. Here is a summary of the files and their purposes: 421 | 422 | * `boot.bin` is generated by the Xilinx SDK and is actually three files. To generate it from scratch, follow the instructions from Section 3 up through [Section 3.5 Creating boot.bin](#boot.bin). To repack it from existing components, follow [Repacking boot.bin](#repack). `boot.bin` contains: 423 | * Bitstream (`rocketchip_wrapper.bit`) configures the FPGA with the rocket chip design. To build it with the GUI, see [Section 3.2 Generating a Bitstream](#bitstream) and to build it with the command-line, see: [Working with Vivado](#vivado). 424 | * First Stage Bootloader (`FSBL.elf`) - This bootloader configures the Zynq processing system based on the block design in the Vivado project. The FSBL will hand-off to `u-boot` once the processing system is setup. We build the FSBL using the Xilinx SDK and hardware information exported from Vivado. (see [Section 3.3](#fsbl)) 425 | * u-boot (`u-boot.elf`) - This bootloader takes configuration information and prepares the ARM processing system for booting linux. Once configuration is complete, `u-boot` will hand-off execution to the ARM linux kernel. We build `u-boot` directly from the [Xilinx u-boot repository](https://github.com/Xilinx/u-boot-xlnx), with some configuration modifications to support Rocket. (see [Section 3.4](#u-boot)) 426 | * ARM Linux (`uImage`) - This is a copy of linux designed to run on the ARM processing system. From within this linux environment, we will be able to run tools (like `fesvr-zedboard`) to interact with the RISC-V Rocket Core. We build directly from the [Xilinx linux repository](https://github.com/Xilinx/linux-xlnx), with a custom device tree file to support Rocket. (see [Section 3.6](#arm-linux)) 427 | * ARM RAMDisk (`uramdisk.image.gz`) - The RAMDisk is mounted by ARM Linux and contains the root filesystem. For obtaining it, see [Section 3.6](#arm-linux), and for modifying it, see [Appendix B](#transferring). 428 | * `devicetree.dtb` - Contains information about the ARM core's peripherals for Linux. (See [Section 3.6](#arm-linux)) 429 | * `riscv/` (optional) - This directory is only needed if you intend to run Linux on the rocket chip itself. 430 | * RISC-V Linux (`riscv/vmlinux`) - This is the kernel binary for Linux on Rocket. If you are using the zybo, you will need to use a special kernel that ignores floating point instructions, since the zybo cannot fit an FPU. Fetching this version is handled automatically by our scripts. (See [Section 3.7](#riscv-linux)) 431 | * RISC-V RAMDisk (`riscv/root.bin`) - The RAMDisk is mounted by RISC-V Linux and contains the root filesystem. (See [Section 3.7](#riscv-linux)) 432 | 433 | 434 | ###F) Building fesvr-zynq 435 | 436 | The source code for the fesvr-zynq binary is in the [riscv-fesvr repo](http://github.com/ucb-bar/riscv-fesvr). To build the riscv-fesvr binary for Linux ARM target (to run on Zynq board), type: 437 | 438 | $ mkdir build 439 | $ cd build 440 | $ ../configure --host=arm-xilinx-linux-gnueabi 441 | $ make 442 | 443 | from the riscv-fesvr/build directory and make sure you have the Xilinx SDK in your PATH. When installing fesvr-zynq, don't forget to copy the library as well (`build/libfesvr.so` to `/usr/local/lib` on the board). 444 | 445 | 446 | 447 | 448 | Acknowledgments 449 | --------------- 450 | In addition to those that [contributed](https://github.com/ucb-bar/rocket-chip#contributors) to rocket chip, this repository is based on internal repositories contributed by: 451 | 452 | - Rimas Avizienis 453 | - Jonathan Bachrach 454 | - Scott Beamer 455 | - Sagar Karandikar 456 | - Andrew Waterman 457 | -------------------------------------------------------------------------------- /common/Makefrag: -------------------------------------------------------------------------------- 1 | # This makefrag is sourced by each board's subdirectory 2 | 3 | JOBS = 16 4 | base_dir = $(abspath ..) 5 | common = $(base_dir)/common 6 | output_delivery = deliver_output 7 | 8 | ifneq ($(BOARD_MODEL),) 9 | insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board_part" "$(BOARD_MODEL)"/g 10 | endif 11 | 12 | 13 | verilog_srcs = \ 14 | src/verilog/clocking.vh \ 15 | src/verilog/rocketchip_wrapper.v \ 16 | src/verilog/Top.$(CONFIG).v \ 17 | 18 | 19 | default: project 20 | 21 | 22 | 23 | # Specialize sources for board 24 | # ------------------------------------------------------------------------------ 25 | src/verilog/rocketchip_wrapper.v: $(common)/rocketchip_wrapper.v 26 | cp -a $(common)/rocketchip_wrapper.v src/verilog/ 27 | 28 | src/tcl/$(BOARD)_rocketchip.tcl: $(common)/zynq_rocketchip.tcl Makefile 29 | sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/PART_NUMBER_HERE/$(PART)/g;$(insert_board);s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \ 30 | $(common)/zynq_rocketchip.tcl > src/tcl/$(BOARD)_rocketchip.tcl 31 | 32 | src/tcl/make_bitstream.tcl: $(common)/make_bitstream.tcl 33 | sed 's/BOARD_NAME_HERE/$(BOARD)/g' \ 34 | $(common)/make_bitstream.tcl > src/tcl/make_bitstream.tcl 35 | 36 | rocket: 37 | cd $(base_dir)/rocket-chip/fsim; \ 38 | make verilog CONFIG=$(CONFIG); \ 39 | cp -a generated-src/Top.$(CONFIG).v $(base_dir)/$(BOARD)/src/verilog 40 | 41 | 42 | 43 | # Project generation 44 | # ------------------------------------------------------------------------------ 45 | project = $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr 46 | $(project): | src/verilog/rocketchip_wrapper.v src/tcl/$(BOARD)_rocketchip.tcl 47 | vivado -mode tcl -source src/tcl/$(BOARD)_rocketchip.tcl; 48 | project: $(project) 49 | 50 | vivado: $(project) 51 | vivado $(project) & 52 | 53 | bitstream = $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit 54 | $(bitstream): src/tcl/make_bitstream.tcl $(verilog_srcs) src/constrs/base.xdc | $(project) 55 | vivado -mode tcl -source src/tcl/make_bitstream.tcl 56 | bitstream: $(bitstream) 57 | 58 | hwspec = $(BOARD)_rocketchip/$(BOARD)_rocketchip.sdk/rocketchip_wrapper.hdf 59 | $(hwspec): $(bitstream) 60 | -mkdir $(BOARD)_rocketchip/$(BOARD)_rocketchip.sdk 61 | vivado -mode tcl -source src/tcl/export_hardware.tcl 62 | 63 | fsbl = $(BOARD)_rocketchip/$(BOARD)_rocketchip.sdk/FSBL/Debug/FSBL.elf 64 | $(fsbl): $(hwspec) 65 | xsdk -batch -source src/tcl/build_fsbl.tcl 66 | fsbl: $(fsbl) 67 | 68 | # Platform software generation 69 | # ------------------------------------------------------------------------------ 70 | arm_linux_dir = $(base_dir)/common/linux-xlnx 71 | uboot_dir = $(base_dir)/common/u-boot-xlnx 72 | soft_build_dir = soft_build 73 | 74 | arm-linux: arm-uboot # must first build uboot because we need tools 75 | # compile kernel 76 | git submodule update --init $(arm_linux_dir) 77 | # no make clean included here since one copy of linux should work on all boards 78 | cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig 79 | cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS) 80 | # convert zImage to uImage 81 | cd $(arm_linux_dir) && export PATH=$(uboot_dir)/tools:$$PATH && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- UIMAGE_LOADADDR=0x8000 uImage 82 | mkdir -p $(output_delivery) 83 | cp $(arm_linux_dir)/arch/arm/boot/uImage $(output_delivery)/ 84 | 85 | arm-uboot: 86 | # compile board-compatible u-boot 87 | git submodule update --init $(uboot_dir) 88 | # copy relevant configuration files 89 | if [ -a soft_config/boards.cfg ] ; \ 90 | then \ 91 | cp soft_config/boards.cfg $(uboot_dir)/ ; \ 92 | fi; 93 | cp soft_config/zynq_$(UBOOT_CONFIG).h $(uboot_dir)/include/configs/ 94 | # actually build 95 | cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- zynq_$(UBOOT_CONFIG)_config 96 | cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS) 97 | mkdir -p $(soft_build_dir) 98 | cp $(uboot_dir)/u-boot $(soft_build_dir)/u-boot.elf 99 | 100 | arm-dtb: 101 | export PATH=$(arm_linux_dir)/scripts/dtc:$$PATH && dtc -I dts -O dtb -o $(output_delivery)/devicetree.dtb soft_config/$(BOARD)_devicetree.dts 102 | 103 | 104 | 105 | # Handle images and git submodule for prebuilt modules 106 | # ------------------------------------------------------------------------------ 107 | images = fpga-images-$(BOARD)/boot.bif 108 | $(images): 109 | git submodule update --init --depth=1 fpga-images-$(BOARD) 110 | 111 | fetch-images: $(images) 112 | 113 | fpga-images-$(BOARD)/boot.bin: $(images) $(bitstream) 114 | cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin 115 | 116 | load-sd: $(images) 117 | $(base_dir)/common/load_card.sh $(SD) 118 | 119 | ramdisk-open: $(images) 120 | mkdir ramdisk 121 | dd if=fpga-images-$(BOARD)/uramdisk.image.gz bs=64 skip=1 | \ 122 | gunzip -c | sudo sh -c 'cd ramdisk/ && cpio -i' 123 | 124 | ramdisk-close: 125 | @if [ ! -d "ramdisk" ]; then \ 126 | echo "No ramdisk to close (use make ramdisk-open first)"; \ 127 | exit 1; \ 128 | fi 129 | sh -c 'cd ramdisk/ && sudo find . | sudo cpio -H newc -o' | gzip -9 > uramdisk.cpio.gz 130 | mkimage -A arm -O linux -T ramdisk -d uramdisk.cpio.gz fpga-images-$(BOARD)/uramdisk.image.gz 131 | rm uramdisk.cpio.gz 132 | @echo "Don't forget to remove ramdisk before opening it again (sudo rm -rf ramdisk)" 133 | 134 | 135 | # Fetch ramdisk for user building from scratch 136 | # ------------------------------------------------------------------------------ 137 | s3_url = https://s3-us-west-1.amazonaws.com/riscv.org/fpga-zynq-files 138 | ramdisk_url = $(s3_url)/uramdisk.image.gz 139 | fetch-ramdisk: 140 | mkdir -p $(output_delivery) 141 | curl $(ramdisk_url) > $(output_delivery)/uramdisk.image.gz 142 | 143 | 144 | # Rebuild from bif for user building from scratch 145 | # ------------------------------------------------------------------------------ 146 | $(output_delivery)/boot.bin: 147 | cd $(output_delivery); bootgen -image output.bif -w -o boot.bin 148 | 149 | 150 | # Fetch pre-built risc-v linux binary and root fs from S3 151 | # ------------------------------------------------------------------------------ 152 | 153 | riscv_root_bin = $(s3_url)/root.bin 154 | ifeq ($(BOARD), zybo) 155 | riscv_vmlinux = $(s3_url)/vmlinux_nofpu 156 | else 157 | riscv_vmlinux = $(s3_url)/vmlinux 158 | endif 159 | sd_riscv = fpga-images-$(BOARD)/riscv 160 | sd_riscv_scratch = $(output_delivery)/riscv 161 | 162 | fetch-riscv-linux: 163 | mkdir -p $(sd_riscv) 164 | curl $(riscv_root_bin) > $(sd_riscv)/root.bin 165 | curl $(riscv_vmlinux) > $(sd_riscv)/vmlinux 166 | 167 | fetch-riscv-linux-deliver: 168 | mkdir -p $(sd_riscv_scratch) 169 | curl $(riscv_root_bin) > $(sd_riscv_scratch)/root.bin 170 | curl $(riscv_vmlinux) > $(sd_riscv_scratch)/vmlinux 171 | 172 | clean: 173 | rm -f *.log *.jou *.str 174 | 175 | .PHONY: vivado rocket fetch-images load-sd ramdisk-open ramdisk-close clean 176 | -------------------------------------------------------------------------------- /common/load_card.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | if [ -z "$1" ] 4 | then 5 | echo "Please provide a path to a SD card" 6 | exit 1 7 | fi 8 | 9 | fpga_images_dir=`ls -d fpga-images-*` 10 | 11 | set -x 12 | cp $fpga_images_dir/boot.bin $1 13 | cp $fpga_images_dir/devicetree.dtb $1 14 | cp $fpga_images_dir/uImage $1 15 | cp $fpga_images_dir/uramdisk.image.gz $1 16 | # if user downloaded riscv-linux, copy that over also 17 | if [ -a $fpga_images_dir/riscv/vmlinux ] 18 | then 19 | mkdir -p $1/riscv 20 | cp $fpga_images_dir/riscv/vmlinux $1/riscv/ 21 | cp $fpga_images_dir/riscv/root.bin $1/riscv/ 22 | fi 23 | -------------------------------------------------------------------------------- /common/make_bitstream.tcl: -------------------------------------------------------------------------------- 1 | open_project BOARD_NAME_HERE_rocketchip/BOARD_NAME_HERE_rocketchip.xpr 2 | reset_run synth_1 3 | reset_run impl_1 4 | launch_runs synth_1 5 | wait_on_run synth_1 6 | launch_runs impl_1 -to_step write_bitstream 7 | wait_on_run impl_1 8 | exit 9 | -------------------------------------------------------------------------------- /common/rocketchip_wrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | `include "clocking.vh" 3 | 4 | module rocketchip_wrapper 5 | (DDR_addr, 6 | DDR_ba, 7 | DDR_cas_n, 8 | DDR_ck_n, 9 | DDR_ck_p, 10 | DDR_cke, 11 | DDR_cs_n, 12 | DDR_dm, 13 | DDR_dq, 14 | DDR_dqs_n, 15 | DDR_dqs_p, 16 | DDR_odt, 17 | DDR_ras_n, 18 | DDR_reset_n, 19 | DDR_we_n, 20 | FIXED_IO_ddr_vrn, 21 | FIXED_IO_ddr_vrp, 22 | FIXED_IO_mio, 23 | FIXED_IO_ps_clk, 24 | FIXED_IO_ps_porb, 25 | FIXED_IO_ps_srstb, 26 | `ifndef differential_clock 27 | clk); 28 | `else 29 | SYSCLK_P, 30 | SYSCLK_N); 31 | `endif 32 | 33 | inout [14:0]DDR_addr; 34 | inout [2:0]DDR_ba; 35 | inout DDR_cas_n; 36 | inout DDR_ck_n; 37 | inout DDR_ck_p; 38 | inout DDR_cke; 39 | inout DDR_cs_n; 40 | inout [3:0]DDR_dm; 41 | inout [31:0]DDR_dq; 42 | inout [3:0]DDR_dqs_n; 43 | inout [3:0]DDR_dqs_p; 44 | inout DDR_odt; 45 | inout DDR_ras_n; 46 | inout DDR_reset_n; 47 | inout DDR_we_n; 48 | 49 | inout FIXED_IO_ddr_vrn; 50 | inout FIXED_IO_ddr_vrp; 51 | inout [53:0]FIXED_IO_mio; 52 | inout FIXED_IO_ps_clk; 53 | inout FIXED_IO_ps_porb; 54 | inout FIXED_IO_ps_srstb; 55 | 56 | `ifndef differential_clock 57 | input clk; 58 | `else 59 | input SYSCLK_P; 60 | input SYSCLK_N; 61 | `endif 62 | 63 | wire FCLK_RESET0_N; 64 | 65 | wire [31:0]M_AXI_araddr; 66 | wire [1:0]M_AXI_arburst; 67 | wire [7:0]M_AXI_arlen; 68 | wire M_AXI_arready; 69 | wire [2:0]M_AXI_arsize; 70 | wire M_AXI_arvalid; 71 | wire [31:0]M_AXI_awaddr; 72 | wire [1:0]M_AXI_awburst; 73 | wire [7:0]M_AXI_awlen; 74 | wire [3:0]M_AXI_wstrb; 75 | wire M_AXI_awready; 76 | wire [2:0]M_AXI_awsize; 77 | wire M_AXI_awvalid; 78 | wire M_AXI_bready; 79 | wire M_AXI_bvalid; 80 | wire [31:0]M_AXI_rdata; 81 | wire M_AXI_rlast; 82 | wire M_AXI_rready; 83 | wire M_AXI_rvalid; 84 | wire [31:0]M_AXI_wdata; 85 | wire M_AXI_wlast; 86 | wire M_AXI_wready; 87 | wire M_AXI_wvalid; 88 | wire [11:0] M_AXI_arid, M_AXI_awid; // outputs from ARM core 89 | wire [11:0] M_AXI_bid, M_AXI_rid; // inputs to ARM core 90 | 91 | wire [4:0] raddr, waddr; 92 | reg [4:0] raddr_r, waddr_r; 93 | reg [11:0] arid_r, awid_r; 94 | reg [15:0] host_out_bits_r; 95 | 96 | wire host_in_fifo_full, host_in_fifo_empty, host_in_fifo_rden, host_in_fifo_wren; 97 | wire host_out_fifo_full, host_out_fifo_empty, host_out_fifo_wren, host_out_fifo_rden; 98 | wire [31:0] host_in_fifo_dout, host_out_fifo_dout; 99 | wire [5:0] host_out_fifo_count; 100 | reg host_out_count, host_in_count; 101 | 102 | wire [31:0]S_AXI_addr; 103 | wire S_AXI_arready; 104 | wire S_AXI_arvalid; 105 | wire S_AXI_awready; 106 | wire S_AXI_awvalid; 107 | wire S_AXI_bready; 108 | wire S_AXI_bvalid; 109 | wire [1:0]S_AXI_bresp; 110 | wire [63:0]S_AXI_rdata; 111 | wire S_AXI_rlast; 112 | reg S_AXI_rlast_r; 113 | wire S_AXI_rready; 114 | wire S_AXI_rvalid; 115 | wire [63:0]S_AXI_wdata; 116 | wire S_AXI_wlast; 117 | wire S_AXI_wready; 118 | wire S_AXI_wvalid; 119 | wire [5:0] S_AXI_arid, S_AXI_awid; // inputs to ARM core 120 | wire [5:0] S_AXI_bid, S_AXI_rid; // outputs from ARM core 121 | 122 | wire mem_req_cmd_val, mem_req_cmd_rdy, mem_req_cmd_rw, mem_req_data_val, mem_req_data_rdy; 123 | wire mem_resp_val,mem_resp_rdy; 124 | wire [4:0] mem_req_tag, mem_resp_tag; 125 | wire [25:0] mem_req_addr; 126 | wire [127:0] mem_req_data_bits; 127 | reg [63:0] mem_resp_data_buf; 128 | 129 | wire reset, reset_cpu; 130 | 131 | wire host_in_valid, host_in_ready, host_out_ready, host_out_valid; 132 | wire [15:0] host_in_bits, host_out_bits; 133 | wire host_clk; 134 | wire gclk_i, gclk_fbout, host_clk_i, mmcm_locked; 135 | 136 | system system_i 137 | (.DDR_addr(DDR_addr), 138 | .DDR_ba(DDR_ba), 139 | .DDR_cas_n(DDR_cas_n), 140 | .DDR_ck_n(DDR_ck_n), 141 | .DDR_ck_p(DDR_ck_p), 142 | .DDR_cke(DDR_cke), 143 | .DDR_cs_n(DDR_cs_n), 144 | .DDR_dm(DDR_dm), 145 | .DDR_dq(DDR_dq), 146 | .DDR_dqs_n(DDR_dqs_n), 147 | .DDR_dqs_p(DDR_dqs_p), 148 | .DDR_odt(DDR_odt), 149 | .DDR_ras_n(DDR_ras_n), 150 | .DDR_reset_n(DDR_reset_n), 151 | .DDR_we_n(DDR_we_n), 152 | .FCLK_RESET0_N(FCLK_RESET0_N), 153 | .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), 154 | .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), 155 | .FIXED_IO_mio(FIXED_IO_mio), 156 | .FIXED_IO_ps_clk(FIXED_IO_ps_clk), 157 | .FIXED_IO_ps_porb(FIXED_IO_ps_porb), 158 | .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), 159 | // master AXI interface (zynq = master, fpga = slave) 160 | .M_AXI_araddr(M_AXI_araddr), 161 | .M_AXI_arburst(M_AXI_arburst), // burst type 162 | .M_AXI_arcache(), 163 | .M_AXI_arid(M_AXI_arid), 164 | .M_AXI_arlen(M_AXI_arlen), // burst length (#transfers) 165 | .M_AXI_arlock(), 166 | .M_AXI_arprot(), 167 | .M_AXI_arqos(), 168 | .M_AXI_arready(M_AXI_arready), 169 | .M_AXI_arregion(), 170 | .M_AXI_arsize(M_AXI_arsize), // burst size (bits/transfer) 171 | .M_AXI_arvalid(M_AXI_arvalid), 172 | // 173 | .M_AXI_awaddr(M_AXI_awaddr), 174 | .M_AXI_awburst(M_AXI_awburst), 175 | .M_AXI_awcache(), 176 | .M_AXI_awid(M_AXI_awid), 177 | .M_AXI_awlen(M_AXI_awlen), 178 | .M_AXI_awlock(), 179 | .M_AXI_awprot(), 180 | .M_AXI_awqos(), 181 | .M_AXI_awready(M_AXI_awready), 182 | .M_AXI_awregion(), 183 | .M_AXI_awsize(M_AXI_awsize), 184 | .M_AXI_awvalid(M_AXI_awvalid), 185 | // 186 | .M_AXI_bid(M_AXI_bid), 187 | .M_AXI_bready(M_AXI_bready), 188 | .M_AXI_bresp(2'b00), 189 | .M_AXI_bvalid(M_AXI_bvalid), 190 | // 191 | .M_AXI_rdata(M_AXI_rdata), 192 | .M_AXI_rid(M_AXI_rid), 193 | .M_AXI_rlast(M_AXI_rlast), 194 | .M_AXI_rready(M_AXI_rready), 195 | .M_AXI_rresp(), 196 | .M_AXI_rvalid(M_AXI_rvalid), 197 | // 198 | .M_AXI_wdata(M_AXI_wdata), 199 | .M_AXI_wlast(M_AXI_wlast), 200 | .M_AXI_wready(M_AXI_wready), 201 | .M_AXI_wstrb(M_AXI_wstrb), 202 | .M_AXI_wvalid(M_AXI_wvalid), 203 | // slave AXI interface (fpga = master, zynq = slave) 204 | // connected directly to DDR controller to handle test chip mem 205 | .S_AXI_araddr(S_AXI_addr), 206 | .S_AXI_arburst(2'b01), // type INCR 207 | .S_AXI_arcache(4'b0011), 208 | .S_AXI_arid(S_AXI_arid), 209 | .S_AXI_arlen(8'd7), // burst length = 8 transfers 210 | .S_AXI_arlock(1'b0), 211 | .S_AXI_arprot(3'b000), 212 | .S_AXI_arqos(4'b0000), 213 | .S_AXI_arready(S_AXI_arready), 214 | .S_AXI_arregion(4'b0000), 215 | .S_AXI_arsize(3'b011), // burst size = 64 bits/beat 216 | .S_AXI_arvalid(S_AXI_arvalid), 217 | // 218 | .S_AXI_awaddr(S_AXI_addr), 219 | .S_AXI_awburst(2'b01), 220 | .S_AXI_awcache(4'b0011), 221 | .S_AXI_awid(S_AXI_awid), 222 | .S_AXI_awlen(8'd7), // burst length = 8 transfers 223 | .S_AXI_awlock(1'b0), 224 | .S_AXI_awprot(3'b000), 225 | .S_AXI_awqos(4'b0000), 226 | .S_AXI_awready(S_AXI_awready), 227 | .S_AXI_awregion(4'b0000), 228 | .S_AXI_awsize(3'b011), 229 | .S_AXI_awvalid(S_AXI_awvalid), 230 | // 231 | .S_AXI_bid(S_AXI_bid), 232 | .S_AXI_bready(S_AXI_bready), 233 | .S_AXI_bresp(), 234 | .S_AXI_bvalid(S_AXI_bvalid), 235 | // 236 | .S_AXI_rid(S_AXI_rid), 237 | .S_AXI_rdata(S_AXI_rdata), 238 | .S_AXI_rlast(S_AXI_rlast), 239 | .S_AXI_rready(S_AXI_rready), 240 | .S_AXI_rresp(), 241 | .S_AXI_rvalid(S_AXI_rvalid), 242 | // 243 | .S_AXI_wdata(S_AXI_wdata), 244 | .S_AXI_wlast(S_AXI_wlast), 245 | .S_AXI_wready(S_AXI_wready), 246 | .S_AXI_wstrb(8'hff), 247 | .S_AXI_wvalid(S_AXI_wvalid), 248 | .ext_clk_in(host_clk) 249 | ); 250 | 251 | `define DCOUNT_ADDR 5'h00 252 | `define RFIFO_ADDR 5'h01 253 | 254 | `define WFIFO_ADDR 5'h00 255 | `define RESET_ADDR 5'h1f 256 | 257 | // HTIF interface between ARM and reference chip on FPGA via memory mapped registers 258 | // 2 read addresses : 1 for FIFO data count (0x0), 1 for FIFO data (0x1) 259 | // 2 write addresses: 1 for FIFO data (0x0), 1 for reset (0x31) 260 | 261 | // host_in (from ARM to fpga) 262 | 263 | assign waddr = M_AXI_awaddr[6:2]; 264 | assign raddr = M_AXI_araddr[6:2]; 265 | 266 | fifo_32x32 host_in_fifo ( 267 | .clk(host_clk), 268 | .reset(reset), 269 | .din(M_AXI_wdata), 270 | .wren(host_in_fifo_wren), 271 | .rden(host_in_fifo_rden), 272 | .dout(host_in_fifo_dout), 273 | .full(host_in_fifo_full), 274 | .empty(host_in_fifo_empty), 275 | .count() 276 | ); 277 | 278 | assign host_in_valid = !host_in_fifo_empty; 279 | assign host_in_fifo_rden = host_in_count && host_in_valid && host_in_ready; 280 | assign host_in_bits = !host_in_count ? host_in_fifo_dout[15:0] : host_in_fifo_dout[31:16]; 281 | 282 | // host_out (from FPGA to ARM) 283 | 284 | assign host_out_ready = !host_out_fifo_full; 285 | assign host_out_fifo_wren = (host_out_count == 1'b1); 286 | assign host_out_fifo_rden = M_AXI_rvalid && M_AXI_rready && (raddr_r == `RFIFO_ADDR); 287 | 288 | fifo_32x32 host_out_fifo ( 289 | .clk(host_clk), 290 | .reset(reset), 291 | .din({host_out_bits, host_out_bits_r}), 292 | .wren(host_out_fifo_wren), 293 | .rden(host_out_fifo_rden), 294 | .dout(host_out_fifo_dout), 295 | .full(host_out_fifo_full), 296 | .empty(host_out_fifo_empty), 297 | .count(host_out_fifo_count) 298 | ); 299 | 300 | assign reset = !FCLK_RESET0_N || !mmcm_locked; 301 | 302 | parameter st_rd_idle = 1'b0; 303 | parameter st_rd_read = 1'b1; 304 | 305 | reg st_rd = st_rd_idle; 306 | 307 | parameter st_wr_idle = 2'd0; 308 | parameter st_wr_write = 2'd1; 309 | parameter st_wr_ack = 2'd2; 310 | 311 | reg [1:0] st_wr = st_wr_idle; 312 | 313 | always @(posedge host_clk) 314 | begin 315 | 316 | if (reset) 317 | begin 318 | host_out_bits_r <= 16'd0; 319 | host_out_count <= 1'd0; 320 | host_in_count <= 1'd0; 321 | raddr_r <= 5'd0; 322 | waddr_r <= 5'd0; 323 | arid_r <= 12'd0; 324 | awid_r <= 12'd0; 325 | st_rd <= st_rd_idle; 326 | st_wr <= st_wr_idle; 327 | end 328 | else 329 | begin 330 | if (host_out_valid) 331 | begin 332 | host_out_bits_r <= host_out_bits; 333 | host_out_count <= host_out_count + 1; 334 | end 335 | if (host_in_valid && host_in_ready) 336 | host_in_count <= host_in_count + 1; 337 | 338 | // state machine to handle reads from AXI master (ARM) 339 | case (st_rd) 340 | st_rd_idle : begin 341 | if (M_AXI_arvalid) 342 | begin 343 | st_rd <= st_rd_read; 344 | raddr_r <= raddr; 345 | arid_r <= M_AXI_arid; 346 | end 347 | end 348 | st_rd_read : begin 349 | if (M_AXI_rready) 350 | st_rd <= st_rd_idle; 351 | end 352 | endcase 353 | 354 | // state machine to handle writes from AXI master 355 | case (st_wr) 356 | st_wr_idle : begin 357 | if (M_AXI_awvalid && M_AXI_wvalid) 358 | begin 359 | st_wr <= st_wr_write; 360 | waddr_r <= waddr; 361 | awid_r <= M_AXI_awid; 362 | end 363 | end 364 | st_wr_write : begin 365 | if (!host_in_fifo_full || (waddr_r == `RESET_ADDR)) 366 | st_wr <= st_wr_ack; 367 | end 368 | st_wr_ack : begin 369 | if (M_AXI_bready) 370 | st_wr <= st_wr_idle; 371 | end 372 | endcase 373 | 374 | end 375 | end 376 | 377 | assign M_AXI_arready = (st_rd == st_rd_idle); 378 | assign M_AXI_rvalid = (st_rd == st_rd_read); 379 | assign M_AXI_rlast = (st_rd == st_rd_read); 380 | assign M_AXI_rdata = (raddr_r == `DCOUNT_ADDR) ? {26'd0, host_out_fifo_count} : host_out_fifo_dout; 381 | assign M_AXI_rid = arid_r; 382 | 383 | wire do_write = (st_wr == st_wr_write); 384 | assign M_AXI_awready = do_write; 385 | assign M_AXI_wready = do_write; 386 | assign host_in_fifo_wren = do_write && (waddr_r == `WFIFO_ADDR); 387 | assign reset_cpu = do_write && (waddr_r == `RESET_ADDR); 388 | 389 | assign M_AXI_bvalid = (st_wr == st_wr_ack); 390 | assign M_AXI_bid = awid_r; 391 | 392 | // interface between test chip mem interface and zynq DDR via HP0 AXI port 393 | parameter st_IDLE = 2'b00; 394 | parameter st_READ = 2'b01; 395 | parameter st_START_WRITE = 2'b10; 396 | parameter st_WRITE = 2'b11; 397 | // parameter st_WRITE_ACK = 3'b100; 398 | 399 | reg [1:0] state_r = st_IDLE; // for poweron global set/reset 400 | reg [2:0] write_count = 3'd0; 401 | reg read_count = 1'b0; 402 | 403 | always @(posedge host_clk) 404 | begin 405 | if (reset) 406 | begin 407 | state_r <= st_IDLE; 408 | write_count <= 3'd0; 409 | read_count <= 1'b0; 410 | mem_resp_data_buf <= 64'd0; 411 | S_AXI_rlast_r <= 1'b0; 412 | end 413 | else 414 | S_AXI_rlast_r <= S_AXI_rlast && S_AXI_rvalid; 415 | if (S_AXI_rvalid) 416 | begin 417 | read_count <= read_count + 1; 418 | mem_resp_data_buf <= S_AXI_rdata; 419 | end 420 | 421 | case (state_r) 422 | st_IDLE : begin 423 | if (mem_req_cmd_val && !mem_req_cmd_rw) 424 | state_r <= st_READ; 425 | else if (mem_req_cmd_val && mem_req_cmd_rw && mem_req_data_val) 426 | state_r <= st_START_WRITE; 427 | end 428 | st_READ : begin 429 | if (S_AXI_arready) 430 | state_r <= st_IDLE; 431 | end 432 | st_START_WRITE : begin 433 | if (S_AXI_awready) 434 | state_r <= st_WRITE; 435 | end 436 | st_WRITE : begin 437 | if (S_AXI_wready && mem_req_data_val) 438 | begin 439 | write_count <= write_count + 1; 440 | if (write_count == 3'd7) 441 | // state_r <= st_WRITE_ACK; 442 | state_r <= st_IDLE; 443 | end 444 | end 445 | // st_WRITE_ACK : begin 446 | // if (S_AXI_bvalid) 447 | // state_r <= st_IDLE; 448 | // end 449 | // default : begin // Fault Recovery 450 | // <= ; 451 | // end 452 | endcase 453 | end 454 | 455 | assign S_AXI_awvalid = (state_r == st_START_WRITE); 456 | assign S_AXI_arvalid = (state_r == st_READ); 457 | assign mem_req_cmd_rdy = ((state_r == st_START_WRITE) && S_AXI_awready) || ((state_r == st_READ) && S_AXI_arready); 458 | assign S_AXI_wvalid = (state_r == st_WRITE) && mem_req_data_val; 459 | assign S_AXI_wlast = (state_r == st_WRITE) && (write_count == 3'd7); 460 | 461 | assign S_AXI_rready = 1'b1; 462 | assign mem_resp_val = read_count; // FIXME: assuming mem_resp_rdy is always 1 (i think its OK) 463 | 464 | assign mem_req_data_rdy = (state_r == st_WRITE) && write_count[0] && S_AXI_wready; 465 | assign S_AXI_addr = {4'h1, mem_req_addr[21:0], 6'd0}; 466 | assign S_AXI_wdata = write_count[0] ? mem_req_data_bits[127:64] : mem_req_data_bits[63:0]; 467 | assign S_AXI_bready = 1'b1; //(state_r == st_WRITE_ACK); 468 | 469 | /* 470 | fifo_8x5 tag_queue ( 471 | .clk(host_clk), 472 | .reset(reset), 473 | .din(mem_req_tag), 474 | .wren(S_AXI_arvalid & S_AXI_arready), 475 | .rden(S_AXI_rlast_r), 476 | .dout(mem_resp_tag), 477 | .full(), 478 | .empty() 479 | ); 480 | */ 481 | 482 | assign S_AXI_arid = {1'b0, mem_req_tag}; 483 | assign S_AXI_awid = 6'd0; 484 | assign mem_resp_tag = S_AXI_rid[4:0]; 485 | 486 | Top top( 487 | .clk(host_clk), 488 | .reset(reset_cpu), 489 | //.io_host_clk( ) 490 | //.io_host_clk_edge( ) 491 | .io_host_in_ready( host_in_ready ), 492 | .io_host_in_valid( host_in_valid ), 493 | .io_host_in_bits( host_in_bits ), 494 | .io_host_out_ready( host_out_ready ), 495 | .io_host_out_valid( host_out_valid ), 496 | .io_host_out_bits( host_out_bits ), 497 | //.io_host_debug_stats_pcr( ) 498 | .io_mem_req_cmd_ready( mem_req_cmd_rdy ), 499 | .io_mem_req_cmd_valid( mem_req_cmd_val ), 500 | .io_mem_req_cmd_bits_addr( mem_req_addr ), 501 | .io_mem_req_cmd_bits_tag( mem_req_tag ), 502 | .io_mem_req_cmd_bits_rw( mem_req_cmd_rw ), 503 | .io_mem_req_data_ready( mem_req_data_rdy ), 504 | .io_mem_req_data_valid( mem_req_data_val ), 505 | .io_mem_req_data_bits_data( mem_req_data_bits ), 506 | .io_mem_resp_ready( mem_resp_rdy ), 507 | .io_mem_resp_valid( mem_resp_val ), 508 | .io_mem_resp_bits_data( {S_AXI_rdata, mem_resp_data_buf} ), 509 | .io_mem_resp_bits_tag( mem_resp_tag ) 510 | ); 511 | `ifndef differential_clock 512 | IBUFG ibufg_gclk (.I(clk), .O(gclk_i)); 513 | `else 514 | IBUFDS #(.DIFF_TERM("TRUE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) clk_ibufds (.O(gclk_i), .I(SYSCLK_P), .IB(SYSCLK_N)); 515 | `endif 516 | BUFG bufg_host_clk (.I(host_clk_i), .O(host_clk)); 517 | 518 | MMCME2_BASE #( 519 | .BANDWIDTH("OPTIMIZED"), 520 | .CLKFBOUT_MULT_F(`RC_CLK_MULT), 521 | .CLKFBOUT_PHASE(0.0), 522 | .CLKIN1_PERIOD(`ZYNQ_CLK_PERIOD), 523 | .CLKOUT1_DIVIDE(1), 524 | .CLKOUT2_DIVIDE(1), 525 | .CLKOUT3_DIVIDE(1), 526 | .CLKOUT4_DIVIDE(1), 527 | .CLKOUT5_DIVIDE(1), 528 | .CLKOUT6_DIVIDE(1), 529 | .CLKOUT0_DIVIDE_F(`RC_CLK_DIVIDE), 530 | .CLKOUT0_DUTY_CYCLE(0.5), 531 | .CLKOUT1_DUTY_CYCLE(0.5), 532 | .CLKOUT2_DUTY_CYCLE(0.5), 533 | .CLKOUT3_DUTY_CYCLE(0.5), 534 | .CLKOUT4_DUTY_CYCLE(0.5), 535 | .CLKOUT5_DUTY_CYCLE(0.5), 536 | .CLKOUT6_DUTY_CYCLE(0.5), 537 | .CLKOUT0_PHASE(0.0), 538 | .CLKOUT1_PHASE(0.0), 539 | .CLKOUT2_PHASE(0.0), 540 | .CLKOUT3_PHASE(0.0), 541 | .CLKOUT4_PHASE(0.0), 542 | .CLKOUT5_PHASE(0.0), 543 | .CLKOUT6_PHASE(0.0), 544 | .CLKOUT4_CASCADE("FALSE"), 545 | .DIVCLK_DIVIDE(1), 546 | .REF_JITTER1(0.0), 547 | .STARTUP_WAIT("FALSE") 548 | ) MMCME2_BASE_inst ( 549 | .CLKOUT0(host_clk_i), 550 | .CLKOUT0B(), 551 | .CLKOUT1(), 552 | .CLKOUT1B(), 553 | .CLKOUT2(), 554 | .CLKOUT2B(), 555 | .CLKOUT3(), 556 | .CLKOUT3B(), 557 | .CLKOUT4(), 558 | .CLKOUT5(), 559 | .CLKOUT6(), 560 | .CLKFBOUT(gclk_fbout), 561 | .CLKFBOUTB(), 562 | .LOCKED(mmcm_locked), 563 | .CLKIN1(gclk_i), 564 | .PWRDWN(1'b0), 565 | .RST(1'b0), 566 | .CLKFBIN(gclk_fbout)); 567 | 568 | endmodule 569 | 570 | 571 | // fifo queues originally from fifos.v 572 | 573 | /* 574 | module fifo_8x5 ( 575 | input clk, 576 | input reset, 577 | input wren, 578 | input rden, 579 | input [4:0] din, 580 | output reg empty, 581 | output reg full, 582 | output [4:0] dout 583 | ); 584 | 585 | reg [4:0] data [0:7]; 586 | reg [2:0] raddr, waddr; 587 | wire [2:0] waddr_next, raddr_next; 588 | wire write = wren && (rden || !full); 589 | wire read = rden && !empty; 590 | 591 | assign waddr_next = write ? waddr + 1'b1 : waddr; 592 | assign raddr_next = read ? raddr + 1'b1 : raddr; 593 | assign dout = data[raddr]; 594 | 595 | always @(posedge clk) 596 | begin 597 | if (reset) 598 | begin 599 | empty <= 1'b1; 600 | full <= 1'b0; 601 | raddr <= 3'd0; 602 | waddr <= 3'd0; 603 | end 604 | else 605 | begin 606 | waddr <= waddr_next; 607 | raddr <= raddr_next; 608 | if (write) 609 | data[waddr] <= din; 610 | 611 | if (read && raddr_next == waddr_next && !full) 612 | empty <= 1'b1; 613 | else if (write && !read) 614 | empty <= 1'b0; 615 | 616 | if (write && raddr_next == waddr_next) 617 | full <= 1'b1; 618 | else if (read && !write) 619 | full <= 1'b0; 620 | 621 | end 622 | end 623 | endmodule 624 | */ 625 | 626 | module fifo_32x32 ( 627 | input clk, 628 | input reset, 629 | input wren, 630 | input rden, 631 | input [31:0] din, 632 | output reg empty, 633 | output reg full, 634 | output [31:0] dout, 635 | output [4:0] count 636 | ); 637 | 638 | reg [31:0] data [0:31]; 639 | reg [4:0] raddr, waddr, cnt; 640 | wire [4:0] waddr_next, raddr_next; 641 | wire write = wren && (rden || !full); 642 | wire read = rden && !empty; 643 | 644 | assign waddr_next = write ? waddr + 1'b1 : waddr; 645 | assign raddr_next = read ? raddr + 1'b1 : raddr; 646 | assign dout = data[raddr]; 647 | assign count = cnt; 648 | 649 | always @(posedge clk) 650 | begin 651 | if (reset) 652 | begin 653 | empty <= 1'b1; 654 | full <= 1'b0; 655 | raddr <= 5'd0; 656 | waddr <= 5'd0; 657 | cnt <= 5'd0; 658 | end 659 | else 660 | begin 661 | waddr <= waddr_next; 662 | raddr <= raddr_next; 663 | if (write) 664 | data[waddr] <= din; 665 | 666 | if (read && raddr_next == waddr_next && !full) 667 | empty <= 1'b1; 668 | else if (write && !read) 669 | empty <= 1'b0; 670 | 671 | if (write && raddr_next == waddr_next) 672 | full <= 1'b1; 673 | else if (read && !write) 674 | full <= 1'b0; 675 | 676 | if (write ^ read) 677 | cnt <= write ? cnt + 1 : cnt - 1; 678 | 679 | end 680 | end 681 | endmodule 682 | -------------------------------------------------------------------------------- /common/zynq_rocketchip.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado (TM) v2014.4 (64-bit) 3 | # 4 | # BOARD_NAME_HERE_rocketchip.tcl: Tcl script for re-creating project 'BOARD_NAME_HERE_rocketchip' 5 | # 6 | # Generated by Vivado on Tue Jan 06 14:00:36 PST 2015 7 | # IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 8 | # 9 | # This file contains the Vivado Tcl commands for re-creating the project to the state* 10 | # when this script was generated. In order to re-create the project, please source this 11 | # file in the Vivado Tcl Shell. 12 | # 13 | # * Note that the runs in the created project will be configured the same way as the 14 | # original project, however they will not be launched automatically. To regenerate the 15 | # run results please launch the synthesis/implementation runs as needed. 16 | 17 | # Set the reference directory for source file relative paths (by default the value is script directory path) 18 | set origin_dir "." 19 | 20 | # Set the directory path for the original project from where this script was exported 21 | set orig_proj_dir "[file normalize "$origin_dir/BOARD_NAME_HERE_rocketchip"]" 22 | 23 | # Create project 24 | create_project BOARD_NAME_HERE_rocketchip $orig_proj_dir 25 | 26 | # Set the directory path for the new project 27 | set proj_dir [get_property directory [current_project]] 28 | 29 | # Set project properties 30 | set obj [get_projects BOARD_NAME_HERE_rocketchip] 31 | set_property "default_lib" "xil_defaultlib" $obj 32 | set_property "part" "PART_NUMBER_HERE" $obj 33 | # REPLACE FOR OFFICIAL BOARD NAME $obj 34 | set_property "simulator_language" "Mixed" $obj 35 | 36 | # Create 'sources_1' fileset (if not found) 37 | if {[string equal [get_filesets -quiet sources_1] ""]} { 38 | create_fileset -srcset sources_1 39 | } 40 | 41 | # Set 'sources_1' fileset object 42 | set obj [get_filesets sources_1] 43 | set files [list \ 44 | "[file normalize "$origin_dir/src/verilog/clocking.vh"]"\ 45 | "[file normalize "$origin_dir/src/verilog/Top.CHISEL_CONFIG_HERE.v"]"\ 46 | "[file normalize "$origin_dir/src/verilog/rocketchip_wrapper.v"]"\ 47 | ] 48 | add_files -norecurse -fileset $obj $files 49 | 50 | # Set 'sources_1' fileset file properties for remote files 51 | # None 52 | 53 | # Set 'sources_1' fileset file properties for local files 54 | # None 55 | 56 | # Set 'sources_1' fileset properties 57 | set obj [get_filesets sources_1] 58 | set_property "top" "rocketchip_wrapper" $obj 59 | 60 | # Create 'constrs_1' fileset (if not found) 61 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 62 | create_fileset -constrset constrs_1 63 | } 64 | 65 | # Set 'constrs_1' fileset object 66 | set obj [get_filesets constrs_1] 67 | 68 | # Add/Import constrs file and set constrs file properties 69 | set file "[file normalize "$origin_dir/src/constrs/base.xdc"]" 70 | set file_added [add_files -norecurse -fileset $obj $file] 71 | set file "$origin_dir/src/constrs/base.xdc" 72 | set file [file normalize $file] 73 | set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] 74 | set_property "file_type" "XDC" $file_obj 75 | 76 | # Set 'constrs_1' fileset properties 77 | set obj [get_filesets constrs_1] 78 | set_property "target_constrs_file" "[file normalize "$origin_dir/src/constrs/base.xdc"]" $obj 79 | 80 | # Create 'sim_1' fileset (if not found) 81 | if {[string equal [get_filesets -quiet sim_1] ""]} { 82 | create_fileset -simset sim_1 83 | } 84 | 85 | # Set 'sim_1' fileset object 86 | set obj [get_filesets sim_1] 87 | # Empty (no sources present) 88 | 89 | # Set 'sim_1' fileset properties 90 | set obj [get_filesets sim_1] 91 | set_property "top" "rocketchip_wrapper" $obj 92 | 93 | # Create 'synth_1' run (if not found) 94 | if {[string equal [get_runs -quiet synth_1] ""]} { 95 | create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 96 | } else { 97 | set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] 98 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 99 | } 100 | set obj [get_runs synth_1] 101 | set_property "needs_refresh" "1" $obj 102 | set_property "part" "PART_NUMBER_HERE" $obj 103 | 104 | # Create 'impl_1' run (if not found) 105 | if {[string equal [get_runs -quiet impl_1] ""]} { 106 | create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 107 | } else { 108 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 109 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 110 | } 111 | set obj [get_runs impl_1] 112 | set_property "needs_refresh" "1" $obj 113 | set_property "part" "PART_NUMBER_HERE" $obj 114 | 115 | puts "INFO: Project created:BOARD_NAME_HERE_rocketchip" 116 | 117 | puts "INFO: Recreating block diagram from src/tcl/BOARD_NAME_HERE_bd.tcl" 118 | source src/tcl/BOARD_NAME_HERE_bd.tcl 119 | 120 | exit 121 | -------------------------------------------------------------------------------- /rocket-chip: -------------------------------------------------------------------------------- 1 | .. -------------------------------------------------------------------------------- /zedboard/Makefile: -------------------------------------------------------------------------------- 1 | BOARD = zedboard 2 | UBOOT_CONFIG = zed 3 | BOARD_MODEL = em.avnet.com:zed:part0:1.0 4 | PART = xc7z020clg484-1 5 | # CONFIG is the target configuration for the rocket-chip generator 6 | CONFIG ?= DefaultFPGAConfig 7 | #CONFIG ?= FPGAMsiL2 8 | 9 | include ../common/Makefrag 10 | -------------------------------------------------------------------------------- /zedboard/build_image.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | #----------------------- 4 | # A script to rebuild all components for the FPGA image 5 | #----------------------- 6 | 7 | orig_path=$PWD 8 | 9 | #### Check paths and available tools 10 | 11 | echo "Checking for environment variables..." 12 | 13 | # check $TOP 14 | if [ "$TOP" == "" ]; then 15 | echo "Error: Please set variable \$TOP to the lowrisc-chip directory and run again." 16 | exit 1 17 | fi 18 | 19 | # Check $RISCV is set 20 | if [ "$RISCV" == "" ]; then 21 | echo "Error: Please set up the RISCV environment variables and run again." 22 | echo "An example riscv environment setup script is provided as \$TOP/set_riscv_env.sh" 23 | exit 1 24 | fi 25 | 26 | # check for Xilinx vivado 27 | vivado_path=`which vivado` 28 | if [ "$vivado_path" == "" ]; then 29 | echo "Error: Please set up the Xilinx environment variables and run again." 30 | echo "(For 64-bit Ubuntu) Normally you can do this by sourcing /Xilinx/Install/Dir/Vivado/2014.4/settings64.sh" 31 | exit 1 32 | fi 33 | 34 | # check for vivado version 35 | vivado_version=`vivado -version` 36 | if [[ "$vivado_version" != *v2014.4* ]]; then 37 | echo "Warning: You are using a Xilinx Vivado other than 2014.4. There may be problem in generating FPGA bitstreams." 38 | fi 39 | 40 | # prepare log files 41 | echo "git submodule log file" > $TOP/fpga-zynq/zedboard/build_image_submodule.log 42 | echo "riscv64-unknown-elf toolchain log file" > $TOP/fpga-zynq/zedboard/build_image_riscv64_unknown_elf.log 43 | echo "riscv-linux toolchain log file" > $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 44 | echo "Xilinx FPGA log file" > $TOP/fpga-zynq/zedboard/build_image_xilinx.log 45 | echo "RISC-V Linux log file" > $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 46 | echo "ARM Linux log file" > $TOP/fpga-zynq/zedboard/build_image_arm.log 47 | 48 | 49 | echo "Checking for cross-compiling tools..." 50 | 51 | # check for riscv-tools 52 | riscv_elf_gcc=`which riscv64-unknown-elf-gcc` 53 | if [ "$riscv_elf_gcc" == "" ]; then 54 | echo "Compiling the riscv64-unknwon-elf toolchain..." 55 | cd $TOP 56 | git submodule update --init riscv-tools >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 57 | cd riscv-tools 58 | git submodule update --init --recursive >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 59 | ./build.sh >> $TOP/fpga-zynq/zedboard/build_image_riscv64_unknown_elf.log 60 | echo "The riscv64-unknwon-elf toolchain compiled." 61 | fi 62 | 63 | riscv_linux_gcc=`which riscv-linux-gcc` 64 | if [ "$riscv_linux_gcc" == "" ]; then 65 | echo "Compiling the riscv-linux toolchain..." 66 | cd $TOP 67 | git submodule update --init riscv-tools >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 68 | cd riscv-tools 69 | if [ ! -e riscv-gcc ]; then 70 | git clone https://github.com/lowrisc/riscv-gcc.git >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 71 | fi 72 | cd riscv-gcc 73 | if [ ! -e build ]; then mkdir build; fi 74 | cd build 75 | make clean 76 | ../configure --prefix=$RISCV >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 77 | make -j linux >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 78 | echo "The riscv-linux toolchain compiled." 79 | fi 80 | 81 | #### Build the bitstream 82 | 83 | echo "Build the boot.bin..." 84 | 85 | cd $TOP 86 | git submodule update --init rocket uncore chisel hardfloat >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 87 | cd $TOP/fpga-zynq/zedboard 88 | git submodule update --init --recursive >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 89 | 90 | echo "Step 1: Build the FPGA bitstream..." 91 | 92 | make rocket >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 93 | make bitstream >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 94 | 95 | #### Build the FSBL 96 | 97 | echo "Step 2: Build the FSBL..." 98 | 99 | make fsbl >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 100 | 101 | #### Build the ARM u-boot 102 | 103 | echo "Step 3: Build the ARM u-boot..." 104 | 105 | make arm-uboot >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 106 | cp soft_build/u-boot.elf fpga-images-zedboard/boot_image/ 107 | 108 | #### Build the boot.bin 109 | 110 | echo "Finally: Generate the boot.bin..." 111 | 112 | rm fpga-images-zedboard/boot.bin 113 | make fpga-images-zedboard/boot.bin 114 | 115 | #### Build the fesvr-zynq 116 | 117 | echo "Build fesvr-zynq..." 118 | 119 | cd $TOP/riscv-tools/riscv-fesvr 120 | if [ ! -d build_fpga ]; then 121 | mkdir build_fpga 122 | fi 123 | cd build_fpga 124 | ../configure --host=arm-xilinx-linux-gnueabi >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 125 | make -j >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 126 | 127 | #### Build proxy kernel (pk) 128 | 129 | echo "Build proxy kernel (pk)..." 130 | 131 | cd $TOP/riscv-tools/riscv-pk 132 | if [ ! -d build ]; then 133 | mkdir build 134 | cd build 135 | ../configure --prefix=$RISCV/riscv64-unknown-elf --host=riscv64-unknown-elf >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 136 | fi 137 | cd $TOP/riscv-tools/riscv-pk/build 138 | make -j >> $TOP/fpga-zynq/zedboard/build_image_xilinx.log 139 | 140 | #### prepare the ARM ramdisk 141 | 142 | echo "Prepare the ARM RAMDisk..." 143 | echo "[Note] Root password is needed." 144 | 145 | cd $TOP/fpga-zynq/zedboard 146 | make ramdisk-open 147 | sudo cp $TOP/riscv-tools/riscv-fesvr/build_fpga/fesvr-zedboard ramdisk/home/root/fesvr-zynq 148 | sudo cp $TOP/riscv-tools/riscv-fesvr/build_fpga/libfesvr.so ramdisk/usr/local/lib/libfesvr.so 149 | sudo cp $TOP/riscv-tools/riscv-pk/build/pk ramdisk/home/root/pk 150 | make ramdisk-close 151 | sudo \rm -fr ramdisk 152 | 153 | #### Build the ARM Linux kernel 154 | 155 | echo "Build the ARM Linux kernel..." 156 | make arm-linux >> $TOP/fpga-zynq/zedboard/build_image_arm.log 157 | cp deliver_output/uImage fpga-images-zedboard/uImage 158 | 159 | echo "Generate Zynq ARM device map..." 160 | make arm-dtb >> $TOP/fpga-zynq/zedboard/build_image_arm.log 161 | cp deliver_output/devicetree.dtb fpga-images-zedboard/devicetree.dtb 162 | 163 | #### Build the RISC-V Linux Kernel 164 | 165 | echo "Build the RISC-V Linux Kernel..." 166 | cd $TOP/riscv-tools 167 | if [ ! -d linux-3.14.13 ]; then 168 | curl https://www.kernel.org/pub/linux/kernel/v3.x/linux-3.14.13.tar.xz | tar -xJ 169 | cd linux-3.14.13 170 | git init >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 171 | git remote add origin https://github.com/riscv/riscv-linux.git >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 172 | git fetch >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 173 | # currently we use an old version of riscv-linux 174 | git checkout -f 989153f >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 175 | fi 176 | cd $TOP/riscv-tools/linux-3.14.13 177 | make ARCH=riscv defconfig >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 178 | make ARCH=riscv -j vmlinux >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 179 | cp vmlinux $TOP/fpga-zynq/zedboard/fpga-images-zedboard/riscv/vmlinux 180 | 181 | #### Build the Busybox init 182 | 183 | echo "Build the Busybox init tools and the RISC-V RAMDisk..." 184 | 185 | cd $TOP/riscv-tools 186 | if [ ! -d busybox-1.21.1 ]; then 187 | curl -L http://busybox.net/downloads/busybox-1.21.1.tar.bz2 | tar -xj 188 | fi 189 | cd busybox-1.21.1 190 | if [ ! -d .config ]; then 191 | cp $TOP/riscv-tools/busybox_config .config 192 | fi 193 | make -j >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 194 | 195 | $TOP/riscv-tools/make_root.sh 196 | #cp root.bin $TOP/fpga-zynq/zedboard/fpga-images-zedboard/riscv/root.bin 197 | 198 | #### Build the Tag Linux tests can copy them to the root.bin 199 | cd $TOP/riscv-tools 200 | git submodule update --init lowrisc-tag-tests >> $TOP/fpga-zynq/zedboard/build_image_submodule.log 201 | cd lowrisc-tag-tests/tests 202 | make linux >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 203 | cd $TOP/riscv-tools/hello 204 | make >> $TOP/fpga-zynq/zedboard/build_image_riscv_linux.log 205 | cd $TOP/riscv-tools/busybox-1.21.1 206 | sudo mount -o loop root.bin mnt 207 | sudo mkdir mnt/test 208 | sudo cp ../lowrisc-tag-tests/tests/tag_ld_st.linux mnt/test/ 209 | sudo cp ../lowrisc-tag-tests/tests/parity.linux mnt/test/ 210 | sudo cp ../hello/hello.linux mnt/test/ 211 | sudo umount mnt 212 | cp root.bin $TOP/fpga-zynq/zedboard/fpga-images-zedboard/riscv/root.bin 213 | 214 | #### Finished 215 | echo "" 216 | echo "--------------------------------------------------------------------------------" 217 | echo "The following files have been build in fpga-images-zedboard:" 218 | echo " boot.bin boot_image/system.bit boot_image/u-boot.elf boot_image/zynq_fsbl.elf" 219 | echo " devicetree riscv/vmlinux riscv/root.bin uImage uramdisk.image.gz" 220 | 221 | cd $orig_path 222 | -------------------------------------------------------------------------------- /zedboard/soft_config/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /zedboard/soft_config/zedboard_devicetree.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 - 2014 Xilinx 3 | * Copyright (C) 2012 National Instruments Corp. 4 | * 5 | * This software is licensed under the terms of the GNU General Public 6 | * License version 2, as published by the Free Software Foundation, and 7 | * may be copied, distributed, and modified under those terms. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | */ 14 | /dts-v1/; 15 | /include/ "zynq-7000.dtsi" 16 | 17 | / { 18 | model = "Zynq Zed Development Board"; 19 | compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; 20 | 21 | aliases { 22 | ethernet0 = &gem0; 23 | serial0 = &uart1; 24 | spi0 = &qspi; 25 | }; 26 | 27 | memory { 28 | device_type = "memory"; 29 | reg = <0x0 0x10000000>; 30 | }; 31 | 32 | htif_0: htif@43c00000 { 33 | #address-cells = <1>; 34 | #size-cells = <1>; 35 | compatible = "generic-uio", "uio", "uio_pdrv"; 36 | reg = <0x43c00000 0x1000>; 37 | }; 38 | 39 | chosen { 40 | bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; 41 | linux,stdout-path = "/amba/serial@e0001000"; 42 | }; 43 | }; 44 | 45 | &qspi { 46 | status = "okay"; 47 | is-dual = <0>; 48 | num-cs = <1>; 49 | xlnx,fb-clk = <0x1>; 50 | xlnx,qspi-mode = <0x0>; 51 | flash@0 { 52 | compatible = "n25q128"; 53 | reg = <0x0>; 54 | spi-tx-bus-width = <1>; 55 | spi-rx-bus-width = <4>; 56 | spi-max-frequency = <50000000>; 57 | #address-cells = <1>; 58 | #size-cells = <1>; 59 | partition@qspi-fsbl-uboot { 60 | label = "qspi-fsbl-uboot"; 61 | reg = <0x0 0x100000>; 62 | }; 63 | partition@qspi-linux { 64 | label = "qspi-linux"; 65 | reg = <0x100000 0x500000>; 66 | }; 67 | partition@qspi-device-tree { 68 | label = "qspi-device-tree"; 69 | reg = <0x600000 0x20000>; 70 | }; 71 | partition@qspi-rootfs { 72 | label = "qspi-rootfs"; 73 | reg = <0x620000 0x5E0000>; 74 | }; 75 | partition@qspi-bitstream { 76 | label = "qspi-bitstream"; 77 | reg = <0xC00000 0x400000>; 78 | }; 79 | }; 80 | }; 81 | 82 | &usb0 { 83 | status = "okay"; 84 | dr_mode = "host"; 85 | phy_type = "ulpi"; 86 | }; 87 | 88 | &gem0 { 89 | status = "okay"; 90 | phy-mode = "rgmii-id"; 91 | 92 | phy0: phy@0 { 93 | reg = <0>; 94 | }; 95 | }; 96 | 97 | &sdhci0 { 98 | status = "okay"; 99 | }; 100 | 101 | &uart1 { 102 | status = "okay"; 103 | }; 104 | -------------------------------------------------------------------------------- /zedboard/soft_config/zynq-7000.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 - 2014 Xilinx 3 | * 4 | * This software is licensed under the terms of the GNU General Public 5 | * License version 2, as published by the Free Software Foundation, and 6 | * may be copied, distributed, and modified under those terms. 7 | * 8 | * This program is distributed in the hope that it will be useful, 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | * GNU General Public License for more details. 12 | */ 13 | /include/ "skeleton.dtsi" 14 | 15 | / { 16 | compatible = "xlnx,zynq-7000"; 17 | 18 | cpus { 19 | #address-cells = <1>; 20 | #size-cells = <0>; 21 | 22 | cpu@0 { 23 | compatible = "arm,cortex-a9"; 24 | device_type = "cpu"; 25 | reg = <0>; 26 | clocks = <&clkc 3>; 27 | clock-latency = <1000>; 28 | cpu0-supply = <®ulator_vccpint>; 29 | operating-points = < 30 | /* kHz uV */ 31 | 666667 1000000 32 | 333334 1000000 33 | 222223 1000000 34 | >; 35 | }; 36 | 37 | cpu@1 { 38 | compatible = "arm,cortex-a9"; 39 | device_type = "cpu"; 40 | reg = <1>; 41 | clocks = <&clkc 3>; 42 | }; 43 | }; 44 | 45 | pmu { 46 | compatible = "arm,cortex-a9-pmu"; 47 | interrupts = <0 5 4>, <0 6 4>; 48 | interrupt-parent = <&intc>; 49 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; 50 | }; 51 | 52 | regulator_vccpint: fixedregulator@0 { 53 | compatible = "regulator-fixed"; 54 | regulator-name = "VCCPINT"; 55 | regulator-min-microvolt = <1000000>; 56 | regulator-max-microvolt = <1000000>; 57 | regulator-boot-on; 58 | regulator-always-on; 59 | }; 60 | 61 | amba { 62 | compatible = "simple-bus"; 63 | #address-cells = <1>; 64 | #size-cells = <1>; 65 | interrupt-parent = <&intc>; 66 | ranges; 67 | 68 | adc@f8007100 { 69 | compatible = "xlnx,zynq-xadc-1.00.a"; 70 | reg = <0xf8007100 0x20>; 71 | interrupts = <0 7 4>; 72 | interrupt-parent = <&intc>; 73 | clocks = <&clkc 12>; 74 | }; 75 | 76 | can0: can@e0008000 { 77 | compatible = "xlnx,zynq-can-1.0"; 78 | status = "disabled"; 79 | clocks = <&clkc 19>, <&clkc 36>; 80 | clock-names = "ref_clk", "aper_clk"; 81 | reg = <0xe0008000 0x1000>; 82 | interrupts = <0 28 4>; 83 | interrupt-parent = <&intc>; 84 | }; 85 | 86 | can1: can@e0009000 { 87 | compatible = "xlnx,zynq-can-1.0"; 88 | status = "disabled"; 89 | clocks = <&clkc 20>, <&clkc 37>; 90 | clock-names = "ref_clk", "aper_clk"; 91 | reg = <0xe0009000 0x1000>; 92 | interrupts = <0 51 4>; 93 | interrupt-parent = <&intc>; 94 | }; 95 | 96 | gpio0: gpio@e000a000 { 97 | compatible = "xlnx,zynq-gpio-1.0"; 98 | #gpio-cells = <2>; 99 | clocks = <&clkc 42>; 100 | gpio-controller; 101 | interrupt-parent = <&intc>; 102 | interrupts = <0 20 4>; 103 | reg = <0xe000a000 0x1000>; 104 | }; 105 | 106 | i2c0: i2c@e0004000 { 107 | compatible = "cdns,i2c-r1p10"; 108 | status = "disabled"; 109 | clocks = <&clkc 38>; 110 | interrupt-parent = <&intc>; 111 | interrupts = <0 25 4>; 112 | reg = <0xe0004000 0x1000>; 113 | #address-cells = <1>; 114 | #size-cells = <0>; 115 | }; 116 | 117 | i2c1: i2c@e0005000 { 118 | compatible = "cdns,i2c-r1p10"; 119 | status = "disabled"; 120 | clocks = <&clkc 39>; 121 | interrupt-parent = <&intc>; 122 | interrupts = <0 48 4>; 123 | reg = <0xe0005000 0x1000>; 124 | #address-cells = <1>; 125 | #size-cells = <0>; 126 | }; 127 | 128 | intc: interrupt-controller@f8f01000 { 129 | compatible = "arm,cortex-a9-gic"; 130 | #interrupt-cells = <3>; 131 | interrupt-controller; 132 | reg = <0xF8F01000 0x1000>, 133 | <0xF8F00100 0x100>; 134 | }; 135 | 136 | L2: cache-controller { 137 | compatible = "arm,pl310-cache"; 138 | reg = <0xF8F02000 0x1000>; 139 | arm,data-latency = <3 2 2>; 140 | arm,tag-latency = <2 2 2>; 141 | cache-unified; 142 | cache-level = <2>; 143 | }; 144 | 145 | memory-controller@f8006000 { 146 | compatible = "xlnx,zynq-ddrc-1.0"; 147 | reg = <0xf8006000 0x1000>; 148 | xlnx,has-ecc = <0x0>; 149 | }; 150 | 151 | ocmc: ocmc@f800c000 { 152 | compatible = "xlnx,zynq-ocmc-1.0"; 153 | interrupt-parent = <&intc>; 154 | interrupts = <0 3 4>; 155 | reg = <0xf800c000 0x1000>; 156 | }; 157 | 158 | uart0: serial@e0000000 { 159 | compatible = "xlnx,xuartps"; 160 | status = "disabled"; 161 | clocks = <&clkc 23>, <&clkc 40>; 162 | clock-names = "ref_clk", "aper_clk"; 163 | reg = <0xE0000000 0x1000>; 164 | interrupts = <0 27 4>; 165 | }; 166 | 167 | uart1: serial@e0001000 { 168 | compatible = "xlnx,xuartps"; 169 | status = "disabled"; 170 | clocks = <&clkc 24>, <&clkc 41>; 171 | clock-names = "ref_clk", "aper_clk"; 172 | reg = <0xE0001000 0x1000>; 173 | interrupts = <0 50 4>; 174 | }; 175 | 176 | spi0: spi@e0006000 { 177 | compatible = "xlnx,zynq-spi-r1p6"; 178 | reg = <0xe0006000 0x1000>; 179 | status = "disabled"; 180 | interrupt-parent = <&intc>; 181 | interrupts = <0 26 4>; 182 | clocks = <&clkc 25>, <&clkc 34>; 183 | clock-names = "ref_clk", "pclk"; 184 | #address-cells = <1>; 185 | #size-cells = <0>; 186 | }; 187 | 188 | spi1: spi@e0007000 { 189 | compatible = "xlnx,zynq-spi-r1p6"; 190 | reg = <0xe0007000 0x1000>; 191 | status = "disabled"; 192 | interrupt-parent = <&intc>; 193 | interrupts = <0 49 4>; 194 | clocks = <&clkc 26>, <&clkc 35>; 195 | clock-names = "ref_clk", "pclk"; 196 | #address-cells = <1>; 197 | #size-cells = <0>; 198 | }; 199 | 200 | qspi: spi@e000d000 { 201 | clock-names = "ref_clk", "pclk"; 202 | clocks = <&clkc 10>, <&clkc 43>; 203 | compatible = "xlnx,zynq-qspi-1.0"; 204 | status = "disabled"; 205 | interrupt-parent = <&intc>; 206 | interrupts = <0 19 4>; 207 | reg = <0xe000d000 0x1000>; 208 | #address-cells = <1>; 209 | #size-cells = <0>; 210 | }; 211 | 212 | smcc: memory-controller@e000e000 { 213 | #address-cells = <1>; 214 | #size-cells = <1>; 215 | status = "disabled"; 216 | clock-names = "memclk", "aclk"; 217 | clocks = <&clkc 11>, <&clkc 44>; 218 | compatible = "arm,pl353-smc-r2p1"; 219 | interrupt-parent = <&intc>; 220 | interrupts = <0 18 4>; 221 | ranges ; 222 | reg = <0xe000e000 0x1000>; 223 | nand0: flash@e1000000 { 224 | status = "disabled"; 225 | compatible = "arm,pl353-nand-r2p1"; 226 | reg = <0xe1000000 0x1000000>; 227 | #address-cells = <0x1>; 228 | #size-cells = <0x1>; 229 | }; 230 | nor0: flash@e2000000 { 231 | status = "disabled"; 232 | compatible = "cfi-flash"; 233 | reg = <0xe2000000 0x1000>; 234 | #address-cells = <1>; 235 | #size-cells = <1>; 236 | }; 237 | }; 238 | 239 | gem0: ethernet@e000b000 { 240 | compatible = "cdns,gem"; 241 | reg = <0xe000b000 0x4000>; 242 | status = "disabled"; 243 | interrupts = <0 22 4>; 244 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 245 | clock-names = "pclk", "hclk", "tx_clk"; 246 | #address-cells = <1>; 247 | #size-cells = <0>; 248 | }; 249 | 250 | gem1: ethernet@e000c000 { 251 | compatible = "cdns,gem"; 252 | reg = <0xe000c000 0x4000>; 253 | status = "disabled"; 254 | interrupts = <0 45 4>; 255 | clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 256 | clock-names = "pclk", "hclk", "tx_clk"; 257 | #address-cells = <1>; 258 | #size-cells = <0>; 259 | }; 260 | 261 | sdhci0: sdhci@e0100000 { 262 | compatible = "arasan,sdhci-8.9a"; 263 | status = "disabled"; 264 | clock-names = "clk_xin", "clk_ahb"; 265 | clocks = <&clkc 21>, <&clkc 32>; 266 | interrupt-parent = <&intc>; 267 | interrupts = <0 24 4>; 268 | reg = <0xe0100000 0x1000>; 269 | }; 270 | 271 | sdhci1: sdhci@e0101000 { 272 | compatible = "arasan,sdhci-8.9a"; 273 | status = "disabled"; 274 | clock-names = "clk_xin", "clk_ahb"; 275 | clocks = <&clkc 22>, <&clkc 33>; 276 | interrupt-parent = <&intc>; 277 | interrupts = <0 47 4>; 278 | reg = <0xe0101000 0x1000>; 279 | }; 280 | 281 | slcr: slcr@f8000000 { 282 | #address-cells = <1>; 283 | #size-cells = <1>; 284 | compatible = "xlnx,zynq-slcr", "syscon"; 285 | reg = <0xF8000000 0x1000>; 286 | ranges; 287 | clkc: clkc@100 { 288 | #clock-cells = <1>; 289 | compatible = "xlnx,ps7-clkc"; 290 | ps-clk-frequency = <33333333>; 291 | fclk-enable = <0>; 292 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 293 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 294 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 295 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 296 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 297 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", 298 | "gem1_aper", "sdio0_aper", "sdio1_aper", 299 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 300 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 301 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 302 | "dbg_trc", "dbg_apb"; 303 | reg = <0x100 0x100>; 304 | }; 305 | }; 306 | 307 | dmac_s: dmac@f8003000 { 308 | compatible = "arm,pl330", "arm,primecell"; 309 | reg = <0xf8003000 0x1000>; 310 | interrupt-parent = <&intc>; 311 | interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 312 | "dma4", "dma5", "dma6", "dma7"; 313 | interrupts = <0 13 4>, 314 | <0 14 4>, <0 15 4>, 315 | <0 16 4>, <0 17 4>, 316 | <0 40 4>, <0 41 4>, 317 | <0 42 4>, <0 43 4>; 318 | #dma-cells = <1>; 319 | #dma-channels = <8>; 320 | #dma-requests = <4>; 321 | clocks = <&clkc 27>; 322 | clock-names = "apb_pclk"; 323 | }; 324 | 325 | devcfg: devcfg@f8007000 { 326 | clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 327 | clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 328 | compatible = "xlnx,zynq-devcfg-1.0"; 329 | interrupt-parent = <&intc>; 330 | interrupts = <0 8 4>; 331 | reg = <0xf8007000 0x100>; 332 | }; 333 | 334 | global_timer: timer@f8f00200 { 335 | compatible = "arm,cortex-a9-global-timer"; 336 | reg = <0xf8f00200 0x20>; 337 | interrupts = <1 11 0x301>; 338 | interrupt-parent = <&intc>; 339 | clocks = <&clkc 4>; 340 | }; 341 | 342 | ttc0: timer@f8001000 { 343 | interrupt-parent = <&intc>; 344 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 345 | compatible = "cdns,ttc"; 346 | clocks = <&clkc 6>; 347 | reg = <0xF8001000 0x1000>; 348 | }; 349 | 350 | ttc1: timer@f8002000 { 351 | interrupt-parent = <&intc>; 352 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 353 | compatible = "cdns,ttc"; 354 | clocks = <&clkc 6>; 355 | reg = <0xF8002000 0x1000>; 356 | }; 357 | 358 | scutimer: timer@f8f00600 { 359 | interrupt-parent = <&intc>; 360 | interrupts = <1 13 0x301>; 361 | compatible = "arm,cortex-a9-twd-timer"; 362 | reg = <0xf8f00600 0x20>; 363 | clocks = <&clkc 4>; 364 | }; 365 | 366 | watchdog0: watchdog@f8005000 { 367 | clocks = <&clkc 45>; 368 | compatible = "xlnx,zynq-wdt-r1p2"; 369 | device_type = "watchdog"; 370 | interrupt-parent = <&intc>; 371 | interrupts = <0 9 1>; 372 | reg = <0xf8005000 0x1000>; 373 | reset = <0>; 374 | timeout-sec = <10>; 375 | }; 376 | 377 | scuwatchdog: watchdog@f8f00620 { 378 | clocks = <&clkc 4>; 379 | compatible = "xlnx,ps7-scuwdt-1.00.a"; 380 | device_type = "watchdog"; 381 | interrupt-parent = <&intc>; 382 | interrupts = <1 14 0x301>; 383 | reg = <0xf8f00620 0xe0>; 384 | }; 385 | 386 | usb0: usb@e0002000 { 387 | clocks = <&clkc 28>; 388 | compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; 389 | status = "disabled"; 390 | interrupt-parent = <&intc>; 391 | interrupts = <0 21 4>; 392 | reg = <0xe0002000 0x1000>; 393 | }; 394 | 395 | usb1: usb@e0003000 { 396 | clocks = <&clkc 29>; 397 | compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; 398 | status = "disabled"; 399 | interrupt-parent = <&intc>; 400 | interrupts = <0 44 4>; 401 | reg = <0xe0003000 0x1000>; 402 | }; 403 | }; 404 | }; 405 | -------------------------------------------------------------------------------- /zedboard/soft_config/zynq_zed.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Xilinx, Inc. 3 | * 4 | * Configuration for Zynq Evaluation and Development Board - ZedBoard 5 | * See zynq-common.h for Zynq common configs 6 | * 7 | * SPDX-License-Identifier: GPL-2.0+ 8 | */ 9 | 10 | #ifndef __CONFIG_ZYNQ_ZED_H 11 | #define __CONFIG_ZYNQ_ZED_H 12 | 13 | #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 14 | 15 | #define CONFIG_ZYNQ_SERIAL_UART1 16 | #define CONFIG_ZYNQ_GEM0 17 | #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 18 | 19 | #define CONFIG_SYS_NO_FLASH 20 | 21 | #define CONFIG_ZYNQ_USB 22 | #define CONFIG_ZYNQ_SDHCI0 23 | #define CONFIG_ZYNQ_QSPI 24 | 25 | #define CONFIG_ZYNQ_BOOT_FREEBSD 26 | #define CONFIG_DEFAULT_DEVICE_TREE zynq-zed 27 | 28 | #include 29 | 30 | #endif /* __CONFIG_ZYNQ_ZED_H */ 31 | -------------------------------------------------------------------------------- /zedboard/src/constrs/base.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN Y9 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | create_clock -name gclk_0 -period "10" -waveform {0.0 5.0} [get_ports clk] 4 | -------------------------------------------------------------------------------- /zedboard/src/tcl/build_fsbl.tcl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/tclsh 2 | set_workspace zedboard_rocketchip/zedboard_rocketchip.sdk 3 | create_project -type hw -name rocketchip_wrapper_hw_platform_0 -hwspec zedboard_rocketchip/zedboard_rocketchip.sdk/rocketchip_wrapper.hdf 4 | create_project -type app -name FSBL -hwproject rocketchip_wrapper_hw_platform_0 -proc ps7_cortexa9_0 -os standalone -lang C -app {Zynq FSBL} 5 | build -type all 6 | exit 7 | 8 | -------------------------------------------------------------------------------- /zedboard/src/tcl/export_hardware.tcl: -------------------------------------------------------------------------------- 1 | open_project zedboard_rocketchip/zedboard_rocketchip.xpr 2 | write_hwdef -force -file zedboard_rocketchip/zedboard_rocketchip.sdk/rocketchip_wrapper.hdf 3 | exit 4 | -------------------------------------------------------------------------------- /zedboard/src/tcl/zedboard_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: system 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | ################################################################ 11 | # Check if script is running in correct Vivado version. 12 | ################################################################ 13 | set scripts_vivado_version 2014.4 14 | set current_vivado_version [version -short] 15 | 16 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 17 | puts "" 18 | puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." 19 | 20 | return 1 21 | } 22 | 23 | ################################################################ 24 | # START 25 | ################################################################ 26 | 27 | # To test this script, run the following commands from Vivado Tcl console: 28 | # source system_script.tcl 29 | 30 | # If you do not already have a project created, 31 | # you can create a project using the following command: 32 | # create_project project_1 myproj -part xc7z020clg484-1 33 | # set_property BOARD_PART em.avnet.com:zed:part0:1.0 [current_project] 34 | 35 | 36 | # CHANGE DESIGN NAME HERE 37 | set design_name system 38 | 39 | # If you do not already have an existing IP Integrator design open, 40 | # you can create a design using the following command: 41 | # create_bd_design $design_name 42 | 43 | # CHECKING IF PROJECT EXISTS 44 | if { [get_projects -quiet] eq "" } { 45 | puts "ERROR: Please open or create a project!" 46 | return 1 47 | } 48 | 49 | 50 | # Creating design if needed 51 | set errMsg "" 52 | set nRet 0 53 | 54 | set cur_design [current_bd_design -quiet] 55 | set list_cells [get_bd_cells -quiet] 56 | 57 | if { ${design_name} eq "" } { 58 | # USE CASES: 59 | # 1) Design_name not set 60 | 61 | set errMsg "ERROR: Please set the variable to a non-empty value." 62 | set nRet 1 63 | 64 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 65 | # USE CASES: 66 | # 2): Current design opened AND is empty AND names same. 67 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 68 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 69 | 70 | if { $cur_design ne $design_name } { 71 | puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." 72 | set design_name [get_property NAME $cur_design] 73 | } 74 | puts "INFO: Constructing design in IPI design <$cur_design>..." 75 | 76 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 77 | # USE CASES: 78 | # 5) Current design opened AND has components AND same names. 79 | 80 | set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." 81 | set nRet 1 82 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 83 | # USE CASES: 84 | # 6) Current opened design, has components, but diff names, design_name exists in project. 85 | # 7) No opened design, design_name exists in project. 86 | 87 | set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." 88 | set nRet 2 89 | 90 | } else { 91 | # USE CASES: 92 | # 8) No opened design, design_name not in project. 93 | # 9) Current opened design, has components, but diff names, design_name not in project. 94 | 95 | puts "INFO: Currently there is no design <$design_name> in project, so creating one..." 96 | 97 | create_bd_design $design_name 98 | 99 | puts "INFO: Making design <$design_name> as current_bd_design." 100 | current_bd_design $design_name 101 | 102 | } 103 | 104 | puts "INFO: Currently the variable is equal to \"$design_name\"." 105 | 106 | if { $nRet != 0 } { 107 | puts $errMsg 108 | return $nRet 109 | } 110 | 111 | ################################################################## 112 | # DESIGN PROCs 113 | ################################################################## 114 | 115 | 116 | 117 | # Procedure to create entire design; Provide argument to make 118 | # procedure reusable. If parentCell is "", will use root. 119 | proc create_root_design { parentCell } { 120 | 121 | if { $parentCell eq "" } { 122 | set parentCell [get_bd_cells /] 123 | } 124 | 125 | # Get object for parentCell 126 | set parentObj [get_bd_cells $parentCell] 127 | if { $parentObj == "" } { 128 | puts "ERROR: Unable to find parent cell <$parentCell>!" 129 | return 130 | } 131 | 132 | # Make sure parentObj is hier blk 133 | set parentType [get_property TYPE $parentObj] 134 | if { $parentType ne "hier" } { 135 | puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." 136 | return 137 | } 138 | 139 | # Save current instance; Restore later 140 | set oldCurInst [current_bd_instance .] 141 | 142 | # Set parent object as current 143 | current_bd_instance $parentObj 144 | 145 | 146 | # Create interface ports 147 | set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] 148 | set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] 149 | set M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI ] 150 | set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {25000000} CONFIG.PROTOCOL {AXI4} ] $M_AXI 151 | set S_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI ] 152 | set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.DATA_WIDTH {64} CONFIG.FREQ_HZ {25000000} CONFIG.ID_WIDTH {6} CONFIG.MAX_BURST_LENGTH {16} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S_AXI 153 | 154 | # Create ports 155 | set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] 156 | set ext_clk_in [ create_bd_port -dir I -type clk ext_clk_in ] 157 | set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {M_AXI:S_AXI} CONFIG.FREQ_HZ {25000000} ] $ext_clk_in 158 | 159 | # Create instance: axi_interconnect_0, and set properties 160 | set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] 161 | set_property -dict [ list CONFIG.ENABLE_ADVANCED_OPTIONS {0} CONFIG.NUM_MI {1} ] $axi_interconnect_0 162 | 163 | # Create instance: axi_interconnect_1, and set properties 164 | set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] 165 | set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_interconnect_1 166 | 167 | # Create instance: proc_sys_reset_0, and set properties 168 | set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] 169 | 170 | # Create instance: processing_system7_0, and set properties 171 | set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] 172 | set_property -dict [ list CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ 173 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {142.857132} \ 174 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ 175 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666667} \ 176 | CONFIG.PCW_CLK0_FREQ {100000000} CONFIG.PCW_CLK1_FREQ {142857132} \ 177 | CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {1} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 178 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 179 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} CONFIG.PCW_EN_EMIO_TTC0 {1} \ 180 | CONFIG.PCW_EN_ENET0 {1} CONFIG.PCW_EN_GPIO {1} \ 181 | CONFIG.PCW_EN_QSPI {1} CONFIG.PCW_EN_SDIO0 {1} \ 182 | CONFIG.PCW_EN_TTC0 {1} CONFIG.PCW_EN_UART1 {1} \ 183 | CONFIG.PCW_EN_USB0 {1} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.00000} \ 184 | CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150.000000} CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ 185 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 186 | CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_0_PULLUP {disabled} \ 187 | CONFIG.PCW_MIO_0_SLEW {slow} CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ 188 | CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_10_SLEW {slow} \ 189 | CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_11_PULLUP {disabled} \ 190 | CONFIG.PCW_MIO_11_SLEW {slow} CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ 191 | CONFIG.PCW_MIO_12_PULLUP {disabled} CONFIG.PCW_MIO_12_SLEW {slow} \ 192 | CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_13_PULLUP {disabled} \ 193 | CONFIG.PCW_MIO_13_SLEW {slow} CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ 194 | CONFIG.PCW_MIO_14_PULLUP {disabled} CONFIG.PCW_MIO_14_SLEW {slow} \ 195 | CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_15_PULLUP {disabled} \ 196 | CONFIG.PCW_MIO_15_SLEW {slow} CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ 197 | CONFIG.PCW_MIO_16_PULLUP {disabled} CONFIG.PCW_MIO_16_SLEW {fast} \ 198 | CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_17_PULLUP {disabled} \ 199 | CONFIG.PCW_MIO_17_SLEW {fast} CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ 200 | CONFIG.PCW_MIO_18_PULLUP {disabled} CONFIG.PCW_MIO_18_SLEW {fast} \ 201 | CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_19_PULLUP {disabled} \ 202 | CONFIG.PCW_MIO_19_SLEW {fast} CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ 203 | CONFIG.PCW_MIO_1_PULLUP {disabled} CONFIG.PCW_MIO_1_SLEW {fast} \ 204 | CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_20_PULLUP {disabled} \ 205 | CONFIG.PCW_MIO_20_SLEW {fast} CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ 206 | CONFIG.PCW_MIO_21_PULLUP {disabled} CONFIG.PCW_MIO_21_SLEW {fast} \ 207 | CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_22_PULLUP {disabled} \ 208 | CONFIG.PCW_MIO_22_SLEW {fast} CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ 209 | CONFIG.PCW_MIO_23_PULLUP {disabled} CONFIG.PCW_MIO_23_SLEW {fast} \ 210 | CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_24_PULLUP {disabled} \ 211 | CONFIG.PCW_MIO_24_SLEW {fast} CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ 212 | CONFIG.PCW_MIO_25_PULLUP {disabled} CONFIG.PCW_MIO_25_SLEW {fast} \ 213 | CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_26_PULLUP {disabled} \ 214 | CONFIG.PCW_MIO_26_SLEW {fast} CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ 215 | CONFIG.PCW_MIO_27_PULLUP {disabled} CONFIG.PCW_MIO_27_SLEW {fast} \ 216 | CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_28_PULLUP {disabled} \ 217 | CONFIG.PCW_MIO_28_SLEW {fast} CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ 218 | CONFIG.PCW_MIO_29_PULLUP {disabled} CONFIG.PCW_MIO_29_SLEW {fast} \ 219 | CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_2_SLEW {fast} \ 220 | CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_30_PULLUP {disabled} \ 221 | CONFIG.PCW_MIO_30_SLEW {fast} CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ 222 | CONFIG.PCW_MIO_31_PULLUP {disabled} CONFIG.PCW_MIO_31_SLEW {fast} \ 223 | CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_32_PULLUP {disabled} \ 224 | CONFIG.PCW_MIO_32_SLEW {fast} CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ 225 | CONFIG.PCW_MIO_33_PULLUP {disabled} CONFIG.PCW_MIO_33_SLEW {fast} \ 226 | CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_34_PULLUP {disabled} \ 227 | CONFIG.PCW_MIO_34_SLEW {fast} CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ 228 | CONFIG.PCW_MIO_35_PULLUP {disabled} CONFIG.PCW_MIO_35_SLEW {fast} \ 229 | CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_36_PULLUP {disabled} \ 230 | CONFIG.PCW_MIO_36_SLEW {fast} CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ 231 | CONFIG.PCW_MIO_37_PULLUP {disabled} CONFIG.PCW_MIO_37_SLEW {fast} \ 232 | CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_38_PULLUP {disabled} \ 233 | CONFIG.PCW_MIO_38_SLEW {fast} CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ 234 | CONFIG.PCW_MIO_39_PULLUP {disabled} CONFIG.PCW_MIO_39_SLEW {fast} \ 235 | CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_3_SLEW {fast} \ 236 | CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_40_PULLUP {disabled} \ 237 | CONFIG.PCW_MIO_40_SLEW {fast} CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ 238 | CONFIG.PCW_MIO_41_PULLUP {disabled} CONFIG.PCW_MIO_41_SLEW {fast} \ 239 | CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_42_PULLUP {disabled} \ 240 | CONFIG.PCW_MIO_42_SLEW {fast} CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ 241 | CONFIG.PCW_MIO_43_PULLUP {disabled} CONFIG.PCW_MIO_43_SLEW {fast} \ 242 | CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_44_PULLUP {disabled} \ 243 | CONFIG.PCW_MIO_44_SLEW {fast} CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ 244 | CONFIG.PCW_MIO_45_PULLUP {disabled} CONFIG.PCW_MIO_45_SLEW {fast} \ 245 | CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_46_PULLUP {disabled} \ 246 | CONFIG.PCW_MIO_46_SLEW {slow} CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ 247 | CONFIG.PCW_MIO_47_PULLUP {disabled} CONFIG.PCW_MIO_47_SLEW {slow} \ 248 | CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_48_PULLUP {disabled} \ 249 | CONFIG.PCW_MIO_48_SLEW {slow} CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ 250 | CONFIG.PCW_MIO_49_PULLUP {disabled} CONFIG.PCW_MIO_49_SLEW {slow} \ 251 | CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_4_SLEW {fast} \ 252 | CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_50_PULLUP {disabled} \ 253 | CONFIG.PCW_MIO_50_SLEW {slow} CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ 254 | CONFIG.PCW_MIO_51_PULLUP {disabled} CONFIG.PCW_MIO_51_SLEW {slow} \ 255 | CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_52_PULLUP {disabled} \ 256 | CONFIG.PCW_MIO_52_SLEW {slow} CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ 257 | CONFIG.PCW_MIO_53_PULLUP {disabled} CONFIG.PCW_MIO_53_SLEW {slow} \ 258 | CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_5_SLEW {fast} \ 259 | CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_6_SLEW {fast} \ 260 | CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_7_SLEW {slow} \ 261 | CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_8_SLEW {fast} \ 262 | CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_9_PULLUP {disabled} \ 263 | CONFIG.PCW_MIO_9_SLEW {slow} CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \ 264 | CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#wp#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio} CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {1} \ 265 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ 266 | CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ 267 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ 268 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ 269 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 270 | CONFIG.PCW_SD0_GRP_WP_ENABLE {1} CONFIG.PCW_SD0_GRP_WP_IO {MIO 46} \ 271 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 272 | CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ 273 | CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} CONFIG.PCW_TTC0_TTC0_IO {EMIO} \ 274 | CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ 275 | CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.41} \ 276 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \ 277 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \ 278 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 279 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333313} \ 280 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 281 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 282 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ 283 | CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} CONFIG.PCW_USE_S_AXI_HP0 {1} \ 284 | CONFIG.preset {ZedBoard*} ] $processing_system7_0 285 | 286 | # Create interface connections 287 | connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S_AXI] [get_bd_intf_pins axi_interconnect_1/S00_AXI] 288 | connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] 289 | connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] 290 | connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] 291 | connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] 292 | connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] 293 | 294 | # Create port connections 295 | connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] 296 | connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] 297 | connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] 298 | connect_bd_net -net rocketchip_clk_1 [get_bd_ports ext_clk_in] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 299 | 300 | # Create address segments 301 | create_bd_addr_seg -range 0x1000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI/Reg] SEG_zedboard_rocketchip_Reg 302 | create_bd_addr_seg -range 0x20000000 -offset 0x0 [get_bd_addr_spaces S_AXI] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM 303 | 304 | 305 | # Restore current instance 306 | current_bd_instance $oldCurInst 307 | 308 | save_bd_design 309 | } 310 | # End of create_root_design() 311 | 312 | 313 | ################################################################## 314 | # MAIN FLOW 315 | ################################################################## 316 | 317 | create_root_design "" 318 | 319 | 320 | -------------------------------------------------------------------------------- /zedboard/src/verilog/clocking.vh: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Rocket Chip Clock Configuration 4 | 5 | 6 | Rocket Chip 1000 RC_CLK_MULT 7 | Clockrate = --------------- X ------------- 8 | (in MHz) ZYNQ_CLK_PERIOD RC_CLK_DIVIDE 9 | 10 | 11 | This sets the parameters used by rocketchip_wrapper.v to 12 | generate its own clock. 13 | 14 | Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE. 15 | ZYNQ_CLK_PERIOD should only be changed to match the input 16 | clock period set in the Vivado GUI and 17 | hw/src/constrs/pin_constraints.xdc 18 | 19 | */ 20 | 21 | 22 | `ifndef _clocking_vh_ 23 | `define _clocking_vh_ 24 | 25 | 26 | `define ZYNQ_CLK_PERIOD 10.0 27 | 28 | `define RC_CLK_MULT 10.0 29 | 30 | `define RC_CLK_DIVIDE 40.0 31 | 32 | 33 | `endif // _clocking_vh_ 34 | --------------------------------------------------------------------------------