├── .gitignore ├── .gitmodules ├── .travis.yml ├── CONTRIBUTORS ├── Jenkinsfile ├── LICENSE.Berkeley ├── LICENSE.Cambridge ├── LICENSE.SiFive ├── LICENSE.jtag ├── Makefrag ├── Makefrag-build ├── README.md ├── bootrom ├── .gitignore ├── Makefile ├── bootrom.S ├── bootrom.img ├── hostdetect.c └── linker.ld ├── csrc ├── SimDTM.cc ├── comlog.cc ├── emulator.cc ├── float_fix.cc ├── jtag_vpi.c └── verilator.h ├── jenkins └── Makefile ├── project ├── .gitignore ├── build.properties ├── build.scala └── plugins.sbt ├── sbt-launch.jar ├── scripts ├── .gitignore ├── Makefile ├── authors ├── check_cache_trace.py ├── check_comparator_trace.py ├── copyright-file ├── debug_rom │ ├── Makefile │ ├── debug_rom.S │ └── link.ld ├── modify-copyright ├── toaxe.py ├── tracegen+check.sh ├── tracegen.py ├── tracestats.py ├── vlsi_mem_gen └── vlsi_rom_gen ├── set_env.sh ├── src ├── main │ └── verilog │ │ ├── SimJTAG_xilinx.v │ │ ├── ascii_code.v │ │ ├── axis_gmii_rx.v │ │ ├── axis_gmii_tx.v │ │ ├── chip_top.sv │ │ ├── chip_top_dummy.sv │ │ ├── config.vh │ │ ├── consts.vh │ │ ├── debug_system.sv │ │ ├── dualmem.v │ │ ├── dualmem_32K_64.sv │ │ ├── dualmem_widen.v │ │ ├── dualmem_widen8.v │ │ ├── eth_lfsr.v │ │ ├── fpga_srams_edited.v │ │ ├── framing_top.sv │ │ ├── fstore2.v │ │ ├── lfsr.v │ │ ├── mii_to_rmii_0_open.v │ │ ├── my_fifo.v │ │ ├── nasti_channel.sv │ │ ├── periph_soc.sv │ │ ├── ps2.v │ │ ├── ps2_defines.v │ │ ├── ps2_keyboard.v │ │ ├── ps2_translation_table.v │ │ ├── rachelset.v │ │ ├── rx_delay.v │ │ ├── sd_bus.sv │ │ ├── sd_clock_divider.v │ │ ├── sd_cmd_serial_host.v │ │ ├── sd_crc_16.v │ │ ├── sd_crc_7.v │ │ ├── sd_data_serial_host.sv │ │ ├── sd_defines.h │ │ ├── sd_top.sv │ │ ├── spi_wrapper.sv │ │ ├── stubs.sv │ │ └── uart.v └── test │ ├── cxx │ ├── common │ │ ├── dpi_host_behav.cpp │ │ ├── dpi_host_behav.h │ │ ├── dpi_ram_behav.cpp │ │ ├── dpi_ram_behav.h │ │ ├── elf.h │ │ ├── globals.cpp │ │ ├── globals.h │ │ ├── loadelf.cpp │ │ └── loadelf.hpp │ └── veri │ │ └── veri_top.cc │ └── verilog │ ├── chip_top_tb.sv │ ├── host_behav.sv │ ├── host_behav_dummy.sv │ ├── nasti_ram_behav.sv │ ├── nasti_ram_dummy.sv │ ├── nasti_ram_sim.sv │ └── sd_verilator_model.sv ├── unitest ├── .gitignore ├── Makefile └── vlsi_mem_gen ├── vcs ├── .gitignore └── Makefile ├── vsim ├── .gitignore ├── Makefile ├── locore.S ├── lowrisc.lds ├── tlbtest.S └── tlbtest.sh └── vsrc ├── AsyncResetReg.v ├── ClockDivider2.v ├── ClockDivider3.v ├── DebugTransportJTAG-orig.sv ├── JTAGDTM.sv ├── JTAGDummy.v ├── JtagTapController_artix.sv ├── JtagTapController_asic.sv ├── SimDTM.v ├── SimDTM_JTAG.sv ├── TestDriver.v ├── jtag_addr.v ├── jtag_dummy.v ├── jtag_modules.sv ├── jtag_rom.v ├── jtag_vpi.tab ├── jtag_vpi.v ├── jtagsm_dummy.sv ├── plusarg_reader.v ├── vsim_bscan_dummy.v └── vsim_glbl.v /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/lowrisc-chip/HEAD/.gitignore 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