├── .gitignore ├── COPYING.BSD ├── COPYING.CC ├── ChangeLog ├── Makefile ├── README.md ├── doc ├── .gitignore ├── ChangeLog ├── Makefile ├── README.adoc └── custom.wordlist ├── riscv-ovpsim ├── ChangeLog.md ├── LICENSE.pdf ├── README.md ├── bin │ ├── Linux64 │ │ ├── libdwarf-20120410.so │ │ ├── libelf.so.0.8.13 │ │ ├── libtcl8.4.so │ │ ├── riscv-none-embed-gdb │ │ └── riscvOVPsim.exe │ ├── OVP_GNU_PACKAGES_GPL_LICENSE.txt │ ├── OVP_TCL_LICENSE.txt │ ├── OVP_WIN_PTHREADS_LICENSE.txt │ ├── README.md │ └── Windows64 │ │ ├── libdwarf-20120410.dll │ │ ├── libelf-0.8.13.dll │ │ ├── lmgr11_imperas.dll │ │ ├── pthreadGC2-w64.dll │ │ ├── riscv-none-embed-gdb.exe │ │ ├── riscvOVPsim.exe │ │ └── tcl85.dll ├── config-yaml │ ├── Makefile │ ├── README.md │ ├── examples │ │ ├── Ibex_RV32IMC.yaml │ │ ├── Ibex_RV32IMC_platform.yaml │ │ ├── RVB32I_isa.yaml │ │ └── RVB32I_platform.yaml │ ├── main.py │ ├── requirements.txt │ └── writeOVPsimConfig.py ├── doc │ ├── OVP_Model_Specific_Information_riscv_RV64GCV.pdf │ ├── README.md │ └── riscvOVPsim_User_Guide.pdf ├── examples │ ├── CoreMark │ │ ├── 32_core_portme.c │ │ ├── 32_core_portme.h │ │ ├── LICENSE.md │ │ ├── README.md │ │ ├── RUN_RV32_CoreMark.bat │ │ ├── RUN_RV32_CoreMark.sh │ │ └── coremark.RISCV32.elf │ ├── README.md │ ├── bitmanip │ │ ├── Makefile │ │ ├── README.md │ │ ├── RUN_RV64GC_BITMANIP_EXAMPLE.bat │ │ ├── RUN_RV64GC_BITMANIP_EXAMPLE.sh │ │ ├── bdep.S │ │ ├── bdep.elf │ │ ├── bext.S │ │ ├── bext.elf │ │ ├── clz.S │ │ ├── clz.elf │ │ ├── ctz.S │ │ ├── ctz.elf │ │ ├── pcnt.S │ │ └── pcnt.elf │ ├── dhrystone │ │ ├── DEBUG_GDB_RV32_dhrystone.bat │ │ ├── DEBUG_GDB_RV32_dhrystone.sh │ │ ├── README.md │ │ ├── RUN_RV32_dhrystone.bat │ │ ├── RUN_RV32_dhrystone.sh │ │ ├── RUN_RV64_dhrystone.bat │ │ ├── RUN_RV64_dhrystone.sh │ │ ├── dhrystone.RISCV32.elf │ │ ├── dhrystone.RISCV64.elf │ │ └── dhrystone.c │ ├── fibonacci │ │ ├── README.md │ │ ├── RUN_RV32_fibonacci.bat │ │ ├── RUN_RV32_fibonacci.sh │ │ ├── RUN_RV64_fibonacci.bat │ │ ├── RUN_RV64_fibonacci.sh │ │ ├── RUN_RV64_fibonacci_signature_dump.bat │ │ ├── RUN_RV64_fibonacci_signature_dump.sh │ │ ├── fibonacci.RISCV32.elf │ │ ├── fibonacci.RISCV64.elf │ │ └── fibonacci.c │ ├── linpack │ │ ├── README.md │ │ ├── RUN_RV32_linpack.bat │ │ ├── RUN_RV32_linpack.sh │ │ ├── linpack.RISCV32.elf │ │ └── linpack.c │ └── vector │ │ ├── 16.7.c │ │ ├── 16.7.elf │ │ ├── 6.4.c │ │ ├── 6.4.elf │ │ ├── 7.7.c │ │ ├── 7.7.elf │ │ ├── README.md │ │ ├── RUN_RV64GC_VECTOR_EXAMPLE.bat │ │ ├── RUN_RV64GC_VECTOR_EXAMPLE.sh │ │ ├── conditional.c │ │ ├── conditional.elf │ │ ├── memcpy.c │ │ ├── memcpy.elf │ │ ├── mixed-width-mask.c │ │ ├── mixed-width-mask.elf │ │ ├── saxpy.c │ │ ├── saxpy.elf │ │ ├── vector-vector-add.c │ │ └── vector-vector-add.elf ├── riscvOVPsim.jpg └── source │ ├── README.md │ ├── riscvAttrs.c │ ├── riscvBlockState.h │ ├── riscvBus.c │ ├── riscvBus.h │ ├── riscvCSR.c │ ├── riscvCSR.h │ ├── riscvCSRTypes.h │ ├── riscvCluster.c │ ├── riscvCluster.h │ ├── riscvConfig.h │ ├── riscvConfigList.c │ ├── riscvDebug.c │ ├── riscvDebug.h │ ├── riscvDecode.c │ ├── riscvDecode.h │ ├── riscvDecodeTypes.h │ ├── riscvDerivedMorph.h │ ├── riscvDisassemble.c │ ├── riscvDisassembleFormats.h │ ├── riscvDoc.c │ ├── riscvDoc.h │ ├── riscvExceptionDefinitions.h │ ├── riscvExceptionTypes.h │ ├── riscvExceptions.c │ ├── riscvExceptions.h │ ├── riscvFunctions.h │ ├── riscvInfo.c │ ├── riscvInstructionInfo.h │ ├── riscvMain.c │ ├── riscvMessage.h │ ├── riscvMode.h │ ├── riscvModelCallbacks.h │ ├── riscvMorph.c │ ├── riscvMorph.h │ ├── riscvParameters.c │ ├── riscvParameters.h │ ├── riscvRegisterTypes.h │ ├── riscvRegisters.h │ ├── riscvSemiHost.c │ ├── riscvStructure.h │ ├── riscvTypeRefs.h │ ├── riscvTypes.h │ ├── riscvUtils.c │ ├── riscvUtils.h │ ├── riscvVM.c │ ├── riscvVM.h │ ├── riscvVMConstants.h │ ├── riscvVariant.c │ ├── riscvVariant.h │ └── riscvVectorTypes.h ├── riscv-target ├── Codasip-simulator │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ └── rv32i │ │ └── Makefile.include ├── README.md ├── grift │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ ├── rv32i │ │ └── Makefile.include │ │ ├── rv32im │ │ └── Makefile.include │ │ ├── rv32imc │ │ └── Makefile.include │ │ ├── rv64i │ │ └── Makefile.include │ │ └── rv64im │ │ └── Makefile.include ├── ibex │ ├── README.md │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ └── rv32imc │ │ ├── Makefile.include │ │ ├── handler.S │ │ ├── isa.yaml │ │ ├── link.ld │ │ └── platform.yaml ├── ri5cy │ ├── README.md │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ └── rv32imc │ │ ├── Makefile.include │ │ ├── handler.S │ │ └── link.ld ├── riscvOVPsim │ ├── README.md │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ ├── rv32Zicsr │ │ └── Makefile.include │ │ ├── rv32Zifencei │ │ └── Makefile.include │ │ ├── rv32i │ │ └── Makefile.include │ │ ├── rv32im │ │ └── Makefile.include │ │ └── rv32imc │ │ └── Makefile.include ├── rocket │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ ├── rv32Zicsr │ │ └── Makefile.include │ │ ├── rv32Zifencei │ │ └── Makefile.include │ │ ├── rv32i │ │ └── Makefile.include │ │ ├── rv32im │ │ └── Makefile.include │ │ └── rv32imc │ │ └── Makefile.include ├── sail-riscv-c │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ ├── rv32Zicsr │ │ └── Makefile.include │ │ ├── rv32Zifencei │ │ └── Makefile.include │ │ ├── rv32i │ │ └── Makefile.include │ │ ├── rv32im │ │ └── Makefile.include │ │ └── rv32imc │ │ └── Makefile.include ├── sail-riscv-ocaml │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ │ ├── rv32Zicsr │ │ └── Makefile.include │ │ ├── rv32Zifencei │ │ └── Makefile.include │ │ ├── rv32i │ │ └── Makefile.include │ │ ├── rv32im │ │ └── Makefile.include │ │ └── rv32imc │ │ └── Makefile.include ├── sifive-formal │ ├── compliance_io.h │ ├── compliance_test.h │ ├── device │ │ └── rv32i │ │ │ └── Makefile.include │ └── formalspec-env │ │ ├── LICENSE │ │ ├── aw_test_macros.h │ │ ├── encoding.h │ │ ├── p │ │ ├── link.ld │ │ └── riscv_test.h │ │ └── test_macros.h └── spike │ ├── compliance_io.h │ ├── compliance_test.h │ └── device │ ├── rv32Zicsr │ └── Makefile.include │ ├── rv32Zifencei │ └── Makefile.include │ ├── rv32i │ └── Makefile.include │ ├── rv32im │ └── Makefile.include │ └── rv32imc │ └── Makefile.include ├── riscv-test-env ├── LICENSE ├── aw_test_macros.h ├── encoding.h ├── p │ ├── link.ld │ └── riscv_test.h ├── pm │ ├── link.ld │ └── riscv_test.h ├── pt │ ├── link.ld │ └── riscv_test.h ├── riscv_test_macros.h ├── test_macros.h ├── v │ ├── entry.S │ ├── link.ld │ ├── riscv_test.h │ ├── string.c │ └── vm.c └── verify.sh ├── riscv-test-suite ├── README.md ├── deprecated │ ├── rv32mi │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── breakpoint.reference_output │ │ │ ├── csr.reference_output │ │ │ ├── illegal.reference_output │ │ │ ├── ma_addr.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── mcsr.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── shamt.reference_output │ │ ├── rv64mi │ │ │ ├── Makefrag │ │ │ ├── access.S │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ └── scall.S │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── shamt.S │ ├── rv32si │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── csr.reference_output │ │ │ ├── dirty.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── wfi.reference_output │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ ├── rv32ua │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── amoadd_w.reference_output │ │ │ ├── amoand_w.reference_output │ │ │ ├── amomax_w.reference_output │ │ │ ├── amomaxu_w.reference_output │ │ │ ├── amomin_w.reference_output │ │ │ ├── amominu_w.reference_output │ │ │ ├── amoor_w.reference_output │ │ │ ├── amoswap_w.reference_output │ │ │ ├── amoxor_w.reference_output │ │ │ └── lrsc.reference_output │ │ ├── rv64ua │ │ │ ├── Makefrag │ │ │ ├── amoadd_d.S │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_d.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_d.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_d.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_d.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_d.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_d.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_d.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_d.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ ├── rv32uc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ └── rvc.reference_output │ │ ├── rv64uc │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ └── rvc.S │ ├── rv32ud │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64ud │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── structural.S │ │ └── src │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ ├── rv32uf │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fcvt_w.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ ├── move.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64uf │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ └── rv32ui │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ ├── add.reference_output │ │ ├── addi.reference_output │ │ ├── and.reference_output │ │ ├── andi.reference_output │ │ ├── auipc.reference_output │ │ ├── beq.reference_output │ │ ├── bge.reference_output │ │ ├── bgeu.reference_output │ │ ├── blt.reference_output │ │ ├── bltu.reference_output │ │ ├── bne.reference_output │ │ ├── fence_i.reference_output │ │ ├── jal.reference_output │ │ ├── jalr.reference_output │ │ ├── lb.reference_output │ │ ├── lbu.reference_output │ │ ├── lh.reference_output │ │ ├── lhu.reference_output │ │ ├── lui.reference_output │ │ ├── lw.reference_output │ │ ├── or.reference_output │ │ ├── ori.reference_output │ │ ├── sb.reference_output │ │ ├── sh.reference_output │ │ ├── simple.reference_output │ │ ├── sll.reference_output │ │ ├── slli.reference_output │ │ ├── slt.reference_output │ │ ├── slti.reference_output │ │ ├── sltiu.reference_output │ │ ├── sltu.reference_output │ │ ├── sra.reference_output │ │ ├── srai.reference_output │ │ ├── srl.reference_output │ │ ├── srli.reference_output │ │ ├── sub.reference_output │ │ ├── sw.reference_output │ │ ├── xor.reference_output │ │ └── xori.reference_output │ │ ├── rv64ui │ │ ├── Makefrag │ │ ├── add.S │ │ ├── addi.S │ │ ├── addiw.S │ │ ├── addw.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── ld.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── lwu.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sd.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slliw.S │ │ ├── sllw.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── sraiw.S │ │ ├── sraw.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── srliw.S │ │ ├── srlw.S │ │ ├── sub.S │ │ ├── subw.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S │ │ └── src │ │ ├── Makefrag.spike │ │ ├── add.S │ │ ├── addi.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── sub.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S ├── rv32Zicsr │ ├── .gitignore │ ├── Makefile │ ├── Makefrag │ ├── references │ │ ├── I-CSRRC-01.reference_output │ │ ├── I-CSRRCI-01.reference_output │ │ ├── I-CSRRS-01.reference_output │ │ ├── I-CSRRSI-01.reference_output │ │ ├── I-CSRRW-01.reference_output │ │ └── I-CSRRWI-01.reference_output │ └── src │ │ ├── I-CSRRC-01.S │ │ ├── I-CSRRCI-01.S │ │ ├── I-CSRRS-01.S │ │ ├── I-CSRRSI-01.S │ │ ├── I-CSRRW-01.S │ │ └── I-CSRRWI-01.S ├── rv32Zifencei │ ├── .gitignore │ ├── Makefile │ ├── Makefrag │ ├── references │ │ └── I-FENCE.I-01.reference_output │ └── src │ │ └── I-FENCE.I-01.S ├── rv32i │ ├── .gitignore │ ├── Makefile │ ├── Makefrag │ ├── coverage │ │ ├── report.txt │ │ └── summary.txt │ ├── references │ │ ├── I-ADD-01.reference_output │ │ ├── I-ADDI-01.reference_output │ │ ├── I-AND-01.reference_output │ │ ├── I-ANDI-01.reference_output │ │ ├── I-AUIPC-01.reference_output │ │ ├── I-BEQ-01.reference_output │ │ ├── I-BGE-01.reference_output │ │ ├── I-BGEU-01.reference_output │ │ ├── I-BLT-01.reference_output │ │ ├── I-BLTU-01.reference_output │ │ ├── I-BNE-01.reference_output │ │ ├── I-DELAY_SLOTS-01.reference_output │ │ ├── I-EBREAK-01.reference_output │ │ ├── I-ECALL-01.reference_output │ │ ├── I-ENDIANESS-01.reference_output │ │ ├── I-IO-01.reference_output │ │ ├── I-JAL-01.reference_output │ │ ├── I-JALR-01.reference_output │ │ ├── I-LB-01.reference_output │ │ ├── I-LBU-01.reference_output │ │ ├── I-LH-01.reference_output │ │ ├── I-LHU-01.reference_output │ │ ├── I-LUI-01.reference_output │ │ ├── I-LW-01.reference_output │ │ ├── I-MISALIGN_JMP-01.reference_output │ │ ├── I-MISALIGN_LDST-01.reference_output │ │ ├── I-NOP-01.reference_output │ │ ├── I-OR-01.reference_output │ │ ├── I-ORI-01.reference_output │ │ ├── I-RF_size-01.reference_output │ │ ├── I-RF_width-01.reference_output │ │ ├── I-RF_x0-01.reference_output │ │ ├── I-SB-01.reference_output │ │ ├── I-SH-01.reference_output │ │ ├── I-SLL-01.reference_output │ │ ├── I-SLLI-01.reference_output │ │ ├── I-SLT-01.reference_output │ │ ├── I-SLTI-01.reference_output │ │ ├── I-SLTIU-01.reference_output │ │ ├── I-SLTU-01.reference_output │ │ ├── I-SRA-01.reference_output │ │ ├── I-SRAI-01.reference_output │ │ ├── I-SRL-01.reference_output │ │ ├── I-SRLI-01.reference_output │ │ ├── I-SUB-01.reference_output │ │ ├── I-SW-01.reference_output │ │ ├── I-XOR-01.reference_output │ │ └── I-XORI-01.reference_output │ └── src │ │ ├── I-ADD-01.S │ │ ├── I-ADDI-01.S │ │ ├── I-AND-01.S │ │ ├── I-ANDI-01.S │ │ ├── I-AUIPC-01.S │ │ ├── I-BEQ-01.S │ │ ├── I-BGE-01.S │ │ ├── I-BGEU-01.S │ │ ├── I-BLT-01.S │ │ ├── I-BLTU-01.S │ │ ├── I-BNE-01.S │ │ ├── I-DELAY_SLOTS-01.S │ │ ├── I-EBREAK-01.S │ │ ├── I-ECALL-01.S │ │ ├── I-ENDIANESS-01.S │ │ ├── I-IO-01.S │ │ ├── I-JAL-01.S │ │ ├── I-JALR-01.S │ │ ├── I-LB-01.S │ │ ├── I-LBU-01.S │ │ ├── I-LH-01.S │ │ ├── I-LHU-01.S │ │ ├── I-LUI-01.S │ │ ├── I-LW-01.S │ │ ├── I-MISALIGN_JMP-01.S │ │ ├── I-MISALIGN_LDST-01.S │ │ ├── I-NOP-01.S │ │ ├── I-OR-01.S │ │ ├── I-ORI-01.S │ │ ├── I-RF_size-01.S │ │ ├── I-RF_width-01.S │ │ ├── I-RF_x0-01.S │ │ ├── I-SB-01.S │ │ ├── I-SH-01.S │ │ ├── I-SLL-01.S │ │ ├── I-SLLI-01.S │ │ ├── I-SLT-01.S │ │ ├── I-SLTI-01.S │ │ ├── I-SLTIU-01.S │ │ ├── I-SLTU-01.S │ │ ├── I-SRA-01.S │ │ ├── I-SRAI-01.S │ │ ├── I-SRL-01.S │ │ ├── I-SRLI-01.S │ │ ├── I-SUB-01.S │ │ ├── I-SW-01.S │ │ ├── I-XOR-01.S │ │ └── I-XORI-01.S ├── rv32im │ ├── Makefile │ ├── Makefrag │ ├── coverage │ │ ├── report.txt │ │ └── summary.txt │ ├── references │ │ ├── DIV.reference_output │ │ ├── DIVU.reference_output │ │ ├── MUL.reference_output │ │ ├── MULH.reference_output │ │ ├── MULHSU.reference_output │ │ ├── MULHU.reference_output │ │ ├── REM.reference_output │ │ └── REMU.reference_output │ └── src │ │ ├── DIV.S │ │ ├── DIVU.S │ │ ├── MUL.S │ │ ├── MULH.S │ │ ├── MULHSU.S │ │ ├── MULHU.S │ │ ├── REM.S │ │ └── REMU.S ├── rv32imc │ ├── Makefile │ ├── Makefrag │ ├── coverage │ │ ├── report.txt │ │ └── summary.txt │ ├── references │ │ ├── C-ADD.reference_output │ │ ├── C-ADDI.reference_output │ │ ├── C-ADDI16SP.reference_output │ │ ├── C-ADDI4SPN.reference_output │ │ ├── C-AND.reference_output │ │ ├── C-ANDI.reference_output │ │ ├── C-BEQZ.reference_output │ │ ├── C-BNEZ.reference_output │ │ ├── C-J.reference_output │ │ ├── C-JAL.reference_output │ │ ├── C-JALR.reference_output │ │ ├── C-JR.reference_output │ │ ├── C-LI.reference_output │ │ ├── C-LUI.reference_output │ │ ├── C-LW.reference_output │ │ ├── C-LWSP.reference_output │ │ ├── C-MV.reference_output │ │ ├── C-OR.reference_output │ │ ├── C-SLLI.reference_output │ │ ├── C-SRAI.reference_output │ │ ├── C-SRLI.reference_output │ │ ├── C-SUB.reference_output │ │ ├── C-SW.reference_output │ │ ├── C-SWSP.reference_output │ │ └── C-XOR.reference_output │ └── src │ │ ├── C-ADD.S │ │ ├── C-ADDI.S │ │ ├── C-ADDI16SP.S │ │ ├── C-ADDI4SPN.S │ │ ├── C-AND.S │ │ ├── C-ANDI.S │ │ ├── C-BEQZ.S │ │ ├── C-BNEZ.S │ │ ├── C-J.S │ │ ├── C-JAL.S │ │ ├── C-JALR.S │ │ ├── C-JR.S │ │ ├── C-LI.S │ │ ├── C-LUI.S │ │ ├── C-LW.S │ │ ├── C-LWSP.S │ │ ├── C-MV.S │ │ ├── C-OR.S │ │ ├── C-SLLI.S │ │ ├── C-SRAI.S │ │ ├── C-SRLI.S │ │ ├── C-SUB.S │ │ ├── C-SW.S │ │ ├── C-SWSP.S │ │ └── C-XOR.S └── wip │ ├── rv64i │ ├── Makefile │ ├── Makefrag │ ├── references │ │ ├── ADDIW.reference_output │ │ ├── ADDW.reference_output │ │ ├── SLLIW.reference_output │ │ ├── SLLW.reference_output │ │ ├── SRAIW.reference_output │ │ ├── SRAW.reference_output │ │ ├── SRLIW.reference_output │ │ ├── SRLW.reference_output │ │ └── SUBW.reference_output │ └── src │ │ ├── ADDIW.S │ │ ├── ADDW.S │ │ ├── SLLIW.S │ │ ├── SLLW.S │ │ ├── SRAIW.S │ │ ├── SRAW.S │ │ ├── SRLIW.S │ │ ├── SRLW.S │ │ └── SUBW.S │ └── rv64im │ ├── Makefile │ ├── Makefrag │ ├── references │ ├── DIVW.reference_output │ ├── MULW.reference_output │ ├── REMUW.reference_output │ └── REMW.reference_output │ └── src │ ├── DIVW.S │ ├── MULW.S │ ├── REMUW.S │ └── REMW.S └── spec ├── TestFormatSpec.adoc ├── TestFormatSpec.pdf └── testpool.jpg /.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore editor backup files 2 | *~ 3 | # Ignore transients generated by the tests 4 | /.cproject 5 | /.project 6 | /work/ 7 | /setup.env 8 | #ignore Mac file system artifacts 9 | *.DS_Store 10 | -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore editor backups 2 | *~ 3 | # Generated files 4 | custom.dict 5 | README.pdf 6 | README.html -------------------------------------------------------------------------------- /doc/custom.wordlist: -------------------------------------------------------------------------------- 1 | AsciiDoc 2 | asciidoc 3 | AsciiDoctor 4 | asciidoctor 5 | aspell 6 | autotools 7 | CGEN 8 | cmake 9 | Codasip 10 | creativecommons 11 | CY 12 | Davidmann 13 | discoverable 14 | DUT 15 | EF 16 | enforceability 17 | FPGA 18 | GDB 19 | Generis 20 | github 21 | Hajek 22 | HDL 23 | http 24 | https 25 | IC 26 | ies 27 | immunities 28 | Imperas 29 | io 30 | IM 31 | ISA 32 | legalcode 33 | licensor 34 | licensors 35 | licensor's 36 | LLVM 37 | makefile 38 | makefiles 39 | Marcela 40 | md 41 | merchantability 42 | Nostersky 43 | nz 44 | pagewidth 45 | parameterization 46 | pdf 47 | publicdomain 48 | Radek 49 | README 50 | riscv 51 | riscvOVPsim 52 | RTL 53 | rv 54 | RVTEST 55 | SiFive 56 | spdx 57 | src 58 | subdirectory 59 | sublicensable 60 | synched 61 | tbd 62 | testbench 63 | toc 64 | toolchain 65 | TVM 66 | URI 67 | Verilator 68 | Verilog 69 | waivable 70 | WIPO 71 | wordlist 72 | www 73 | Zachariasova 74 | -------------------------------------------------------------------------------- /riscv-ovpsim/LICENSE.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/LICENSE.pdf -------------------------------------------------------------------------------- /riscv-ovpsim/bin/Linux64/libdwarf-20120410.so: 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license Version 2.1 6 | 7 | Ref: https://www.gnu.org/licenses/license-list.html 8 | -------------------------------------------------------------------------------- /riscv-ovpsim/bin/README.md: -------------------------------------------------------------------------------- 1 | riscvOVPsim/bin/README.md 2 | --- 3 | In this directory are the different host platforms that the simulator runs on. 4 | 5 | Each directory includes the binary libraries and executables required to run the simulation. 6 | -------------------------------------------------------------------------------- /riscv-ovpsim/bin/Windows64/libdwarf-20120410.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/bin/Windows64/libdwarf-20120410.dll -------------------------------------------------------------------------------- /riscv-ovpsim/bin/Windows64/libelf-0.8.13.dll: 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| mtime: 16 | implemented: False 17 | nmi: 18 | address: 0x800000FC # trap vec (mtvec base) + 0x7C 19 | reset: 20 | address: 0x80000080 # boot address + 0x80 21 | -------------------------------------------------------------------------------- /riscv-ovpsim/config-yaml/examples/RVB32I_platform.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Imperas Software Ltd 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http:#www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | nmi: 16 | address: 0x010 17 | reset: 18 | address: 0x1000 19 | 20 | mcause: 21 | implemented: true 22 | 23 | mtime: 24 | implemented: false 25 | mtimecmp: 26 | implemented: false 27 | mtval: 28 | implemented: true 29 | # is_hardwired: true 30 | 31 | -------------------------------------------------------------------------------- /riscv-ovpsim/config-yaml/requirements.txt: -------------------------------------------------------------------------------- 1 | Cerberus>=1.3.1 2 | ruamel.yaml>=0.16.0 3 | oyaml>=0.9 4 | riscv-config==1.0.0 5 | -------------------------------------------------------------------------------- /riscv-ovpsim/doc/OVP_Model_Specific_Information_riscv_RV64GCV.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/doc/OVP_Model_Specific_Information_riscv_RV64GCV.pdf -------------------------------------------------------------------------------- /riscv-ovpsim/doc/README.md: -------------------------------------------------------------------------------- 1 | riscvOVPsim/doc/README.md 2 | --- 3 | In this directory is the simulator documentation as a pdf file. 4 | 5 | The document lists the different processor variants and configurations the simulator supports and explains all the different command line options needed to execute cross compiled RISC-V target _elf_ files. 6 | 7 | To see all the RISC-V models available from OVP visit [risc-v-processors](http://www.ovpworld.org/library/wikka.php?wakka=RiscVprocessors). 8 | 9 | To see all the detailed documentation of the models visit [risc-v-processors pdf documents](http://www.ovpworld.org/procmodeldocs) (and scroll down to the section on RISC-V). 10 | -------------------------------------------------------------------------------- /riscv-ovpsim/doc/riscvOVPsim_User_Guide.pdf: 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%BATCHDIR% 6 | 7 | ..\..\bin\Windows64\riscvOVPsim.exe ^ 8 | --program coremark.RISCV32.elf ^ 9 | --variant RVB32I ^ 10 | --override riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | %* ^ 12 | -argv 0 0 0x66 13 | 14 | ;rem validate with args 15 | ;rem 0 0 0x66 16 | ;rem and 17 | ;rem 0x3415 0x3415 0x66 18 | ;rem next argument is iterations, default 1000 19 | 20 | if not defined calledscript ( pause ) 21 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/CoreMark/RUN_RV32_CoreMark.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program coremark.RISCV32.elf \ 8 | --variant RVB32I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU "$@" \ 10 | -argv 0 0 0x66 11 | 12 | # validate with args 13 | # 0 0 0x66 14 | # and 15 | # 0x3415 0x3415 0x66 16 | # next argument is iterations, default 1000 17 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/CoreMark/coremark.RISCV32.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/CoreMark/coremark.RISCV32.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/bitmanip/Makefile: -------------------------------------------------------------------------------- 1 | ifndef IMPERAS_HOME 2 | IMPERAS_ERROR := $(error "IMPERAS_HOME not defined, please setup Imperas/OVP environment") 3 | endif 4 | IMPERAS_HOME := $(shell getpath.exe "$(IMPERAS_HOME)") 5 | 6 | SRC = $(wildcard *.S) 7 | ELF = $(SRC:.S=.elf) 8 | OD = $(SRC:.S=.od) 9 | 10 | PATH := $(PATH):$(IMPERAS_HOME)/lib/$(IMPERAS_ARCH)/CrossCompiler/riscv-none-embed/bin 11 | RISCV_PREFIX ?= riscv-none-embed- 12 | RISCV_CC ?= $(RISCV_PREFIX)gcc 13 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 14 | 15 | OPT_CC = -mabi=lp64 -march=rv64im -DXLEN64 16 | OPT_CC += -Wl,-Ttext=0x80000000 -nostartfiles 17 | 18 | 19 | all: $(ELF) $(OD) 20 | 21 | %.elf: %.S 22 | @echo "# Build $@" 23 | $(RISCV_CC) $(OPT_CC) -o $@ $< 24 | 25 | %.od: %.elf 26 | @echo "# Objdump $<" 27 | $(RISCV_OBJDUMP) -D $< > $@ 28 | 29 | clean: 30 | rm -f $(ELF) $(OD) 31 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/bitmanip/RUN_RV64GC_BITMANIP_EXAMPLE.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | apps=$(ls *.elf | sort -d) 7 | PS3='Please Choose Bit Manipulation Example: ' 8 | select app in $apps 9 | do 10 | break 11 | done 12 | echo "Selected Example $app" 13 | 14 | # Run Example 15 | ${bindir}/riscvOVPsim.exe \ 16 | --variant RVB64I \ 17 | --override riscvOVPsim/cpu/add_Extensions=MAFDCBSU \ 18 | --program ${app} \ 19 | --override riscvOVPsim/cpu/defaultsemihost=F \ 20 | --override riscvOVPsim/cpu/debugflags=6 \ 21 | --override riscvOVPsim/cpu/wfi_is_nop=0 \ 22 | --override riscvOVPsim/cpu/simulateexceptions=T \ 23 | --override riscvOVPsim/cpu/PMP_registers=0 \ 24 | --override riscvOVPsim/cpu/ASID_bits=0 \ 25 | --override riscvOVPsim/cpu/tval_ii_code=F \ 26 | --customcontrol \ 27 | "$@" 28 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/bitmanip/bdep.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/bitmanip/bdep.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/bitmanip/bext.elf: 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-------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | 5 | # To start GDB connected to the simulator we add -gdbconsole 6 | RUN_RV32_dhrystone.sh -gdbconsole "$@" 7 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/dhrystone/README.md: -------------------------------------------------------------------------------- 1 | riscvOVPsim/examples/*/README.md 2 | --- 3 | 4 | In this directory is an example application. 5 | 6 | It has been cross compiled to create the _elf_ files provided. 7 | 8 | There are scripts to load the elf files and execute the simulator. 9 | 10 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/dhrystone/RUN_RV32_dhrystone.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | ;rem move into the Example Directory 4 | set BATCHDIR=%~dp0% 5 | cd /d %BATCHDIR% 6 | 7 | ..\..\bin\Windows64\riscvOVPsim.exe ^ 8 | --program dhrystone.RISCV32.elf ^ 9 | --variant RVB32I ^ 10 | --override riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | %* 12 | 13 | if not defined calledscript ( pause ) 14 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/dhrystone/RUN_RV32_dhrystone.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program dhrystone.RISCV32.elf \ 8 | --variant RVB32I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU \ 10 | "$@" 11 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/dhrystone/RUN_RV64_dhrystone.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | ;rem move into the Example Directory 4 | set BATCHDIR=%~dp0% 5 | cd /d %BATCHDIR% 6 | 7 | ..\..\bin\Windows64\riscvOVPsim.exe ^ 8 | --program dhrystone.RISCV64.elf ^ 9 | --variant RVB64I ^ 10 | --override riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | %* 12 | 13 | if not defined calledscript ( pause ) 14 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/dhrystone/RUN_RV64_dhrystone.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program dhrystone.RISCV64.elf \ 8 | --variant RVB64I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU \ 10 | "$@" 11 | 12 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/dhrystone/dhrystone.RISCV32.elf: -------------------------------------------------------------------------------- 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riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | %* 12 | 13 | if not defined calledscript ( pause ) 14 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/RUN_RV32_fibonacci.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program fibonacci.RISCV32.elf \ 8 | --variant RVB32I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU \ 10 | "$@" 11 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/RUN_RV64_fibonacci.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | ;rem move into the Example Directory 4 | set BATCHDIR=%~dp0% 5 | cd /d %BATCHDIR% 6 | 7 | ..\..\bin\Windows64\riscvOVPsim.exe ^ 8 | --program fibonacci.RISCV64.elf ^ 9 | --variant RVB64I ^ 10 | --override riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | %* 12 | 13 | if not defined calledscript ( pause ) 14 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/RUN_RV64_fibonacci.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program fibonacci.RISCV64.elf \ 8 | --variant RVB64I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU \ 10 | "$@" 11 | 12 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/RUN_RV64_fibonacci_signature_dump.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | ;rem move into the Example Directory 4 | set BATCHDIR=%~dp0% 5 | cd /d %BATCHDIR% 6 | 7 | ..\..\bin\Windows64\riscvOVPsim.exe ^ 8 | --program fibonacci.RISCV64.elf ^ 9 | --variant RVB64I ^ 10 | --override riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | --signaturedump ^ 12 | --override riscvOVPsim/cpu/sigdump/SignatureFile=fib.sig.dat.txt ^ 13 | --override riscvOVPsim/cpu/sigdump/StartSymbol="resultArray" ^ 14 | --override riscvOVPsim/cpu/sigdump/ByteCount=48 ^ 15 | --override riscvOVPsim/cpu/sigdump/SignatureAtEnd=T ^ 16 | --logfile fib.sig.run.log ^ 17 | %* 18 | 19 | if not defined calledscript ( pause ) 20 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/RUN_RV64_fibonacci_signature_dump.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program fibonacci.RISCV64.elf \ 8 | --variant RVB64I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU \ 10 | --signaturedump \ 11 | --override riscvOVPsim/cpu/sigdump/SignatureFile=fib.sig.dat.txt \ 12 | --override riscvOVPsim/cpu/sigdump/StartSymbol="resultArray" \ 13 | --override riscvOVPsim/cpu/sigdump/ByteCount=48 \ 14 | --override riscvOVPsim/cpu/sigdump/SignatureAtEnd=T \ 15 | --logfile fib.sig.run.log \ 16 | "$@" 17 | 18 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/fibonacci.RISCV32.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/fibonacci/fibonacci.RISCV32.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/fibonacci/fibonacci.RISCV64.elf: -------------------------------------------------------------------------------- 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linpack.RISCV32.elf ^ 9 | --variant RVB32I ^ 10 | --override riscvOVPsim/cpu/add_Extensions=MACSU ^ 11 | %* 12 | 13 | if not defined calledscript ( pause ) 14 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/linpack/RUN_RV32_linpack.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | ${bindir}/riscvOVPsim.exe \ 7 | --program linpack.RISCV32.elf \ 8 | --variant RVB32I \ 9 | --override riscvOVPsim/cpu/add_Extensions=MACSU \ 10 | "$@" 11 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/linpack/linpack.RISCV32.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/linpack/linpack.RISCV32.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/16.7.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/vector/16.7.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/6.4.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/vector/6.4.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/7.7.elf: -------------------------------------------------------------------------------- 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--override riscvOVPsim/cpu/vector_version=0.7.1-draft-20190605 ^ 31 | --override riscvOVPsim/cpu/VLEN=512 ^ 32 | --override riscvOVPsim/cpu/SLEN=64 ^ 33 | %* 34 | 35 | if not defined calledscript ( pause ) 36 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/RUN_RV64GC_VECTOR_EXAMPLE.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd $(dirname $0) 4 | bindir=$(dirname $(dirname $(pwd)))/bin/Linux64 5 | 6 | apps=$(ls *.elf | sort -d) 7 | PS3='Please Choose Vector Example: ' 8 | select app in $apps 9 | do 10 | break 11 | done 12 | echo "Selected Example $app" 13 | 14 | # Run Example 15 | ${bindir}/riscvOVPsim.exe \ 16 | --program ${app} \ 17 | --variant RVB64I \ 18 | --override riscvOVPsim/cpu/add_Extensions=MAFDCVSU \ 19 | --override riscvOVPsim/cpu/vector_version=0.7.1-draft-20190605 \ 20 | --override riscvOVPsim/cpu/VLEN=512 \ 21 | --override riscvOVPsim/cpu/SLEN=64 \ 22 | "$@" 23 | -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/conditional.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/vector/conditional.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/memcpy.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/examples/vector/memcpy.elf -------------------------------------------------------------------------------- /riscv-ovpsim/examples/vector/mixed-width-mask.elf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-ovpsim/riscvOVPsim.jpg -------------------------------------------------------------------------------- /riscv-ovpsim/source/README.md: -------------------------------------------------------------------------------- 1 | riscvOVPsim/source/README.md 2 | --- 3 | 4 | In this directory is the **_full source_** of the OVP model of the RISC-V processor and it is **_available as open source under the Apache 2.0 license_**. 5 | 6 | The model makes use of the OVP headers and OVP open standard APIs which are available as open source from Open Virtual Platforms (OVP). 7 | 8 | If you want to see the headers, examine the APIs, edit the source, recompile it, and then run the model on an OVP compliant simulator then please visit [www.OVPworld.org](http://www.ovpworld.org). 9 | 10 | You can download the package that includes all the model source from OVP here: [www.ovpworld.org/downloads#riscv.models](http://www.ovpworld.org/downloads/#riscv.models) and can download the simulator and headers etc. here: [www.ovpworld.org/downloads/#ovpsim](http://www.ovpworld.org/downloads/#ovpsim). 11 | 12 | To see all the RISC-V models available from OVP visit [risc-v-processors](http://www.ovpworld.org/library/wikka.php?wakka=RiscVprocessors). 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /riscv-ovpsim/source/riscvDebug.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 13 | * either express or implied. 14 | * 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | */ 19 | 20 | #pragma once 21 | 22 | // Imperas header files 23 | #include "hostapi/impTypes.h" 24 | 25 | // model header files 26 | #include "riscvTypeRefs.h" 27 | #include "riscvVariant.h" 28 | 29 | // 30 | // Free register descriptions, if they have been allocated 31 | // 32 | void riscvFreeRegInfo(riscvP riscv); 33 | 34 | -------------------------------------------------------------------------------- /riscv-ovpsim/source/riscvDerivedMorph.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 13 | * either express or implied. 14 | * 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | */ 19 | 20 | #pragma once 21 | 22 | // model header files 23 | #include "riscvTypeRefs.h" 24 | 25 | // 26 | // Code generation actions 27 | // 28 | #define RISCV_DERIVED_MORPH_FN(_NAME) void _NAME(riscvP riscv, void *clientData) 29 | typedef RISCV_DERIVED_MORPH_FN((*riscvDerivedMorphFn)); 30 | -------------------------------------------------------------------------------- /riscv-ovpsim/source/riscvDoc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 13 | * either express or implied. 14 | * 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | */ 19 | 20 | #pragma once 21 | 22 | // model header files 23 | #include "riscvTypeRefs.h" 24 | 25 | // 26 | // Create processor documentation 27 | // 28 | void riscvDoc(riscvP riscv); 29 | -------------------------------------------------------------------------------- /riscv-target/Codasip-simulator/compliance_io.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance Test Header File 2 | // Copyright (c) 2017, Codasip Ltd. All Rights Reserved. 3 | // See LICENSE for license details. 4 | // 5 | // Description: Common header file for RV32I tests 6 | 7 | 8 | #ifndef _COMPLIANCE_IO_H 9 | #define _COMPLIANCE_IO_H 10 | 11 | //----------------------------------------------------------------------- 12 | // RV IO Macros 13 | //----------------------------------------------------------------------- 14 | 15 | #define RVTEST_IO_INIT 16 | #define RVTEST_IO_PUTC(_R) 17 | #define RVTEST_IO_WRITE_STR(_SP, _STR) 18 | #define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) 19 | 20 | #endif // _COMPLIANCE_IO_H 21 | -------------------------------------------------------------------------------- /riscv-target/Codasip-simulator/device/rv32i/Makefile.include: -------------------------------------------------------------------------------- 1 | # TBD 2 | 3 | TARGET_SIM ?= codix_berkelium-ia-isimulator 4 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 5 | 6 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 7 | $(error Target simulator executable '$(TARGET_SIM)` not found) 8 | endif 9 | 10 | RUN_TARGET=\ 11 | $(TARGET_SIM) $(TARGET_FLAGS) -r --info 5 \ 12 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>$(work_dir_isa)/$(*).signature.output 13 | # +signature=$(work_dir_isa)/$(*).signature.output \ 14 | # $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 15 | 16 | RISCV_PREFIX ?= codix_berkelium-ia- 17 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 18 | RISCV_GCC_OPTS ?= -nostdlib -nodefaultlibs 19 | 20 | COMPILE_TARGET=\ 21 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 22 | -I$(ROOTDIR)/riscv-test-env/ \ 23 | -I$(ROOTDIR)/riscv-test-env/p/ \ 24 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 25 | $$< -o $(work_dir_isa)/$$@ 26 | -------------------------------------------------------------------------------- /riscv-target/README.md: -------------------------------------------------------------------------------- 1 | # RISC-V Targets 2 | 3 | The Target Environment needs setting up to allow the compliance tests to be run on that Target. This can be used while developing compliance test suites or it can be used with new Targets to see if they correctly execute the compliance test suites and are compliant! 4 | 5 | This directory provides the necsessary files for the currently available Targets. 6 | -------------------------------------------------------------------------------- /riscv-target/grift/device/rv32i/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= grift-sim 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) --arch=RV32I \ 9 | --mem-dump-begin=begin_signature --mem-dump-end=end_signature \ 10 | --halt-pc=grift_stop_addr \ 11 | $(work_dir_isa)/$< > $(work_dir_isa)/$(*).signature.output 2> $(work_dir_isa)/$@; 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/grift/device/rv32im/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= grift-sim 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) --arch=RV32IM \ 9 | --mem-dump-begin=begin_signature --mem-dump-end=end_signature \ 10 | --halt-pc=grift_stop_addr \ 11 | $(work_dir_isa)/$< > $(work_dir_isa)/$(*).signature.output 2> $(work_dir_isa)/$@; 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/grift/device/rv32imc/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= grift-sim 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) --arch=RV32GC \ 9 | --mem-dump-begin=begin_signature --mem-dump-end=end_signature \ 10 | --halt-pc=grift_stop_addr \ 11 | $(work_dir_isa)/$< > $(work_dir_isa)/$(*).signature.output 2> $(work_dir_isa)/$@; 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/grift/device/rv64i/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= grift-sim 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) --arch=RV64I \ 9 | --mem-dump-begin=begin_signature --mem-dump-end=end_signature \ 10 | --halt-pc=grift_stop_addr \ 11 | $(work_dir_isa)/$< > $(work_dir_isa)/$(*).signature.output 2> $(work_dir_isa)/$@; 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/grift/device/rv64im/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= grift-sim 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) --arch=RV64IM \ 9 | --mem-dump-begin=begin_signature --mem-dump-end=end_signature \ 10 | --halt-pc=grift_stop_addr \ 11 | $(work_dir_isa)/$< > $(work_dir_isa)/$(*).signature.output 2> $(work_dir_isa)/$@; 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/ibex/README.md: -------------------------------------------------------------------------------- 1 | # Running ibex as part of the framework 2 | # Instructions for building the target can be found in the lowRISC github repository 3 | # Once built the frameowrk can be run as follows 4 | 5 | # If the simulator executable is called Vibex_riscv_compliance 6 | # define this variable including the PATH 7 | export TARGET_SIM=/home/moore/git/lowRISCV/ibex/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance 8 | 9 | # define the CC prefix and target device 10 | export RISCV_PREFIX=riscv-none-embed- 11 | export RISCV_TARGET=ibex 12 | export RISCV_DEVICE=rv32imc 13 | 14 | # execute 15 | make clean 16 | make RISCV_ISA=rv32i 17 | make RISCV_ISA=rv32im 18 | make RISCV_ISA=rv32imc 19 | 20 | 21 | 22 | # 23 | # compare with golden 24 | # 25 | export RISCV_PREFIX=riscv-none-embed- 26 | export RISCV_DEVICE=ibex_rv32imc 27 | export RISCV_TARGET=golden 28 | make RISCV_ISA=rv32i 29 | -------------------------------------------------------------------------------- /riscv-target/ibex/device/rv32imc/handler.S: -------------------------------------------------------------------------------- 1 | .section .text.trap; 2 | .align 4; 3 | 4 | _trap_start: 5 | j _trap_exception 6 | j _int_exc 7 | j _int_exc 8 | j _int_exc 9 | j _int_exc 10 | j _int_exc 11 | j _int_exc 12 | j _int_exc 13 | j _int_exc 14 | j _int_exc 15 | j _int_exc 16 | j _int_exc 17 | j _int_exc 18 | 19 | 20 | // This could be exception or user interrupt 21 | // 0xb is the environment call to indicate the end 22 | _trap_exception: 23 | csrr a0, mcause; 24 | addi a1, zero, 0xb 25 | beq a0, a1, 1f 26 | la a1, begin_signature 27 | sw a0, 0(a1); 28 | 1: 29 | la a0, write_tohost; 30 | jr a0; 31 | 32 | _int_exc: 33 | la a0, write_tohost; 34 | jr a0; 35 | 36 | -------------------------------------------------------------------------------- /riscv-target/ibex/device/rv32imc/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x00000000; 7 | .text.trap : { *(.text.trap) } 8 | 9 | . = 0x00000080; 10 | .text.init : { *(.text.init) } 11 | 12 | . = ALIGN(0x1000); 13 | .tohost : { *(.tohost) } 14 | 15 | . = ALIGN(0x1000); 16 | .text : { *(.text) } 17 | 18 | . = ALIGN(0x1000); 19 | .data : { *(.data) } 20 | .data.string : { *(.data.string)} 21 | .bss : { *(.bss) } 22 | _end = .; 23 | } 24 | 25 | -------------------------------------------------------------------------------- /riscv-target/ibex/device/rv32imc/platform.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Imperas Software Ltd 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http:#www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | mtime: 16 | implemented: False 17 | nmi: 18 | address: 0x800000FC # trap vec (mtvec base) + 0x7C 19 | reset: 20 | address: 0x80000080 # boot address + 0x80 21 | -------------------------------------------------------------------------------- /riscv-target/ri5cy/README.md: -------------------------------------------------------------------------------- 1 | # Running the compliance tests with RI5CY 2 | Build RI5CY's core testbench by navigating to `riscv/tb/core` and calling `make 3 | vsim-all` or if you prefer verilator `make verilate`. 4 | 5 | Set `TARGET_SIM` by providing the `vsim` executable and the work directory of 6 | the compiled model of RI5CY e.g. 7 | `export TARGET_SIM=vsim -work RI5CY_REPO/tb/core/work` 8 | or point `TARGET_SIM` to the compiled verilator testbench e.g. 9 | `export TARGET_SIM=RI5CY_REPO/tb/core/testbench_verilator` 10 | 11 | Now set the following variables: 12 | ``` 13 | export RISCV_PREFIX=riscv32-unknown-elf- 14 | export RISCV_TARGET=ri5cy 15 | export RISCV_DEVICE=rv32imc 16 | ``` 17 | 18 | You are now ready to run the tests. The following are supported: 19 | * `make RISCV_ISA=rv32i` 20 | * `make RISCV_ISA=rv32im` 21 | * `make RISCV_ISA=rv32imc` 22 | -------------------------------------------------------------------------------- /riscv-target/ri5cy/device/rv32imc/handler.S: -------------------------------------------------------------------------------- 1 | .section .text.trap; 2 | .align 4; 3 | 4 | _trap_start: 5 | j _trap_exception 6 | j _int_exc 7 | j _int_exc 8 | j _int_exc 9 | j _int_exc 10 | j _int_exc 11 | j _int_exc 12 | j _int_exc 13 | j _int_exc 14 | j _int_exc 15 | j _int_exc 16 | j _int_exc 17 | j _int_exc 18 | 19 | 20 | // This could be exception or user interrupt 21 | // 0xb is the environment call to indicate the end 22 | _trap_exception: 23 | csrr a0, mcause; 24 | addi a1, zero, 0xb 25 | beq a0, a1, 1f 26 | la a1, begin_signature 27 | sw a0, 0(a1); 28 | 1: 29 | la a0, write_tohost; 30 | jr a0; 31 | 32 | _int_exc: 33 | la a0, write_tohost; 34 | jr a0; 35 | 36 | -------------------------------------------------------------------------------- /riscv-target/ri5cy/device/rv32imc/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | 7 | . = 0x00000000; 8 | .text.trap : { *(.text.trap) } 9 | 10 | . = 0x00000080; 11 | .text.init : { *(.text.init) } 12 | 13 | . = ALIGN(0x1000); 14 | .tohost : { *(.tohost) } 15 | 16 | . = ALIGN(0x1000); 17 | .text : { *(.text) } 18 | _etext = .; 19 | 20 | . = ALIGN(0x1000); 21 | .data : { *(.data) } 22 | .data.string : { *(.data.string)} 23 | _edata = .; 24 | 25 | .bss : { *(.bss) } 26 | _end = .; 27 | 28 | } 29 | -------------------------------------------------------------------------------- /riscv-target/riscvOVPsim/README.md: -------------------------------------------------------------------------------- 1 | # Accessing riscvOVPsim 2 | 3 | As we create the RISCV.org compliance test suite, the Imperas developed _riscvOVPsim_ compliance simulator is included as part of this GitHub repository. For more information please contact info@ovpworld.org or info@imperas.com or visit http://www.imperas.com/riscv. 4 | 5 | For more information on riscvOVPsim look here: [riscv-ovpsim./README.md](../../riscv-ovpsim/README.md). 6 | -------------------------------------------------------------------------------- /riscv-target/rocket/device/rv32im/Makefile.include: -------------------------------------------------------------------------------- 1 | ../rv32i/Makefile.include -------------------------------------------------------------------------------- /riscv-target/rocket/device/rv32imc/Makefile.include: -------------------------------------------------------------------------------- 1 | ../rv32i/Makefile.include -------------------------------------------------------------------------------- /riscv-target/sail-riscv-c/device/rv32Zicsr/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) \ 9 | --test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>&2 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-c/device/rv32Zifencei/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) \ 9 | --test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>&2 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-c/device/rv32i/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) \ 9 | --test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>&2 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-c/device/rv32im/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) \ 9 | --test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>&2 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-c/device/rv32imc/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) \ 9 | --test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>&2 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-ocaml/device/rv32Zicsr/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_ocaml_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) -isa=rv32 \ 9 | -test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@; 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-ocaml/device/rv32Zifencei/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_ocaml_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) -isa=rv32 \ 9 | -test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@; 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-ocaml/device/rv32i/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_ocaml_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) -isa=rv32 \ 9 | -test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@; 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-ocaml/device/rv32im/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_ocaml_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) -isa=rv32 \ 9 | -test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@; 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sail-riscv-ocaml/device/rv32imc/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= riscv_ocaml_sim_RV32 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) -isa=rv32 \ 9 | -test-signature=$(work_dir_isa)/$(*).signature.output \ 10 | $(work_dir_isa)/$< 2> $(work_dir_isa)/$@; 11 | 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 16 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 17 | 18 | COMPILE_TARGET=\ 19 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ 20 | -I$(ROOTDIR)/riscv-test-env/ \ 21 | -I$(ROOTDIR)/riscv-test-env/p/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ 24 | -o $(work_dir_isa)/$$@; \ 25 | $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump 26 | -------------------------------------------------------------------------------- /riscv-target/sifive-formal/formalspec-env/p/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | .text.init : { *(.text.init) } 7 | . = ALIGN(0x1000); 8 | .tohost : { *(.tohost) } 9 | . = ALIGN(0x1000); 10 | .text : { *(.text) } 11 | . = ALIGN(0x1000); 12 | .data : { *(.data) } 13 | .data.string : { *(.data.string) } 14 | .bss : { *(.bss) } 15 | PROVIDE(read_signature = 0xffc00); 16 | _end = .; 17 | } 18 | 19 | -------------------------------------------------------------------------------- /riscv-target/spike/device/rv32Zicsr/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= spike 2 | TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) 3 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 4 | $(error Target simulator executable '$(TARGET_SIM)` not found) 5 | endif 6 | 7 | RUN_TARGET=\ 8 | $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \ 9 | +signature=$(*).signature.output \ 10 | $< 2> $@; \ 11 | cat $(*).signature.output | sed 's/.\{8\}/& /g' | \ 12 | awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \ 13 | mv temp $(*).signature.output; 14 | 15 | 16 | RISCV_PREFIX ?= riscv32-unknown-elf- 17 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 18 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 19 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 20 | 21 | COMPILE_TARGET=\ 22 | $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ 23 | -I$(ROOTDIR)/riscv-test-env/ \ 24 | -I$(ROOTDIR)/riscv-test-env/p/ \ 25 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 26 | -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \ 27 | -o $$@; \ 28 | $$(RISCV_OBJDUMP) -D $$@ > $$@.objdump 29 | -------------------------------------------------------------------------------- /riscv-test-env/p/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x00000000; 7 | .text.trap : { *(.text.trap) } 8 | 9 | . = 0x80000000; 10 | .text.init : { *(.text.init) } 11 | 12 | . = ALIGN(0x1000); 13 | .tohost : { *(.tohost) } 14 | . = ALIGN(0x1000); 15 | .text : { *(.text) } 16 | . = ALIGN(0x1000); 17 | .data : { *(.data) } 18 | .data.string : { *(.data.string)} 19 | .bss : { *(.bss) } 20 | _end = .; 21 | } 22 | 23 | -------------------------------------------------------------------------------- /riscv-test-env/pm/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | .data : { *(.data) } 14 | .bss : { *(.bss) } 15 | _end = .; 16 | } 17 | 18 | -------------------------------------------------------------------------------- /riscv-test-env/pm/riscv_test.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef _ENV_PHYSICAL_MULTI_CORE_H 4 | #define _ENV_PHYSICAL_MULTI_CORE_H 5 | 6 | #include "../p/riscv_test.h" 7 | 8 | #undef RISCV_MULTICORE_DISABLE 9 | #define RISCV_MULTICORE_DISABLE 10 | 11 | #endif 12 | -------------------------------------------------------------------------------- /riscv-test-env/pt/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | .data : { *(.data) } 14 | .bss : { *(.bss) } 15 | _end = .; 16 | } 17 | 18 | -------------------------------------------------------------------------------- /riscv-test-env/v/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | .data : { *(.data) } 14 | .bss : { *(.bss) } 15 | _end = .; 16 | } 17 | 18 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/Makefrag: -------------------------------------------------------------------------------- 1 | rv32mi_sc_tests = \ 2 | breakpoint \ 3 | ma_fetch \ 4 | ma_addr \ 5 | scall \ 6 | sbreak \ 7 | shamt \ 8 | csr \ 9 | mcsr \ 10 | illegal 11 | 12 | ifeq ($(RISCV_TARGET),riscvOVPsim) 13 | rv32mi_sc_tests := $(subst breakpoint,,$(rv32mi_sc_tests)) 14 | endif 15 | 16 | rv32mi_tests = $(addsuffix .elf, $(rv32mi_sc_tests)) 17 | 18 | target_tests += $(rv32mi_tests) 19 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/breakpoint.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | ffffffff 11 | 0000000a 12 | 0000000b 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/csr.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000003 4 | 00000003 5 | 00000002 6 | 00000006 7 | 00000002 8 | 0bad1dea 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/illegal.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffff 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/ma_addr.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/ma_fetch.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/mcsr.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000000 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/sbreak.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/scall.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000001 3 | 00000002 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/references/shamt.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00010000 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64mi/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64mi tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64mi_sc_tests = \ 6 | access \ 7 | breakpoint \ 8 | csr \ 9 | mcsr \ 10 | illegal \ 11 | ma_fetch \ 12 | ma_addr \ 13 | scall \ 14 | sbreak \ 15 | 16 | rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) 17 | 18 | spike_tests += $(rv64mi_p_tests) 19 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64mi/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/csr.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64mi/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/ma_fetch.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64mi/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/sbreak.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64mi/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/scall.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64si/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | ma_fetch \ 9 | scall \ 10 | wfi \ 11 | sbreak \ 12 | 13 | rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) 14 | 15 | spike_tests += $(rv64si_p_tests) 16 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/rv64si/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # wfi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test wait-for-interrupt instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64S 14 | RV_COMPLIANCE_CODE_BEGIN 15 | 16 | # Make sure wfi doesn't halt the hart, even if interrupts are disabled 17 | csrc sstatus, SSTATUS_SIE 18 | csrs sie, SIP_SSIP 19 | csrs sip, SIP_SSIP 20 | wfi 21 | 22 | RV_COMPLIANCE_HALT 23 | 24 | TEST_PASSFAIL 25 | 26 | RV_COMPLIANCE_CODE_END 27 | 28 | .data 29 | RVTEST_DATA_BEGIN 30 | 31 | TEST_DATA 32 | 33 | RVTEST_DATA_END 34 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/breakpoint.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/breakpoint.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/csr.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/illegal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/illegal.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/ma_addr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/ma_addr.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/ma_fetch.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/mcsr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/mcsr.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/sbreak.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32mi/src/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/scall.S" 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/Makefrag: -------------------------------------------------------------------------------- 1 | rv32si_sc_tests = \ 2 | csr \ 3 | ma_fetch \ 4 | scall \ 5 | sbreak \ 6 | wfi \ 7 | dirty 8 | 9 | # ma_fetch - needs signature and it says it failed.. 10 | 11 | rv32si_tests = $(addsuffix .elf, $(rv32si_sc_tests)) 12 | 13 | target_tests += $(rv32si_tests) 14 | 15 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/references/csr.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000003 4 | 00000003 5 | 00000002 6 | 00000006 7 | 00000002 8 | 0bad1dea 9 | 0bad0000 10 | 0badbeef 11 | ffffffff 12 | ffffffff 13 | 00000000 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/references/dirty.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffff 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/references/ma_fetch.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/references/sbreak.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/references/scall.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000001 3 | 00000002 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/references/wfi.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000001 3 | 00000002 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/rv64si/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | ma_fetch \ 9 | scall \ 10 | wfi \ 11 | sbreak \ 12 | 13 | rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) 14 | 15 | spike_tests += $(rv64si_p_tests) 16 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/rv64si/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # wfi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test wait-for-interrupt instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "compliance_test.h" 12 | #include "compliance_io.h" 13 | #include "aw_test_macros.h" 14 | 15 | 16 | RVTEST_RV64S 17 | RV_COMPLIANCE_CODE_BEGIN 18 | 19 | # Make sure wfi doesn't halt the hart, even if interrupts are disabled 20 | csrc sstatus, SSTATUS_SIE 21 | csrs sie, SIP_SSIP 22 | csrs sip, SIP_SSIP 23 | 24 | li TESTNUM, 1 25 | SWSIG(1, TESTNUM) 26 | wfi 27 | li TESTNUM, 2 28 | SWSIG(2, TESTNUM) 29 | 30 | RV_COMPLIANCE_HALT 31 | 32 | TEST_PASSFAIL 33 | 34 | RV_COMPLIANCE_CODE_END 35 | 36 | .data 37 | RV_COMPLIANCE_DATA_BEGIN 38 | test_res: 39 | .fill 40, 4, -1 40 | RV_COMPLIANCE_DATA_END 41 | 42 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | ma_fetch \ 9 | scall \ 10 | sbreak \ 11 | wfi \ 12 | 13 | rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) 14 | 15 | spike32_tests += $(rv32si_p_tests) 16 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/csr.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/dirty.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #undef SATP_MODE_SV39 8 | #define SATP_MODE_SV39 SATP_MODE_SV32 9 | 10 | #include "../rv64si/dirty.S" 11 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/ma_fetch.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/sbreak.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/scall.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32si/src/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/wfi.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/Makefrag: -------------------------------------------------------------------------------- 1 | rv32ua_sc_tests = \ 2 | amoadd_w \ 3 | amoand_w \ 4 | amomax_w \ 5 | amomin_w \ 6 | amominu_w \ 7 | amoxor_w \ 8 | amoswap_w \ 9 | lrsc \ 10 | amomaxu_w \ 11 | amoor_w 12 | 13 | # ToDo - investigate this test 14 | rv32ua_sc_tests := $(subst lrsc,,$(rv32ua_sc_tests)) 15 | 16 | rv32ua_tests = $(addsuffix .elf, $(rv32ua_sc_tests)) 17 | 18 | target_tests += $(rv32ua_tests) 19 | 20 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amoadd_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 7ffff800 5 | 7ffff800 6 | fffff800 7 | ffffffff 8 | ffffffff 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amoand_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 80000000 5 | 80000000 6 | 80000000 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amomax_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | fffff800 5 | 00000000 6 | 00000001 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amomaxu_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | fffff800 5 | 00000000 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amomin_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 80000000 5 | 00000000 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amominu_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 80000000 5 | 00000000 6 | 00000000 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amoor_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | fffff800 5 | fffff800 6 | fffff801 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amoswap_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | fffff800 5 | fffff800 6 | 80000000 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/amoxor_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 7ffff800 5 | 7ffff800 6 | bffff801 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/references/lrsc.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000001 5 | 00000000 6 | 00000001 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/rv64ua/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ua tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ua_sc_tests = \ 6 | amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ 7 | amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ 8 | lrsc \ 9 | 10 | rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) 11 | rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) 12 | 13 | spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests) 14 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ua tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ua_sc_tests = \ 6 | amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ 7 | lrsc \ 8 | 9 | rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) 10 | rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) 11 | 12 | spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests) 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amoadd_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoadd_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amoand_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoand_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amomax_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomax_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amomaxu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomaxu_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amomin_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomin_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amominu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amominu_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amoor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoor_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amoswap_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoswap_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/amoxor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoxor_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ua/src/lrsc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/lrsc.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uc/Makefrag: -------------------------------------------------------------------------------- 1 | rv32uc_sc_tests = \ 2 | rvc \ 3 | 4 | rv32uc_tests = $(addsuffix .elf, $(rv32uc_sc_tests)) 5 | 6 | target_tests += $(rv32uc_tests) 7 | 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uc/references/rvc.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 0000029b 4 | 00001630 5 | 00001424 6 | 00001224 7 | fedcba99 8 | ffffffff 9 | fffffff1 10 | fffffff0 11 | ffffffff 12 | ffffffe1 13 | 000fffe1 14 | ffffffff 15 | ffffffee 16 | 0000000e 17 | 00000012 18 | 00000016 19 | 00000004 20 | ffffffff 21 | ffffffff 22 | 00012340 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | fffffffe 38 | fffffffe 39 | ffffffff 40 | ffffffff 41 | fedcba99 42 | ffffffff 43 | 00000246 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uc/rv64uc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uc_sc_tests = \ 6 | rvc \ 7 | 8 | rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests)) 9 | rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests)) 10 | 11 | spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests) 12 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uc/src/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uc_sc_tests = \ 6 | rvc \ 7 | 8 | rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests)) 9 | rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests)) 10 | 11 | spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests) 12 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uc/src/rvc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uc/rvc.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/Makefrag: -------------------------------------------------------------------------------- 1 | rv32ud_sc_tests = \ 2 | fadd \ 3 | fdiv \ 4 | fclass \ 5 | fcmp \ 6 | fcvt \ 7 | fmadd \ 8 | fmin \ 9 | ldst \ 10 | recoding \ 11 | 12 | # fcvt_w fails to asm 13 | 14 | # TODO: use this line instead of the last of the previous once move and structural tests have been implemented 15 | # ldst move structural recoding \ 16 | 17 | rv32ud_tests = $(addsuffix .elf, $(rv32ud_sc_tests)) 18 | 19 | target_tests += $(rv32ud_tests) 20 | 21 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fadd.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fclass.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000002 5 | 00000004 6 | 00000008 7 | 00000010 8 | 00000020 9 | 00000040 10 | 00000080 11 | 00000100 12 | 00000200 13 | 0000000c 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fcmp.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fcvt.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fdiv.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | 00000010 18 | 00000011 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fmadd.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/fmin.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | ffffffff 20 | ffffffff 21 | 00000014 22 | 00000015 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 0000001e 32 | 0000001f 33 | 00000020 34 | 00000021 35 | 00000022 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/ldst.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/references/recoding.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000001 5 | 00000000 6 | 00000001 7 | 00000001 8 | 00000000 9 | ffffffff 10 | ffffffff 11 | 00000000 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | 00000001 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/rv64ud/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ud tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ud_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move structural recoding \ 8 | 9 | rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) 10 | rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) 11 | 12 | spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests) 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fadd.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fclass.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcmp.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcvt.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcvt_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fdiv.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fmadd.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fmin.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/move.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ud/src/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/recoding.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/Makefrag: -------------------------------------------------------------------------------- 1 | rv32uf_sc_tests = \ 2 | fadd \ 3 | fdiv \ 4 | fclass \ 5 | fcmp \ 6 | fcvt \ 7 | fcvt_w \ 8 | fmadd \ 9 | fmin \ 10 | ldst \ 11 | move \ 12 | recoding 13 | 14 | rv32uf_tests = $(addsuffix .elf, $(rv32uf_sc_tests)) 15 | 16 | target_tests += $(rv32uf_tests) 17 | 18 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fadd.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fclass.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000002 5 | 00000004 6 | 00000008 7 | 00000010 8 | 00000020 9 | 00000040 10 | 00000080 11 | 00000100 12 | 00000200 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fcmp.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fcvt.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fcvt_w.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | ffffffff 12 | ffffffff 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fdiv.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fmadd.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/fmin.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | ffffffff 20 | ffffffff 21 | 00000014 22 | 00000015 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 0000001e 32 | 0000001f 33 | 00000020 34 | 00000021 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/ldst.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 40000000 4 | bf800000 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/move.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000034 5 | 00000014 6 | 00000001 7 | 00000054 8 | 00000014 9 | 00000050 10 | ffffffff 11 | 12345678 12 | 92345678 13 | 12345678 14 | 92345678 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | 92345678 22 | 12345678 23 | 92345678 24 | 12345678 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 12345678 32 | 92345678 33 | 92345678 34 | 12345678 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/references/recoding.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000001 5 | 00000000 6 | 00000001 7 | 00000001 8 | 00000000 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/rv64uf/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uf tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uf_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) 10 | rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) 11 | 12 | spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/rv64uf/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RV_COMPLIANCE_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) 17 | TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RV_COMPLIANCE_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf800000 30 | .word 0x40000000 31 | .word 0x40400000 32 | .word 0xc0800000 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uf tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uf_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests)) 10 | rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests)) 11 | 12 | spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests) 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fadd.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fclass.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcmp.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt_w.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fdiv.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fmadd.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fmin.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/move.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32uf/src/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/recoding.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/Makefrag: -------------------------------------------------------------------------------- 1 | rv32ui_sc_tests = \ 2 | simple \ 3 | add addi \ 4 | and andi \ 5 | auipc \ 6 | beq bge bgeu blt bltu bne \ 7 | fence_i \ 8 | jal jalr \ 9 | lb lbu lh lhu lw \ 10 | lui \ 11 | or ori \ 12 | sb sh sw \ 13 | sll slli \ 14 | slt slti sltiu sltu \ 15 | sra srai \ 16 | srl srli \ 17 | sub \ 18 | xor xori 19 | 20 | rv32ui_tests = $(addsuffix .elf, $(rv32ui_sc_tests)) 21 | 22 | target_tests += $(rv32ui_tests) 23 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/add.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000002 5 | 0000000a 6 | ffff8000 7 | 80000000 8 | 7fff8000 9 | 00007fff 10 | 7fffffff 11 | 80007ffe 12 | 80007fff 13 | 7fff7fff 14 | ffffffff 15 | 00000000 16 | fffffffe 17 | 80000000 18 | 00000018 19 | 00000019 20 | 0000001a 21 | 00000018 22 | 00000019 23 | 0000001a 24 | 00000018 25 | 00000019 26 | 0000001a 27 | 00000018 28 | 00000019 29 | 0000001a 30 | 00000018 31 | 00000019 32 | 0000001a 33 | 00000018 34 | 00000019 35 | 0000001a 36 | 0000000f 37 | 00000020 38 | 00000000 39 | 00000000 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/addi.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000002 5 | 0000000a 6 | fffff800 7 | 80000000 8 | 7ffff800 9 | 000007ff 10 | 7fffffff 11 | 800007fe 12 | 800007ff 13 | 7ffff7ff 14 | ffffffff 15 | 00000000 16 | fffffffe 17 | 80000000 18 | 00000018 19 | 00000018 20 | 00000017 21 | 00000016 22 | 00000018 23 | 00000017 24 | 00000016 25 | 00000020 26 | 00000000 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/and.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 0f000f00 4 | 00f000f0 5 | 000f000f 6 | f000f000 7 | 0f000f00 8 | 00f000f0 9 | ff00ff00 10 | 0f000f00 11 | 00f000f0 12 | 000f000f 13 | 0f000f00 14 | 00f000f0 15 | 000f000f 16 | 0f000f00 17 | 00f000f0 18 | 000f000f 19 | 0f000f00 20 | 00f000f0 21 | 000f000f 22 | 0f000f00 23 | 00f000f0 24 | 000f000f 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/andi.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ff00ff00 4 | 000000f0 5 | 0000000f 6 | 00000000 7 | 00000000 8 | 00000700 9 | 000000f0 10 | f00ff00f 11 | 00000700 12 | 000000f0 13 | 0000000f 14 | 00000000 15 | 00000000 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/auipc.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00002710 4 | ffffd8f0 5 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/beq.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000003 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/bge.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000015 23 | 00000016 24 | 00000017 25 | 00000003 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/bgeu.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000015 23 | 00000016 24 | 00000017 25 | 00000003 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/blt.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000003 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/bltu.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000003 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/bne.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000002 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000003 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | 00000000 32 | 00000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/fence_i.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 000001bc 4 | 00000309 5 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/jal.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffff 4 | 00000003 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/jalr.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffff 4 | ffffffff 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000004 9 | ffffffff 10 | ffffffff 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/lb.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffff 4 | 00000000 5 | fffffff0 6 | 0000000f 7 | ffffffff 8 | 00000000 9 | fffffff0 10 | 0000000f 11 | ffffffff 12 | 00000000 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000002 20 | 00000002 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/lbu.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 000000ff 4 | 00000000 5 | 000000f0 6 | 0000000f 7 | 000000ff 8 | 00000000 9 | 000000f0 10 | 0000000f 11 | 000000ff 12 | 00000000 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000002 20 | 00000002 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/lh.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 000000ff 4 | ffffff00 5 | 00000ff0 6 | fffff00f 7 | 000000ff 8 | ffffff00 9 | 00000ff0 10 | fffff00f 11 | 000000ff 12 | ffffff00 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000002 20 | 00000002 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/lhu.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 000000ff 4 | 0000ff00 5 | 00000ff0 6 | 0000f00f 7 | 000000ff 8 | 0000ff00 9 | 00000ff0 10 | 0000f00f 11 | 000000ff 12 | 0000ff00 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000002 20 | 00000002 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/lui.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | fffff800 5 | 000007ff 6 | fffff800 7 | 00000000 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/lw.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00ff00ff 4 | ff00ff00 5 | 0ff00ff0 6 | f00ff00f 7 | 00ff00ff 8 | ff00ff00 9 | 0ff00ff0 10 | f00ff00f 11 | 00ff00ff 12 | ff00ff00 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000002 20 | 00000002 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/or.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ff0fff0f 4 | fff0fff0 5 | 0fff0fff 6 | f0fff0ff 7 | ff0fff0f 8 | ff0fff0f 9 | ff00ff00 10 | ff0fff0f 11 | fff0fff0 12 | 0fff0fff 13 | ff0fff0f 14 | fff0fff0 15 | 0fff0fff 16 | ff0fff0f 17 | fff0fff0 18 | 0fff0fff 19 | ff0fff0f 20 | fff0fff0 21 | 0fff0fff 22 | ff0fff0f 23 | fff0fff0 24 | 0fff0fff 25 | ff00ff00 26 | 00ff00ff 27 | 00000000 28 | 00000000 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/ori.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffff0f 4 | 0ff00ff0 5 | 00ff07ff 6 | f00ff0ff 7 | ff00fff0 8 | 0ff00ff0 9 | 00ff07ff 10 | f00ff0ff 11 | 0ff00ff0 12 | ffffffff 13 | f00ff0ff 14 | 000000f0 15 | 00000000 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sb.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffaa 4 | 00000000 5 | ffffefa0 6 | 0000000a 7 | ffffffaa 8 | 00000000 9 | ffffffa0 10 | 0000000a 11 | 00000078 12 | ffffff98 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000015 23 | 00000016 24 | 00000017 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sh.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 000000aa 4 | ffffaa00 5 | beef0aa0 6 | ffffa00a 7 | 000000aa 8 | ffffaa00 9 | 00000aa0 10 | ffffa00a 11 | 00005678 12 | 00003098 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000015 23 | 00000016 24 | 00000017 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/simple.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ffffffff 4 | ffffffff 5 | ffffffff 6 | ffffffff 7 | ffffffff 8 | ffffffff 9 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sll.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000002 5 | 00000080 6 | 00004000 7 | 80000000 8 | ffffffff 9 | fffffffe 10 | ffffff80 11 | ffffc000 12 | 80000000 13 | 21212121 14 | 42424242 15 | 90909080 16 | 48484000 17 | 80000000 18 | 21212121 19 | 42424242 20 | 90909080 21 | 48484000 22 | ffffffff 23 | 00000080 24 | 00004000 25 | 00000018 26 | 00000080 27 | 00004000 28 | 80000000 29 | 00000080 30 | 00004000 31 | 80000000 32 | 00000080 33 | 00004000 34 | 80000000 35 | 00000080 36 | 00004000 37 | 80000000 38 | 00000080 39 | 00004000 40 | 80000000 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/slli.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000001 4 | 00000002 5 | 00000080 6 | 00004000 7 | 80000000 8 | ffffffff 9 | fffffffe 10 | ffffff80 11 | ffffc000 12 | 80000000 13 | 21212121 14 | 42424242 15 | 90909080 16 | 48484000 17 | 80000000 18 | 00000080 19 | 00000080 20 | 00004000 21 | 80000000 22 | 00000080 23 | 00004000 24 | 80000000 25 | 00000000 26 | 00000000 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/slt.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000000 5 | 00000001 6 | 00000000 7 | 00000000 8 | 00000001 9 | 00000001 10 | 00000001 11 | 00000000 12 | 00000000 13 | 00000001 14 | 00000000 15 | 00000000 16 | 00000001 17 | 00000000 18 | 00000000 19 | 00000001 20 | 00000000 21 | 00000001 22 | 00000000 23 | 00000001 24 | 00000000 25 | 00000001 26 | 00000000 27 | 00000001 28 | 00000000 29 | 00000001 30 | 00000000 31 | 00000001 32 | 00000000 33 | 00000001 34 | 00000000 35 | 00000001 36 | 00000000 37 | 00000001 38 | 00000000 39 | 00000000 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/slti.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000000 5 | 00000001 6 | 00000000 7 | 00000000 8 | 00000001 9 | 00000001 10 | 00000001 11 | 00000000 12 | 00000000 13 | 00000001 14 | 00000000 15 | 00000000 16 | 00000001 17 | 00000000 18 | 00000001 19 | 00000000 20 | 00000001 21 | 00000000 22 | 00000001 23 | 00000000 24 | 00000001 25 | 00000000 26 | 00000000 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sltiu.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000000 5 | 00000001 6 | 00000000 7 | 00000001 8 | 00000000 9 | 00000001 10 | 00000001 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000001 15 | 00000001 16 | 00000000 17 | 00000000 18 | 00000001 19 | 00000000 20 | 00000001 21 | 00000000 22 | 00000001 23 | 00000000 24 | 00000001 25 | 00000001 26 | 00000000 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sltu.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000000 5 | 00000001 6 | 00000000 7 | 00000001 8 | 00000000 9 | 00000001 10 | 00000001 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000001 15 | 00000001 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000001 20 | 00000000 21 | 00000001 22 | 00000000 23 | 00000001 24 | 00000000 25 | 00000001 26 | 00000000 27 | 00000001 28 | 00000000 29 | 00000001 30 | 00000000 31 | 00000001 32 | 00000000 33 | 00000001 34 | 00000000 35 | 00000001 36 | 00000001 37 | 00000000 38 | 00000000 39 | 00000000 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sra.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | c0000000 5 | ff000000 6 | fffe0000 7 | ffffffff 8 | 7fffffff 9 | 3fffffff 10 | 00ffffff 11 | 0001ffff 12 | 00000000 13 | 81818181 14 | c0c0c0c0 15 | ff030303 16 | fffe0606 17 | ffffffff 18 | 81818181 19 | c0c0c0c0 20 | ff030303 21 | fffe0606 22 | ffffffff 23 | ff000000 24 | fffe0000 25 | 00000000 26 | ff000000 27 | fffe0000 28 | ffffffff 29 | ff000000 30 | fffe0000 31 | ffffffff 32 | ff000000 33 | fffe0000 34 | ffffffff 35 | ff000000 36 | fffe0000 37 | ffffffff 38 | ff000000 39 | fffe0000 40 | ffffffff 41 | 00000000 42 | 00000020 43 | 00000000 44 | 00000000 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/srai.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | c0000000 5 | ff000000 6 | fffe0000 7 | ffffffff 8 | 7fffffff 9 | 3fffffff 10 | 00ffffff 11 | 0001ffff 12 | 00000000 13 | 81818181 14 | c0c0c0c0 15 | ff030303 16 | fffe0606 17 | ffffffff 18 | ff000000 19 | ff000000 20 | fffe0000 21 | ffffffff 22 | ff000000 23 | fffe0000 24 | ffffffff 25 | 00000000 26 | 00000000 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/srl.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 40000000 5 | 01000000 6 | 00020000 7 | 00000001 8 | ffffffff 9 | 7fffffff 10 | 01ffffff 11 | 0003ffff 12 | 00000001 13 | 21212121 14 | 10909090 15 | 00424242 16 | 00008484 17 | 00000000 18 | 21212121 19 | 10909090 20 | 00424242 21 | 00008484 22 | 00000000 23 | 01000000 24 | 00020000 25 | 00000000 26 | 01000000 27 | 00020000 28 | 00000001 29 | 01000000 30 | 00020000 31 | 00000001 32 | 01000000 33 | 00020000 34 | 00000001 35 | 01000000 36 | 00020000 37 | 00000001 38 | 01000000 39 | 00020000 40 | 00000001 41 | 00000000 42 | 00000020 43 | 00000000 44 | 00000000 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | ffffffff 52 | ffffffff 53 | ffffffff 54 | ffffffff 55 | ffffffff 56 | ffffffff 57 | ffffffff 58 | ffffffff 59 | ffffffff 60 | ffffffff 61 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/srli.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 80000000 4 | 40000000 5 | 01000000 6 | 00020000 7 | 00000001 8 | ffffffff 9 | 7fffffff 10 | 01ffffff 11 | 0003ffff 12 | 00000001 13 | 21212121 14 | 10909090 15 | 00424242 16 | 00008484 17 | 00000000 18 | 01000000 19 | 01000000 20 | 00020000 21 | 00000001 22 | 01000000 23 | 00020000 24 | 00000001 25 | 00000000 26 | 00000000 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sub.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00000000 4 | 00000000 5 | fffffffc 6 | 00008000 7 | 80000000 8 | 80008000 9 | ffff8001 10 | 7fffffff 11 | 7fff8000 12 | 7fff8001 13 | 80007fff 14 | 00000001 15 | fffffffe 16 | 00000000 17 | 00000002 18 | 00000003 19 | 00000000 20 | 00000002 21 | 00000003 22 | 00000004 23 | 00000002 24 | 00000003 25 | 00000004 26 | 00000002 27 | 00000003 28 | 00000004 29 | 00000002 30 | 00000003 31 | 00000004 32 | 00000002 33 | 00000003 34 | 00000004 35 | 0000000f 36 | 00000020 37 | 00000000 38 | 00000000 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/sw.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | 00aa00aa 4 | aa00aa00 5 | 0aa00aa0 6 | a00aa00a 7 | 00aa00aa 8 | aa00aa00 9 | 0aa00aa0 10 | a00aa00a 11 | 12345678 12 | 58213098 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000015 23 | 00000016 24 | 00000017 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/xor.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | f00ff00f 4 | ff00ff00 5 | 0ff00ff0 6 | 00ff00ff 7 | f00ff00f 8 | f00ff00f 9 | 00000000 10 | f00ff00f 11 | ff00ff00 12 | 0ff00ff0 13 | f00ff00f 14 | ff00ff00 15 | 0ff00ff0 16 | f00ff00f 17 | ff00ff00 18 | 0ff00ff0 19 | f00ff00f 20 | ff00ff00 21 | 0ff00ff0 22 | f00ff00f 23 | ff00ff00 24 | 0ff00ff0 25 | ff00ff00 26 | 00ff00ff 27 | 00000000 28 | 00000000 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/references/xori.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | ffffffff 3 | ff00f00f 4 | 0ff00f00 5 | 00ff0ff0 6 | f00ff0ff 7 | ff00f00f 8 | 0ff00f00 9 | 00ff0ff0 10 | f00ff0ff 11 | 0ff00f00 12 | 00ff0ff0 13 | f00ff0ff 14 | 000000f0 15 | 00000000 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/rv64ui/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ui tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ui_sc_tests = \ 6 | add addi addiw addw \ 7 | and andi \ 8 | auipc \ 9 | beq bge bgeu blt bltu bne \ 10 | simple \ 11 | fence_i \ 12 | jal jalr \ 13 | lb lbu lh lhu lw lwu ld \ 14 | lui \ 15 | or ori \ 16 | sb sh sw sd \ 17 | sll slli slliw sllw \ 18 | slt slti sltiu sltu \ 19 | sra srai sraiw sraw \ 20 | srl srli srliw srlw \ 21 | sub subw \ 22 | xor xori \ 23 | 24 | rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests)) 25 | rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests)) 26 | 27 | spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests) 28 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/rv64ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # auipc.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test auipc instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "compliance_test.h" 12 | #include "compliance_io.h" 13 | #include "aw_test_macros.h" 14 | 15 | RVTEST_RV64U 16 | RV_COMPLIANCE_CODE_BEGIN 17 | 18 | TEST_CASE(2, a0, 10000, \ 19 | .align 3; \ 20 | lla a0, 1f + 10000; \ 21 | jal a1, 1f; \ 22 | 1: sub a0, a0, a1; \ 23 | ) 24 | 25 | TEST_CASE(3, a0, -10000, \ 26 | .align 3; \ 27 | lla a0, 1f - 10000; \ 28 | jal a1, 1f; \ 29 | 1: sub a0, a0, a1; \ 30 | ) 31 | 32 | TEST_PASSFAIL 33 | 34 | RV_COMPLIANCE_CODE_END 35 | 36 | .data 37 | RV_COMPLIANCE_DATA_BEGIN 38 | test_res: 39 | .fill 4, 4, -1 40 | RV_COMPLIANCE_DATA_END 41 | 42 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/rv64ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # simple.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This is the most basic self checking test. If your simulator does not 8 | # pass thiss then there is little chance that it will pass any of the 9 | # more complicated self checking tests. 10 | # 11 | 12 | #include "riscv_test.h" 13 | #include "compliance_test.h" 14 | #include "compliance_io.h" 15 | #include "aw_test_macros.h" 16 | 17 | RVTEST_RV64U 18 | RV_COMPLIANCE_CODE_BEGIN 19 | 20 | RV_COMPLIANCE_HALT 21 | 22 | RV_COMPLIANCE_CODE_END 23 | 24 | 25 | .data 26 | 27 | RV_COMPLIANCE_DATA_BEGIN 28 | 29 | test_res: 30 | .fill 8, 4, -1 31 | 32 | RV_COMPLIANCE_DATA_END 33 | 34 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/Makefrag.spike: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ui tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ui_sc_tests = \ 6 | simple \ 7 | add addi \ 8 | and andi \ 9 | auipc \ 10 | beq bge bgeu blt bltu bne \ 11 | fence_i \ 12 | jal jalr \ 13 | lb lbu lh lhu lw \ 14 | lui \ 15 | or ori \ 16 | sb sh sw \ 17 | sll slli \ 18 | slt slti sltiu sltu \ 19 | sra srai \ 20 | srl srli \ 21 | sub \ 22 | xor xori \ 23 | 24 | rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) 25 | rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests)) 26 | 27 | spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests) 28 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/add.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/add.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/addi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/addi.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/and.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/and.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/andi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/andi.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/auipc.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/beq.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/beq.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/bge.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bge.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/bgeu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bgeu.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/blt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/blt.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/bltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bltu.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/bne.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bne.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/fence_i.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/jal.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/jalr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/jalr.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/lb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lb.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/lbu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lbu.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/lh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lh.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/lhu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lhu.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lui.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/lw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lw.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/or.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/or.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/ori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/ori.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sb.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sh.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/simple.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sll.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sll.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/slli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slli.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/slt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slt.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/slti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slti.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sltiu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sltiu.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sltu.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sra.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sra.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/srai.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srai.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/srl.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srl.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/srli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srli.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sub.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sub.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/sw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sw.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/xor.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/xor.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/deprecated/rv32ui/src/xori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/xori.S" 8 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-test-suite/rv32Zicsr/.gitignore -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/references/I-CSRRC-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffffffe 3 | ffffffff 4 | 800f0000 5 | 7fffffff 6 | 00000000 7 | ffffffff 8 | fffffffe 9 | fffffffe 10 | 800f0000 11 | 000f0000 12 | 00000000 13 | edcba987 14 | ffffffff 15 | 00000000 16 | ffffffff 17 | ffffffff 18 | 00000000 19 | 42726e6f 20 | 00000000 21 | f7ff8818 22 | ffffffff 23 | 69c7ad8b 24 | 49c1a903 25 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/references/I-CSRRCI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffffffe 3 | ffffffff 4 | ffffffe0 5 | ffffffef 6 | fffffff0 7 | ffffffff 8 | ffffffff 9 | fffffffe 10 | fffffffe 11 | ffffffe0 12 | ffffffe0 13 | ffffffe0 14 | ffffffff 15 | 00000000 16 | 32165490 17 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/references/I-CSRRS-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 7ff0ffff 5 | 80000000 6 | ffffffff 7 | 00000000 8 | 00000001 9 | 00000001 10 | 7ff0ffff 11 | fff0ffff 12 | ffffffff 13 | 12345678 14 | 00000000 15 | 12345678 16 | 00000000 17 | 12345678 18 | 00000000 19 | 42726e6f 20 | 00000000 21 | f7ff8818 22 | 00000000 23 | 96385274 24 | b63e56fc 25 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/references/I-CSRRSI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 0000001f 5 | 00000010 6 | 0000000f 7 | 00000000 8 | 00000000 9 | 00000001 10 | 00000001 11 | 0000001f 12 | 0000001f 13 | 0000001f 14 | 00000000 15 | 3216549f 16 | 32165498 17 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/references/I-CSRRW-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | ffffffff 5 | 7fffffff 6 | 80000000 7 | 12345678 8 | 9abcdef0 9 | 12345678 10 | 9abcdef0 11 | 00000000 12 | 00000000 13 | 00000000 14 | 14725836 15 | 96385274 16 | 32165498 17 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zicsr/references/I-CSRRWI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000001 4 | 00000000 5 | 0000001f 6 | 0000000f 7 | 00000010 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zifencei/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-test-suite/rv32Zifencei/.gitignore -------------------------------------------------------------------------------- /riscv-test-suite/rv32Zifencei/references/I-FENCE.I-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000030 2 | 00000012 3 | 00000042 4 | 001101b3 5 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/riscv-test-suite/rv32i/.gitignore -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-ADD-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffff802 3 | ffffffff 4 | fffff5cb 5 | 80000000 6 | 00001a34 7 | 07654320 8 | 80000000 9 | 80000000 10 | 07654320 11 | 00001a34 12 | 80000000 13 | fffff5cb 14 | fffffffe 15 | fffff802 16 | 00000000 17 | ffffffff 18 | fffff802 19 | ffffffff 20 | fffff5cb 21 | 80000000 22 | 00001a34 23 | 07654320 24 | 80000000 25 | 80000000 26 | 07654320 27 | 00001a34 28 | 80000000 29 | fffff5cb 30 | fffffffe 31 | fffff802 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-ADDI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffff802 3 | ffffffff 4 | ffffffff 5 | fffff800 6 | 00000000 7 | 07653b21 8 | 80000000 9 | fffff801 10 | fffff7ff 11 | 00000a34 12 | 80000000 13 | fffff5cb 14 | fffffffe 15 | fffff802 16 | 00000000 17 | ffffffff 18 | fffff802 19 | ffffffff 20 | ffffffff 21 | fffff800 22 | 00000000 23 | 07653b21 24 | 80000000 25 | fffff801 26 | fffff7ff 27 | 00000a34 28 | 80000000 29 | fffff5cb 30 | fffffffe 31 | fffff802 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-AND-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 000005cc 5 | 00000000 6 | 00000000 7 | 07654321 8 | 00000001 9 | 00000001 10 | 07654321 11 | 00000000 12 | 00000000 13 | 000005cc 14 | ffffffff 15 | 00000001 16 | 00000000 17 | 00000000 18 | 00000001 19 | 00000000 20 | 000005cc 21 | 00000000 22 | 00000000 23 | 07654321 24 | 00000001 25 | 00000001 26 | 07654321 27 | 00000000 28 | 00000000 29 | 000005cc 30 | ffffffff 31 | 00000001 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-ANDI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000800 7 | 07654000 8 | 00000001 9 | 00000000 10 | fffff800 11 | 00001000 12 | 00000000 13 | 000005cc 14 | ffffffff 15 | 00000001 16 | 00000000 17 | 00000000 18 | 00000001 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000800 23 | 07654000 24 | 00000001 25 | 00000000 26 | fffff800 27 | 00001000 28 | 00000000 29 | 000005cc 30 | ffffffff 31 | 00000001 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 007ff000 4 | 00001000 5 | 01234000 6 | 80000000 7 | 01234000 8 | fffff000 9 | 00001000 10 | 7ffff000 11 | 54321000 12 | 00800000 13 | 00000000 14 | 007ff000 15 | 00000000 16 | 00001000 17 | 00000000 18 | 00000000 19 | 007ff000 20 | 00001000 21 | 01234000 22 | 80000000 23 | 01234000 24 | fffff000 25 | 00001000 26 | 7ffff000 27 | 54321000 28 | 00800000 29 | 00000000 30 | 007ff000 31 | 00000000 32 | 00001000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-BEQ-01.reference_output: -------------------------------------------------------------------------------- 1 | 000123ab 2 | 000123ab 3 | 000123ab 4 | 000123ab 5 | 000123ab 6 | 000123ab 7 | 000123ab 8 | 000123ab 9 | 000123ab 10 | 000123ab 11 | 000123ab 12 | 000123ab 13 | 000123ab 14 | 0000cccc 15 | 000123ab 16 | 0000cccc 17 | 000123ab 18 | 000123ab 19 | 000123ab 20 | 000123ab 21 | 000123ab 22 | 000123ab 23 | 000123ab 24 | 000123ab 25 | 000123ab 26 | 000123ab 27 | 000123ab 28 | 000123ab 29 | 000123ab 30 | 0000cccc 31 | 000123ab 32 | 0000cccc 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-BGE-01.reference_output: -------------------------------------------------------------------------------- 1 | 000123ab 2 | 0000cccc 3 | 0000cccc 4 | 0000cccc 5 | 0000cccc 6 | 000123ab 7 | 0000cccc 8 | 0000cccc 9 | 000123ab 10 | 000123ab 11 | 0000cccc 12 | 000123ab 13 | 000123ab 14 | 0000cccc 15 | 000123ab 16 | 0000cccc 17 | 000123ab 18 | 0000cccc 19 | 0000cccc 20 | 0000cccc 21 | 0000cccc 22 | 000123ab 23 | 0000cccc 24 | 0000cccc 25 | 000123ab 26 | 000123ab 27 | 0000cccc 28 | 000123ab 29 | 000123ab 30 | 0000cccc 31 | 000123ab 32 | 0000cccc 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-BGEU-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000cccc 2 | 000123ab 3 | 000123ab 4 | 000123ab 5 | 000123ab 6 | 000123ab 7 | 000123ab 8 | 0000cccc 9 | 000123ab 10 | 0000cccc 11 | 0000cccc 12 | 0000cccc 13 | 0000cccc 14 | 0000cccc 15 | 0000cccc 16 | 0000cccc 17 | 0000cccc 18 | 000123ab 19 | 000123ab 20 | 000123ab 21 | 000123ab 22 | 000123ab 23 | 000123ab 24 | 0000cccc 25 | 000123ab 26 | 0000cccc 27 | 0000cccc 28 | 0000cccc 29 | 0000cccc 30 | 0000cccc 31 | 0000cccc 32 | 0000cccc 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-BLT-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000cccc 2 | 000123ab 3 | 000123ab 4 | 000123ab 5 | 000123ab 6 | 0000cccc 7 | 000123ab 8 | 000123ab 9 | 0000cccc 10 | 0000cccc 11 | 000123ab 12 | 0000cccc 13 | 0000cccc 14 | 000123ab 15 | 0000cccc 16 | 000123ab 17 | 0000cccc 18 | 000123ab 19 | 000123ab 20 | 000123ab 21 | 000123ab 22 | 0000cccc 23 | 000123ab 24 | 000123ab 25 | 0000cccc 26 | 0000cccc 27 | 000123ab 28 | 0000cccc 29 | 0000cccc 30 | 000123ab 31 | 0000cccc 32 | 000123ab 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-BLTU-01.reference_output: -------------------------------------------------------------------------------- 1 | 000123ab 2 | 0000cccc 3 | 0000cccc 4 | 0000cccc 5 | 0000cccc 6 | 0000cccc 7 | 0000cccc 8 | 000123ab 9 | 0000cccc 10 | 000123ab 11 | 000123ab 12 | 000123ab 13 | 000123ab 14 | 000123ab 15 | 000123ab 16 | 000123ab 17 | 000123ab 18 | 0000cccc 19 | 0000cccc 20 | 0000cccc 21 | 0000cccc 22 | 0000cccc 23 | 0000cccc 24 | 000123ab 25 | 0000cccc 26 | 000123ab 27 | 000123ab 28 | 000123ab 29 | 000123ab 30 | 000123ab 31 | 000123ab 32 | 000123ab 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-BNE-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000cccc 2 | 0000cccc 3 | 0000cccc 4 | 0000cccc 5 | 0000cccc 6 | 0000cccc 7 | 0000cccc 8 | 0000cccc 9 | 0000cccc 10 | 0000cccc 11 | 0000cccc 12 | 0000cccc 13 | 0000cccc 14 | 000123ab 15 | 0000cccc 16 | 000123ab 17 | 0000cccc 18 | 0000cccc 19 | 0000cccc 20 | 0000cccc 21 | 0000cccc 22 | 0000cccc 23 | 0000cccc 24 | 0000cccc 25 | 0000cccc 26 | 0000cccc 27 | 0000cccc 28 | 0000cccc 29 | 0000cccc 30 | 000123ab 31 | 0000cccc 32 | 000123ab 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-DELAY_SLOTS-01.reference_output: -------------------------------------------------------------------------------- 1 | 11111111 2 | 22222222 3 | 33333333 4 | 44444444 5 | 55555555 6 | 66666666 7 | 77777777 8 | 88888888 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-EBREAK-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000003 2 | 11111111 3 | 00000000 4 | 00000000 5 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-ECALL-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000000b 2 | 11111111 3 | 00000000 4 | 00000000 5 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-ENDIANESS-01.reference_output: -------------------------------------------------------------------------------- 1 | 01234567 2 | 00004567 3 | 00000123 4 | 00000089 5 | 00000067 6 | 00000045 7 | 00000023 8 | 00000001 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-IO-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000001 4 | ffffffff 5 | 7fffffff 6 | 80000000 7 | 00000001 8 | 00000001 9 | 00000002 10 | 00000000 11 | 80000000 12 | 80000001 13 | ffffffff 14 | ffffffff 15 | 00000000 16 | fffffffe 17 | 7ffffffe 18 | 7fffffff 19 | 7fffffff 20 | 7fffffff 21 | 80000000 22 | 7ffffffe 23 | fffffffe 24 | ffffffff 25 | 80000000 26 | 80000000 27 | 80000001 28 | 7fffffff 29 | ffffffff 30 | 00000000 31 | 00000001 32 | 0000abcd 33 | 0000abce 34 | 0000abcf 35 | 0000abd0 36 | 0000abd1 37 | 0000abd2 38 | 0000abd3 39 | 00000000 40 | 00000000 41 | 00000000 42 | 36925814 43 | 36925814 44 | 36925814 45 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-JAL-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 0000cccc 3 | 0000cccc 4 | 0000cccc 5 | 0000cccc 6 | 0000cccc 7 | 0000cccc 8 | 0000cccc 9 | 0000cccc 10 | 0000cccc 11 | 0000cccc 12 | 0000cccc 13 | 0000cccc 14 | 0000cccc 15 | 0000cccc 16 | 0000cccc 17 | 0000cccc 18 | 0000cccc 19 | 0000cccc 20 | 0000cccc 21 | 0000cccc 22 | 0000cccc 23 | 0000cccc 24 | 0000cccc 25 | 0000cccc 26 | 0000cccc 27 | 0000cccc 28 | 0000cccc 29 | 0000cccc 30 | 0000cccc 31 | 0000cccc 32 | 0000cccc 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-JALR-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000cccc 2 | 0000cccc 3 | 0000cccc 4 | 0000cccc 5 | 0000cccc 6 | 0000cccc 7 | 0000cccc 8 | 0000cccc 9 | 0000cccc 10 | 0000cccc 11 | 0000cccc 12 | 0000cccc 13 | 0000cccc 14 | 0000cccc 15 | 0000cccc 16 | 0000cccc 17 | 0000cccc 18 | 0000cccc 19 | 0000cccc 20 | 0000cccc 21 | 0000cccc 22 | 0000cccc 23 | 0000cccc 24 | 0000cccc 25 | 0000cccc 26 | 0000cccc 27 | 0000cccc 28 | 0000cccc 29 | 0000cccc 30 | 0000cccc 31 | 0000cccc 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-LB-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | ffffffbb 3 | ffffffdd 4 | 0000000c 5 | 0000000d 6 | fffffff0 7 | 0000000b 8 | 0000000e 9 | ffffffee 10 | ffffffbb 11 | ffffffdd 12 | 0000000c 13 | 0000000d 14 | fffffff0 15 | 0000000b 16 | 0000000e 17 | ffffffee 18 | ffffffbb 19 | ffffffdd 20 | 0000000c 21 | 0000000d 22 | fffffff0 23 | 0000000b 24 | 0000000e 25 | ffffffee 26 | ffffffbb 27 | ffffffdd 28 | 0000000c 29 | 0000000d 30 | fffffff0 31 | 0000000b 32 | 0000000e 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-LBU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 000000bb 3 | 000000dd 4 | 0000000c 5 | 0000000d 6 | 000000f0 7 | 0000000b 8 | 0000000e 9 | 000000ee 10 | 000000bb 11 | 000000dd 12 | 0000000c 13 | 0000000d 14 | 000000f0 15 | 0000000b 16 | 0000000e 17 | 000000ee 18 | 000000bb 19 | 000000dd 20 | 0000000c 21 | 0000000d 22 | 000000f0 23 | 0000000b 24 | 0000000e 25 | 000000ee 26 | 000000bb 27 | 000000dd 28 | 0000000c 29 | 0000000d 30 | 000000f0 31 | 0000000b 32 | 0000000e 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-LH-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000bbb 3 | ffffdd0d 4 | ffffcc0c 5 | ffffdd0d 6 | 000000f0 7 | 00000eee 8 | 00000eee 9 | 00000eee 10 | 00000bbb 11 | ffffdd0d 12 | ffffcc0c 13 | ffffdd0d 14 | 000000f0 15 | 00000eee 16 | 00000eee 17 | 00000eee 18 | 00000bbb 19 | ffffdd0d 20 | ffffcc0c 21 | ffffdd0d 22 | 000000f0 23 | 00000eee 24 | 00000eee 25 | 00000eee 26 | 00000bbb 27 | ffffdd0d 28 | ffffcc0c 29 | ffffdd0d 30 | 000000f0 31 | 00000eee 32 | 00000eee 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-LHU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000bbb 3 | 0000dd0d 4 | 0000cc0c 5 | 0000dd0d 6 | 000000f0 7 | 00000eee 8 | 00000eee 9 | 00000eee 10 | 00000bbb 11 | 0000dd0d 12 | 0000cc0c 13 | 0000dd0d 14 | 000000f0 15 | 00000eee 16 | 00000eee 17 | 00000eee 18 | 00000bbb 19 | 0000dd0d 20 | 0000cc0c 21 | 0000dd0d 22 | 000000f0 23 | 00000eee 24 | 00000eee 25 | 00000eee 26 | 00000bbb 27 | 0000dd0d 28 | 0000cc0c 29 | 0000dd0d 30 | 000000f0 31 | 00000eee 32 | 00000eee 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-LUI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 007ff000 4 | 00001000 5 | 01234000 6 | 80000000 7 | 01234000 8 | fffff000 9 | 00001000 10 | 7ffff000 11 | 54321000 12 | 00800000 13 | 00000000 14 | 007ff000 15 | 00000000 16 | 00001000 17 | 00000000 18 | 00000000 19 | 007ff000 20 | 00001000 21 | 01234000 22 | 80000000 23 | 01234000 24 | fffff000 25 | 00001000 26 | 7ffff000 27 | 54321000 28 | 00800000 29 | 00000000 30 | 007ff000 31 | 00000000 32 | 00001000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-LW-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | dd0d0eee 3 | dd0d0eee 4 | 0bbbcc0c 5 | dd0d0eee 6 | 0fff00f0 7 | dd0d0eee 8 | dd0d0eee 9 | dd0d0eee 10 | dd0d0eee 11 | dd0d0eee 12 | 0bbbcc0c 13 | dd0d0eee 14 | 0fff00f0 15 | dd0d0eee 16 | dd0d0eee 17 | dd0d0eee 18 | dd0d0eee 19 | dd0d0eee 20 | 0bbbcc0c 21 | dd0d0eee 22 | 0fff00f0 23 | dd0d0eee 24 | dd0d0eee 25 | dd0d0eee 26 | dd0d0eee 27 | dd0d0eee 28 | 0bbbcc0c 29 | dd0d0eee 30 | 0fff00f0 31 | dd0d0eee 32 | dd0d0eee 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-MISALIGN_JMP-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000002 2 | 00000000 3 | 11111111 4 | 22222222 5 | 33333333 6 | 44444444 7 | 00000002 8 | 00000000 9 | 55555555 10 | 00000002 11 | 00000000 12 | 66666666 13 | 00000002 14 | 00000000 15 | 77777777 16 | 00000002 17 | 00000000 18 | 88888888 19 | 00000002 20 | 00000000 21 | 99999999 22 | 00000002 23 | 00000000 24 | aaaaaaaa 25 | 00000002 26 | 00000000 27 | bbbbbbbb 28 | 00000002 29 | 00000000 30 | cccccccc 31 | 00000002 32 | 00000000 33 | dddddddd 34 | 00000002 35 | 00000000 36 | eeeeeeee 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-MISALIGN_LDST-01.reference_output: -------------------------------------------------------------------------------- 1 | 91a1b1c1 2 | 91a1b1c1 3 | 91a1b1c1 4 | 91a1b1c1 5 | 00000001 6 | 00000004 7 | 00000002 8 | 00000004 9 | 00000003 10 | 00000004 11 | fffff202 12 | fffff202 13 | ffffd2e2 14 | ffffd2e2 15 | 0000f202 16 | 0000f202 17 | 0000d2e2 18 | 0000d2e2 19 | 00000001 20 | 00000004 21 | 00000003 22 | 00000004 23 | 00000001 24 | 00000004 25 | 00000003 26 | 00000004 27 | 00000000 28 | 99999999 29 | 99999999 30 | 99999999 31 | 00000001 32 | 00000006 33 | 00000002 34 | 00000006 35 | 00000003 36 | 00000006 37 | 99990000 38 | 99999999 39 | 00009999 40 | 99999999 41 | 00000001 42 | 00000006 43 | 00000003 44 | 00000006 45 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-NOP-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000002 3 | 00000003 4 | 00000004 5 | 00000005 6 | 00000006 7 | 00000007 8 | 00000008 9 | 00000009 10 | 0000000a 11 | 0000000b 12 | 0000000c 13 | 0000000d 14 | 0000000e 15 | 0000000f 16 | 00000010 17 | 00000011 18 | 00000012 19 | 00000013 20 | 00000014 21 | 00000015 22 | 00000016 23 | 00000017 24 | 00000018 25 | 00000019 26 | 0000001a 27 | 0000001b 28 | 0000001c 29 | 0000001d 30 | 0000001e 31 | 0000001f 32 | 00000018 33 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-OR-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffff801 3 | ffffffff 4 | ffffefff 5 | 80000000 6 | 00001a34 7 | ffffffff 8 | 7fffffff 9 | 7fffffff 10 | ffffffff 11 | 00001a34 12 | 80000000 13 | ffffefff 14 | ffffffff 15 | fffff801 16 | 00000000 17 | ffffffff 18 | fffff801 19 | ffffffff 20 | ffffefff 21 | 80000000 22 | 00001a34 23 | ffffffff 24 | 7fffffff 25 | 7fffffff 26 | ffffffff 27 | 00001a34 28 | 80000000 29 | ffffefff 30 | ffffffff 31 | fffff801 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-ORI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffff801 3 | ffffffff 4 | ffffffff 5 | fffff800 6 | fffff800 7 | fffffb21 8 | 7fffffff 9 | fffff801 10 | ffffffff 11 | fffffa34 12 | 80000000 13 | ffffefff 14 | ffffffff 15 | fffff801 16 | 00000000 17 | ffffffff 18 | fffff801 19 | ffffffff 20 | ffffffff 21 | fffff800 22 | fffff800 23 | fffffb21 24 | 7fffffff 25 | fffff801 26 | ffffffff 27 | fffffa34 28 | 80000000 29 | ffffefff 30 | ffffffff 31 | fffff801 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-RF_size-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 56333249 3 | 2d562052 4 | 52697363 5 | 736b7920 6 | 73746572 7 | 6e204e6f 8 | 4d696c61 9 | 6f646173 10 | 6b794063 11 | 74657273 12 | 286e6f73 13 | 656b2048 14 | 20526164 15 | 6f6d292c 16 | 69702e63 17 | 636f6461 18 | 6a656b40 19 | 20286861 20 | 616a656b 21 | 61766520 22 | 2e204c65 23 | 636f6d29 24 | 7369702e 25 | 6620796f 26 | 67652069 27 | 65737361 28 | 7573206d 29 | 3a290d0a 30 | 68697320 31 | 61642074 32 | 75207265 33 | 00000000 34 | 56333249 35 | 2d562052 36 | 52697363 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-RF_width-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 80000000 3 | 80000000 4 | 80000000 5 | 80000000 6 | 80000000 7 | 80000000 8 | 80000000 9 | 80000000 10 | 80000000 11 | 80000000 12 | 80000000 13 | 80000000 14 | 80000000 15 | 80000000 16 | 80000000 17 | 80000000 18 | 80000000 19 | 80000000 20 | 80000000 21 | 80000000 22 | 80000000 23 | 80000000 24 | 80000000 25 | 80000000 26 | 80000000 27 | 80000000 28 | 80000000 29 | 80000000 30 | 80000000 31 | 80000000 32 | 80000000 33 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-RF_x0-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SB-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000ffff 2 | ffffffff 3 | ffffffff 4 | ffffffff 5 | 21ffffff 6 | ffffff01 7 | ffffff00 8 | ffffffff 9 | ffffffff 10 | 01ffff00 11 | 34ccffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ff01ffff 16 | 00ff0000 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | 21ffffff 21 | ff00ff01 22 | ffffff00 23 | ffffffff 24 | ffffffff 25 | ffffff00 26 | 34ccffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | 01ffffff 31 | ffff00ff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SH-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000ffff 2 | ffffffff 3 | ffffffff 4 | ffffffff 5 | ffffffff 6 | ffff0001 7 | ffff0800 8 | ffffffff 9 | ffffffff 10 | ffff0000 11 | edccf801 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | 000107ff 16 | 00000000 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | 00000001 22 | ffff0800 23 | ffffffff 24 | ffffffff 25 | ffff0000 26 | edccffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffff0000 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SLL-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 00007ff0 5 | 00000000 6 | 00000000 7 | 43210000 8 | fffffffe 9 | 00000001 10 | ffffffff 11 | 00002468 12 | 00000000 13 | ffedcc00 14 | 80000000 15 | f8010000 16 | 00000000 17 | ffffffff 18 | 00000001 19 | 00000000 20 | 00007ff0 21 | 00000000 22 | 00000000 23 | 43210000 24 | fffffffe 25 | 00000001 26 | ffffffff 27 | 00002468 28 | 00000000 29 | ffedcc00 30 | 80000000 31 | f8010000 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SLLI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 00007ff0 5 | 00000000 6 | 00000000 7 | 43210000 8 | fffffffe 9 | 00000001 10 | ffffffff 11 | 00002468 12 | 00000000 13 | ffedcc00 14 | 80000000 15 | f8010000 16 | 00000000 17 | ffffffff 18 | 00000001 19 | 00000000 20 | 00007ff0 21 | 00000000 22 | 00000000 23 | 43210000 24 | fffffffe 25 | 00000001 26 | ffffffff 27 | 00002468 28 | 00000000 29 | ffedcc00 30 | 80000000 31 | f8010000 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SLT-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000001 7 | 00000000 8 | 00000000 9 | 00000001 10 | 00000001 11 | 00000000 12 | 00000001 13 | 00000001 14 | 00000000 15 | 00000001 16 | 00000000 17 | 00000001 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000001 23 | 00000000 24 | 00000000 25 | 00000001 26 | 00000001 27 | 00000000 28 | 00000001 29 | 00000001 30 | 00000000 31 | 00000001 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SLTI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000001 13 | 00000001 14 | 00000000 15 | 00000001 16 | 00000000 17 | 00000001 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000001 29 | 00000001 30 | 00000000 31 | 00000001 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000001 4 | 00000001 5 | 00000001 6 | 00000001 7 | 00000001 8 | 00000000 9 | 00000001 10 | 00000000 11 | 00000001 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000001 19 | 00000001 20 | 00000001 21 | 00000001 22 | 00000001 23 | 00000001 24 | 00000000 25 | 00000001 26 | 00000000 27 | 00000001 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SLTU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000001 4 | 00000001 5 | 00000001 6 | 00000001 7 | 00000001 8 | 00000000 9 | 00000001 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000001 19 | 00000001 20 | 00000001 21 | 00000001 22 | 00000001 23 | 00000001 24 | 00000000 25 | 00000001 26 | 00000000 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SRA-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 0000007f 5 | 00000000 6 | 00000000 7 | 00000765 8 | 3fffffff 9 | 00000001 10 | ffffffff 11 | 0000091a 12 | f8000000 13 | ffffffed 14 | ffffffff 15 | ffffffff 16 | 00000000 17 | ffffffff 18 | 00000001 19 | 00000000 20 | 0000007f 21 | 00000000 22 | 00000000 23 | 00000765 24 | 3fffffff 25 | 00000001 26 | ffffffff 27 | 0000091a 28 | f8000000 29 | ffffffed 30 | ffffffff 31 | ffffffff 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SRAI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 0000007f 5 | 00000000 6 | 00000000 7 | 00000765 8 | 3fffffff 9 | 00000001 10 | ffffffff 11 | 0000091a 12 | f8000000 13 | ffffffed 14 | ffffffff 15 | ffffffff 16 | 00000000 17 | ffffffff 18 | 00000001 19 | 00000000 20 | 0000007f 21 | 00000000 22 | 00000000 23 | 00000765 24 | 3fffffff 25 | 00000001 26 | ffffffff 27 | 0000091a 28 | f8000000 29 | ffffffed 30 | ffffffff 31 | ffffffff 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SRL-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 0000007f 5 | 00000000 6 | 00000000 7 | 00000765 8 | 3fffffff 9 | 00000001 10 | ffffffff 11 | 0000091a 12 | 08000000 13 | 00ffffed 14 | 00000001 15 | 0000ffff 16 | 00000000 17 | ffffffff 18 | 00000001 19 | 00000000 20 | 0000007f 21 | 00000000 22 | 00000000 23 | 00000765 24 | 3fffffff 25 | 00000001 26 | ffffffff 27 | 0000091a 28 | 08000000 29 | 00ffffed 30 | 00000001 31 | 0000ffff 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SRLI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000000 4 | 0000007f 5 | 00000000 6 | 00000000 7 | 00000765 8 | 3fffffff 9 | 00000001 10 | ffffffff 11 | 0000091a 12 | 08000000 13 | 00ffffed 14 | 00000001 15 | 0000ffff 16 | 00000000 17 | ffffffff 18 | 00000001 19 | 00000000 20 | 0000007f 21 | 00000000 22 | 00000000 23 | 00000765 24 | 3fffffff 25 | 00000001 26 | ffffffff 27 | 0000091a 28 | 08000000 29 | 00ffffed 30 | 00000001 31 | 0000ffff 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SUB-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000800 3 | 00000001 4 | 00001a33 5 | 80000000 6 | fffff5cc 7 | 07654322 8 | 7ffffffe 9 | 80000002 10 | f89abcde 11 | 00000a34 12 | 80000000 13 | ffffe5cd 14 | 00000000 15 | fffff800 16 | 00000000 17 | ffffffff 18 | 00000800 19 | 00000001 20 | 00001a33 21 | 80000000 22 | fffff5cc 23 | 07654322 24 | 7ffffffe 25 | 80000002 26 | f89abcde 27 | 00000a34 28 | 80000000 29 | ffffe5cd 30 | 00000000 31 | fffff800 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-SW-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff 2 | 00000001 3 | 00000000 4 | 000007ff 5 | 00000000 6 | 00000800 7 | 07654321 8 | 7fffffff 9 | 00000001 10 | ffffffff 11 | 00001234 12 | 80000000 13 | ffffedcc 14 | ffffffff 15 | fffff801 16 | fffffffe 17 | 00000000 18 | 00000001 19 | 00000000 20 | 000007ff 21 | 00000000 22 | 00000800 23 | 07654321 24 | 7fffffff 25 | 00000001 26 | ffffffff 27 | 00001234 28 | 80000000 29 | ffffedcc 30 | ffffffff 31 | fffff801 32 | fffffffe 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-XOR-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffff800 3 | ffffffff 4 | ffffea33 5 | 80000000 6 | 00001a34 7 | f89abcde 8 | 7ffffffe 9 | 7ffffffe 10 | f89abcde 11 | 00001a34 12 | 80000000 13 | ffffea33 14 | 00000000 15 | fffff800 16 | 00000000 17 | ffffffff 18 | fffff800 19 | ffffffff 20 | ffffea33 21 | 80000000 22 | 00001a34 23 | f89abcde 24 | 7ffffffe 25 | 7ffffffe 26 | f89abcde 27 | 00001a34 28 | 80000000 29 | ffffea33 30 | 00000000 31 | fffff800 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32i/references/I-XORI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | fffff800 3 | ffffffff 4 | ffffffff 5 | fffff800 6 | fffff000 7 | f89abb21 8 | 7ffffffe 9 | fffff801 10 | 000007ff 11 | ffffea34 12 | 80000000 13 | ffffea33 14 | 00000000 15 | fffff800 16 | 00000000 17 | ffffffff 18 | fffff800 19 | ffffffff 20 | ffffffff 21 | fffff800 22 | fffff000 23 | f89abb21 24 | 7ffffffe 25 | fffff801 26 | 000007ff 27 | ffffea34 28 | 80000000 29 | ffffea33 30 | 00000000 31 | fffff800 32 | 00000000 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | 00000000 37 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/DIV.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | ffffffff 7 | 00000001 8 | ffffffff 9 | 00000000 10 | 00000000 11 | ffffffff 12 | ffffffff 13 | 00000001 14 | 00000000 15 | 00000000 16 | ffffffff 17 | 7fffffff 18 | 80000001 19 | 00000001 20 | 00000000 21 | ffffffff 22 | 80000000 23 | 80000000 24 | ffffffff 25 | 00000001 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/DIVU.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | ffffffff 7 | 00000001 8 | 00000000 9 | 00000000 10 | 00000000 11 | ffffffff 12 | ffffffff 13 | 00000001 14 | 00000002 15 | 00000001 16 | ffffffff 17 | 7fffffff 18 | 00000000 19 | 00000001 20 | 00000000 21 | ffffffff 22 | 80000000 23 | 00000000 24 | 00000001 25 | 00000001 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/MUL.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000001 8 | ffffffff 9 | 7fffffff 10 | 80000000 11 | 00000000 12 | ffffffff 13 | 00000001 14 | 80000001 15 | 80000000 16 | 00000000 17 | 7fffffff 18 | 80000001 19 | 00000001 20 | 80000000 21 | 00000000 22 | 80000000 23 | 80000000 24 | 80000000 25 | 00000000 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/MULH.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | ffffffff 9 | 00000000 10 | ffffffff 11 | 00000000 12 | ffffffff 13 | 00000000 14 | ffffffff 15 | 00000000 16 | 00000000 17 | 00000000 18 | ffffffff 19 | 3fffffff 20 | c0000000 21 | 00000000 22 | ffffffff 23 | 00000000 24 | c0000000 25 | 40000000 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/MULHSU.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | 00000000 17 | 00000000 18 | 7ffffffe 19 | 3fffffff 20 | 3fffffff 21 | 00000000 22 | ffffffff 23 | 80000000 24 | c0000000 25 | c0000000 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/MULHU.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | fffffffe 14 | 7ffffffe 15 | 7fffffff 16 | 00000000 17 | 00000000 18 | 7ffffffe 19 | 3fffffff 20 | 3fffffff 21 | 00000000 22 | 00000000 23 | 7fffffff 24 | 3fffffff 25 | 40000000 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/REM.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000001 7 | 00000000 8 | 00000000 9 | 00000001 10 | 00000001 11 | ffffffff 12 | 00000000 13 | 00000000 14 | ffffffff 15 | ffffffff 16 | 7fffffff 17 | 00000000 18 | 00000000 19 | 00000000 20 | 7fffffff 21 | 80000000 22 | 00000000 23 | 00000000 24 | ffffffff 25 | 00000000 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32im/references/REMU.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000001 7 | 00000000 8 | 00000001 9 | 00000001 10 | 00000001 11 | ffffffff 12 | 00000000 13 | 00000000 14 | 00000001 15 | 7fffffff 16 | 7fffffff 17 | 00000000 18 | 7fffffff 19 | 00000000 20 | 7fffffff 21 | 80000000 22 | 00000000 23 | 80000000 24 | 00000001 25 | 00000000 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | ffffffff 38 | ffffffff 39 | ffffffff 40 | ffffffff 41 | ffffffff 42 | ffffffff 43 | ffffffff 44 | ffffffff 45 | ffffffff 46 | ffffffff 47 | ffffffff 48 | ffffffff 49 | ffffffff 50 | ffffffff 51 | 00000000 52 | 00000000 53 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-ADD.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000001 7 | 00000002 8 | 00000000 9 | 00008000 10 | 00008001 11 | ffffffff 12 | 00000000 13 | fffffffe 14 | 00007ffe 15 | 00007fff 16 | 00007fff 17 | 00008000 18 | 00007ffe 19 | 0000fffe 20 | 0000ffff 21 | 00008000 22 | 00008001 23 | 00007fff 24 | 0000ffff 25 | 00010000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-ADDI.reference_output: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000002 3 | 0000000f 4 | 00000010 5 | 0000001f 6 | 00000002 7 | 00000003 8 | 00000010 9 | 00000011 10 | 00000020 11 | 00000000 12 | 00000001 13 | 0000000e 14 | 0000000f 15 | 0000001e 16 | 00080000 17 | 00080001 18 | 0008000e 19 | 0008000f 20 | 0008001e 21 | 00080001 22 | 00080002 23 | 0008000f 24 | 00080010 25 | 0008001f 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-ADDI16SP.reference_output: -------------------------------------------------------------------------------- 1 | 00000010 2 | 00000030 3 | 00000070 4 | 00000260 5 | 00000060 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-ADDI4SPN.reference_output: -------------------------------------------------------------------------------- 1 | 00000004 2 | 00000008 3 | 0000000c 4 | 00000010 5 | 000003fc 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-AND.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000001 8 | 00000001 9 | 00000001 10 | 00000000 11 | 00000000 12 | 00000001 13 | ffffffff 14 | 00007fff 15 | 00008000 16 | 00000000 17 | 00000001 18 | 00007fff 19 | 00007fff 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00008000 24 | 00000000 25 | 00008000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-ANDI.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000001 8 | 00000000 9 | 00000001 10 | 00000001 11 | 00000000 12 | 00000001 13 | 00000010 14 | 0000001f 15 | ffffffe1 16 | 00000000 17 | 00000001 18 | 00000010 19 | 0000001f 20 | 0007ffe1 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 25 | 00080000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-BEQZ.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-BNEZ.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-J.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-JAL.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-JALR.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-JR.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-LI.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00000010 4 | 0000001f 5 | ffffffe1 6 | 00000000 7 | 00000001 8 | 00000010 9 | 0000001f 10 | ffffffe1 11 | 00000000 12 | 00000001 13 | 00000010 14 | 0000001f 15 | ffffffe1 16 | 00000000 17 | 00000001 18 | 00000010 19 | 0000001f 20 | ffffffe1 21 | 00000000 22 | 00000001 23 | 00000010 24 | 0000001f 25 | ffffffe1 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-LUI.reference_output: -------------------------------------------------------------------------------- 1 | 00001000 2 | 00002000 3 | 0000f000 4 | 0001f000 5 | fffff000 6 | 00001000 7 | 00002000 8 | 0000f000 9 | 0001f000 10 | fffff000 11 | 00001000 12 | 00002000 13 | 0000f000 14 | 0001f000 15 | fffff000 16 | 00001000 17 | 00002000 18 | 0000f000 19 | 0001f000 20 | fffff000 21 | 00001000 22 | 00002000 23 | 0000f000 24 | 0001f000 25 | fffff000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-LW.reference_output: -------------------------------------------------------------------------------- 1 | 11111111 2 | 22222222 3 | 33333333 4 | 44444444 5 | 55555555 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-LWSP.reference_output: -------------------------------------------------------------------------------- 1 | 11111111 2 | 22222222 3 | 33333333 4 | 44444444 5 | 55555555 6 | 00000000 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-MV.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000001 7 | 00000001 8 | 00000001 9 | 00000001 10 | 00000001 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | 00007fff 17 | 00007fff 18 | 00007fff 19 | 00007fff 20 | 00007fff 21 | 00008000 22 | 00008000 23 | 00008000 24 | 00008000 25 | 00008000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-OR.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000001 7 | 00000001 8 | ffffffff 9 | 00007fff 10 | 00008001 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | 00007fff 17 | 00007fff 18 | ffffffff 19 | 00007fff 20 | 0000ffff 21 | 00008000 22 | 00008001 23 | ffffffff 24 | 0000ffff 25 | 00008000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-SLLI.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000002 7 | 00000004 8 | 00008000 9 | 00010000 10 | 80000000 11 | fffffffe 12 | fffffffc 13 | ffff8000 14 | ffff0000 15 | 80000000 16 | 000ffffe 17 | 001ffffc 18 | ffff8000 19 | ffff0000 20 | 80000000 21 | 00100000 22 | 00200000 23 | 00000000 24 | 00000000 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-SRAI.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | 0003ffff 17 | 0001ffff 18 | 0000000f 19 | 00000007 20 | 00000000 21 | 00040000 22 | 00020000 23 | 00000010 24 | 00000008 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-SRLI.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 7fffffff 12 | 3fffffff 13 | 0001ffff 14 | 0000ffff 15 | 00000001 16 | 0003ffff 17 | 0001ffff 18 | 0000000f 19 | 00000007 20 | 00000000 21 | 00040000 22 | 00020000 23 | 00000010 24 | 00000008 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-SUB.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | ffffffff 7 | 00000000 8 | fffffffe 9 | 00007ffe 10 | 00007fff 11 | 00000001 12 | 00000002 13 | 00000000 14 | 00008000 15 | 00008001 16 | ffff8001 17 | ffff8002 18 | ffff8000 19 | 00000000 20 | 00000001 21 | ffff8000 22 | ffff8001 23 | ffff7fff 24 | ffffffff 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-SW.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000001 8 | ffffffff 9 | ffffffff 10 | 00007fff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | ffffffff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | 00008000 38 | 00000000 39 | 00000000 40 | 00000000 41 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-SWSP.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000000 7 | 00000001 8 | ffffffff 9 | ffffffff 10 | ffffffff 11 | ffffffff 12 | ffffffff 13 | ffffffff 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | ffffffff 18 | ffffffff 19 | ffffffff 20 | ffffffff 21 | ffffffff 22 | 00007fff 23 | ffffffff 24 | ffffffff 25 | ffffffff 26 | ffffffff 27 | ffffffff 28 | ffffffff 29 | ffffffff 30 | ffffffff 31 | ffffffff 32 | ffffffff 33 | ffffffff 34 | ffffffff 35 | ffffffff 36 | ffffffff 37 | 00008000 38 | 00000000 39 | 00000000 40 | 00000000 41 | -------------------------------------------------------------------------------- /riscv-test-suite/rv32imc/references/C-XOR.reference_output: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | ffffffff 4 | 00007fff 5 | 00008000 6 | 00000001 7 | 00000000 8 | fffffffe 9 | 00007ffe 10 | 00008001 11 | ffffffff 12 | fffffffe 13 | 00000000 14 | ffff8000 15 | ffff7fff 16 | 00007fff 17 | 00007ffe 18 | ffff8000 19 | 00000000 20 | 0000ffff 21 | 00008000 22 | 00008001 23 | ffff7fff 24 | 0000ffff 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | -------------------------------------------------------------------------------- /spec/TestFormatSpec.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/spec/TestFormatSpec.pdf -------------------------------------------------------------------------------- /spec/testpool.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lowRISC/riscv-compliance/5a978cfd444d5e640150d46703deda99057b2bbb/spec/testpool.jpg --------------------------------------------------------------------------------