├── .gitignore ├── LICENSE ├── README.md ├── doc ├── analog_sweep.png ├── block_diagram.odg ├── block_diagram.png ├── bnc_z0_sweep.png ├── falling_edge.png ├── first_sweep.png └── tdr_r0_pcb.jpg ├── gateware ├── README.md ├── dac.py ├── delay.py ├── spi.py ├── sweeps │ ├── 6002_ustrip_load_0.npy │ ├── 6002_ustrip_load_1.npy │ ├── 6002_ustrip_load_2.npy │ ├── 6002_ustrip_load_3.npy │ ├── 6002_ustrip_load_4.npy │ ├── 6002_ustrip_load_5.npy │ ├── 6002_ustrip_load_6.npy │ ├── 6002_ustrip_load_7.npy │ ├── 6002_ustrip_load_8.npy │ ├── 6002_ustrip_load_9.npy │ ├── NOTES │ ├── black_sma_0.npy │ ├── black_sma_1.npy │ ├── black_sma_2.npy │ ├── black_sma_3.npy │ ├── black_sma_4.npy │ ├── black_sma_5.npy │ ├── black_sma_6.npy │ ├── black_sma_7.npy │ ├── black_sma_8.npy │ ├── black_sma_9.npy │ ├── bnc_tee_25ohm_0.npy │ ├── bnc_tee_25ohm_1.npy │ ├── bnc_tee_25ohm_2.npy │ ├── bnc_tee_25ohm_3.npy │ ├── bnc_tee_25ohm_4.npy │ ├── bnc_tee_25ohm_5.npy │ ├── bnc_tee_25ohm_6.npy │ ├── bnc_tee_25ohm_7.npy │ ├── bnc_tee_25ohm_8.npy │ ├── bnc_tee_25ohm_9.npy │ ├── bnc_tee_50ohm_0.npy │ ├── bnc_tee_50ohm_1.npy │ ├── bnc_tee_50ohm_2.npy │ ├── bnc_tee_50ohm_3.npy │ ├── bnc_tee_50ohm_4.npy │ ├── bnc_tee_50ohm_5.npy │ ├── bnc_tee_50ohm_6.npy │ ├── bnc_tee_50ohm_7.npy │ ├── bnc_tee_50ohm_8.npy │ ├── bnc_tee_50ohm_9.npy │ ├── bnc_tee_open_0.npy │ ├── bnc_tee_open_1.npy │ ├── bnc_tee_open_2.npy │ ├── bnc_tee_open_3.npy │ ├── bnc_tee_open_4.npy │ ├── bnc_tee_open_5.npy │ ├── bnc_tee_open_6.npy │ ├── bnc_tee_open_7.npy │ ├── bnc_tee_open_8.npy │ ├── bnc_tee_open_9.npy │ ├── fr408_1mm_cpwg_load_0.npy │ ├── fr408_1mm_cpwg_load_1.npy │ ├── fr408_1mm_cpwg_load_2.npy │ ├── fr408_1mm_cpwg_load_3.npy │ ├── fr408_1mm_cpwg_load_4.npy │ ├── fr408_1mm_cpwg_load_5.npy │ ├── fr408_1mm_cpwg_load_6.npy │ ├── fr408_1mm_cpwg_load_7.npy │ ├── fr408_1mm_cpwg_load_8.npy │ ├── fr408_1mm_cpwg_load_9.npy │ ├── fr408_1mm_cpwg_open_0.npy │ ├── fr408_1mm_cpwg_open_1.npy │ ├── fr408_1mm_cpwg_open_2.npy │ ├── fr408_1mm_cpwg_open_3.npy │ ├── fr408_1mm_cpwg_open_4.npy │ ├── fr408_1mm_cpwg_open_5.npy │ ├── fr408_1mm_cpwg_open_6.npy │ ├── fr408_1mm_cpwg_open_7.npy │ ├── fr408_1mm_cpwg_open_8.npy │ ├── fr408_1mm_cpwg_open_9.npy │ ├── linx_sma_6002_ustrip_0.npy │ ├── linx_sma_6002_ustrip_1.npy │ ├── linx_sma_6002_ustrip_2.npy │ ├── linx_sma_6002_ustrip_3.npy │ ├── linx_sma_6002_ustrip_4.npy │ ├── linx_sma_6002_ustrip_5.npy │ ├── linx_sma_6002_ustrip_6.npy │ ├── linx_sma_6002_ustrip_7.npy │ ├── linx_sma_6002_ustrip_8.npy │ ├── linx_sma_6002_ustrip_9.npy │ ├── m_m_sma_open_0.npy │ ├── m_m_sma_open_1.npy │ ├── m_m_sma_open_2.npy │ ├── m_m_sma_open_3.npy │ ├── m_m_sma_open_4.npy │ ├── m_m_sma_open_5.npy │ ├── m_m_sma_open_6.npy │ ├── m_m_sma_open_7.npy │ ├── m_m_sma_open_8.npy │ ├── m_m_sma_open_9.npy │ ├── m_m_sma_short_0.npy │ ├── m_m_sma_short_1.npy │ ├── m_m_sma_short_2.npy │ ├── m_m_sma_short_3.npy │ ├── m_m_sma_short_4.npy │ ├── m_m_sma_short_5.npy │ ├── m_m_sma_short_6.npy │ ├── m_m_sma_short_7.npy │ ├── m_m_sma_short_8.npy │ ├── m_m_sma_short_9.npy │ ├── m_m_sma_thru_0.npy │ ├── m_m_sma_thru_1.npy │ ├── m_m_sma_thru_2.npy │ ├── m_m_sma_thru_3.npy │ ├── m_m_sma_thru_4.npy │ ├── m_m_sma_thru_5.npy │ ├── m_m_sma_thru_6.npy │ ├── m_m_sma_thru_7.npy │ ├── m_m_sma_thru_8.npy │ ├── m_m_sma_thru_9.npy │ ├── m_m_thru_load_0.npy │ ├── m_m_thru_load_1.npy │ ├── m_m_thru_load_2.npy │ ├── m_m_thru_load_3.npy │ ├── m_m_thru_load_4.npy │ ├── m_m_thru_load_5.npy │ ├── m_m_thru_load_6.npy │ ├── m_m_thru_load_7.npy │ ├── m_m_thru_load_8.npy │ ├── m_m_thru_load_9.npy │ ├── plot_sandbox.py │ ├── sbb_cpwg_load_0.npy │ ├── sbb_cpwg_load_1.npy │ ├── sbb_cpwg_load_2.npy │ ├── sbb_cpwg_load_3.npy │ ├── sbb_cpwg_load_4.npy │ ├── sbb_cpwg_load_5.npy │ ├── sbb_cpwg_load_6.npy │ ├── sbb_cpwg_load_7.npy │ ├── sbb_cpwg_load_8.npy │ ├── sbb_cpwg_load_9.npy │ ├── sbb_cpwg_open_0.npy │ ├── sbb_cpwg_open_1.npy │ ├── sbb_cpwg_open_2.npy │ ├── sbb_cpwg_open_3.npy │ ├── sbb_cpwg_open_4.npy │ ├── sbb_cpwg_open_5.npy │ ├── sbb_cpwg_open_6.npy │ ├── sbb_cpwg_open_7.npy │ ├── sbb_cpwg_open_8.npy │ ├── sbb_cpwg_open_9.npy │ ├── siw_load_0.npy │ ├── siw_load_1.npy │ ├── siw_load_2.npy │ ├── siw_load_3.npy │ ├── siw_load_4.npy │ ├── siw_load_5.npy │ ├── siw_load_6.npy │ ├── siw_load_7.npy │ ├── siw_load_8.npy │ ├── siw_load_9.npy │ ├── siw_open_0.npy │ ├── siw_open_1.npy │ ├── siw_open_2.npy │ ├── siw_open_3.npy │ ├── siw_open_4.npy │ ├── siw_open_5.npy │ ├── siw_open_6.npy │ ├── siw_open_7.npy │ ├── siw_open_8.npy │ ├── siw_open_9.npy │ ├── sma_to_ufl_0.npy │ ├── sma_to_ufl_1.npy │ ├── sma_to_ufl_2.npy │ ├── sma_to_ufl_3.npy │ ├── sma_to_ufl_4.npy │ ├── sma_to_ufl_5.npy │ ├── sma_to_ufl_6.npy │ ├── sma_to_ufl_7.npy │ ├── sma_to_ufl_8.npy │ ├── sma_to_ufl_9.npy │ ├── split_bad_port_0.npy │ ├── split_bad_port_1.npy │ ├── split_bad_port_2.npy │ ├── split_bad_port_3.npy │ ├── split_bad_port_4.npy │ ├── split_bad_port_5.npy │ ├── split_bad_port_6.npy │ ├── split_bad_port_7.npy │ ├── split_bad_port_8.npy │ ├── split_bad_port_9.npy │ ├── trl_0201_cap_load_0.npy │ ├── trl_0201_cap_load_1.npy │ ├── trl_0201_cap_load_2.npy │ ├── trl_0201_cap_load_3.npy │ ├── trl_0201_cap_load_4.npy │ ├── trl_0201_cap_load_5.npy │ ├── trl_0201_cap_load_6.npy │ ├── trl_0201_cap_load_7.npy │ ├── trl_0201_cap_load_8.npy │ ├── trl_0201_cap_load_9.npy │ ├── trl_0201_cap_open_0.npy │ ├── trl_0201_cap_open_1.npy │ ├── trl_0201_cap_open_2.npy │ ├── trl_0201_cap_open_3.npy │ ├── trl_0201_cap_open_4.npy │ ├── trl_0201_cap_open_5.npy │ ├── trl_0201_cap_open_6.npy │ ├── trl_0201_cap_open_7.npy │ ├── trl_0201_cap_open_8.npy │ ├── trl_0201_cap_open_9.npy │ ├── trl_shunt_bias_0.npy │ ├── trl_shunt_bias_1.npy │ ├── trl_shunt_bias_2.npy │ ├── trl_shunt_bias_3.npy │ ├── trl_shunt_bias_4.npy │ ├── trl_shunt_bias_5.npy │ ├── trl_shunt_bias_6.npy │ ├── trl_shunt_bias_7.npy │ ├── trl_shunt_bias_8.npy │ ├── trl_shunt_bias_9.npy │ ├── unconnected_0.npy │ ├── unconnected_1.npy │ ├── unconnected_2.npy │ ├── unconnected_3.npy │ ├── unconnected_4.npy │ ├── unconnected_5.npy │ ├── unconnected_6.npy │ ├── unconnected_7.npy │ ├── unconnected_8.npy │ ├── unconnected_9.npy │ ├── white_sma_open_0.npy │ ├── white_sma_open_1.npy │ ├── white_sma_open_2.npy │ ├── white_sma_open_3.npy │ ├── white_sma_open_4.npy │ ├── white_sma_open_5.npy │ ├── white_sma_open_6.npy │ ├── white_sma_open_7.npy │ ├── white_sma_open_8.npy │ └── white_sma_open_9.npy ├── tdr.py ├── tdr_dump.py └── uart.py ├── hardware ├── bom │ └── ibom.html ├── clock.sch ├── comparator.sch ├── conn_power.sch ├── dac.sch ├── delay.sch ├── fpga.sch ├── output_driver.sch ├── tdr-cache.lib ├── tdr.kicad_pcb ├── tdr.pro ├── tdr.sch ├── tdr_bom.ods └── trig_level_dac.sch ├── software ├── README.md ├── bbone_spi_bitbang.py ├── init_gpio.sh ├── mmap_gpio.py ├── plot.py └── tdr.py ├── tdr_r0_schematic.pdf └── test └── mdo3000_j3_digital.set /.gitignore: -------------------------------------------------------------------------------- 1 | # For PCBs designed using KiCad: http://www.kicad-pcb.org/ 2 | # Format documentation: http://kicad-pcb.org/help/file-formats/ 3 | 4 | # Temporary files 5 | *.000 6 | *.bak 7 | *.bck 8 | *.kicad_pcb-bak 9 | *~ 10 | _autosave-* 11 | *.tmp 12 | *-cache.lib 13 | *-rescue.lib 14 | *-save.pro 15 | *-save.kicad_pcb 16 | 17 | # Netlist files (exported from Eeschema) 18 | *.net 19 | 20 | # Autorouter files (exported from Pcbnew) 21 | *.dsn 22 | *.ses 23 | 24 | # Exported BOM files 25 | *.xml 26 | *.csv 27 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Jon Klein 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # tdr 2 | Prototype time domain reflectometer/sampling oscilloscope. 3 | 90 gigasamples/second equivalent time sampling with an actual sampling rate of 5 kilosamples/second. 4 | 5 | The input bandwidth is TBD, maybe 8 GHz? 6 | 7 | ![r0 block diagram](/doc/block_diagram.png) 8 | ![r0 pcb](/doc/tdr_r0_pcb.jpg) 9 | 10 | Following is sampling the falling edge of the TDR pulse, impedance of a BNC tee, and a 1.2 GHz sine wave with analog triggering. 11 | 12 | ![r0 sweep](/doc/falling_edge.png) 13 | ![r0 sweep](/doc/bnc_z0_sweep.png) 14 | ![r0 sweep](/doc/analog_sweep.png) 15 | 16 | -------------------------------------------------------------------------------- /doc/analog_sweep.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/analog_sweep.png -------------------------------------------------------------------------------- /doc/block_diagram.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/block_diagram.odg -------------------------------------------------------------------------------- /doc/block_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/block_diagram.png -------------------------------------------------------------------------------- /doc/bnc_z0_sweep.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/bnc_z0_sweep.png -------------------------------------------------------------------------------- /doc/falling_edge.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/falling_edge.png -------------------------------------------------------------------------------- /doc/first_sweep.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/first_sweep.png -------------------------------------------------------------------------------- /doc/tdr_r0_pcb.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/doc/tdr_r0_pcb.jpg -------------------------------------------------------------------------------- /gateware/README.md: -------------------------------------------------------------------------------- 1 | This folder contains an incomplete and under development port of the TDR control software to migen. 2 | -------------------------------------------------------------------------------- /gateware/dac.py: -------------------------------------------------------------------------------- 1 | # jon klein 2 | # tdr gateware 3 | 4 | # this is my first attempt at HDL in awhile and my first time using migen 5 | # copying from this is probably a bad idea 6 | 7 | # mit license 8 | 9 | from migen import * 10 | from migen.fhdl import verilog 11 | from spi import _SPI_TX_Master 12 | 13 | 14 | class DacController(Module): 15 | def __init__(self): 16 | # DAC7563SDSCR dual DAC 17 | # VoutA - cmp ref 18 | # VoutB - trig voltage 19 | # inputs 20 | self.dac_a = Signal(12) 21 | self.dac_b = Signal(12) 22 | 23 | 24 | self.load = Signal(1) 25 | 26 | # outputs 27 | self.dac_sdi = Signal(1) 28 | self.dac_cs = Signal(1) 29 | self.dac_sck = Signal(1) 30 | self.dac_clr = Signal(1) 31 | self.ready = Signal(1) 32 | 33 | # internal 34 | self.dac_ready = Signal(1) 35 | self.dac_load = Signal(1) 36 | self.dac_b_reg = Signal(12) 37 | self.dac_reg = Signal(24) 38 | 39 | self.startup_delay = Signal(10) 40 | 41 | # load dac over spi 42 | dac_spi = _SPI_TX_Master(24, rising_data = False) 43 | self.submodules += dac_spi 44 | self.comb += [ 45 | self.dac_cs.eq(dac_spi.cs), 46 | self.dac_sck.eq(dac_spi.sck), 47 | self.dac_sdi.eq(dac_spi.mosi), 48 | dac_spi.data_in.eq(self.dac_reg), 49 | dac_spi.load.eq(self.dac_load), 50 | self.dac_ready.eq(dac_spi.ready)] 51 | 52 | 53 | dacfsm = FSM(reset_state="STARTUP") 54 | self.submodules += dacfsm 55 | 56 | 57 | dacfsm.act("STARTUP", 58 | NextValue(self.startup_delay, 1000), 59 | NextState("INIT"), 60 | ) 61 | 62 | 63 | 64 | dacfsm.act("INIT", 65 | NextValue(self.dac_reg, Cat(0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1)), 66 | NextValue(self.startup_delay, self.startup_delay - 1), 67 | If(self.startup_delay == 0, 68 | NextState("INIT_LOAD"), 69 | ) 70 | # enabe internal ref, set dac gain to 2 71 | # [x x][1 1 1][x x x][x....x 1] enable internal ref 72 | ) 73 | 74 | dacfsm.act("INIT_LOAD", 75 | NextState("INIT_WAIT"), 76 | self.dac_load.eq(1) 77 | ) 78 | 79 | dacfsm.act("INIT_WAIT", 80 | If(self.dac_ready, 81 | NextState("WAIT_CMD"), 82 | ).Else( 83 | NextState("INIT_WAIT"), 84 | ) 85 | ) 86 | 87 | dacfsm.act("WAIT_CMD", 88 | self.ready.eq(1), 89 | If(self.load, 90 | NextState("LOAD_DACA"), 91 | NextValue(self.dac_b_reg, self.dac_b[::-1]), 92 | NextValue(self.dac_reg, Cat(0, 0, 0, 0, 0, 0, 0, 0, self.dac_a[::-1], 0, 0, 0, 0)) 93 | ).Else( 94 | NextState("WAIT_CMD") 95 | ) 96 | ) 97 | 98 | 99 | dacfsm.act("LOAD_DACA", 100 | If(self.dac_ready, 101 | NextState("WAIT_DACA"), 102 | self.dac_load.eq(1) 103 | ).Else( 104 | NextState("LOAD_DACA"), 105 | ) 106 | ) 107 | 108 | dacfsm.act("WAIT_DACA", 109 | If(self.dac_ready, 110 | NextState("LOAD_DACB"), 111 | # [x x][0 0 0][0 0 1][12 bits data, x, x, x, x] # update dac b 112 | NextValue(self.dac_reg, Cat(0, 0, 0, 0, 0, 0, 0, 1, self.dac_b_reg, 0, 0, 0, 0)) 113 | 114 | ).Else( 115 | NextState("WAIT_DACA"), 116 | ) 117 | ) 118 | 119 | dacfsm.act("LOAD_DACB", 120 | If(self.dac_ready, 121 | NextState("WAIT_DACB"), 122 | self.dac_load.eq(1) 123 | ).Else( 124 | NextState("LOAD_DACB"), 125 | ) 126 | ) 127 | 128 | dacfsm.act("WAIT_DACB", 129 | If(self.dac_ready, 130 | NextState("WAIT_CMD"), 131 | ).Else( 132 | NextState("WAIT_DACB"), 133 | ) 134 | ) 135 | 136 | 137 | 138 | def dac_test(dut): 139 | for i in range(130): 140 | yield 141 | 142 | yield [dut.dac_a.eq(0x03), dut.dac_b.eq(0x777), dut.load.eq(1)] 143 | yield 144 | yield [dut.dac_a.eq(0x0), dut.dac_b.eq(0x0), dut.load.eq(0)] 145 | for i in range(130): 146 | yield 147 | 148 | if __name__ == '__main__': 149 | dac_dut = DacController() 150 | run_simulation(dac_dut, dac_test(dac_dut), vcd_name="dac.vcd") 151 | verilog.convert(DacController()).write("dac.v") 152 | 153 | -------------------------------------------------------------------------------- /gateware/delay.py: -------------------------------------------------------------------------------- 1 | # jon klein 2 | # tdr gateware 3 | 4 | # this is my first attempt at HDL in awhile and my first time using migen 5 | # copying from this is probably a bad idea 6 | 7 | # mit license 8 | 9 | from migen import * 10 | from migen.fhdl import verilog 11 | from spi import _SPI_TX_Master 12 | 13 | class DelayController(Module): 14 | def __init__(self): 15 | ''' controls an NB6L295MMNG digital delay 16 | accepts delay1 and delay2 parallel inputs 17 | on the rising edge of load, store delay1 and delay2 18 | then load delay with these values over spi ''' 19 | 20 | 21 | # outputs 22 | self.sck = Signal(1) 23 | self.en = Signal(1) # TODO: EN WORKS AS CHIP SELECT< ACTIVE HIGH.. 24 | self.sdin = Signal(1) 25 | self.sload = Signal(1) 26 | self.ready = Signal(1) 27 | 28 | # inputs 29 | self.delay1 = Signal(9) 30 | self.delay2 = Signal(9) 31 | self.load = Signal(1) 32 | 33 | # internal 34 | self.delay1_reg = Signal(9) 35 | self.delay2_reg = Signal(9) 36 | self.spi_data_reg = Signal(11) 37 | 38 | ''' Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by 39 | using the SCLK input pin and latching the data with the SLOAD input pin. The 11?bit SHIFT REGISTER shifts once per rising 40 | edge of the SCLK input. 41 | [psel][msel][d0]...[d8] 42 | psel, 0 to load pd0, 1 to load pd1 43 | msel, 0 to select dual paths, 1 to select extended delay path 44 | d0..d8, delay value 45 | ''' 46 | 47 | delay_spi = _SPI_TX_Master(11, rising_data = True) 48 | self.submodules += delay_spi 49 | 50 | 51 | self.comb += [ 52 | self.sck.eq(delay_spi.sck), 53 | self.sdin.eq(delay_spi.mosi)] 54 | 55 | delay_fsm = FSM(reset_state="INIT") 56 | self.submodules += delay_fsm 57 | 58 | # wait for load pulse 59 | delay_fsm.act("INIT", 60 | self.ready.eq(1), 61 | 62 | If(self.load, 63 | NextState("LOADA"), 64 | NextValue(self.delay1_reg, self.delay1), 65 | NextValue(self.delay2_reg, self.delay2) 66 | ), 67 | ) 68 | 69 | # load delay1 bits over spi 70 | delay_fsm.act("LOADA", 71 | self.en.eq(1), 72 | delay_spi.data_in.eq(Cat(0, 0, self.delay1_reg)), 73 | delay_spi.load.eq(1), 74 | NextState("WAITA"), 75 | ) 76 | 77 | delay_fsm.act("WAITA", 78 | self.ready.eq(0), 79 | self.en.eq(1), 80 | If(delay_spi.bit_count == 11, 81 | self.sload.eq(1) 82 | ).Else( 83 | self.sload.eq(0) 84 | ), 85 | 86 | If(delay_spi.ready, 87 | NextState("ENDA") 88 | ).Else( 89 | NextState("WAITA") 90 | ) 91 | ) 92 | 93 | delay_fsm.act("ENDA", 94 | self.ready.eq(0), 95 | self.en.eq(0), 96 | NextState("LOADB") 97 | ) 98 | 99 | 100 | 101 | # send delay2 bits over spi 102 | delay_fsm.act("LOADB", 103 | self.ready.eq(0), 104 | self.en.eq(1), 105 | delay_spi.data_in.eq(Cat(1, 0, self.delay2_reg)), 106 | delay_spi.load.eq(1), 107 | NextState("WAITB"), 108 | ) 109 | 110 | delay_fsm.act("WAITB", 111 | self.ready.eq(0), 112 | self.en.eq(1), 113 | If(delay_spi.bit_count == 11, 114 | self.sload.eq(1) 115 | ).Else( 116 | self.sload.eq(0) 117 | ), 118 | 119 | If(delay_spi.ready, 120 | NextState("END") 121 | ).Else( 122 | NextState("WAITB") 123 | ) 124 | ) 125 | 126 | delay_fsm.act("END", 127 | self.ready.eq(0), 128 | self.en.eq(1), 129 | NextState("INIT") 130 | ) 131 | 132 | 133 | 134 | 135 | def delay_test(dut): 136 | yield [dut.delay1.eq(0x03), dut.delay2.eq(0xff), dut.load.eq(0)] 137 | yield 138 | yield dut.load.eq(1) 139 | yield 140 | yield dut.load.eq(0) 141 | for i in range(190): 142 | yield 143 | 144 | yield [dut.delay1.eq(0xaa), dut.delay2.eq(0x77), dut.load.eq(0)] 145 | yield 146 | yield dut.load.eq(1) 147 | yield 148 | yield dut.load.eq(0) 149 | for i in range(190): 150 | yield 151 | 152 | 153 | 154 | if __name__ == '__main__': 155 | delay_dut = DelayController() 156 | run_simulation(delay_dut, delay_test(delay_dut), vcd_name="delay.vcd") 157 | verilog.convert(DelayController()).write("delay.v") 158 | -------------------------------------------------------------------------------- /gateware/spi.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | # so, NB6L295M latches data on the rising edge 5 | # DAC7563SDSCR latches data on the falling edge 6 | class _SPI_TX_Master(Module): 7 | def __init__(self, width, rising_data = False): 8 | # outputs 9 | self.sck = Signal() 10 | self.mosi = Signal() 11 | self.cs = Signal() 12 | self.ready = Signal() 13 | 14 | # inputs 15 | self.data_in = Signal(width) 16 | self.load = Signal() 17 | 18 | # internal 19 | self.data_reg = Signal(width) 20 | self.bit_count = Signal(5) 21 | 22 | 23 | 24 | # logic 25 | spifsm = FSM(reset_state="INIT") 26 | self.submodules += spifsm 27 | 28 | spifsm.act("INIT", 29 | self.cs.eq(1), 30 | self.sck.eq(0), 31 | self.ready.eq(1), 32 | NextValue(self.bit_count, 0), 33 | If(self.load, 34 | NextValue(self.data_reg, self.data_in), 35 | NextState("SETUP") 36 | ).Else( 37 | NextState("INIT") 38 | ) 39 | ) 40 | 41 | self.comb += self.mosi.eq(self.data_reg[0]) 42 | 43 | if not rising_data: 44 | spifsm.act("SETUP", 45 | self.cs.eq(0), 46 | self.sck.eq(1), 47 | NextState("DATA_CLKH") 48 | ) 49 | 50 | spifsm.act("DATA_CLKH", 51 | self.cs.eq(0), 52 | self.sck.eq(1), 53 | NextState("DATA_CLKL") 54 | ) 55 | 56 | spifsm.act("DATA_CLKL", 57 | self.cs.eq(0), 58 | self.sck.eq(0), 59 | NextValue(self.data_reg, self.data_reg >> 1), 60 | NextValue(self.bit_count, self.bit_count +1), 61 | If(self.bit_count != width - 1, 62 | NextState("DATA_CLKH") 63 | ).Else( 64 | NextState("POST") 65 | ) 66 | 67 | ) 68 | 69 | spifsm.act("POST", 70 | self.cs.eq(1), 71 | self.sck.eq(0), 72 | NextState("INIT") 73 | ) 74 | 75 | else: 76 | spifsm.act("SETUP", 77 | self.cs.eq(0), 78 | self.sck.eq(0), 79 | NextState("DATA_CLKH") 80 | ) 81 | 82 | spifsm.act("DATA_CLKH", 83 | self.cs.eq(0), 84 | self.sck.eq(1), 85 | NextValue(self.data_reg, self.data_reg >> 1), 86 | NextValue(self.bit_count, self.bit_count +1), 87 | If(self.bit_count != width - 1, 88 | NextState("DATA_CLKL") 89 | ).Else( 90 | NextState("POST") 91 | ) 92 | 93 | ) 94 | 95 | spifsm.act("DATA_CLKL", 96 | self.cs.eq(0), 97 | self.sck.eq(0), 98 | NextState("DATA_CLKH"), 99 | 100 | ) 101 | 102 | 103 | spifsm.act("POST", 104 | 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calc_voltage(sweep): 11 | return 4 * ((sweep[:-1] - 2048.)/4096) 12 | 13 | def read_sweep(prefix): 14 | files = glob.glob(prefix + '*.npy') 15 | sweep = np.zeros(NPOINTS) 16 | 17 | for filename in files: 18 | with open(filename) as f: 19 | sweep += calc_voltage(np.load(f)) 20 | return sweep / len(files) 21 | 22 | def cal_load(): 23 | return read_sweep('m_m_thru_load') 24 | 25 | if __name__ == '__main__': 26 | cal = cal_load() 27 | 28 | sweeps = ['bnc_tee_25ohm', 'bnc_tee_50ohm', 'bnc_tee_open'] 29 | 30 | for s in sweeps: 31 | sweep = read_sweep(s) - cal 32 | rho = sweep / v_fwd 33 | rho[rho > .99999] = .99999 34 | z0 = 50 * (1 + rho) / (1 - rho) 35 | d = 1000 * t * 3e8 / 2. 36 | plot(d[200:] - d[200], z0[200:]) 37 | ylim(0, 100) 38 | 39 | grid(True) 40 | legend(sweeps) 41 | title('BNC tee terminated terminated at zero, one, and two ports') 42 | xlabel('electrical length (mm)') 43 | ylabel('z (ohms)') 44 | #show() 45 | plt.savefig('sweep.png') 46 | pdb.set_trace() 47 | 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| # mit license 8 | 9 | from migen import * 10 | from migen.fhdl import verilog 11 | from migen.build.platforms import ice40_up5k_b_evn 12 | from migen.build.generic_platform import * 13 | 14 | import pins 15 | 16 | from spi import _SPI_TX_Master 17 | from delay import DelayController 18 | from uart import UartTx 19 | from dac import DacController 20 | 21 | 22 | 23 | #class RefSelect(Module): 24 | # def __init__(self): 25 | # # outputs 26 | # self.ref_sel = Signal(1) 27 | # self.trig_sel = Signal(2) 28 | # 29 | # # for now, hardcode for tdr mode with internal clock 30 | # self.comb += [self.ref_sel.eq(0)] # TODO: verify ref sel for internal clock 31 | # self.comb += [self.trig_sel.eq(0)] # TODO: verify ref sel for tdr 32 | 33 | def ref_test(dut): 34 | pass 35 | 36 | def tdr_test(dut): 37 | # let dac initialize 38 | for d in range(200): 39 | yield 40 | 41 | for analog_value in [100, 500, 900, 3100, 4000]: 42 | yield dut.start_sweep.eq(0) 43 | yield dut.start_sweep.eq(1) 44 | yield 45 | yield dut.start_sweep.eq(0) 46 | 47 | for d in range(7000): 48 | comp_val = dut.cmp_voltage < analog_value 49 | yield dut.comp_in.eq(comp_val) 50 | yield 51 | 52 | class TDRController(Module): 53 | def __init__(self, plat = None): 54 | simulation = (plat == None) 55 | 56 | DELAY_STEPS = 500 57 | DAC_SETTLE_CYCLES = int((12e6) * (10e-6)) 58 | DELAY_SETTLE_CYCLES = int((12e6) * (10e-6)) 59 | 60 | if not simulation: 61 | # external inputs 62 | self.comp_in = plat.request("comp_in", 0) 63 | 64 | # external outputs 65 | self.start_sweep = plat.request("start_sweep", 0) 66 | 67 | self.delay_sck = plat.request("delay_sck", 0) 68 | self.delay_en = plat.request("delay_en", 0) 69 | self.delay_sdin = plat.request("delay_sdin", 0) 70 | self.delay_sload = plat.request("delay_sload", 0) 71 | 72 | self.trig_sel0 = plat.request("trig_sel0", 0) 73 | self.trig_sel1 = plat.request("trig_sel1", 0) 74 | self.ref_sel = plat.request("ref_sel", 0) 75 | 76 | self.dac_clr = plat.request("dac_clr", 0) 77 | self.dac_cs = plat.request("dac_cs", 0) 78 | self.dac_sck = plat.request("dac_sck", 0) 79 | self.dac_sdi = plat.request("dac_sdi", 0) 80 | 81 | 82 | self.uart_tx = plat.request("uart_tx", 0) 83 | self.uart_rx = plat.request("uart_rx", 0) 84 | 85 | self.clk_in = plat.request("clk_in", 0) 86 | self.clk_out = plat.request("clk_out", 0) 87 | 88 | 89 | else: 90 | # external inputs 91 | self.comp_in = Signal() 92 | self.start_sweep = Signal() 93 | 94 | # external outputs 95 | self.delay_sck = Signal() 96 | self.delay_en = Signal() 97 | self.delay_sdin = Signal() 98 | self.delay_sload = Signal() 99 | 100 | self.trig_sel0 = Signal() 101 | self.trig_sel1 = Signal() 102 | self.ref_sel = Signal() 103 | 104 | self.dac_clr = Signal() 105 | self.dac_cs = Signal() 106 | self.dac_sck = Signal() 107 | self.dac_sdi = Signal() 108 | 109 | self.uart_tx = Signal() 110 | self.uart_rx = Signal() 111 | 112 | self.clk_in = Signal() 113 | self.clk_out = Signal() 114 | 115 | 116 | DELAY_STEPS = 3 117 | 118 | 119 | # internal signals 120 | delay_state = Signal(11) 121 | self.cmp_voltage = cmp_voltage = Signal(12) 122 | cmp_bit = Signal(5) 123 | settle_count = Signal(16) 124 | 125 | # ... 126 | self.comb += self.clk_out.eq(self.clk_in) 127 | 128 | # create dac controller 129 | dac_controller = DacController() 130 | self.submodules += dac_controller 131 | self.comb += [ 132 | self.dac_clr.eq(dac_controller.dac_clr), 133 | self.dac_cs.eq(dac_controller.dac_cs), 134 | self.dac_sck.eq(dac_controller.dac_sck), 135 | self.dac_sdi.eq(dac_controller.dac_sdi)] 136 | 137 | # create delay controller 138 | delay_controller = DelayController() 139 | self.submodules += delay_controller 140 | self.comb += [ 141 | self.delay_sck.eq(delay_controller.sck), 142 | self.delay_en.eq(delay_controller.en), 143 | self.delay_sdin.eq(delay_controller.sdin), 144 | self.delay_sload.eq(delay_controller.sload)] 145 | 146 | self.comb += delay_controller.delay2.eq(delay_state) 147 | self.comb += delay_controller.delay1.eq(0) 148 | 149 | # create ref select, assign to external pins 150 | #ref_select = RefSelect() 151 | #self.submodules += ref_select 152 | self.comb += [ 153 | self.ref_sel.eq(0), 154 | self.trig_sel0.eq(0), 155 | self.trig_sel1.eq(0)] 156 | 157 | # create uart tx 158 | uart_tx = UartTx(sim = simulation) 159 | self.submodules += uart_tx 160 | self.comb += [self.uart_tx.eq(uart_tx.tx)] 161 | 162 | # create fsm 163 | tdrfsm = FSM(reset_state="INIT") 164 | self.submodules += tdrfsm 165 | 166 | # INIT - wait for DAC to become ready 167 | tdrfsm.act("INIT", 168 | If(dac_controller.ready, 169 | NextState("WAIT_FOR_SWEEP"), 170 | ), 171 | ) 172 | 173 | tdrfsm.act("WAIT_FOR_SWEEP", 174 | self.start_sweep.eq(1), 175 | #NextState("START_SWEEP"), 176 | If(self.uart_rx == 0, 177 | NextState("START_SWEEP"), 178 | ), 179 | ) 180 | 181 | tdrfsm.act("START_SWEEP", 182 | NextState("SET_DELAY"), 183 | NextValue(delay_state, 0), 184 | NextValue(cmp_voltage, 2048), 185 | #NextValue(cmp_voltage, 0), 186 | NextValue(cmp_bit, 10) 187 | 188 | ) 189 | 190 | 191 | tdrfsm.act("SET_DELAY", 192 | # PROGRAM DELAY LINES 193 | NextState("WAIT_FOR_DELAY"), 194 | delay_controller.load.eq(1), 195 | NextValue(settle_count, DELAY_SETTLE_CYCLES), 196 | ) 197 | 198 | tdrfsm.act("WAIT_FOR_DELAY", 199 | # WAIT FOR DELAY LINES TO FINISH 200 | NextValue(settle_count, settle_count - 1), 201 | If(delay_controller.ready & (settle_count == 0), 202 | NextState("SET_VOLTAGE"), 203 | ), 204 | ) 205 | 206 | tdrfsm.act("SET_VOLTAGE", 207 | # SET VOLTAGE TO CMP_VOLTAGE 208 | dac_controller.dac_a.eq(0), 209 | dac_controller.dac_b.eq(cmp_voltage), 210 | dac_controller.load.eq(1), 211 | NextState("WAIT_FOR_VOLTAGE"), 212 | 213 | ) 214 | 215 | tdrfsm.act("WAIT_FOR_VOLTAGE", 216 | If(dac_controller.ready, 217 | NextState("SETTLE_VOLTAGE"), 218 | NextValue(settle_count, DAC_SETTLE_CYCLES), 219 | ), 220 | ) 221 | 222 | 223 | tdrfsm.act("SETTLE_VOLTAGE", 224 | If(settle_count == 0, 225 | NextState("MEASURE_VOLTAGE_BINARY"), 226 | ), 227 | NextValue(settle_count, settle_count - 1), 228 | ) 229 | 230 | tdrfsm.act("MEASURE_VOLTAGE_BINARY", 231 | If(self.comp_in, 232 | NextValue(cmp_voltage, cmp_voltage + (1 << cmp_bit)) 233 | ).Else( 234 | NextValue(cmp_voltage, cmp_voltage - (1 << cmp_bit)) 235 | 236 | ), 237 | 238 | 239 | NextValue(cmp_bit, cmp_bit -1), 240 | 241 | If(cmp_bit == 0, 242 | NextState("SEND_VOLTAGE_LSB"), 243 | ).Else( 244 | NextState("SET_VOLTAGE"), 245 | ), 246 | ) 247 | 248 | 249 | tdrfsm.act("MEASURE_VOLTAGE_BRUTE", 250 | If((self.comp_in == 0) | (cmp_voltage > 3800), 251 | NextState("SEND_VOLTAGE_LSB"), 252 | #NextValue(settle_count, 1000), 253 | ).Else( 254 | NextValue(cmp_voltage, cmp_voltage + 16), 255 | NextState("SET_VOLTAGE"), 256 | ) 257 | ) 258 | 259 | tdrfsm.act("SEND_VOLTAGE_LSB", 260 | If(uart_tx.ready, 261 | # send delay/voltage over uart 262 | uart_tx.load.eq(1), 263 | 264 | If(delay_state == DELAY_STEPS, 265 | uart_tx.data.eq(1), 266 | ).Else( 267 | uart_tx.data.eq(cmp_voltage & 0xFF), 268 | #uart_tx.data.eq(delay_state & 0xFF), 269 | ), 270 | 271 | NextState("SEND_VOLTAGE_MSB"), 272 | ) 273 | ) 274 | 275 | tdrfsm.act("SEND_VOLTAGE_MSB", 276 | If(uart_tx.ready, 277 | # send delay/voltage over uart 278 | uart_tx.load.eq(1), 279 | 280 | If(delay_state == DELAY_STEPS, 281 | uart_tx.data.eq(1), 282 | ).Else( 283 | uart_tx.data.eq(cmp_voltage[8:]), 284 | ), 285 | 286 | If(delay_state == DELAY_STEPS, 287 | NextState("WAIT_FOR_SWEEP"), 288 | # if this is the sample in the sweep, return to wait for sweep 289 | ).Else( 290 | NextState("SET_DELAY"), 291 | NextValue(delay_state, delay_state + 1), 292 | NextValue(cmp_voltage, 2048), 293 | #NextValue(cmp_voltage, 0), 294 | NextValue(cmp_bit, 10), 295 | # otherwise, increment delay counter, reprogram delay 296 | ) 297 | ) 298 | 299 | ) 300 | 301 | 302 | 303 | 304 | if __name__ == '__main__': 305 | 306 | #tdr_dut = TDRController() 307 | #run_simulation(tdr_dut, tdr_test(tdr_dut), vcd_name="tdr.vcd") 308 | #verilog.convert(TDRController()).write("tdr.v") 309 | 310 | plat = ice40_up5k_b_evn.Platform() 311 | plat.add_extension([ 312 | ("comp_in", 0, Pins("J3:14")), 313 | ("start_sweep", 0, Pins("J3:0")), 314 | ("delay_sck", 0, Pins("J3:1")), 315 | ("delay_en", 0, Pins("J3:2")), 316 | ("delay_sdin", 0, Pins("J3:3")), 317 | ("delay_sload", 0, Pins("J3:4")), 318 | ("trig_sel0", 0, Pins("J3:5")), 319 | ("trig_sel1", 0, Pins("J3:6")), 320 | ("ref_sel", 0, Pins("J3:7")), 321 | ("dac_clr", 0, Pins("J3:9")), 322 | ("dac_cs", 0, Pins("J3:10")), 323 | ("dac_sck", 0, Pins("J3:11")), 324 | ("dac_sdi", 0, Pins("J3:12")), 325 | ("uart_tx", 0, Pins("J3:13")), 326 | ("uart_rx", 0, Pins("J3:15")), 327 | ("clk_in", 0, Pins("J3:16")), 328 | ("clk_out", 0, Pins("J3:17")), 329 | 330 | ]) 331 | 332 | plat.build(TDRController(plat = plat)) 333 | plat.create_programmer().flash(0, 'build/top.bin') 334 | 335 | -------------------------------------------------------------------------------- /gateware/tdr_dump.py: -------------------------------------------------------------------------------- 1 | import serial 2 | from pylab import * 3 | import pdb 4 | import time 5 | 6 | N_DELAYS = 501 7 | 8 | 9 | file_prefix = raw_input("enter filename:") 10 | 11 | def grab_sweep(): 12 | with serial.Serial('/dev/ttyACM1', 460800, timeout = 10) as ser: 13 | ser.flush() 14 | tstart = time.time() 15 | ser.write(b'a') 16 | sweep = ser.read(N_DELAYS * 2) 17 | print("sweep length: {}".format(len(sweep))) 18 | tend = time.time() 19 | print("sweep time: {}".format(tend - tstart)) 20 | sweep = np.frombuffer(sweep, dtype=np.uint16) 21 | print(sweep) 22 | return sweep 23 | 24 | 25 | t = arange(N_DELAYS-1) * 11.2e-12 26 | for i in range(10): 27 | sweep = grab_sweep() 28 | with open("sweeps/{}_{}.npy".format(file_prefix, i), 'w') as f: 29 | np.save(f, sweep) 30 | sweep = 4 * ((sweep - 2048.)/4096) 31 | #plot(sweep[:-1], 'o') 32 | plot(t, sweep[:-1]) 33 | 34 | grid(True) 35 | title('falling edge of TDR pulse') 36 | ylabel('voltage (V)') 37 | xlabel('time (ns)') 38 | show() 39 | 40 | 41 | -------------------------------------------------------------------------------- /gateware/uart.py: -------------------------------------------------------------------------------- 1 | # jon klein 2 | # tdr gateware 3 | 4 | # this is my first attempt at HDL in awhile and my first time using migen 5 | # copying from this is probably a bad idea 6 | 7 | # mit license 8 | 9 | from migen import * 10 | from migen.fhdl import verilog 11 | 12 | 13 | class UartTx(Module): 14 | def __init__(self, sim = False): 15 | # inputs 16 | self.data = Signal(8) 17 | self.load = Signal(1) 18 | 19 | # outputs 20 | self.tx = Signal(1) 21 | self.ready = Signal(1) 22 | 23 | # internal 24 | self.tx_count = Signal(12) 25 | self.tx_clock = Signal(1) 26 | self.bitcount = Signal(4) 27 | self.tx_reg = Signal(8) 28 | 29 | fpga_clk = 10e6 30 | baudrate = 460800 31 | 32 | tx_divisor = int(fpga_clk / baudrate) 33 | if sim: 34 | tx_divisor = 3 35 | 36 | uartfsm = FSM(reset_state="INIT") 37 | self.submodules += uartfsm 38 | 39 | uartfsm.act("INIT", 40 | self.tx.eq(1), 41 | self.ready.eq(1), 42 | If(self.load, 43 | NextState("START"), 44 | NextValue(self.tx_count, tx_divisor), 45 | NextValue(self.tx_reg, self.data), 46 | ).Else( 47 | NextState("INIT") 48 | ) 49 | ) 50 | 51 | uartfsm.act("START", 52 | self.tx.eq(0), 53 | If(self.tx_count == 0, 54 | NextValue(self.tx_count, tx_divisor), 55 | NextValue(self.bitcount, 8), 56 | NextState("SENDBIT") 57 | ).Else( 58 | NextValue(self.tx_count, self.tx_count - 1), 59 | NextState("START") 60 | ) 61 | ) 62 | 63 | uartfsm.act("SENDBIT", 64 | self.tx.eq(self.tx_reg[0]), 65 | If(self.tx_count == 0, 66 | NextValue(self.tx_count, tx_divisor), 67 | NextValue(self.bitcount, self.bitcount - 1), 68 | NextValue(self.tx_reg, self.tx_reg >> 1), 69 | ).Else( 70 | NextValue(self.tx_count, self.tx_count - 1), 71 | ), 72 | 73 | If((self.bitcount == 0) and (self.tx_count == 0), 74 | NextState("ENDBIT") 75 | ).Else( 76 | NextState("SENDBIT") 77 | ) 78 | ) 79 | 80 | uartfsm.act("ENDBIT", 81 | self.tx.eq(1), 82 | If(self.tx_count == 0, 83 | NextState("INIT") 84 | ).Else( 85 | NextValue(self.tx_count, self.tx_count - 1), 86 | NextState("ENDBIT") 87 | ) 88 | ) 89 | 90 | 91 | 92 | def uart_test(dut): 93 | yield [dut.data.eq(0x33), dut.load.eq(0)] 94 | yield 95 | yield dut.load.eq(1) 96 | yield 97 | yield dut.load.eq(0) 98 | for i in range(120): 99 | yield 100 | 101 | if __name__ == '__main__': 102 | uart_dut = UartTx() 103 | run_simulation(uart_dut, uart_test(uart_dut), vcd_name="uart.vcd") 104 | verilog.convert(UartTx()).write("uart.v") 105 | -------------------------------------------------------------------------------- /hardware/comparator.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:tdr-cache 3 | EELAYER 26 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 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4550 3350 315 | Text HLabel 3250 3350 0 50 Input ~ 0 316 | REF_INPUT 317 | Text HLabel 4950 5750 3 50 Input ~ 0 318 | ~LATCH 319 | Text HLabel 5350 5750 3 50 Input ~ 0 320 | LATCH 321 | $Comp 322 | L tdr-rescue:SY89321L-synth_lib-tdr-rescue U402 323 | U 1 1 5BC3E45C 324 | P 8650 3300 325 | F 0 "U402" H 8650 3715 50 0000 C CNN 326 | F 1 "SY89321L" H 8650 3624 50 0000 C CNN 327 | F 2 "vna_footprints:DFN-8-1EP_2x2mm_Pitch0.5mm" H 8550 3300 50 0001 C CNN 328 | F 3 "" H 8550 3300 50 0001 C CNN 329 | 1 8650 3300 330 | 1 0 0 -1 331 | $EndComp 332 | $Comp 333 | L Device:R_Small R404 334 | U 1 1 5BC3F0C6 335 | P 7450 2950 336 | F 0 "R404" V 7350 3000 50 0000 L CNN 337 | F 1 "68" V 7350 2800 50 0000 L CNN 338 | F 2 "Resistors_SMD:R_0402" H 7450 2950 50 0001 C CNN 339 | F 3 "~" H 7450 2950 50 0001 C CNN 340 | 1 7450 2950 341 | 1 0 0 -1 342 | $EndComp 343 | $Comp 344 | L power:+3V3 #PWR0225 345 | U 1 1 5BC41D98 346 | P 9250 2700 347 | F 0 "#PWR0225" H 9250 2550 50 0001 C CNN 348 | F 1 "+3V3" H 9265 2873 50 0000 C CNN 349 | F 2 "" H 9250 2700 50 0001 C CNN 350 | F 3 "" H 9250 2700 50 0001 C CNN 351 | 1 9250 2700 352 | 1 0 0 -1 353 | $EndComp 354 | Wire Wire Line 355 | 9100 3150 9250 3150 356 | Text HLabel 9850 3250 2 50 Output ~ 0 357 | COMP_OUT 358 | Wire Wire Line 359 | 9100 3250 9850 3250 360 | $Comp 361 | L power:GND #PWR0226 362 | U 1 1 5BC43ABE 363 | P 9250 3500 364 | F 0 "#PWR0226" H 9250 3250 50 0001 C CNN 365 | F 1 "GND" V 9255 3372 50 0000 R CNN 366 | F 2 "" H 9250 3500 50 0001 C CNN 367 | F 3 "" H 9250 3500 50 0001 C CNN 368 | 1 9250 3500 369 | 1 0 0 -1 370 | $EndComp 371 | Wire Wire Line 372 | 9100 3450 9250 3450 373 | Wire Wire Line 374 | 9250 3450 9250 3500 375 | Wire Wire Line 376 | 9250 2700 9250 2750 377 | $Comp 378 | L Device:C_Small C405 379 | U 1 1 5BC45A33 380 | P 9400 2900 381 | F 0 "C405" H 9550 2950 50 0000 L CNN 382 | F 1 "10 nF" H 9550 2850 50 0000 L CNN 383 | F 2 "Capacitors_SMD:C_0402" H 9400 2900 50 0001 C CNN 384 | F 3 "~" H 9400 2900 50 0001 C CNN 385 | 1 9400 2900 386 | 1 0 0 -1 387 | $EndComp 388 | $Comp 389 | L power:GND #PWR0227 390 | U 1 1 5BC46600 391 | P 9400 3050 392 | F 0 "#PWR0227" H 9400 2800 50 0001 C CNN 393 | F 1 "GND" V 9405 2922 50 0001 R CNN 394 | F 2 "" H 9400 3050 50 0001 C CNN 395 | F 3 "" H 9400 3050 50 0001 C CNN 396 | 1 9400 3050 397 | 1 0 0 -1 398 | $EndComp 399 | Wire Wire Line 400 | 9250 2750 9400 2750 401 | Wire Wire Line 402 | 9400 2750 9400 2800 403 | Connection ~ 9250 2750 404 | Wire Wire Line 405 | 9250 2750 9250 3150 406 | Wire Wire Line 407 | 9400 3000 9400 3050 408 | $Comp 409 | L power:GND #PWR0228 410 | U 1 1 5BC47E75 411 | P 8650 3900 412 | F 0 "#PWR0228" H 8650 3650 50 0001 C CNN 413 | F 1 "GND" V 8655 3772 50 0000 R CNN 414 | F 2 "" H 8650 3900 50 0001 C CNN 415 | F 3 "" H 8650 3900 50 0001 C CNN 416 | 1 8650 3900 417 | 1 0 0 -1 418 | $EndComp 419 | Wire Wire Line 420 | 8650 3800 8650 3900 421 | $Comp 422 | L Device:C_Small C404 423 | U 1 1 5BC48B4A 424 | P 8050 3750 425 | F 0 "C404" H 8150 3800 50 0000 L CNN 426 | F 1 "DNP" H 8150 3700 50 0000 L CNN 427 | F 2 "Capacitors_SMD:C_0402" H 8050 3750 50 0001 C CNN 428 | F 3 "~" H 8050 3750 50 0001 C CNN 429 | 1 8050 3750 430 | 1 0 0 -1 431 | $EndComp 432 | Wire Wire Line 433 | 8050 3850 8050 3900 434 | Wire Wire Line 435 | 8200 3450 8050 3450 436 | Wire Wire Line 437 | 8050 3450 8050 3650 438 | $Comp 439 | L power:+3V3 #PWR0229 440 | U 1 1 5BC4B212 441 | P 8050 3900 442 | F 0 "#PWR0229" H 8050 3750 50 0001 C CNN 443 | F 1 "+3V3" H 8065 4073 50 0000 C CNN 444 | F 2 "" H 8050 3900 50 0001 C CNN 445 | F 3 "" H 8050 3900 50 0001 C CNN 446 | 1 8050 3900 447 | -1 0 0 1 448 | $EndComp 449 | Text Notes 2950 3150 0 50 ~ 0 450 | +/- 2V 451 | $Comp 452 | L Device:R_Small R405 453 | U 1 1 5C37AFC8 454 | P 4800 5000 455 | F 0 "R405" V 4700 4900 50 0000 L CNN 456 | F 1 "50" V 4900 4950 50 0000 L CNN 457 | F 2 "Resistors_SMD:R_0402" H 4800 5000 50 0001 C CNN 458 | F 3 "~" H 4800 5000 50 0001 C CNN 459 | 1 4800 5000 460 | 0 1 1 0 461 | $EndComp 462 | $Comp 463 | L Device:R_Small R406 464 | U 1 1 5C37B0A4 465 | P 5650 5000 466 | F 0 "R406" V 5750 4900 50 0000 L CNN 467 | F 1 "50" V 5550 4950 50 0000 L CNN 468 | F 2 "Resistors_SMD:R_0402" H 5650 5000 50 0001 C CNN 469 | F 3 "~" H 5650 5000 50 0001 C CNN 470 | 1 5650 5000 471 | 0 -1 -1 0 472 | $EndComp 473 | $Comp 474 | L Device:R_Small R407 475 | U 1 1 5C34FAEE 476 | P 5700 4300 477 | F 0 "R407" V 5800 4350 50 0000 L CNN 478 | F 1 "JMP" V 5800 4150 50 0000 L CNN 479 | F 2 "Resistors_SMD:R_0402" H 5700 4300 50 0001 C CNN 480 | F 3 "~" H 5700 4300 50 0001 C CNN 481 | 1 5700 4300 482 | 0 -1 -1 0 483 | $EndComp 484 | Wire Wire Line 485 | 5850 4300 5800 4300 486 | Wire Wire Line 487 | 5600 4300 5350 4300 488 | Wire Wire Line 489 | 5350 3950 5350 4300 490 | Wire Wire Line 491 | 5350 4300 5350 4500 492 | Wire Wire Line 493 | 5350 4500 5600 4500 494 | Connection ~ 5350 4300 495 | $Comp 496 | L Device:R_Small R408 497 | U 1 1 5C356819 498 | P 5700 4500 499 | F 0 "R408" V 5800 4550 50 0000 L CNN 500 | F 1 "DNI" V 5800 4350 50 0000 L CNN 501 | F 2 "Resistors_SMD:R_0402" H 5700 4500 50 0001 C CNN 502 | F 3 "~" H 5700 4500 50 0001 C CNN 503 | 1 5700 4500 504 | 0 -1 -1 0 505 | $EndComp 506 | $Comp 507 | L power:+3V3 #PWR0245 508 | U 1 1 5C356953 509 | P 5850 4500 510 | F 0 "#PWR0245" H 5850 4350 50 0001 C CNN 511 | F 1 "+3V3" V 5865 4628 50 0000 L CNN 512 | F 2 "" H 5850 4500 50 0001 C CNN 513 | F 3 "" H 5850 4500 50 0001 C CNN 514 | 1 5850 4500 515 | 0 1 1 0 516 | $EndComp 517 | Wire Wire Line 518 | 5850 4500 5800 4500 519 | $Comp 520 | L Device:C_Small C406 521 | U 1 1 5C36E21C 522 | P 6600 5200 523 | F 0 "C406" H 6200 5250 50 0000 L CNN 524 | F 1 "4.7 uF" H 6200 5150 50 0000 L CNN 525 | F 2 "Capacitors_SMD:C_0603" H 6600 5200 50 0001 C CNN 526 | F 3 "~" H 6600 5200 50 0001 C CNN 527 | 1 6600 5200 528 | 1 0 0 -1 529 | $EndComp 530 | $Comp 531 | L power:+3V3 #PWR0147 532 | U 1 1 5C36E2D5 533 | P 6600 5050 534 | F 0 "#PWR0147" H 6600 4900 50 0001 C CNN 535 | F 1 "+3V3" H 6615 5223 50 0000 C CNN 536 | F 2 "" H 6600 5050 50 0001 C CNN 537 | F 3 "" H 6600 5050 50 0001 C CNN 538 | 1 6600 5050 539 | 1 0 0 -1 540 | $EndComp 541 | Wire Wire Line 542 | 6600 5100 6600 5050 543 | $Comp 544 | L power:GND #PWR0148 545 | U 1 1 5C370836 546 | P 6600 5350 547 | F 0 "#PWR0148" H 6600 5100 50 0001 C CNN 548 | F 1 "GND" H 6605 5177 50 0000 C CNN 549 | F 2 "" H 6600 5350 50 0001 C CNN 550 | F 3 "" H 6600 5350 50 0001 C CNN 551 | 1 6600 5350 552 | 1 0 0 -1 553 | $EndComp 554 | Wire Wire Line 555 | 6600 5300 6600 5350 556 | $Comp 557 | L Device:R_Small R? 558 | U 1 1 5C6F135B 559 | P 7200 2950 560 | F 0 "R?" V 7100 3000 50 0000 L CNN 561 | F 1 "68" V 7100 2800 50 0000 L CNN 562 | F 2 "Resistors_SMD:R_0402" H 7200 2950 50 0001 C CNN 563 | F 3 "~" H 7200 2950 50 0001 C CNN 564 | 1 7200 2950 565 | 1 0 0 -1 566 | $EndComp 567 | Wire Wire Line 568 | 5850 3350 7450 3350 569 | Wire Wire Line 570 | 5850 3250 7200 3250 571 | $Comp 572 | L power:+3V3 #PWR? 573 | U 1 1 5C6F3BB4 574 | P 7200 2700 575 | F 0 "#PWR?" H 7200 2550 50 0001 C CNN 576 | F 1 "+3V3" H 7215 2873 50 0000 C CNN 577 | F 2 "" H 7200 2700 50 0001 C CNN 578 | F 3 "" H 7200 2700 50 0001 C CNN 579 | 1 7200 2700 580 | 1 0 0 -1 581 | $EndComp 582 | $Comp 583 | L power:+3V3 #PWR? 584 | U 1 1 5C6F3BE1 585 | P 7450 2700 586 | F 0 "#PWR?" H 7450 2550 50 0001 C CNN 587 | F 1 "+3V3" H 7465 2873 50 0000 C CNN 588 | F 2 "" H 7450 2700 50 0001 C CNN 589 | F 3 "" H 7450 2700 50 0001 C CNN 590 | 1 7450 2700 591 | 1 0 0 -1 592 | $EndComp 593 | Wire Wire Line 594 | 7450 2700 7450 2850 595 | Wire Wire Line 596 | 7200 2700 7200 2850 597 | Wire Wire Line 598 | 7200 3050 7200 3250 599 | Connection ~ 7200 3250 600 | Wire Wire Line 601 | 7200 3250 8200 3250 602 | Wire Wire Line 603 | 7450 3050 7450 3350 604 | Connection ~ 7450 3350 605 | Wire Wire Line 606 | 7450 3350 8200 3350 607 | Text Notes 6550 2400 0 50 ~ 0 608 | TODO: fix this termination... this probably isn't optimal 609 | $Comp 610 | L Device:C_Small C? 611 | U 1 1 5C7043F2 612 | P 4950 5250 613 | F 0 "C?" H 5042 5296 50 0000 L CNN 614 | F 1 "10 nF" H 5042 5205 50 0000 L CNN 615 | F 2 "Capacitors_SMD:C_0402" H 4950 5250 50 0001 C CNN 616 | F 3 "~" H 4950 5250 50 0001 C CNN 617 | 1 4950 5250 618 | 1 0 0 -1 619 | $EndComp 620 | $Comp 621 | L Device:C_Small C? 622 | U 1 1 5C70444C 623 | P 5350 5250 624 | F 0 "C?" H 5442 5296 50 0000 L CNN 625 | F 1 "10 nF" H 5442 5205 50 0000 L CNN 626 | F 2 "Capacitors_SMD:C_0402" H 5350 5250 50 0001 C CNN 627 | F 3 "~" H 5350 5250 50 0001 C CNN 628 | 1 5350 5250 629 | 1 0 0 -1 630 | $EndComp 631 | Text Notes 2100 5150 0 50 ~ 0 632 | TODO: clean up this termination, it probably isn't optimal.. 633 | Wire Wire Line 634 | 4900 5000 4950 5000 635 | Wire Wire Line 636 | 5150 3950 5150 4650 637 | Wire Wire Line 638 | 5350 5150 5350 5000 639 | Wire Wire Line 640 | 5350 5000 5550 5000 641 | Wire Wire Line 642 | 4950 5150 4950 5000 643 | $Comp 644 | L power:+3V3 #PWR? 645 | U 1 1 5C710F4A 646 | P 5800 5000 647 | F 0 "#PWR?" H 5800 4850 50 0001 C CNN 648 | F 1 "+3V3" V 5815 5128 50 0000 L CNN 649 | F 2 "" H 5800 5000 50 0001 C CNN 650 | F 3 "" H 5800 5000 50 0001 C CNN 651 | 1 5800 5000 652 | 0 1 1 0 653 | $EndComp 654 | Wire Wire Line 655 | 5800 5000 5750 5000 656 | $Comp 657 | L power:+3V3 #PWR? 658 | U 1 1 5C7126A3 659 | P 4600 5000 660 | F 0 "#PWR?" H 4600 4850 50 0001 C CNN 661 | F 1 "+3V3" V 4615 5128 50 0000 L CNN 662 | F 2 "" H 4600 5000 50 0001 C CNN 663 | F 3 "" H 4600 5000 50 0001 C CNN 664 | 1 4600 5000 665 | 0 -1 -1 0 666 | $EndComp 667 | Wire Wire Line 668 | 4600 5000 4700 5000 669 | Wire Wire Line 670 | 5350 5350 5350 5750 671 | Wire Wire Line 672 | 4950 5000 4950 4650 673 | Wire Wire Line 674 | 4950 4650 5150 4650 675 | Connection ~ 4950 5000 676 | Connection ~ 5350 5000 677 | Wire Wire Line 678 | 5350 5000 5350 4650 679 | Wire Wire Line 680 | 5350 4650 5250 4650 681 | Wire Wire Line 682 | 5250 4650 5250 3950 683 | Wire Wire Line 684 | 4950 5750 4950 5350 685 | $EndSCHEMATC 686 | -------------------------------------------------------------------------------- /hardware/output_driver.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:tdr-cache 3 | EELAYER 26 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 5 8 8 | Title "" 9 | Date "" 10 | Rev "" 11 | Comp "" 12 | Comment1 "" 13 | Comment2 "" 14 | Comment3 "" 15 | Comment4 "" 16 | $EndDescr 17 | $Comp 18 | L tdr-rescue:ADCMP580-synth_lib-tdr-rescue U? 19 | U 1 1 5BC2B59B 20 | P 5700 3350 21 | AR Path="/5BC41CC8/5BC2B59B" Ref="U?" Part="1" 22 | AR Path="/5BC2B41E/5BC2B59B" Ref="U501" Part="1" 23 | F 0 "U501" H 5000 3950 50 0000 L CNN 24 | F 1 "ADCMP580" H 5000 3850 50 0000 L CNN 25 | F 2 "Housings_DFN_QFN:QFN-16-1EP_3x3mm_Pitch0.5mm" H 4800 3850 50 0001 C CNN 26 | F 3 "" H 4800 3850 50 0001 C CNN 27 | 1 5700 3350 28 | 1 0 0 -1 29 | $EndComp 30 | $Comp 31 | L power:+5VA #PWR? 32 | U 1 1 5BC2B5A2 33 | P 5550 2150 34 | AR Path="/5BC41CC8/5BC2B5A2" Ref="#PWR?" Part="1" 35 | AR Path="/5BC2B41E/5BC2B5A2" Ref="#PWR0230" Part="1" 36 | F 0 "#PWR0230" H 5550 2000 50 0001 C CNN 37 | F 1 "+5VA" V 5550 2400 50 0000 C CNN 38 | F 2 "" H 5550 2150 50 0001 C CNN 39 | F 3 "" H 5550 2150 50 0001 C CNN 40 | 1 5550 2150 41 | 1 0 0 -1 42 | $EndComp 43 | $Comp 44 | L power:-5VA #PWR? 45 | U 1 1 5BC2B5A8 46 | P 5850 2150 47 | AR Path="/5BC41CC8/5BC2B5A8" Ref="#PWR?" Part="1" 48 | AR Path="/5BC2B41E/5BC2B5A8" Ref="#PWR0231" Part="1" 49 | F 0 "#PWR0231" H 5850 2250 50 0001 C CNN 50 | F 1 "-5VA" H 5865 2323 50 0000 C CNN 51 | F 2 "" H 5850 2150 50 0001 C CNN 52 | F 3 "" H 5850 2150 50 0001 C CNN 53 | 1 5850 2150 54 | 1 0 0 -1 55 | $EndComp 56 | $Comp 57 | L power:GND #PWR? 58 | U 1 1 5BC2B5AE 59 | P 5850 4050 60 | AR Path="/5BC41CC8/5BC2B5AE" Ref="#PWR?" Part="1" 61 | AR Path="/5BC2B41E/5BC2B5AE" Ref="#PWR0232" Part="1" 62 | F 0 "#PWR0232" H 5850 3800 50 0001 C CNN 63 | F 1 "GND" H 5855 3877 50 0000 C CNN 64 | F 2 "" H 5850 4050 50 0001 C CNN 65 | F 3 "" H 5850 4050 50 0001 C CNN 66 | 1 5850 4050 67 | 1 0 0 -1 68 | $EndComp 69 | Wire Wire Line 70 | 5850 4000 5850 4050 71 | $Comp 72 | L power:GND #PWR? 73 | U 1 1 5BC2B5B5 74 | P 5950 4050 75 | AR Path="/5BC41CC8/5BC2B5B5" Ref="#PWR?" Part="1" 76 | AR Path="/5BC2B41E/5BC2B5B5" Ref="#PWR0233" Part="1" 77 | F 0 "#PWR0233" H 5950 3800 50 0001 C CNN 78 | F 1 "GND" H 5955 3877 50 0000 C CNN 79 | F 2 "" H 5950 4050 50 0001 C CNN 80 | F 3 "" H 5950 4050 50 0001 C CNN 81 | 1 5950 4050 82 | 1 0 0 -1 83 | $EndComp 84 | Wire Wire Line 85 | 5950 4050 5950 4000 86 | $Comp 87 | L power:GND #PWR? 88 | U 1 1 5BC2B5BC 89 | P 6400 3500 90 | AR Path="/5BC41CC8/5BC2B5BC" Ref="#PWR?" Part="1" 91 | AR Path="/5BC2B41E/5BC2B5BC" Ref="#PWR0234" Part="1" 92 | F 0 "#PWR0234" H 6400 3250 50 0001 C CNN 93 | F 1 "GND" V 6405 3372 50 0000 R CNN 94 | F 2 "" H 6400 3500 50 0001 C CNN 95 | F 3 "" H 6400 3500 50 0001 C CNN 96 | 1 6400 3500 97 | 0 -1 -1 0 98 | $EndComp 99 | Wire Wire Line 100 | 6400 3500 6350 3500 101 | $Comp 102 | L power:GND #PWR? 103 | U 1 1 5BC2B5C3 104 | P 6400 3200 105 | AR Path="/5BC41CC8/5BC2B5C3" Ref="#PWR?" Part="1" 106 | AR Path="/5BC2B41E/5BC2B5C3" Ref="#PWR0235" Part="1" 107 | F 0 "#PWR0235" H 6400 2950 50 0001 C CNN 108 | F 1 "GND" V 6405 3072 50 0000 R CNN 109 | F 2 "" H 6400 3200 50 0001 C CNN 110 | F 3 "" H 6400 3200 50 0001 C CNN 111 | 1 6400 3200 112 | 0 -1 -1 0 113 | $EndComp 114 | Wire Wire Line 115 | 6400 3200 6350 3200 116 | $Comp 117 | L power:GND #PWR? 118 | U 1 1 5BC2B5CA 119 | P 5650 2650 120 | AR Path="/5BC41CC8/5BC2B5CA" Ref="#PWR?" Part="1" 121 | AR Path="/5BC2B41E/5BC2B5CA" Ref="#PWR0236" Part="1" 122 | F 0 "#PWR0236" H 5650 2400 50 0001 C CNN 123 | F 1 "GND" V 5700 2650 50 0001 C CNN 124 | F 2 "" H 5650 2650 50 0001 C CNN 125 | F 3 "" H 5650 2650 50 0001 C CNN 126 | 1 5650 2650 127 | -1 0 0 1 128 | $EndComp 129 | $Comp 130 | L Device:C_Small C? 131 | U 1 1 5BC2B5D0 132 | P 5250 2400 133 | AR Path="/5BC41CC8/5BC2B5D0" Ref="C?" Part="1" 134 | AR Path="/5BC2B41E/5BC2B5D0" Ref="C502" Part="1" 135 | F 0 "C502" H 4850 2450 50 0000 L CNN 136 | F 1 "10 nF" H 4850 2350 50 0000 L CNN 137 | F 2 "Capacitors_SMD:C_0402" H 5250 2400 50 0001 C CNN 138 | F 3 "~" H 5250 2400 50 0001 C CNN 139 | 1 5250 2400 140 | 1 0 0 -1 141 | $EndComp 142 | Wire Wire Line 143 | 5550 2150 5550 2250 144 | Wire Wire Line 145 | 5550 2250 5250 2250 146 | Wire Wire Line 147 | 5250 2250 5250 2300 148 | Connection ~ 5550 2250 149 | Wire Wire Line 150 | 5550 2250 5550 2700 151 | $Comp 152 | L power:GND #PWR? 153 | U 1 1 5BC2B5DC 154 | P 5250 2550 155 | AR Path="/5BC41CC8/5BC2B5DC" Ref="#PWR?" Part="1" 156 | AR Path="/5BC2B41E/5BC2B5DC" Ref="#PWR0237" Part="1" 157 | F 0 "#PWR0237" H 5250 2300 50 0001 C CNN 158 | F 1 "GND" H 5250 2400 50 0000 C CNN 159 | F 2 "" H 5250 2550 50 0001 C CNN 160 | F 3 "" H 5250 2550 50 0001 C CNN 161 | 1 5250 2550 162 | 1 0 0 -1 163 | $EndComp 164 | Wire Wire Line 165 | 5250 2550 5250 2500 166 | $Comp 167 | L power:+5VA #PWR? 168 | U 1 1 5BC2B5E3 169 | P 5200 4100 170 | AR Path="/5BC41CC8/5BC2B5E3" Ref="#PWR?" Part="1" 171 | AR Path="/5BC2B41E/5BC2B5E3" Ref="#PWR0238" Part="1" 172 | F 0 "#PWR0238" H 5200 3950 50 0001 C CNN 173 | F 1 "+5VA" V 5200 4350 50 0000 C CNN 174 | F 2 "" H 5200 4100 50 0001 C CNN 175 | F 3 "" H 5200 4100 50 0001 C CNN 176 | 1 5200 4100 177 | 0 -1 -1 0 178 | $EndComp 179 | Wire Wire Line 180 | 5550 4000 5550 4100 181 | Wire Wire Line 182 | 5550 4100 5300 4100 183 | $Comp 184 | L Device:C_Small C? 185 | U 1 1 5BC2B5EB 186 | P 5300 4250 187 | AR Path="/5BC41CC8/5BC2B5EB" Ref="C?" Part="1" 188 | AR Path="/5BC2B41E/5BC2B5EB" Ref="C503" Part="1" 189 | F 0 "C503" H 5392 4296 50 0000 L CNN 190 | F 1 "10 nF" H 5392 4205 50 0000 L CNN 191 | F 2 "Capacitors_SMD:C_0402" H 5300 4250 50 0001 C CNN 192 | F 3 "~" H 5300 4250 50 0001 C CNN 193 | 1 5300 4250 194 | 1 0 0 -1 195 | $EndComp 196 | $Comp 197 | L power:GND #PWR? 198 | U 1 1 5BC2B5F2 199 | P 5300 4400 200 | AR Path="/5BC41CC8/5BC2B5F2" Ref="#PWR?" Part="1" 201 | AR Path="/5BC2B41E/5BC2B5F2" Ref="#PWR0239" Part="1" 202 | F 0 "#PWR0239" H 5300 4150 50 0001 C CNN 203 | F 1 "GND" H 5300 4250 50 0000 C CNN 204 | F 2 "" H 5300 4400 50 0001 C CNN 205 | F 3 "" H 5300 4400 50 0001 C CNN 206 | 1 5300 4400 207 | 1 0 0 -1 208 | $EndComp 209 | Wire Wire Line 210 | 5300 4400 5300 4350 211 | Wire Wire Line 212 | 5300 4150 5300 4100 213 | Connection ~ 5300 4100 214 | Wire Wire Line 215 | 5300 4100 5200 4100 216 | $Comp 217 | L Device:R_Small R? 218 | U 1 1 5BC2B5FC 219 | P 5750 2350 220 | AR Path="/5BC41CC8/5BC2B5FC" Ref="R?" Part="1" 221 | AR Path="/5BC2B41E/5BC2B5FC" Ref="R503" Part="1" 222 | F 0 "R503" V 5650 2400 50 0000 L CNN 223 | F 1 "1k" V 5650 2200 50 0000 L CNN 224 | F 2 "Resistors_SMD:R_0402" H 5750 2350 50 0001 C CNN 225 | F 3 "~" H 5750 2350 50 0001 C CNN 226 | 1 5750 2350 227 | 1 0 0 -1 228 | $EndComp 229 | $Comp 230 | L power:GND #PWR? 231 | U 1 1 5BC2B603 232 | P 5750 2150 233 | AR Path="/5BC41CC8/5BC2B603" Ref="#PWR?" Part="1" 234 | AR Path="/5BC2B41E/5BC2B603" Ref="#PWR0240" Part="1" 235 | F 0 "#PWR0240" H 5750 1900 50 0001 C CNN 236 | F 1 "GND" V 5750 1900 50 0000 C CNN 237 | F 2 "" H 5750 2150 50 0001 C CNN 238 | F 3 "" H 5750 2150 50 0001 C CNN 239 | 1 5750 2150 240 | -1 0 0 1 241 | $EndComp 242 | Wire Wire Line 243 | 5750 2150 5750 2250 244 | Wire Wire Line 245 | 5750 2450 5750 2700 246 | Wire Wire Line 247 | 5850 2150 5850 2250 248 | $Comp 249 | L Device:C_Small C? 250 | U 1 1 5BC2B60C 251 | P 6100 2400 252 | AR Path="/5BC41CC8/5BC2B60C" Ref="C?" Part="1" 253 | AR Path="/5BC2B41E/5BC2B60C" Ref="C504" Part="1" 254 | F 0 "C504" H 6192 2446 50 0000 L CNN 255 | F 1 "10 nF" H 6192 2355 50 0000 L CNN 256 | F 2 "Capacitors_SMD:C_0402" H 6100 2400 50 0001 C CNN 257 | F 3 "~" H 6100 2400 50 0001 C CNN 258 | 1 6100 2400 259 | 1 0 0 -1 260 | $EndComp 261 | $Comp 262 | L power:GND #PWR? 263 | U 1 1 5BC2B613 264 | P 6100 2550 265 | AR Path="/5BC41CC8/5BC2B613" Ref="#PWR?" Part="1" 266 | AR Path="/5BC2B41E/5BC2B613" Ref="#PWR0241" Part="1" 267 | F 0 "#PWR0241" H 6100 2300 50 0001 C CNN 268 | F 1 "GND" H 6100 2400 50 0000 C CNN 269 | F 2 "" H 6100 2550 50 0001 C CNN 270 | F 3 "" H 6100 2550 50 0001 C CNN 271 | 1 6100 2550 272 | 1 0 0 -1 273 | $EndComp 274 | Wire Wire Line 275 | 6100 2550 6100 2500 276 | Wire Wire Line 277 | 6100 2300 6100 2250 278 | Wire Wire Line 279 | 6100 2250 5850 2250 280 | Connection ~ 5850 2250 281 | Wire Wire Line 282 | 5850 2250 5850 2700 283 | Wire Wire Line 284 | 5650 2650 5650 2700 285 | Wire Wire Line 286 | 5650 4000 5650 4900 287 | Text Notes 7000 3250 0 50 ~ 0 288 | +/- 2V 289 | $Comp 290 | L Device:R_Small R? 291 | U 1 1 5BC2C332 292 | P 5750 5000 293 | AR Path="/5BC41CC8/5BC2C332" Ref="R?" Part="1" 294 | AR Path="/5BC2B41E/5BC2C332" Ref="R504" Part="1" 295 | F 0 "R504" V 5650 5050 50 0000 L CNN 296 | F 1 "1k" V 5650 4850 50 0000 L CNN 297 | F 2 "Resistors_SMD:R_0402" H 5750 5000 50 0001 C CNN 298 | F 3 "~" H 5750 5000 50 0001 C CNN 299 | 1 5750 5000 300 | -1 0 0 1 301 | $EndComp 302 | $Comp 303 | L Device:R_Small R? 304 | U 1 1 5BC2C459 305 | P 5650 5000 306 | AR Path="/5BC41CC8/5BC2C459" Ref="R?" Part="1" 307 | AR Path="/5BC2B41E/5BC2C459" Ref="R502" Part="1" 308 | F 0 "R502" V 5550 5050 50 0000 L CNN 309 | F 1 "JMP" V 5550 4850 50 0000 L CNN 310 | F 2 "Resistors_SMD:R_0402" H 5650 5000 50 0001 C CNN 311 | F 3 "~" H 5650 5000 50 0001 C CNN 312 | 1 5650 5000 313 | 1 0 0 -1 314 | $EndComp 315 | $Comp 316 | L power:GND #PWR? 317 | U 1 1 5BC2C4B0 318 | P 5650 5150 319 | AR Path="/5BC41CC8/5BC2C4B0" Ref="#PWR?" Part="1" 320 | AR Path="/5BC2B41E/5BC2C4B0" Ref="#PWR0242" Part="1" 321 | F 0 "#PWR0242" H 5650 4900 50 0001 C CNN 322 | F 1 "GND" H 5650 5000 50 0000 C CNN 323 | F 2 "" H 5650 5150 50 0001 C CNN 324 | F 3 "" H 5650 5150 50 0001 C CNN 325 | 1 5650 5150 326 | 1 0 0 -1 327 | $EndComp 328 | $Comp 329 | L power:GND #PWR? 330 | U 1 1 5BC2C4CD 331 | P 5750 5150 332 | AR Path="/5BC41CC8/5BC2C4CD" Ref="#PWR?" Part="1" 333 | AR Path="/5BC2B41E/5BC2C4CD" Ref="#PWR0243" Part="1" 334 | F 0 "#PWR0243" H 5750 4900 50 0001 C CNN 335 | F 1 "GND" H 5750 5000 50 0000 C CNN 336 | F 2 "" H 5750 5150 50 0001 C CNN 337 | F 3 "" H 5750 5150 50 0001 C CNN 338 | 1 5750 5150 339 | 1 0 0 -1 340 | $EndComp 341 | Wire Wire Line 342 | 5750 4000 5750 4900 343 | Wire Wire Line 344 | 5650 5100 5650 5150 345 | Wire Wire Line 346 | 5750 5100 5750 5150 347 | Text Notes 5250 5550 0 50 ~ 0 348 | DISABLE LATCH 349 | Wire Wire Line 350 | 6350 3400 7850 3400 351 | $Comp 352 | L Device:R_Small R? 353 | U 1 1 5BC2E533 354 | P 7850 3750 355 | AR Path="/5BC41CC8/5BC2E533" Ref="R?" Part="1" 356 | AR Path="/5BC2B41E/5BC2E533" Ref="R505" Part="1" 357 | F 0 "R505" V 7750 3800 50 0000 L CNN 358 | F 1 "DNI" V 7750 3600 50 0000 L CNN 359 | F 2 "Resistors_SMD:R_0402" H 7850 3750 50 0001 C CNN 360 | F 3 "~" H 7850 3750 50 0001 C CNN 361 | 1 7850 3750 362 | 1 0 0 -1 363 | $EndComp 364 | $Comp 365 | L power:GND #PWR? 366 | U 1 1 5BC2E6C0 367 | P 7850 3900 368 | AR Path="/5BC41CC8/5BC2E6C0" Ref="#PWR?" Part="1" 369 | AR Path="/5BC2B41E/5BC2E6C0" Ref="#PWR0244" Part="1" 370 | F 0 "#PWR0244" H 7850 3650 50 0001 C CNN 371 | F 1 "GND" H 7850 3750 50 0000 C CNN 372 | F 2 "" H 7850 3900 50 0001 C CNN 373 | F 3 "" H 7850 3900 50 0001 C CNN 374 | 1 7850 3900 375 | 1 0 0 -1 376 | $EndComp 377 | Wire Wire Line 378 | 7850 3850 7850 3900 379 | Wire Wire Line 380 | 7850 3650 7850 3400 381 | $Comp 382 | L Device:R_Small R? 383 | U 1 1 5BC2F328 384 | P 8100 3400 385 | AR Path="/5BC41CC8/5BC2F328" Ref="R?" Part="1" 386 | AR Path="/5BC2B41E/5BC2F328" Ref="R507" Part="1" 387 | F 0 "R507" V 8000 3450 50 0000 L CNN 388 | F 1 "JMP" V 8000 3250 50 0000 L CNN 389 | F 2 "Resistors_SMD:R_0201" H 8100 3400 50 0001 C CNN 390 | F 3 "~" H 8100 3400 50 0001 C CNN 391 | 1 8100 3400 392 | 0 -1 -1 0 393 | $EndComp 394 | $Comp 395 | L Device:R_Small R? 396 | U 1 1 5BC2F385 397 | P 8100 3300 398 | AR Path="/5BC41CC8/5BC2F385" Ref="R?" Part="1" 399 | AR Path="/5BC2B41E/5BC2F385" Ref="R506" Part="1" 400 | F 0 "R506" V 8000 3350 50 0000 L CNN 401 | F 1 "JMP" V 8000 3150 50 0000 L CNN 402 | F 2 "Resistors_SMD:R_0201" H 8100 3300 50 0001 C CNN 403 | F 3 "~" H 8100 3300 50 0001 C CNN 404 | 1 8100 3300 405 | 0 1 1 0 406 | $EndComp 407 | Wire Wire Line 408 | 6350 3300 8000 3300 409 | Wire Wire Line 410 | 7850 3400 8000 3400 411 | Connection ~ 7850 3400 412 | Text HLabel 8800 3300 2 50 Input ~ 0 413 | PULSE_OUT_P 414 | Text HLabel 8800 3400 2 50 Input ~ 0 415 | PULSE_OUT_N 416 | Wire Wire Line 417 | 8200 3300 8800 3300 418 | Wire Wire Line 419 | 8800 3400 8200 3400 420 | Text HLabel 4000 3300 0 50 Input ~ 0 421 | CLK_IN_P 422 | Text HLabel 4000 3400 0 50 Input ~ 0 423 | CLK_IN_N 424 | $Comp 425 | L Device:C_Small C? 426 | U 1 1 5BC34BA3 427 | P 4500 4000 428 | AR Path="/5BC41CC8/5BC34BA3" Ref="C?" Part="1" 429 | AR Path="/5BC2B41E/5BC34BA3" Ref="C501" Part="1" 430 | F 0 "C501" H 4592 4046 50 0000 L CNN 431 | F 1 "10 nF" H 4592 3955 50 0000 L CNN 432 | F 2 "Capacitors_SMD:C_0402" H 4500 4000 50 0001 C CNN 433 | F 3 "~" H 4500 4000 50 0001 C CNN 434 | 1 4500 4000 435 | 1 0 0 -1 436 | $EndComp 437 | $Comp 438 | L power:GND #PWR? 439 | U 1 1 5BC35338 440 | P 4500 4150 441 | AR Path="/5BC41CC8/5BC35338" Ref="#PWR?" Part="1" 442 | AR Path="/5BC2B41E/5BC35338" Ref="#PWR0246" Part="1" 443 | F 0 "#PWR0246" H 4500 3900 50 0001 C CNN 444 | F 1 "GND" V 4550 4150 50 0001 C CNN 445 | F 2 "" H 4500 4150 50 0001 C CNN 446 | F 3 "" H 4500 4150 50 0001 C CNN 447 | 1 4500 4150 448 | 1 0 0 -1 449 | $EndComp 450 | Wire Wire Line 451 | 4500 4150 4500 4100 452 | Wire Wire Line 453 | 4000 3300 5050 3300 454 | Wire Wire Line 455 | 4000 3400 5050 3400 456 | $Comp 457 | L power:+3V3 #PWR0248 458 | U 1 1 5C348861 459 | P 5000 3500 460 | F 0 "#PWR0248" H 5000 3350 50 0001 C CNN 461 | F 1 "+3V3" V 5015 3628 50 0000 L CNN 462 | F 2 "" H 5000 3500 50 0001 C CNN 463 | F 3 "" H 5000 3500 50 0001 C CNN 464 | 1 5000 3500 465 | 0 -1 -1 0 466 | $EndComp 467 | Wire Wire Line 468 | 5000 3500 5050 3500 469 | $Comp 470 | L power:+3V3 #PWR0249 471 | U 1 1 5C348FB2 472 | P 5000 3200 473 | F 0 "#PWR0249" H 5000 3050 50 0001 C CNN 474 | F 1 "+3V3" V 5015 3328 50 0000 L CNN 475 | F 2 "" H 5000 3200 50 0001 C CNN 476 | F 3 "" H 5000 3200 50 0001 C CNN 477 | 1 5000 3200 478 | 0 -1 -1 0 479 | $EndComp 480 | Wire Wire Line 481 | 5050 3200 5000 3200 482 | $Comp 483 | L power:+3V3 #PWR0253 484 | U 1 1 5C349D6E 485 | P 4500 3800 486 | F 0 "#PWR0253" H 4500 3650 50 0001 C CNN 487 | F 1 "+3V3" H 4515 3973 50 0000 C CNN 488 | F 2 "" H 4500 3800 50 0001 C CNN 489 | F 3 "" H 4500 3800 50 0001 C CNN 490 | 1 4500 3800 491 | 1 0 0 -1 492 | $EndComp 493 | Wire Wire Line 494 | 4500 3800 4500 3900 495 | $EndSCHEMATC 496 | -------------------------------------------------------------------------------- /hardware/tdr-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # 74xx1g14_74xx1G14 5 | # 6 | DEF 74xx1g14_74xx1G14 U 0 40 Y Y 1 F N 7 | F0 "U" -550 350 60 H V C CNN 8 | F1 "74xx1g14_74xx1G14" -400 450 60 H V C CNN 9 | F2 "" 0 0 60 H V C CNN 10 | F3 "" 0 0 60 H V C CNN 11 | DRAW 12 | S -150 200 150 -200 0 1 0 N 13 | X A 2 -450 0 300 R 50 50 1 1 I 14 | X GND 3 0 -500 300 U 50 50 1 1 I 15 | X Y 4 450 0 300 L 50 50 1 1 I 16 | X Vcc 5 0 500 300 D 50 50 1 1 I 17 | ENDDRAW 18 | ENDDEF 19 | # 20 | # 74xx_74HC244 21 | # 22 | DEF 74xx_74HC244 U 0 40 Y Y 1 L N 23 | F0 "U" -300 650 50 H V C CNN 24 | F1 "74xx_74HC244" -300 -650 50 H V C CNN 25 | F2 "" 0 0 50 H I C CNN 26 | F3 "" 0 0 50 H I C CNN 27 | ALIAS 74HCT244 28 | $FPLIST 29 | TSSOP*4.4x6.5mm*P0.65mm* 30 | SSOP*4.4x6.5mm*P0.65mm* 31 | $ENDFPLIST 32 | DRAW 33 | S -300 600 300 -600 1 1 10 f 34 | P 4 1 0 6 50 0 -50 50 -50 -50 50 0 N 35 | X 1OE 1 -500 -400 200 R 50 50 1 0 I I 36 | X GND 10 0 -800 200 U 50 50 1 0 W 37 | X 2A3 11 -500 -200 200 R 50 50 1 0 I 38 | X 1Y3 12 500 200 200 L 50 50 1 0 O 39 | X 2A2 13 -500 -100 200 R 50 50 1 0 I 40 | X 1Y2 14 500 300 200 L 50 50 1 0 O 41 | X 2A1 15 -500 0 200 R 50 50 1 0 I 42 | X 1Y1 16 500 400 200 L 50 50 1 0 O 43 | X 2A0 17 -500 100 200 R 50 50 1 0 I 44 | X 1Y0 18 500 500 200 L 50 50 1 0 O 45 | X 2OE 19 -500 -500 200 R 50 50 1 0 I I 46 | X 1A0 2 -500 500 200 R 50 50 1 0 I 47 | X VCC 20 0 800 200 D 50 50 1 0 W 48 | X 2Y0 3 500 100 200 L 50 50 1 0 O 49 | X 1A1 4 -500 400 200 R 50 50 1 0 I 50 | X 2Y1 5 500 0 200 L 50 50 1 0 O 51 | X 1A2 6 -500 300 200 R 50 50 1 0 I 52 | X 2Y2 7 500 -100 200 L 50 50 1 0 O 53 | X 1A3 8 -500 200 200 R 50 50 1 0 I 54 | X 2Y3 9 500 -200 200 L 50 50 1 0 O 55 | ENDDRAW 56 | ENDDEF 57 | # 58 | # Connector_Barrel_Jack_Switch 59 | # 60 | DEF Connector_Barrel_Jack_Switch J 0 20 Y N 1 F N 61 | F0 "J" 0 210 50 H V C CNN 62 | F1 "Connector_Barrel_Jack_Switch" 0 -200 50 H V C CNN 63 | F2 "" 50 -40 50 H I C CNN 64 | F3 "" 50 -40 50 H I C CNN 65 | $FPLIST 66 | BarrelJack* 67 | $ENDFPLIST 68 | DRAW 69 | A -130 100 25 901 -901 0 1 10 F -130 125 -130 75 70 | A -130 100 25 901 -901 0 1 10 N -130 125 -130 75 71 | S -200 150 200 -150 0 1 10 f 72 | S 145 125 -130 75 0 1 10 F 73 | P 2 0 1 10 50 -90 75 -65 N 74 | P 2 0 1 10 200 100 150 100 N 75 | P 4 0 1 10 200 0 50 0 50 -90 25 -65 N 76 | P 6 0 1 10 -150 -100 -100 -100 -50 -50 0 -100 100 -100 200 -100 N 77 | X ~ 1 300 100 100 L 50 50 1 1 P 78 | X ~ 2 300 -100 100 L 50 50 1 1 P 79 | X ~ 3 300 0 100 L 50 50 1 1 P 80 | ENDDRAW 81 | ENDDEF 82 | # 83 | # Connector_Conn_Coaxial 84 | # 85 | DEF Connector_Conn_Coaxial J 0 40 Y N 1 F N 86 | F0 "J" 10 120 50 H V C CNN 87 | F1 "Connector_Conn_Coaxial" 115 0 50 V V C CNN 88 | F2 "" 0 0 50 H I C CNN 89 | F3 "" 0 0 50 H I C CNN 90 | $FPLIST 91 | *BNC* 92 | *SMA* 93 | *SMB* 94 | *SMC* 95 | *Cinch* 96 | $ENDFPLIST 97 | DRAW 98 | A -2 0 71 1636 0 0 1 10 N -70 20 70 0 99 | A -1 0 71 0 -1638 0 1 10 N 70 0 -70 -20 100 | C 0 0 20 0 1 8 N 101 | P 2 0 1 0 -100 0 -20 0 N 102 | P 2 0 1 0 0 -100 0 -70 N 103 | X In 1 -200 0 100 R 50 50 1 1 P 104 | X Ext 2 0 -200 100 U 50 50 1 1 P 105 | ENDDRAW 106 | ENDDEF 107 | # 108 | # Connector_Generic_Conn_02x01 109 | # 110 | DEF Connector_Generic_Conn_02x01 J 0 40 Y N 1 F N 111 | F0 "J" 50 100 50 H V C CNN 112 | F1 "Connector_Generic_Conn_02x01" 50 -100 50 H V C CNN 113 | F2 "" 0 0 50 H I C CNN 114 | F3 "" 0 0 50 H I C CNN 115 | $FPLIST 116 | Connector*:*_2x??_* 117 | $ENDFPLIST 118 | DRAW 119 | S -50 5 0 -5 1 1 6 N 120 | S -50 50 150 -50 1 1 10 f 121 | S 150 5 100 -5 1 1 6 N 122 | X Pin_1 1 -200 0 150 R 50 50 1 1 P 123 | X Pin_2 2 300 0 150 L 50 50 1 1 P 124 | ENDDRAW 125 | ENDDEF 126 | # 127 | # Connector_Generic_Conn_02x06_Counter_Clockwise 128 | # 129 | DEF Connector_Generic_Conn_02x06_Counter_Clockwise J 0 40 Y N 1 F N 130 | F0 "J" 50 300 50 H V C CNN 131 | F1 "Connector_Generic_Conn_02x06_Counter_Clockwise" 50 -400 50 H V C CNN 132 | F2 "" 0 0 50 H I C CNN 133 | F3 "" 0 0 50 H I C CNN 134 | $FPLIST 135 | Connector*:*_2x??_* 136 | $ENDFPLIST 137 | DRAW 138 | S -50 -295 0 -305 1 1 6 N 139 | S -50 -195 0 -205 1 1 6 N 140 | S -50 -95 0 -105 1 1 6 N 141 | S -50 5 0 -5 1 1 6 N 142 | S -50 105 0 95 1 1 6 N 143 | S -50 205 0 195 1 1 6 N 144 | S -50 250 150 -350 1 1 10 f 145 | S 150 -295 100 -305 1 1 6 N 146 | S 150 -195 100 -205 1 1 6 N 147 | S 150 -95 100 -105 1 1 6 N 148 | S 150 5 100 -5 1 1 6 N 149 | S 150 105 100 95 1 1 6 N 150 | S 150 205 100 195 1 1 6 N 151 | X Pin_1 1 -200 200 150 R 50 50 1 1 P 152 | X Pin_10 10 300 0 150 L 50 50 1 1 P 153 | X Pin_11 11 300 100 150 L 50 50 1 1 P 154 | X Pin_12 12 300 200 150 L 50 50 1 1 P 155 | X Pin_2 2 -200 100 150 R 50 50 1 1 P 156 | X Pin_3 3 -200 0 150 R 50 50 1 1 P 157 | X Pin_4 4 -200 -100 150 R 50 50 1 1 P 158 | X Pin_5 5 -200 -200 150 R 50 50 1 1 P 159 | X Pin_6 6 -200 -300 150 R 50 50 1 1 P 160 | X Pin_7 7 300 -300 150 L 50 50 1 1 P 161 | X Pin_8 8 300 -200 150 L 50 50 1 1 P 162 | X Pin_9 9 300 -100 150 L 50 50 1 1 P 163 | ENDDRAW 164 | ENDDEF 165 | # 166 | # Connector_TestPoint 167 | # 168 | DEF Connector_TestPoint TP 0 30 N N 1 F N 169 | F0 "TP" 0 270 50 H V C CNN 170 | F1 "Connector_TestPoint" 0 200 50 H V C CNN 171 | F2 "" 200 0 50 H I C CNN 172 | F3 "" 200 0 50 H I C CNN 173 | $FPLIST 174 | Pin* 175 | Test* 176 | $ENDFPLIST 177 | DRAW 178 | C 0 130 30 0 1 0 N 179 | X 1 1 0 0 100 U 50 50 1 1 P 180 | ENDDRAW 181 | ENDDEF 182 | # 183 | # Device_CP1_Small 184 | # 185 | DEF Device_CP1_Small C 0 10 N N 1 F N 186 | F0 "C" 10 70 50 H V L CNN 187 | F1 "Device_CP1_Small" 10 -80 50 H V L CNN 188 | F2 "" 0 0 50 H I C CNN 189 | F3 "" 0 0 50 H I C CNN 190 | $FPLIST 191 | CP_* 192 | $ENDFPLIST 193 | DRAW 194 | A 0 -140 125 1186 614 0 1 12 N -60 -30 60 -30 195 | P 2 0 1 12 -60 20 60 20 N 196 | P 2 0 1 0 -50 60 -30 60 N 197 | P 2 0 1 0 -40 50 -40 70 N 198 | X ~ 1 0 100 80 D 50 50 1 1 P 199 | X ~ 2 0 -100 80 U 50 50 1 1 P 200 | ENDDRAW 201 | ENDDEF 202 | # 203 | # Device_C_Small 204 | # 205 | DEF Device_C_Small C 0 10 N N 1 F N 206 | F0 "C" 10 70 50 H V L CNN 207 | F1 "Device_C_Small" 10 -80 50 H V L CNN 208 | F2 "" 0 0 50 H I C CNN 209 | F3 "" 0 0 50 H I C CNN 210 | $FPLIST 211 | C_* 212 | $ENDFPLIST 213 | DRAW 214 | P 2 0 1 13 -60 -20 60 -20 N 215 | P 2 0 1 12 -60 20 60 20 N 216 | X ~ 1 0 100 80 D 50 50 1 1 P 217 | X ~ 2 0 -100 80 U 50 50 1 1 P 218 | ENDDRAW 219 | ENDDEF 220 | # 221 | # Device_LED 222 | # 223 | DEF Device_LED D 0 40 N N 1 F N 224 | F0 "D" 0 100 50 H V C CNN 225 | F1 "Device_LED" 0 -100 50 H V C CNN 226 | F2 "" 0 0 50 H I C CNN 227 | F3 "" 0 0 50 H I C CNN 228 | $FPLIST 229 | LED* 230 | LED_SMD:* 231 | LED_THT:* 232 | $ENDFPLIST 233 | DRAW 234 | P 2 0 1 8 -50 -50 -50 50 N 235 | P 2 0 1 0 -50 0 50 0 N 236 | P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N 237 | P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N 238 | P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N 239 | X K 1 -150 0 100 R 50 50 1 1 P 240 | X A 2 150 0 100 L 50 50 1 1 P 241 | ENDDRAW 242 | ENDDEF 243 | # 244 | # Device_L_Small 245 | # 246 | DEF Device_L_Small L 0 10 N N 1 F N 247 | F0 "L" 30 40 50 H V L CNN 248 | F1 "Device_L_Small" 30 -40 50 H V L CNN 249 | F2 "" 0 0 50 H I C CNN 250 | F3 "" 0 0 50 H I C CNN 251 | $FPLIST 252 | Choke_* 253 | *Coil* 254 | Inductor_* 255 | L_* 256 | $ENDFPLIST 257 | DRAW 258 | A 0 -60 20 -899 899 0 1 0 N 0 -80 0 -40 259 | A 0 -20 20 -899 899 0 1 0 N 0 -40 0 0 260 | A 0 20 20 -899 899 0 1 0 N 0 0 0 40 261 | A 0 60 20 -899 899 0 1 0 N 0 40 0 80 262 | X ~ 1 0 100 20 D 50 50 1 1 P 263 | X ~ 2 0 -100 20 U 50 50 1 1 P 264 | ENDDRAW 265 | ENDDEF 266 | # 267 | # Device_Opamp_Dual_Generic 268 | # 269 | DEF Device_Opamp_Dual_Generic U 0 20 Y Y 3 F N 270 | F0 "U" 0 200 50 H V L CNN 271 | F1 "Device_Opamp_Dual_Generic" 0 -200 50 H V L CNN 272 | F2 "" 0 0 50 H I C CNN 273 | F3 "" 0 0 50 H I C CNN 274 | $FPLIST 275 | SOIC*3.9x4.9mm*P1.27mm* 276 | DIP*W7.62mm* 277 | MSOP*3x3mm*P0.65mm* 278 | SSOP*2.95x2.8mm*P0.65mm* 279 | TSSOP*3x3mm*P0.65mm* 280 | VSSOP*P0.5mm* 281 | TO?99* 282 | $ENDFPLIST 283 | DRAW 284 | P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f 285 | P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f 286 | X ~ 1 300 0 100 L 50 50 1 1 O 287 | X - 2 -300 -100 100 R 50 50 1 1 I 288 | X + 3 -300 100 100 R 50 50 1 1 I 289 | X + 5 -300 100 100 R 50 50 2 1 I 290 | X - 6 -300 -100 100 R 50 50 2 1 I 291 | X ~ 7 300 0 100 L 50 50 2 1 O 292 | X V- 4 -100 -300 150 U 50 50 3 1 W 293 | X V+ 8 -100 300 150 D 50 50 3 1 W 294 | ENDDRAW 295 | ENDDEF 296 | # 297 | # Device_Polyfuse_Small 298 | # 299 | DEF Device_Polyfuse_Small F 0 0 N Y 1 F N 300 | F0 "F" -75 0 50 V V C CNN 301 | F1 "Device_Polyfuse_Small" 75 0 50 V V C CNN 302 | F2 "" 50 -200 50 H I L CNN 303 | F3 "" 0 0 50 H I C CNN 304 | $FPLIST 305 | *polyfuse* 306 | *PTC* 307 | $ENDFPLIST 308 | DRAW 309 | S -20 50 20 -50 0 1 0 N 310 | P 2 0 1 0 0 100 0 -100 N 311 | P 4 0 1 0 -40 50 -40 30 40 -30 40 -50 N 312 | X ~ 1 0 100 25 D 50 50 1 1 P 313 | X ~ 2 0 -100 25 U 50 50 1 1 P 314 | ENDDRAW 315 | ENDDEF 316 | # 317 | # Device_Q_PMOS_GSD 318 | # 319 | DEF Device_Q_PMOS_GSD Q 0 0 Y N 1 F N 320 | F0 "Q" 200 50 50 H V L CNN 321 | F1 "Device_Q_PMOS_GSD" 200 -50 50 H V L CNN 322 | F2 "" 200 100 50 H I C CNN 323 | F3 "" 0 0 50 H I C CNN 324 | DRAW 325 | C 65 0 111 0 1 10 N 326 | C 100 -70 11 0 1 0 F 327 | C 100 70 11 0 1 0 F 328 | P 2 0 1 0 2 0 10 0 N 329 | P 2 0 1 0 30 -70 100 -70 N 330 | P 2 0 1 10 30 -50 30 -90 N 331 | P 2 0 1 0 30 0 100 0 N 332 | P 2 0 1 10 30 20 30 -20 N 333 | P 2 0 1 0 30 70 100 70 N 334 | P 2 0 1 10 30 90 30 50 N 335 | P 2 0 1 0 100 -70 100 -100 N 336 | P 2 0 1 0 100 -70 100 0 N 337 | P 2 0 1 0 100 100 100 70 N 338 | P 3 0 1 10 10 75 10 -75 10 -75 N 339 | P 4 0 1 0 90 0 50 -15 50 15 90 0 F 340 | P 4 0 1 0 100 -70 130 -70 130 70 100 70 N 341 | P 4 0 1 0 110 -20 115 -15 145 -15 150 -10 N 342 | P 4 0 1 0 130 -15 115 10 145 10 130 -15 N 343 | X G 1 -200 0 200 R 50 50 1 1 I 344 | X S 2 100 -200 100 U 50 50 1 1 P 345 | X D 3 100 200 100 D 50 50 1 1 P 346 | ENDDRAW 347 | ENDDEF 348 | # 349 | # Device_R_Pack04 350 | # 351 | DEF Device_R_Pack04 RN 0 0 Y N 1 F N 352 | F0 "RN" -300 0 50 V V C CNN 353 | F1 "Device_R_Pack04" 200 0 50 V V C CNN 354 | F2 "" 275 0 50 V I C CNN 355 | F3 "" 0 0 50 H I C CNN 356 | $FPLIST 357 | DIP* 358 | SOIC* 359 | $ENDFPLIST 360 | DRAW 361 | S -250 -95 150 95 0 1 10 f 362 | S -225 75 -175 -75 0 1 10 N 363 | S -125 75 -75 -75 0 1 10 N 364 | S -25 75 25 -75 0 1 10 N 365 | S 75 75 125 -75 0 1 10 N 366 | P 2 0 1 0 -200 -100 -200 -75 N 367 | P 2 0 1 0 -200 75 -200 100 N 368 | P 2 0 1 0 -100 -100 -100 -75 N 369 | P 2 0 1 0 -100 75 -100 100 N 370 | P 2 0 1 0 0 -100 0 -75 N 371 | P 2 0 1 0 0 75 0 100 N 372 | P 2 0 1 0 100 -100 100 -75 N 373 | P 2 0 1 0 100 75 100 100 N 374 | X R1.1 1 -200 -200 100 U 50 50 1 1 P 375 | X R2.1 2 -100 -200 100 U 50 50 1 1 P 376 | X R3.1 3 0 -200 100 U 50 50 1 1 P 377 | X R4.1 4 100 -200 100 U 50 50 1 1 P 378 | X R4.2 5 100 200 100 D 50 50 1 1 P 379 | X R3.2 6 0 200 100 D 50 50 1 1 P 380 | X R2.2 7 -100 200 100 D 50 50 1 1 P 381 | X R1.2 8 -200 200 100 D 50 50 1 1 P 382 | ENDDRAW 383 | ENDDEF 384 | # 385 | # Device_R_Small 386 | # 387 | DEF Device_R_Small R 0 10 N N 1 F N 388 | F0 "R" 30 20 50 H V L CNN 389 | F1 "Device_R_Small" 30 -40 50 H V L CNN 390 | F2 "" 0 0 50 H I C CNN 391 | F3 "" 0 0 50 H I C CNN 392 | $FPLIST 393 | R_* 394 | $ENDFPLIST 395 | DRAW 396 | S -30 70 30 -70 0 1 8 N 397 | X ~ 1 0 100 30 D 50 50 1 1 P 398 | X ~ 2 0 -100 30 U 50 50 1 1 P 399 | ENDDRAW 400 | ENDDEF 401 | # 402 | # Mechanical_MountingHole 403 | # 404 | DEF Mechanical_MountingHole H 0 40 Y Y 1 F N 405 | F0 "H" 0 200 50 H V C CNN 406 | F1 "Mechanical_MountingHole" 0 125 50 H V C CNN 407 | F2 "" 0 0 50 H I C CNN 408 | F3 "" 0 0 50 H I C CNN 409 | $FPLIST 410 | MountingHole* 411 | $ENDFPLIST 412 | DRAW 413 | C 0 0 50 0 1 50 N 414 | ENDDRAW 415 | ENDDEF 416 | # 417 | # ld39100_LD39100 418 | # 419 | DEF ld39100_LD39100 U 0 40 Y Y 1 F N 420 | F0 "U" -400 300 60 H V C CNN 421 | F1 "ld39100_LD39100" -250 400 60 H V C CNN 422 | F2 "" 0 0 60 H I C CNN 423 | F3 "" 0 0 60 H I C CNN 424 | DRAW 425 | S -300 200 300 -250 0 1 0 N 426 | X EN 1 -500 100 200 R 50 50 1 1 I 427 | X GND 2 -500 0 200 R 50 50 1 1 W 428 | X PG 3 -500 -100 200 R 50 50 1 1 O 429 | X Vout 4 500 -100 200 L 50 50 1 1 w 430 | X ADJ/NC 5 500 0 200 L 50 50 1 1 I 431 | X Vin 6 500 100 200 L 50 50 1 1 W 432 | X GND 7 0 -450 200 U 50 50 1 1 I 433 | ENDDRAW 434 | ENDDEF 435 | # 436 | # lm27762_LM27762 437 | # 438 | DEF lm27762_LM27762 U 0 40 Y Y 1 F N 439 | F0 "U" -350 950 60 H V C CNN 440 | F1 "lm27762_LM27762" -200 1050 60 H V C CNN 441 | F2 "" -100 -700 60 H I C CNN 442 | F3 "" -100 -700 60 H I C CNN 443 | DRAW 444 | S 350 750 -350 -750 0 1 0 N 445 | X PGOOD 1 -550 250 200 R 50 50 1 1 O 446 | X C1+ 10 -550 -200 200 R 50 50 1 1 I 447 | X OUT+ 11 550 550 200 L 50 50 1 1 O 448 | X EN+ 12 -550 -550 200 R 50 50 1 1 I 449 | X GND 13 0 -950 200 U 50 50 1 1 O 450 | X FB+ 2 550 250 200 L 50 50 1 1 I 451 | X VIN 3 -550 550 200 R 50 50 1 1 W 452 | X GND 4 550 -50 200 L 50 50 1 1 W 453 | X CP 5 550 650 200 L 50 50 1 1 O 454 | X OUT- 6 550 -650 200 L 50 50 1 1 O 455 | X FB- 7 550 -350 200 L 50 50 1 1 I 456 | X EN- 8 -550 -650 200 R 50 50 1 1 I 457 | X C1- 9 -550 100 200 R 50 50 1 1 I 458 | ENDDRAW 459 | ENDDEF 460 | # 461 | # power_+3.3VP 462 | # 463 | DEF power_+3.3VP #PWR 0 0 Y Y 1 F P 464 | F0 "#PWR" 150 -50 50 H I C CNN 465 | F1 "power_+3.3VP" 0 100 50 H V C CNN 466 | F2 "" 0 0 50 H I C CNN 467 | F3 "" 0 0 50 H I C CNN 468 | DRAW 469 | P 3 0 1 0 0 0 0 40 0 40 N 470 | P 7 0 1 0 20 30 0 40 -20 30 -10 70 10 70 20 30 20 30 N 471 | X +3.3VP 1 0 0 0 U 50 50 0 0 W N 472 | ENDDRAW 473 | ENDDEF 474 | # 475 | # power_+3V3 476 | # 477 | DEF power_+3V3 #PWR 0 0 Y Y 1 F P 478 | F0 "#PWR" 0 -150 50 H I C CNN 479 | F1 "power_+3V3" 0 140 50 H V C CNN 480 | F2 "" 0 0 50 H I C CNN 481 | F3 "" 0 0 50 H I C CNN 482 | ALIAS +3.3V 483 | DRAW 484 | P 2 0 1 0 -30 50 0 100 N 485 | P 2 0 1 0 0 0 0 100 N 486 | P 2 0 1 0 0 100 30 50 N 487 | X +3V3 1 0 0 0 U 50 50 1 1 W N 488 | ENDDRAW 489 | ENDDEF 490 | # 491 | # power_+5VA 492 | # 493 | DEF power_+5VA #PWR 0 0 Y Y 1 F P 494 | F0 "#PWR" 0 -150 50 H I C CNN 495 | F1 "power_+5VA" 0 140 50 H V C CNN 496 | F2 "" 0 0 50 H I C CNN 497 | F3 "" 0 0 50 H I C CNN 498 | DRAW 499 | P 2 0 1 0 -30 50 0 100 N 500 | P 2 0 1 0 0 0 0 100 N 501 | P 2 0 1 0 0 100 30 50 N 502 | X +5VA 1 0 0 0 U 50 50 1 1 W N 503 | ENDDRAW 504 | ENDDEF 505 | # 506 | # power_-5VA 507 | # 508 | DEF power_-5VA #PWR 0 0 Y Y 1 F P 509 | F0 "#PWR" 0 100 50 H I C CNN 510 | F1 "power_-5VA" 0 150 50 H V C CNN 511 | F2 "" 0 0 50 H I C CNN 512 | F3 "" 0 0 50 H I C CNN 513 | DRAW 514 | P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F 515 | X -5VA 1 0 0 0 U 50 50 0 0 W N 516 | ENDDRAW 517 | ENDDEF 518 | # 519 | # power_GND 520 | # 521 | DEF power_GND #PWR 0 0 Y Y 1 F P 522 | F0 "#PWR" 0 -250 50 H I C CNN 523 | F1 "power_GND" 0 -150 50 H V C CNN 524 | F2 "" 0 0 50 H I C CNN 525 | F3 "" 0 0 50 H I C CNN 526 | DRAW 527 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 528 | X GND 1 0 0 0 D 50 50 1 1 W N 529 | ENDDRAW 530 | ENDDEF 531 | # 532 | # power_VPP 533 | # 534 | DEF power_VPP #PWR 0 0 Y Y 1 F P 535 | F0 "#PWR" 0 -150 50 H I C CNN 536 | F1 "power_VPP" 0 150 50 H V C CNN 537 | F2 "" 0 0 50 H I C CNN 538 | F3 "" 0 0 50 H I C CNN 539 | DRAW 540 | P 2 0 1 0 -30 50 0 100 N 541 | P 2 0 1 0 0 0 0 100 N 542 | P 2 0 1 0 0 100 30 50 N 543 | X VPP 1 0 0 0 U 50 50 1 1 W N 544 | ENDDRAW 545 | ENDDEF 546 | # 547 | # synth_lib_DAC7563SDSCR 548 | # 549 | DEF synth_lib_DAC7563SDSCR U 0 40 Y Y 1 F N 550 | F0 "U" -250 400 50 H V C CNN 551 | F1 "synth_lib_DAC7563SDSCR" 0 500 50 H V C CNN 552 | F2 "" 250 200 50 H I C CNN 553 | F3 "" 250 200 50 H I C CNN 554 | DRAW 555 | S -300 300 400 -300 0 1 0 N 556 | X VoutA 1 -500 200 200 R 50 50 1 1 O 557 | X Vref 10 600 200 200 L 50 50 1 1 B 558 | X GND 11 50 -500 200 U 50 50 1 1 W 559 | X VoutB 2 -500 100 200 R 50 50 1 1 O 560 | X GND 3 -500 0 200 R 50 50 1 1 W 561 | X ~LDAC 4 -500 -100 200 R 50 50 1 1 I 562 | X ~CLR 5 -500 -200 200 R 50 50 1 1 I 563 | X ~SYNC 6 600 -200 200 L 50 50 1 1 I 564 | X SCLK 7 600 -100 200 L 50 50 1 1 I 565 | X Din 8 600 0 200 L 50 50 1 1 I 566 | X AVdd 9 600 100 200 L 50 50 1 1 W 567 | ENDDRAW 568 | ENDDEF 569 | # 570 | # synth_lib_X0060L5050AHF 571 | # 572 | DEF synth_lib_X0060L5050AHF U 0 40 Y Y 1 F N 573 | F0 "U" -450 250 50 H V C CNN 574 | F1 "synth_lib_X0060L5050AHF" -200 350 50 H V C CNN 575 | F2 "" 0 0 50 H I C CNN 576 | F3 "" 0 0 50 H I C CNN 577 | DRAW 578 | S -500 150 500 -300 0 1 0 N 579 | P 2 0 1 0 -50 50 -150 50 N 580 | P 2 0 1 0 100 -50 150 -50 N 581 | P 3 0 1 0 -50 50 50 -50 100 -50 N 582 | P 4 0 1 0 -150 -50 -50 -50 50 50 150 50 N 583 | X GND 1 -50 -500 200 U 50 50 1 1 W 584 | X RF2_IO2 2 700 -50 200 L 50 50 1 1 B 585 | X GND 3 50 -500 200 U 50 50 1 1 W 586 | X RF1_IO2 4 700 50 200 L 50 50 1 1 B 587 | X RF2_IO1 5 -700 50 200 R 50 50 1 1 B 588 | X RF1_IO1 6 -700 -50 200 R 50 50 1 1 B 589 | ENDDRAW 590 | ENDDEF 591 | # 592 | # tdr-rescue_ADCMP580-synth_lib-tdr-rescue 593 | # 594 | DEF tdr-rescue_ADCMP580-synth_lib-tdr-rescue U 0 40 Y Y 1 F N 595 | F0 "U" -900 500 50 H V C CNN 596 | F1 "tdr-rescue_ADCMP580-synth_lib-tdr-rescue" -750 600 50 H V C CNN 597 | F2 "" -900 500 50 H I C CNN 598 | F3 "" -900 500 50 H I C CNN 599 | DRAW 600 | S -450 450 450 -450 0 1 0 N 601 | X Vtp 1 -650 150 200 R 50 50 1 1 I 602 | X ~Q 10 650 -50 200 L 50 50 1 1 O 603 | X Q 11 650 50 200 L 50 50 1 1 O 604 | X GND 12 650 150 200 L 50 50 1 1 W 605 | X Vee 13 150 650 200 D 50 50 1 1 W 606 | X HYS 14 50 650 200 D 50 50 1 1 O 607 | X GND 15 -50 650 200 D 50 50 1 1 W 608 | X Vcc1 16 -150 650 200 D 50 50 1 1 W 609 | X GND 17 250 -650 200 U 50 50 1 1 W 610 | X Vp 2 -650 50 200 R 50 50 1 1 I 611 | X Vn 3 -650 -50 200 R 50 50 1 1 I 612 | X Vtn 4 -650 -150 200 R 50 50 1 1 I 613 | X Vcc1 5 -150 -650 200 U 50 50 1 1 W 614 | X ~LE 6 -50 -650 200 U 50 50 1 1 I 615 | X LE 7 50 -650 200 U 50 50 1 1 I 616 | X Vtt 8 150 -650 200 U 50 50 1 1 I 617 | X GND 9 650 -150 200 L 50 50 1 1 I 618 | ENDDRAW 619 | ENDDEF 620 | # 621 | # tdr-rescue_CDCLVP1204-synth_lib-tdr-rescue 622 | # 623 | DEF tdr-rescue_CDCLVP1204-synth_lib-tdr-rescue U 0 40 Y Y 1 F N 624 | F0 "U" -650 700 50 H V C CNN 625 | F1 "tdr-rescue_CDCLVP1204-synth_lib-tdr-rescue" -450 800 50 H V C CNN 626 | F2 "" -600 800 50 H I C CNN 627 | F3 "" -600 800 50 H I C CNN 628 | DRAW 629 | S 350 600 -350 -600 0 1 0 N 630 | X GND 1 -550 -400 200 R 50 50 1 1 I 631 | X OUTN0 10 550 400 200 L 50 50 1 1 O 632 | X OUTP1 11 550 200 200 L 50 50 1 1 O 633 | X OUTN1 12 550 100 200 L 50 50 1 1 O 634 | X OUTP2 13 550 -100 200 L 50 50 1 1 O 635 | X OUTN2 14 550 -200 200 L 50 50 1 1 O 636 | X OUTP3 15 550 -400 200 L 50 50 1 1 O 637 | X OUTN3 16 550 -500 200 L 50 50 1 1 O 638 | X GND 17 -550 -500 200 R 50 50 1 1 I 639 | X IN_SEL 2 -550 -250 200 R 50 50 1 1 I 640 | X INP1 3 -550 -50 200 R 50 50 1 1 I 641 | X INN1 4 -550 -150 200 R 50 50 1 1 I 642 | X VCC 5 -550 500 200 R 50 50 1 1 I 643 | X INP0 6 -550 150 200 R 50 50 1 1 I 644 | X INN0 7 -550 250 200 R 50 50 1 1 I 645 | X VAC_REF 8 -550 400 200 R 50 50 1 1 I 646 | X OUTP0 9 550 500 200 L 50 50 1 1 O 647 | ENDDRAW 648 | ENDDEF 649 | # 650 | # tdr-rescue_DV75D_TCXO-synth_lib-tdr-rescue 651 | # 652 | DEF tdr-rescue_DV75D_TCXO-synth_lib-tdr-rescue X 0 40 Y Y 1 F N 653 | F0 "X" -650 400 50 H V C CNN 654 | F1 "tdr-rescue_DV75D_TCXO-synth_lib-tdr-rescue" -450 300 50 H V C CNN 655 | F2 "" -650 400 50 H I C CNN 656 | F3 "" -650 400 50 H I C CNN 657 | DRAW 658 | S -200 200 300 -200 1 1 10 f 659 | P 8 1 1 0 25 -25 50 -25 50 25 75 25 75 -25 100 -25 100 25 125 25 N 660 | X NC 1 -300 0 100 R 50 50 1 1 N 661 | X GND 2 0 -300 100 U 50 50 1 1 W 662 | X OUT 3 400 0 100 L 50 50 1 1 O 663 | X V+ 4 0 300 100 D 50 50 1 1 W 664 | ENDDRAW 665 | ENDDEF 666 | # 667 | # tdr-rescue_ICS853S057I-tdr 668 | # 669 | DEF tdr-rescue_ICS853S057I-tdr U 0 40 Y Y 1 F N 670 | F0 "U" -500 650 50 H V C CNN 671 | F1 "tdr-rescue_ICS853S057I-tdr" -300 750 50 H V C CNN 672 | F2 "" -400 550 50 H I C CNN 673 | F3 "" -400 550 50 H I C CNN 674 | DRAW 675 | S -300 550 300 -550 0 1 0 N 676 | X Vcc 1 -500 450 200 R 50 50 1 1 W 677 | X Vee 10 -500 -450 200 R 50 50 1 1 W 678 | X Vee 11 500 -450 200 L 50 50 1 1 W 679 | X Vbb2 12 500 -350 200 L 50 50 1 1 W 680 | X Vbb1 13 500 -250 200 L 50 50 1 1 W 681 | X Vcc 14 500 -150 200 L 50 50 1 1 W 682 | X nQ 15 500 -50 200 L 50 50 1 1 O 683 | X Q 16 500 50 200 L 50 50 1 1 O 684 | X Vcc 17 500 150 200 L 50 50 1 1 W 685 | X SEL0 18 500 250 200 L 50 50 1 1 I 686 | X SEL1 19 500 350 200 L 50 50 1 1 I 687 | X CLK0 2 -500 350 200 R 50 50 1 1 I 688 | X Vcc 20 500 450 200 L 50 50 1 1 W 689 | X ~CLK0 3 -500 250 200 R 50 50 1 1 I 690 | X CLK1 4 -500 150 200 R 50 50 1 1 I 691 | X ~CLK1 5 -500 50 200 R 50 50 1 1 I 692 | X CLK2 6 -500 -50 200 R 50 50 1 1 I 693 | X ~CLK2 7 -500 -150 200 R 50 50 1 1 I 694 | X CLK3 8 -500 -250 200 R 50 50 1 1 I 695 | X ~CLK3 9 -500 -350 200 R 50 50 1 1 I 696 | ENDDRAW 697 | ENDDEF 698 | # 699 | # tdr-rescue_NB6L295MMNG-synth_lib-tdr-rescue 700 | # 701 | DEF tdr-rescue_NB6L295MMNG-synth_lib-tdr-rescue U 0 40 Y Y 1 F N 702 | F0 "U" -1050 700 50 H V C CNN 703 | F1 "tdr-rescue_NB6L295MMNG-synth_lib-tdr-rescue" -850 800 50 H V C CNN 704 | F2 "" 0 0 50 H I C CNN 705 | F3 "" 0 0 50 H I C CNN 706 | DRAW 707 | S -550 550 550 -550 0 1 10 N 708 | X VCC 1 -650 250 100 R 50 50 1 1 W 709 | X ~VT1 10 50 -650 100 U 50 50 1 1 P 710 | X GND 11 150 -650 100 U 50 50 1 1 W 711 | X VCC1 12 250 -650 100 U 50 50 1 1 W 712 | X ~Q1 13 650 -250 100 L 50 50 1 1 O 713 | X Q1 14 650 -150 100 L 50 50 1 1 O 714 | X VCC1 15 650 -50 100 L 50 50 1 1 W 715 | X VCC0 16 650 50 100 L 50 50 1 1 W 716 | X ~Q0 17 650 150 100 L 50 50 1 1 O 717 | X Q0 18 650 250 100 L 50 50 1 1 O 718 | X VCC0 19 200 650 100 D 50 50 1 1 W 719 | X ~EN 2 -650 150 100 R 50 50 1 1 I 720 | X GND 20 100 650 100 D 50 50 1 1 W 721 | X ~VT0 21 0 650 100 D 50 50 1 1 P 722 | X ~IN0 22 -100 650 100 D 50 50 1 1 I 723 | X IN0 23 -200 650 100 D 50 50 1 1 I 724 | X VT0 24 -300 650 100 D 50 50 1 1 P 725 | X EP 25 350 -650 100 U 50 50 1 1 W 726 | X SLOAD 3 -650 50 100 R 50 50 1 1 I 727 | X SDIN 4 -650 -50 100 R 50 50 1 1 I 728 | X SCLK 5 -650 -150 100 R 50 50 1 1 I 729 | X VCC 6 -650 -250 100 R 50 50 1 1 W 730 | X VT1 7 -250 -650 100 U 50 50 1 1 P 731 | X IN1 8 -150 -650 100 U 50 50 1 1 I 732 | X ~IN1 9 -50 -650 100 U 50 50 1 1 I 733 | ENDDRAW 734 | ENDDEF 735 | # 736 | # tdr-rescue_SY89321L-synth_lib-tdr-rescue 737 | # 738 | DEF tdr-rescue_SY89321L-synth_lib-tdr-rescue U 0 40 Y Y 1 F N 739 | F0 "U" -400 350 50 H V C CNN 740 | F1 "tdr-rescue_SY89321L-synth_lib-tdr-rescue" -250 450 50 H V C CNN 741 | F2 "" -100 0 50 H I C CNN 742 | F3 "" -100 0 50 H I C CNN 743 | DRAW 744 | S -250 250 250 -300 0 1 0 N 745 | X NC 1 -450 150 200 R 50 50 1 1 N 746 | X IN 2 -450 50 200 R 50 50 1 1 I 747 | X ~IN 3 -450 -50 200 R 50 50 1 1 I 748 | X VBB 4 -450 -150 200 R 50 50 1 1 W 749 | X GND 5 450 -150 200 L 50 50 1 1 W 750 | X NC 6 450 -50 200 L 50 50 1 1 N 751 | X Q 7 450 50 200 L 50 50 1 1 O 752 | X Vcc 8 450 150 200 L 50 50 1 1 W 753 | X GND 9 0 -500 200 U 50 50 1 1 W 754 | ENDDRAW 755 | ENDDEF 756 | # 757 | #End Library 758 | -------------------------------------------------------------------------------- /hardware/tdr.pro: -------------------------------------------------------------------------------- 1 | update=22/05/2015 07:44:53 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [pcbnew] 9 | version=1 10 | LastNetListRead= 11 | UseCmpFile=1 12 | PadDrill=0.600000000000 13 | PadDrillOvalY=0.600000000000 14 | PadSizeH=1.500000000000 15 | PadSizeV=1.500000000000 16 | PcbTextSizeV=1.500000000000 17 | PcbTextSizeH=1.500000000000 18 | PcbTextThickness=0.300000000000 19 | ModuleTextSizeV=1.000000000000 20 | ModuleTextSizeH=1.000000000000 21 | ModuleTextSizeThickness=0.150000000000 22 | SolderMaskClearance=0.000000000000 23 | SolderMaskMinWidth=0.000000000000 24 | DrawSegmentWidth=0.200000000000 25 | BoardOutlineThickness=0.100000000000 26 | ModuleOutlineThickness=0.150000000000 27 | [cvpcb] 28 | version=1 29 | NetIExt=net 30 | [eeschema] 31 | version=1 32 | LibDir= 33 | [eeschema/libraries] 34 | -------------------------------------------------------------------------------- /hardware/tdr.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:tdr-cache 3 | EELAYER 26 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 1 8 8 | Title "" 9 | Date "" 10 | Rev "" 11 | Comp "" 12 | Comment1 "" 13 | Comment2 "" 14 | Comment3 "" 15 | Comment4 "" 16 | $EndDescr 17 | $Sheet 18 | S 8400 750 1100 4600 19 | U 5BC3F686 20 | F0 "conn_power" 50 21 | F1 "conn_power.sch" 50 22 | F2 "EXT_TRIG" O R 9500 5150 50 23 | F3 "PULSE_OUT_P" I L 8400 950 50 24 | F4 "ANALOG_INPUT" O L 8400 4900 50 25 | F5 "PULSE_OUT_N" I L 8400 1050 50 26 | F6 "EXT_REF_P" O L 8400 4350 50 27 | F7 "EXT_REF_N" O L 8400 4450 50 28 | F8 "ANALOG_TRIG" O L 8400 3750 50 29 | F9 "PGOOD_3V3" O L 8400 3400 50 30 | $EndSheet 31 | $Sheet 32 | S 750 800 1000 6600 33 | U 5BC3F72A 34 | F0 "clock" 50 35 | F1 "clock.sch" 50 36 | F2 "EXT_CLK_P" I R 1750 7100 50 37 | F3 "EXT_CLK_N" I R 1750 7200 50 38 | F4 "CLK_PULSE_P" O R 1750 950 50 39 | F5 "CLK_PULSE_N" O R 1750 1050 50 40 | F6 "CLK_SAMPLE_P" O R 1750 2950 50 41 | F7 "CLK_SEL" I R 1750 6100 50 42 | F8 "EXT_TRIG" I R 1750 6850 50 43 | F9 "CLK_SAMPLE_N" O R 1750 3050 50 44 | F10 "CLK_FPGA" O R 1750 6350 50 45 | F11 "ANALOG_TRIG_INPUT" I R 1750 5650 50 46 | F12 "ANALOG_TRIG_REF" I R 1750 5750 50 47 | F13 "TRIG_SEL1" O R 1750 6600 50 48 | F14 "TRIG_SEL0" O R 1750 6500 50 49 | $EndSheet 50 | $Sheet 51 | S 6250 2750 1100 3100 52 | U 5BC41CC8 53 | F0 "comparator" 50 54 | F1 "comparator.sch" 50 55 | F2 "COMP_INPUT" I R 7350 4900 50 56 | F3 "REF_INPUT" I L 6250 4900 50 57 | F4 "~LATCH" I L 6250 3050 50 58 | F5 "LATCH" I L 6250 2950 50 59 | F6 "COMP_OUT" O R 7350 5650 50 60 | $EndSheet 61 | $Sheet 62 | S 6250 750 1100 1750 63 | U 5BC2B41E 64 | F0 "output_driver" 50 65 | F1 "output_driver.sch" 50 66 | F2 "PULSE_OUT_P" I R 7350 950 50 67 | F3 "PULSE_OUT_N" I R 7350 1050 50 68 | F4 "CLK_IN_P" I L 6250 950 50 69 | F5 "CLK_IN_N" I L 6250 1050 50 70 | $EndSheet 71 | Wire Wire Line 72 | 6000 950 6250 950 73 | Wire Wire Line 74 | 6000 1050 6250 1050 75 | Wire Wire Line 76 | 6000 4900 6250 4900 77 | Wire Wire Line 78 | 7350 5650 7600 5650 79 | Text Label 7600 5650 0 50 ~ 0 80 | COMPARATOR_OUTPUT 81 | Text Label 9750 5150 0 50 ~ 0 82 | EXT_TRIG 83 | Wire Wire Line 84 | 9750 5150 9500 5150 85 | Text Label 1850 6850 0 50 ~ 0 86 | EXT_TRIG 87 | Wire Wire Line 88 | 1850 7200 1750 7200 89 | Text Label 1850 7100 0 50 ~ 0 90 | EXT_CLK_P 91 | Wire Wire Line 92 | 1850 7100 1750 7100 93 | Text Label 1850 7200 0 50 ~ 0 94 | EXT_CLK_N 95 | Text Label 8300 4350 2 50 ~ 0 96 | EXT_CLK_P 97 | Text Label 8300 4450 2 50 ~ 0 98 | EXT_CLK_N 99 | Wire Wire Line 100 | 7350 4900 8400 4900 101 | Wire Wire Line 102 | 7350 950 8400 950 103 | Wire Wire Line 104 | 7350 1050 8400 1050 105 | Wire Wire Line 106 | 1850 6850 1750 6850 107 | Wire Wire Line 108 | 1850 3050 1750 3050 109 | Text Label 1850 2950 0 50 ~ 0 110 | CLK_SAMPLE_P 111 | Wire Wire Line 112 | 1850 2950 1750 2950 113 | Text Label 1850 3050 0 50 ~ 0 114 | CLK_SAMPLE_N 115 | Wire Wire Line 116 | 1850 1050 1750 1050 117 | Text Label 1850 950 0 50 ~ 0 118 | CLK_PULSE_P 119 | Wire Wire Line 120 | 1850 950 1750 950 121 | Text Label 1850 1050 0 50 ~ 0 122 | CLK_PULSE_N 123 | Text Label 4850 950 2 50 ~ 0 124 | CLK_PULSE_P 125 | Text Label 4850 1050 2 50 ~ 0 126 | CLK_PULSE_N 127 | Text Label 4700 2950 2 50 ~ 0 128 | CLK_SAMPLE_P 129 | Text Label 4700 3050 2 50 ~ 0 130 | CLK_SAMPLE_N 131 | Wire Wire Line 132 | 4850 950 5000 950 133 | Wire Wire Line 134 | 4850 1050 5000 1050 135 | Wire Wire Line 136 | 4850 2950 5000 2950 137 | Wire Wire Line 138 | 4850 3050 5000 3050 139 | Wire Wire Line 140 | 8300 4350 8400 4350 141 | Wire Wire Line 142 | 8300 4450 8400 4450 143 | Text Label 4250 3750 0 50 ~ 0 144 | COMPARATOR_OUTPUT 145 | Text Notes 1150 700 0 50 ~ 0 146 | 200 mA 147 | Text Notes 5100 650 0 50 ~ 0 148 | 170 mA typ, 120 mA for outputs? 149 | Text Notes 6550 700 0 50 ~ 0 150 | 60 mA 151 | Text Notes 6600 2700 0 50 ~ 0 152 | 80 mA 153 | Wire Wire Line 154 | 1750 6100 2800 6100 155 | Wire Wire Line 156 | 1750 6350 2800 6350 157 | Wire Wire Line 158 | 4100 1750 5000 1750 159 | Wire Wire Line 160 | 5000 1850 4100 1850 161 | Wire Wire Line 162 | 4100 1950 5000 1950 163 | Wire Wire Line 164 | 5000 2050 4100 2050 165 | $Sheet 166 | S 5000 750 1000 2700 167 | U 5BC64E97 168 | F0 "delay_pulse" 50 169 | F1 "delay.sch" 50 170 | F2 "~EN" I L 5000 1850 50 171 | F3 "DELAY0_IN" I L 5000 950 50 172 | F4 "~DELAY0_IN" I L 5000 1050 50 173 | F5 "DELAY1_IN" I L 5000 2950 50 174 | F6 "~DELAY1_IN" I L 5000 3050 50 175 | F7 "DELAY0_OUT" O R 6000 950 50 176 | F8 "~DELAY0_OUT" O R 6000 1050 50 177 | F9 "DELAY1_OUT" O R 6000 2950 50 178 | F10 "~DELAY1_OUT" O R 6000 3050 50 179 | F11 "SLOAD" I L 5000 1750 50 180 | F12 "SDIN" I L 5000 1950 50 181 | F13 "SCLK" I L 5000 2050 50 182 | $EndSheet 183 | Wire Wire Line 184 | 1750 6500 2800 6500 185 | Wire Wire Line 186 | 1750 6600 2800 6600 187 | Text Label 8300 3750 2 50 ~ 0 188 | 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/loxodes/tdr/5ad6947db3a3db398e9f3452fa06fbd07c2054f2/hardware/tdr_bom.ods -------------------------------------------------------------------------------- /hardware/trig_level_dac.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:tdr-cache 3 | EELAYER 26 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 7 8 8 | Title "" 9 | Date "" 10 | Rev "" 11 | Comp "" 12 | Comment1 "" 13 | Comment2 "" 14 | Comment3 "" 15 | Comment4 "" 16 | $EndDescr 17 | Text HLabel 2550 4800 0 50 Input ~ 0 18 | DAC_CS 19 | Text HLabel 2550 4700 0 50 Input ~ 0 20 | DAC_SCK 21 | Text HLabel 2550 4600 0 50 Input ~ 0 22 | DAC_SDI 23 | Text HLabel 8400 2850 2 50 Output ~ 0 24 | DAC_VOUT 25 | Text Notes 3900 3900 0 50 ~ 0 26 | DAC7563SDSCR 27 | Text HLabel 8450 5000 2 50 Output ~ 0 28 | TRIG_VOUT 29 | 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Wire Line 493 | 6550 4400 6550 4900 494 | Wire Wire Line 495 | 6550 4900 6850 4900 496 | $Comp 497 | L Device:R_Small R704 498 | U 1 1 5C2BC2C2 499 | P 6150 4400 500 | F 0 "R704" V 5954 4400 50 0000 C CNN 501 | F 1 "13k" V 6045 4400 50 0000 C CNN 502 | F 2 "Resistors_SMD:R_0402" H 6150 4400 50 0001 C CNN 503 | F 3 "~" H 6150 4400 50 0001 C CNN 504 | 1 6150 4400 505 | 0 1 1 0 506 | $EndComp 507 | Wire Wire Line 508 | 6250 4400 6550 4400 509 | Connection ~ 6550 4400 510 | $Comp 511 | L Device:R_Small R706 512 | U 1 1 5C2BD35E 513 | P 6200 5100 514 | F 0 "R706" V 6004 5100 50 0000 C CNN 515 | F 1 "13k" V 6095 5100 50 0000 C CNN 516 | F 2 "Resistors_SMD:R_0402" H 6200 5100 50 0001 C CNN 517 | F 3 "~" H 6200 5100 50 0001 C CNN 518 | 1 6200 5100 519 | 0 1 1 0 520 | $EndComp 521 | $Comp 522 | L Device:R_Small R708 523 | U 1 1 5C2BD402 524 | P 6550 5450 525 | F 0 "R708" H 6491 5404 50 0000 R CNN 526 | F 1 "10k" H 6491 5495 50 0000 R CNN 527 | F 2 "Resistors_SMD:R_0402" H 6550 5450 50 0001 C CNN 528 | F 3 "~" H 6550 5450 50 0001 C CNN 529 | 1 6550 5450 530 | -1 0 0 1 531 | $EndComp 532 | $Comp 533 | L power:GND #PWR0293 534 | U 1 1 5C2BD4BD 535 | P 6550 5700 536 | F 0 "#PWR0293" H 6550 5450 50 0001 C CNN 537 | F 1 "GND" H 6555 5527 50 0000 C CNN 538 | F 2 "" H 6550 5700 50 0001 C CNN 539 | F 3 "" H 6550 5700 50 0001 C CNN 540 | 1 6550 5700 541 | -1 0 0 -1 542 | $EndComp 543 | Wire Wire Line 544 | 6550 5550 6550 5700 545 | Wire Wire Line 546 | 6550 5350 6550 5100 547 | Wire Wire Line 548 | 6550 5100 6300 5100 549 | Wire Wire Line 550 | 6550 5100 6850 5100 551 | Connection ~ 6550 5100 552 | Wire Wire Line 553 | 5900 4400 6050 4400 554 | Text Label 5900 2250 2 50 ~ 0 555 | DAC_VREF 556 | $Comp 557 | L Device:R_Small R709 558 | U 1 1 5C2C520A 559 | P 7050 2250 560 | F 0 "R709" V 6854 2250 50 0000 C CNN 561 | F 1 "10k" V 6945 2250 50 0000 C CNN 562 | F 2 "Resistors_SMD:R_0402" H 7050 2250 50 0001 C CNN 563 | F 3 "~" H 7050 2250 50 0001 C CNN 564 | 1 7050 2250 565 | 0 1 1 0 566 | $EndComp 567 | Wire Wire Line 568 | 7150 2250 7600 2250 569 | Wire Wire Line 570 | 7600 2250 7600 2850 571 | Wire Wire Line 572 | 6950 2250 6550 2250 573 | Wire Wire Line 574 | 6550 2250 6550 2750 575 | Wire Wire Line 576 | 6550 2750 6850 2750 577 | $Comp 578 | L Device:R_Small R703 579 | U 1 1 5C2C5218 580 | P 6150 2250 581 | F 0 "R703" V 5954 2250 50 0000 C CNN 582 | F 1 "13k" V 6045 2250 50 0000 C CNN 583 | F 2 "Resistors_SMD:R_0402" H 6150 2250 50 0001 C CNN 584 | F 3 "~" H 6150 2250 50 0001 C CNN 585 | 1 6150 2250 586 | 0 1 1 0 587 | $EndComp 588 | Wire Wire Line 589 | 6250 2250 6550 2250 590 | Connection ~ 6550 2250 591 | $Comp 592 | L Device:R_Small R705 593 | U 1 1 5C2C5221 594 | P 6200 2950 595 | F 0 "R705" V 6004 2950 50 0000 C CNN 596 | F 1 "13k" V 6095 2950 50 0000 C CNN 597 | F 2 "Resistors_SMD:R_0402" H 6200 2950 50 0001 C CNN 598 | F 3 "~" H 6200 2950 50 0001 C CNN 599 | 1 6200 2950 600 | 0 1 1 0 601 | $EndComp 602 | $Comp 603 | L Device:R_Small R707 604 | U 1 1 5C2C5228 605 | P 6550 3300 606 | F 0 "R707" H 6491 3254 50 0000 R CNN 607 | F 1 "10k" H 6491 3345 50 0000 R CNN 608 | F 2 "Resistors_SMD:R_0402" H 6550 3300 50 0001 C CNN 609 | F 3 "~" H 6550 3300 50 0001 C CNN 610 | 1 6550 3300 611 | -1 0 0 1 612 | $EndComp 613 | $Comp 614 | L power:GND #PWR0294 615 | U 1 1 5C2C522F 616 | P 6550 3550 617 | F 0 "#PWR0294" H 6550 3300 50 0001 C CNN 618 | F 1 "GND" H 6555 3377 50 0000 C CNN 619 | F 2 "" H 6550 3550 50 0001 C CNN 620 | F 3 "" H 6550 3550 50 0001 C CNN 621 | 1 6550 3550 622 | -1 0 0 -1 623 | $EndComp 624 | Wire Wire Line 625 | 6550 3400 6550 3550 626 | Wire Wire Line 627 | 6550 3200 6550 2950 628 | Wire Wire Line 629 | 6550 2950 6300 2950 630 | Wire Wire Line 631 | 6550 2950 6850 2950 632 | Connection ~ 6550 2950 633 | Wire Wire Line 634 | 5900 2250 6050 2250 635 | Connection ~ 7600 2850 636 | Wire Wire Line 637 | 7600 2850 7850 2850 638 | Wire Wire Line 639 | 6100 2950 5300 2950 640 | Wire Wire Line 641 | 4500 4500 5300 4500 642 | Wire Wire Line 643 | 5300 4500 5300 5100 644 | Wire Wire Line 645 | 5300 5100 6100 5100 646 | Wire Wire Line 647 | 4500 4400 5300 4400 648 | $Comp 649 | L Device:C_Small C705 650 | U 1 1 5C2D1C28 651 | P 7050 1850 652 | F 0 "C705" V 6821 1850 50 0000 C CNN 653 | F 1 "10 pF" V 6912 1850 50 0000 C CNN 654 | F 2 "Capacitors_SMD:C_0402" H 7050 1850 50 0001 C CNN 655 | F 3 "~" H 7050 1850 50 0001 C CNN 656 | 1 7050 1850 657 | 0 1 1 0 658 | $EndComp 659 | Wire Wire Line 660 | 7150 1850 7600 1850 661 | Wire Wire Line 662 | 7600 1850 7600 2250 663 | Connection ~ 7600 2250 664 | Wire Wire Line 665 | 6950 1850 6550 1850 666 | Wire Wire Line 667 | 6550 1850 6550 2250 668 | $Comp 669 | L Device:C_Small C706 670 | U 1 1 5C2D5541 671 | P 7050 4050 672 | F 0 "C706" V 6821 4050 50 0000 C CNN 673 | F 1 "10 pF" V 6912 4050 50 0000 C CNN 674 | F 2 "Capacitors_SMD:C_0402" H 7050 4050 50 0001 C CNN 675 | F 3 "~" H 7050 4050 50 0001 C CNN 676 | 1 7050 4050 677 | 0 1 1 0 678 | $EndComp 679 | Wire Wire Line 680 | 7150 4050 7600 4050 681 | Wire Wire Line 682 | 7600 4050 7600 4400 683 | Connection ~ 7600 4400 684 | Wire Wire Line 685 | 6950 4050 6550 4050 686 | Wire Wire Line 687 | 6550 4050 6550 4400 688 | Wire Wire Line 689 | 5300 2950 5300 4400 690 | Text Notes 7900 3950 0 50 ~ 0 691 | gain of 0.8 692 | $Comp 693 | L Device:R_Small R712 694 | U 1 1 5C2F11A3 695 | P 7950 5000 696 | F 0 "R712" V 7754 5000 50 0000 C CNN 697 | F 1 "10k" V 7845 5000 50 0000 C CNN 698 | F 2 "Resistors_SMD:R_0402" H 7950 5000 50 0001 C CNN 699 | F 3 "~" H 7950 5000 50 0001 C CNN 700 | 1 7950 5000 701 | 0 1 1 0 702 | $EndComp 703 | Wire Wire Line 704 | 7600 5000 7850 5000 705 | Wire Wire Line 706 | 8050 5000 8150 5000 707 | $Comp 708 | L Device:R_Small R711 709 | U 1 1 5C2F573B 710 | P 7950 2850 711 | F 0 "R711" V 7754 2850 50 0000 C CNN 712 | F 1 "JMP" V 7845 2850 50 0000 C CNN 713 | F 2 "Resistors_SMD:R_0402" H 7950 2850 50 0001 C CNN 714 | F 3 "~" H 7950 2850 50 0001 C CNN 715 | 1 7950 2850 716 | 0 1 1 0 717 | $EndComp 718 | Wire Wire Line 719 | 8050 2850 8150 2850 720 | $Comp 721 | L Device:R_Small R713 722 | U 1 1 5C2F7AEE 723 | P 8150 3050 724 | F 0 "R713" V 7954 3050 50 0000 C CNN 725 | F 1 "DNP" V 8045 3050 50 0000 C CNN 726 | F 2 "Resistors_SMD:R_0402" H 8150 3050 50 0001 C CNN 727 | F 3 "~" H 8150 3050 50 0001 C CNN 728 | 1 8150 3050 729 | -1 0 0 1 730 | $EndComp 731 | Wire Wire Line 732 | 8150 2850 8150 2950 733 | Connection ~ 8150 2850 734 | Wire Wire Line 735 | 8150 2850 8400 2850 736 | $Comp 737 | L power:GND #PWR0295 738 | U 1 1 5C2F9F24 739 | P 8150 3250 740 | F 0 "#PWR0295" H 8150 3000 50 0001 C CNN 741 | F 1 "GND" H 8155 3077 50 0000 C CNN 742 | F 2 "" H 8150 3250 50 0001 C CNN 743 | F 3 "" H 8150 3250 50 0001 C CNN 744 | 1 8150 3250 745 | -1 0 0 -1 746 | $EndComp 747 | Wire Wire Line 748 | 8150 3150 8150 3250 749 | $Comp 750 | L Device:R_Small R714 751 | U 1 1 5C2FC601 752 | P 8150 5200 753 | F 0 "R714" V 7954 5200 50 0000 C CNN 754 | F 1 "DNP" V 8045 5200 50 0000 C CNN 755 | F 2 "Resistors_SMD:R_0402" H 8150 5200 50 0001 C CNN 756 | F 3 "~" H 8150 5200 50 0001 C CNN 757 | 1 8150 5200 758 | -1 0 0 1 759 | $EndComp 760 | $Comp 761 | L power:GND #PWR0296 762 | U 1 1 5C2FC609 763 | P 8150 5400 764 | F 0 "#PWR0296" H 8150 5150 50 0001 C CNN 765 | F 1 "GND" H 8155 5227 50 0000 C CNN 766 | F 2 "" H 8150 5400 50 0001 C CNN 767 | F 3 "" H 8150 5400 50 0001 C CNN 768 | 1 8150 5400 769 | -1 0 0 -1 770 | $EndComp 771 | Wire Wire Line 772 | 8150 5300 8150 5400 773 | Wire Wire Line 774 | 8150 5100 8150 5000 775 | Connection ~ 8150 5000 776 | Wire Wire Line 777 | 8150 5000 8450 5000 778 | Text Notes 6800 1400 0 50 ~ 0 779 | TODO: SIMULATE 780 | Wire Wire Line 781 | 4550 4800 4550 5600 782 | Wire Wire Line 783 | 4550 5600 3400 5600 784 | Wire Wire Line 785 | 3400 5600 3400 4900 786 | Wire Wire Line 787 | 3400 4900 3100 4900 788 | Wire Wire Line 789 | 2700 4900 2550 4900 790 | Text HLabel 2550 4900 0 50 Input ~ 0 791 | DAC_~CLR 792 | $Comp 793 | L Device:R_Small R701 794 | U 1 1 5C36F4E9 795 | P 3400 5850 796 | F 0 "R701" V 3596 5850 50 0000 C CNN 797 | F 1 "10k" V 3505 5850 50 0000 C CNN 798 | F 2 "Resistors_SMD:R_0402" H 3400 5850 50 0001 C CNN 799 | F 3 "~" H 3400 5850 50 0001 C CNN 800 | 1 3400 5850 801 | -1 0 0 1 802 | $EndComp 803 | $Comp 804 | L power:GND #PWR0149 805 | U 1 1 5C36F5ED 806 | P 3400 6050 807 | F 0 "#PWR0149" H 3400 5800 50 0001 C CNN 808 | F 1 "GND" H 3405 5877 50 0000 C CNN 809 | F 2 "" H 3400 6050 50 0001 C CNN 810 | F 3 "" H 3400 6050 50 0001 C CNN 811 | 1 3400 6050 812 | -1 0 0 -1 813 | $EndComp 814 | Wire Wire Line 815 | 3400 5600 3400 5750 816 | Connection ~ 3400 5600 817 | Wire Wire Line 818 | 3400 5950 3400 6050 819 | Text Notes 8200 4300 0 50 ~ 0 820 | TODO: WHAT IS THE STATE OF THIS AT STARTUP? 821 | Wire Wire Line 822 | 2150 3150 3200 3150 823 | Wire Wire Line 824 | 3200 3150 3200 4400 825 | Wire Wire Line 826 | 1300 4100 3100 4100 827 | Wire Wire Line 828 | 3100 4100 3100 4500 829 | $EndSCHEMATC 830 | -------------------------------------------------------------------------------- /software/README.md: -------------------------------------------------------------------------------- 1 | Scraps of software to test the TDR with beaglebone bit-banging. 2 | Eventually I'll replace this with an fpga programmed in migen... 3 | -------------------------------------------------------------------------------- /software/bbone_spi_bitbang.py: -------------------------------------------------------------------------------- 1 | from mmap_gpio import GPIO 2 | 3 | class bitbang_spi: 4 | def __init__(self, spi_cs, spi_mosi, spi_miso, spi_clk, rising_data = True, latch = None, enable_low = True): 5 | self.gpio = GPIO() 6 | 7 | self.rising_data = rising_data 8 | self.enable_low = enable_low 9 | 10 | self.spi_cs = spi_cs 11 | self.spi_mosi = spi_mosi 12 | self.spi_miso = spi_miso 13 | self.spi_clk = spi_clk 14 | self.latch = latch 15 | 16 | self.gpio.set_output(spi_cs) 17 | self.gpio.set_output(spi_mosi) 18 | self.gpio.set_output(spi_clk) 19 | 20 | if self.spi_miso != None: 21 | self.gpio.set_input(spi_miso) 22 | if self.latch != None: 23 | self.gpio.set_output(latch) 24 | 25 | self.gpio.set_value(spi_cs, self.enable_low) 26 | 27 | def transfer(self, payload, bits = 8): 28 | self.gpio.set_value(self.spi_cs, not self.enable_low) 29 | self.gpio.set_value(self.spi_clk, self.gpio.LOW) 30 | if self.latch != None: 31 | self.gpio.set_value(self.latch, self.gpio.LOW) 32 | 33 | response = 0 34 | for i in range(bits): 35 | response = response << 1 36 | # data clocked in on clock rising edge 37 | self.gpio.set_value(self.spi_mosi, (payload >> (bits - (i + 1))) & 0x01) 38 | self.gpio.set_value(self.spi_clk, self.gpio.HIGH) 39 | 40 | if self.spi_miso != None: 41 | response |= self.gpio.read_value(self.spi_miso) 42 | 43 | if self.latch!= None and i == bits - 1: 44 | self.gpio.set_value(self.latch, self.gpio.HIGH) 45 | 46 | self.gpio.set_value(self.spi_clk, self.gpio.LOW) 47 | 48 | if self.latch != None: 49 | self.gpio.set_value(self.latch, self.gpio.LOW) 50 | 51 | self.gpio.set_value(self.spi_cs, self.enable_low) 52 | 53 | 54 | return response 55 | -------------------------------------------------------------------------------- /software/init_gpio.sh: -------------------------------------------------------------------------------- 1 | config-pin P8_3 gpio 2 | config-pin P8_4 gpio 3 | config-pin P8_5 gpio 4 | config-pin P8_6 gpio 5 | config-pin P8_7 gpio 6 | config-pin P8_8 gpio 7 | config-pin P8_9 gpio 8 | config-pin P8_10 gpio 9 | config-pin P8_11 gpio 10 | config-pin P8_12 gpio 11 | config-pin P8_13 gpio 12 | config-pin P8_14 gpio 13 | config-pin P8_15 gpio 14 | -------------------------------------------------------------------------------- /software/mmap_gpio.py: -------------------------------------------------------------------------------- 1 | # mmap bit-banging io library 2 | 3 | # inspired by: 4 | # https://graycat.io/tutorials/beaglebone-io-using-python-mmap/ 5 | from mmap import mmap 6 | import time, struct 7 | 8 | class GPIO: 9 | def __init__(self): 10 | GPIO_offset = [0x44e07000, 0x4804c000, 0x481ac000, 0x481ae000] 11 | GPIO_size = 0xfff 12 | self.gpio_mem = [] 13 | 14 | self.HIGH = True 15 | self.LOW = False 16 | 17 | with open("/dev/mem", "r+b" ) as f: 18 | for offset in GPIO_offset: 19 | self.gpio_mem.append(mmap(f.fileno(), GPIO_size, offset=offset)) 20 | 21 | 22 | def _read_reg(self, port, offset): 23 | return struct.unpack("