├── .gitignore ├── LICENSE ├── README.md ├── Readme源码说明.txt ├── chapter2 ├── chapter2.cr.mti ├── chapter2.mpf ├── sim_chapter2.sv ├── testgen.sv ├── testintf.sv ├── testintfcmp.sv ├── testtf.sv ├── vish_stacktrace.vstf ├── vsim.wlf └── vsim_stacktrace.vstf ├── chapter3 ├── ch3.sv ├── chapter3.cr.mti ├── chapter3.mpf └── vsim.wlf ├── chapter4 ├── accumulator.sv ├── cc_event_handshake.sv ├── chapter4.cr.mti ├── chapter4.mpf ├── counter.sv ├── cross_cd_cnt_state.sv ├── cross_cd_trigger.sv ├── dcfifo.sv ├── decoder.sv ├── delay_chain.sv ├── delay_chain_mem.sv ├── digital_led.sv ├── digital_osc_trigger.sv ├── edge2en.sv ├── encoder.sv ├── key_process.sv ├── memory.sv ├── mux.sv ├── pulse_widen.sv ├── pwm.sv ├── quadrature_inc_enc.sv ├── scfifo.sv ├── shiftreg.sv ├── sim_dcfifo_wave.do ├── sim_delay_chain_mem.do ├── sim_keyprocess_wave.do ├── sim_mem_spramrf.do ├── sim_mem_spramrfsine.do ├── sim_oscope_trigsmp_wave.do ├── sim_pwm_wave.do ├── sim_qei_wave.do ├── sim_scfifo2_wave.do ├── sim_scfifo_wave.do ├── sim_stopwatch_wave.do ├── sindata8b256.dat ├── stop_watch_fsm.sv ├── test_cc_event_wave.do ├── test_cccnt_wave.do ├── test_mem_wave.do ├── test_pulse_widen_wave.do ├── vish_stacktrace.vstf └── vsim.wlf ├── chapter5 ├── chapter5.cr.mti ├── chapter5.mpf ├── counter.sv ├── iic_master.sv ├── iic_master_slave_test.sv ├── iic_slave.sv ├── iis.sv ├── sim_iic_wave_detail.do ├── sim_spi_wave.do ├── sim_spi_wave_detail.do ├── sim_uart_wave.do ├── spi.sv ├── transcript ├── uart.sv └── vsim.wlf ├── chapter6 ├── axi4.cr.mti ├── axi4.mpf ├── axi4full.sv ├── axi4lite.cr.mti ├── axi4lite_if.sv ├── axi4lite_master.sv ├── axi4lite_slave.sv ├── axi4lite_vivado_ip_template.sv ├── axi4s_fifo.sv ├── mm_intercon.sv ├── periph_pwm.sv ├── periph_spi.sv ├── pico_mm_if.cr.mti ├── pico_mm_if.mpf ├── sim_axi4lite_wave.do ├── sim_axi4s_wave.do ├── sim_pico_mm_if_wave.do ├── str_common.sv ├── str_pipe_controller.sv ├── test_axi4lite.sv ├── test_pico_mm_if.sv ├── vish_stacktrace.vstf └── vsim.wlf ├── chapter7 ├── chapter7.cr.mti ├── chapter7.mpf ├── cic.sv ├── cordic.cr.mti ├── cordic.mpf ├── cordic.sv ├── cordic2.cr.mti ├── cordic2.mpf ├── cordic2.sv ├── cordic_str.cr.mti ├── cordic_str.mpf ├── cordic_str.sv ├── dds.cr.mti ├── dds.mpf ├── dds.sv ├── div_str.sv ├── fft_mem.cr.mti ├── fft_mem.mpf ├── fir.cr.mti ├── fir.mpf ├── fir.sv ├── fixedpoint_pkg.sv.obs ├── iir.cr.mti ├── iir.mpf ├── iir.sv ├── intp_deci.sv ├── mm_fft.sv ├── muladd.sv ├── pid.sv ├── pid2.sv ├── r22sdf.cr.mti ├── r22sdf.mpf ├── r22sdf.sv ├── r2sdf.cr.mti ├── r2sdf.mpf ├── r2sdf.sv ├── sim_cordic2_wave.do ├── sim_cordic_str_wave.do ├── sim_cordic_wave.do ├── sim_fir_wave.do ├── sim_iir_wave.do ├── sim_mmfft.do ├── sim_pid_inverter.do ├── sim_r22sdf_1s_wave.do ├── sim_r22sdf_2s_wave.do ├── sim_r22sdf_3s_wave.do ├── sim_r22sdf_wave.do ├── sim_r2sdf_2s_wave.do ├── sim_r2sdf_4s_wave.do ├── sim_slow_div_wave.do ├── sim_slow_mul_wave.do ├── sim_slow_sqrt_wave.do ├── sim_sqrt_str_wave.do ├── sim_sr441to480.do ├── slow_div.sv ├── slow_mult.sv ├── slow_sqrt.sv ├── sqrt_str.sv ├── sr441to480.sv ├── test_fp_lets.sv ├── test_fp_pkg.cr.mti ├── test_fp_pkg.mpf ├── test_pid.cr.mti ├── test_pid.mpf ├── test_pid.sv ├── test_pid_2.cr.mti ├── test_pid_2.mpf ├── test_sqrt_str.cr.mti ├── test_sqrt_str.mpf ├── test_str_usdiv.cr.mti ├── test_str_usdiv.do ├── test_str_usdiv.mpf ├── up_down_sampling.cr.mti ├── up_down_sampling.mpf └── vsim.wlf ├── chapter8 ├── adpll.sv ├── am.sv ├── bpsk.sv ├── crc.sv ├── fm.sv ├── lfsr.sv ├── man_coding.sv ├── qam.sv ├── sim_am_wave.do ├── sim_bpsk_wave.do ├── sim_car_rec_wave.do ├── sim_car_rec_wave2.do ├── sim_fm_wave.do ├── sim_qam_iqth_wave.do ├── sim_qam_ova_wave.do ├── sim_qam_sj_wave.do ├── sim_qam_wave.do ├── test_am.cr.mti ├── test_am.mpf ├── test_baseband.sv ├── test_bb_sys.cr.mti ├── test_bb_sys.mpf ├── test_bbsys_wave.do ├── test_bbsys_wave_detail.do ├── test_bpsk.cr.mti ├── test_bpsk.mpf ├── test_carrier_recovery.cr.mti ├── test_carrier_recovery.mpf ├── test_fm.cr.mti ├── test_fm.mpf ├── test_qam16.cr.mti ├── test_qam16.mpf └── vsim.wlf ├── chisel ├── .gitignore ├── .idea │ ├── .gitignore │ ├── codeStyles │ │ ├── Project.xml │ │ └── codeStyleConfig.xml │ ├── misc.xml │ ├── modules.xml │ ├── scala_settings.xml │ └── vcs.xml ├── README.md ├── build.sbt ├── project │ └── plugins.sbt └── src │ ├── main │ └── scala │ │ ├── RenamePorts2AmbaConventions.md │ │ ├── gen_verilog.scala │ │ ├── loywong │ │ ├── accumulator.scala │ │ ├── axi4lite_to_localmm.scala │ │ ├── cordic.md │ │ ├── cordic.scala │ │ ├── cordic_iteration.ods │ │ ├── counter.scala │ │ ├── cross_clock_domain.scala │ │ ├── decoder.scala │ │ ├── delay_chain.scala │ │ ├── edge2en.scala │ │ ├── encoder.scala │ │ ├── memory.scala │ │ ├── scfifo.scala │ │ ├── shift_reg.scala │ │ ├── str_common.scala │ │ ├── str_pipe_control.scala │ │ └── util.scala │ │ └── temp.scala │ └── test │ └── scala │ ├── loywongtest │ ├── axi4lite_test_common.scala │ └── str_test_common.scala │ ├── temp.scala │ ├── test_accumulator.scala │ ├── test_axi4l_0.scala │ ├── test_str_0.scala │ ├── test_str_cordic_0.scala │ ├── test_str_cordic_1.scala │ ├── test_str_cordic_2.scala │ ├── test_str_dwc_0.scala │ ├── test_str_dwc_1.scala │ ├── test_str_dwc_2.scala │ ├── test_str_krm_0.scala │ ├── test_str_krm_1.scala │ └── test_str_krm_2.scala ├── common.sv ├── foreword.png ├── foreword.svg ├── 《FPGA应用开发和仿真》第一版第一次印刷勘误表(20190130).pdf ├── 《FPGA应用开发和仿真》第一版第一次印刷勘误表(Errata_20190531).pdf └── 《FPGA应用开发和仿真》第一版第一次印刷勘误表(Errata_20201022).pdf /.gitignore: -------------------------------------------------------------------------------- 1 | **/.DS_Store 2 | **/*.bak 3 | **/*.bkp 4 | **/*.wlf 5 | **/*.vstf 6 | **/wlft* 7 | **/work/ 8 | **/*.code-workspace 9 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 loykylewong (loywong@gmail.com) 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Readme源码说明.txt: -------------------------------------------------------------------------------- 1 | 源码内有Modelsim工程，其工程文件（mpf文件，实为文本文件）内对源文件等的引用采用的是绝对路径，如需要打开mpf工程复现仿真过程，需要先用文本编辑器打开mpf文件，查找替换文件路径至您下载解压后的文件路径。 2 | 3 | There ara Modelsim projects(created by ModelSim PE Student Edition 10.4a) in the source code. References to the source files in those project file (".mpf" file, a kind of text file) are absolute paths. 4 | If you need to open a mpf project to reproduce the simulation process, you have to open the mpf file with a text editor, find and replace those file paths to the paths of the files in your computer. 5 | -------------------------------------------------------------------------------- /chapter2/testgen.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module delaychain8 #( 3 | parameter DW = 8 4 | )( 5 | input wire clk, rst, en, 6 | input wire [DW - 1 : 0] in, 7 | output logic [DW - 1 : 0] out 8 | ); 9 | logic [DW - 1 : 0] dly[8]; 10 | always_ff@(posedge clk) begin 11 | if(rst) dly = '{8{'0}}; 12 | else if(en) begin 13 | dly[0:7] <= {in, dly[0:6]}; 14 | end 15 | end 16 | assign out = dly[7]; 17 | 18 | endmodule 19 | 20 | module fir #( 21 | parameter DW = 16, 22 | parameter TAPS = 32, 23 | parameter real COEF[TAPS] = '{TAPS{0.0}} 24 | )( 25 | input wire [$clog2(TAPS) - 1 : 0] addr, 26 | output logic signed [DW - 1 : 0] cout 27 | ); 28 | localparam FW = DW - 1; 29 | logic signed [DW - 1 : 0] coefs[TAPS]; 30 | 31 | generate 32 | for(genvar i = 0; i < TAPS; i++) begin :init_coefs 33 | assign coefs[i] = COEF[i] * (2.0 ** FW); 34 | end 35 | endgenerate 36 | 37 | always_comb begin 38 | cout = coefs[addr]; 39 | end 40 | 41 | endmodule 42 | 43 | //00-00, 44 | //01-01, 45 | //10-11, 46 | //11-10 47 | module gray2bin #( 48 | parameter DW = 8 49 | )( 50 | input wire [DW-1:0] gray, 51 | output var logic [DW-1:0] bin 52 | ); 53 | task nn(input [3:0] a, output logic [3:0] b); 54 | b = ~a; 55 | b = ^b; 56 | endtask 57 | generate 58 | for(genvar i = 0; i < DW; i++) begin// : binbits 59 | assign bin[i] = ^gray[DW-1:i]; 60 | end 61 | endgenerate 62 | endmodule 63 | 64 | module testgen; 65 | logic [3:0] addr = 4'b0; 66 | always #10 addr++; 67 | logic signed [15:0] cout; 68 | fir #(16, 4, '{0.3, 0.2, 0.56, -0.99}) the_fir(addr, cout); 69 | endmodule 70 | -------------------------------------------------------------------------------- /chapter2/testintf.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | interface membus #( 3 | parameter LEN = 256, DW = 8 4 | )( 5 | input wire clk, input wire rst 6 | ); 7 | logic [$clog2(LEN) - 1 : 0] addr; 8 | logic [DW - 1 : 0] d, q; 9 | logic wr; 10 | modport master( 11 | output addr, d, wr, 12 | input clk, rst, q 13 | ); 14 | modport slave( 15 | input clk, rst, addr, d, wr, 16 | output q 17 | ); 18 | endinterface 19 | 20 | module mem #( 21 | parameter LEN = 256, DW = 8 22 | )(membus.slave bus); 23 | 24 | logic [DW - 1 : 0] m[LEN] = '{LEN{'0}}; 25 | always_ff@(posedge bus.clk) begin 26 | if(bus.rst) m <= '{LEN{'0}}; 27 | else if(bus.wr) m[bus.addr] <= bus.d; 28 | end 29 | always_ff@(posedge bus.clk) begin 30 | if(bus.rst) bus.q <= '0; 31 | else bus.q <= m[bus.addr]; 32 | end 33 | endmodule 34 | 35 | module mem_tester #( 36 | parameter LEN = 256, DW = 8 37 | )(membus.master bus); 38 | initial bus.addr = '0; 39 | always@(posedge bus.clk) begin 40 | if(bus.rst) bus.addr <= '0; 41 | else bus.addr <= bus.addr + 1'b1; 42 | end 43 | assign bus.wr = 1'b1; 44 | assign bus.d = bus.addr; 45 | endmodule 46 | 47 | module testintf; 48 | logic clk = '0, rst = '0; 49 | always #5 clk = ~clk; 50 | initial begin 51 | #10 rst = '1; 52 | #20 rst = '0; 53 | end 54 | membus #(64,8) the_bus(clk, rst); 55 | mem_tester #(64,8) the_tester(the_bus); 56 | mem #(64,8) the_mem(the_bus); 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /chapter2/testintfcmp.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module mem #( 3 | parameter LEN = 256, DW = 8 4 | )( 5 | input wire clk, rst, 6 | input wire [$clog2(LEN) - 1 : 0] addr, 7 | input wire [DW - 1 : 0] d, 8 | input wire wr, 9 | output logic [DW - 1 : 0] q 10 | ); 11 | logic [DW - 1 : 0] m[LEN] = '{LEN{'0}}; 12 | always_ff@(posedge clk) begin 13 | if(rst) m <= '{LEN{'0}}; 14 | else if(wr) m[addr] <= d; 15 | end 16 | always_ff@(posedge clk) begin 17 | if(rst) q <= '0; 18 | else q <= m[addr]; 19 | end 20 | endmodule 21 | 22 | module mem_tester #( 23 | parameter LEN = 256, DW = 8 24 | )( 25 | input wire clk, rst, 26 | output logic [$clog2(LEN) - 1 : 0] addr, 27 | output logic [DW - 1 : 0] d, 28 | output logic wr, 29 | input wire [DW - 1 : 0] q 30 | ); 31 | initial addr = '0; 32 | always@(posedge clk) begin 33 | if(rst) addr <= '0; 34 | else addr <= addr + 1'b1; 35 | end 36 | assign wr = 1'b1; 37 | assign d = DW'(addr); 38 | endmodule 39 | 40 | module testintfcmp; 41 | logic clk = '0, rst = '0; 42 | always #5 clk = ~clk; 43 | initial begin 44 | #10 rst = '1; 45 | #20 rst = '0; 46 | end 47 | logic [5:0] addr; 48 | logic [7:0] d, q; 49 | logic wr; 50 | mem_tester #(64,8) the_tester(clk, rst, addr, d, wr, q); 51 | mem #(64,8) the_mem(clk, rst, addr, d, wr, q); 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /chapter2/testtf.sv: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter2/vish_stacktrace.vstf: -------------------------------------------------------------------------------- 1 | # Current time Sat Apr 15 13:14:48 2017 2 | # ModelSim PE Student Edition Stack Trace 3 | # Program = vish 4 | # Id = "10.4a" 5 | # Version = "2015.03" 6 | # Date = "Apr 7 2015" 7 | # Platform = win32pe 8 | 9 | Exception c0000005 has occurred at address 0055b612. Traceback: 10 | -------------------------------------------------------------------------------- /chapter2/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter2/vsim.wlf -------------------------------------------------------------------------------- /chapter2/vsim_stacktrace.vstf: -------------------------------------------------------------------------------- 1 | # Current time Fri Apr 14 16:24:55 2017 2 | # ModelSim PE Student Edition Stack Trace 3 | # Program = vsim 4 | # Id = "10.4a" 5 | # Version = "2015.03" 6 | # Date = "Apr 7 2015" 7 | # Platform = win32pe 8 | # Signature = ac8c563de6ee885313f1754f0d1a83f5 9 | # --> START OF USERCODE 10 | # 0 0x738fb6df: 'memset + 0x5f' in 'c:\windows\winsxs\x86_microsoft.vc90.crt_1fc8b3b9a1e18e3b_9.0.30729.9247_none_5090cb78bcba4a35\msvcr90.dll' 11 | # <-- END OF USERCODE 12 | # 1 0x006df66a: '' 13 | # 2 0x00510505: '' 14 | # 3 0x00f69a7d: '' 15 | # 4 0x004011c5: '' 16 | # 5 0x0051d50d: '' 17 | # 6 0x00521936: '' 18 | # 7 0x00521a09: '' 19 | # 8 0x00521a28: '' 20 | # 9 0x007274d3: '' 21 | # 10 0x0081c9dd: '' 22 | # 11 0x774a04a8: 'LdrSetAppCompatDllRedirectionCallback + 0x1d288' in 'c:\windows\system32\ntdll.dll' 23 | # 12 0x7745f1ba: 'RtlUnwind + 0x1ba' in 'c:\windows\system32\ntdll.dll' 24 | # 13 0x774708ef: 'KiUserExceptionDispatcher + 0xf' in 'c:\windows\system32\ntdll.dll' 25 | # 14 0x006df66a: '' 26 | # 15 0x004e8c06: '' 27 | # 16 0xff0c4c4c: '' 28 | # 17 0x0040105c: '' 29 | # 18 0x00443d64: '' 30 | # End of Stack Trace 31 | 32 | 33 | # Current time Fri Apr 14 16:48:20 2017 34 | # ModelSim PE Student Edition Stack Trace 35 | # Program = vsim 36 | # Id = "10.4a" 37 | # Version = "2015.03" 38 | # Date = "Apr 7 2015" 39 | # Platform = win32pe 40 | # Signature = ac8c563de6ee885313f1754f0d1a83f5 41 | # --> START OF USERCODE 42 | # 0 0x738fb6df: 'memset + 0x5f' in 'c:\windows\winsxs\x86_microsoft.vc90.crt_1fc8b3b9a1e18e3b_9.0.30729.9247_none_5090cb78bcba4a35\msvcr90.dll' 43 | # <-- END OF USERCODE 44 | # 1 0x006df66a: '' 45 | # 2 0x00510505: '' 46 | # 3 0x00f69a7d: '' 47 | # 4 0x004011c5: '' 48 | # 5 0x0051d50d: '' 49 | # 6 0x00521936: '' 50 | # 7 0x00521a09: '' 51 | # 8 0x00521a28: '' 52 | # 9 0x007274d3: '' 53 | # 10 0x0081c9dd: '' 54 | # 11 0x774a04a8: 'LdrSetAppCompatDllRedirectionCallback + 0x1d288' in 'c:\windows\system32\ntdll.dll' 55 | # 12 0x7745f1ba: 'RtlUnwind + 0x1ba' in 'c:\windows\system32\ntdll.dll' 56 | # 13 0x774708ef: 'KiUserExceptionDispatcher + 0xf' in 'c:\windows\system32\ntdll.dll' 57 | # 14 0x006df66a: '' 58 | # 15 0x004e8c06: '' 59 | # 16 0xff0c0fda: '' 60 | # 17 0x0040105c: '' 61 | # 18 0x00443d64: '' 62 | # End of Stack Trace 63 | 64 | 65 | -------------------------------------------------------------------------------- /chapter3/chapter3.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter3/ch3.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter3/ch3.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package simSrcGen 4 | -- Compiling module test_ch3 5 | -- Compiling module code3_3 6 | -- Compiling module code3_4 7 | -- Compiling module code3_5 8 | -- Compiling module code3_6_7 9 | -- Compiling module code3_8 10 | -- Compiling module code3_9 11 | -- Importing package simSrcGen 12 | -- Compiling module code3_10 13 | -- Compiling module bin2gray 14 | -- Compiling package Q15Types 15 | -- Compiling module code3_11 16 | -- Importing package Q15Types 17 | 18 | Top level modules: 19 | test_ch3 20 | code3_3 21 | code3_4 22 | code3_5 23 | code3_6_7 24 | code3_8 25 | code3_9 26 | code3_10 27 | 28 | } {} {}} 29 | -------------------------------------------------------------------------------- /chapter3/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter3/vsim.wlf -------------------------------------------------------------------------------- /chapter4/accumulator.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | `default_nettype none 3 | `include "../Common.sv" 4 | module TestAccu; 5 | import SimSrcGen::*; 6 | logic clk; 7 | initial GenClk(clk, 2, 10); 8 | logic rst; 9 | initial GenRst(clk, rst, 1, 1); 10 | logic [15:0] d = '0, acc; 11 | always #10 d++; 12 | Accumulator #(16) theAcc(clk, rst, 1'b1, d, acc); 13 | logic [5:0] dm = '0, accm; 14 | always #10 dm++; 15 | AccuM #(50) theAccM(clk, rst, 1'b1, dm, accm); 16 | endmodule 17 | 18 | module Accumulator #( parameter DW = 8 )( 19 | input wire clk, rst, en, 20 | input wire [DW - 1 : 0] d, 21 | output logic [DW - 1 : 0] acc 22 | ); 23 | always_ff@(posedge clk) begin 24 | if(rst) acc <= '0; 25 | else if(en) acc <= acc + d; 26 | end 27 | endmodule 28 | 29 | module AccuM #( parameter M = 100 )( 30 | input wire clk, rst, en, 31 | input wire [$clog2(M) - 1 : 0] d, 32 | output logic [$clog2(M) - 1 : 0] acc 33 | ); 34 | logic [$clog2(M) - 1 : 0] acc_next; 35 | always_comb begin 36 | acc_next = acc + d; 37 | if(acc_next >= M || acc_next < acc) 38 | acc_next -= M; 39 | end 40 | always_ff@(posedge clk) begin 41 | if(rst) acc <= '0; 42 | else if(en) acc <= acc_next; 43 | end 44 | endmodule 45 | -------------------------------------------------------------------------------- /chapter4/cc_event_handshake.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | 4 | module TestCCEvent; 5 | import SimSrcGen::*; 6 | logic clk_a, clk_b; 7 | initial GenClk(clk_a, 2, 10); 8 | initial GenClk(clk_b, 1, 12); 9 | logic in = 0; 10 | initial begin 11 | #100 in = 1; 12 | #10 in = 0; 13 | #80 in = 1; 14 | #10 in = 0; 15 | end 16 | logic busy, out; 17 | CrossClkEvent theCCEvent(clk_a, clk_b, in, busy, out); 18 | endmodule 19 | 20 | module CrossClkEvent ( 21 | input wire clk_a, clk_b, 22 | input wire in, // domain a 23 | output logic busy, // domain a 24 | output logic out // domain b 25 | ); 26 | logic ra0 = '0, ra1 = '0, ra2 = '0; 27 | logic rb0 = '0, rb1 = '0, rb2 = '0; 28 | // === clk_a domain === 29 | always_ff@(posedge clk_a) begin 30 | if(in) ra0 <= 1'b1; 31 | else if(ra2) ra0 <= 1'b0; 32 | end 33 | always_ff@(posedge clk_a) begin 34 | {ra2, ra1} <= {ra1, rb1}; 35 | end 36 | assign busy = ra0 | ra2; 37 | // === clk_b domain === 38 | always_ff@(posedge clk_b) begin 39 | {rb2, rb1, rb0} <= {rb1, rb0, ra0}; 40 | end 41 | assign out = rb1 & ~rb2; 42 | endmodule 43 | -------------------------------------------------------------------------------- /chapter4/counter.sv: -------------------------------------------------------------------------------- 1 | `ifndef __COUNTER_SV__ 2 | `define __COUNTER_SV__ 3 | 4 | `include "../common.sv" 5 | `default_nettype none 6 | 7 | module TestCounter; 8 | import SimSrcGen::*; 9 | logic clk; 10 | logic rst; 11 | logic en; 12 | initial GenClk(clk, 2, 10); 13 | initial GenRst(clk, rst, 10, 1); 14 | initial begin 15 | en = 1'b1; 16 | #100 en = 1'b0; 17 | #100 en = 1'b1; 18 | end 19 | logic [6:0] cnt; 20 | logic co; 21 | Counter #(128) theCnt(clk, rst, en, cnt, co); 22 | endmodule 23 | 24 | module TestCntSecMinHr; 25 | import SimSrcGen::*; 26 | logic clk; 27 | logic rst; 28 | initial GenClk(clk, 0, 100ms); 29 | initial GenRst(clk, rst, 0, 1); 30 | logic [5:0] sec, min; 31 | logic [4:0] hr; 32 | CntSecMinHr theCntSMH(clk, rst, sec, min, hr); 33 | endmodule 34 | 35 | module CntSecMinHr( 36 | input wire clk, rst, 37 | output logic [5:0] sec, 38 | output logic [5:0] min, 39 | output logic [4:0] hr 40 | ); 41 | logic en1sec, en1min, en1hr; 42 | Counter #(10) cnt1sec (.clk(clk), .rst(rst), .en( 1'b1), .cnt(), .co(en1sec)); 43 | Counter #(60) cnt60sec(.clk(clk), .rst(rst), .en(en1sec), .cnt(sec), .co(en1min)); 44 | Counter #(60) cnt60min(.clk(clk), .rst(rst), .en(en1min), .cnt(min), .co(en1hr )); 45 | Counter #(24) cnt24hr (.clk(clk), .rst(rst), .en(en1hr ), .cnt(hr ), .co()); 46 | endmodule 47 | 48 | module Counter #( 49 | parameter M = 100 50 | )( 51 | input wire clk, rst, en, 52 | output logic [$clog2(M) - 1 : 0] cnt, 53 | output logic co 54 | ); 55 | assign co = en & (cnt == M - 1); 56 | always_ff@(posedge clk) begin 57 | if(rst) cnt <= '0; 58 | else if(en) begin 59 | if(cnt < M - 1) cnt <= cnt + 1'b1; 60 | else cnt <= '0; 61 | end 62 | end 63 | endmodule 64 | 65 | module CounterMax #( 66 | parameter DW = 8 67 | )( 68 | input wire clk, rst, en, 69 | input wire [DW - 1 : 0] max, 70 | output logic [DW - 1 : 0] cnt, 71 | output logic co 72 | ); 73 | assign co = en & (cnt == max); 74 | always_ff@(posedge clk) begin 75 | if(rst) cnt <= '0; 76 | else if(en) begin 77 | if(cnt < max) cnt <= cnt + 1'b1; 78 | else cnt <= '0; 79 | end 80 | end 81 | endmodule 82 | 83 | `endif 84 | -------------------------------------------------------------------------------- /chapter4/cross_cd_cnt_state.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | module TestCCCnt; 4 | import SimSrcGen::*; 5 | logic clk_a, clk_b; 6 | initial GenClk(clk_a, 2, 10); 7 | initial GenClk(clk_b, 1, 9); 8 | logic inc = 0; 9 | always #10 inc = $random(); 10 | logic [7:0] cnt_a, cnt_b; 11 | CrossClkCnt theCCCnt(clk_a, clk_b, inc, cnt_a, cnt_b); 12 | endmodule 13 | 14 | module CrossClkCnt #( parameter W = 8 )( 15 | input wire clk_a, clk_b, 16 | input wire rst_a, rst_b, 17 | input wire inc, 18 | output logic [W - 1 : 0] cnt_a = '0, cnt_b 19 | ); 20 | // === clk_a domain === 21 | logic [W - 1 : 0] bin_next; 22 | logic [W - 1 : 0] gray, gray_next; 23 | always_comb begin 24 | bin_next = cnt_a + inc; 25 | gray_next = bin_next ^ (bin_next >> 1); 26 | end 27 | always_ff@(posedge clk_a) begin 28 | if(rst_a) begin 29 | cnt_a <= '0; 30 | gray <= '0; 31 | end 32 | else begin 33 | cnt_a <= bin_next; 34 | gray <= gray_next; 35 | end 36 | end 37 | // === clk_b domain === 38 | logic [W - 1 : 0] gray_sync[2]; 39 | always_ff@(posedge clk_b) begin 40 | if(rst_b) begin 41 | gray_sync <= {W'(0), W'(0)}; 42 | end 43 | else begin 44 | gray_sync <= {gray, gray_sync[0]}; 45 | end 46 | end 47 | always_comb begin 48 | for(int i = 0; i < W; i++) 49 | cnt_b[i] = ^(gray_sync[1] >> i); 50 | end 51 | endmodule 52 | -------------------------------------------------------------------------------- /chapter4/cross_cd_trigger.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | module TestCcdTrigger; 4 | import SimSrcGen::*; 5 | logic clk_a, clk_b; 6 | initial GenClk(clk_a, 2, 10); 7 | initial GenClk(clk_b, 1, 9); 8 | logic trig_i = 0; 9 | always #10 trig_i = $random(); 10 | logic trig_o; 11 | CcdTrigger theCcdTrigger(clk_a, clk_b, trig_i, trig_o); 12 | endmodule 13 | 14 | module CcdTrigger #( 15 | parameter int SYNC_STG = 2 // must be no less than 1 16 | )( 17 | input clk_a, 18 | input trig_i, 19 | input clk_b, 20 | output logic trig_o 21 | ); 22 | // ---- domain a ---- 23 | logic toggle_a = 1'b0; 24 | always_ff@(posedge clk_a) 25 | begin 26 | if(trig_i) 27 | begin 28 | toggle_a <= ~toggle_a; 29 | end 30 | end 31 | // ---- domain b ---- 32 | logic [SYNC_STG:0] toggle_b; 33 | always_ff@(posedge clk_b) 34 | begin 35 | toggle_b <= {toggle_b[SYNC_STG-1:0], toggle_a}; 36 | end 37 | always_ff@(posedge clk_b) 38 | begin 39 | trig_o <= ^toggle_b[SYNC_STG-:2]; 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /chapter4/decoder.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | module TestDecoder; 4 | import CombFunctions::*; 5 | logic [2:0] a = 5'b0; 6 | logic [7:0] y; 7 | always #10 a++; 8 | Decoder #(3) theDec(a, y); 9 | endmodule 10 | 11 | module Decoder #( 12 | parameter INW = 4 13 | )( 14 | input wire [INW - 1 : 0] in, 15 | output logic [2**INW - 1 : 0] out 16 | ); 17 | assign out = (2**INW)'(1) << in; 18 | endmodule 19 | -------------------------------------------------------------------------------- /chapter4/delay_chain.sv: -------------------------------------------------------------------------------- 1 | `ifndef __DELAY_CHAIN_SV__ 2 | `define __DELAY_CHAIN_SV__ 3 | 4 | `timescale 1ns/1ps 5 | `default_nettype none 6 | `include "../Common.sv" 7 | 8 | module TestDelayChain; 9 | import SimSrcGen::*; 10 | logic [7:0] a, y; 11 | logic clk; 12 | logic rst; 13 | initial GenClk(clk, 2, 10); 14 | initial GenRst(clk, rst, 1, 2); 15 | always #10 a = $random(); 16 | DelayChain #(8,0) dc(clk, rst, 1'b1, a, y); 17 | endmodule 18 | 19 | module DelayChain #( 20 | parameter DW = 8, 21 | parameter LEN = 4 22 | )( 23 | input wire clk, rst, en, 24 | input wire [DW - 1 : 0] in, 25 | output logic [DW - 1 : 0] out 26 | ); 27 | generate 28 | if(LEN == 0) begin 29 | assign out = in; 30 | end 31 | else if(LEN == 1) begin 32 | logic [DW - 1 : 0] dly; 33 | always_ff@(posedge clk) begin 34 | if(rst) dly = '0; 35 | else if(en) dly <= in; 36 | end 37 | assign out = dly; 38 | end 39 | else begin 40 | logic [DW - 1 : 0] dly[0 : LEN - 1]; 41 | always_ff@(posedge clk) begin 42 | if(rst) dly = '{LEN{'0}}; 43 | else if(en) dly[0 : LEN - 1] <= {in, dly[0 : LEN - 2]}; 44 | end 45 | assign out = dly[LEN - 1]; 46 | end 47 | endgenerate 48 | endmodule 49 | 50 | `endif 51 | -------------------------------------------------------------------------------- /chapter4/digital_led.sv: -------------------------------------------------------------------------------- 1 | 2 | module Bin2Bcd ( 3 | input wire clk, 4 | input wire [7 : 0] bin, 5 | output logic [2 : 0][3 : 0] bcd 6 | ); 7 | logic [7 : 0] bin_temp; 8 | logic [2 : 0][3 : 0] bcd_temp; 9 | always@(posedge clk) begin 10 | if(bin_temp >= 8'd100) begin 11 | bin_temp <= bin_temp - 8'd100; 12 | bcd_temp <= bcd_temp + 12'h100; 13 | end 14 | else if(bin_temp >= 8'd010) begin 15 | bin_temp <= bin_temp - 8'd010; 16 | bcd_temp <= bcd_temp + 12'h010; 17 | end 18 | else if(bin_temp >= 8'd001) begin 19 | bin_temp <= bin_temp - 8'd001; 20 | bcd_temp <= bcd_temp + 12'h001; 21 | end 22 | else begin 23 | bin_temp <= bin; 24 | bcd_temp <= 20'h0; 25 | bcd <= bcd_temp; 26 | end 27 | end 28 | endmodule 29 | 30 | module DigitalLedSeg ( 31 | input wire clk, 32 | input wire [3 : 0] in, 33 | output logic [6 : 0] seg 34 | ); 35 | logic [6:0] segs[16] = '{ 36 | 7'h3f, 7'h06, 7'h5b, 7'h4f, 7'h66, 7'h6d, 7'h7d, 7'h07, 37 | 7'h7f, 7'h6f, 7'h77, 7'h7c, 7'h39, 7'h5e, 7'h79, 7'h71}; 38 | always_ff@(posedge clk) seg <= segs[in]; 39 | endmodule 40 | -------------------------------------------------------------------------------- /chapter4/edge2en.sv: -------------------------------------------------------------------------------- 1 | `ifndef __EDEG2EN_SV__ 2 | `define __EDEG2EN_SV__ 3 | 4 | `include "../common.sv" 5 | 6 | `timescale 1ns/1ps 7 | `default_nettype none 8 | module TestEdge2En; 9 | import SimSrcGen::*; 10 | logic clk; 11 | initial GenClk(clk, 2, 10); 12 | logic in; 13 | initial begin 14 | in = 0; 15 | #44 in = 1; 16 | #56 in = 0; 17 | end 18 | logic en0, en1, en2; 19 | Rising2En #(0) theR2E0(clk, in, en0, ); 20 | Rising2En theR2E1(clk, in, en1, ); 21 | Rising2En #(2) theR2E2(clk, in, en2, ); 22 | endmodule 23 | 24 | module Rising2En #( parameter SYNC_STG = 1 )( 25 | input wire clk, in, 26 | output logic en, out 27 | ); 28 | logic [SYNC_STG : 0] dly; 29 | always_ff@(posedge clk) begin 30 | dly <= {dly[SYNC_STG - 1 : 0], in}; 31 | end 32 | assign en = (SYNC_STG ? dly[SYNC_STG -: 2] : {dly, in}) == 2'b01; 33 | assign out = dly[SYNC_STG]; 34 | endmodule 35 | 36 | module Falling2En #( parameter SYNC_STG = 1 )( 37 | input wire clk, in, 38 | output logic en, out 39 | ); 40 | logic [SYNC_STG : 0] dly; 41 | always_ff@(posedge clk) begin 42 | dly <= {dly[SYNC_STG - 1 : 0], in}; 43 | end 44 | assign en = (SYNC_STG ? dly[SYNC_STG -: 2] : {dly, in}) == 2'b10; 45 | assign out = dly[SYNC_STG]; 46 | endmodule 47 | 48 | module Edge2En #( parameter SYNC_STG = 1 )( 49 | input wire clk, in, 50 | output logic rising, falling, out 51 | ); 52 | logic [SYNC_STG : 0] dly; 53 | always_ff@(posedge clk) begin 54 | dly <= {dly[SYNC_STG - 1 : 0], in}; 55 | end 56 | assign rising = (SYNC_STG ? dly[SYNC_STG -: 2] : {dly, in}) == 2'b01; 57 | assign falling = (SYNC_STG ? dly[SYNC_STG -: 2] : {dly, in}) == 2'b10; 58 | assign out = dly[SYNC_STG]; 59 | endmodule 60 | 61 | `endif 62 | -------------------------------------------------------------------------------- /chapter4/encoder.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | module TestEncoder; 4 | import CombFunctions::*; 5 | logic [7:0] a = 5'b0; 6 | logic [2:0] y; 7 | always #10 a++; 8 | // Encoder #(3) theEnc(a, y); 9 | `DEF_PRIO_ENC(PrioEnc8to3, 3) 10 | always_comb y = PrioEnc8to3(a); 11 | endmodule 12 | 13 | module Encoder #( 14 | parameter OUTW = 4 15 | )( 16 | input wire [2**OUTW - 1 : 0] in, 17 | output logic [OUTW - 1 : 0] out 18 | ); 19 | always_comb begin 20 | out = '0; 21 | for(integer i = 2**OUTW - 1; i >= 0; i--) begin 22 | if(in[i]) out = OUTW'(i); 23 | end 24 | end 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /chapter4/key_process.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ms/1us 2 | `default_nettype none 3 | `include "../Common.sv" 4 | module TestKeyProcess; 5 | import SimSrcGen::GenClk; 6 | logic clk; 7 | initial GenClk(clk, 0.02, 0.1); 8 | task automatic KeyPress(ref logic key, input realtime t); 9 | for(int i = 0; i < 30; i++) begin 10 | #0.13ms key = '0; #0.12ms key = '1; 11 | end 12 | #t; key = '0; 13 | endtask 14 | logic key = '0, key_en; 15 | initial begin 16 | #10 KeyPress(key, 50); 17 | #50 KeyPress(key, 50); 18 | end 19 | KeyProcess #(100, 1) theKeyProc(clk, key, key_en); 20 | endmodule 21 | 22 | module KeyProcess #( 23 | parameter SMP_INTV = 1_000_000, 24 | parameter KEY_NUM = 1 25 | )( 26 | input wire clk, 27 | input wire [KEY_NUM - 1 : 0] key, 28 | output logic [KEY_NUM - 1 :0] key_en 29 | ); 30 | logic [$clog2(SMP_INTV) - 1 : 0] smp_cnt = '0; 31 | wire en_intv = (smp_cnt == SMP_INTV - 1); 32 | always_ff@(posedge clk) begin 33 | if(smp_cnt < SMP_INTV - 1) smp_cnt <= smp_cnt + 1'b1; 34 | else smp_cnt <= '0; 35 | end 36 | logic [KEY_NUM - 1 : 0] key_reg[2] = '{2{'0}}; 37 | always_ff@(posedge clk) begin 38 | if(en_intv) key_reg[0] <= key; 39 | key_reg[1] <= key_reg[0]; 40 | end 41 | assign key_en = ~key_reg[1] & key_reg[0]; 42 | endmodule 43 | -------------------------------------------------------------------------------- /chapter4/mux.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | module TestMux; 4 | logic [7:0] a[4] = '{4{'0}}, y; 5 | logic [1:0] sel = '0; 6 | always #10 a[0]++; 7 | always #20 a[1]++; 8 | always #40 a[2]++; 9 | always #80 a[3]++; 10 | always #160 sel++; 11 | Mux #(8, 4) theMux(a, sel, y); 12 | endmodule 13 | 14 | module Mux #( 15 | parameter DW = 8, 16 | parameter CH = 4 17 | )( 18 | input wire [DW - 1 : 0] in[CH], 19 | input wire [$clog2(CH) - 1 : 0] sel, 20 | output logic [DW - 1 : 0] out 21 | ); 22 | assign out = in[sel]; 23 | endmodule 24 | -------------------------------------------------------------------------------- /chapter4/pulse_widen.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | `default_nettype none 3 | `include "../Common.sv" 4 | module TestPulseWiden; 5 | import SimSrcGen::*; 6 | logic clk; 7 | initial GenClk(clk, 2, 10); 8 | logic in; 9 | initial begin 10 | in = 0; 11 | #44 in = 1; 12 | #56 in = 0; 13 | #100 in = 1; 14 | #10 in = 0; 15 | end 16 | logic out, out2, out3; 17 | PulseWiden #(4) pw1(clk, in, out); 18 | PulseWiden #(2) pw2(clk, in, out2); 19 | PulseWiden #(3) pw3(clk, in, out3); 20 | endmodule 21 | 22 | module PulseWiden #( parameter RATIO = 1 )( 23 | input wire clk, in, 24 | output logic out 25 | ); 26 | logic [$clog2(RATIO + 1) - 1 : 0] cnt = '0; 27 | always_ff@(posedge clk) begin 28 | if(in) cnt <= RATIO; 29 | else if(cnt > 0) cnt <= cnt - 1'b1; 30 | end 31 | assign out = cnt > 0; 32 | endmodule 33 | -------------------------------------------------------------------------------- /chapter4/quadrature_inc_enc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | `default_nettype none 3 | `include "../Common.sv" 4 | module TestQuadEncIf; 5 | import SimSrcGen::*; 6 | task automatic QuadEncGo(ref logic a, b, input logic ccw, realtime qprd); 7 | a = 0; b = 0; 8 | if(!ccw) begin 9 | #qprd a = 1; #qprd b = 1; #qprd a = 0; #qprd b = 0; 10 | end 11 | else begin 12 | #qprd b = 1; #qprd a = 1; #qprd b = 0; #qprd a = 0; 13 | end 14 | endtask 15 | logic a0 = '0, b0 = '0, a1 = '0, b1 = '0; 16 | initial begin 17 | for(int i = 0; i < 40; i++) QuadEncGo(a0, b0, 0, 100); 18 | for(int i = 0; i < 50; i++) QuadEncGo(a0, b0, 1, 80); 19 | #1000 $stop(); 20 | end 21 | initial begin 22 | for(int i = 0; i < 30; i++) QuadEncGo(a1, b1, 0, 133.333); 23 | for(int i = 0; i < 40; i++) QuadEncGo(a1, b1, 1, 100); 24 | end 25 | logic clk, rst; 26 | initial GenClk(clk, 8, 10); 27 | initial GenRst(clk, rst, 1, 1); 28 | logic [7:0] acc0, acc1; 29 | logic acc_valid; 30 | QuadEncIf #(2, 8, 1000) theQei(clk, rst, '{a1, a0}, '{b1, b0}, '{acc1, acc0}, acc_valid); 31 | endmodule 32 | 33 | module QuadEncIf #( 34 | parameter CH = 1, 35 | parameter ACCW = 16, 36 | parameter SMP_INTV = 1_000_000 37 | )( 38 | input wire clk, rst, 39 | input wire a[CH], b[CH], 40 | output logic signed [ACCW - 1 : 0] acc[CH], 41 | output logic acc_valid 42 | ); 43 | logic co; 44 | Counter #(SMP_INTV) theIntvCnt(clk, rst, 1'b1, , co); 45 | logic [1:0] a_reg[CH], b_reg[CH]; 46 | logic a_rising[CH], a_falling[CH], b_rising[CH], b_falling[CH]; 47 | logic [ACCW - 1 : 0] iacc[CH]; 48 | generate 49 | for(genvar ch = 0; ch < CH; ch++) begin : channel 50 | always_ff@(posedge clk) begin 51 | if(rst) begin 52 | a_reg[ch] <= 2'b00; b_reg[ch] <= 2'b00; 53 | end 54 | else begin 55 | a_reg[ch] <= {a_reg[ch][0], a[ch]}; 56 | b_reg[ch] <= {b_reg[ch][0], b[ch]}; 57 | end 58 | end 59 | assign a_rising[ch] = a_reg[ch] == 2'b01; 60 | assign a_falling[ch] = a_reg[ch] == 2'b10; 61 | assign b_rising[ch] = b_reg[ch] == 2'b01; 62 | assign b_falling[ch] = b_reg[ch] == 2'b10; 63 | always_ff@(posedge clk) begin 64 | if(rst) iacc[ch] <= '0; 65 | else if(co) iacc[ch] <= '0; 66 | else if(a_rising[ch]) iacc[ch] <= iacc[ch] + (b_reg[ch][0]?-1:1); 67 | else if(a_falling[ch]) iacc[ch] <= iacc[ch] + (b_reg[ch][0]?1:-1); 68 | else if(b_rising[ch]) iacc[ch] <= iacc[ch] + (a_reg[ch][0]?1:-1); 69 | else if(b_falling[ch]) iacc[ch] <= iacc[ch] + (a_reg[ch][0]?-1:1); 70 | end 71 | always_ff@(posedge clk) begin 72 | if(rst) acc[ch] <= '0; 73 | else if(co) acc[ch] <= iacc[ch]; 74 | end 75 | end 76 | endgenerate 77 | always_ff@(posedge clk) acc_valid <= co; 78 | endmodule 79 | -------------------------------------------------------------------------------- /chapter4/shiftreg.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../Common.sv" 3 | module TestShiftReg; 4 | 5 | endmodule 6 | 7 | module ShiftReg #( 8 | parameter DW = 8 9 | )( 10 | input wire clk, rst, shift, load, 11 | input wire [DW - 1 : 0] d, 12 | input wire serial_in, 13 | output logic [DW - 1 : 0] q 14 | ); 15 | always_ff@(posedge clk) begin 16 | if(rst) q <= '0; 17 | else if(load) q <= d; 18 | else if(shift) q <= {q, serial_in}; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /chapter4/sim_dcfifo_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider {write side} 4 | add wave -noupdate /TestDcFifo/w_clk 5 | add wave -noupdate /TestDcFifo/w_rst 6 | add wave -noupdate /TestDcFifo/din 7 | add wave -noupdate /TestDcFifo/wr 8 | add wave -noupdate /TestDcFifo/w_wc 9 | add wave -noupdate /TestDcFifo/w_rc 10 | add wave -noupdate /TestDcFifo/w_dc 11 | add wave -noupdate /TestDcFifo/w_fu 12 | add wave -noupdate /TestDcFifo/w_em 13 | add wave -noupdate -divider {read side} 14 | add wave -noupdate /TestDcFifo/r_clk 15 | add wave -noupdate /TestDcFifo/r_rst 16 | add wave -noupdate /TestDcFifo/rd 17 | add wave -noupdate /TestDcFifo/dout 18 | add wave -noupdate /TestDcFifo/r_wc 19 | add wave -noupdate /TestDcFifo/r_rc 20 | add wave -noupdate /TestDcFifo/r_dc 21 | add wave -noupdate /TestDcFifo/r_fu 22 | add wave -noupdate /TestDcFifo/r_em 23 | TreeUpdate [SetDefaultTree] 24 | WaveRestoreCursors {{Cursor 1} {201200 ps} 0} 25 | quietly wave cursor active 1 26 | configure wave -namecolwidth 150 27 | configure wave -valuecolwidth 100 28 | configure wave -justifyvalue left 29 | configure wave -signalnamewidth 1 30 | configure wave -snapdistance 10 31 | configure wave -datasetprefix 0 32 | configure wave -rowmargin 4 33 | configure wave -childrowmargin 2 34 | configure wave -gridoffset 0 35 | configure wave -gridperiod 1 36 | configure wave -griddelta 40 37 | configure wave -timeline 0 38 | configure wave -timelineunits ns 39 | update 40 | WaveRestoreZoom {158300 ps} {696400 ps} 41 | -------------------------------------------------------------------------------- /chapter4/sim_delay_chain_mem.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestDelayChainMem/clk 4 | add wave -noupdate /TestDelayChainMem/en 5 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestDelayChainMem/a 6 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestDelayChainMem/y 7 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestDelayChainMem/dc/addr 8 | TreeUpdate [SetDefaultTree] 9 | WaveRestoreCursors 10 | quietly wave cursor active 0 11 | configure wave -namecolwidth 79 12 | configure wave -valuecolwidth 45 13 | configure wave -justifyvalue left 14 | configure wave -signalnamewidth 1 15 | configure wave -snapdistance 10 16 | configure wave -datasetprefix 0 17 | configure wave -rowmargin 4 18 | configure wave -childrowmargin 2 19 | configure wave -gridoffset 7500 20 | configure wave -gridperiod 1 21 | configure wave -griddelta 40 22 | configure wave -timeline 0 23 | configure wave -timelineunits ns 24 | update 25 | WaveRestoreZoom {0 ps} {343216 ps} 26 | -------------------------------------------------------------------------------- /chapter4/sim_keyprocess_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestKeyProcess/clk 4 | add wave -noupdate /TestKeyProcess/key 5 | add wave -noupdate /TestKeyProcess/key_en 6 | add wave -noupdate /TestKeyProcess/theKeyProc/en_intv 7 | add wave -noupdate -expand /TestKeyProcess/theKeyProc/key_reg 8 | TreeUpdate [SetDefaultTree] 9 | WaveRestoreCursors {{Cursor 1} {162891 us} 0} 10 | quietly wave cursor active 1 11 | configure wave -namecolwidth 150 12 | configure wave -valuecolwidth 100 13 | configure wave -justifyvalue left 14 | configure wave -signalnamewidth 1 15 | configure wave -snapdistance 10 16 | configure wave -datasetprefix 0 17 | configure wave -rowmargin 4 18 | configure wave -childrowmargin 2 19 | configure wave -gridoffset 7500 20 | configure wave -gridperiod 1 21 | configure wave -griddelta 40 22 | configure wave -timeline 0 23 | configure wave -timelineunits ms 24 | update 25 | WaveRestoreZoom {0 us} {525 ms} 26 | -------------------------------------------------------------------------------- /chapter4/sim_mem_spramrf.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestMem/clk 4 | add wave -noupdate -radix hexadecimal /TestMem/a 5 | add wave -noupdate /TestMem/we 6 | add wave -noupdate -radix hexadecimal /TestMem/d 7 | add wave -noupdate -radix hexadecimal /TestMem/q 8 | TreeUpdate [SetDefaultTree] 9 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 10 | quietly wave cursor active 0 11 | configure wave -namecolwidth 69 12 | configure wave -valuecolwidth 52 13 | configure wave -justifyvalue left 14 | configure wave -signalnamewidth 1 15 | configure wave -snapdistance 10 16 | configure wave -datasetprefix 0 17 | configure wave -rowmargin 4 18 | configure wave -childrowmargin 2 19 | configure wave -gridoffset 7500 20 | configure wave -gridperiod 1 21 | configure wave -griddelta 40 22 | configure wave -timeline 0 23 | configure wave -timelineunits ns 24 | update 25 | WaveRestoreZoom {0 ps} {231800 ps} 26 | -------------------------------------------------------------------------------- /chapter4/sim_mem_spramrfsine.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestMem/clk 4 | add wave -noupdate /TestMem/a 5 | add wave -noupdate /TestMem/we 6 | add wave -noupdate /TestMem/d 7 | add wave -noupdate -format Analog-Interpolated -height 74 -max 127.0 -min -127.0 -radix decimal /TestMem/q 8 | TreeUpdate [SetDefaultTree] 9 | WaveRestoreCursors 10 | quietly wave cursor active 0 11 | configure wave -namecolwidth 82 12 | configure wave -valuecolwidth 50 13 | configure wave -justifyvalue left 14 | configure wave -signalnamewidth 1 15 | configure wave -snapdistance 10 16 | configure wave -datasetprefix 0 17 | configure wave -rowmargin 4 18 | configure wave -childrowmargin 2 19 | configure wave -gridoffset 7500 20 | configure wave -gridperiod 1 21 | configure wave -griddelta 40 22 | configure wave -timeline 0 23 | configure wave -timelineunits ns 24 | update 25 | WaveRestoreZoom {0 ps} {7273 ns} 26 | -------------------------------------------------------------------------------- /chapter4/sim_oscope_trigsmp_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestOscopeTrigSmp/clk 4 | add wave -noupdate /TestOscopeTrigSmp/rst 5 | add wave -noupdate -format Analog-Step -height 74 -max 127.0 -min -127.0 -radix decimal -radixshowbase 0 /TestOscopeTrigSmp/sig 6 | add wave -noupdate /TestOscopeTrigSmp/smpEn 7 | add wave -noupdate -radix decimal -radixshowbase 0 /TestOscopeTrigSmp/level 8 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestOscopeTrigSmp/hpos 9 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestOscopeTrigSmp/to 10 | add wave -noupdate /TestOscopeTrigSmp/start 11 | add wave -noupdate /TestOscopeTrigSmp/busy 12 | add wave -noupdate /TestOscopeTrigSmp/read 13 | add wave -noupdate -format Analog-Step -height 74 -max 127.0 -min -127.0 -radix decimal -radixshowbase 0 /TestOscopeTrigSmp/dout 14 | add wave -noupdate -divider {in fsm} 15 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/trigger 16 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/state 17 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/state_nxt 18 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/data_cnting 19 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/data_cnt_clr 20 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/data_cnt 21 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/trigger_flag 22 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/trigger_flag_clr 23 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/trigger_flag_set 24 | add wave -noupdate /TestOscopeTrigSmp/theOscpTrigSmp/theFsm/fifo_write 25 | TreeUpdate [SetDefaultTree] 26 | WaveRestoreCursors 27 | quietly wave cursor active 0 28 | configure wave -namecolwidth 131 29 | configure wave -valuecolwidth 60 30 | configure wave -justifyvalue left 31 | configure wave -signalnamewidth 1 32 | configure wave -snapdistance 10 33 | configure wave -datasetprefix 0 34 | configure wave -rowmargin 4 35 | configure wave -childrowmargin 2 36 | configure wave -gridoffset 7500 37 | configure wave -gridperiod 1 38 | configure wave -griddelta 40 39 | configure wave -timeline 0 40 | configure wave -timelineunits ns 41 | update 42 | WaveRestoreZoom {0 ps} {211509700 ps} 43 | -------------------------------------------------------------------------------- /chapter4/sim_pwm_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestPwm/clk 4 | add wave -noupdate /TestPwm/rst 5 | add wave -noupdate -divider pwm 6 | add wave -noupdate /TestPwm/co 7 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestPwm/udata 8 | add wave -noupdate /TestPwm/pwm 9 | add wave -noupdate -divider {pwm signed} 10 | add wave -noupdate /TestPwm/co_s 11 | add wave -noupdate -radix decimal -radixshowbase 0 /TestPwm/sdata 12 | add wave -noupdate /TestPwm/pwm_s 13 | add wave -noupdate -divider {diff time} 14 | add wave -noupdate /TestPwm/co_dt 15 | add wave -noupdate -radix decimal -radixshowbase 0 /TestPwm/sdata_dt 16 | add wave -noupdate /TestPwm/pwm_dt_p 17 | add wave -noupdate /TestPwm/pwm_dt_n 18 | add wave -noupdate -divider {diff fixed low} 19 | add wave -noupdate /TestPwm/co_fl 20 | add wave -noupdate -radix decimal -radixshowbase 0 /TestPwm/sdata_fl 21 | add wave -noupdate /TestPwm/pwm_fl_p 22 | add wave -noupdate /TestPwm/pwm_fl_n 23 | TreeUpdate [SetDefaultTree] 24 | WaveRestoreCursors 25 | quietly wave cursor active 0 26 | configure wave -namecolwidth 98 27 | configure wave -valuecolwidth 53 28 | configure wave -justifyvalue left 29 | configure wave -signalnamewidth 1 30 | configure wave -snapdistance 10 31 | configure wave -datasetprefix 0 32 | configure wave -rowmargin 4 33 | configure wave -childrowmargin 2 34 | configure wave -gridoffset 7500 35 | configure wave -gridperiod 1 36 | configure wave -griddelta 40 37 | configure wave -timeline 0 38 | configure wave -timelineunits ns 39 | update 40 | WaveRestoreZoom {0 ps} {5751531 ps} 41 | -------------------------------------------------------------------------------- /chapter4/sim_qei_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestQuadEncIf/clk 4 | add wave -noupdate /TestQuadEncIf/rst 5 | add wave -noupdate -divider ch0 6 | add wave -noupdate /TestQuadEncIf/a0 7 | add wave -noupdate /TestQuadEncIf/b0 8 | add wave -noupdate {/TestQuadEncIf/theQei/a_rising[0]} 9 | add wave -noupdate {/TestQuadEncIf/theQei/a_falling[0]} 10 | add wave -noupdate {/TestQuadEncIf/theQei/b_rising[0]} 11 | add wave -noupdate {/TestQuadEncIf/theQei/b_falling[0]} 12 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestQuadEncIf/theQei/iacc[0]} 13 | add wave -noupdate -radix decimal -radixshowbase 0 /TestQuadEncIf/acc0 14 | add wave -noupdate /TestQuadEncIf/acc_valid 15 | add wave -noupdate -divider ch1 16 | add wave -noupdate /TestQuadEncIf/a1 17 | add wave -noupdate /TestQuadEncIf/b1 18 | add wave -noupdate {/TestQuadEncIf/theQei/a_rising[1]} 19 | add wave -noupdate {/TestQuadEncIf/theQei/a_falling[1]} 20 | add wave -noupdate {/TestQuadEncIf/theQei/b_rising[1]} 21 | add wave -noupdate {/TestQuadEncIf/theQei/b_falling[1]} 22 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestQuadEncIf/theQei/iacc[1]} 23 | add wave -noupdate -radix decimal -radixshowbase 0 /TestQuadEncIf/acc1 24 | add wave -noupdate /TestQuadEncIf/acc_valid 25 | TreeUpdate [SetDefaultTree] 26 | WaveRestoreCursors 27 | quietly wave cursor active 0 28 | configure wave -namecolwidth 102 29 | configure wave -valuecolwidth 38 30 | configure wave -justifyvalue left 31 | configure wave -signalnamewidth 1 32 | configure wave -snapdistance 10 33 | configure wave -datasetprefix 0 34 | configure wave -rowmargin 4 35 | configure wave -childrowmargin 2 36 | configure wave -gridoffset 7500 37 | configure wave -gridperiod 1 38 | configure wave -griddelta 40 39 | configure wave -timeline 0 40 | configure wave -timelineunits ns 41 | update 42 | WaveRestoreZoom {0 ps} {34650 ns} 43 | -------------------------------------------------------------------------------- /chapter4/sim_scfifo2_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestScFifo/clk 4 | add wave -noupdate /TestScFifo/wr 5 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/din 6 | add wave -noupdate /TestScFifo/rd 7 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/dout 8 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestScFifo/wc 9 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestScFifo/rc 10 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestScFifo/dc 11 | add wave -noupdate /TestScFifo/fu 12 | add wave -noupdate /TestScFifo/em 13 | add wave -noupdate -divider {In ScFifo} 14 | add wave -noupdate /TestScFifo/theFifo/write 15 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/theFifo/din 16 | add wave -noupdate /TestScFifo/theFifo/read 17 | add wave -noupdate /TestScFifo/theFifo/rd_dly 18 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/theFifo/qout_b 19 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/theFifo/qout_b_reg 20 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/theFifo/dout 21 | TreeUpdate [SetDefaultTree] 22 | WaveRestoreCursors {{Cursor 1} {81100 ps} 0} 23 | quietly wave cursor active 1 24 | configure wave -namecolwidth 106 25 | configure wave -valuecolwidth 53 26 | configure wave -justifyvalue left 27 | configure wave -signalnamewidth 1 28 | configure wave -snapdistance 10 29 | configure wave -datasetprefix 0 30 | configure wave -rowmargin 4 31 | configure wave -childrowmargin 2 32 | configure wave -gridoffset 7500 33 | configure wave -gridperiod 1 34 | configure wave -griddelta 40 35 | configure wave -timeline 0 36 | configure wave -timelineunits ns 37 | update 38 | WaveRestoreZoom {0 ps} {496700 ps} 39 | -------------------------------------------------------------------------------- /chapter4/sim_scfifo_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestScFifo/clk 4 | add wave -noupdate /TestScFifo/wr 5 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/din 6 | add wave -noupdate /TestScFifo/rd 7 | add wave -noupdate /TestScFifo/theFifo/rd_dly 8 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/theFifo/qout_b 9 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/theFifo/qout_b_reg 10 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestScFifo/dout 11 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestScFifo/wc 12 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestScFifo/rc 13 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestScFifo/dc 14 | add wave -noupdate /TestScFifo/fu 15 | add wave -noupdate /TestScFifo/em 16 | TreeUpdate [SetDefaultTree] 17 | WaveRestoreCursors {{Cursor 1} {293000 ps} 0} 18 | quietly wave cursor active 1 19 | configure wave -namecolwidth 106 20 | configure wave -valuecolwidth 53 21 | configure wave -justifyvalue left 22 | configure wave -signalnamewidth 1 23 | configure wave -snapdistance 10 24 | configure wave -datasetprefix 0 25 | configure wave -rowmargin 4 26 | configure wave -childrowmargin 2 27 | configure wave -gridoffset 7500 28 | configure wave -gridperiod 1 29 | configure wave -griddelta 40 30 | configure wave -timeline 0 31 | configure wave -timelineunits ns 32 | update 33 | WaveRestoreZoom {72 ns} {443300 ps} 34 | -------------------------------------------------------------------------------- /chapter4/sim_stopwatch_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestStopWatchFsm/clk 4 | add wave -noupdate /TestStopWatchFsm/rst 5 | add wave -noupdate /TestStopWatchFsm/k0 6 | add wave -noupdate /TestStopWatchFsm/k0en 7 | add wave -noupdate /TestStopWatchFsm/k1 8 | add wave -noupdate /TestStopWatchFsm/k1en 9 | add wave -noupdate -divider fsm 10 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestStopWatchFsm/sw_sm/state 11 | add wave -noupdate /TestStopWatchFsm/t 12 | add wave -noupdate /TestStopWatchFsm/f 13 | add wave -noupdate /TestStopWatchFsm/r 14 | add wave -noupdate /TestStopWatchFsm/u 15 | add wave -noupdate -divider counters 16 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestStopWatchFsm/cnt_centisec 17 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestStopWatchFsm/cnt_sec 18 | add wave -noupdate -divider outputs 19 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestStopWatchFsm/centisec 20 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestStopWatchFsm/sec 21 | TreeUpdate [SetDefaultTree] 22 | WaveRestoreCursors 23 | quietly wave cursor active 0 24 | configure wave -namecolwidth 111 25 | configure wave -valuecolwidth 40 26 | configure wave -justifyvalue left 27 | configure wave -signalnamewidth 1 28 | configure wave -snapdistance 10 29 | configure wave -datasetprefix 0 30 | configure wave -rowmargin 4 31 | configure wave -childrowmargin 2 32 | configure wave -gridoffset 7500 33 | configure wave -gridperiod 1 34 | configure wave -griddelta 40 35 | configure wave -timeline 0 36 | configure wave -timelineunits ms 37 | update 38 | WaveRestoreZoom {0 us} {4417875 us} 39 | -------------------------------------------------------------------------------- /chapter4/stop_watch_fsm.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ms/1us 2 | `default_nettype none 3 | `include "../Common.sv" 4 | module TestStopWatchFsm; 5 | import SimSrcGen::*; 6 | logic clk, rst; 7 | initial GenClk(clk, 0.8, 1); 8 | initial GenRst(clk, rst, 1, 1); 9 | logic k0 = '0, k1 = '0; 10 | initial begin 11 | #200 KeyPress(k0, 50); //start 12 | #450 KeyPress(k0, 50); //pause 13 | #220 KeyPress(k1, 50); //stop 14 | #260 KeyPress(k0, 50); //start 15 | #450 KeyPress(k1, 50); //freeze 16 | #680 KeyPress(k1, 50); //freeze 17 | #990 KeyPress(k0, 50); //run 18 | #220 KeyPress(k0, 50); //pause 19 | #120 KeyPress(k1, 50); //stop 20 | #100 $stop(); 21 | end 22 | logic k0en, k1en; 23 | KeyProcess #(10, 2) key2en(clk, {k1, k0}, {k1en, k0en}); 24 | logic t, f, r, u; 25 | StopWatchFsm sw_sm(clk, rst, k0en, k1en, t, f, r, u); 26 | logic en_10ms; 27 | Counter #(10) cntClk(clk, rst | r, t, , en_10ms); 28 | logic en_1sec, en_1min; 29 | logic [6:0] cnt_centisec; 30 | logic [5:0] cnt_sec; 31 | Counter #(100) cntCentiSec(clk, rst | r, en_10ms, cnt_centisec, en_1sec); 32 | Counter #(60) cntSec(clk, rst | r, en_1sec, cnt_sec, en_1min); 33 | logic [6:0] centisec; 34 | logic [5:0] sec; 35 | always@(posedge clk) begin 36 | if(rst) begin 37 | centisec <= 7'b0; 38 | sec <= 6'b0; 39 | end 40 | else if(~f | u) begin 41 | centisec <= cnt_centisec; 42 | sec <= cnt_sec; 43 | end 44 | end 45 | endmodule 46 | 47 | module StopWatchFsm( 48 | input wire clk, rst, k0, k1, 49 | output logic timming, freezing, reset, update 50 | ); 51 | localparam S_STOP = 4'h1; 52 | localparam S_RUN = 4'h2; 53 | localparam S_PAUSE = 4'h4; 54 | localparam S_FREEZE = 4'h8; 55 | logic [3:0] state, state_nxt; 56 | always_ff@(posedge clk) begin 57 | if(rst) state <= S_STOP; 58 | else state <= state_nxt; 59 | end 60 | always_comb begin 61 | state_nxt = state; 62 | case(state) 63 | S_STOP: 64 | if(k0) state_nxt = S_RUN; 65 | S_RUN: 66 | if(k0) state_nxt = S_PAUSE; 67 | else if(k1) state_nxt = S_FREEZE; 68 | S_PAUSE: 69 | if(k0) state_nxt = S_RUN; 70 | else if(k1) state_nxt = S_STOP; 71 | S_FREEZE: 72 | if(k0) state_nxt = S_RUN; 73 | else if(k1) state_nxt = S_FREEZE; 74 | default: state_nxt = state; 75 | endcase 76 | end 77 | always_ff@(posedge clk) 78 | timming <= (state == S_RUN) || (state == S_FREEZE); 79 | always_ff@(posedge clk) 80 | freezing <= (state == S_FREEZE); 81 | always_ff@(posedge clk) 82 | reset <= k1 && (state == S_PAUSE); 83 | always_ff@(posedge clk) 84 | update <= k1 && (state == S_FREEZE); 85 | endmodule 86 | -------------------------------------------------------------------------------- /chapter4/test_cc_event_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestCCEvent/theCCEvent/clk_a 4 | add wave -noupdate /TestCCEvent/theCCEvent/in 5 | add wave -noupdate /TestCCEvent/theCCEvent/ra0 6 | add wave -noupdate /TestCCEvent/theCCEvent/ra1 7 | add wave -noupdate /TestCCEvent/theCCEvent/ra2 8 | add wave -noupdate /TestCCEvent/theCCEvent/busy 9 | add wave -noupdate /TestCCEvent/theCCEvent/clk_b 10 | add wave -noupdate /TestCCEvent/theCCEvent/rb0 11 | add wave -noupdate /TestCCEvent/theCCEvent/rb1 12 | add wave -noupdate /TestCCEvent/theCCEvent/rb2 13 | add wave -noupdate /TestCCEvent/theCCEvent/out 14 | TreeUpdate [SetDefaultTree] 15 | WaveRestoreCursors {{Cursor 1} {354 ns} 0} 16 | quietly wave cursor active 1 17 | configure wave -namecolwidth 150 18 | configure wave -valuecolwidth 100 19 | configure wave -justifyvalue left 20 | configure wave -signalnamewidth 1 21 | configure wave -snapdistance 10 22 | configure wave -datasetprefix 0 23 | configure wave -rowmargin 4 24 | configure wave -childrowmargin 2 25 | configure wave -gridoffset 7500 26 | configure wave -gridperiod 1 27 | configure wave -griddelta 40 28 | configure wave -timeline 0 29 | configure wave -timelineunits ns 30 | update 31 | WaveRestoreZoom {0 ns} {992 ns} 32 | -------------------------------------------------------------------------------- /chapter4/test_cccnt_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider {cd clk_a} 4 | add wave -noupdate /TestCCCnt/clk_a 5 | add wave -noupdate /TestCCCnt/inc 6 | add wave -noupdate /TestCCCnt/cnt_a 7 | add wave -noupdate -divider {inner cccnt} 8 | add wave -noupdate /TestCCCnt/theCCCnt/clk_a 9 | add wave -noupdate /TestCCCnt/theCCCnt/inc 10 | add wave -noupdate /TestCCCnt/theCCCnt/cnt_a 11 | add wave -noupdate /TestCCCnt/theCCCnt/bin_next 12 | add wave -noupdate /TestCCCnt/theCCCnt/gray_next 13 | add wave -noupdate /TestCCCnt/theCCCnt/gray 14 | add wave -noupdate /TestCCCnt/theCCCnt/clk_b 15 | add wave -noupdate /TestCCCnt/theCCCnt/gray_sync 16 | add wave -noupdate /TestCCCnt/theCCCnt/cnt_b 17 | add wave -noupdate -divider {cd clk_b} 18 | add wave -noupdate /TestCCCnt/clk_b 19 | add wave -noupdate /TestCCCnt/cnt_b 20 | TreeUpdate [SetDefaultTree] 21 | WaveRestoreCursors 22 | quietly wave cursor active 0 23 | configure wave -namecolwidth 100 24 | configure wave -valuecolwidth 64 25 | configure wave -justifyvalue left 26 | configure wave -signalnamewidth 1 27 | configure wave -snapdistance 10 28 | configure wave -datasetprefix 0 29 | configure wave -rowmargin 4 30 | configure wave -childrowmargin 2 31 | configure wave -gridoffset 7500 32 | configure wave -gridperiod 1 33 | configure wave -griddelta 40 34 | configure wave -timeline 0 35 | configure wave -timelineunits ns 36 | update 37 | WaveRestoreZoom {878 ns} {1007 ns} 38 | -------------------------------------------------------------------------------- /chapter4/test_mem_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestMem/a 4 | add wave -noupdate /TestMem/clk 5 | add wave -noupdate -format Analog-Step -height 74 -max 127.0 -min -127.0 -radix decimal /TestMem/q 6 | TreeUpdate [SetDefaultTree] 7 | WaveRestoreCursors {{Cursor 1} {4457000 ps} 0} 8 | quietly wave cursor active 1 9 | configure wave -namecolwidth 150 10 | configure wave -valuecolwidth 100 11 | configure wave -justifyvalue left 12 | configure wave -signalnamewidth 1 13 | configure wave -snapdistance 10 14 | configure wave -datasetprefix 0 15 | configure wave -rowmargin 4 16 | configure wave -childrowmargin 2 17 | configure wave -gridoffset 7500 18 | configure wave -gridperiod 1 19 | configure wave -griddelta 40 20 | configure wave -timeline 0 21 | configure wave -timelineunits ns 22 | update 23 | WaveRestoreZoom {2691 ns} {6485500 ps} 24 | -------------------------------------------------------------------------------- /chapter4/test_pulse_widen_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestPulseWiden/clk 4 | add wave -noupdate /TestPulseWiden/in 5 | add wave -noupdate /TestPulseWiden/pw1/cnt 6 | add wave -noupdate /TestPulseWiden/out 7 | add wave -noupdate /TestPulseWiden/pw2/cnt 8 | add wave -noupdate /TestPulseWiden/out2 9 | add wave -noupdate /TestPulseWiden/pw3/cnt 10 | add wave -noupdate /TestPulseWiden/out3 11 | TreeUpdate [SetDefaultTree] 12 | WaveRestoreCursors 13 | quietly wave cursor active 0 14 | configure wave -namecolwidth 76 15 | configure wave -valuecolwidth 53 16 | configure wave -justifyvalue left 17 | configure wave -signalnamewidth 1 18 | configure wave -snapdistance 10 19 | configure wave -datasetprefix 0 20 | configure wave -rowmargin 4 21 | configure wave -childrowmargin 2 22 | configure wave -gridoffset 7500 23 | configure wave -gridperiod 1 24 | configure wave -griddelta 40 25 | configure wave -timeline 0 26 | configure wave -timelineunits ns 27 | update 28 | WaveRestoreZoom {185140 ps} {403846 ps} 29 | -------------------------------------------------------------------------------- /chapter4/vish_stacktrace.vstf: -------------------------------------------------------------------------------- 1 | # Current time Tue May 09 15:01:00 2017 2 | # ModelSim PE Student Edition Stack Trace 3 | # Program = vish 4 | # Id = "10.4a" 5 | # Version = "2015.03" 6 | # Date = "Apr 7 2015" 7 | # Platform = win32pe 8 | 9 | Exception c0000005 has occurred at address 73431bb0. Traceback: 10 | -------------------------------------------------------------------------------- /chapter4/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter4/vsim.wlf -------------------------------------------------------------------------------- /chapter5/counter.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "../../book2015.sv" 3 | 4 | module TestCounter; 5 | import SimSrcGen::*; 6 | logic clk; 7 | logic rst; 8 | logic en; 9 | initial GenClk(clk, 2, 10); 10 | initial GenRst(clk, rst, 10, 1); 11 | initial begin 12 | en = 1'b1; 13 | #100 en = 1'b0; 14 | #100 en = 1'b1; 15 | end 16 | logic [6:0] cnt; 17 | logic co; 18 | Counter #(128) theCnt(clk, rst, en, cnt, co); 19 | endmodule 20 | 21 | module TestCntSecMinHr; 22 | import SimSrcGen::*; 23 | logic clk; 24 | logic rst; 25 | initial GenClk(clk, 0, 100ms); 26 | initial GenRst(clk, rst, 0, 1); 27 | logic [5:0] sec, min; 28 | logic [4:0] hr; 29 | CntSecMinHr theCntSMH(clk, rst, sec, min, hr); 30 | endmodule 31 | 32 | module CntSecMinHr( 33 | input wire clk, rst, 34 | output logic [5:0] sec, 35 | output logic [5:0] min, 36 | output logic [4:0] hr 37 | ); 38 | logic en1sec, en1min, en1hr; 39 | Counter #(10) cnt1sec (.clk(clk), .rst(rst), .en( 1'b1), .cnt(), .co(en1sec)); 40 | Counter #(60) cnt60sec(.clk(clk), .rst(rst), .en(en1sec), .cnt(sec), .co(en1min)); 41 | Counter #(60) cnt60min(.clk(clk), .rst(rst), .en(en1min), .cnt(min), .co(en1hr )); 42 | Counter #(24) cnt24hr (.clk(clk), .rst(rst), .en(en1hr ), .cnt(hr ), .co()); 43 | endmodule 44 | 45 | module Counter #( 46 | parameter M = 100 47 | )( 48 | input wire clk, rst, en, 49 | output logic [$clog2(M) - 1 : 0] cnt, 50 | output logic co 51 | ); 52 | assign co = en & (cnt == M - 1); 53 | always_ff@(posedge clk) begin 54 | if(rst) cnt <= '0; 55 | else if(en) begin 56 | if(cnt < M - 1) cnt <= cnt + 1'b1; 57 | else cnt <= '0; 58 | end 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /chapter5/iis.sv: -------------------------------------------------------------------------------- 1 | `ifndef __IIS_SV__ 2 | `define __IIS_SV__ 3 | 4 | `include "../common.sv" 5 | `include "../chapter4/counter.sv" 6 | `include "../chapter4/edge2en.sv" 7 | 8 | `default_nettype none 9 | `timescale 1ns/10ps 10 | 11 | module TestIis; 12 | import SimSrcGen::*; 13 | logic clk; 14 | initial GenClk(clk, 10ns, 40.69ns); // 24.576M 15 | // ==== transmitter side ==== 16 | logic sck, ws, sd, sck_fall, f_sync, txdata_rd; 17 | // sck 3.072M, ws 48k 18 | IisClkGen #(64, 8) iisClk(clk, sck, ws, sck_fall, f_sync); 19 | logic signed [31:0] txdata[2]; 20 | IisTransmitter iisTrans(clk, sck_fall, f_sync, txdata, txdata_rd, sd); 21 | // ==== receiver side ==== 22 | logic signed [31:0] rxdata[2]; 23 | logic rxdata_valid; 24 | IisReceiver iisRecv(clk, sck, ws, sd, rxdata, rxdata_valid); 25 | // ==== transmitter side data ==== 26 | always_ff@(posedge clk) begin 27 | if(txdata_rd) txdata = '{$random(), $random()}; 28 | end 29 | endmodule 30 | 31 | module IisClkGen #( 32 | parameter SCK_TO_WS = 64, 33 | parameter MCK_TO_SCK = 8 34 | )( 35 | input wire mck, 36 | output logic sck, 37 | output logic ws, 38 | output logic sck_fall, 39 | output logic frame_sync 40 | ); 41 | localparam SCKW = $clog2(MCK_TO_SCK); 42 | localparam WSW = $clog2(SCK_TO_WS); 43 | logic [SCKW - 1 : 0] cnt_sck; 44 | logic cnt_sck_co; 45 | logic [WSW - 1 : 0] cnt_ws; 46 | always_ff@(posedge mck) sck <= cnt_sck >= SCKW'(MCK_TO_SCK / 2); 47 | always_ff@(posedge mck) ws <= cnt_ws >= WSW'(SCK_TO_WS / 2); 48 | always_ff@(posedge mck) sck_fall <= cnt_sck_co; 49 | Counter #(MCK_TO_SCK) cntSck( 50 | mck, 1'b0, 1'b1, cnt_sck, cnt_sck_co); 51 | Counter #(SCK_TO_WS) cntWs( 52 | mck, 1'b0, cnt_sck_co, cnt_ws, ); 53 | assign frame_sync = (cnt_ws == 0) && cnt_sck_co; 54 | endmodule 55 | 56 | module IisTransmitter ( 57 | input wire mck, 58 | input wire sck_fall, 59 | input wire frame_sync, 60 | input wire signed [31:0] data[2], //data[0]: left; data[1]: right 61 | output logic data_rd, 62 | output logic iis_sd 63 | ); 64 | assign data_rd = frame_sync; 65 | logic data_rd_dly; 66 | logic [63:0] shift_reg; 67 | always_ff@(posedge mck) data_rd_dly <= data_rd; 68 | always_ff@(posedge mck) begin 69 | if(data_rd_dly) shift_reg <= {data[0], data[1]}; 70 | else if(sck_fall) shift_reg <= {shift_reg[62:0], 1'b0}; 71 | end 72 | assign iis_sd = shift_reg[63]; 73 | endmodule 74 | 75 | module IisReceiver ( 76 | input wire mck, iis_sck, iis_ws, iis_sd, 77 | output logic signed [31:0] data[2], 78 | output logic data_valid 79 | ); 80 | logic sck_rising, sck_reg, ws_falling, sd_reg; 81 | Rising2En #(2) sckRising(mck, iis_sck, sck_rising, sck_reg); 82 | Falling2En #(2) wsFalling(mck, iis_ws, ws_falling, ); 83 | Rising2En #(2) sdSync(mck, iis_sd, , sd_reg); 84 | logic [7:0] bit_cnt; 85 | Counter #(256) bitCnt(mck, ws_falling, sck_rising, bit_cnt, ); 86 | logic frame_end; 87 | always_ff@(posedge mck) frame_end <= (bit_cnt == 8'd0) && sck_rising; 88 | always_ff@(posedge mck) data_valid <= frame_end; 89 | logic [63:0] shift_reg; 90 | always_ff@(posedge mck) begin 91 | if(frame_end) {data[0], data[1]} <= shift_reg; 92 | else if(sck_rising) shift_reg <= {shift_reg[62:0], sd_reg}; 93 | end 94 | endmodule 95 | 96 | `endif 97 | -------------------------------------------------------------------------------- /chapter5/sim_spi_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestSpi/clk 4 | add wave -noupdate /TestSpi/rst 5 | add wave -noupdate -divider master 6 | add wave -noupdate /TestSpi/start 7 | add wave -noupdate /TestSpi/ss_mask 8 | add wave -noupdate /TestSpi/trans_len 9 | add wave -noupdate /TestSpi/mread 10 | add wave -noupdate /TestSpi/mtx_d 11 | add wave -noupdate /TestSpi/mvalid 12 | add wave -noupdate /TestSpi/mrx_d 13 | add wave -noupdate /TestSpi/mbusy 14 | add wave -noupdate -divider spi 15 | add wave -noupdate {/TestSpi/ss_n[3]} 16 | add wave -noupdate /TestSpi/sclk0 17 | add wave -noupdate /TestSpi/mosi 18 | add wave -noupdate /TestSpi/miso 19 | add wave -noupdate -divider slave 20 | add wave -noupdate /TestSpi/sread 21 | add wave -noupdate /TestSpi/stx_d 22 | add wave -noupdate /TestSpi/svalid 23 | add wave -noupdate /TestSpi/srx_d 24 | TreeUpdate [SetDefaultTree] 25 | WaveRestoreCursors {{Cursor 1} {682142 ps} 0} 26 | quietly wave cursor active 1 27 | configure wave -namecolwidth 115 28 | configure wave -valuecolwidth 68 29 | configure wave -justifyvalue left 30 | configure wave -signalnamewidth 1 31 | configure wave -snapdistance 10 32 | configure wave -datasetprefix 0 33 | configure wave -rowmargin 4 34 | configure wave -childrowmargin 2 35 | configure wave -gridoffset 7500 36 | configure wave -gridperiod 1 37 | configure wave -griddelta 40 38 | configure wave -timeline 0 39 | configure wave -timelineunits ns 40 | update 41 | WaveRestoreZoom {0 ps} {4980150 ps} 42 | -------------------------------------------------------------------------------- /chapter5/transcript: -------------------------------------------------------------------------------- 1 | # OpenFile Z:/projects/modelsim/FPGA_Book_2017/chapter5/iic_slave.sv 2 | -------------------------------------------------------------------------------- /chapter5/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter5/vsim.wlf -------------------------------------------------------------------------------- /chapter6/axi4lite.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4s_fifo.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4s_fifo.sv 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling module TestMem 6 | -- Importing package SimSrcGen 7 | -- Compiling module SpRamRf 8 | -- Compiling module SpRamWf 9 | -- Compiling module SdpRamRf 10 | -- Compiling module DpRam 11 | -- Compiling module SdcRam 12 | -- Compiling module DcRam 13 | -- Compiling module SpRamRfSine 14 | -- Compiling module TestScFifo 15 | -- Compiling module ScFifo1 16 | -- Compiling module ScFifo2 17 | -- Compiling module TestAxi4StreamFifo 18 | -- Compiling interface Axi4StreamIf 19 | -- Compiling module Axi4sFifo 20 | 21 | Top level modules: 22 | TestMem 23 | SpRamRf 24 | SpRamWf 25 | DpRam 26 | SdcRam 27 | DcRam 28 | TestScFifo 29 | ScFifo1 30 | TestAxi4StreamFifo 31 | 32 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4full.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4full.sv 33 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 34 | -- Compiling package SimSrcGen 35 | -- Compiling package CombFunctions 36 | -- Compiling module TestBurstAddrGen 37 | -- Importing package SimSrcGen 38 | -- Compiling module Axi4BurstAddrGen 39 | 40 | Top level modules: 41 | TestBurstAddrGen 42 | 43 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4lite_if.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4lite_if.sv 44 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 45 | -- Compiling interface Axi4LiteIf 46 | 47 | Top level modules: 48 | --none-- 49 | 50 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4lite_slave.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4lite_slave.sv 51 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 52 | -- Compiling module Axi4LiteSlave 53 | 54 | Top level modules: 55 | Axi4LiteSlave 56 | 57 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter6/test_axi4lite.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter6/test_axi4lite.sv 58 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 59 | -- Compiling package SimSrcGen 60 | -- Compiling package CombFunctions 61 | -- Compiling module TestMem 62 | -- Importing package SimSrcGen 63 | -- Compiling module SpRamRf 64 | -- Compiling module SpRamWf 65 | -- Compiling module SdpRamRf 66 | -- Compiling module DpRam 67 | -- Compiling module SdcRam 68 | -- Compiling module DcRam 69 | -- Compiling module SpRamRfSine 70 | -- Compiling module TestAxi4Lite 71 | 72 | Top level modules: 73 | TestMem 74 | SpRamRf 75 | SpRamWf 76 | SdpRamRf 77 | DpRam 78 | SdcRam 79 | DcRam 80 | TestAxi4Lite 81 | 82 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4lite_master.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter6/axi4lite_master.sv 83 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 84 | -- Compiling package SimSrcGen 85 | -- Compiling package CombFunctions 86 | -- Compiling module TestCounter 87 | -- Importing package SimSrcGen 88 | -- Compiling module TestCntSecMinHr 89 | -- Compiling module CntSecMinHr 90 | -- Compiling module Counter 91 | -- Compiling module CounterMax 92 | -- Compiling module Axi4LiteMasterEg 93 | 94 | Top level modules: 95 | TestCounter 96 | TestCntSecMinHr 97 | Axi4LiteMasterEg 98 | 99 | } {} {}} 100 | -------------------------------------------------------------------------------- /chapter6/axi4lite_if.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `timescale 1ns/100ps 3 | 4 | interface Axi4LiteIf #( parameter AW = 32)( 5 | input wire clk, reset_n 6 | ); 7 | logic [AW-1:0] awaddr; 8 | logic [2:0] awprot; 9 | logic awvalid = '0, awready; 10 | logic [31:0] wdata; 11 | logic [3:0] wstrb; 12 | logic wvalid = '0, wready; 13 | logic [1:0] bresp; 14 | logic bvalid = '0, bready; 15 | logic [AW-1:0] araddr; 16 | logic [2:0] arprot; 17 | logic arvalid = '0, arready; 18 | logic [31:0] rdata; 19 | logic [1:0] rresp; 20 | logic rvalid = '0, rready; 21 | modport master( 22 | input clk, reset_n, 23 | output awaddr, awprot, awvalid, input awready, 24 | output wdata, wstrb, wvalid, input wready, 25 | input bresp, bvalid, output bready, 26 | output araddr, arprot, arvalid, input arready, 27 | input rdata, rresp, rvalid, output rready 28 | ); 29 | modport slave( 30 | input clk, reset_n, 31 | input awaddr, awprot, awvalid, output awready, 32 | input wdata, wstrb, wvalid, output wready, 33 | output bresp, bvalid, input bready, 34 | input araddr, arprot, arvalid, output arready, 35 | output rdata, rresp, rvalid, input rready 36 | ); 37 | // task Write( 38 | // input logic [AW-1:0] addr, logic [31:0] data, 39 | // logic [31:0] strb = '1, logic [2:0] prot = '0 40 | // ); 41 | // @(posedge clk) begin 42 | // awaddr = addr; awprot = prot; awvalid = '1; 43 | // wdata = data; wstrb = strb; wvalid = '1; 44 | // bready = '1; 45 | // end 46 | // fork 47 | // wait(awready) @(posedge clk) awvalid = '0; 48 | // wait(wready) @(posedge clk) wvalid = '0; 49 | // wait(bvalid) @(posedge clk) bready = '0; 50 | // join 51 | // endtask 52 | // task Read( 53 | // input logic [AW-1:0] addr, output logic [31:0] data, 54 | // input logic [3:0] prot = '0 55 | // ); 56 | // @(posedge clk) begin 57 | // araddr = addr; arprot = prot; arvalid = '1; 58 | // rready = '1; 59 | // end 60 | // wait(arready) @(posedge clk) arvalid = '0; 61 | // wait(rvalid) @(posedge clk) begin 62 | // rready = '0; 63 | // data = rdata; 64 | // end 65 | // endtask 66 | endinterface 67 | -------------------------------------------------------------------------------- /chapter6/axi4lite_master.sv: -------------------------------------------------------------------------------- 1 | `include "../chapter4/counter.sv" 2 | 3 | `default_nettype none 4 | `timescale 1ns/100ps 5 | 6 | module Axi4LiteMasterEg ( 7 | Axi4LiteIf.master m, 8 | input wire start 9 | ); 10 | localparam [31:0] START_ADDR = 0; 11 | localparam LEN = 8; 12 | logic [7:0] acnt; 13 | logic acnt_co; 14 | CounterMax #(8) addrCnt(m.clk, 15 | ~m.reset_n | start, m.bvalid & m.bready, 8'd7, acnt, acnt_co); 16 | // ==== ar channel ==== 17 | assign m.araddr = (acnt + START_ADDR) << 2; 18 | assign m.arprot = 3'b0; 19 | always_ff@(posedge m.clk) begin 20 | if(~m.reset_n) m.arvalid <= '0; 21 | else if(start | (m.bvalid & m.bready & ~acnt_co)) m.arvalid <= '1; 22 | else if(m.arvalid & m.arready) m.arvalid <= '0; 23 | end 24 | // ==== r channel ==== 25 | assign m.rready = '1; 26 | logic signed [31:0] data; 27 | always_ff@(posedge m.clk) begin 28 | if(~m.reset_n) data <= '0; 29 | else if(m.rvalid) data <= m.rdata; 30 | end 31 | // ==== aw channel ==== 32 | assign m.awaddr = (acnt + START_ADDR) << 2; 33 | assign m.awprot = 3'b0; 34 | always_ff@(posedge m.clk) begin 35 | if(~m.reset_n) m.awvalid <= '0; 36 | else if(m.rvalid) m.awvalid <= '1; 37 | else if(m.awvalid & m.awready) m.awvalid <= '0; 38 | end 39 | // ==== w channel ==== 40 | assign m.wdata = -data; 41 | assign m.wstrb = 4'b1111; 42 | always_ff@(posedge m.clk) begin 43 | if(~m.reset_n) m.wvalid <= '0; 44 | else if(m.rvalid) m.wvalid <= '1; 45 | else if(m.wvalid & m.wready) m.wvalid <= '0; 46 | end 47 | // ==== b channel ==== 48 | assign m.bready = '1; 49 | endmodule 50 | -------------------------------------------------------------------------------- /chapter6/axi4lite_slave.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `timescale 1ns/100ps 3 | 4 | module Axi4LiteSlave #(parameter REG_NUM = 8)( 5 | Axi4LiteIf.slave s, 6 | output logic [31:0] regs[REG_NUM] 7 | ); 8 | logic regs_wr, regs_rd; 9 | // ==== aw channel ==== 10 | assign s.awready = 1'b1; // always ready 11 | logic [s.AW-3 : 0] waddr_reg; // byte addr --> reg addr 12 | always_ff@(posedge s.clk) begin 13 | if(~s.reset_n) waddr_reg <= '0; 14 | else if(s.awvalid) waddr_reg <= s.awaddr[s.AW-1 : 2]; 15 | end 16 | // === w channel === 17 | assign regs_wr = s.wvalid & s.wready; 18 | always_ff@(posedge s.clk) begin 19 | if(~s.reset_n) s.wready <= 1'b0; 20 | else if(s.awvalid) s.wready <= 1'b1; //waddr got 21 | else if(s.wvalid & s.wready) s.wready <= 1'b0; //handshake 22 | end 23 | // === b ch === 24 | assign s.bresp = 2'b00; // always ok 25 | always_ff@(posedge s.clk) begin 26 | if(~s.reset_n) s.bvalid <= 1'b0; 27 | else if(s.wvalid & s.wready) s.bvalid <= 1'b1;//wdata got 28 | else if(s.bvalid & s.bready) s.bvalid <= 1'b0;//handshake 29 | end 30 | // === ar ch === 31 | logic [s.AW-3 : 0] raddr_reg; 32 | always_ff@(posedge s.clk) begin 33 | if(~s.reset_n) raddr_reg <= 1'b0; 34 | else if(s.arvalid) raddr_reg <= s.araddr[s.AW-1 : 2]; 35 | end 36 | always_ff@(posedge s.clk) begin 37 | if(~s.reset_n) s.arready <= 1'b0; 38 | else if(s.arvalid & ~s.arready) s.arready <= 1'b1; //raddr got 39 | else if(s.arvalid & s.arready) s.arready <= 1'b0;//handshake 40 | end 41 | assign regs_rd = s.arvalid & s.arready; 42 | // === r ch === 43 | assign s.rresp = 2'b00; // always ok 44 | always_ff@(posedge s.clk) begin 45 | if(~s.reset_n) s.rvalid <= 1'b0; 46 | else if(regs_rd) s.rvalid <= 1'b1; 47 | else if(s.rvalid & s.rready) s.rvalid <= 1'b0; 48 | end 49 | always_ff@(posedge s.clk) begin 50 | if(regs_rd) s.rdata <= regs[raddr_reg]; 51 | end 52 | // === regs === 53 | always_ff@(posedge s.clk) begin 54 | if(~s.reset_n) regs = '{REG_NUM{'0}}; 55 | else if(regs_wr) begin 56 | if(s.wstrb[0]) regs[waddr_reg][0+:8] <= s.wdata[0+:8]; 57 | if(s.wstrb[1]) regs[waddr_reg][8+:8] <= s.wdata[8+:8]; 58 | if(s.wstrb[2]) regs[waddr_reg][16+:8] <= s.wdata[16+:8]; 59 | if(s.wstrb[3]) regs[waddr_reg][24+:8] <= s.wdata[24+:8]; 60 | end 61 | end 62 | endmodule 63 | -------------------------------------------------------------------------------- /chapter6/mm_intercon.sv: -------------------------------------------------------------------------------- 1 | `ifndef __MM_INTERCON_SV__ 2 | `define __MM_INTERCON_SV__ 3 | 4 | `default_nettype none 5 | `timescale 1ns/100ps 6 | 7 | interface PicoMmIf#(parameter AW = 16)( input wire clk, rst ); 8 | logic [AW-1:0] addr; 9 | logic write; logic [31:0] wrdata; 10 | logic read; logic [31:0] rddata; 11 | modport master(input clk, rst, rddata, 12 | output addr, write, wrdata, read); 13 | modport slave(input clk, rst, addr, write, wrdata, read, 14 | output rddata); 15 | task automatic Write( 16 | input logic [31:0] a, input logic [31:0] d); 17 | addr = a; wrdata = d; write = 1'b1; 18 | @(posedge clk) write = 1'b0; 19 | endtask 20 | task automatic Read( 21 | input logic [31:0] a); 22 | addr = a; read = 1'b1; 23 | @(posedge clk) read = 1'b0; 24 | endtask 25 | endinterface 26 | 27 | module PicoMmInterconnector1to3 ( 28 | PicoMmIf.slave s, 29 | PicoMmIf.master m[3] 30 | ); 31 | assign m[0].wrdata = s.wrdata; 32 | assign m[1].wrdata = s.wrdata; 33 | assign m[2].wrdata = s.wrdata; 34 | always_comb begin 35 | casez(s.addr) 36 | 32'h0000_????: begin 37 | m[0].write = s.write; 38 | m[0].read = s.read; 39 | m[0].addr = s.addr[m[0].AW-1:0]; 40 | end 41 | 32'h0001_000?: begin 42 | m[1].write = s.write; 43 | m[1].read = s.read; 44 | m[1].addr = s.addr[m[1].AW-1:0]; 45 | end 46 | 32'h0001_001?: begin 47 | m[2].write = s.write; 48 | m[2].read = s.read; 49 | m[2].addr = s.addr[m[2].AW-1:0]; 50 | end 51 | default: begin 52 | m[2].write = '0; 53 | m[2].read = '0; 54 | m[2].addr = '0; 55 | end 56 | endcase 57 | end 58 | logic [31:0] addr_reg; 59 | always_ff@(posedge s.clk) addr_reg <= s.addr; 60 | always_comb begin 61 | casez(addr_reg) 62 | 32'h0000_????: s.rddata = m[0].rddata; 63 | 32'h0001_000?: s.rddata = m[1].rddata; 64 | 32'h0001_001?: s.rddata = m[2].rddata; 65 | default: s.rddata = '0; 66 | endcase 67 | end 68 | endmodule 69 | 70 | module PicoMmIntercon #( 71 | parameter M_NUM = 4, 72 | parameter [31:0] BA[M_NUM] 73 | )( 74 | PicoMmIf.slave s, PicoMmIf.master m[M_NUM] 75 | ); 76 | logic [M_NUM-1 : 0] sel, sel_reg; 77 | always_ff@(posedge s.clk) sel_reg <= sel; 78 | logic [31:0] rddata[M_NUM]; 79 | generate 80 | for(genvar i = 0; i < M_NUM; i++) begin 81 | always@(*) begin 82 | sel[i] = s.addr[31 : m[i].AW] == BA[i][31 : m[i].AW]; 83 | m[i].addr = s.addr[m[i].AW - 1 : 0]; 84 | m[i].wrdata = s.wrdata; 85 | m[i].write = s.write & sel[i]; 86 | m[i].read = s.read & sel[i]; 87 | rddata[i] = m[i].rddata; 88 | end 89 | end 90 | endgenerate 91 | always_comb begin 92 | s.rddata = '0; 93 | for(int i = 0; i < M_NUM; i++) begin 94 | if(sel_reg[i]) s.rddata = rddata[i]; 95 | end 96 | end 97 | endmodule 98 | 99 | `endif 100 | -------------------------------------------------------------------------------- /chapter6/periph_pwm.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `timescale 1ns/100ps 3 | 4 | module Pwm2 ( 5 | input wire clk, rst, 6 | input wire [31 : 0] max, 7 | input wire [31 : 0] data, 8 | output logic pwm, co 9 | ); 10 | logic [31 : 0] cnt = '0; 11 | always_ff@(posedge clk) begin 12 | if(rst) cnt <= '0; 13 | else if(cnt < max) cnt <= cnt + 1'd1; 14 | else cnt <= '0; 15 | end 16 | always_ff@(posedge clk) pwm <= (data > cnt); 17 | assign co = cnt == max; 18 | endmodule 19 | 20 | module PeriphPwm ( 21 | input wire clk, rst, 22 | input wire addr, 23 | input wire [31 : 0] wrdata, 24 | input wire write, 25 | output logic [31 : 0] rddata, 26 | output logic pwm, co 27 | ); 28 | logic [31 : 0] period, duty; 29 | always_ff@(posedge clk) begin 30 | if(rst) begin 31 | period <= '0; 32 | duty <= '0; 33 | end 34 | else if(write) begin 35 | case(addr) 36 | 0: period <= wrdata; 37 | 1: duty <= wrdata; 38 | endcase 39 | end 40 | end 41 | assign rddata = addr == 0 ? period : duty; 42 | Pwm2 thePwm(clk, rst, period, duty, pwm, co); 43 | endmodule 44 | 45 | module PeriphPwm2 ( 46 | PicoMmIf.slave s, 47 | output logic pwm, co 48 | ); 49 | wire addr = s.addr >> 2; 50 | logic [31 : 0] period, duty; 51 | always_ff@(posedge s.clk) begin 52 | if(s.rst) begin 53 | period <= '0; 54 | duty <= '0; 55 | end 56 | else if(s.write) begin 57 | case(addr) 58 | 0: period <= s.wrdata; 59 | 1: duty <= s.wrdata; 60 | endcase 61 | end 62 | end 63 | always_ff@(posedge s.clk) s.rddata <= addr == 0 ? period : duty; 64 | Pwm2 thePwm(s.clk, s.rst, period, duty, pwm, co); 65 | endmodule 66 | -------------------------------------------------------------------------------- /chapter6/pico_mm_if.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter6/periph_pwm.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter6/periph_pwm.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling module Pwm2 4 | -- Compiling module PeriphPwm 5 | -- Compiling module PeriphPwm2 6 | 7 | Top level modules: 8 | PeriphPwm 9 | PeriphPwm2 10 | 11 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter6/periph_spi.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter6/periph_spi.sv 12 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 13 | -- Compiling package SimSrcGen 14 | -- Compiling package CombFunctions 15 | -- Compiling module TestCounter 16 | -- Importing package SimSrcGen 17 | -- Compiling module TestCntSecMinHr 18 | -- Compiling module CntSecMinHr 19 | -- Compiling module Counter 20 | -- Compiling module CounterMax 21 | -- Compiling module TestSpi 22 | -- Compiling module SpiMaster 23 | -- Compiling module SpiSlave 24 | -- Compiling module TestMem 25 | -- Compiling module SpRamRf 26 | -- Compiling module SpRamWf 27 | -- Compiling module SdpRamRf 28 | -- Compiling module DpRam 29 | -- Compiling module SdcRam 30 | -- Compiling module DcRam 31 | -- Compiling module SpRamRfSine 32 | -- Compiling module TestScFifo 33 | -- Compiling module ScFifo1 34 | -- Compiling module ScFifo2 35 | -- Compiling module PeriphSpiMaster 36 | -- Compiling module PeriphSpiMaster2 37 | -- Compiling module PeriphSpiMaster3 38 | 39 | Top level modules: 40 | TestCounter 41 | TestCntSecMinHr 42 | TestSpi 43 | TestMem 44 | SpRamRf 45 | SpRamWf 46 | DpRam 47 | SdcRam 48 | DcRam 49 | TestScFifo 50 | ScFifo1 51 | PeriphSpiMaster 52 | PeriphSpiMaster2 53 | PeriphSpiMaster3 54 | 55 | } {} {}} 56 | -------------------------------------------------------------------------------- /chapter6/sim_axi4lite_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestAxi4Lite/theIf/clk 4 | add wave -noupdate /TestAxi4Lite/theIf/reset_n 5 | add wave -noupdate -radix unsigned /TestAxi4Lite/theIf/araddr 6 | add wave -noupdate /TestAxi4Lite/theIf/arprot 7 | add wave -noupdate /TestAxi4Lite/theIf/arvalid 8 | add wave -noupdate /TestAxi4Lite/theIf/arready 9 | add wave -noupdate -radix decimal /TestAxi4Lite/theIf/rdata 10 | add wave -noupdate /TestAxi4Lite/theIf/rresp 11 | add wave -noupdate /TestAxi4Lite/theIf/rvalid 12 | add wave -noupdate /TestAxi4Lite/theIf/rready 13 | add wave -noupdate -radix unsigned /TestAxi4Lite/theIf/awaddr 14 | add wave -noupdate /TestAxi4Lite/theIf/awprot 15 | add wave -noupdate /TestAxi4Lite/theIf/awvalid 16 | add wave -noupdate /TestAxi4Lite/theIf/awready 17 | add wave -noupdate -radix decimal /TestAxi4Lite/theIf/wdata 18 | add wave -noupdate /TestAxi4Lite/theIf/wstrb 19 | add wave -noupdate /TestAxi4Lite/theIf/wvalid 20 | add wave -noupdate /TestAxi4Lite/theIf/wready 21 | add wave -noupdate /TestAxi4Lite/theIf/bresp 22 | add wave -noupdate /TestAxi4Lite/theIf/bvalid 23 | add wave -noupdate /TestAxi4Lite/theIf/bready 24 | add wave -noupdate -radix hexadecimal -childformat {{{/TestAxi4Lite/theSla/raddr_reg[2]} -radix hexadecimal} {{/TestAxi4Lite/theSla/raddr_reg[1]} -radix hexadecimal} {{/TestAxi4Lite/theSla/raddr_reg[0]} -radix hexadecimal}} -subitemconfig {{/TestAxi4Lite/theSla/raddr_reg[2]} {-height 15 -radix hexadecimal} {/TestAxi4Lite/theSla/raddr_reg[1]} {-height 15 -radix hexadecimal} {/TestAxi4Lite/theSla/raddr_reg[0]} {-height 15 -radix hexadecimal}} /TestAxi4Lite/theSla/raddr_reg 25 | add wave -noupdate -radix hexadecimal -childformat {{{/TestAxi4Lite/theSla/waddr_reg[2]} -radix hexadecimal} {{/TestAxi4Lite/theSla/waddr_reg[1]} -radix hexadecimal} {{/TestAxi4Lite/theSla/waddr_reg[0]} -radix hexadecimal}} -subitemconfig {{/TestAxi4Lite/theSla/waddr_reg[2]} {-height 15 -radix hexadecimal} {/TestAxi4Lite/theSla/waddr_reg[1]} {-height 15 -radix hexadecimal} {/TestAxi4Lite/theSla/waddr_reg[0]} {-height 15 -radix hexadecimal}} /TestAxi4Lite/theSla/waddr_reg 26 | add wave -noupdate -radix decimal -childformat {{{/TestAxi4Lite/regs[0]} -radix decimal} {{/TestAxi4Lite/regs[1]} -radix decimal} {{/TestAxi4Lite/regs[2]} -radix decimal} {{/TestAxi4Lite/regs[3]} -radix decimal} {{/TestAxi4Lite/regs[4]} -radix decimal} {{/TestAxi4Lite/regs[5]} -radix decimal} {{/TestAxi4Lite/regs[6]} -radix decimal} {{/TestAxi4Lite/regs[7]} -radix decimal}} -expand -subitemconfig {{/TestAxi4Lite/regs[0]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[1]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[2]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[3]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[4]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[5]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[6]} {-height 15 -radix decimal} {/TestAxi4Lite/regs[7]} {-height 15 -radix decimal}} /TestAxi4Lite/regs 27 | TreeUpdate [SetDefaultTree] 28 | WaveRestoreCursors {{Cursor 1} {16300 ps} 0} 29 | quietly wave cursor active 1 30 | configure wave -namecolwidth 115 31 | configure wave -valuecolwidth 86 32 | configure wave -justifyvalue left 33 | configure wave -signalnamewidth 1 34 | configure wave -snapdistance 10 35 | configure wave -datasetprefix 0 36 | configure wave -rowmargin 4 37 | configure wave -childrowmargin 2 38 | configure wave -gridoffset 7500 39 | configure wave -gridperiod 1 40 | configure wave -griddelta 40 41 | configure wave -timeline 0 42 | configure wave -timelineunits ns 43 | update 44 | WaveRestoreZoom {0 ps} {83200 ps} 45 | -------------------------------------------------------------------------------- /chapter6/sim_pico_mm_if_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider cu2ic 4 | add wave -noupdate /TestPicoMmIf/pico_cu2ic/clk 5 | add wave -noupdate /TestPicoMmIf/pico_cu2ic/rst 6 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestPicoMmIf/pico_cu2ic/addr 7 | add wave -noupdate /TestPicoMmIf/pico_cu2ic/write 8 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestPicoMmIf/pico_cu2ic/wrdata 9 | add wave -noupdate /TestPicoMmIf/pico_cu2ic/read 10 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestPicoMmIf/pico_cu2ic/rddata 11 | add wave -noupdate -divider ic2mem 12 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[0]/clk} 13 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[0]/rst} 14 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[0]/addr} 15 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[0]/write} 16 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[0]/wrdata} 17 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[0]/read} 18 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[0]/rddata} 19 | add wave -noupdate -divider ic2pwm 20 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[1]/clk} 21 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[1]/rst} 22 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[1]/addr} 23 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[1]/write} 24 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[1]/wrdata} 25 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[1]/read} 26 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[1]/rddata} 27 | add wave -noupdate -divider pwm 28 | add wave -noupdate /TestPicoMmIf/pwm 29 | add wave -noupdate -divider ic2spim 30 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[2]/clk} 31 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[2]/rst} 32 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[2]/addr} 33 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[2]/write} 34 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[2]/wrdata} 35 | add wave -noupdate {/TestPicoMmIf/pico_ic2per[2]/read} 36 | add wave -noupdate -radix hexadecimal -radixshowbase 0 {/TestPicoMmIf/pico_ic2per[2]/rddata} 37 | add wave -noupdate -divider spim 38 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestPicoMmIf/ss_n 39 | add wave -noupdate /TestPicoMmIf/sclk0 40 | add wave -noupdate /TestPicoMmIf/sclk1 41 | add wave -noupdate /TestPicoMmIf/mosi 42 | add wave -noupdate /TestPicoMmIf/mosi_tri 43 | add wave -noupdate /TestPicoMmIf/miso 44 | TreeUpdate [SetDefaultTree] 45 | WaveRestoreCursors {{Cursor 1} {48900 ps} 0} 46 | quietly wave cursor active 1 47 | configure wave -namecolwidth 150 48 | configure wave -valuecolwidth 100 49 | configure wave -justifyvalue left 50 | configure wave -signalnamewidth 1 51 | configure wave -snapdistance 10 52 | configure wave -datasetprefix 0 53 | configure wave -rowmargin 4 54 | configure wave -childrowmargin 2 55 | configure wave -gridoffset 7500 56 | configure wave -gridperiod 1 57 | configure wave -griddelta 40 58 | configure wave -timeline 0 59 | configure wave -timelineunits ns 60 | update 61 | WaveRestoreZoom {9100 ps} {17200 ps} 62 | -------------------------------------------------------------------------------- /chapter6/test_axi4lite.sv: -------------------------------------------------------------------------------- 1 | `include "../common.sv" 2 | `include "../chapter4/memory.sv" 3 | 4 | `default_nettype none 5 | `timescale 1ns/100ps 6 | 7 | module TestAxi4Lite; 8 | import SimSrcGen::*; 9 | logic clk; 10 | logic rst; 11 | initial GenClk(clk, 8, 10); 12 | initial GenRst(clk, rst, 2, 2); 13 | Axi4LiteIf #(5) theIf(clk, ~rst); 14 | logic start = '0; 15 | Axi4LiteMasterEg theMas(theIf, start); 16 | logic [31:0] regs[8]; 17 | Axi4LiteSlave #(8) theSla(theIf, regs); 18 | initial begin 19 | wait(rst); wait(~rst); 20 | theSla.regs = '{123, -2334, 48327342, -218377853, 232889, 33612, -812, -456783321}; 21 | end 22 | initial begin 23 | repeat(10) @(posedge clk); 24 | start = '1; 25 | @(posedge clk) start = '0; 26 | repeat(100) @(posedge clk); 27 | $stop(); 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /chapter6/test_pico_mm_if.sv: -------------------------------------------------------------------------------- 1 | `include "../common.sv" 2 | `include "../chapter4/memory.sv" 3 | 4 | `default_nettype none 5 | `timescale 1ns/100ps 6 | 7 | module TestPicoMmIf; 8 | import SimSrcGen::*; 9 | logic clk, rst; 10 | initial GenClk(clk, 8, 10); 11 | initial GenRst(clk, rst, 1, 1); 12 | PicoMmIf #(32) pico_cu2ic(clk, rst); 13 | PicoMmIf pico_ic2per[3](clk, rst); 14 | defparam pico_ic2per[0].AW = 16; 15 | defparam pico_ic2per[1].AW = 4; 16 | defparam pico_ic2per[2].AW = 4; 17 | PicoMmIntercon #(3, 18 | '{32'h0000_0000, 32'h0001_0000, 32'h0001_0010}) 19 | theIc( pico_cu2ic, pico_ic2per); 20 | SpRamRf #(32, 16384) theMem( pico_ic2per[0].clk, 21 | pico_ic2per[0].addr[15:2], pico_ic2per[0].write, 22 | pico_ic2per[0].wrdata, pico_ic2per[0].rddata); 23 | logic pwm, co; 24 | PeriphPwm2 thePwm(pico_ic2per[1], pwm, co); 25 | logic sclk0, sclk1, mosi, mosi_tri, miso = '1, busy; 26 | logic [23:0] ss_n; 27 | PeriphSpiMaster3 theSpim(pico_ic2per[2], 28 | sclk0, sclk1, mosi, mosi_tri, miso, ss_n, busy); 29 | initial begin 30 | repeat(10) @(posedge clk); 31 | // ==== test memory ==== 32 | // write 2 data 33 | pico_cu2ic.Write(32'h0000_0c00, 32'h1234_5678); 34 | pico_cu2ic.Write(32'h0000_0c04, 32'h9abc_edf0); 35 | // read 2 data 36 | pico_cu2ic.Read(32'h0000_0c00); 37 | pico_cu2ic.Read(32'h0000_0c04); 38 | // ==== test pwm ==== 39 | // set period = 100 clks, duty = 33% 40 | pico_cu2ic.Write(32'h0001_0000, 32'd99); 41 | pico_cu2ic.Write(32'h0001_0004, 32'd33); 42 | // read settings 43 | pico_cu2ic.Read(32'h0001_0000); 44 | pico_cu2ic.Read(32'h0001_0004); 45 | // ==== test spi ==== 46 | // prepare 2 data in tx fifo 47 | pico_cu2ic.Write(32'h0001_0010, 32'h7c); 48 | pico_cu2ic.Write(32'h0001_0010, 32'h5b); 49 | // start transaction 50 | pico_cu2ic.Write(32'h0001_0014, 32'h01_000001); 51 | // wait while SpiMaster busy 52 | do begin 53 | pico_cu2ic.Read(32'h0001_0018); 54 | @(posedge clk); 55 | end while( pico_cu2ic.rddata[16] ); 56 | // read data from rx fifo 57 | pico_cu2ic.Read(32'h0001_0010); 58 | pico_cu2ic.Read(32'h0001_0010); 59 | repeat(100) @(posedge clk); 60 | $stop(); 61 | end 62 | endmodule 63 | -------------------------------------------------------------------------------- /chapter6/vish_stacktrace.vstf: -------------------------------------------------------------------------------- 1 | # Current time Fri Jun 02 16:43:57 2017 2 | # ModelSim PE Student Edition Stack Trace 3 | # Program = vish 4 | # Id = "10.4a" 5 | # Version = "2015.03" 6 | # Date = "Apr 7 2015" 7 | # Platform = win32pe 8 | 9 | Exception c0000005 has occurred at address 0058827b. Traceback: 10 | -------------------------------------------------------------------------------- /chapter6/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter6/vsim.wlf -------------------------------------------------------------------------------- /chapter7/chapter7.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/slow_div.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter7/slow_div.sv 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling module TestCounter 6 | -- Importing package SimSrcGen 7 | -- Compiling module TestCntSecMinHr 8 | -- Compiling module CntSecMinHr 9 | -- Compiling module Counter 10 | -- Compiling module CounterMax 11 | -- Compiling module TestSlowDiv 12 | -- Compiling module SlowDiv 13 | 14 | Top level modules: 15 | TestCounter 16 | TestCntSecMinHr 17 | CounterMax 18 | TestSlowDiv 19 | 20 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter7/slow_mult.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter7/slow_mult.sv 21 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 22 | -- Compiling package SimSrcGen 23 | -- Compiling package CombFunctions 24 | -- Compiling module TestCounter 25 | -- Importing package SimSrcGen 26 | -- Compiling module TestCntSecMinHr 27 | -- Compiling module CntSecMinHr 28 | -- Compiling module Counter 29 | -- Compiling module CounterMax 30 | -- Compiling module TestSlowMult 31 | -- Compiling module SlowMult 32 | 33 | Top level modules: 34 | TestCounter 35 | TestCntSecMinHr 36 | CounterMax 37 | TestSlowMult 38 | 39 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter7/slow_sqrt.sv {1 {vlog -work work -vopt -sv Z:/projects/modelsim/FPGA_Book_2017/chapter7/slow_sqrt.sv 40 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 41 | -- Compiling package SimSrcGen 42 | -- Compiling package CombFunctions 43 | -- Compiling module TestSlowSqrt 44 | -- Importing package SimSrcGen 45 | -- Compiling module SlowSqrt 46 | 47 | Top level modules: 48 | TestSlowSqrt 49 | 50 | } {} {}} 51 | -------------------------------------------------------------------------------- /chapter7/cordic.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/cordic.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/cordic.sv 2 | Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCordic 7 | -- Importing package SimSrcGen 8 | -- Compiling module CordicStage 9 | -- Compiling module Cordic 10 | -- Importing package Fixedpoint 11 | 12 | Top level modules: 13 | TestCordic 14 | 15 | } {} {}} 16 | -------------------------------------------------------------------------------- /chapter7/cordic2.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/cordic2.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/cordic2.sv 2 | Model Technology ModelSim SE-64 vlog 10.6e Compiler 2018.06 Jun 23 2018 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCordic2 7 | -- Importing package SimSrcGen 8 | -- Compiling module CordicRotStage 9 | -- Compiling module CordicVecStage 10 | -- Compiling module Cordic2 11 | -- Importing package Fixedpoint 12 | 13 | Top level modules: 14 | TestCordic2 15 | 16 | } {} {}} 17 | -------------------------------------------------------------------------------- /chapter7/cordic_str.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/cordic_str.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/cordic_str.sv 2 | Model Technology ModelSim SE-64 vlog 10.6e Compiler 2018.06 Jun 23 2018 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCordicStr 7 | -- Importing package SimSrcGen 8 | -- Compiling module CordicRotStage 9 | -- Compiling module CordicVecStage 10 | -- Compiling module CordicQuadrantTrans 11 | -- Compiling module CordicStr 12 | -- Importing package Fixedpoint 13 | 14 | Top level modules: 15 | TestCordicStr 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /chapter7/dds.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/dds.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/dds.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling module TestDDS 6 | -- Importing package SimSrcGen 7 | -- Compiling module DDS 8 | 9 | Top level modules: 10 | TestDDS 11 | 12 | } {} {}} 13 | -------------------------------------------------------------------------------- /chapter7/dds.sv: -------------------------------------------------------------------------------- 1 | `ifndef __DDS_SV__ 2 | `define __DDS_SV__ 3 | 4 | `include "../common.sv" 5 | 6 | `timescale 1ns/100ps 7 | `default_nettype none 8 | 9 | module TestDDS; 10 | import SimSrcGen::*; 11 | logic clk, rst; 12 | initial GenClk(clk, 80, 100); 13 | initial GenRst(clk, rst, 2, 2); 14 | real freqr = 1e6, fstepr = 49e6/(1e-3*100e6); // from 1MHz to 50MHz in 1ms 15 | always@(posedge clk) begin 16 | if(rst) freqr = 1e6; 17 | else freqr += fstepr; 18 | end 19 | logic signed [31:0] freq; 20 | always@(posedge clk) begin 21 | freq <= 2.0**32 * freqr / 100e6; // frequency to freq control word 22 | end 23 | logic signed [31:0] phase = '0; 24 | logic signed [9:0] swave; 25 | DDS #(32, 10, 13) theDDS(clk, rst, 1'b1, freq, phase, swave); 26 | endmodule 27 | 28 | module DDS #( 29 | parameter PW = 32, DW = 10, AW = 13 30 | )( 31 | input wire clk, rst, en, 32 | input wire signed [PW - 1 : 0] freq, phase, 33 | output logic signed [DW - 1 : 0] out 34 | ); 35 | localparam LEN = 2**AW; 36 | localparam real PI = 3.1415926535897932; 37 | logic signed [DW-1 : 0] sine[LEN]; 38 | initial begin 39 | for(int i = 0; i < LEN; i++) begin 40 | sine[i] = $sin(2.0 * PI * i / LEN) * (2.0**(DW-1) - 1.0); 41 | end 42 | end 43 | logic [PW-1 : 0] phaseAcc; 44 | always_ff@(posedge clk) begin 45 | if(rst) phaseAcc <= '0; 46 | else if(en) phaseAcc <= phaseAcc + freq; 47 | end 48 | wire [PW-1 : 0] phaseSum = phaseAcc + phase; 49 | always_ff@(posedge clk) begin 50 | if(rst) out <= '0; 51 | else if(en) out <= sine[phaseSum[PW-1 -: AW]]; 52 | end 53 | endmodule 54 | 55 | module OrthDDS #( 56 | parameter PW = 32, DW = 10, AW = 13 57 | )( 58 | input wire clk, rst, en, 59 | input wire signed [PW - 1 : 0] freq, phase, 60 | output logic signed [DW - 1 : 0] sin, cos 61 | ); 62 | localparam LEN = 2**AW; 63 | localparam real PI = 3.1415926535897932; 64 | logic signed [DW-1 : 0] sine[LEN]; 65 | initial begin 66 | for(int i = 0; i < LEN; i++) begin 67 | sine[i] = $sin(2.0 * PI * i / LEN) * (2.0**(DW-1) - 1.0); 68 | end 69 | end 70 | logic [PW-1 : 0] phaseAcc, phSum0, phSum1; 71 | always_ff@(posedge clk) begin 72 | if(rst) phaseAcc <= '0; 73 | else if(en) phaseAcc <= phaseAcc + freq; 74 | end 75 | always_ff@(posedge clk) begin 76 | if(rst) begin 77 | phSum0 <= '0; 78 | phSum1 <= PW'(1) <<< (PW-2); // 90deg 79 | end 80 | else if(en) begin 81 | phSum0 <= phaseAcc + phase; 82 | phSum1 <= phaseAcc + phase + (PW'(1) <<< (PW-2)); 83 | end 84 | end 85 | always_ff@(posedge clk) begin 86 | if(rst) sin <= '0; 87 | else if(en) sin <= sine[phSum0[PW-1 -: AW]]; 88 | end 89 | always_ff@(posedge clk) begin 90 | if(rst) cos <= '0; 91 | else if(en) cos <= sine[phSum1[PW-1 -: AW]]; 92 | end 93 | endmodule 94 | 95 | `endif 96 | -------------------------------------------------------------------------------- /chapter7/fft_mem.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/mm_fft.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/mm_fft.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestMem 7 | -- Importing package SimSrcGen 8 | -- Compiling module SpRamRf 9 | -- Compiling module SpRamWf 10 | -- Compiling module SdpRamRf 11 | -- Compiling module DpRam 12 | -- Compiling module SdcRam 13 | -- Compiling module DcRam 14 | -- Compiling module SpRamRfSine 15 | -- Compiling interface PicoMmIf 16 | -- Compiling module PicoMmInterconnector1to3 17 | -- Compiling module PicoMmIntercon 18 | -- Compiling module TestMmFFT 19 | -- Compiling module FFTCoefRom 20 | -- Compiling module MmFFT 21 | 22 | Top level modules: 23 | TestMem 24 | SpRamWf 25 | SdpRamRf 26 | DpRam 27 | SdcRam 28 | DcRam 29 | PicoMmInterconnector1to3 30 | PicoMmIntercon 31 | TestMmFFT 32 | 33 | } {} {}} 34 | -------------------------------------------------------------------------------- /chapter7/fir.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/fir.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/fir.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling module TestCounter 6 | -- Importing package SimSrcGen 7 | -- Compiling module TestCntSecMinHr 8 | -- Compiling module CntSecMinHr 9 | -- Compiling module Counter 10 | -- Compiling module CounterMax 11 | -- Compiling module TestDDS 12 | -- Compiling module DDS 13 | -- Compiling module TestFir 14 | -- Compiling module FIR 15 | 16 | Top level modules: 17 | TestCounter 18 | TestCntSecMinHr 19 | CounterMax 20 | TestDDS 21 | TestFir 22 | 23 | } {} {}} 24 | -------------------------------------------------------------------------------- /chapter7/fir.sv: -------------------------------------------------------------------------------- 1 | `ifndef __FIR_SV__ 2 | `define __FIR_SV__ 3 | 4 | `include "../common.sv" 5 | `include "../chapter4/counter.sv" 6 | `include "./dds.sv" 7 | 8 | `timescale 1ns/100ps 9 | `default_nettype none 10 | 11 | module TestFir; 12 | import SimSrcGen::*; 13 | logic clk, rst; 14 | initial GenClk(clk, 80, 100); 15 | initial GenRst(clk, rst, 2, 2); 16 | real freqr = 1e6, fstepr = 49e6/(1e-3*100e6); // from 1MHz to 50MHz in 1ms 17 | always@(posedge clk) begin 18 | if(rst) freqr = 1e6; 19 | else freqr += fstepr; 20 | end 21 | logic signed [31:0] freq; 22 | always@(posedge clk) begin 23 | freq <= 2.0**32 * freqr / 100e6; // frequency to freq control word 24 | end 25 | logic signed [31:0] phase = '0; 26 | logic signed [9:0] swave; 27 | DDS #(32, 10, 13) theDDS(clk, rst, 1'b1, freq, phase, swave); 28 | logic signed [9:0] filtered, harm3; 29 | logic square = '0, en15; 30 | Counter #(15) cnt15(clk, rst, 1'b1, , en15); 31 | always_ff@(posedge clk) if(en15) square <= ~square; 32 | FIR #(10, 27, '{ -0.005646, 0.006428, 0.019960, 0.033857, 0.036123, 33 | 0.016998, -0.022918, -0.068988, -0.097428, -0.087782, 34 | -0.036153, 0.039431, 0.106063, 0.132519, 0.106063, 35 | 0.039431, -0.036153, -0.087782, -0.097428, -0.068988, 36 | -0.022918, 0.016998, 0.036123, 0.033857, 0.019960, 37 | 0.006428, -0.005646 38 | }) theFir1(clk, rst, 1'b1, 10'(integer'(swave * 0.9)), filtered), 39 | theFir2(clk, rst, 1'b1, square ? 10'sd500 : -10'sd500, harm3); 40 | endmodule 41 | 42 | module FIR #( 43 | parameter DW = 10, 44 | parameter TAPS = 8, 45 | parameter real COEF[TAPS] = '{TAPS{0.124}} 46 | )( 47 | input wire clk, rst, en, 48 | input wire signed [DW-1 : 0] in, // Q1.9 49 | output logic signed [DW-1 : 0] out // Q1.9 50 | ); 51 | localparam N = TAPS - 1; 52 | logic signed [DW-1 : 0] coef[TAPS]; 53 | logic signed [DW-1 : 0] prod[TAPS]; 54 | logic signed [DW-1 : 0] delay[TAPS]; 55 | //`DEF_FP_MUL(mul, 1, DW-1, 1, DW-1, DW-1); //Q1.9 * Q1.9 -> Q1.9 56 | generate 57 | for(genvar t = 0; t < TAPS; t++) begin 58 | assign coef[t] = COEF[t] * 2.0**(DW-1.0); 59 | assign prod[t] = //mul(in, coef[t]); 60 | ( (2*DW)'(in) * (2*DW)'(coef[t]) ) >>> (DW-1); 61 | 62 | end 63 | endgenerate 64 | generate 65 | for(genvar t = 0; t < TAPS; t++) begin 66 | always_ff@(posedge clk) begin 67 | if(rst) delay[t] <= '0; 68 | else if(en) begin 69 | if(t == 0) delay[0] <= prod[N - t]; 70 | else delay[t] <= prod[N - t] + delay[t - 1]; 71 | end 72 | end 73 | end 74 | endgenerate 75 | assign out = delay[N]; 76 | endmodule 77 | 78 | `endif 79 | -------------------------------------------------------------------------------- /chapter7/fixedpoint_pkg.sv.obs: -------------------------------------------------------------------------------- 1 | 2 | package Fixedpoint; 3 | let max(x, y) = x > y? x : y; 4 | `define DEF_FP_ADD(name, i0, f0, i1, f1, fr) \ 5 | let name(x, y) = \ 6 | ((f0) >= (f1)) ? \ 7 | ( ( max((i0),(i1))+(f0))'(x) + \ 8 | ( (max((i0),(i1))+(f0))'(y) <<< ((f0)-(f1)) ) \ 9 | ) >>> ((f0)-(fr)) : \ 10 | ( ( (max((i0),(i1))+(f1))'(x) <<< ((f1)-(f0)) ) + \ 11 | (max((i0),(i1))+(f1))'(y) \ 12 | ) >>> ((f1)-(fr)); 13 | `define DEF_FP_MUL(name, i0, f0, i1, f1, fr) \ 14 | let name(x, y) = \ 15 | ( ((i0)+(i1)+(f0)+(f1))'(x) * ((i0)+(i1)+(f0)+(f1))'(y) \ 16 | ) >>> ((f0)+(f1)-(fr)); 17 | endpackage -------------------------------------------------------------------------------- /chapter7/iir.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/iir.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/iir.sv 2 | Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCounter 7 | -- Importing package SimSrcGen 8 | -- Compiling module TestCntSecMinHr 9 | -- Compiling module CntSecMinHr 10 | -- Compiling module Counter 11 | -- Compiling module CounterMax 12 | -- Compiling module TestDDS 13 | -- Compiling module DDS 14 | -- Compiling module OrthDDS 15 | -- Compiling module TestIir 16 | -- Compiling module IIR 17 | -- Compiling module IIR2nd 18 | -- Importing package Fixedpoint 19 | 20 | Top level modules: 21 | TestCounter 22 | TestCntSecMinHr 23 | CounterMax 24 | TestDDS 25 | OrthDDS 26 | TestIir 27 | 28 | } {} {}} 29 | -------------------------------------------------------------------------------- /chapter7/iir.sv: -------------------------------------------------------------------------------- 1 | `ifndef __IIR_SV__ 2 | `define __IIR_SV__ 3 | 4 | `include "../common.sv" 5 | `include "../chapter4/counter.sv" 6 | `include "./dds.sv" 7 | 8 | `timescale 1ns/100ps 9 | `default_nettype none 10 | 11 | module TestIir; 12 | import SimSrcGen::*; 13 | logic clk, rst; 14 | initial GenClk(clk, 80, 100); 15 | initial GenRst(clk, rst, 2, 2); 16 | real freqr = 1e6, fstepr = 49e6/(1e-3*100e6); // from 1MHz to 50MHz in 1ms 17 | always@(posedge clk) begin 18 | if(rst) freqr = 1e6; 19 | else freqr += fstepr; 20 | end 21 | logic signed [31:0] freq; 22 | always@(posedge clk) begin 23 | freq <= 2.0**32 * freqr / 100e6; // freq control word 24 | end 25 | logic signed [31:0] phase = '0; 26 | logic signed [9:0] swave; 27 | DDS #(32, 10, 13) theDDS(clk, rst, 1'b1, freq, phase, swave); 28 | logic signed [9:0] filtered, harm3; 29 | logic square = '0, en15; 30 | Counter #(15) cnt15(clk, rst, 1'b1, , en15); 31 | always_ff@(posedge clk) if(en15) square <= ~square; 32 | IIR #(10, 5, 3, '{ 0.262748, 0.262748, 0.060908 }, // GAIN 33 | '{ '{ 1, -1.368053, 1 }, // s0:NUM 34 | '{ 1, -1.779618, 1 }, // s1:NUM 35 | '{ 1, 0 , -1 } }, // s2:NUM 36 | '{ '{ -1.519556, 0.969571}, // s0:DEN 37 | '{ -1.665517, 0.974258}, // s1:DEN 38 | '{ -1.569518, 0.936203} } // s2:DEN 39 | ) theIir1(clk, rst, 1'b1, 10'(integer'(swave * 0.9)), filtered), 40 | theIir2(clk, rst, 1'b1, square?10'sd500:-10'sd500, harm3); 41 | endmodule 42 | 43 | module IIR #( 44 | parameter DW = 10, EW = 4, STG = 2, 45 | parameter real GAIN[STG], real NUM[STG][3], real DEN[STG][2] 46 | )( 47 | input wire clk, rst, en, 48 | input wire signed [DW-1 : 0] in, 49 | output logic signed [DW-1 : 0] out 50 | ); 51 | localparam W = EW + DW; 52 | logic signed [W-1 : 0] sio[STG+1]; 53 | assign sio[0] = in, out = sio[STG]; 54 | generate 55 | for(genvar s = 0; s < STG; s++) begin 56 | IIR2nd #(W, DW-1, GAIN[s], NUM[s], DEN[s]) theIir(clk, rst, en, sio[s], sio[s+1]); 57 | end 58 | endgenerate 59 | endmodule 60 | 61 | module IIR2nd #( 62 | parameter DW = 14, FW = 9, 63 | parameter real GAIN, real NUM[3], real DEN[2] 64 | )( 65 | input wire clk, rst, en, 66 | input wire signed [DW-1 : 0] in, // Q(DW-FW).FW 67 | output logic signed [DW-1 : 0] out // Q(DW-FW).FW 68 | ); 69 | import Fixedpoint::*; 70 | wire signed [DW-1:0] n0 = (NUM[0] * 2.0**FW); 71 | wire signed [DW-1:0] n1 = (NUM[1] * 2.0**FW); 72 | wire signed [DW-1:0] n2 = (NUM[2] * 2.0**FW); 73 | wire signed [DW-1:0] d1 = (DEN[0] * 2.0**FW); 74 | wire signed [DW-1:0] d2 = (DEN[1] * 2.0**FW); 75 | wire signed [DW-1:0] g = (GAIN * 2.0**FW); 76 | `DEF_FP_MUL(mul, DW-FW, FW, DW-FW, FW, FW); 77 | logic signed [DW-1:0] z1, z0; 78 | wire signed [DW-1:0] pn0 = mul(in, n0); 79 | wire signed [DW-1:0] pn1 = mul(in, n1); 80 | wire signed [DW-1:0] pn2 = mul(in, n2); 81 | wire signed [DW-1:0] pd1 = mul(o, d1); 82 | wire signed [DW-1:0] pd2 = mul(o, d2); 83 | wire signed [DW-1:0] o = pn0 + z0; 84 | always_ff@(posedge clk) begin 85 | if(rst) begin z0 <= '0; z1 <= '0; out <= '0; end 86 | else if(en) begin 87 | z1 <= pn2 - pd2; 88 | z0 <= pn1 - pd1 + z1; 89 | out <= mul(o, g); 90 | end 91 | end 92 | endmodule 93 | 94 | `endif 95 | -------------------------------------------------------------------------------- /chapter7/intp_deci.sv: -------------------------------------------------------------------------------- 1 | `ifndef __INTP_DECI_SV__ 2 | `define __INTP_DECI_SV__ 3 | 4 | `timescale 1ns/100ps 5 | `default_nettype none 6 | 7 | module InterpDeci #( 8 | parameter integer W = 10, 9 | parameter logic HOLD = 0 10 | )( 11 | input wire clk, rst, eni, eno, 12 | input wire signed [W-1:0] in, 13 | output logic signed [W-1:0] out 14 | ); 15 | logic signed [W-1:0] candi; 16 | always_ff@(posedge clk) begin 17 | if(rst) candi <= '0; 18 | else if(eni) candi <= in; 19 | else if(eno) candi <= HOLD ? candi : '0; 20 | end 21 | always_ff@(posedge clk) begin 22 | if(rst) out <= '0; 23 | else if(eno) out <= candi; 24 | end 25 | endmodule 26 | 27 | `endif 28 | -------------------------------------------------------------------------------- /chapter7/pid.sv: -------------------------------------------------------------------------------- 1 | `ifndef __PID_SV__ 2 | `define __PID_SV__ 3 | 4 | `include "../common.sv" 5 | 6 | module Pid #( 7 | parameter W = 32, FW = 16, 8 | parameter real P = 8, real I = 192, real D = 0, 9 | parameter real N = 100, real TS = 0.002, 10 | parameter real LIMIT = 10000 11 | )( 12 | input wire clk, rst, en, 13 | input wire signed [W-1:0] in, 14 | output logic signed [W-1:0] out 15 | ); 16 | import Fixedpoint::*; 17 | wire signed [W-1:0] p = P * (2.0 ** FW); 18 | wire signed [W-1:0] i = (I * TS) * (2.0 ** FW); 19 | wire signed [W-1:0] d = D * (2.0 ** FW); 20 | wire signed [W-1:0] n = N * (2.0 ** FW); 21 | wire signed [W-1:0] ts = TS * (2.0 ** FW); 22 | wire signed [W-1:0] lim = LIMIT * (2.0 ** FW); 23 | `DEF_FP_MUL(mul, W-FW, FW, W-FW, FW, FW); 24 | wire signed [W-1:0] xp = mul(in, p); 25 | wire signed [W-1:0] xi = mul(in, i); 26 | logic signed [W-1:0] xi_acc; 27 | always_ff@(posedge clk) begin 28 | if(rst) xi_acc <= 1'sb0; 29 | else if(en) begin 30 | if(xi_acc + xi > lim) xi_acc <= lim; 31 | else if(xi_acc + xi < -lim) xi_acc <= -lim; 32 | else xi_acc <= xi_acc + xi; 33 | end 34 | end 35 | logic signed [W-1:0] dacc; 36 | wire signed [W-1:0] xd = mul(in, d); 37 | wire signed [W-1:0] xnd = mul((xd - dacc), n); 38 | wire signed [W-1:0] tnd = mul(xnd, ts); 39 | always_ff@(posedge clk) begin 40 | if(rst) dacc <= 1'sb0; 41 | else if(en) begin 42 | if(dacc + tnd > lim) dacc = lim; 43 | else if(dacc + tnd < -lim) dacc = -lim; 44 | else dacc <= dacc + tnd; 45 | end 46 | end 47 | always_ff@(posedge clk) begin 48 | if(rst) out <= 1'sb0; 49 | else if(en) out <= xp + xi_acc + xnd; 50 | end 51 | endmodule 52 | 53 | `endif 54 | -------------------------------------------------------------------------------- /chapter7/pid2.sv: -------------------------------------------------------------------------------- 1 | `ifndef __PID_SV__ 2 | `define __PID_SV__ 3 | 4 | `include "../common.sv" 5 | 6 | module Pid2 #( 7 | parameter W = 32, FW = 16, 8 | parameter real P = 8, real I = 192, real D = 0, 9 | parameter real N = 100, real TS = 0.002, 10 | parameter real LIMIT = 10000 11 | )( 12 | input wire clk, rst, en, 13 | input wire signed [W-1:0] in, 14 | output logic signed [W-1:0] out 15 | ); 16 | import Fixedpoint::*; 17 | wire signed [W-1:0] p = P * (2.0 ** FW); 18 | wire signed [W-1:0] i = (I * TS) * (2.0 ** FW); // actually i * ts 19 | wire signed [W-1:0] d = (D / TS) * (2.0 ** FW); // actually d / ts 20 | wire signed [W-1:0] n = (N * TS) * (2.0 ** FW); // actually n * ts 21 | // wire signed [W-1:0] ts = TS * (2.0 ** FW); 22 | wire signed [W-1:0] ialim = LIMIT * (2.0 ** FW); 23 | wire signed [W-1:0] dalim = (LIMIT / (N*TS > 0.0 ? N*TS : -N*TS)) * (2.0 ** FW); 24 | `DEF_FP_MUL(mul, W-FW, FW, W-FW, FW, FW); 25 | wire signed [W-1:0] xp = mul(in, p); 26 | wire signed [W-1:0] xi = mul(in, i); 27 | logic signed [W-1:0] xi_acc; 28 | always_ff@(posedge clk) begin 29 | if(rst) xi_acc <= 1'sb0; 30 | else if(en) begin 31 | if(xi_acc + xi > ialim) xi_acc <= ialim; 32 | else if(xi_acc + xi < -ialim) xi_acc <= -ialim; 33 | else xi_acc <= xi_acc + xi; 34 | end 35 | end 36 | logic signed [W-1:0] dacc; 37 | wire signed [W-1:0] xd = mul(in, d); 38 | wire signed [W-1:0] xnd = mul((xd - dacc), n); 39 | // wire signed [W-1:0] tnd = mul(xnd, ts); 40 | always_ff@(posedge clk) begin 41 | if(rst) dacc <= 1'sb0; 42 | else if(en) begin 43 | if(dacc + xnd > dalim) dacc = dalim; 44 | else if(dacc + xnd < -dalim) dacc = -dalim; 45 | else dacc <= dacc + xnd; 46 | end 47 | end 48 | always_ff@(posedge clk) begin 49 | if(rst) out <= 1'sb0; 50 | else if(en) out <= xp + xi_acc + xnd; 51 | end 52 | endmodule 53 | 54 | `endif 55 | -------------------------------------------------------------------------------- /chapter7/r22sdf.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/r22sdf.sv {2 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/r22sdf.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module DelayChainMem 7 | -- Compiling module TestDelayChainMem 8 | -- Importing package SimSrcGen 9 | -- Compiling module TestR22Sdf 10 | -- Importing package R22SdfDefines 11 | -- Compiling package R22SdfDefines 12 | -- Compiling module Bf2I 13 | -- Compiling module Bf2II 14 | -- Compiling module R22SdfCoefRom 15 | -- Compiling module R22Sdf 16 | ** Warning: Z:/projects/modelsim/FPGA_Book_2017/chapter7/r22sdf.sv(155): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. 17 | 18 | 19 | Top level modules: 20 | TestDelayChainMem 21 | TestR22Sdf 22 | 23 | } {} {}} 24 | -------------------------------------------------------------------------------- /chapter7/r2sdf.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter7/sim_cordic_str_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -radix binary /TestCordicStr/clk 4 | add wave -noupdate -radix binary /TestCordicStr/rst 5 | add wave -noupdate -format Analog-Step -height 74 -max 32766.999999999993 -min -32768.0 -radix decimal /TestCordicStr/ang 6 | add wave -noupdate -radix binary /TestCordicStr/rot_ready 7 | add wave -noupdate -format Analog-Step -height 74 -max 30002.000000000007 -min -30003.0 -radix decimal /TestCordicStr/cos 8 | add wave -noupdate -format Analog-Step -height 74 -max 30002.000000000007 -min -30003.0 -radix decimal /TestCordicStr/sin 9 | add wave -noupdate -radix decimal /TestCordicStr/arem 10 | add wave -noupdate -radix binary /TestCordicStr/inter_valid 11 | add wave -noupdate -radix binary /TestCordicStr/inter_ready 12 | add wave -noupdate -radix decimal /TestCordicStr/xrem 13 | add wave -noupdate -radix decimal /TestCordicStr/yrem 14 | add wave -noupdate -format Analog-Step -height 74 -max 32767.0 -min -32767.0 -radix decimal /TestCordicStr/aout 15 | add wave -noupdate -radix binary /TestCordicStr/vec_valid 16 | add wave -noupdate /TestCordicStr/angle_out 17 | add wave -noupdate /TestCordicStr/angle_ref 18 | add wave -noupdate -group rot_stgs /TestCordicStr/theRotCordic/a 19 | add wave -noupdate -group rot_stgs /TestCordicStr/theRotCordic/x 20 | add wave -noupdate -group rot_stgs /TestCordicStr/theRotCordic/y 21 | add wave -noupdate -group rot_stgs /TestCordicStr/theRotCordic/r 22 | add wave -noupdate -group rot_stgs /TestCordicStr/theRotCordic/v 23 | add wave -noupdate -expand -group vec_stgs /TestCordicStr/theVecCordic/a 24 | add wave -noupdate -expand -group vec_stgs /TestCordicStr/theVecCordic/x 25 | add wave -noupdate -expand -group vec_stgs /TestCordicStr/theVecCordic/y 26 | add wave -noupdate -expand -group vec_stgs -expand /TestCordicStr/theVecCordic/r 27 | add wave -noupdate -expand -group vec_stgs -expand /TestCordicStr/theVecCordic/v 28 | TreeUpdate [SetDefaultTree] 29 | WaveRestoreCursors {{Cursor 1} {634393000 ps} 0} {{Cursor 2} {327913000 ps} 0} 30 | quietly wave cursor active 1 31 | configure wave -namecolwidth 150 32 | configure wave -valuecolwidth 100 33 | configure wave -justifyvalue left 34 | configure wave -signalnamewidth 1 35 | configure wave -snapdistance 10 36 | configure wave -datasetprefix 0 37 | configure wave -rowmargin 4 38 | configure wave -childrowmargin 2 39 | configure wave -gridoffset 0 40 | configure wave -gridperiod 62500000 41 | configure wave -griddelta 10 42 | configure wave -timeline 0 43 | configure wave -timelineunits us 44 | update 45 | WaveRestoreZoom {0 ps} {980 us} 46 | -------------------------------------------------------------------------------- /chapter7/sim_fir_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestFir/clk 4 | add wave -noupdate -format Analog-Step -height 74 -max 511.0 -min -511.0 -radix decimal -radixshowbase 1 /TestFir/swave 5 | add wave -noupdate -format Analog-Step -height 74 -max 511.0 -min -512.0 -radix decimal -radixshowbase 1 /TestFir/filtered 6 | add wave -noupdate /TestFir/square 7 | add wave -noupdate -format Analog-Step -height 74 -max 202.0 -min -229.0 -radix decimal -radixshowbase 0 /TestFir/harm3 8 | TreeUpdate [SetDefaultTree] 9 | WaveRestoreCursors {{Cursor 1} {90563000 ps} 0} 10 | quietly wave cursor active 1 11 | configure wave -namecolwidth 81 12 | configure wave -valuecolwidth 49 13 | configure wave -justifyvalue left 14 | configure wave -signalnamewidth 1 15 | configure wave -snapdistance 10 16 | configure wave -datasetprefix 0 17 | configure wave -rowmargin 4 18 | configure wave -childrowmargin 2 19 | configure wave -gridoffset 7500 20 | configure wave -gridperiod 1 21 | configure wave -griddelta 40 22 | configure wave -timeline 0 23 | configure wave -timelineunits ns 24 | update 25 | WaveRestoreZoom {90132 ns} {91470800 ps} 26 | -------------------------------------------------------------------------------- /chapter7/sim_iir_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestIir/clk 4 | add wave -noupdate /TestIir/rst 5 | add wave -noupdate -format Analog-Step -height 74 -max 511.0 -min -511.0 -radix decimal -radixshowbase 0 /TestIir/swave 6 | add wave -noupdate -format Analog-Step -height 74 -max 511.00000000000006 -min -512.0 -radix decimal -radixshowbase 0 /TestIir/filtered 7 | add wave -noupdate /TestIir/square 8 | add wave -noupdate -format Analog-Step -height 74 -max 233.99999999999997 -min -228.0 -radix decimal -radixshowbase 0 /TestIir/harm3 9 | TreeUpdate [SetDefaultTree] 10 | WaveRestoreCursors {{Cursor 1} {138393000 ps} 0} 11 | quietly wave cursor active 1 12 | configure wave -namecolwidth 150 13 | configure wave -valuecolwidth 100 14 | configure wave -justifyvalue left 15 | configure wave -signalnamewidth 1 16 | configure wave -snapdistance 10 17 | configure wave -datasetprefix 0 18 | configure wave -rowmargin 4 19 | configure wave -childrowmargin 2 20 | configure wave -gridoffset 7500 21 | configure wave -gridperiod 1 22 | configure wave -griddelta 40 23 | configure wave -timeline 0 24 | configure wave -timelineunits ns 25 | update 26 | WaveRestoreZoom {0 ps} {525001100 ps} 27 | -------------------------------------------------------------------------------- /chapter7/sim_pid_inverter.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestPID/rst 4 | add wave -noupdate /TestPID/pwm 5 | add wave -noupdate -format Analog-Step -height 40 -max 1536.0 -min -1536.0 -radix decimal -radixshowbase 0 /TestPID/brg_out 6 | add wave -noupdate /TestPID/inn_res 7 | add wave -noupdate /TestPID/load_res 8 | add wave -noupdate /TestPID/des_amp 9 | add wave -noupdate /TestPID/vpwr 10 | add wave -noupdate -format Analog-Step -height 74 -max 11.234700000000002 -min -11.1768 /TestPID/out_volt 11 | add wave -noupdate -format Analog-Step -height 74 -max 1279.0 -min -1280.0 -radix decimal -radixshowbase 0 /TestPID/inverterCtrl/sin_volt 12 | add wave -noupdate -format Analog-Step -height 40 -max 1000.0 -min -1000.0 -radix decimal -radixshowbase 0 /TestPID/inverterCtrl/v_err 13 | add wave -noupdate -format Analog-Step -height 74 -max 640.0 -min -860.0 -radix decimal -radixshowbase 0 /TestPID/inverterCtrl/pid_out_int 14 | add wave -noupdate /TestPID/inverterCtrl/spwm 15 | TreeUpdate [SetDefaultTree] 16 | WaveRestoreCursors {{Cursor 1} {44960635568 ps} 0} 17 | quietly wave cursor active 1 18 | configure wave -namecolwidth 105 19 | configure wave -valuecolwidth 66 20 | configure wave -justifyvalue left 21 | configure wave -signalnamewidth 1 22 | configure wave -snapdistance 10 23 | configure wave -datasetprefix 0 24 | configure wave -rowmargin 4 25 | configure wave -childrowmargin 2 26 | configure wave -gridoffset 7500 27 | configure wave -gridperiod 1 28 | configure wave -griddelta 40 29 | configure wave -timeline 0 30 | configure wave -timelineunits ms 31 | update 32 | WaveRestoreZoom {0 ps} {47250003150 ps} 33 | -------------------------------------------------------------------------------- /chapter7/sim_r2sdf_2s_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestR2Sdf/clk 4 | add wave -noupdate /TestR2Sdf/rst 5 | add wave -noupdate /TestR2Sdf/sc 6 | add wave -noupdate /TestR2Sdf/inv 7 | add wave -noupdate /TestR2Sdf/sync 8 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestR2Sdf/cnt 9 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestR2Sdf/cntidx 10 | add wave -noupdate -radix decimal -radixshowbase 0 /TestR2Sdf/x 11 | add wave -noupdate -radix decimal -childformat {{/TestR2Sdf/out.re -radix decimal} {/TestR2Sdf/out.im -radix decimal}} -radixshowbase 0 -expand -subitemconfig {/TestR2Sdf/out.re {-height 15 -radix decimal -radixshowbase 0} /TestR2Sdf/out.im {-height 15 -radix decimal -radixshowbase 0}} /TestR2Sdf/out 12 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x1[1]} 13 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z1[1]} 14 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x0[1]} 15 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z0[1]} 16 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/waddr} 17 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/w} 18 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/mulin} 19 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/mulout} 20 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x1[0]} 21 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z1[0]} 22 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x0[0]} 23 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z0[0]} 24 | TreeUpdate [SetDefaultTree] 25 | WaveRestoreCursors {{Cursor 1} {929054 ps} 0} 26 | quietly wave cursor active 1 27 | configure wave -namecolwidth 150 28 | configure wave -valuecolwidth 100 29 | configure wave -justifyvalue left 30 | configure wave -signalnamewidth 1 31 | configure wave -snapdistance 10 32 | configure wave -datasetprefix 0 33 | configure wave -rowmargin 4 34 | configure wave -childrowmargin 2 35 | configure wave -gridoffset 7500 36 | configure wave -gridperiod 1 37 | configure wave -griddelta 40 38 | configure wave -timeline 0 39 | configure wave -timelineunits ns 40 | update 41 | WaveRestoreZoom {887099 ps} {1005943 ps} 42 | -------------------------------------------------------------------------------- /chapter7/sim_r2sdf_4s_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestR2Sdf/clk 4 | add wave -noupdate /TestR2Sdf/rst 5 | add wave -noupdate /TestR2Sdf/sc 6 | add wave -noupdate /TestR2Sdf/inv 7 | add wave -noupdate -radix unsigned -childformat {{{/TestR2Sdf/cnt[3]} -radix unsigned} {{/TestR2Sdf/cnt[2]} -radix unsigned} {{/TestR2Sdf/cnt[1]} -radix unsigned} {{/TestR2Sdf/cnt[0]} -radix unsigned}} -radixshowbase 0 -subitemconfig {{/TestR2Sdf/cnt[3]} {-height 15 -radix unsigned -radixshowbase 0} {/TestR2Sdf/cnt[2]} {-height 15 -radix unsigned -radixshowbase 0} {/TestR2Sdf/cnt[1]} {-height 15 -radix unsigned -radixshowbase 0} {/TestR2Sdf/cnt[0]} {-height 15 -radix unsigned -radixshowbase 0}} /TestR2Sdf/cnt 8 | add wave -noupdate /TestR2Sdf/isync 9 | add wave -noupdate -radix decimal -radixshowbase 0 /TestR2Sdf/x 10 | add wave -noupdate /TestR2Sdf/osync 11 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestR2Sdf/dataIdx 12 | add wave -noupdate -radix decimal -childformat {{/TestR2Sdf/out.re -radix decimal} {/TestR2Sdf/out.im -radix decimal}} -radixshowbase 0 -expand -subitemconfig {/TestR2Sdf/out.re {-height 15 -radix decimal -radixshowbase 0} /TestR2Sdf/out.im {-height 15 -radix decimal -radixshowbase 0}} /TestR2Sdf/out 13 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x1[1]} 14 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z1[1]} 15 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x0[1]} 16 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z0[1]} 17 | add wave -noupdate {/TestR2Sdf/theR2Sdf/mulStg[0]/cnt_dly} 18 | add wave -noupdate -radix decimal -childformat {{{/TestR2Sdf/theR2Sdf/mulStg[0]/waddr[0]} -radix decimal}} -radixshowbase 0 -subitemconfig {{/TestR2Sdf/theR2Sdf/mulStg[0]/waddr[0]} {-height 15 -radix decimal -radixshowbase 0}} {/TestR2Sdf/theR2Sdf/mulStg[0]/waddr} 19 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/w} 20 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/mulin} 21 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/mulStg[0]/mulout} 22 | add wave -noupdate {/TestR2Sdf/theR2Sdf/bfStg[0]/s_dly} 23 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x1[0]} 24 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z1[0]} 25 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_x0[0]} 26 | add wave -noupdate -radix decimal -radixshowbase 0 {/TestR2Sdf/theR2Sdf/bf2_z0[0]} 27 | TreeUpdate [SetDefaultTree] 28 | WaveRestoreCursors 29 | quietly wave cursor active 0 30 | configure wave -namecolwidth 97 31 | configure wave -valuecolwidth 71 32 | configure wave -justifyvalue left 33 | configure wave -signalnamewidth 1 34 | configure wave -snapdistance 10 35 | configure wave -datasetprefix 0 36 | configure wave -rowmargin 4 37 | configure wave -childrowmargin 2 38 | configure wave -gridoffset 7500 39 | configure wave -gridperiod 1 40 | configure wave -griddelta 40 41 | configure wave -timeline 0 42 | configure wave -timelineunits ns 43 | update 44 | WaveRestoreZoom {474200 ps} {586740 ps} 45 | -------------------------------------------------------------------------------- /chapter7/sim_slow_div_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestSlowDiv/clk 4 | add wave -noupdate /TestSlowDiv/rst 5 | add wave -noupdate -radix unsigned /TestSlowDiv/ddend 6 | add wave -noupdate -radix unsigned /TestSlowDiv/dsor 7 | add wave -noupdate /TestSlowDiv/start 8 | add wave -noupdate -radix unsigned -childformat {{{/TestSlowDiv/quot[7]} -radix unsigned} {{/TestSlowDiv/quot[6]} -radix unsigned} {{/TestSlowDiv/quot[5]} -radix unsigned} {{/TestSlowDiv/quot[4]} -radix unsigned} {{/TestSlowDiv/quot[3]} -radix unsigned} {{/TestSlowDiv/quot[2]} -radix unsigned} {{/TestSlowDiv/quot[1]} -radix unsigned} {{/TestSlowDiv/quot[0]} -radix unsigned}} -subitemconfig {{/TestSlowDiv/quot[7]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[6]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[5]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[4]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[3]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[2]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[1]} {-height 15 -radix unsigned} {/TestSlowDiv/quot[0]} {-height 15 -radix unsigned}} /TestSlowDiv/quot 9 | add wave -noupdate -radix unsigned /TestSlowDiv/rem 10 | add wave -noupdate /TestSlowDiv/valid 11 | add wave -noupdate /TestSlowDiv/busy 12 | add wave -noupdate -divider slow_div 13 | add wave -noupdate -radix unsigned /TestSlowDiv/theSD/bit_cnt 14 | add wave -noupdate /TestSlowDiv/theSD/bit_co 15 | add wave -noupdate -radix unsigned /TestSlowDiv/theSD/ddend 16 | add wave -noupdate -radix unsigned /TestSlowDiv/theSD/dsor 17 | add wave -noupdate -radix unsigned /TestSlowDiv/theSD/quot 18 | add wave -noupdate -radix unsigned /TestSlowDiv/theSD/remainder 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {9898200 ps} 0} 21 | quietly wave cursor active 1 22 | configure wave -namecolwidth 95 23 | configure wave -valuecolwidth 39 24 | configure wave -justifyvalue left 25 | configure wave -signalnamewidth 1 26 | configure wave -snapdistance 10 27 | configure wave -datasetprefix 0 28 | configure wave -rowmargin 4 29 | configure wave -childrowmargin 2 30 | configure wave -gridoffset 7500 31 | configure wave -gridperiod 1 32 | configure wave -griddelta 40 33 | configure wave -timeline 0 34 | configure wave -timelineunits ns 35 | update 36 | WaveRestoreZoom {9878300 ps} {9899400 ps} 37 | -------------------------------------------------------------------------------- /chapter7/sim_slow_mul_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestSlowMult/clk 4 | add wave -noupdate /TestSlowMult/rst 5 | add wave -noupdate -radix unsigned /TestSlowMult/mcand 6 | add wave -noupdate -radix unsigned /TestSlowMult/mer 7 | add wave -noupdate /TestSlowMult/start 8 | add wave -noupdate -radix unsigned /TestSlowMult/prod 9 | add wave -noupdate /TestSlowMult/valid 10 | add wave -noupdate /TestSlowMult/busy 11 | add wave -noupdate -divider slow_mult 12 | add wave -noupdate /TestSlowMult/theSM/bit_cnt 13 | add wave -noupdate /TestSlowMult/theSM/bit_co 14 | add wave -noupdate -radix unsigned /TestSlowMult/theSM/mcand 15 | add wave -noupdate -radix unsigned -childformat {{{/TestSlowMult/theSM/mer[7]} -radix unsigned} {{/TestSlowMult/theSM/mer[6]} -radix unsigned} {{/TestSlowMult/theSM/mer[5]} -radix unsigned} {{/TestSlowMult/theSM/mer[4]} -radix unsigned} {{/TestSlowMult/theSM/mer[3]} -radix unsigned} {{/TestSlowMult/theSM/mer[2]} -radix unsigned} {{/TestSlowMult/theSM/mer[1]} -radix unsigned} {{/TestSlowMult/theSM/mer[0]} -radix unsigned}} -subitemconfig {{/TestSlowMult/theSM/mer[7]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[6]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[5]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[4]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[3]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[2]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[1]} {-height 15 -radix unsigned} {/TestSlowMult/theSM/mer[0]} {-height 15 -radix unsigned}} /TestSlowMult/theSM/mer 16 | add wave -noupdate -radix unsigned /TestSlowMult/theSM/sum 17 | TreeUpdate [SetDefaultTree] 18 | WaveRestoreCursors {{Cursor 1} {10650100 ps} 0} 19 | quietly wave cursor active 1 20 | configure wave -namecolwidth 97 21 | configure wave -valuecolwidth 64 22 | configure wave -justifyvalue left 23 | configure wave -signalnamewidth 1 24 | configure wave -snapdistance 10 25 | configure wave -datasetprefix 0 26 | configure wave -rowmargin 4 27 | configure wave -childrowmargin 2 28 | configure wave -gridoffset 7500 29 | configure wave -gridperiod 1 30 | configure wave -griddelta 40 31 | configure wave -timeline 0 32 | configure wave -timelineunits ns 33 | update 34 | WaveRestoreZoom {10648300 ps} {10669200 ps} 35 | -------------------------------------------------------------------------------- /chapter7/sim_slow_sqrt_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestSlowSqrt/clk 4 | add wave -noupdate /TestSlowSqrt/rst 5 | add wave -noupdate -radix unsigned -childformat {{{/TestSlowSqrt/sq[15]} -radix unsigned} {{/TestSlowSqrt/sq[14]} -radix unsigned} {{/TestSlowSqrt/sq[13]} -radix unsigned} {{/TestSlowSqrt/sq[12]} -radix unsigned} {{/TestSlowSqrt/sq[11]} -radix unsigned} {{/TestSlowSqrt/sq[10]} -radix unsigned} {{/TestSlowSqrt/sq[9]} -radix unsigned} {{/TestSlowSqrt/sq[8]} -radix unsigned} {{/TestSlowSqrt/sq[7]} -radix unsigned} {{/TestSlowSqrt/sq[6]} -radix unsigned} {{/TestSlowSqrt/sq[5]} -radix unsigned} {{/TestSlowSqrt/sq[4]} -radix unsigned} {{/TestSlowSqrt/sq[3]} -radix unsigned} {{/TestSlowSqrt/sq[2]} -radix unsigned} {{/TestSlowSqrt/sq[1]} -radix unsigned} {{/TestSlowSqrt/sq[0]} -radix unsigned}} -subitemconfig {{/TestSlowSqrt/sq[15]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[14]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[13]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[12]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[11]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[10]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[9]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[8]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[7]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[6]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[5]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[4]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[3]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[2]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[1]} {-height 15 -radix unsigned} {/TestSlowSqrt/sq[0]} {-height 15 -radix unsigned}} /TestSlowSqrt/sq 6 | add wave -noupdate /TestSlowSqrt/start 7 | add wave -noupdate -radix unsigned /TestSlowSqrt/rt 8 | add wave -noupdate -radix unsigned /TestSlowSqrt/rem 9 | add wave -noupdate /TestSlowSqrt/valid 10 | add wave -noupdate -divider {slow sqrt} 11 | add wave -noupdate -radix unsigned /TestSlowSqrt/theSqrt/num 12 | add wave -noupdate -radix unsigned /TestSlowSqrt/theSqrt/sub 13 | add wave -noupdate -radix unsigned /TestSlowSqrt/theSqrt/bm 14 | add wave -noupdate -radix unsigned /TestSlowSqrt/theSqrt/res 15 | add wave -noupdate -radix unsigned /TestSlowSqrt/crt 16 | add wave -noupdate -radix unsigned /TestSlowSqrt/crem 17 | TreeUpdate [SetDefaultTree] 18 | WaveRestoreCursors {{Cursor 1} {5047100 ps} 0} 19 | quietly wave cursor active 1 20 | configure wave -namecolwidth 71 21 | configure wave -valuecolwidth 39 22 | configure wave -justifyvalue left 23 | configure wave -signalnamewidth 1 24 | configure wave -snapdistance 10 25 | configure wave -datasetprefix 0 26 | configure wave -rowmargin 4 27 | configure wave -childrowmargin 2 28 | configure wave -gridoffset 7500 29 | configure wave -gridperiod 1 30 | configure wave -griddelta 40 31 | configure wave -timeline 0 32 | configure wave -timelineunits ns 33 | update 34 | WaveRestoreZoom {5030300 ps} {5052300 ps} 35 | -------------------------------------------------------------------------------- /chapter7/sim_sqrt_str_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /test_sqrt_str/seed0 4 | add wave -noupdate /test_sqrt_str/seed1 5 | add wave -noupdate /test_sqrt_str/seed2 6 | add wave -noupdate /test_sqrt_str/clk 7 | add wave -noupdate /test_sqrt_str/rst 8 | add wave -noupdate -radix unsigned /test_sqrt_str/num 9 | add wave -noupdate /test_sqrt_str/us_last 10 | add wave -noupdate /test_sqrt_str/us_ready 11 | add wave -noupdate /test_sqrt_str/us_valid 12 | add wave -noupdate -radix unsigned /test_sqrt_str/sqrt 13 | add wave -noupdate -radix unsigned /test_sqrt_str/rem 14 | add wave -noupdate /test_sqrt_str/ds_last 15 | add wave -noupdate /test_sqrt_str/ds_ready 16 | add wave -noupdate /test_sqrt_str/ds_valid 17 | TreeUpdate [SetDefaultTree] 18 | WaveRestoreCursors {{Cursor 1} {96476772 ps} 0} 19 | quietly wave cursor active 1 20 | configure wave -namecolwidth 150 21 | configure wave -valuecolwidth 100 22 | configure wave -justifyvalue left 23 | configure wave -signalnamewidth 1 24 | configure wave -snapdistance 10 25 | configure wave -datasetprefix 0 26 | configure wave -rowmargin 4 27 | configure wave -childrowmargin 2 28 | configure wave -gridoffset 0 29 | configure wave -gridperiod 62500000 30 | configure wave -griddelta 10 31 | configure wave -timeline 0 32 | configure wave -timelineunits us 33 | update 34 | WaveRestoreZoom {96326090 ps} {96651381 ps} 35 | -------------------------------------------------------------------------------- /chapter7/slow_sqrt.sv: -------------------------------------------------------------------------------- 1 | `ifndef __SLOW_SQRT_SV__ 2 | `define __SLOW_SQRT_SV__ 3 | 4 | `include "../common.sv" 5 | 6 | `timescale 1ns/100ps 7 | `default_nettype none 8 | 9 | module TestSlowSqrt; 10 | import SimSrcGen::*; 11 | logic clk, rst; 12 | initial GenClk(clk, 8, 10); 13 | initial GenRst(clk, rst, 2, 2); 14 | logic [15:0] sq = '0; 15 | logic [7:0] rt, rem; 16 | logic start = '0, valid; 17 | SlowSqrt #(8) theSqrt(clk, rst, sq, start, rt, rem, valid); 18 | initial begin 19 | repeat(10) @(posedge clk); 20 | repeat(1000) begin 21 | @(posedge clk) begin 22 | sq <= $random(); 23 | start <= '1; 24 | end 25 | @(posedge clk) start <= '0; 26 | do @(posedge clk); 27 | while(~valid); 28 | end 29 | @(posedge clk) $stop(); 30 | end 31 | logic [7:0] crt, crem; 32 | always_ff@(posedge clk) begin 33 | if(valid) begin 34 | crt = $floor($sqrt(sq)); 35 | crem = sq - 16'(crt) * crt; 36 | if(crt != rt || crem != rem) begin 37 | $display("err: sqrt(%d) -> %d ... %d", sq, rt, rem); 38 | $display("\tshould be %d ... %d", crt, crem); 39 | end 40 | end 41 | end 42 | endmodule 43 | 44 | module SlowSqrt #( parameter RTW = 8 )( // root witdh 45 | input wire clk, rst, 46 | input wire [RTW * 2 - 1 : 0] in, 47 | input wire start, 48 | output logic [RTW - 1 : 0] sqrt, 49 | output logic [RTW - 1 : 0] rem, 50 | output logic valid 51 | ); 52 | localparam DW = RTW * 2; 53 | logic [DW - 1 : 0] res; 54 | logic [DW - 1 : 0] bm; // the \Delta r 55 | logic [DW - 1 : 0] num; 56 | wire [DW - 1 : 0] sub = res + bm; // the res' 57 | wire [DW -1 : 0] bmm = {2'b01, {(DW - 2){1'b0}}}; // highest segment 58 | always_ff@(posedge clk) begin 59 | if(rst) valid <= 1'b0; 60 | else valid <= (bm == 1'd1); 61 | end 62 | always_ff@(posedge clk) begin 63 | if(rst) bm <= '0; 64 | else if(bm > '0) bm <= bm >> 2; 65 | else if(start) bm <= bmm >> 2; 66 | end 67 | always_ff@(posedge clk) begin 68 | if(rst) begin res <= 1'b0; num <= 1'b0; end 69 | else if(bm > '0) begin 70 | if(num >= sub) begin 71 | num <= num - sub; 72 | res <= (res >> 1) + bm; 73 | end 74 | else res <= (res >> 1); 75 | end 76 | else if(start) begin 77 | if(in >= bmm) begin 78 | num <= in - bmm; 79 | res <= bmm; 80 | end 81 | else begin 82 | num <= in; 83 | res <= 0; 84 | end 85 | end 86 | end 87 | always_ff@(posedge clk) begin 88 | if(rst) begin sqrt <= '0; rem <= '0; end 89 | else if(bm == 1'd1) begin 90 | if(num >= sub) begin 91 | sqrt <= {1'b0, res[DW - 1 : 1]} + bm; 92 | rem <= num - sub; 93 | end 94 | else begin 95 | sqrt <= {1'b0, res[DW - 1 : 1]}; 96 | rem <= num; 97 | end 98 | end 99 | end 100 | endmodule 101 | 102 | `endif 103 | -------------------------------------------------------------------------------- /chapter7/sqrt_str.sv: -------------------------------------------------------------------------------- 1 | `ifndef __STR_SQRT_SV__ 2 | `define __STR_SQRT_SV__ 3 | 4 | `timescale 1ns/1ps 5 | `default_nettype none 6 | 7 | module str_sqrt_stg #( 8 | parameter integer RBP = 0, // root working bit pos 9 | parameter integer RDW = 4 // root width 10 | )( 11 | input wire clk, rst, 12 | // rem & root input from prev. stg. 13 | input wire [2*RDW-1:0] remi, 14 | input wire [ RDW-1:0] rooti, 15 | input wire ilast, ivalid, 16 | output wire iready, 17 | // rem & root output to next. stg. 18 | output logic [2*RDW-1:0] remo, 19 | output logic [ RDW-1:0] rooto, 20 | output logic olast, ovalid, 21 | input wire oready 22 | ); 23 | wire ish = ivalid & iready; 24 | wire osh = ovalid & oready; 25 | assign iready = osh | ~ovalid; 26 | always_ff @(posedge clk) begin : proc_ovalid 27 | if(rst) ovalid <= 1'b0; 28 | else if(ish) ovalid <= 1'b1; 29 | else if(oready) ovalid <= 1'b0; 30 | end 31 | generate if(RBP >= RDW) 32 | $fatal("Stage exceed limit."); 33 | endgenerate 34 | // delta root 35 | wire [RDW-1:0] dr = (RDW)'(1) << RBP; 36 | // sub = enough ? 2 * rooti * dr + dr^2 37 | wire [2*RDW-1:0] sub = (rooti << (RBP+1)) | ((2*RDW)'(1) << (2*RBP)); 38 | wire enough = remi >= sub; 39 | always_ff @(posedge clk) begin : proc_output 40 | if(rst) begin 41 | remo <= '0; 42 | rooto <= '0; 43 | olast <= 1'b0; 44 | end 45 | else if(ish) begin 46 | olast <= ilast; 47 | if(enough) begin 48 | remo <= remi - sub; 49 | rooto <= rooti | dr; 50 | end 51 | else begin 52 | remo <= remi; 53 | rooto <= rooti; 54 | end 55 | end 56 | end 57 | endmodule : str_sqrt_stg 58 | 59 | module str_sqrt #( 60 | parameter integer RDW = 4 61 | )( 62 | input wire clk, rst, 63 | input wire [2*RDW-1:0] num, 64 | input wire ilast, ivalid, 65 | output wire iready, 66 | output wire [ RDW-1:0] sqrt, 67 | output wire [2*RDW-1:0] rem, 68 | output wire olast, ovalid, 69 | input wire oready 70 | ); 71 | wire [2*RDW-1:0] rems[RDW+1]; 72 | wire [ RDW-1:0] root[RDW+1]; 73 | wire [ RDW :0] last, valid, ready; 74 | assign rems[RDW] = num; 75 | assign root[RDW] = '0; 76 | assign last[RDW] = ilast; 77 | assign valid[RDW] = ivalid; 78 | assign iready = ready[RDW]; 79 | generate 80 | for(genvar i = RDW-1; i >=0; i--) begin :stages 81 | str_sqrt_stg #(i, RDW) sqrt_stg(clk, rst, 82 | rems[i+1], root[i+1], last[i+1], valid[i+1], ready[i+1], 83 | rems[i], root[i], last[i], valid[i], ready[i] 84 | ); 85 | end 86 | endgenerate 87 | assign sqrt = root [0]; 88 | assign rem = rems [0]; 89 | assign olast = last [0]; 90 | assign ovalid = valid[0]; 91 | assign ready[0] = oready; 92 | 93 | endmodule 94 | 95 | `default_nettype wire 96 | `endif 97 | -------------------------------------------------------------------------------- /chapter7/test_fp_lets.sv: -------------------------------------------------------------------------------- 1 | `ifndef __TEST_FP_LETS_SV__ 2 | `define __TEST_FP_LETS_SV__ 3 | 4 | `include "../common.sv" 5 | `include "./fixedpoint_pkg.sv" 6 | 7 | `timescale 1ns/100ps 8 | `default_nettype none 9 | 10 | module TestFpLets; 11 | import SimSrcGen::*; 12 | import Fixedpoint::*; 13 | logic clk, rst; 14 | initial GenClk(clk, 8, 10); 15 | initial GenRst(clk, rst, 2, 2); 16 | logic signed [15:0] q1_15a, q1_15b; 17 | logic signed [31:0] q9_23; 18 | int seed = 67349; 19 | always_ff@(posedge clk) begin 20 | q1_15a = $dist_uniform(seed, -32767, 32767); 21 | q1_15b = $dist_uniform(seed, -32767, 32767); 22 | q9_23 = $dist_uniform(seed, -8388607, 8388607); 23 | end 24 | `DEF_FP_ADD(add_1q15_1q15, 1, 15, 1, 15, 15); 25 | `DEF_FP_ADD(add_1q15_9q23_q15, 1, 15, 9, 23, 15); 26 | `DEF_FP_ADD(add_1q15_9q23_q23, 1, 15, 9, 23, 23); 27 | `DEF_FP_MUL(mul_1q15_1q15, 1, 15, 1, 15, 15); 28 | `DEF_FP_MUL(mul_1q15_1q15_q30, 1, 15, 1, 15, 30); 29 | `DEF_FP_MUL(mul_1q15_9q23_q23, 1, 15, 9, 23, 23); 30 | int s0, s1, s2, p0, p1, p2; 31 | assign s0 = add_1q15_1q15 (q1_15a, q1_15b); 32 | assign s1 = add_1q15_9q23_q15(q1_15a, q9_23); 33 | assign s2 = add_1q15_9q23_q23(q1_15a, q9_23); 34 | assign p0 = mul_1q15_1q15 (q1_15a, q1_15b); 35 | assign p1 = mul_1q15_1q15_q30(q1_15a, q1_15b); 36 | assign p2 = mul_1q15_9q23_q23(q1_15a, q9_23); 37 | real q1_15a_r, q1_15b_r, q9_23r; 38 | real s0r, s1r, s2r, p0r, p1r, p2r; 39 | real s0rc, s1rc, s2rc, p0rc, p1rc, p2rc; 40 | let abs(x) = x >= 0? x : -x; 41 | always@* begin 42 | q1_15a_r = real'(q1_15a) / (2.0**15); 43 | q1_15b_r = real'(q1_15b) / (2.0**15); 44 | q9_23r = real'(q9_23) / (2.0**23); 45 | s0r = real'(s0) / (2.0**15); 46 | s1r = real'(s1) / (2.0**15); 47 | s2r = real'(s2) / (2.0**23); 48 | p0r = real'(p0) / (2.0**15); 49 | p1r = real'(p1) / (2.0**30); 50 | p2r = real'(p2) / (2.0**23); 51 | s0rc = q1_15a_r + q1_15b_r; 52 | s1rc = q1_15a_r + q9_23r; 53 | s2rc = q1_15a_r + q9_23r; 54 | p0rc = q1_15a_r * q1_15b_r; 55 | p1rc = q1_15a_r * q1_15b_r; 56 | p2rc = q1_15a_r * q9_23r; 57 | #1 begin 58 | if(abs(s0r - s0rc) > 0.5**15) $display("s0r: %g - s0rc: %g", s0r, s0rc); 59 | if(abs(s1r - s1rc) > 0.5**15) $display("s1r: %g - s1rc: %g", s1r, s1rc); 60 | if(abs(s2r - s2rc) > 0.5**23) $display("s2r: %g - s2rc: %g", s2r, s2rc); 61 | if(abs(p0r - p0rc) > 0.5**15) $display("p0r: %g - p0rc: %g", p0r, p0rc); 62 | if(abs(p1r - p1rc) > 0.5**30) $display("p1r: %g - p1rc: %g", p1r, p1rc); 63 | if(abs(p2r - p2rc) > 0.5**23) $display("p2r: %g - p2rc: %g", p2r, p2rc); 64 | end 65 | end 66 | endmodule 67 | 68 | `endif 69 | -------------------------------------------------------------------------------- /chapter7/test_fp_pkg.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter7/test_pid.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/test_pid.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/test_pid.sv 2 | Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCounter 7 | -- Importing package SimSrcGen 8 | -- Compiling module TestCntSecMinHr 9 | -- Compiling module CntSecMinHr 10 | -- Compiling module Counter 11 | -- Compiling module CounterMax 12 | -- Compiling module TestDDS 13 | -- Compiling module DDS 14 | -- Compiling module OrthDDS 15 | -- Compiling module TestIir 16 | -- Compiling module IIR 17 | -- Compiling module IIR2nd 18 | -- Importing package Fixedpoint 19 | -- Compiling module TestPwm 20 | -- Compiling module Pwm 21 | -- Compiling module PwmSigned 22 | -- Compiling module PwmDiffTime 23 | -- Compiling module PwmDiffFixedLow 24 | -- Compiling module RisingDelay 25 | -- Compiling module TestPID 26 | -- Compiling module SimpleInverterCtrl 27 | 28 | Top level modules: 29 | TestCounter 30 | TestCntSecMinHr 31 | CounterMax 32 | TestDDS 33 | OrthDDS 34 | TestIir 35 | TestPwm 36 | TestPID 37 | 38 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter7/pid.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/pid.sv 39 | Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 40 | -- Compiling package SimSrcGen 41 | -- Compiling package CombFunctions 42 | -- Compiling package Fixedpoint 43 | -- Compiling module Pid 44 | -- Importing package Fixedpoint 45 | 46 | Top level modules: 47 | Pid 48 | 49 | } {} {}} 50 | -------------------------------------------------------------------------------- /chapter7/test_pid.sv: -------------------------------------------------------------------------------- 1 | `include "../common.sv" 2 | `include "../chapter4/counter.sv" 3 | `include "./iir.sv" 4 | `include "./dds.sv" 5 | `include "../chapter4/pwm.sv" 6 | 7 | `timescale 1ns/100ps 8 | `default_nettype none 9 | 10 | module TestPID; 11 | import SimSrcGen::*; 12 | logic clk, rst; 13 | initial GenClk(clk, 8000, 10000); 14 | initial GenRst(clk, rst, 2, 2); 15 | logic signed [11:0] des_amp = 10*2.0**7; //10V (Q5.7) 16 | logic signed [11:0] vfb; // Q5.7 17 | logic pwm; 18 | SimpleInverterCtrl inverterCtrl( 19 | clk, rst, 24'sd8389, 24'sd0, des_amp, pwm, vfb); 20 | logic signed [11:0] vpwr = 12*2.0**7; //bridge supply 12V(Q5.7) 21 | wire signed [11:0] brg_out = pwm ? (vpwr) : (-vpwr); 22 | logic signed [39:0] lc_out; // Q5.35 23 | wire signed [39:0] lc_in = brg_out <<< 28; //Q5.7 -> Q5.35 24 | IIR #(40, 32, 1, '{ 7.59959214012339e-09 }, // g 25 | '{'{ 0, 1, 0.999_946_334_773 }}, // num 0~2 26 | '{'{ -1.999_838_997_761, 0.999_839_012_960 }}) // den 1~2 27 | theLCFilter ( clk, rst, 1'b1, lc_in, lc_out ); 28 | real inn_volt; 29 | assign inn_volt = lc_out / 2.0**35; 30 | real load_res = 10.0, inn_res = 0.5; 31 | real out_volt; 32 | assign out_volt = inn_volt * load_res / (load_res + inn_res); 33 | assign vfb = out_volt * 2.0**7; 34 | 35 | initial begin 36 | repeat(5_000_00) @(posedge clk); 37 | load_res = 5.0; // load res from 10Ohm to 5.0Ohm 38 | repeat(10_000_00) @(posedge clk); 39 | des_amp = 5 * 2.0**7; // desire amp from 10V to 5V 40 | repeat(10_000_00) @(posedge clk); 41 | vpwr = 10*2.0**7; // bridge supply from 12V to 10V 42 | repeat(20_000_00) @(posedge clk); 43 | $stop(); 44 | end 45 | endmodule 46 | module SimpleInverterCtrl( 47 | input wire clk, rst, // 100MHz 48 | input wire signed [23:0] freq, // fout = freq * 100k / 2^24 49 | input wire signed [23:0] phase, // phout = phase * PI / 2^23 50 | input wire signed [11:0] amp, // desire amp(Q5.7) 51 | output logic spwm, // spwm for half bridge 52 | input wire signed [11:0] volt_fb // Q5.7 feedback voltage 53 | ); 54 | logic en_100k; 55 | logic signed [11:0] sine; //Q1.10 56 | DDS #( 24, 12, 14 ) theDDS( 57 | clk, rst, en_100k, freq, phase, sine ); 58 | logic signed [11:0] sin_volt; //Q5.7 59 | always_ff@(posedge clk) begin 60 | if(rst) sin_volt <= '0; 61 | else if(en_100k) 62 | sin_volt = (24'(sine) * amp) >>> 11; //Q1.11*Q5.7->Q5.7 63 | end 64 | wire signed [11:0] v_err = sin_volt - volt_fb; //Q5.7 65 | wire signed [47:0] pid_in = v_err <<< 17; //Q5.7->Q24.24 66 | logic signed [47:0] pid_out; 67 | Pid2 #( .W(36), .FW(24), .P(39), .I(2.35e5/100e3), .D(1.1e-3), 68 | .N(1.64e5), .TS(1/100e3), .LIMIT(1000) ) 69 | thePid ( clk, rst, en_100k, pid_in, pid_out ); 70 | wire signed [23:0] pid_out_int = pid_out[47:24]; 71 | wire signed [9:0] duty = (pid_out_int > 10'sd500)? 10'sd500 : 72 | (pid_out_int < -10'sd500)? -10'sd500 : 73 | pid_out_int; 74 | PwmSigned #( .M(1000) ) thePwm( 75 | clk, rst, duty, spwm, en_100k); 76 | endmodule 77 | -------------------------------------------------------------------------------- /chapter7/test_pid_2.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/test_pid.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/test_pid.sv 2 | Model Technology ModelSim SE-64 vlog 10.6e Compiler 2018.06 Jun 23 2018 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCounter 7 | -- Importing package SimSrcGen 8 | -- Compiling module TestCntSecMinHr 9 | -- Compiling module CntSecMinHr 10 | -- Compiling module Counter 11 | -- Compiling module CounterMax 12 | -- Compiling module TestDDS 13 | -- Compiling module DDS 14 | -- Compiling module OrthDDS 15 | -- Compiling module TestIir 16 | -- Compiling module IIR 17 | -- Compiling module IIR2nd 18 | -- Importing package Fixedpoint 19 | -- Compiling module TestPwm 20 | -- Compiling module Pwm 21 | -- Compiling module PwmSigned 22 | -- Compiling module PwmDiffTime 23 | -- Compiling module PwmDiffFixedLow 24 | -- Compiling module RisingDelay 25 | -- Compiling module TestPID 26 | -- Compiling module SimpleInverterCtrl 27 | 28 | Top level modules: 29 | TestCounter 30 | TestCntSecMinHr 31 | CounterMax 32 | TestDDS 33 | OrthDDS 34 | TestIir 35 | TestPwm 36 | TestPID 37 | 38 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter7/pid.sv {1 {vlog -work work -vopt -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/pid.sv 39 | Model Technology ModelSim SE-64 vlog 10.6e Compiler 2018.06 Jun 23 2018 40 | -- Compiling package SimSrcGen 41 | -- Compiling package CombFunctions 42 | -- Compiling package Fixedpoint 43 | -- Compiling module Pid 44 | -- Importing package Fixedpoint 45 | 46 | Top level modules: 47 | Pid 48 | 49 | } {} {}} 50 | -------------------------------------------------------------------------------- /chapter7/test_sqrt_str.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter7/test_str_usdiv.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter7/test_str_usdiv.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /test_str_usdiv/DW 4 | add wave -noupdate /test_str_usdiv/seed0 5 | add wave -noupdate /test_str_usdiv/seed1 6 | add wave -noupdate /test_str_usdiv/seed2 7 | add wave -noupdate /test_str_usdiv/clk 8 | add wave -noupdate /test_str_usdiv/rst 9 | add wave -noupdate -radix unsigned /test_str_usdiv/cnt 10 | add wave -noupdate -radix unsigned /test_str_usdiv/num 11 | add wave -noupdate -radix unsigned /test_str_usdiv/den 12 | add wave -noupdate /test_str_usdiv/us_last 13 | add wave -noupdate /test_str_usdiv/us_ready 14 | add wave -noupdate /test_str_usdiv/us_valid 15 | add wave -noupdate /test_str_usdiv/uhs 16 | add wave -noupdate -radix unsigned /test_str_usdiv/n 17 | add wave -noupdate -radix unsigned /test_str_usdiv/ref_num 18 | add wave -noupdate -radix unsigned /test_str_usdiv/ref_den 19 | add wave -noupdate -radix unsigned /test_str_usdiv/quo 20 | add wave -noupdate -radix unsigned /test_str_usdiv/rem 21 | add wave -noupdate /test_str_usdiv/ds_last 22 | add wave -noupdate /test_str_usdiv/ds_ready 23 | add wave -noupdate /test_str_usdiv/ds_valid 24 | add wave -noupdate /test_str_usdiv/dhs 25 | TreeUpdate [SetDefaultTree] 26 | WaveRestoreCursors {{Cursor 1} {1232215000 ps} 0} {{Cursor 2} {35550506996 ps} 0} 27 | quietly wave cursor active 1 28 | configure wave -namecolwidth 114 29 | configure wave -valuecolwidth 85 30 | configure wave -justifyvalue left 31 | configure wave -signalnamewidth 1 32 | configure wave -snapdistance 10 33 | configure wave -datasetprefix 0 34 | configure wave -rowmargin 4 35 | configure wave -childrowmargin 2 36 | configure wave -gridoffset 0 37 | configure wave -gridperiod 62500000 38 | configure wave -griddelta 10 39 | configure wave -timeline 0 40 | configure wave -timelineunits us 41 | update 42 | WaveRestoreZoom {1232198054 ps} {1232435665 ps} 43 | -------------------------------------------------------------------------------- /chapter7/up_down_sampling.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter7/cic.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/cic.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module Integrator 7 | -- Compiling module Comb 8 | -- Compiling module CicUpSampler 9 | -- Importing package Fixedpoint 10 | -- Compiling module CicDownSampler 11 | 12 | Top level modules: 13 | CicUpSampler 14 | CicDownSampler 15 | 16 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter7/intp_deci.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/intp_deci.sv 17 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 18 | -- Compiling module InterpDeci 19 | 20 | Top level modules: 21 | InterpDeci 22 | 23 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter7/sr441to480.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter7/sr441to480.sv 24 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 25 | -- Compiling package SimSrcGen 26 | -- Compiling package CombFunctions 27 | -- Compiling package Fixedpoint 28 | -- Compiling module TestCounter 29 | -- Importing package SimSrcGen 30 | -- Compiling module TestCntSecMinHr 31 | -- Compiling module CntSecMinHr 32 | -- Compiling module Counter 33 | -- Compiling module CounterMax 34 | -- Compiling module TestDDS 35 | -- Compiling module DDS 36 | -- Compiling module TestFir 37 | -- Compiling module FIR 38 | -- Compiling module TestSr441to480 39 | -- Compiling module SmpRate441to480 40 | 41 | Top level modules: 42 | TestCounter 43 | TestCntSecMinHr 44 | CounterMax 45 | TestDDS 46 | TestFir 47 | TestSr441to480 48 | 49 | } {} {}} 50 | -------------------------------------------------------------------------------- /chapter7/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter7/vsim.wlf -------------------------------------------------------------------------------- /chapter8/crc.sv: -------------------------------------------------------------------------------- 1 | `ifndef __CRC_SV__ 2 | `define __CRC_SV__ 3 | `include "../chapter4/counter.sv" 4 | 5 | module CRCGenerator #( 6 | parameter N = 8, 7 | parameter [N-1 : 0] FB = 8'hcd,//FB = representation value >> 1 8 | parameter [N-1 : 0] INIT = 8'h00 9 | )( 10 | input wire clk, rst, en, in, 11 | // 8 bits will be ignored after dlast, padding dummy bits 12 | input wire calc_start, calc_last, 13 | output logic out 14 | ); 15 | logic crc, crc_end; // crc outputting, crc output finish 16 | Counter #(N) crcBitCnt(clk, rst, en & crc, , crc_end); 17 | always_ff@(posedge clk) begin 18 | if(rst) crc <= '0; 19 | else if(en & calc_last) crc <= '1; 20 | else if(crc_end | en&calc_start) crc <= '0; 21 | end 22 | logic [N-1:0] lfsr; 23 | always_ff@(posedge clk) begin 24 | if(rst) lfsr <= '0; 25 | else if(en & calc_start) 26 | lfsr <= (INIT[0]^in) ? (INIT>>1)^FB : (INIT>>1); 27 | else if(en) 28 | lfsr <= crc? lfsr >> 1 : 29 | (lfsr[0]^in) ? (lfsr>>1)^FB : (lfsr>>1); 30 | end 31 | assign out = crc ? lfsr[0] : in; 32 | endmodule 33 | 34 | module CRCChecker #( 35 | parameter N = 8, 36 | parameter [N-1 : 0] FB = 8'hcd, // FB = representation value>> 1 37 | parameter [N-1 : 0] INIT = 8'h00 38 | )( 39 | input wire clk, rst, en, in, 40 | input wire chk_start, chk_last, // chk_last including crc bits 41 | output logic err // should occur when chk_last and en high 42 | ); 43 | logic [N-1:0] lfsr, lfsr_nxt; 44 | always_ff@(posedge clk) begin 45 | if(rst) lfsr <= '0; 46 | else if(en & chk_start) 47 | lfsr <= (INIT[0] ^ in) ? (INIT>>1) ^ FB : (INIT>>1); 48 | else if(en) lfsr <= lfsr_nxt; 49 | end 50 | always_comb lfsr_nxt = (lfsr[0] ^ in) ? 51 | (lfsr >> 1) ^ FB : (lfsr >> 1); 52 | assign err = en & chk_last & (lfsr_nxt != N'(0)); 53 | endmodule 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /chapter8/lfsr.sv: -------------------------------------------------------------------------------- 1 | `ifndef __LFSR_SV__ 2 | `define __LFSR_SV__ 3 | 4 | module LFSR #( 5 | parameter N = 8, 6 | parameter [N-1:0] FB = 8'h8e, //FB = representation value >> 1 7 | parameter [N-1:0] INIT = 8'hff 8 | )( 9 | input wire clk, rst, en, 10 | output logic [N-1:0] out 11 | ); 12 | always_ff@(posedge clk) begin 13 | if(rst) out <= INIT; 14 | else if(en) out <= (out[0]) ? (out >> 1) ^ FB : (out >> 1); 15 | end 16 | endmodule 17 | 18 | `endif 19 | -------------------------------------------------------------------------------- /chapter8/man_coding.sv: -------------------------------------------------------------------------------- 1 | `ifndef __MAN_CODING_SV__ 2 | `define __MAN_CODING_SV__ 3 | 4 | module ManchesterEncoder #( parameter POL = 0 )( // POL = 0 or 1 5 | input wire clk, rst, en, en180, in, 6 | output logic man, dman, sck 7 | ); 8 | always_ff@(posedge clk) begin 9 | if(rst) sck <= 1'b0; 10 | else if(en) sck <= '1; 11 | else if(en180) sck <= '0; 12 | end 13 | always_ff@(posedge clk) begin 14 | if(rst) man <= '0; 15 | else if(en) man <= in ^ (POL? 1'b1 : 1'b0); 16 | else if(en180) man <= in ^ (POL? 1'b0 : 1'b1); 17 | end 18 | always_ff@(posedge clk) begin 19 | if(rst) dman <= '0; 20 | else if(en) dman <= ~dman; 21 | else if(en180) dman <= in ~^ dman; 22 | end 23 | endmodule 24 | 25 | module HystComp #( 26 | parameter W = 12, 27 | parameter real HYST = 0.1 28 | )( 29 | input wire clk, rst, en, 30 | input wire signed [W-1:0] in, 31 | output logic out 32 | ); 33 | wire signed [W-1:0] hyst = HYST * 2**(W-1); 34 | always_ff@(posedge clk) begin 35 | if(rst) out <= '0; 36 | else if(~out & in > hyst) out <= '1; 37 | else if(out & in < -hyst) out <= '0; 38 | end 39 | endmodule 40 | 41 | module DiffManDecoder #( parameter PERIOD = 10 )( // period of NRZ 42 | input wire clk, rst, en, in, 43 | output logic out, out_valid 44 | ); 45 | localparam integer P3Q = PERIOD * 3.0 / 4.0; 46 | logic [$clog2(PERIOD) : 0] pcnt; 47 | logic in_reg, in_edge; 48 | always_ff@(posedge clk) if(en) in_reg <= in; 49 | assign in_edge = in_reg ^ in; 50 | always_ff@(posedge clk) begin 51 | if(rst) pcnt <= '0; 52 | else if(en) begin 53 | if (pcnt >= P3Q && in_edge) pcnt <= '0; 54 | else pcnt <= pcnt + 1'b1; 55 | end 56 | end 57 | logic trans; 58 | always_ff@(posedge clk) begin 59 | if(rst) trans <= '0; 60 | else if(en & in_edge) begin 61 | if(pcnt >= P3Q) trans <= '0; 62 | else trans <= '1; 63 | end 64 | end 65 | always_ff@(posedge clk) begin 66 | if((en & in_edge) && pcnt >= P3Q) out <= ~trans; 67 | end 68 | always_ff@(posedge clk) 69 | out_valid <= ((en & in_edge) && pcnt >= P3Q); 70 | endmodule 71 | 72 | `endif 73 | -------------------------------------------------------------------------------- /chapter8/sim_am_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestAM/clk 4 | add wave -noupdate /TestAM/rst 5 | add wave -noupdate -format Analog-Step -height 40 -max 1951.0000000000005 -min -1971.0 -radix decimal -radixshowbase 0 /TestAM/randsig 6 | add wave -noupdate -format Analog-Interpolated -height 40 -max 1030.0 -min -1230.0 -radix decimal -radixshowbase 0 /TestAM/bbsig 7 | add wave -noupdate -format Analog-Step -height 40 -max 1947.0 -min -1947.0 -radix decimal -radixshowbase 0 /TestAM/carrier 8 | add wave -noupdate -format Analog-Step -height 40 -max 2417.0 -min -2432.0 -radix decimal -radixshowbase 0 /TestAM/reg_am 9 | add wave -noupdate -format Analog-Step -height 40 -max 1257.0000000000002 -min -1204.0 -radix decimal -radixshowbase 0 /TestAM/reg_am_noi 10 | add wave -noupdate -format Analog-Step -height 40 -max 1200.0 -radix decimal -radixshowbase 0 /TestAM/envDemod/abs 11 | add wave -noupdate -format Analog-Interpolated -height 40 -max 400.0 -min -400.0 -radix decimal -radixshowbase 0 /TestAM/reg_am_demod 12 | add wave -noupdate -format Analog-Step -height 40 -max 1154.0 -min -1138.0 -radix decimal -childformat {{{/TestAM/dsb_am[12]} -radix decimal} {{/TestAM/dsb_am[11]} -radix decimal} {{/TestAM/dsb_am[10]} -radix decimal} {{/TestAM/dsb_am[9]} -radix decimal} {{/TestAM/dsb_am[8]} -radix decimal} {{/TestAM/dsb_am[7]} -radix decimal} {{/TestAM/dsb_am[6]} -radix decimal} {{/TestAM/dsb_am[5]} -radix decimal} {{/TestAM/dsb_am[4]} -radix decimal} {{/TestAM/dsb_am[3]} -radix decimal} {{/TestAM/dsb_am[2]} -radix decimal} {{/TestAM/dsb_am[1]} -radix decimal} {{/TestAM/dsb_am[0]} -radix decimal}} -radixshowbase 0 -subitemconfig {{/TestAM/dsb_am[12]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[11]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[10]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[9]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[8]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[7]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[6]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[5]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[4]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[3]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[2]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[1]} {-height 15 -radix decimal -radixshowbase 0} {/TestAM/dsb_am[0]} {-height 15 -radix decimal -radixshowbase 0}} /TestAM/dsb_am 13 | add wave -noupdate -format Analog-Step -height 40 -max 562.0 -min -640.0 -radix decimal -radixshowbase 0 /TestAM/ssb_am 14 | add wave -noupdate -format Analog-Step -height 40 -max 536.00000000000011 -min -651.0 -radix decimal -radixshowbase 0 /TestAM/ssb_am_noi 15 | add wave -noupdate -format Analog-Step -height 40 -max 489.00000000000011 -min -584.0 -radix decimal /TestAM/cohDemod/mix 16 | add wave -noupdate -format Analog-Interpolated -height 40 -max 448.0 -min -528.0 -radix decimal -radixshowbase 0 /TestAM/ssb_am_demod 17 | TreeUpdate [SetDefaultTree] 18 | WaveRestoreCursors 19 | quietly wave cursor active 0 20 | configure wave -namecolwidth 116 21 | configure wave -valuecolwidth 40 22 | configure wave -justifyvalue left 23 | configure wave -signalnamewidth 1 24 | configure wave -snapdistance 10 25 | configure wave -datasetprefix 0 26 | configure wave -rowmargin 4 27 | configure wave -childrowmargin 2 28 | configure wave -gridoffset 7500 29 | configure wave -gridperiod 1 30 | configure wave -griddelta 40 31 | configure wave -timeline 0 32 | configure wave -timelineunits ns 33 | update 34 | WaveRestoreZoom {0 ps} {14700 ns} 35 | -------------------------------------------------------------------------------- /chapter8/sim_fm_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestFM/clk 4 | add wave -noupdate /TestFM/rst 5 | add wave -noupdate -format Analog-Step -height 40 -max 1950.9999999999998 -min -1911.0 -radix decimal -radixshowbase 0 /TestFM/randsig 6 | add wave -noupdate -format Analog-Step -height 40 -max 1498.0 -min -1499.0 -radix decimal -radixshowbase 0 /TestFM/bbsig 7 | add wave -noupdate -format Analog-Step -height 40 -max 2047.0 -min -2047.0 -radix decimal -radixshowbase 0 /TestFM/wbfm 8 | add wave -noupdate -format Analog-Step -height 40 -max 2300.0 -min -2271.0 -radix decimal -radixshowbase 0 /TestFM/fmDemod/in_fil 9 | add wave -noupdate -format Analog-Step -height 40 -max 2300.0 -radix decimal -childformat {{{/TestFM/fmDemod/theEnvDet/abs[13]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[12]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[11]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[10]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[9]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[8]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[7]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[6]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[5]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[4]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[3]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[2]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[1]} -radix decimal} {{/TestFM/fmDemod/theEnvDet/abs[0]} -radix decimal}} -radixshowbase 0 -subitemconfig {{/TestFM/fmDemod/theEnvDet/abs[13]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[12]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[11]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[10]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[9]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[8]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[7]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[6]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[5]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[4]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[3]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[2]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[1]} {-height 15 -radix decimal -radixshowbase 0} {/TestFM/fmDemod/theEnvDet/abs[0]} {-height 15 -radix decimal -radixshowbase 0}} /TestFM/fmDemod/theEnvDet/abs 10 | add wave -noupdate -format Analog-Interpolated -height 40 -max 499.99999999999994 -min -600.0 -radix decimal -radixshowbase 0 /TestFM/wbfm_demod 11 | TreeUpdate [SetDefaultTree] 12 | WaveRestoreCursors 13 | quietly wave cursor active 0 14 | configure wave -namecolwidth 106 15 | configure wave -valuecolwidth 39 16 | configure wave -justifyvalue left 17 | configure wave -signalnamewidth 1 18 | configure wave -snapdistance 10 19 | configure wave -datasetprefix 0 20 | configure wave -rowmargin 4 21 | configure wave -childrowmargin 2 22 | configure wave -gridoffset 7500 23 | configure wave -gridperiod 1 24 | configure wave -griddelta 40 25 | configure wave -timeline 0 26 | configure wave -timelineunits ns 27 | update 28 | WaveRestoreZoom {0 ps} {10500 ns} 29 | -------------------------------------------------------------------------------- /chapter8/sim_qam_iqth_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestQAM16/clk 4 | add wave -noupdate /TestQAM16/rst 5 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestQAM16/lfsr_out 6 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/txi 7 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/txq 8 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/rxi 9 | add wave -noupdate -radix unsigned -childformat {{{/TestQAM16/rxq[1]} -radix unsigned} {{/TestQAM16/rxq[0]} -radix unsigned}} -radixshowbase 0 -subitemconfig {{/TestQAM16/rxq[1]} {-height 15 -radix unsigned -radixshowbase 0} {/TestQAM16/rxq[0]} {-height 15 -radix unsigned -radixshowbase 0}} /TestQAM16/rxq 10 | add wave -noupdate -radix hexadecimal -childformat {{{/TestQAM16/rxd[3]} -radix hexadecimal} {{/TestQAM16/rxd[2]} -radix hexadecimal} {{/TestQAM16/rxd[1]} -radix hexadecimal} {{/TestQAM16/rxd[0]} -radix hexadecimal}} -radixshowbase 0 -subitemconfig {{/TestQAM16/rxd[3]} {-height 15 -radix hexadecimal -radixshowbase 0} {/TestQAM16/rxd[2]} {-height 15 -radix hexadecimal -radixshowbase 0} {/TestQAM16/rxd[1]} {-height 15 -radix hexadecimal -radixshowbase 0} {/TestQAM16/rxd[0]} {-height 15 -radix hexadecimal -radixshowbase 0}} /TestQAM16/rxd 11 | add wave -noupdate -format Analog-Step -height 40 -min -2047.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/ilvl 12 | add wave -noupdate -format Analog-Step -height 40 -min -2047.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/qlvl 13 | add wave -noupdate -format Analog-Step -height 40 -max 1240.0000000000002 -min -1249.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/ilevel 14 | add wave -noupdate -format Analog-Step -height 40 -max 1376.0 -min -1326.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/qlevel 15 | add wave -noupdate -format Analog-Step -height 40 -max 833.99999999999989 -min -836.0 -radix decimal -radixshowbase 0 /TestQAM16/qam_if 16 | add wave -noupdate -format Analog-Step -height 40 -max 352.99999999999994 -min -306.0 -radix decimal -radixshowbase 0 /TestQAM16/ibb 17 | add wave -noupdate -format Analog-Step -height 40 -max 401.0 -min -402.0 -radix decimal -radixshowbase 0 /TestQAM16/qbb 18 | add wave -noupdate /TestQAM16/qamSJ/pedge 19 | add wave -noupdate /TestQAM16/qamSJ/sp_cnt 20 | add wave -noupdate /TestQAM16/qamSJ/sync 21 | add wave -noupdate -format Analog-Step -height 40 -max 343.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/iabs 22 | add wave -noupdate -format Analog-Step -height 40 -max 345.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/qabs 23 | add wave -noupdate -format Analog-Step -height 40 -max 343.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/i_peak 24 | add wave -noupdate -format Analog-Step -height 40 -max 345.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/q_peak 25 | add wave -noupdate -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/ith 26 | add wave -noupdate -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/qth 27 | TreeUpdate [SetDefaultTree] 28 | WaveRestoreCursors 29 | quietly wave cursor active 0 30 | configure wave -namecolwidth 106 31 | configure wave -valuecolwidth 42 32 | configure wave -justifyvalue left 33 | configure wave -signalnamewidth 1 34 | configure wave -snapdistance 10 35 | configure wave -datasetprefix 0 36 | configure wave -rowmargin 4 37 | configure wave -childrowmargin 2 38 | configure wave -gridoffset 7500 39 | configure wave -gridperiod 1 40 | configure wave -griddelta 40 41 | configure wave -timeline 0 42 | configure wave -timelineunits ns 43 | update 44 | WaveRestoreZoom {3673997 ps} {12205009 ps} 45 | -------------------------------------------------------------------------------- /chapter8/sim_qam_sj_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly virtual function -install /TestQAM16 -env /TestQAM16 { &{/TestQAM16/lfsr_out[3], /TestQAM16/lfsr_out[2], /TestQAM16/lfsr_out[1], /TestQAM16/lfsr_out[0] }} lfsr3210 3 | quietly WaveActivateNextPane {} 0 4 | add wave -noupdate /TestQAM16/clk 5 | add wave -noupdate /TestQAM16/rst 6 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestQAM16/lfsr_out 7 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/txi 8 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/txq 9 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/rxi 10 | add wave -noupdate -radix unsigned -childformat {{{/TestQAM16/rxq[1]} -radix unsigned} {{/TestQAM16/rxq[0]} -radix unsigned}} -radixshowbase 0 -subitemconfig {{/TestQAM16/rxq[1]} {-height 15 -radix unsigned -radixshowbase 0} {/TestQAM16/rxq[0]} {-height 15 -radix unsigned -radixshowbase 0}} /TestQAM16/rxq 11 | add wave -noupdate -radix hexadecimal -childformat {{{/TestQAM16/rxd[3]} -radix hexadecimal} {{/TestQAM16/rxd[2]} -radix hexadecimal} {{/TestQAM16/rxd[1]} -radix hexadecimal} {{/TestQAM16/rxd[0]} -radix hexadecimal}} -radixshowbase 0 -subitemconfig {{/TestQAM16/rxd[3]} {-height 15 -radix hexadecimal -radixshowbase 0} {/TestQAM16/rxd[2]} {-height 15 -radix hexadecimal -radixshowbase 0} {/TestQAM16/rxd[1]} {-height 15 -radix hexadecimal -radixshowbase 0} {/TestQAM16/rxd[0]} {-height 15 -radix hexadecimal -radixshowbase 0}} /TestQAM16/rxd 12 | add wave -noupdate -format Analog-Step -height 40 -max 1024.0 -min -1024.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/ilvl 13 | add wave -noupdate -format Analog-Step -height 40 -max 1024.0 -min -1024.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/qlvl 14 | add wave -noupdate -format Analog-Step -height 40 -max 1397.9999999999998 -min -1433.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/ilevel 15 | add wave -noupdate -format Analog-Step -height 40 -max 1580.0000000000002 -min -1471.0 -radix decimal -radixshowbase 0 /TestQAM16/qamod/qlevel 16 | add wave -noupdate -format Analog-Step -height 40 -max 1866.0000000000002 -min -1979.0 -radix decimal -radixshowbase 0 /TestQAM16/qam_if 17 | add wave -noupdate -format Analog-Step -height 40 -max 715.0 -min -736.0 -radix decimal -radixshowbase 0 /TestQAM16/ibb 18 | add wave -noupdate -format Analog-Step -height 40 -max 773.99999999999989 -min -706.0 -radix decimal -radixshowbase 0 /TestQAM16/qbb 19 | add wave -noupdate /TestQAM16/qamSJ/pedge 20 | add wave -noupdate /TestQAM16/qamSJ/pedge_dly 21 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestQAM16/qamSJ/sp_cnt 22 | add wave -noupdate /TestQAM16/qamSJ/sync 23 | add wave -noupdate -format Analog-Step -height 40 -max 411.99999999999994 -min -413.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/idiff 24 | add wave -noupdate -format Analog-Step -height 40 -max 408.0 -min -430.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/qdiff 25 | add wave -noupdate -max 407.0 -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/pulse 26 | add wave -noupdate -radix decimal -radixshowbase 0 /TestQAM16/qamSJ/pulse_peak 27 | TreeUpdate [SetDefaultTree] 28 | WaveRestoreCursors 29 | quietly wave cursor active 0 30 | configure wave -namecolwidth 97 31 | configure wave -valuecolwidth 40 32 | configure wave -justifyvalue left 33 | configure wave -signalnamewidth 1 34 | configure wave -snapdistance 10 35 | configure wave -datasetprefix 0 36 | configure wave -rowmargin 4 37 | configure wave -childrowmargin 2 38 | configure wave -gridoffset 7500 39 | configure wave -gridperiod 1 40 | configure wave -griddelta 40 41 | configure wave -timeline 0 42 | configure wave -timelineunits ns 43 | update 44 | WaveRestoreZoom {6588581 ps} {7623443 ps} 45 | -------------------------------------------------------------------------------- /chapter8/test_am.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter8/test_bb_sys.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter8/man_coding.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/man_coding.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling module ManchesterEncoder 4 | -- Compiling module HystComp 5 | -- Compiling module DiffManDecoder 6 | 7 | Top level modules: 8 | ManchesterEncoder 9 | HystComp 10 | DiffManDecoder 11 | 12 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter8/test_baseband.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/test_baseband.sv 13 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 14 | -- Compiling package SimSrcGen 15 | -- Compiling package CombFunctions 16 | -- Compiling package Fixedpoint 17 | -- Compiling module TestCounter 18 | -- Importing package SimSrcGen 19 | -- Compiling module TestCntSecMinHr 20 | -- Compiling module CntSecMinHr 21 | -- Compiling module Counter 22 | -- Compiling module CounterMax 23 | -- Compiling module TestDDS 24 | -- Compiling module DDS 25 | -- Compiling module TestFir 26 | -- Compiling module FIR 27 | -- Compiling module TestBasebandSys 28 | 29 | Top level modules: 30 | TestCounter 31 | TestCntSecMinHr 32 | CounterMax 33 | TestDDS 34 | TestFir 35 | TestBasebandSys 36 | 37 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter8/lfsr.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/lfsr.sv 38 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 39 | -- Compiling module LFSR 40 | 41 | Top level modules: 42 | LFSR 43 | 44 | } {} {}} Z:/projects/modelsim/FPGA_Book_2017/chapter8/crc.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/crc.sv 45 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 46 | -- Compiling package SimSrcGen 47 | -- Compiling package CombFunctions 48 | -- Compiling package Fixedpoint 49 | -- Compiling module TestCounter 50 | -- Importing package SimSrcGen 51 | -- Compiling module TestCntSecMinHr 52 | -- Compiling module CntSecMinHr 53 | -- Compiling module Counter 54 | -- Compiling module CounterMax 55 | -- Compiling module CRCGenerator 56 | -- Compiling module CRCChecker 57 | 58 | Top level modules: 59 | TestCounter 60 | TestCntSecMinHr 61 | CounterMax 62 | CRCGenerator 63 | CRCChecker 64 | 65 | } {} {}} 66 | -------------------------------------------------------------------------------- /chapter8/test_bbsys_wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestBasebandSys/clk 4 | add wave -noupdate /TestBasebandSys/rst 5 | add wave -noupdate /TestBasebandSys/dr_en 6 | add wave -noupdate /TestBasebandSys/dr_en180 7 | add wave -noupdate /TestBasebandSys/data_bit 8 | add wave -noupdate /TestBasebandSys/dbit_start 9 | add wave -noupdate /TestBasebandSys/dbit_last 10 | add wave -noupdate /TestBasebandSys/dbit_crc 11 | add wave -noupdate /TestBasebandSys/dman 12 | add wave -noupdate -format Analog-Step -height 40 -max 1427.0 -min -1477.0 -radix decimal /TestBasebandSys/baseband 13 | add wave -noupdate -format Analog-Step -height 40 -max 2047.0 -min -2048.0 -radix decimal /TestBasebandSys/bb_noi 14 | add wave -noupdate -format Analog-Step -height 40 -max 1614.0 -min -1663.0 -radix decimal /TestBasebandSys/bb_filtered 15 | add wave -noupdate /TestBasebandSys/bb_1bit 16 | add wave -noupdate /TestBasebandSys/decoded 17 | add wave -noupdate /TestBasebandSys/dec_valid 18 | add wave -noupdate /TestBasebandSys/chk_start 19 | add wave -noupdate /TestBasebandSys/chk_last 20 | add wave -noupdate /TestBasebandSys/err_reg 21 | TreeUpdate [SetDefaultTree] 22 | WaveRestoreCursors {{Cursor 1} {26846800 ps} 0} 23 | quietly wave cursor active 1 24 | configure wave -namecolwidth 94 25 | configure wave -valuecolwidth 50 26 | configure wave -justifyvalue left 27 | configure wave -signalnamewidth 1 28 | configure wave -snapdistance 10 29 | configure wave -datasetprefix 0 30 | configure wave -rowmargin 4 31 | configure wave -childrowmargin 2 32 | configure wave -gridoffset 7500 33 | configure wave -gridperiod 1 34 | configure wave -griddelta 40 35 | configure wave -timeline 0 36 | configure wave -timelineunits ns 37 | update 38 | WaveRestoreZoom {15179600 ps} {24628200 ps} 39 | -------------------------------------------------------------------------------- /chapter8/test_bbsys_wave_detail.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /TestBasebandSys/clk 4 | add wave -noupdate /TestBasebandSys/rst 5 | add wave -noupdate /TestBasebandSys/dr_en 6 | add wave -noupdate /TestBasebandSys/dr_en180 7 | add wave -noupdate /TestBasebandSys/lfsr_en 8 | add wave -noupdate /TestBasebandSys/lfsr_out 9 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestBasebandSys/bit_cnt 10 | add wave -noupdate /TestBasebandSys/data_bit 11 | add wave -noupdate /TestBasebandSys/dbit_start 12 | add wave -noupdate /TestBasebandSys/dbit_last 13 | add wave -noupdate /TestBasebandSys/crcGen/crc 14 | add wave -noupdate /TestBasebandSys/crcGen/crc_end 15 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestBasebandSys/crcGen/lfsr 16 | add wave -noupdate /TestBasebandSys/dbit_crc 17 | add wave -noupdate /TestBasebandSys/dr_en 18 | add wave -noupdate /TestBasebandSys/dr_en180 19 | add wave -noupdate /TestBasebandSys/dman 20 | add wave -noupdate -format Analog-Step -height 74 -max 1426.9999999999998 -min -1477.0 -radix decimal /TestBasebandSys/baseband 21 | add wave -noupdate -format Analog-Step -height 74 -max 2046.9999999999995 -min -2048.0 -radix decimal /TestBasebandSys/bb_noi 22 | add wave -noupdate -format Analog-Step -height 74 -max 1614.0 -min -1663.0 -radix decimal /TestBasebandSys/bb_filtered 23 | add wave -noupdate -radix decimal /TestBasebandSys/theHystComp/hyst 24 | add wave -noupdate /TestBasebandSys/bb_1bit 25 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestBasebandSys/theDmanDec/pcnt 26 | add wave -noupdate /TestBasebandSys/theDmanDec/trans 27 | add wave -noupdate /TestBasebandSys/decoded 28 | add wave -noupdate /TestBasebandSys/dec_valid 29 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestBasebandSys/dec_reg 30 | add wave -noupdate -radix unsigned -radixshowbase 0 /TestBasebandSys/dec_bcnt 31 | add wave -noupdate /TestBasebandSys/chk_start 32 | add wave -noupdate /TestBasebandSys/chk_last 33 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestBasebandSys/crcChk/lfsr 34 | add wave -noupdate -radix hexadecimal -radixshowbase 0 /TestBasebandSys/crcChk/lfsr_nxt 35 | add wave -noupdate /TestBasebandSys/err_reg 36 | TreeUpdate [SetDefaultTree] 37 | WaveRestoreCursors {{Cursor 1} {48933000 ps} 0} 38 | quietly wave cursor active 1 39 | configure wave -namecolwidth 150 40 | configure wave -valuecolwidth 100 41 | configure wave -justifyvalue left 42 | configure wave -signalnamewidth 1 43 | configure wave -snapdistance 10 44 | configure wave -datasetprefix 0 45 | configure wave -rowmargin 4 46 | configure wave -childrowmargin 2 47 | configure wave -gridoffset 7500 48 | configure wave -gridperiod 1 49 | configure wave -griddelta 40 50 | configure wave -timeline 0 51 | configure wave -timelineunits ns 52 | update 53 | WaveRestoreZoom {0 ps} {52500 ns} 54 | -------------------------------------------------------------------------------- /chapter8/test_bpsk.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /chapter8/test_carrier_recovery.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter8/adpll.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/adpll.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCounter 7 | -- Importing package SimSrcGen 8 | -- Compiling module TestCntSecMinHr 9 | -- Compiling module CntSecMinHr 10 | -- Compiling module Counter 11 | -- Compiling module CounterMax 12 | -- Compiling module TestDDS 13 | -- Compiling module DDS 14 | -- Compiling module OrthDDS 15 | -- Compiling module TestFir 16 | -- Compiling module FIR 17 | -- Compiling module Pid 18 | -- Importing package Fixedpoint 19 | -- Compiling module TestDelayChain 20 | -- Compiling module DelayChain 21 | -- Compiling module InterpDeci 22 | -- Compiling module TestQAM16 23 | -- Compiling module QAMModulator 24 | -- Compiling module QAMDemod 25 | -- Compiling module PeakHolder 26 | -- Compiling module QAM16SyncJudge 27 | -- Compiling module TestQamCarRec 28 | -- Compiling module ADPLL 29 | 30 | Top level modules: 31 | TestCounter 32 | TestCntSecMinHr 33 | CounterMax 34 | TestDDS 35 | TestFir 36 | TestDelayChain 37 | TestQAM16 38 | TestQamCarRec 39 | 40 | } {} {}} 41 | -------------------------------------------------------------------------------- /chapter8/test_fm.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter8/fm.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/fm.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCounter 7 | -- Importing package SimSrcGen 8 | -- Compiling module TestCntSecMinHr 9 | -- Compiling module CntSecMinHr 10 | -- Compiling module Counter 11 | -- Compiling module CounterMax 12 | -- Compiling module TestDDS 13 | -- Compiling module DDS 14 | -- Compiling module TestFir 15 | -- Compiling module FIR 16 | -- Compiling module TestAM 17 | -- Compiling module AMModulator 18 | -- Importing package Fixedpoint 19 | -- Compiling module AMEnvDemod 20 | -- Compiling module AMCohDemod 21 | -- Compiling module TestFM 22 | -- Compiling module FMModulator 23 | -- Compiling module WBFMDemod 24 | 25 | Top level modules: 26 | TestCounter 27 | TestCntSecMinHr 28 | CounterMax 29 | TestDDS 30 | TestFir 31 | TestAM 32 | TestFM 33 | 34 | } {} {}} 35 | -------------------------------------------------------------------------------- /chapter8/test_qam16.cr.mti: -------------------------------------------------------------------------------- 1 | Z:/projects/modelsim/FPGA_Book_2017/chapter8/qam.sv {1 {vlog -work work -sv -stats=none Z:/projects/modelsim/FPGA_Book_2017/chapter8/qam.sv 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling package SimSrcGen 4 | -- Compiling package CombFunctions 5 | -- Compiling package Fixedpoint 6 | -- Compiling module TestCounter 7 | -- Importing package SimSrcGen 8 | -- Compiling module TestCntSecMinHr 9 | -- Compiling module CntSecMinHr 10 | -- Compiling module Counter 11 | -- Compiling module CounterMax 12 | -- Compiling module TestDelayChain 13 | -- Compiling module DelayChain 14 | -- Compiling module TestDDS 15 | -- Compiling module DDS 16 | -- Compiling module OrthDDS 17 | -- Compiling module TestFir 18 | -- Compiling module FIR 19 | -- Compiling module InterpDeci 20 | -- Compiling module TestQAM16 21 | -- Compiling module QAMModulator 22 | -- Compiling module QAMDemod 23 | -- Compiling module PeakHolder 24 | -- Compiling module QAM16SyncJudge 25 | 26 | Top level modules: 27 | TestCounter 28 | TestCntSecMinHr 29 | CounterMax 30 | TestDelayChain 31 | TestDDS 32 | TestFir 33 | TestQAM16 34 | 35 | } {} {}} 36 | -------------------------------------------------------------------------------- /chapter8/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chapter8/vsim.wlf -------------------------------------------------------------------------------- /chisel/.gitignore: -------------------------------------------------------------------------------- 1 | .bloop/ 2 | generated/ 3 | verilog/ 4 | project/* 5 | target/ 6 | test_run_dir/ 7 | !.mvn/wrapper/maven-wrapper.jar 8 | !**/src/main/**/target/ 9 | !**/src/test/**/target/ 10 | !project/*.sbt 11 | 12 | ### VSCode Metals ### 13 | .metals/ 14 | 15 | ### IntelliJ IDEA ### 16 | .idea/* 17 | !.idea/.gitignore 18 | !.idea/codeStyles 19 | !.idea/inspectionProfiles 20 | !.idea/runConfigurations 21 | !.idea/vcs.xml 22 | !.idea/misc.xml 23 | !.idea/modules.xml 24 | !.idea/scala_settings.xml 25 | !.idea/.name 26 | .idea/workspace.xml 27 | .idea/tasks.xml 28 | .idea/shelf/ 29 | .idea/dataSources/ 30 | .idea/*.iml 31 | .idea/caches/ 32 | *.iws 33 | *.iml 34 | *.ipr 35 | out/ 36 | !**/src/main/**/out/ 37 | !**/src/test/**/out/ 38 | 39 | ### Eclipse ### 40 | .apt_generated 41 | .classpath 42 | .factorypath 43 | .project 44 | .settings 45 | .springBeans 46 | .sts4-cache 47 | bin/ 48 | !**/src/main/**/bin/ 49 | !**/src/test/**/bin/ 50 | 51 | ### NetBeans ### 52 | /nbproject/private/ 53 | /nbbuild/ 54 | /dist/ 55 | /nbdist/ 56 | /.nb-gradle/ 57 | build/ 58 | !**/src/main/**/build/ 59 | !**/src/test/**/build/ 60 | 61 | ### VS Code ### 62 | .vscode/ 63 | 64 | ### Mac OS ### 65 | .DS_Store 66 | 67 | ### Scala ### 68 | .bsp/ 69 | 70 | ### Metals ### 71 | **/metals.log 72 | **/metals*.db 73 | -------------------------------------------------------------------------------- /chisel/.idea/.gitignore: -------------------------------------------------------------------------------- 1 | # Default ignored files 2 | /shelf/ 3 | /workspace.xml 4 | -------------------------------------------------------------------------------- /chisel/.idea/codeStyles/Project.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | 7 | -------------------------------------------------------------------------------- /chisel/.idea/codeStyles/codeStyleConfig.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 5 | -------------------------------------------------------------------------------- /chisel/.idea/misc.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /chisel/.idea/modules.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /chisel/.idea/scala_settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | -------------------------------------------------------------------------------- /chisel/.idea/vcs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /chisel/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.13.1") 2 | -------------------------------------------------------------------------------- /chisel/src/main/scala/RenamePorts2AmbaConventions.md: -------------------------------------------------------------------------------- 1 | Method `RenamePorts2AmbaConventions()` in gen_verilog.scala implemented the following method. 2 | 3 | ### AXI4-Stream 4 | 5 | Requirements: 6 | 7 | 1. Use `IrrevocableIO`; 8 | 2. Name the instance of `IrrevocalbeIO` as: 9 | 10 | * `s**_axis**` or `m**_axis**`, 11 | * `s**_**_axis**_**` or `m**_**_axis**_**`, 12 | 13 | In which: 14 | 15 | * `**` can be any length (including 0) of alphabet character or digit, 16 | * `_**` can be repeated any times. 17 | 18 | Replace: 19 | 20 | ``` 21 | ([sm][^\W_]*(_[^\W_]+)*_axis[^\W_]*(_[^\W_]+)*)_(t?(valid|ready)|[^\W_]+_t?(last|data|user|id|keep|strb))\b 22 | ``` 23 | 24 | To: 25 | 26 | ``` 27 | $1_t$5$6 28 | ``` 29 | 30 | ### AXI4 (and AXI4-Lite) 31 | 32 | Requirements: 33 | 34 | 1. Use `Axi4IO` with 5 channels named as "aw", "w","b","ar","r"; 35 | 2. Name the instance of `Axi4IO` as: 36 | 37 | * `s**_axi**` or `m**_axi**`, 38 | * `s**_**_axi**_**` or `m**_**_axi**_**`, 39 | 40 | In which: 41 | 42 | * 1st character after "axi" can NOT be 's', 43 | * `**` can be any length (including 0) of alphabet character or digit, 44 | * `_**` can be repeated any times. 45 | 46 | Replace: 47 | 48 | ``` 49 | ([sm][^\W_]*(_[^\W_]+)*_(axi|axi[^\W_s][^\W_]*)(_[^\W_]+)*)_(aw|w|b|ar|r)(_[^\W_]+)?_t?(ready|valid|addr|prot|data|strb|resp|id|len|size|burst|lock|cache|qos|region|user)\b 50 | ``` 51 | 52 | To: 53 | 54 | ``` 55 | $1_$5$7 56 | ``` 57 | -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/accumulator.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | package loywong 26 | 27 | import chisel3._ 28 | import chisel3.util._ 29 | 30 | class Accumulator(modu: Int) extends Module { 31 | require(modu > 1) 32 | val dw = log2Up(modu) 33 | val idw = dw + 2 34 | val io = IO(new Bundle { 35 | val en = Input(Bool()) 36 | val step = Input(SInt(dw.W)) 37 | val accu = Output(UInt(dw.W)) 38 | val wrapUp = Output(Bool()) 39 | val wrapDown = Output(Bool()) 40 | }) 41 | 42 | val accu = RegInit(0.U(dw.W)) 43 | val nextRaw = Wire(SInt(idw.W)) 44 | val wrapUp = WireDefault(nextRaw >= modu.S) 45 | val wrapDown = WireDefault(nextRaw < 0.S) 46 | val nextWrap = Wire(UInt(dw.W)) 47 | nextRaw := (0.U(1.W) ## accu).asSInt +& io.step 48 | nextWrap := MuxCase(nextRaw(dw - 1, 0), Seq( 49 | wrapUp -> (nextRaw - modu.S)(dw - 1, 0), 50 | wrapDown -> (nextRaw + modu.S)(dw - 1, 0) 51 | )) 52 | when(io.en) { 53 | accu := nextWrap 54 | } 55 | io.accu := accu 56 | io.wrapUp := wrapUp && io.en 57 | io.wrapDown := wrapDown && io.en 58 | } 59 | 60 | package examples { 61 | class accumulator_example extends Module { 62 | val modu = 100 63 | val io = IO(new Bundle { 64 | val en = Input(Bool()) 65 | val step = Input(SInt(7.W)) 66 | val accu = Output(UInt(7.W)) 67 | val wrapUp = Output(Bool()) 68 | val wrapDown = Output(Bool()) 69 | }) 70 | val theAccu = Module(new Accumulator(modu)) 71 | io <> theAccu.io 72 | 73 | } 74 | } -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/cordic_iteration.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/chisel/src/main/scala/loywong/cordic_iteration.ods -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/decoder.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | package loywong 26 | 27 | import chisel3._ 28 | 29 | object Decoder { 30 | def apply(in:UInt) : UInt = { 1.U << in } 31 | } 32 | 33 | package examples { 34 | class decoder_example(INW: Int = 4) extends Module { 35 | val io = IO(new Bundle { 36 | val in = Input(UInt(INW.W)) 37 | val out = Output(UInt((1 << INW).W)) 38 | }) 39 | io.out := Decoder(io.in) 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/delay_chain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | package loywong 26 | 27 | import chisel3._ 28 | import chisel3.util._ 29 | 30 | package examples { 31 | class delay_chain_example extends Module { 32 | val n = 16 33 | val dw = 8 34 | val io = IO(new Bundle { 35 | val en = Input(Bool()) 36 | val in = Input(UInt(dw.W)) 37 | val out = Output(UInt(dw.W)) 38 | }) 39 | // user chisel3.util.ShiftRegister directly 40 | if(n < 16) 41 | io.out := ShiftRegister(io.in, n, io.en) 42 | else 43 | io.out := ShiftRegister.mem(io.in, n, io.en, true, None) 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/edge2en.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | /* 26 | package loywong 27 | 28 | import chisel3._ 29 | import chisel3.util._ 30 | 31 | // ==== Moved into cross_clock_domain.scala ==== 32 | object Edge2En { 33 | def apply(nStages:Int = 2, in:Bool, initOnes:Boolean = false): (Bool, Bool, Bool) = { 34 | require(nStages >= 0, "nStages must positive in edge2en") 35 | val dly_init = if(initOnes) { 36 | // Fill(nStages + 1, 1.U(1.W)) 37 | ~0.U((nStages + 1).W) 38 | } else { 39 | 0.U((nStages + 1).W) 40 | } 41 | val dly = RegInit(dly_init.cloneType, dly_init) 42 | val rising = WireInit(false.B) 43 | val falling = WireInit(false.B) 44 | if(nStages == 0) { 45 | dly(0) := in 46 | rising := "b01".U === dly(0) ## in 47 | falling := "b10".U === dly(0) ## in 48 | } 49 | else { 50 | dly := (dly << 1) | in.asUInt 51 | rising := "b01".U === dly(nStages) ## dly(nStages - 1) 52 | falling := "b10".U === dly(nStages) ## dly(nStages - 1) 53 | } 54 | (rising, falling, dly(nStages)) 55 | } 56 | } 57 | 58 | package examples { 59 | class edge2en_example(nStages: Int = 2) extends Module { 60 | val io = IO(new Bundle { 61 | val in = Input(Bool()) 62 | val out = Output(Bool()) 63 | val rising = Output(Bool()) 64 | val falling = Output(Bool()) 65 | }) 66 | val (r, f, o) = edge2en(nStages, io.in, true) 67 | io.rising := r 68 | io.falling := f 69 | io.out := o 70 | } 71 | } 72 | */ 73 | -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/encoder.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | package loywong 26 | 27 | import chisel3._ 28 | import chisel3.util._ 29 | 30 | package examples { 31 | /** 32 | * A priority encoder example for emitting verilog. 33 | * @note You should use chisel3.PriorityEncoder directly. 34 | */ 35 | class encoder_example(OUTW: Int = 4) extends Module { 36 | val io = IO(new Bundle { 37 | val in = Input(UInt((1 << OUTW).W)) 38 | val out = Output(UInt(OUTW.W)) 39 | }) 40 | // use chisel3.PriorityEncoder ! 41 | io.out := PriorityEncoder(io.in) 42 | } 43 | } 44 | -------------------------------------------------------------------------------- /chisel/src/main/scala/loywong/shift_reg.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | package loywong 26 | 27 | import chisel3._ 28 | 29 | /*class ShiftReg(nBits: Int) extends Module { 30 | val io = IO(new Bundle { 31 | val shift = Input(Bool()) 32 | val load = Input(Bool()) 33 | val din = Input(UInt(nBits.W)) 34 | val sin = Input(Bool()) 35 | val qout = Output(UInt(nBits.W)) 36 | }) 37 | val regs = RegInit(0.U(nBits.W)) 38 | /*regs := MuxCase(regs, Seq( 39 | ((io.shift ## io.load) === "b10".U) -> regs(nBits - 2, 0) ## io.sin, 40 | ((io.shift ## io.load) === "b01".U) -> io.din, 41 | ((io.shift ## io.load) === "b11".U) -> io.din(nBits - 2, 0) ## io.sin 42 | ))*/ 43 | switch (io.shift ## io.load) { 44 | is("b10".U) { regs := regs(nBits - 2, 0) ## io.sin } 45 | is("b01".U) { regs := io.din } 46 | is("b11".U) { regs := io.din(nBits - 2, 0) ## io.sin } 47 | } 48 | io.qout := regs 49 | }*/ 50 | 51 | class ShiftReg(nBits: Int) { 52 | val regs = RegInit(0.U(nBits.W)) 53 | def load(din: UInt): UInt = { 54 | regs := din 55 | regs 56 | } 57 | def shift(sin: Bool): UInt = { 58 | regs := regs(nBits - 2, 0) ## sin 59 | regs 60 | } 61 | def qout: UInt = regs 62 | } 63 | 64 | package examples { 65 | class shift_reg_example extends Module { 66 | val dw = 10 67 | val io = IO(new Bundle { 68 | val shift = Input(Bool()) 69 | val load = Input(Bool()) 70 | val din = Input(UInt(dw.W)) 71 | val sin = Input(Bool()) 72 | val qout = Output(UInt(dw.W)) 73 | }) 74 | val sr = new ShiftReg(dw) 75 | when(io.shift) { 76 | sr.shift(io.sin) 77 | } 78 | when(io.load) { 79 | sr.load(io.din) 80 | } 81 | io.qout := sr.qout 82 | } 83 | } 84 | -------------------------------------------------------------------------------- /chisel/src/test/scala/temp.scala: -------------------------------------------------------------------------------- 1 | // temp.scala is used for some temporarily function or unit test 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chiseltest._ 6 | import org.scalatest.flatspec.AnyFlatSpec 7 | import loywong._ 8 | import loywong.util._ 9 | import loywongtest._ 10 | 11 | /*class temporarilyTests extends AnyFlatSpec with ChiselScalatestTester { 12 | val x = BigInt("1001_1100_1011_1010_1110_1001_0001".replaceAll("_", ""), 2) 13 | val ss0 = x.bitSlices(6, 1, 3, 5, 4) 14 | println(ss0.map(s => f"0x${s}%x")) 15 | val ss1 = x.bitSlicesByteWise(4, 12, 5) 16 | println(ss1.map(s => f"0x${s}%02x")) 17 | }*/ -------------------------------------------------------------------------------- /chisel/src/test/scala/test_accumulator.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * MIT License 3 | * 4 | * Copyright (c) 2025 loykylewong (loywong@gmail.com) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | import chisel3._ 26 | import chisel3.util._ 27 | import chiseltest._ 28 | import org.scalatest.flatspec.AnyFlatSpec 29 | import org.scalatest.matchers.should.Matchers._ 30 | import loywong._ 31 | 32 | class test_accumulator extends AnyFlatSpec with ChiselScalatestTester { 33 | println() 34 | println("====================") 35 | println("Test Accumulator...") 36 | println("--------------------") 37 | 38 | "DUT" should "pass" in { 39 | val modu = 100 40 | test(new Accumulator(modu)).withAnnotations(Seq(WriteVcdAnnotation)) { 41 | dut => { 42 | dut.clock.step() 43 | dut.reset.poke(true.B) 44 | dut.clock.step() 45 | dut.reset.poke(false.B) 46 | 47 | var x = 0 48 | // ---- step 15 x 20 ---- 49 | var step = 15 50 | dut.io.step.poke(step.S) 51 | dut.io.en.poke(true) 52 | for(i <- 0 until 20) { 53 | dut.clock.step() 54 | x += step 55 | val y = math.floorMod(x, modu) 56 | if(y + step >= modu) 57 | dut.io.wrapUp.expect(true) 58 | else 59 | dut.io.wrapUp.expect(false) 60 | dut.io.wrapDown.expect(false) 61 | dut.io.accu.expect(y.U) 62 | } 63 | // ---- disable ---- 64 | dut.io.en.poke(false) 65 | dut.clock.step(20) 66 | dut.io.accu.expect(math.floorMod(x, modu).U) 67 | // ---- step -20 x 20 ---- 68 | step = -20 69 | dut.io.step.poke(step.S) 70 | dut.io.en.poke(true) 71 | for(i <- 0 until 20) { 72 | dut.clock.step() 73 | x += step 74 | val y = math.floorMod(x, modu) 75 | if(y + step < 0) 76 | dut.io.wrapDown.expect(true) 77 | else 78 | dut.io.wrapDown.expect(false) 79 | dut.io.wrapUp.expect(false) 80 | dut.io.accu.expect(y.U) 81 | } 82 | println("-----------------------------") 83 | println(s"\u001b[1mAccumulator test Pass.\u001b[0m") 84 | println("=============================") 85 | Thread.sleep(1000) 86 | } 87 | } 88 | } 89 | } -------------------------------------------------------------------------------- /common.sv: -------------------------------------------------------------------------------- 1 | `ifndef __COMMON_SV__ 2 | `define __COMMON_SV__ 3 | 4 | package SimSrcGen; 5 | task automatic GenClk( 6 | ref logic clk, input realtime delay, realtime period 7 | ); 8 | clk = 1'b0; 9 | #delay; 10 | forever #(period/2) clk = ~clk; 11 | endtask 12 | task automatic GenRst( 13 | ref logic clk, 14 | ref logic rst, 15 | input int start, 16 | input int duration 17 | ); 18 | rst = 1'b0; 19 | repeat(start) @(posedge clk); 20 | rst = 1'b1; 21 | repeat(duration) @(posedge clk); 22 | rst = 1'b0; 23 | endtask 24 | task automatic KeyPress(ref logic key, input realtime t); 25 | for(int i = 0; i < 30; i++) begin 26 | #0.11ms key = '0; #0.14ms key = '1; 27 | end 28 | #t; key = '0; 29 | endtask 30 | task automatic QuadEncGo(ref logic a, b, input logic ccw, realtime qprd); 31 | a = 0; b = 0; 32 | if(!ccw) begin 33 | #qprd a = 1; #qprd b = 1; #qprd a = 0; #qprd b = 0; 34 | end 35 | else begin 36 | #qprd b = 1; #qprd a = 1; #qprd b = 0; #qprd a = 0; 37 | end 38 | endtask 39 | endpackage 40 | 41 | package CombFunctions; 42 | `define DEF_PRIO_ENC(fname, ow) \ 43 | function automatic logic [ow - 1 : 0] fname( \ 44 | input logic [2**ow - 1 : 0] in \ 45 | ); \ 46 | fname = '0; \ 47 | for(integer i = 2**ow - 1; i >= 0; i--) begin \ 48 | if(in[i]) fname = ow'(i); \ 49 | end \ 50 | endfunction 51 | endpackage 52 | 53 | package Fixedpoint; 54 | let max(x, y) = x > y? x : y; 55 | `define DEF_REAL_TO_Q(name, i, f) \ 56 | let name(x) = ((i)+(f))'(integer(x * (2**(f)))); 57 | `define DEF_Q_TO_REAL(name, i, f) \ 58 | let name(x) = real'($signed(x)) / 2.0 ** (f); 59 | `define DEF_FP_ADD(name, i0, f0, i1, f1, fr) \ 60 | let name(x, y) = \ 61 | ((f0) >= (f1)) ? \ 62 | ( ( max((i0),(i1))+(f0))'(x) + \ 63 | ( (max((i0),(i1))+(f0))'(y) <<< ((f0)-(f1)) ) \ 64 | ) >>> ((f0)-(fr)) : \ 65 | ( ( (max((i0),(i1))+(f1))'(x) <<< ((f1)-(f0)) ) + \ 66 | (max((i0),(i1))+(f1))'(y) \ 67 | ) >>> ((f1)-(fr)); 68 | `define DEF_FP_MUL(name, i0, f0, i1, f1, fr) \ 69 | let name(x, y) = \ 70 | ( ((i0)+(i1)+(f0)+(f1))'(x) * ((i0)+(i1)+(f0)+(f1))'(y) \ 71 | ) >>> ((f0)+(f1)-(fr)); 72 | // // if you need DEF_FP_MUL and your compiler doesn't support "let": 73 | // `define DEF_FP_MUL(name, i0, f0, i1, f1, fr) \ 74 | // function automatic signed [(i0)+(i1)+(fr)-1:0] name(input signed [(i0)+(f0)-1:0] x, input signed [(i1)+(f1)-1:0] y); \ 75 | // name = (((i0)+(i1)+(f0)+(f1))'(x) * ((i0)+(i1)+(f0)+(f1))'(y)) >>> ((f0)+(f1)-(fr)); \ 76 | // endfunction 77 | 78 | `define DEF_CPLX_CALC(typename, addname, subname, mulname, i, f) \ 79 | typedef struct { \ 80 | logic signed [(i)+(f)-1:0] re; \ 81 | logic signed [(i)+(f)-1:0] im; \ 82 | } typename; \ 83 | function automatic typename mulname(typename a, typename b, logic sc); \ 84 | mulname.re = ( (2*(i)+2*(f))'(a.re) * b.re - (2*(i)+2*(f))'(a.im) * b.im ) >>> ((f)+sc); \ 85 | mulname.im = ( (2*(i)+2*(f))'(a.re) * b.im + (2*(i)+2*(f))'(a.im) * b.re ) >>> ((f)+sc); \ 86 | endfunction \ 87 | function automatic typename addname(typename a, typename b, logic sc); \ 88 | addname.re = ( ((i)+(f)+1)'(a.re) + b.re ) >>> sc; \ 89 | addname.im = ( ((i)+(f)+1)'(a.im) + b.im ) >>> sc; \ 90 | endfunction \ 91 | function automatic typename subname(typename a, typename b, logic sc); \ 92 | subname.re = ( ((i)+(f)+1)'(a.re) - b.re ) >>> sc; \ 93 | subname.im = ( ((i)+(f)+1)'(a.im) - b.im ) >>> sc; \ 94 | endfunction 95 | 96 | endpackage 97 | 98 | `endif 99 | -------------------------------------------------------------------------------- /foreword.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/foreword.png -------------------------------------------------------------------------------- /《FPGA应用开发和仿真》第一版第一次印刷勘误表(20190130).pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/《FPGA应用开发和仿真》第一版第一次印刷勘误表(20190130).pdf -------------------------------------------------------------------------------- /《FPGA应用开发和仿真》第一版第一次印刷勘误表(Errata_20190531).pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/《FPGA应用开发和仿真》第一版第一次印刷勘误表(Errata_20190531).pdf -------------------------------------------------------------------------------- /《FPGA应用开发和仿真》第一版第一次印刷勘误表(Errata_20201022).pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/loykylewong/FPGA-Application-Development-and-Simulation/85fd795a10f7f6a1ff41f20f4c2b3c70b9f191d4/《FPGA应用开发和仿真》第一版第一次印刷勘误表(Errata_20201022).pdf --------------------------------------------------------------------------------