├── ram.h ├── stm8.h ├── ram.c ├── app ├── Makefile └── main.c ├── util └── ivt_gen.py ├── LICENSE ├── init.s ├── config.h ├── Makefile ├── README.md ├── uploader └── boot.py ├── main.c ├── stm8s.h └── stm8l.h /ram.h: -------------------------------------------------------------------------------- 1 | #ifndef RAM_H 2 | #define RAM_H 3 | 4 | #include 5 | 6 | void ram_flash_write_block(uint16_t addr, const uint8_t *buf); 7 | 8 | #endif /* RAM_H */ 9 | -------------------------------------------------------------------------------- /stm8.h: -------------------------------------------------------------------------------- 1 | #ifndef STM8_H 2 | #define STM8_H 3 | #if (STM8L) 4 | #include "stm8l.h" 5 | #elif (STM8S) 6 | #include "stm8s.h" 7 | #else 8 | #error MCU family not specified! 9 | #endif 10 | #endif /* STM8_H */ 11 | -------------------------------------------------------------------------------- /ram.c: -------------------------------------------------------------------------------- 1 | #include "ram.h" 2 | #include "stm8.h" 3 | #include "config.h" 4 | 5 | #pragma codeseg RAM_SEG 6 | void ram_flash_write_block(uint16_t addr, const uint8_t *buf) { 7 | /* enable block programming */ 8 | FLASH_CR2 = 1 << FLASH_CR2_PRG; 9 | #if !(STM8L) 10 | FLASH_NCR2 = (uint8_t) ~(1 << FLASH_NCR2_NPRG); 11 | #endif 12 | 13 | /* write data from buffer */ 14 | for (uint8_t i = 0; i < BLOCK_SIZE; i++) 15 | _MEM_(addr + i) = buf[i]; 16 | 17 | /* wait for operation to complete */ 18 | while (!(FLASH_IAPSR & (1 << FLASH_IAPSR_EOP))); 19 | } 20 | -------------------------------------------------------------------------------- /app/Makefile: -------------------------------------------------------------------------------- 1 | MCU ?= stm8s003f3 2 | FAMILY ?= STM8S 3 | ARCH = stm8 4 | 5 | F_CPU ?= 2000000 6 | TARGET ?= main.ihx 7 | 8 | SRCS := $(wildcard *.c) 9 | OBJS = $(SRCS:.c=.rel) 10 | 11 | CC = sdcc 12 | OBJCOPY = sdobjcopy 13 | CFLAGS = -m$(ARCH) -p$(MCU) -D$(FAMILY) 14 | CFLAGS += -DF_CPU=$(F_CPU)UL -I. -I$(LIBDIR) 15 | CFLAGS += --stack-auto --noinduction --use-non-free 16 | LDFLAGS = -m$(ARCH) -l$(ARCH) --out-fmt-ihx 17 | ## RELOCATE_IVT set to 0: 18 | #LDFLAGS += --code-loc 0x8200 19 | ## RELOCATE_IVT set to 1: 20 | LDFLAGS += --code-loc 0x8280 21 | 22 | all: $(TARGET) 23 | 24 | $(TARGET): $(OBJS) 25 | $(CC) $(LDFLAGS) $(OBJS) -o $@ 26 | @$(OBJCOPY) -I ihex --output-target=binary $(TARGET) firmware.bin 27 | 28 | %.rel: %.c 29 | $(CC) $(CFLAGS) -c $< -o $@ 30 | 31 | clean: 32 | rm -f *.map *.asm *.rel *.ihx *.o *.sym *.lk *.lst *.rst *.cdb *.bin 33 | 34 | .PHONY: clean all 35 | -------------------------------------------------------------------------------- /util/ivt_gen.py: -------------------------------------------------------------------------------- 1 | BOOT_ADDR = 0x8400 2 | 3 | prologue = ( 4 | '.module IVT', 5 | '.macro jump addr', 6 | ' jp %s + addr' % hex(BOOT_ADDR), 7 | ' .ds 1', 8 | '.endm', 9 | '', 10 | '.area IVT', 11 | 'int init ; reset', 12 | 'jump 0x4 ; trap',) 13 | 14 | epilogue = ( 15 | '', 16 | '.area GSINIT', 17 | 'init:', 18 | ' ldw x, #l_DATA', 19 | ' jreq 00002$', 20 | '00001$:', 21 | ' clr (s_DATA - 1, x)', 22 | ' decw x', 23 | ' jrne 00001$', 24 | '00002$:', 25 | ' ldw x, #l_INITIALIZER', 26 | ' jreq 00004$', 27 | '00003$:', 28 | ' ld a, (s_INITIALIZER - 1, x)', 29 | ' ld (s_INITIALIZED - 1, x), a', 30 | ' decw x', 31 | ' jrne 00003$', 32 | '00004$:', 33 | ' jp _bootloader_main') 34 | 35 | for i in prologue: print(i) 36 | for i in range(30): 37 | print('jump %s ; int%d' % (hex(i * 4 + 8), i)) 38 | for i in epilogue: print(i) 39 | -------------------------------------------------------------------------------- /app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "../stm8.h" 3 | 4 | #define LED_PIN 4 5 | 6 | void dummy_isr() __interrupt(29) __naked { ; } 7 | 8 | void tim4_isr() __interrupt(TIM4_ISR) { 9 | static uint16_t ctr = 0; 10 | if (++ctr >= 64) { 11 | PD_ODR ^= (1 << LED_PIN); 12 | ctr = 0; 13 | } 14 | TIM4_SR &= ~(1 << TIM4_SR_UIF); 15 | } 16 | 17 | static void timer_config() { 18 | #if STM8L 19 | CLK_PCKENR1 |= 1 << 2; 20 | #endif 21 | /* Prescaler = 128 */ 22 | TIM4_PSCR = 0b00000111; 23 | 24 | /* Frequency = F_CLK / (2 * prescaler * (1 + ARR)) 25 | * = 2 MHz / (2 * 128 * (1 + 77)) = 100 Hz */ 26 | TIM4_ARR = 77; 27 | 28 | TIM4_IER |= (1 << TIM4_IER_UIE); // Enable Update Interrupt 29 | TIM4_CR1 |= (1 << TIM4_CR1_CEN); // Enable TIM4 30 | } 31 | 32 | void main() { 33 | PD_DDR |= (1 << LED_PIN); 34 | PD_CR1 |= (1 << LED_PIN); 35 | 36 | enable_interrupts(); 37 | timer_config(); 38 | 39 | while (1) { 40 | /* interrupts do the job */ 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 lujji 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /init.s: -------------------------------------------------------------------------------- 1 | .module INIT 2 | .macro jump addr 3 | jp 0x8280 + addr 4 | .ds 1 5 | .endm 6 | 7 | .area IVT 8 | int init ; reset 9 | jump 0x4 ; trap 10 | jump 0x8 ; int0 11 | jump 0xc ; int1 12 | jump 0x10 ; int2 13 | jump 0x14 ; int3 14 | jump 0x18 ; int4 15 | jump 0x1c ; int5 16 | jump 0x20 ; int6 17 | jump 0x24 ; int7 18 | jump 0x28 ; int8 19 | jump 0x2c ; int9 20 | jump 0x30 ; int10 21 | jump 0x34 ; int11 22 | jump 0x38 ; int12 23 | jump 0x3c ; int13 24 | jump 0x40 ; int14 25 | jump 0x44 ; int15 26 | jump 0x48 ; int16 27 | jump 0x4c ; int17 28 | jump 0x50 ; int18 29 | jump 0x54 ; int19 30 | jump 0x58 ; int20 31 | jump 0x5c ; int21 32 | jump 0x60 ; int22 33 | jump 0x64 ; int23 34 | jump 0x68 ; int24 35 | jump 0x6c ; int25 36 | jump 0x70 ; int26 37 | jump 0x74 ; int27 38 | jump 0x78 ; int28 39 | jump 0x7c ; int29 40 | 41 | .area SSEG 42 | .area GSINIT 43 | init: 44 | ldw x, #l_DATA 45 | jreq 00002$ 46 | 00001$: 47 | clr (s_DATA - 1, x) 48 | decw x 49 | jrne 00001$ 50 | 00002$: 51 | ldw x, #l_INITIALIZER 52 | jreq 00004$ 53 | 00003$: 54 | ld a, (s_INITIALIZER - 1, x) 55 | ld (s_INITIALIZED - 1, x), a 56 | decw x 57 | jrne 00003$ 58 | 00004$: 59 | jp _bootloader_main 60 | -------------------------------------------------------------------------------- /config.h: -------------------------------------------------------------------------------- 1 | #ifndef CONFIG_H 2 | #define CONFIG_H 3 | 4 | #include "stm8.h" 5 | 6 | /* UART configuration */ 7 | #define BAUDRATE 115200 8 | 9 | #if defined(STM8L) 10 | #define UART_SR USART1_SR 11 | #define UART_CLK_ENABLE() do { CLK_PCKENR1 |= (1 << 5); } while(0) 12 | #else 13 | #define UART_SR UART1_SR 14 | #define UART_CLK_ENABLE() { ; } 15 | #endif 16 | 17 | /* application address */ 18 | #define BOOT_ADDR 0x8280 19 | 20 | /* 21 | * 0 = overwrite vector table during update, 22 | * 1 = use default jump-table 23 | */ 24 | #define RELOCATE_IVT 1 25 | 26 | /* flash block size */ 27 | #define BLOCK_SIZE 64 28 | 29 | /* entry jumper */ 30 | #define BOOT_PIN 3 31 | #define BOOT_PIN_IDR PD_IDR 32 | #define BOOT_PIN_CR1 PD_CR1 33 | 34 | /* internal RC oscillator, CKDIVR = 0 */ 35 | #define F_CPU 16000000UL 36 | 37 | /* not configured by user */ 38 | #define STR(x) #x 39 | #define STRX(x) STR(x) 40 | #define BOOT() __asm__("jp " STRX(BOOT_ADDR)) 41 | #define UART_DIV ((F_CPU + BAUDRATE / 2) / BAUDRATE) 42 | #define UART_SR_TXE 7 43 | #define UART_SR_TC 6 44 | #define UART_SR_RXNE 5 45 | #define UART_DR *(&UART_SR + 0x01) 46 | #define UART_BRR1 *(&UART_SR + 0x02) 47 | #define UART_BRR2 *(&UART_SR + 0x03) 48 | #define UART_CR1 *(&UART_SR + 0x04) 49 | #define UART_CR2 *(&UART_SR + 0x05) 50 | #define UART_CR2_TEN 3 51 | #define UART_CR2_REN 2 52 | 53 | #endif /* CONFIG_H */ 54 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ## STM8S 2 | MCU ?= stm8s003f3 3 | FAMILY ?= STM8S 4 | 5 | ## STM8L 6 | # MCU ?= stm8l051f3 7 | # FAMILY ?= STM8L 8 | 9 | ARCH = stm8 10 | 11 | TARGET ?= main.ihx 12 | 13 | SRCS := $(wildcard *.c) 14 | ASRCS := $(wildcard *.s) 15 | 16 | OBJS = $(SRCS:.c=.rel) 17 | OBJS += $(ASRCS:.s=.rel) 18 | 19 | CC = sdcc 20 | LD = sdld 21 | AS = sdasstm8 22 | OBJCOPY = sdobjcopy 23 | ASFLAGS = -plosgff 24 | CFLAGS = -m$(ARCH) -p$(MCU) -D$(FAMILY) -I. 25 | CFLAGS += --stack-auto --noinduction --use-non-free --noinvariant --opt-code-size 26 | LDFLAGS = -m$(ARCH) -l$(ARCH) --out-fmt-ihx 27 | LDFLAGS += -Wl-bIVT=0x8000 -Wl-bGSINIT=0x8080 28 | 29 | all: $(TARGET) size 30 | 31 | $(TARGET): $(OBJS) 32 | $(CC) $(LDFLAGS) $(OBJS) -o $@ 33 | 34 | %.rel: %.s 35 | $(AS) $(ASFLAGS) $< 36 | 37 | %.rel: %.c 38 | $(CC) $(CFLAGS) -c $< -o $@ 39 | 40 | flash: $(TARGET) 41 | stm8flash -c stlinkv2 -p $(MCU) -w $(TARGET) 42 | 43 | clean: 44 | rm -f *.map *.rel *.ihx *.o *.sym *.lk *.lst *.rst *.cdb *.bin *.asm 45 | 46 | size: 47 | @$(OBJCOPY) -I ihex --output-target=binary $(TARGET) $(TARGET).bin 48 | @echo "-----\nImage size:" 49 | @stat -L -c %s $(TARGET).bin 50 | 51 | ## @TODO: separate option-bytes for stm8s and stm8l! 52 | # enable write-protection on first 10 pages 53 | opt-set: 54 | @echo '0x00 0x09 0xf6 0x00 0xff 0x00 0xff 0x00 0xff 0x00 0xff' | xxd -r > opt.bin 55 | stm8flash -c stlinkv2 -p stm8s003f3 -s opt -w opt.bin 56 | 57 | # reset option-bytes to factory defaults 58 | opt-reset: 59 | @echo '0x00 0x00 0xff 0x00 0xff 0x00 0xff 0x00 0xff 0x00 0xff' | xxd -r > opt.bin 60 | stm8flash -c stlinkv2 -p stm8s003f3 -s opt -w opt.bin 61 | 62 | dump-opt: 63 | stm8flash -c stlinkv2 -p $(MCU) -s opt -r dump_opt.bin 64 | 65 | dump-flash: 66 | stm8flash -c stlinkv2 -p $(MCU) -s flash -r dump_flash.bin 67 | 68 | erase: 69 | tr '\000' '\377' < /dev/zero | dd of=empty.bin bs=8192 count=1 70 | stm8flash -c stlinkv2 -p $(MCU) -s flash -w empty.bin 71 | 72 | .PHONY: clean all flash size dump-opt dump-flash erase 73 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # stm8-bootloader 2 | Serial bootloader for STM8S and STM8L microcontrollers. A detailed write-up on this bootloader is posted [here](https://lujji.github.io/blog/serial-bootloader-for-stm8). 3 | 4 | I am no longer maintaining this repo - for more features check out [this fork](https://github.com/MKesenheimer/stm8-bootloader) by **MKesenheimer**. 5 | 6 | ## Features 7 | 8 | * **small** - fits in 547 bytes (SDCC v3.6.8 #9951) 9 | * **fast** - uploads 4k binary in 1 second @115200bps 10 | * **configurable** - can be adjusted for parts with different flash block size 11 | 12 | ## Configuration 13 | 14 | The default configuration targets low-density devices (STM8S003). To compile for a different target `MCU` and `FAMILY` makefile variables are adjusted accordingly. 15 | 16 | Bootloader configuration is located in `config.h`. 17 | * **BLOCK_SIZE** - flash block size according to device datasheet. This should be set to 64 for low-density devices or 128 for devices with >8k flash. 18 | * **BOOT_ADDR** - application boot address. 19 | * **BOOT_PIN** - entry jumper. This is set to PD3 by default. 20 | * **RELOCATE_IVT** - when set to 1 (default) the interrupt vectors are relocated. When set to 0 the bootloader will overwrite it's own interrupt vector table with the application's IVT, thus eliminating additional CPU overhead during interrupts. Write-protection cannot be used in this case and resulting binary is slightly larger. 21 | 22 | ### Changing boot address 23 | Boot address must be a multiple of BLOCK_SIZE. Address is set in 2 places: 24 | * config.h 25 | * init.s 26 | 27 | Main application is compiled with `--code-loc
` option. When RELOCATE_IVT is set to 0, 0x80 must be subtracted from application address and isr29 must be implemented: `void dummy_isr() __interrupt(29) __naked { ; }`. 28 | 29 | ## Build instructions 30 | Build and flash the bootloader: 31 | 32 | ``` bash 33 | $ make && make flash 34 | ``` 35 | 36 | Enable write-protection (UBC) on pages 0-9 _(TODO: must be adjusted for STML)_: 37 | 38 | ``` bash 39 | $ make opt-set 40 | ``` 41 | 42 | ## Uploading the firmware 43 | 44 | There is a demo application inside `app` directory which toggles PD4 via interrupts. To upload the application short PD3 to ground, power-cycle the MCU and run the uploader utility. DTR pin on UART-USB converter can be connected to RESET pin on STM8 for automatic reset. 45 | 46 | ``` bash 47 | $ cd app && make 48 | $ python ../uploader/boot.py -p /dev/ttyUSB0 firmware.bin 49 | ``` 50 | -------------------------------------------------------------------------------- /uploader/boot.py: -------------------------------------------------------------------------------- 1 | import serial, os, math, argparse 2 | from time import sleep 3 | 4 | BLOCK_SIZE = 64 # 128 for parts with >8k flash 5 | 6 | REQ_ENTER = (0xde, 0xad, 0xbe, 0xef) 7 | ACK = (0xaa, 0xbb) 8 | NACK = (0xde, 0xad) 9 | FILE = None 10 | 11 | def crc8_update(data, crc): 12 | crc ^= data 13 | for i in range(0, 8): 14 | if crc & 0x80 != 0: 15 | crc = (crc << 1) ^ 0x07 16 | else: 17 | crc <<= 1 18 | return crc & 0xFF 19 | 20 | def get_crc(): 21 | crc = 0 22 | data = open(FILE, 'rb') 23 | with data as f: 24 | chunk = bytearray(f.read(BLOCK_SIZE)) 25 | while chunk: 26 | chunk.extend([0xFF] * (BLOCK_SIZE - len(chunk))) 27 | for i in chunk: 28 | crc = crc8_update(i, crc) 29 | chunk = bytearray(f.read(BLOCK_SIZE)) 30 | return crc 31 | 32 | def bootloader_enter(ser): 33 | # toggle reset via DTR 34 | ser.setDTR(True) 35 | sleep(0.1) 36 | ser.setDTR(False) 37 | # send payload 38 | req = bytearray(REQ_ENTER) 39 | chunks = os.path.getsize(FILE) 40 | chunks = int(math.ceil(float(chunks) / BLOCK_SIZE)) 41 | print('Need to send %s chunks' % chunks) 42 | crc = get_crc() 43 | req.extend([chunks, crc, crc]) 44 | ser.write(req) 45 | ser.flushOutput() 46 | return ser 47 | 48 | def bootloader_exec(port, baud): 49 | ser = serial.Serial(port, 115200, timeout=1.0) 50 | bootloader_enter(ser) 51 | data = open(FILE, 'rb') 52 | total = 0 53 | with data as f: 54 | chunk = bytearray(f.read(BLOCK_SIZE)) 55 | while chunk: 56 | rx = ser.read(2) 57 | if len(rx) != 2: 58 | print('Timeout') 59 | return 60 | total += len(chunk) 61 | print(total) 62 | chunk.extend([0xFF] * (BLOCK_SIZE - len(chunk))) 63 | ser.write(chunk) 64 | ser.flushOutput() 65 | chunk = bytearray(f.read(BLOCK_SIZE)) 66 | ack = ser.read(2) 67 | if ack == bytearray(ACK): 68 | print('Done') 69 | elif ack == bytearray(NACK): 70 | print('CRC mismatch') 71 | else: 72 | print('Invalid response') 73 | ser.close() 74 | 75 | if __name__ == "__main__": 76 | parser = argparse.ArgumentParser(description='stm8-bootloader update utility') 77 | parser.add_argument('--port', '-p', default='/dev/ttyUSB0') 78 | parser.add_argument('--baud', '-b', default=115200) 79 | parser.add_argument('file', help='firmware in binary format') 80 | args = parser.parse_args() 81 | FILE = args.file 82 | bootloader_exec(args.port, args.baud) 83 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "config.h" 3 | #include "stm8.h" 4 | #include "ram.h" 5 | 6 | static uint8_t CRC; 7 | static uint8_t ivt[128]; 8 | static uint8_t f_ram[128]; 9 | static uint8_t rx_buffer[BLOCK_SIZE]; 10 | static volatile uint8_t RAM_SEG_LEN; 11 | static void (*flash_write_block)(uint16_t addr, const uint8_t *buf) = 12 | (void (*)(uint16_t, const uint8_t *)) f_ram; 13 | 14 | /** 15 | * Write RAM_SEG section length into RAM_SEG_LEN 16 | */ 17 | inline void get_ram_section_length() { 18 | __asm__("mov _RAM_SEG_LEN, #l_RAM_SEG"); 19 | } 20 | 21 | /** 22 | * Initialize watchdog: 23 | * prescaler = 32, timeout = 63.70ms 24 | */ 25 | inline void iwdg_init() { 26 | IWDG_KR = IWDG_KEY_ENABLE; 27 | IWDG_KR = IWDG_KEY_ACCESS; 28 | IWDG_PR = 2; 29 | IWDG_KR = IWDG_KEY_REFRESH; 30 | } 31 | 32 | /** 33 | * Kick the dog 34 | */ 35 | inline void iwdg_refresh() { 36 | IWDG_KR = IWDG_KEY_REFRESH; 37 | } 38 | 39 | /** 40 | * Initialize UART1 in 8N1 mode 41 | */ 42 | inline void uart_init() { 43 | /* enable UART clock (STM8L only)*/ 44 | UART_CLK_ENABLE(); 45 | /* madness.. */ 46 | UART_BRR2 = ((UART_DIV >> 8) & 0xF0) + (UART_DIV & 0x0F); 47 | UART_BRR1 = UART_DIV >> 4; 48 | /* enable transmitter and receiver */ 49 | UART_CR2 = (1 << UART_CR2_TEN) | (1 << UART_CR2_REN); 50 | } 51 | 52 | /** 53 | * Write byte into UART 54 | */ 55 | static void uart_write(uint8_t data) { 56 | UART_DR = data; 57 | while (!(UART_SR & (1 << UART_SR_TC))); 58 | } 59 | 60 | /** 61 | * Read byte from UART and reset watchdog 62 | */ 63 | static uint8_t uart_read() { 64 | iwdg_refresh(); 65 | while (!(UART_SR & (1 << UART_SR_RXNE))); 66 | return UART_DR; 67 | } 68 | 69 | /** 70 | * Calculate CRC-8-CCIT. 71 | * Polynomial: x^8 + x^2 + x + 1 (0x07) 72 | * 73 | * @param data input byte 74 | * @param crc initial CRC 75 | * @return CRC value 76 | */ 77 | inline uint8_t crc8_update(uint8_t data, uint8_t crc) { 78 | crc ^= data; 79 | for (uint8_t i = 0; i < 8; i++) 80 | crc = (crc & 0x80) ? (crc << 1) ^ 0x07 : crc << 1; 81 | return crc; 82 | } 83 | 84 | /** 85 | * Send ACK response 86 | */ 87 | static void serial_send_ack() { 88 | uart_write(0xAA); 89 | uart_write(0xBB); 90 | } 91 | 92 | /** 93 | * Send NACK response (CRC mismatch) 94 | */ 95 | inline void serial_send_nack() { 96 | uart_write(0xDE); 97 | uart_write(0xAD); 98 | } 99 | 100 | /** 101 | * Read BLOCK_SIZE bytes from UART 102 | * 103 | * @param dest destination buffer 104 | */ 105 | static void serial_read_block(uint8_t *dest) { 106 | serial_send_ack(); 107 | for (uint8_t i = 0; i < BLOCK_SIZE; i++) { 108 | uint8_t rx = uart_read(); 109 | dest[i] = rx; 110 | CRC = crc8_update(rx, CRC); 111 | } 112 | } 113 | 114 | /** 115 | * Enter bootloader and perform firmware update 116 | */ 117 | inline void bootloader_exec() { 118 | uint8_t chunks, crc_rx; 119 | uint16_t addr = BOOT_ADDR; 120 | 121 | /* enter bootloader */ 122 | for (;;) { 123 | uint8_t rx = uart_read(); 124 | if (rx != 0xDE) continue; 125 | rx = uart_read(); 126 | if (rx != 0xAD) continue; 127 | rx = uart_read(); 128 | if (rx != 0xBE) continue; 129 | rx = uart_read(); 130 | if (rx != 0xEF) continue; 131 | chunks = uart_read(); 132 | crc_rx = uart_read(); 133 | rx = uart_read(); 134 | if (crc_rx != rx) 135 | continue; 136 | break; 137 | } 138 | 139 | #if !RELOCATE_IVT 140 | /* get application interrupt table */ 141 | serial_read_block(ivt); 142 | chunks--; 143 | #if BLOCK_SIZE == 64 144 | chunks--; 145 | serial_read_block(ivt + BLOCK_SIZE); 146 | #endif 147 | #endif 148 | 149 | /* unlock flash */ 150 | FLASH_PUKR = FLASH_PUKR_KEY1; 151 | FLASH_PUKR = FLASH_PUKR_KEY2; 152 | while (!(FLASH_IAPSR & (1 << FLASH_IAPSR_PUL))); 153 | 154 | /* get main firmware */ 155 | for (uint8_t i = 0; i < chunks; i++) { 156 | serial_read_block(rx_buffer); 157 | flash_write_block(addr, rx_buffer); 158 | addr += BLOCK_SIZE; 159 | } 160 | 161 | /* verify CRC */ 162 | if (CRC != crc_rx) { 163 | serial_send_nack(); 164 | for (;;) ; 165 | } 166 | 167 | #if !RELOCATE_IVT 168 | /* overwrite vector table preserving the reset interrupt */ 169 | *(uint32_t *) ivt = *(uint32_t *) (0x8000); 170 | flash_write_block(0x8000, ivt); 171 | #if BLOCK_SIZE == 64 172 | flash_write_block(0x8000 + BLOCK_SIZE, ivt + BLOCK_SIZE); 173 | #endif 174 | #endif 175 | 176 | /* lock flash */ 177 | FLASH_IAPSR &= ~(1 << FLASH_IAPSR_PUL); 178 | 179 | serial_send_ack(); 180 | 181 | /* reboot */ 182 | for (;;) ; 183 | } 184 | 185 | /** 186 | * Copy ram_flash_write_block routine into RAM 187 | */ 188 | inline void ram_cpy() { 189 | get_ram_section_length(); 190 | for (uint8_t i = 0; i < RAM_SEG_LEN; i++) 191 | f_ram[i] = ((uint8_t *) ram_flash_write_block)[i]; 192 | } 193 | 194 | void bootloader_main() { 195 | BOOT_PIN_CR1 = 1 << BOOT_PIN; 196 | if (!(BOOT_PIN_IDR & (1 << BOOT_PIN))) { 197 | /* execute bootloader */ 198 | CLK_CKDIVR = 0; 199 | ram_cpy(); 200 | iwdg_init(); 201 | uart_init(); 202 | bootloader_exec(); 203 | } else { 204 | /* jump to application */ 205 | BOOT_PIN_CR1 = 0x00; 206 | BOOT(); 207 | } 208 | } 209 | -------------------------------------------------------------------------------- /stm8s.h: -------------------------------------------------------------------------------- 1 | #ifndef STM8S_H 2 | #define STM8S_H 3 | 4 | #include 5 | 6 | #define _MEM_(mem_addr) (*(volatile uint8_t *)(mem_addr)) 7 | #define _SFR_(mem_addr) (*(volatile uint8_t *)(0x5000 + (mem_addr))) 8 | #define _SFR16_(mem_addr) (*(volatile uint16_t *)(0x5000 + (mem_addr))) 9 | 10 | /* PORT A */ 11 | #define PA_ODR _SFR_(0x00) 12 | #define PA_IDR _SFR_(0x01) 13 | #define PA_DDR _SFR_(0x02) 14 | #define PA_CR1 _SFR_(0x03) 15 | #define PA_CR2 _SFR_(0x04) 16 | 17 | /* PORT B */ 18 | #define PB_ODR _SFR_(0x05) 19 | #define PB_IDR _SFR_(0x06) 20 | #define PB_DDR _SFR_(0x07) 21 | #define PB_CR1 _SFR_(0x08) 22 | #define PB_CR2 _SFR_(0x09) 23 | 24 | /* PORT C */ 25 | #define PC_ODR _SFR_(0x0A) 26 | #define PC_IDR _SFR_(0x0B) 27 | #define PC_DDR _SFR_(0x0C) 28 | #define PC_CR1 _SFR_(0x0D) 29 | #define PC_CR2 _SFR_(0x0E) 30 | 31 | /* PORT D */ 32 | #define PD_ODR _SFR_(0x0F) 33 | #define PD_IDR _SFR_(0x10) 34 | #define PD_DDR _SFR_(0x11) 35 | #define PD_CR1 _SFR_(0x12) 36 | #define PD_CR2 _SFR_(0x13) 37 | 38 | /* PORT E */ 39 | #define PE_ODR _SFR_(0x14) 40 | #define PE_IDR _SFR_(0x15) 41 | #define PE_DDR _SFR_(0x16) 42 | #define PE_CR1 _SFR_(0x17) 43 | #define PE_CR2 _SFR_(0x18) 44 | 45 | /* PORT F */ 46 | #define PF_ODR _SFR_(0x19) 47 | #define PF_IDR _SFR_(0x1A) 48 | #define PF_DDR _SFR_(0x1B) 49 | #define PF_CR1 _SFR_(0x1C) 50 | #define PF_CR2 _SFR_(0x1D) 51 | 52 | /* Flash */ 53 | #define FLASH_CR1 _SFR_(0x5A) 54 | #define FLASH_CR1_HALT 3 55 | #define FLASH_CR1_AHALT 2 56 | #define FLASH_CR1_IE 1 57 | #define FLASH_CR1_FIX 0 58 | #define FLASH_CR2 _SFR_(0x5B) 59 | #define FLASH_CR2_OPT 7 60 | #define FLASH_CR2_WPRG 6 61 | #define FLASH_CR2_ERASE 5 62 | #define FLASH_CR2_FPRG 4 63 | #define FLASH_CR2_PRG 0 64 | #define FLASH_NCR2 _SFR_(0x5C) 65 | #define FLASH_NCR2_NOPT 7 66 | #define FLASH_NCR2_NWPRG 6 67 | #define FLASH_NCR2_NERASE 5 68 | #define FLASH_NCR2_NFPRG 4 69 | #define FLASH_NCR2_NPRG 0 70 | #define FLASH_FPR _SFR_(0x5D) 71 | #define FLASH_NFPR _SFR_(0x5E) 72 | #define FLASH_IAPSR _SFR_(0x5F) 73 | #define FLASH_IAPSR_DUL 3 74 | #define FLASH_IAPSR_EOP 2 75 | #define FLASH_IAPSR_PUL 1 76 | #define FLASH_PUKR _SFR_(0x62) 77 | #define FLASH_PUKR_KEY1 0x56 78 | #define FLASH_PUKR_KEY2 0xAE 79 | #define FLASH_DUKR _SFR_(0x64) 80 | #define FLASH_DUKR_KEY1 FLASH_PUKR_KEY2 81 | #define FLASH_DUKR_KEY2 FLASH_PUKR_KEY1 82 | 83 | /* ITC */ 84 | #define EXTI_CR1 _SFR_(0xA0) 85 | #define EXTI_CR2 _SFR_(0xA1) 86 | 87 | /* RST */ 88 | #define RST_SR _SFR_(0xB3) 89 | 90 | /* Clock */ 91 | #define CLK_ICKR _SFR_(0xC0) 92 | #define CLK_ECKR _SFR_(0xC1) 93 | #define CLK_ECKR_HSERDY 1 94 | #define CLK_ECKR_HSEEN 0 95 | #define CLK_CMSR _SFR_(0xC3) 96 | #define CLK_SWR _SFR_(0xC4) 97 | #define CLK_SWCR _SFR_(0xC5) 98 | #define CLK_SWCR_SWIF 3 99 | #define CLK_SWCR_SWIEN 2 100 | #define CLK_SWCR_SWEN 1 101 | #define CLK_SWCR_SWBSY 0 102 | #define CLK_CKDIVR _SFR_(0xC6) 103 | #define CLK_PCKENR1 _SFR_(0xC7) 104 | #define CLK_CSSR _SFR_(0xC8) 105 | #define CLK_CCOR _SFR_(0xC9) 106 | #define CLK_CCOR_CCOEN 0 107 | #define CLK_PCKENR2 _SFR_(0xCA) 108 | #define CLK_HSITRIMR _SFR_(0xCC) 109 | #define CLK_SWIMCCR _SFR_(0xCD) 110 | 111 | /* Watchdog */ 112 | #define WWDG_CR _SFR_(0xD1) 113 | #define WWDG_WR _SFR_(0xD2) 114 | #define IWDG_KR _SFR_(0xE0) 115 | #define IWDG_KEY_ENABLE 0xCC 116 | #define IWDG_KEY_REFRESH 0xAA 117 | #define IWDG_KEY_ACCESS 0x55 118 | #define IWDG_PR _SFR_(0xE1) 119 | #define IWDG_RLR _SFR_(0xE2) 120 | 121 | /* SPI */ 122 | #define SPI_CR1 _SFR_(0x200) 123 | #define SPI_CR1_LSBFIRST 7 124 | #define SPI_CR1_SPE 6 125 | #define SPI_CR1_BR2 5 126 | #define SPI_CR1_BR1 4 127 | #define SPI_CR1_BR0 3 128 | #define SPI_CR1_MSTR 2 129 | #define SPI_CR1_CPOL 1 130 | #define SPI_CR1_CPHA 0 131 | #define SPI_CR2 _SFR_(0x201) 132 | #define SPI_CR2_BDM 7 133 | #define SPI_CR2_BDOE 6 134 | #define SPI_CR2_CRCEN 5 135 | #define SPI_CR2_CRCNEXT 4 136 | #define SPI_CR2_RXONLY 2 137 | #define SPI_CR2_SSM 1 138 | #define SPI_CR2_SSI 0 139 | #define SPI_ICR _SFR_(0x202) 140 | #define SPI_SR _SFR_(0x203) 141 | #define SPI_SR_BSY 7 142 | #define SPI_SR_OVR 6 143 | #define SPI_SR_MODF 5 144 | #define SPI_SR_CRCERR 4 145 | #define SPI_SR_WKUP 3 146 | #define SPI_SR_TXE 1 147 | #define SPI_SR_RXNE 0 148 | #define SPI_DR _SFR_(0x204) 149 | #define SPI_CRCPR _SFR_(0x205) 150 | #define SPI_RXCRCR _SFR_(0x206) 151 | #define SPI_TXCRCR _SFR_(0x207) 152 | 153 | /* I2C */ 154 | #define I2C_CR1 _SFR_(0x210) 155 | #define I2C_CR1_PE 0 156 | #define I2C_CR2 _SFR_(0x211) 157 | #define I2C_CR2_ACK 2 158 | #define I2C_CR2_STOP 1 159 | #define I2C_CR2_START 0 160 | #define I2C_FREQR _SFR_(0x212) 161 | #define I2C_FREQR_FREQ2 2 162 | #define I2C_FREQR_FREQ1 1 163 | #define I2C_FREQR_FREQ0 0 164 | #define I2C_OARL _SFR_(0x213) 165 | #define I2C_OARH _SFR_(0x214) 166 | #define I2C_OARH_ADDMODE 7 167 | #define I2C_OARH_ADDCONF 6 168 | #define I2C_DR _SFR_(0x216) 169 | #define I2C_SR1 _SFR_(0x217) 170 | #define I2C_SR1_TXE 7 171 | #define I2C_SR1_RXNE 6 172 | #define I2C_SR1_BTF 2 173 | #define I2C_SR1_ADDR 1 174 | #define I2C_SR1_SB 0 175 | #define I2C_SR2 _SFR_(0x218) 176 | #define I2C_SR3 _SFR_(0x219) 177 | #define I2C_SR3_BUSY 1 178 | #define I2C_SR3_MSL 0 179 | #define I2C_ITR _SFR_(0x21A) 180 | #define I2C_CCRL _SFR_(0x21B) 181 | #define I2C_CCRH _SFR_(0x21C) 182 | #define I2C_TRISER _SFR_(0x21D) 183 | #define I2C_PECR _SFR_(0x21E) 184 | 185 | /* UART1 */ 186 | #define UART1_SR _SFR_(0x230) 187 | #define UART1_SR_TXE 7 188 | #define UART1_SR_TC 6 189 | #define UART1_SR_RXNE 5 190 | #define UART1_DR _SFR_(0x231) 191 | #define UART1_BRR1 _SFR_(0x232) 192 | #define UART1_BRR2 _SFR_(0x233) 193 | #define UART1_CR1 _SFR_(0x234) 194 | #define UART1_CR2 _SFR_(0x235) 195 | #define UART1_CR2_TEN 3 196 | #define UART1_CR2_REN 2 197 | #define UART1_CR3 _SFR_(0x236) 198 | #define UART1_CR4 _SFR_(0x237) 199 | #define UART1_CR5 _SFR_(0x238) 200 | #define UART1_GTR _SFR_(0x239) 201 | #define UART1_PSCR _SFR_(0x23A) 202 | 203 | /* UART2 */ 204 | #define UART2_SR _SFR_(0x240) 205 | #define UART2_SR_TXE 7 206 | #define UART2_SR_TC 6 207 | #define UART2_SR_RXNE 5 208 | #define UART2_DR _SFR_(0x241) 209 | #define UART2_BRR1 _SFR_(0x242) 210 | #define UART2_BRR2 _SFR_(0x243) 211 | #define UART2_CR1 _SFR_(0x244) 212 | #define UART2_CR2 _SFR_(0x245) 213 | #define UART2_CR2_TEN 3 214 | #define UART2_CR2_REN 2 215 | #define UART2_CR3 _SFR_(0x246) 216 | #define UART2_CR4 _SFR_(0x247) 217 | #define UART2_CR5 _SFR_(0x248) 218 | #define UART2_CR6 _SFR_(0x249) 219 | #define UART2_GTR _SFR_(0x24A) 220 | #define UART2_PSCR _SFR_(0x24B) 221 | 222 | /* TIM2 */ 223 | #define TIM2_CR1 _SFR_(0x300) 224 | #define TIM2_CR1_ARPE 7 225 | #define TIM2_CR1_OPM 3 226 | #define TIM2_CR1_URS 2 227 | #define TIM2_CR1_UDIS 1 228 | #define TIM2_CR1_CEN 0 229 | #define TIM2_IER _SFR_(0x303) 230 | #define TIM2_SR1 _SFR_(0x304) 231 | #define TIM2_SR2 _SFR_(0x305) 232 | #define TIM2_EGR _SFR_(0x306) 233 | #define TIM2_EGR_TG 6 234 | #define TIM2_EGR_CC3G 3 235 | #define TIM2_EGR_CC2G 2 236 | #define TIM2_EGR_CC1G 1 237 | #define TIM2_EGR_UG 0 238 | #define TIM2_CCMR1 _SFR_(0x307) 239 | #define TIM2_CCMR2 _SFR_(0x308) 240 | #define TIM2_CCMR3 _SFR_(0x309) 241 | #define TIM2_CCER1 _SFR_(0x30A) 242 | #define TIM2_CCER2 _SFR_(0x30B) 243 | #define TIM2_CNTR _SFR16_(0x30C) 244 | #define TIM2_CNTRH _SFR_(0x30C) 245 | #define TIM2_CNTRL _SFR_(0x30D) 246 | #define TIM2_PSCR _SFR_(0x30E) 247 | #define TIM2_ARR _SFR16_(0x30F) 248 | #define TIM2_ARRH _SFR_(0x30F) 249 | #define TIM2_ARRL _SFR_(0x310) 250 | #define TIM2_CCR1H _SFR_(0x311) 251 | #define TIM2_CCR1L _SFR_(0x312) 252 | #define TIM2_CCR2H _SFR_(0x313) 253 | #define TIM2_CCR2L _SFR_(0x314) 254 | #define TIM2_CCR3H _SFR_(0x315) 255 | #define TIM2_CCR3L _SFR_(0x316) 256 | 257 | /* TIM4 */ 258 | #define TIM4_CR1 _SFR_(0x340) 259 | #define TIM4_CR1_ARPE 7 260 | #define TIM4_CR1_OPM 3 261 | #define TIM4_CR1_URS 2 262 | #define TIM4_CR1_UDIS 1 263 | #define TIM4_CR1_CEN 0 264 | #define TIM4_IER _SFR_(0x343) 265 | #define TIM4_IER_UIE 0 266 | #define TIM4_SR _SFR_(0x344) 267 | #define TIM4_SR_UIF 0 268 | #define TIM4_EGR _SFR_(0x345) 269 | #define TIM4_CNTR _SFR_(0x346) 270 | #define TIM4_PSCR _SFR_(0x347) 271 | #define TIM4_ARR _SFR_(0x348) 272 | 273 | /* ADC1 */ 274 | #define ADC1_DB0R _SFR_(0x3E0) 275 | #define ADC1_CSR _SFR_(0x400) 276 | #define ADC1_CSR_EOC 7 277 | #define ADC1_CSR_AWD 6 278 | #define ADC1_CSR_EOCIE 5 279 | #define ADC1_CSR_CH3 3 280 | #define ADC1_CSR_CH2 2 281 | #define ADC1_CSR_CH1 1 282 | #define ADC1_CSR_CH0 0 283 | #define ADC1_CR1 _SFR_(0x401) 284 | #define ADC1_CR1_SPSEL2 6 285 | #define ADC1_CR1_SPSEL1 5 286 | #define ADC1_CR1_SPSEL0 4 287 | #define ADC1_CR1_CONT 1 288 | #define ADC1_CR1_ADON 0 289 | #define ADC1_CR2 _SFR_(0x402) 290 | #define ADC1_CR2_EXTTRIG 6 291 | #define ADC1_CR2_EXTSEL1 5 292 | #define ADC1_CR2_EXTSEL0 4 293 | #define ADC1_CR2_ALIGN 3 294 | #define ADC1_CR2_SCAN 1 295 | #define ADC1_CR3 _SFR_(0x403) 296 | #define ADC1_CR3_DBUF 7 297 | #define ADC1_CR3_OVR 6 298 | #define ADC1_DRH _SFR_(0x404) 299 | #define ADC1_DRL _SFR_(0x405) 300 | #define ADC1_TDRH _SFR_(0x406) 301 | #define ADC1_TDRL _SFR_(0x407) 302 | #define ADC1_HTRH _SFR_(0x408) 303 | #define ADC1_HTRL _SFR_(0x409) 304 | #define ADC1_LTRH _SFR_(0x40A) 305 | #define ADC1_LTRL _SFR_(0x40B) 306 | #define ADC1_AWSRH _SFR_(0x40C) 307 | #define ADC1_AWSRL _SFR_(0x40D) 308 | #define ADC1_AWCRH _SFR_(0x40E) 309 | #define ADC1_AWCRL _SFR_(0x40F) 310 | 311 | /* Interrupts */ 312 | #define TLI_ISR 0 313 | #define AWU_ISR 1 314 | #define CLK_ISR 2 315 | #define EXTI0_ISR 3 316 | #define EXTI1_ISR 4 317 | #define EXTI2_ISR 5 318 | #define EXTI3_ISR 6 319 | #define EXTI4_ISR 7 320 | #define SPI_ISR 10 321 | #define TIM1_OVF_ISR 11 322 | #define TIM1_CC_ISR 12 323 | #define TIM2_OVF_ISR 13 324 | #define TIM2_CC_ISR 14 325 | #define UART1_TXC_ISR 17 326 | #define UART1_RXC_ISR 18 327 | #define I2C_ISR 19 328 | #define ADC1_ISR 22 329 | #define TIM4_ISR 23 330 | #define FLASH_ISR 24 331 | 332 | /* CPU */ 333 | #define CPU_CCR _MEM_(0x7F0A) 334 | 335 | #define enable_interrupts() __asm__("rim"); 336 | #define disable_interrupts() __asm__("sim"); 337 | 338 | #endif /* STM8S_H */ 339 | -------------------------------------------------------------------------------- /stm8l.h: -------------------------------------------------------------------------------- 1 | #ifndef STM8L_H 2 | #define STM8L_H 3 | 4 | #include 5 | 6 | #define _MEM_(mem_addr) (*(volatile uint8_t *)(mem_addr)) 7 | #define _SFR_(mem_addr) (*(volatile uint8_t *)(0x5000 + (mem_addr))) 8 | #define _SFR16_(mem_addr) (*(volatile uint16_t *)(0x5000 + (mem_addr))) 9 | 10 | /* PORT A */ 11 | #define PA_ODR _SFR_(0x00) 12 | #define PA_IDR _SFR_(0x01) 13 | #define PA_DDR _SFR_(0x02) 14 | #define PA_CR1 _SFR_(0x03) 15 | #define PA_CR2 _SFR_(0x04) 16 | 17 | /* PORT B */ 18 | #define PB_ODR _SFR_(0x05) 19 | #define PB_IDR _SFR_(0x06) 20 | #define PB_DDR _SFR_(0x07) 21 | #define PB_CR1 _SFR_(0x08) 22 | #define PB_CR2 _SFR_(0x09) 23 | 24 | /* PORT C */ 25 | #define PC_ODR _SFR_(0x0A) 26 | #define PC_IDR _SFR_(0x0B) 27 | #define PC_DDR _SFR_(0x0C) 28 | #define PC_CR1 _SFR_(0x0D) 29 | #define PC_CR2 _SFR_(0x0E) 30 | 31 | /* PORT D */ 32 | #define PD_ODR _SFR_(0x0F) 33 | #define PD_IDR _SFR_(0x10) 34 | #define PD_DDR _SFR_(0x11) 35 | #define PD_CR1 _SFR_(0x12) 36 | #define PD_CR2 _SFR_(0x13) 37 | 38 | /* PORT E */ 39 | #define PE_ODR _SFR_(0x14) 40 | #define PE_IDR _SFR_(0x15) 41 | #define PE_DDR _SFR_(0x16) 42 | #define PE_CR1 _SFR_(0x17) 43 | #define PE_CR2 _SFR_(0x18) 44 | 45 | /* PORT F */ 46 | #define PF_ODR _SFR_(0x19) 47 | #define PF_IDR _SFR_(0x1A) 48 | #define PF_DDR _SFR_(0x1B) 49 | #define PF_CR1 _SFR_(0x1C) 50 | #define PF_CR2 _SFR_(0x1D) 51 | 52 | /* Flash */ 53 | #define FLASH_CR1 _SFR_(0x50) 54 | #define FLASH_CR1_EEPM 3 55 | #define FLASH_CR1_WAITM 2 56 | #define FLASH_CR1_IE 1 57 | #define FLASH_CR1_FIX 0 58 | #define FLASH_CR2 _SFR_(0x51) 59 | #define FLASH_CR2_OPT 7 60 | #define FLASH_CR2_WPRG 6 61 | #define FLASH_CR2_ERASE 5 62 | #define FLASH_CR2_FPRG 4 63 | #define FLASH_CR2_PRG 0 64 | #define FLASH_PUKR _SFR_(0x52) 65 | #define FLASH_PUKR_KEY1 0x56 66 | #define FLASH_PUKR_KEY2 0xAE 67 | #define FLASH_DUKR _SFR_(0x53) 68 | #define FLASH_DUKR_KEY1 FLASH_PUKR_KEY2 69 | #define FLASH_DUKR_KEY2 FLASH_PUKR_KEY1 70 | #define FLASH_IAPSR _SFR_(0x54) 71 | #define FLASH_IAPSR_HVOFF 6 72 | #define FLASH_IAPSR_DUL 3 73 | #define FLASH_IAPSR_EOP 2 74 | #define FLASH_IAPSR_PUL 1 75 | #define FLASH_IAPSR_WR_PG_DIS 0 76 | 77 | /* DMA1 */ 78 | #define DMA1_GCSR _SFR_(0x70) 79 | #define DMA1_GIR1 _SFR_(0x71) 80 | #define DMA1_C0CR _SFR_(0x75) 81 | #define DMA1_C0SPR _SFR_(0x76) 82 | #define DMA1_C0NDTR _SFR_(0x77) 83 | #define DMA1_C0PARH _SFR_(0x78) 84 | #define DMA1_C0PARL _SFR_(0x79) 85 | #define DMA1_C0M0ARH _SFR_(0x7B) 86 | #define DMA1_C0M0ARL _SFR_(0x7C) 87 | #define DMA1_C1CR _SFR_(0x7F) 88 | #define DMA1_C1SPR _SFR_(0x80) 89 | #define DMA1_C1NDTR _SFR_(0x81) 90 | #define DMA1_C1PARH _SFR_(0x82) 91 | #define DMA1_C1PARL _SFR_(0x83) 92 | #define DMA1_C1M0ARH _SFR_(0x85) 93 | #define DMA1_C1M0ARL _SFR_(0x86) 94 | #define DMA1_C2CR _SFR_(0x89) 95 | #define DMA1_C2SPR _SFR_(0x8A) 96 | #define DMA1_C2NDTR _SFR_(0x8B) 97 | #define DMA1_C2PARH _SFR_(0x8C) 98 | #define DMA1_C2PARL _SFR_(0x8D) 99 | #define DMA1_C2M0ARH _SFR_(0x8F) 100 | #define DMA1_C2M0ARL _SFR_(0x90) 101 | #define DMA1_C3CR _SFR_(0x93) 102 | #define DMA1_C3SPR _SFR_(0x94) 103 | #define DMA1_C3NDTR _SFR_(0x95) 104 | #define DMA1_C3PARH_C3M1ARH _SFR_(0x96) 105 | #define DMA1_C3PARL_C3M1ARL _SFR_(0x97) 106 | #define DMA1_C3M0EAR _SFR_(0x98) 107 | #define DMA1_C3M0ARH _SFR_(0x99) 108 | #define DMA1_C3M0ARL _SFR_(0x9A) 109 | 110 | /* SYSCFG */ 111 | #define SYSCFG_RMPCR3 _SFR_(0x9D) 112 | #define SYSCFG_RMPCR1 _SFR_(0x9E) 113 | #define SYSCFG_RMPCR1_SPI1_REMAP 7 114 | #define SYSCFG_RMPCR1_USART1CK_REMAP 6 115 | #define SYSCFG_RMPCR1_USART1TR_REMAP1 5 116 | #define SYSCFG_RMPCR1_USART1TR_REMAP0 4 117 | #define SYSCFG_RMPCR1_TIM4DMA_REMAP1 3 118 | #define SYSCFG_RMPCR1_TIM4DMA_REMAP0 2 119 | #define SYSCFG_RMPCR1_ADC1DMA_REAMP1 1 120 | #define SYSCFG_RMPCR1_ADC1DMA_REAMP0 0 121 | #define SYSCFG_RMPCR2 _SFR_(0x9F) 122 | 123 | /* ITC */ 124 | #define EXTI_CR1 _SFR_(0xA0) 125 | #define EXTI_CR2 _SFR_(0xA1) 126 | #define EXTI_CR3 _SFR_(0xA2) 127 | #define EXTI_SR1 _SFR_(0xA3) 128 | #define EXTI_SR2 _SFR_(0xA4) 129 | #define EXTI_CONF1 _SFR_(0xA5) 130 | #define WFE_CR1 _SFR_(0xA6) 131 | #define WFE_CR1_EXTI_EV3 7 132 | #define WFE_CR1_EXTI_EV2 6 133 | #define WFE_CR1_EXTI_EV1 5 134 | #define WFE_CR1_EXTI_EV0 4 135 | #define WFE_CR1_TIM1_EV1 3 136 | #define WFE_CR1_TIM1_EV0 2 137 | #define WFE_CR1_TIM2_EV1 1 138 | #define WFE_CR1_TIM2_EV0 0 139 | #define WFE_CR2 _SFR_(0xA7) 140 | #define WFE_CR2_ADC1_COMP_EV 7 141 | #define WFE_CR2_EXTI_EVE_F 6 142 | #define WFE_CR2_EXTI_EVD 5 143 | #define WFE_CR2_EXTI_EVB 4 144 | #define WFE_CR2_EXTI_EV7 3 145 | #define WFE_CR2_EXTI_EV6 2 146 | #define WFE_CR2_EXTI_EV5 1 147 | #define WFE_CR2_EXTI_EV4 0 148 | #define WFE_CR3 _SFR_(0xA8) 149 | #define WFE_CR3_DMA1CH23_EV 7 150 | #define WFE_CR3_DMA1CH01_EV 6 151 | #define WFE_CR3_USART1_EV 5 152 | #define WFE_CR3_I2C1_EV 4 153 | #define WFE_CR3_SPI1_EV 3 154 | #define WFE_CR3_TIM4_EV 2 155 | #define WFE_CR3_TIM3_EV1 1 156 | #define WFE_CR3_TIM3_EV0 0 157 | #define WFE_CR4 _SFR_(0xA9) 158 | #define WFE_CR4_AES_EV 6 159 | #define WFE_CR4_TIM5_EV1 5 160 | #define WFE_CR4_TIM5_EV0 4 161 | #define WFE_CR4_USART3_EV 3 162 | #define WFE_CR4_USART2_EV 2 163 | #define WFE_CR4_SPI2_EV 1 164 | #define WFE_CR4_RTC_CSSLSE_EV 0 165 | #define EXTI_CR4 _SFR_(0xAA) 166 | #define EXTI_CONF2 _SFR_(0xAB) 167 | 168 | /* RST */ 169 | #define RST_CR _SFR_(0xB0) 170 | #define RST_SR _SFR_(0xB1) 171 | #define PWR_CSR1 _SFR_(0xB2) 172 | #define PWR_CSR1_PVDOF 6 173 | #define PWR_CSR1_PVDIF 5 174 | #define PWR_CSR1_PVDIEN 4 175 | #define PWR_CSR1_PLS2 3 176 | #define PWR_CSR1_PLS1 2 177 | #define PWR_CSR1_PLS0 1 178 | #define PWR_CSR1_PVDE 0 179 | #define PWR_CSR2 _SFR_(0xB3) 180 | #define PWR_CSR2_FWU 2 181 | #define PWR_CSR2_ULP 1 182 | #define PWR_CSR2_VREFINTF 0 183 | 184 | /* Clock */ 185 | #define CLK_CKDIVR _SFR_(0xC0) 186 | #define CLK_CRTCR _SFR_(0xC1) 187 | #define CLK_CRTCR_RTCDIV2 7 188 | #define CLK_CRTCR_RTCDIV1 6 189 | #define CLK_CRTCR_RTCDIV0 5 190 | #define CLK_CRTCR_RTCSEL3 4 191 | #define CLK_CRTCR_RTCSEL2 3 192 | #define CLK_CRTCR_RTCSEL1 2 193 | #define CLK_CRTCR_RTCSEL0 1 194 | #define CLK_CRTCR_RTCSWBSY 0 195 | #define CLK_ICKCR _SFR_(0xC2) 196 | #define CLK_ICKCR_BEEPAHALT 6 197 | #define CLK_ICKCR_FHWU 5 198 | #define CLK_ICKCR_SAHALT 4 199 | #define CLK_ICKCR_LSIRDY 3 200 | #define CLK_ICKCR_LSION 2 201 | #define CLK_ICKCR_HSIRDY 1 202 | #define CLK_ICKCR_HSION 0 203 | #define CLK_PCKENR1 _SFR_(0xC3) 204 | #define CLK_PCKENR2 _SFR_(0xC4) 205 | #define CLK_CCOR _SFR_(0xC5) 206 | #define CLK_CCOR_CCODIV2 7 207 | #define CLK_CCOR_CCODIV1 6 208 | #define CLK_CCOR_CCODIV0 5 209 | #define CLK_CCOR_CCOSEL3 4 210 | #define CLK_CCOR_CCOSEL2 3 211 | #define CLK_CCOR_CCOSEL1 2 212 | #define CLK_CCOR_CCOSEL0 1 213 | #define CLK_CCOR_CCOSWBSY 0 214 | #define CLK_ECKCR _SFR_(0xC6) 215 | #define CLK_ECKCR_LSEBYP 5 216 | #define CLK_ECKCR_HSEBYP 4 217 | #define CLK_ECKCR_LSERDY 3 218 | #define CLK_ECKCR_LSEON 2 219 | #define CLK_ECKCR_HSERDY 1 220 | #define CLK_ECKCR_HSEON 0 221 | #define CLK_SCSR _SFR_(0xC7) 222 | #define CLK_SWR _SFR_(0xC8) 223 | #define CLK_SWCR _SFR_(0xC9) 224 | #define CLK_SWCR_SWIF 3 225 | #define CLK_SWCR_SWIEN 2 226 | #define CLK_SWCR_SWEN 1 227 | #define CLK_SWCR_SWBSY 0 228 | #define CLK_CSSR _SFR_(0xCA) 229 | #define CLK_CSSR_CSSDGON 4 230 | #define CLK_CSSR_CSSD 3 231 | #define CLK_CSSR_CSSDIE 2 232 | #define CLK_CSSR_AUX 1 233 | #define CLK_CSSR_CSSEN 0 234 | #define CLK_CBEEPR _SFR_(0xCB) 235 | #define CLK_CBEEPR_CLKBEEPSEL1 2 236 | #define CLK_CBEEPR_CLKBEEPSEL0 1 237 | #define CLK_CBEEPR_BEEPSWBSY 0 238 | #define CLK_HSICALR _SFR_(0xCC) 239 | #define CLK_HSITRIMR _SFR_(0xCD) 240 | #define CLK_HSIUNLCKR _SFR_(0xCE) 241 | #define CLK_REGCSR _SFR_(0xCF) 242 | #define CLK_REGCSR_EEREADY 7 243 | #define CLK_REGCSR_EEBUSY 6 244 | #define CLK_REGCSR_LSEPD 5 245 | #define CLK_REGCSR_HSEPD 4 246 | #define CLK_REGCSR_LSIPD 3 247 | #define CLK_REGCSR_HSIPD 2 248 | #define CLK_REGCSR_REGOFF 1 249 | #define CLK_REGCSR_REGREADY 0 250 | #define CLK_PCKENR3 _SFR_(0xD0) 251 | 252 | /* Watchdog */ 253 | #define WWDG_CR _SFR_(0xD3) 254 | #define WWDG_WR _SFR_(0xD4) 255 | #define IWDG_KR _SFR_(0xE0) 256 | #define IWDG_KEY_ENABLE 0xCC 257 | #define IWDG_KEY_REFRESH 0xAA 258 | #define IWDG_KEY_ACCESS 0x55 259 | #define IWDG_PR _SFR_(0xE1) 260 | #define IWDG_RLR _SFR_(0xE2) 261 | 262 | /* Beeper */ 263 | #define BEEP_CSR1 _SFR_(0xF0) 264 | #define BEEP_CSR2 _SFR_(0xF3) 265 | 266 | /* RTC */ 267 | #define RTC_TR1 _SFR_(0x140) 268 | #define RTC_TR2 _SFR_(0x141) 269 | #define RTC_TR3 _SFR_(0x142) 270 | #define RTC_DR1 _SFR_(0x144) 271 | #define RTC_DR2 _SFR_(0x145) 272 | #define RTC_DR3 _SFR_(0x146) 273 | #define RTC_CR1 _SFR_(0x148) 274 | #define RTC_CR1_FMT 6 275 | #define RTC_CR1_RATIO 4 276 | #define RTC_CR1_BYPSHAD 4 277 | #define RTC_CR1_WUCKSEL2 2 278 | #define RTC_CR1_WUCKSEL1 1 279 | #define RTC_CR1_WUCKSEL0 0 280 | #define RTC_CR2 _SFR_(0x149) 281 | #define RTC_CR2_WUTIE 6 282 | #define RTC_CR2_ALRAIE 4 283 | #define RTC_CR2_WUTE 2 284 | #define RTC_CR2_ALRAE 0 285 | #define RTC_CR3 _SFR_(0x14A) 286 | #define RTC_CR3_COE 7 287 | #define RTC_CR3_OSEL1 6 288 | #define RTC_CR3_OSEL0 5 289 | #define RTC_CR3_POL 4 290 | #define RTC_CR3_COSEL 3 291 | #define RTC_CR3_BCK 2 292 | #define RTC_CR3_SUB1H 1 293 | #define RTC_CR3_ADD1H 0 294 | #define RTC_ISR1 _SFR_(0x14C) 295 | #define RTC_ISR1_INIT 7 296 | #define RTC_ISR1_INITF 6 297 | #define RTC_ISR1_RSF 5 298 | #define RTC_ISR1_INITS 4 299 | #define RTC_ISR1_SHPF 3 300 | #define RTC_ISR1_WUTWF 2 301 | #define RTC_ISR1_RECALPF 1 302 | #define RTC_ISR1_ALRAWF 0 303 | #define RTC_ISR2 _SFR_(0x14D) 304 | #define RTC_ISR2_TAMP3F 7 305 | #define RTC_ISR2_TAMP2F 6 306 | #define RTC_ISR2_TAMP1F 5 307 | #define RTC_ISR2_WUTF 2 308 | #define RTC_ISR2_ALRAF 0 309 | #define RTC_SPRERH _SFR_(0x150) 310 | #define RTC_SPRERL _SFR_(0x151) 311 | #define RTC_APRER _SFR_(0x152) 312 | #define RTC_WUTR _SFR16_(0x154) 313 | #define RTC_WUTRH _SFR_(0x154) 314 | #define RTC_WUTRL _SFR_(0x155) 315 | #define RTC_SSRL _SFR_(0x157) 316 | #define RTC_SSRH _SFR_(0x158) 317 | #define RTC_WPR _SFR_(0x159) 318 | #define RTC_SSRH _SFR_(0x158) 319 | #define RTC_WPR _SFR_(0x159) 320 | #define RTC_SHIFTRH _SFR_(0x15A) 321 | #define RTC_SHIFTRL _SFR_(0x15B) 322 | #define RTC_ALRMAR1 _SFR_(0x15C) 323 | #define RTC_ALRMAR2 _SFR_(0x15D) 324 | #define RTC_ALRMAR3 _SFR_(0x15E) 325 | #define RTC_ALRMAR4 _SFR_(0x15F) 326 | #define RTC_ALRMASSRH _SFR_(0x164) 327 | #define RTC_ALRMASSRL _SFR_(0x165) 328 | #define RTC_ALRMASSMSKR _SFR_(0x166) 329 | #define RTC_CALRH _SFR_(0x16A) 330 | #define RTC_CALRL _SFR_(0x16B) 331 | #define RTC_TCR1 _SFR_(0x16C) 332 | #define RTC_TCR2 _SFR_(0x16D) 333 | 334 | #define CSSLSE_CSR _SFR_(0x190) 335 | 336 | /* SPI1 */ 337 | #define SPI1_CR1 _SFR_(0x200) 338 | #define SPI1_CR1_LSBFIRST 7 339 | #define SPI1_CR1_SPE 6 340 | #define SPI1_CR1_BR2 5 341 | #define SPI1_CR1_BR1 4 342 | #define SPI1_CR1_BR0 3 343 | #define SPI1_CR1_MSTR 2 344 | #define SPI1_CR1_CPOL 1 345 | #define SPI1_CR1_CPHA 0 346 | #define SPI1_CR2 _SFR_(0x201) 347 | #define SPI1_CR2_BDM 7 348 | #define SPI1_CR2_BDOE 6 349 | #define SPI1_CR2_CRCEN 5 350 | #define SPI1_CR2_CRCNEXT 4 351 | #define SPI1_CR2_RXONLY 2 352 | #define SPI1_CR2_SSM 1 353 | #define SPI1_CR2_SSI 0 354 | #define SPI1_ICR _SFR_(0x202) 355 | #define SPI1_SR _SFR_(0x203) 356 | #define SPI1_SR_BSY 7 357 | #define SPI1_SR_OVR 6 358 | #define SPI1_SR_MODF 5 359 | #define SPI1_SR_CRCERR 4 360 | #define SPI1_SR_WKUP 3 361 | #define SPI1_SR_TXE 1 362 | #define SPI1_SR_RXNE 0 363 | #define SPI1_DR _SFR_(0x204) 364 | #define SPI1_CRCPR _SFR_(0x205) 365 | #define SPI1_RXCRCR _SFR_(0x206) 366 | #define SPI1_TXCRCR _SFR_(0x207) 367 | 368 | /* I2C1 */ 369 | #define I2C1_CR1 _SFR_(0x210) 370 | #define I2C1_CR1_NOSTRETCH 7 371 | #define I2C1_CR1_ENGC 6 372 | #define I2C1_CR1_ENPEC 5 373 | #define I2C1_CR1_ENARP 4 374 | #define I2C1_CR1_SMBTYPE 3 375 | #define I2C1_CR1_SMBUS 1 376 | #define I2C1_CR1_PE 0 377 | #define I2C1_CR2 _SFR_(0x211) 378 | #define I2C1_CR2_SWRST 7 379 | #define I2C1_CR2_ALERT 5 380 | #define I2C1_CR2_PEC 4 381 | #define I2C1_CR2_POS 3 382 | #define I2C1_CR2_ACK 2 383 | #define I2C1_CR2_STOP 1 384 | #define I2C1_CR2_START 0 385 | #define I2C1_FREQR _SFR_(0x212) 386 | #define I2C1_FREQR_FREQ5 5 387 | #define I2C1_FREQR_FREQ4 4 388 | #define I2C1_FREQR_FREQ3 3 389 | #define I2C1_FREQR_FREQ2 2 390 | #define I2C1_FREQR_FREQ1 1 391 | #define I2C1_FREQR_FREQ0 0 392 | #define I2C1_OARL _SFR_(0x213) 393 | #define I2C1_OARH _SFR_(0x214) 394 | #define I2C1_OARH_ADDMODE 7 395 | #define I2C1_OARH_ADDCONF 6 396 | #define I2C1_OAR2 _SFR_(0x215) 397 | #define I2C1_DR _SFR_(0x216) 398 | #define I2C1_SR1 _SFR_(0x217) 399 | #define I2C1_SR1_TXE 7 400 | #define I2C1_SR1_RXNE 6 401 | #define I2C1_SR1_BTF 2 402 | #define I2C1_SR1_ADDR 1 403 | #define I2C1_SR1_SB 0 404 | #define I2C1_SR2 _SFR_(0x218) 405 | #define I2C1_SR3 _SFR_(0x219) 406 | #define I2C1_SR3_BUSY 1 407 | #define I2C1_SR3_MSL 0 408 | #define I2C1_ITR _SFR_(0x21A) 409 | #define I2C1_CCRL _SFR_(0x21B) 410 | #define I2C1_CCRH _SFR_(0x21C) 411 | #define I2C1_TRISER _SFR_(0x21D) 412 | #define I2C1_PECR _SFR_(0x21E) 413 | 414 | /* USART1 */ 415 | #define USART1_SR _SFR_(0x230) 416 | #define USART1_SR_TXE 7 417 | #define USART1_SR_TC 6 418 | #define USART1_SR_RXNE 5 419 | #define USART1_DR _SFR_(0x231) 420 | #define USART1_BRR1 _SFR_(0x232) 421 | #define USART1_BRR2 _SFR_(0x233) 422 | #define USART1_CR1 _SFR_(0x234) 423 | #define USART1_CR2 _SFR_(0x235) 424 | #define USART1_CR2_TEN 3 425 | #define USART1_CR2_REN 2 426 | #define USART1_CR3 _SFR_(0x236) 427 | #define USART1_CR4 _SFR_(0x237) 428 | #define USART1_CR5 _SFR_(0x238) 429 | #define USART1_GTR _SFR_(0x239) 430 | #define USART1_PSCR _SFR_(0x23A) 431 | 432 | /* TIM2 */ 433 | #define TIM2_CR1 _SFR_(0x250) 434 | #define TIM2_CR1_ARPE 7 435 | #define TIM2_CR1_DIR 6 436 | #define TIM2_CR1_OPM 3 437 | #define TIM2_CR1_URS 2 438 | #define TIM2_CR1_UDIS 1 439 | #define TIM2_CR1_CEN 0 440 | #define TIM2_CR2 _SFR_(0x251) 441 | #define TIM2_SMCR _SFR_(0x252) 442 | #define TIM2_ETR _SFR_(0x253) 443 | #define TIM2_DER _SFR_(0x254) 444 | #define TIM2_IER _SFR_(0x255) 445 | #define TIM2_SR1 _SFR_(0x256) 446 | #define TIM2_SR2 _SFR_(0x257) 447 | #define TIM2_EGR _SFR_(0x258) 448 | #define TIM2_EGR_BG 7 449 | #define TIM2_EGR_TG 6 450 | #define TIM2_EGR_CC2G 2 451 | #define TIM2_EGR_CC1G 1 452 | #define TIM2_EGR_UG 0 453 | #define TIM2_CCMR1 _SFR_(0x259) 454 | #define TIM2_CCMR2 _SFR_(0x25A) 455 | #define TIM2_CCER1 _SFR_(0x25B) 456 | #define TIM2_CNTR _SFR16_(0x25C) 457 | #define TIM2_CNTRH _SFR_(0x25C) 458 | #define TIM2_CNTRL _SFR_(0x25D) 459 | #define TIM2_PSCR _SFR_(0x25E) 460 | #define TIM2_ARR _SFR16_(0x25F) 461 | #define TIM2_ARRH _SFR_(0x25F) 462 | #define TIM2_ARRL _SFR_(0x260) 463 | #define TIM2_CCR1H _SFR_(0x261) 464 | #define TIM2_CCR1L _SFR_(0x262) 465 | #define TIM2_CCR2H _SFR_(0x263) 466 | #define TIM2_CCR2L _SFR_(0x264) 467 | #define TIM2_BKR _SFR_(0x265) 468 | #define TIM2_OISR _SFR_(0x266) 469 | 470 | /* TIM3 */ 471 | #define TIM3_CR1 _SFR_(0x280) 472 | #define TIM3_CR1_ARPE 7 473 | #define TIM3_CR1_CMS1 6 474 | #define TIM3_CR1_CMS0 5 475 | #define TIM3_CR1_DIR 4 476 | #define TIM3_CR1_OPM 3 477 | #define TIM3_CR1_URS 2 478 | #define TIM3_CR1_UDIS 1 479 | #define TIM3_CR1_CEN 0 480 | #define TIM3_CR2 _SFR_(0x281) 481 | #define TIM3_CR2_MMS2 6 482 | #define TIM3_CR2_MMS1 5 483 | #define TIM3_CR2_MMS0 4 484 | #define TIM3_CR2_CCDS 3 485 | #define TIM3_SMCR _SFR_(0x282) 486 | #define TIM3_ETR _SFR_(0x283) 487 | #define TIM3_DER _SFR_(0x284) 488 | #define TIM3_IER _SFR_(0x285) 489 | #define TIM3_IER_BIE 7 490 | #define TIM3_IER_TIE 6 491 | #define TIM3_IER_CC2IE 2 492 | #define TIM3_IER_CC1IE 1 493 | #define TIM3_IER_UIE 0 494 | #define TIM3_SR1 _SFR_(0x286) 495 | #define TIM3_SR1_BIF 7 496 | #define TIM3_SR1_TIF 6 497 | #define TIM3_SR1_CC2IF 2 498 | #define TIM3_SR1_CC1IF 1 499 | #define TIM3_SR1_UIF 0 500 | #define TIM3_SR2 _SFR_(0x287) 501 | #define TIM3_SR2_CC2OF 2 502 | #define TIM3_SR2_CC1OF 1 503 | #define TIM3_EGR _SFR_(0x288) 504 | #define TIM3_EGR_BG 7 505 | #define TIM3_EGR_TG 6 506 | #define TIM3_EGR_CC2G 2 507 | #define TIM3_EGR_CC1G 1 508 | #define TIM3_EGR_UG 0 509 | #define TIM3_CCMR1 _SFR_(0x289) 510 | #define TIM3_CCMR2 _SFR_(0x28A) 511 | #define TIM3_CCER1 _SFR_(0x28B) 512 | #define TIM3_CNTR _SFR16_(0x28C) 513 | #define TIM3_CNTRH _SFR_(0x28C) 514 | #define TIM3_CNTRL _SFR_(0x28D) 515 | #define TIM3_PSCR _SFR_(0x28E) 516 | #define TIM3_ARR _SFR16_(0x28F) 517 | #define TIM3_ARRH _SFR_(0x28F) 518 | #define TIM3_ARRL _SFR_(0x290) 519 | #define TIM3_CCR1H _SFR_(0x291) 520 | #define TIM3_CCR1L _SFR_(0x292) 521 | #define TIM3_CCR2H _SFR_(0x293) 522 | #define TIM3_CCR2L _SFR_(0x294) 523 | #define TIM3_BKR _SFR_(0x295) 524 | #define TIM3_OISR _SFR_(0x296) 525 | 526 | /* TIM1 */ 527 | #define TIM1_CR1 _SFR_(0x2B0) 528 | #define TIM1_CR2 _SFR_(0x2B1) 529 | #define TIM1_SMCR _SFR_(0x2B2) 530 | #define TIM1_ETR _SFR_(0x2B3) 531 | #define TIM1_DER _SFR_(0x2B4) 532 | #define TIM1_IER _SFR_(0x2B5) 533 | #define TIM1_SR1 _SFR_(0x2B6) 534 | #define TIM1_SR2 _SFR_(0x2B7) 535 | #define TIM1_EGR _SFR_(0x2B8) 536 | #define TIM1_CCMR1 _SFR_(0x2B9) 537 | #define TIM1_CCMR2 _SFR_(0x2BA) 538 | #define TIM1_CCMR3 _SFR_(0x2BB) 539 | #define TIM1_CCMR4 _SFR_(0x2BC) 540 | #define TIM1_CCER1 _SFR_(0x2BD) 541 | #define TIM1_CCER2 _SFR_(0x2BE) 542 | #define TIM1_CNTRH _SFR_(0x2BF) 543 | #define TIM1_CNTRL _SFR_(0x2C0) 544 | #define TIM1_PSCRH _SFR_(0x2C1) 545 | #define TIM1_PSCRL _SFR_(0x2C2) 546 | #define TIM1_ARRH _SFR_(0x2C3) 547 | #define TIM1_ARRL _SFR_(0x2C4) 548 | #define TIM1_RCR _SFR_(0x2C5) 549 | #define TIM1_CCR1H _SFR_(0x2C6) 550 | #define TIM1_CCR1L _SFR_(0x2C7) 551 | #define TIM1_CCR2H _SFR_(0x2C8) 552 | #define TIM1_CCR2L _SFR_(0x2C9) 553 | #define TIM1_CCR3H _SFR_(0x2CA) 554 | #define TIM1_CCR3L _SFR_(0x2CB) 555 | #define TIM1_CCR4H _SFR_(0x2CC) 556 | #define TIM1_CCR4L _SFR_(0x2CD) 557 | #define TIM1_BKR _SFR_(0x2CE) 558 | #define TIM1_DTR _SFR_(0x2CF) 559 | #define TIM1_OISR _SFR_(0x2D0) 560 | #define TIM1_DCR1 _SFR_(0x2D1) 561 | #define TIM1_DCR2 _SFR_(0x2D2) 562 | #define TIM1_DMA1R _SFR_(0x2D3) 563 | 564 | /* TIM4 */ 565 | #define TIM4_CR1 _SFR_(0x2E0) 566 | #define TIM4_CR1_ARPE 7 567 | #define TIM4_CR1_OPM 3 568 | #define TIM4_CR1_URS 2 569 | #define TIM4_CR1_UDIS 1 570 | #define TIM4_CR1_CEN 0 571 | #define TIM4_CR2 _SFR_(0x2E1) 572 | #define TIM4_SMCR _SFR_(0x2E2) 573 | #define TIM4_DER _SFR_(0x2E3) 574 | #define TIM4_IER _SFR_(0x2E4) 575 | #define TIM4_IER_TIE 6 576 | #define TIM4_IER_UIE 0 577 | #define TIM4_SR _SFR_(0x2E5) 578 | #define TIM4_SR_TIF 6 579 | #define TIM4_SR_UIF 0 580 | #define TIM4_EGR _SFR_(0x2E6) 581 | #define TIM4_EGR_TG 6 582 | #define TIM4_EGR_UG 0 583 | #define TIM4_CNTR _SFR_(0x2E7) 584 | #define TIM4_PSCR _SFR_(0x2E8) 585 | #define TIM4_ARR _SFR_(0x2E9) 586 | 587 | /* IR */ 588 | #define IR_CR _SFR_(0x2FF) 589 | 590 | /* TIM5 */ 591 | #define TIM5_CR1 _SFR_(0x300) 592 | #define TIM5_CR2 _SFR_(0x301) 593 | #define TIM5_SMCR _SFR_(0x302) 594 | #define TIM5_ETR _SFR_(0x303) 595 | #define TIM5_DER _SFR_(0x304) 596 | #define TIM5_IER _SFR_(0x305) 597 | #define TIM5_SR1 _SFR_(0x306) 598 | #define TIM5_SR2 _SFR_(0x307) 599 | #define TIM5_EGR _SFR_(0x308) 600 | #define TIM5_CCMR1 _SFR_(0x309) 601 | #define TIM5_CCMR2 _SFR_(0x30A) 602 | #define TIM5_CCER1 _SFR_(0x30B) 603 | #define TIM5_CNTRH _SFR_(0x30C) 604 | #define TIM5_CNTRL _SFR_(0x30D) 605 | #define TIM5_PSCR _SFR_(0x30E) 606 | #define TIM5_ARRH _SFR_(0x30F) 607 | #define TIM5_ARRL _SFR_(0x310) 608 | #define TIM5_CCR1H _SFR_(0x311) 609 | #define TIM5_CCR1L _SFR_(0x312) 610 | #define TIM5_CCR2H _SFR_(0x313) 611 | #define TIM5_CCR2L _SFR_(0x314) 612 | #define TIM5_BKR _SFR_(0x315) 613 | #define TIM5_OISR _SFR_(0x316) 614 | 615 | /* ADC1 */ 616 | #define ADC1_CR1 _SFR_(0x340) 617 | #define ADC1_CR1_OVERIE 7 618 | #define ADC1_CR1_RES1 6 619 | #define ADC1_CR1_RES0 5 620 | #define ADC1_CR1_AWDIE 4 621 | #define ADC1_CR1_EOCIE 3 622 | #define ADC1_CR1_CONT 2 623 | #define ADC1_CR1_START 1 624 | #define ADC1_CR1_ADON 0 625 | #define ADC1_CR2 _SFR_(0x341) 626 | #define ADC1_CR2_PRESC 7 627 | #define ADC1_CR2_TRIG_EDGE1 6 628 | #define ADC1_CR2_TRIG_EDGE0 5 629 | #define ADC1_CR2_EXTSEL1 4 630 | #define ADC1_CR2_EXTSEL0 3 631 | #define ADC1_CR2_SMTP12 2 632 | #define ADC1_CR2_SMTP11 1 633 | #define ADC1_CR2_SMTP10 0 634 | #define ADC1_CR3 _SFR_(0x342) 635 | #define ADC1_CR3_SMTP22 7 636 | #define ADC1_CR3_SMTP21 6 637 | #define ADC1_CR3_SMTP20 5 638 | #define ADC1_CR3_CHSEL4 4 639 | #define ADC1_CR3_CHSEL3 3 640 | #define ADC1_CR3_CHSEL2 2 641 | #define ADC1_CR3_CHSEL1 1 642 | #define ADC1_CR3_CHSEL0 0 643 | #define ADC1_SR _SFR_(0x343) 644 | #define ADC1_SR_OVER 2 645 | #define ADC1_SR_AWD 1 646 | #define ADC1_SR_EOC 0 647 | #define ADC1_DRH _SFR_(0x344) 648 | #define ADC1_DRL _SFR_(0x345) 649 | #define ADC1_HTRH _SFR_(0x346) 650 | #define ADC1_HTRL _SFR_(0x347) 651 | #define ADC1_LTRH _SFR_(0x348) 652 | #define ADC1_LTRL _SFR_(0x349) 653 | #define ADC1_SQR1 _SFR_(0x34A) 654 | #define ADC1_SQR1_DMAOFF 7 655 | #define ADC1_SQR1_CHSEL_STS 5 656 | #define ADC1_SQR1_CHSEL_SVREFINT 4 657 | #define ADC1_SQR1_CHSEL_S27 3 658 | #define ADC1_SQR1_CHSEL_S26 2 659 | #define ADC1_SQR1_CHSEL_S25 1 660 | #define ADC1_SQR1_CHSEL_S24 0 661 | #define ADC1_SQR2 _SFR_(0x34B) 662 | #define ADC1_SQR3 _SFR_(0x34C) 663 | #define ADC1_SQR4 _SFR_(0x34D) 664 | #define ADC1_TRIGR1 _SFR_(0x34E) 665 | #define ADC1_TRIGR1_TSON 5 666 | #define ADC1_TRIGR1_VREFINTON 4 667 | #define ADC1_TRIGR1_TRIG27 3 668 | #define ADC1_TRIGR1_TRIG26 2 669 | #define ADC1_TRIGR1_TRIG25 1 670 | #define ADC1_TRIGR1_TRIG24 0 671 | #define ADC1_TRIGR2 _SFR_(0x34F) 672 | #define ADC1_TRIGR3 _SFR_(0x350) 673 | #define ADC1_TRIGR4 _SFR_(0x351) 674 | 675 | /* DAC */ 676 | #define DAC_CH1CR1 _SFR_(0x380) 677 | #define DAC_CH1CR2 _SFR_(0x381) 678 | #define DAC_CH2CR1 _SFR_(0x382) 679 | #define DAC_CH2CR2 _SFR_(0x383) 680 | #define DAC_SWTRIG _SFR_(0x384) 681 | #define DAC_SR _SFR_(0x385) 682 | #define DAC_CH1RDHRH _SFR_(0x388) 683 | #define DAC_CH1RDHRL _SFR_(0x389) 684 | #define DAC_CH1LDHRH _SFR_(0x38C) 685 | #define DAC_CH1LDHRL _SFR_(0x38D) 686 | #define DAC_CH1DHR8 _SFR_(0x390) 687 | #define DAC_CH2RDHRH _SFR_(0x394) 688 | #define DAC_CH2RDHRL _SFR_(0x395) 689 | #define DAC_CH2LDHRH _SFR_(0x398) 690 | #define DAC_CH2LDHRL _SFR_(0x399) 691 | #define DAC_CH2DHR8 _SFR_(0x39C) 692 | #define DAC_DCH1RDHRH _SFR_(0x3A0) 693 | #define DAC_DCH1RDHRL _SFR_(0x3A1) 694 | #define DAC_DORH _SFR_(0x3AC) 695 | #define DAC_DORL _SFR_(0x3AD) 696 | #define DAC_DCH2RDHRH _SFR_(0x3A2) 697 | #define DAC_DCH2RDHRL _SFR_(0x3A3) 698 | #define DAC_DCH1LDHRH _SFR_(0x3A4) 699 | #define DAC_DCH1LDHRL _SFR_(0x3A5) 700 | #define DAC_DCH2LDHRH _SFR_(0x3A6) 701 | #define DAC_DCH2LDHRL _SFR_(0x3A7) 702 | #define DAC_DCH1DHR8 _SFR_(0x3A8) 703 | #define DAC_DCH2DHR8 _SFR_(0x3A9) 704 | #define DAC_CH1DORH _SFR_(0x3AC) 705 | #define DAC_CH1DORL _SFR_(0x3AD) 706 | #define DAC_CH2DORH _SFR_(0x3B0) 707 | #define DAC_CH2DORL _SFR_(0x3B1) 708 | 709 | /* SPI2 */ 710 | #define SPI2_CR1 _SFR_(0x3C0) 711 | #define SPI2_CR2 _SFR_(0x3C1) 712 | #define SPI2_ICR _SFR_(0x3C2) 713 | #define SPI2_SR _SFR_(0x3C3) 714 | #define SPI2_DR _SFR_(0x3C4) 715 | #define SPI2_CRCPR _SFR_(0x3C5) 716 | #define SPI2_RXCRCR _SFR_(0x3C6) 717 | #define SPI2_TXCRCR _SFR_(0x3C7) 718 | 719 | /* AES */ 720 | #define AES_CR _SFR_(0x3D0) 721 | #define AES_SR _SFR_(0x3D1) 722 | #define AES_DINR _SFR_(0x3D2) 723 | #define AES_DOUTR _SFR_(0x3D3) 724 | 725 | /* USART2 */ 726 | #define USART2_SR _SFR_(0x3E0) 727 | #define USART2_DR _SFR_(0x3E1) 728 | #define USART2_BRR1 _SFR_(0x3E2) 729 | #define USART2_BRR2 _SFR_(0x3E3) 730 | #define USART2_CR1 _SFR_(0x3E4) 731 | #define USART2_CR2 _SFR_(0x3E5) 732 | #define USART2_CR3 _SFR_(0x3E6) 733 | #define USART2_CR4 _SFR_(0x3E7) 734 | #define USART2_CR5 _SFR_(0x3E8) 735 | #define USART2_GTR _SFR_(0x3E9) 736 | #define USART2_PSCR _SFR_(0x3EA) 737 | 738 | /* USART3 */ 739 | #define USART3_SR _SFR_(0x3F0) 740 | #define USART3_DR _SFR_(0x3F1) 741 | #define USART3_BRR1 _SFR_(0x3F2) 742 | #define USART3_BRR2 _SFR_(0x3F3) 743 | #define USART3_CR1 _SFR_(0x3F4) 744 | #define USART3_CR2 _SFR_(0x3F5) 745 | #define USART3_CR3 _SFR_(0x3F6) 746 | #define USART3_CR4 _SFR_(0x3F7) 747 | #define USART3_CR5 _SFR_(0x3F8) 748 | #define USART3_GTR _SFR_(0x3F9) 749 | #define USART3_PSCR _SFR_(0x3FA) 750 | 751 | /* LCD */ 752 | #define LCD_CR1 _SFR_(0x400) 753 | #define LCD_CR2 _SFR_(0x401) 754 | #define LCD_CR3 _SFR_(0x402) 755 | #define LCD_FRQ _SFR_(0x403) 756 | #define LCD_PM0 _SFR_(0x404) 757 | #define LCD_PM1 _SFR_(0x405) 758 | #define LCD_PM2 _SFR_(0x406) 759 | #define LCD_PM3 _SFR_(0x407) 760 | #define LCD_PM4 _SFR_(0x408) 761 | #define LCD_PM5 _SFR_(0x409) 762 | #define LCD_RAM0 _SFR_(0x40C) 763 | #define LCD_RAM1 _SFR_(0x40D) 764 | #define LCD_RAM2 _SFR_(0x40E) 765 | #define LCD_RAM3 _SFR_(0x40F) 766 | #define LCD_RAM4 _SFR_(0x410) 767 | #define LCD_RAM5 _SFR_(0x411) 768 | #define LCD_RAM6 _SFR_(0x412) 769 | #define LCD_RAM7 _SFR_(0x413) 770 | #define LCD_RAM8 _SFR_(0x414) 771 | #define LCD_RAM9 _SFR_(0x415) 772 | #define LCD_RAM10 _SFR_(0x416) 773 | #define LCD_RAM11 _SFR_(0x417) 774 | #define LCD_RAM12 _SFR_(0x418) 775 | #define LCD_RAM13 _SFR_(0x419) 776 | #define LCD_RAM14 _SFR_(0x41A) 777 | #define LCD_RAM15 _SFR_(0x41B) 778 | #define LCD_RAM16 _SFR_(0x41C) 779 | #define LCD_RAM17 _SFR_(0x41D) 780 | #define LCD_RAM18 _SFR_(0x41E) 781 | #define LCD_RAM19 _SFR_(0x41F) 782 | #define LCD_RAM20 _SFR_(0x420) 783 | #define LCD_RAM21 _SFR_(0x421) 784 | #define LCD_CR4 _SFR_(0x42F) 785 | 786 | /* RI */ 787 | #define RI_ICR1 _SFR_(0x431) 788 | #define RI_ICR2 _SFR_(0x432) 789 | #define RI_IOIR1 _SFR_(0x433) 790 | #define RI_IOIR2 _SFR_(0x434) 791 | #define RI_IOIR3 _SFR_(0x435) 792 | #define RI_IOCMR1 _SFR_(0x436) 793 | #define RI_IOCMR2 _SFR_(0x437) 794 | #define RI_IOCMR3 _SFR_(0x438) 795 | #define RI_IOSR1 _SFR_(0x439) 796 | #define RI_IOSR2 _SFR_(0x43A) 797 | #define RI_IOSR3 _SFR_(0x43B) 798 | #define RI_IOGCR _SFR_(0x43C) 799 | #define RI_ASCR1 _SFR_(0x43D) 800 | #define RI_ASCR2 _SFR_(0x43E) 801 | #define RI_RCR _SFR_(0x43F) 802 | #define RI_CR _SFR_(0x450) 803 | #define RI_MASKR1 _SFR_(0x451) 804 | #define RI_MASKR2 _SFR_(0x452) 805 | #define RI_MASKR3 _SFR_(0x453) 806 | #define RI_MASKR4 _SFR_(0x454) 807 | #define RI_IOIR4 _SFR_(0x455) 808 | #define RI_IOCMR4 _SFR_(0x456) 809 | #define RI_IOSR4 _SFR_(0x457) 810 | 811 | /* Comparator */ 812 | #define COMP_CSR1 _SFR_(0x440) 813 | #define COMP_CSR2 _SFR_(0x441) 814 | #define COMP_CSR3 _SFR_(0x442) 815 | #define COMP_CSR4 _SFR_(0x443) 816 | #define COMP_CSR5 _SFR_(0x444) 817 | 818 | /* Interrupts */ 819 | #define TLI_ISR 0 820 | #define FLASH_ISR 1 821 | #define DMA1_01_ISR 2 822 | #define DMA1_23_ISR 3 823 | #define RTC_ISR 4 824 | #define PVD_ISR 5 825 | #define EXTIB_ISR 6 826 | #define EXTID_ISR 7 827 | #define EXTI0_ISR 8 828 | #define EXTI1_ISR 9 829 | #define EXTI2_ISR 10 830 | #define EXTI3_ISR 11 831 | #define EXTI4_ISR 12 832 | #define EXTI5_ISR 13 833 | #define EXTI6_ISR 14 834 | #define EXTI7_ISR 15 835 | #define CLK_ISR 17 836 | #define ADC1_ISR 18 837 | #define TIM2_UPD_ISR 19 838 | #define TIM2_CC_ISR 20 839 | #define TIM3_UPD_ISR 21 840 | #define TIM3_CC_ISR 22 841 | #define RI_ISR 23 842 | #define TIM4_ISR 25 843 | #define SPI1_ISR 26 844 | #define USART1_TXE_ISR 27 845 | #define USART1_RXNE_ISR 28 846 | #define I2C1_ISR 29 847 | 848 | /* CPU */ 849 | #define CPU_CCR _MEM_(0x7F60) 850 | #define ITC_SPR1 _MEM_(0x7F70) 851 | #define ITC_SPR2 _MEM_(0x7F71) 852 | #define ITC_SPR3 _MEM_(0x7F72) 853 | #define ITC_SPR4 _MEM_(0x7F73) 854 | #define ITC_SPR5 _MEM_(0x7F74) 855 | #define ITC_SPR6 _MEM_(0x7F75) 856 | #define ITC_SPR7 _MEM_(0x7F76) 857 | #define ITC_SPR8 _MEM_(0x7F77) 858 | 859 | #define enable_interrupts() __asm__("rim"); 860 | #define disable_interrupts() __asm__("sim"); 861 | 862 | #endif /* STM8L_H */ 863 | --------------------------------------------------------------------------------