├── LICENSE ├── README.md ├── coe ├── lab_1_2.coe ├── lab_2.coe ├── lab_3.coe └── lab_4.coe ├── constr └── constr.xdc ├── docs ├── MIPS基准指令集手册_v1.00.pdf ├── coe指令说明.jpg ├── lab_1_2018.pdf ├── lab_1_n4ddr_user_guide.pdf ├── lab_1_zy.pdf ├── lab_2.pdf ├── lab_2_tutorial.pdf ├── lab_3_tutorial.pdf ├── lab_4.asm ├── lab_4_tutorial.pdf ├── 其他组件实现.pdf └── 指令及对应机器码_2018.pdf ├── sim ├── lab_2_tb.v ├── lab_3_tb.v └── lab_4_tb.v ├── src ├── lab_1_1 │ ├── calculate.v │ ├── display.v │ ├── seg7.v │ └── top.v ├── lab_1_2 │ ├── Ins_ROM │ │ └── Ins_ROM.xci │ ├── Rom.v │ ├── display.v │ └── seg7.v ├── lab_2 │ ├── calculate.v │ ├── display.v │ ├── ip │ │ └── inst_rom │ │ │ └── inst_rom.xci │ ├── seg7.v │ └── top.v ├── lab_3 │ ├── adder.v │ ├── alu.v │ ├── aludec.v │ ├── controller.v │ ├── datapath.v │ ├── flopr.v │ ├── ip │ │ ├── .Xil │ │ │ └── .inst_mem.xcix.lock │ │ ├── clk_wiz_0 │ │ │ └── clk_wiz_0.xci │ │ ├── data_mem │ │ │ └── data_mem.xci │ │ └── inst_mem │ │ │ └── inst_mem.xci │ ├── maindec.v │ ├── mips.v │ ├── mux2.v │ ├── regfile.v │ ├── signext.v │ ├── sl2.v │ └── top.v └── lab_4 │ ├── adder.v │ ├── alu.v │ ├── aludec.v │ ├── controller.v │ ├── datapath.v │ ├── eqcmp.v │ ├── flopenr.v │ ├── flopenrc.v │ ├── flopr.v │ ├── floprc.v │ ├── hazard.v │ ├── ip │ ├── data_mem │ │ └── data_mem.xci │ └── inst_mem │ │ └── inst_mem.xci │ ├── maindec.v │ ├── mips.v │ ├── mux2.v │ ├── mux3.v │ ├── pc.v │ ├── regfile.v │ ├── signext.v │ ├── sl2.v │ └── top.v └── xpr ├── lab_1_1.xpr ├── lab_1_2.xpr ├── lab_2.xpr ├── lab_3.xpr └── lab_4.xpr /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 nate.river 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## 计算机组成原理实验与参考实现 2 | 3 | 本仓库包含重庆大学由2017年开始实施的计算机组成原理课程改革实验内容，通过合理的梯度划分，一步一步由单独器件连接构成CPU，最后实现一个简单的MIPS五级流水CPU。 4 | 5 | 本项目实验为《硬件综合设计》课程前导，同时也可作为NSCSCC（龙芯杯系统能力培养大赛）的入门教程。 6 | 7 | **** 8 | 课程共有四次实验，分别为： 9 | 1. ALU设计，存储器IP使用: [lab_1](https://github.com/cquca/step_into_mips/tree/lab_1) 10 | 2. 简单的取指译码模块: [lab_2](https://github.com/cquca/step_into_mips/tree/lab_2) 11 | 3. 单周期MIPS CPU设计: [lab_3](https://github.com/cquca/step_into_mips/tree/lab_3) 12 | 4. 简单五级流水线MIPS CPU设计: [lab_4](https://github.com/cquca/step_into_mips/tree/lab_4) 13 | 14 | 相关文档资料和分别于本仓库不同分支。 15 | 16 | 预备知识和器件实现:[prepare](https://github.com/cquca/step_into_mips/tree/prepare) 17 | 18 | 附录文档:[appendix](https://github.com/cquca/step_into_mips/tree/appendix) 19 | **** 20 | **参考与致谢** 21 | 22 | 本实验内容以《Digital Design and Computer Architecture》为依托进行设计，同时引入了大量由龙芯中科提供的比赛资源，作为参考文档，特此感谢。 23 | 24 | 若有参考需求，请访问： 25 | 26 | **DDCA:** [Elsevier Book Store](https://www.elsevier.com/books/digital-design-and-computer-architecture/harris/978-0-12-394424-5) 27 | 28 | **NSCSCC:** [全国大学生系统能力培养大赛官网](http://www.nscscc.org/) 29 | 30 | **** -------------------------------------------------------------------------------- /coe/lab_1_2.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 3c01ffff, 4 | 343cf000, 5 | 8c190004, 6 | 8c180008, 7 | 8c17000c, 8 | 8c160010, 9 | 8c150014, 10 | 8c140018, 11 | 8c13001c, 12 | 8c120020, 13 | 8c110024, 14 | 8c1d0000, 15 | 23bdffff, 16 | 17a0fffe, 17 | 03e00008, 18 | af980c60, 19 | 0c00000b, 20 | af970c60, 21 | 0c00000b, 22 | af960c60, 23 | 0c00000b, 24 | af950c60, 25 | 0c00000b, 26 | af940c60, 27 | 0c00000b, 28 | af930c60, 29 | 0c00000b, 30 | af920c60, 31 | 0c00000b, 32 | af910c60, 33 | 0c00000b, 34 | af920c60, 35 | 0c00000b, 36 | af930c60, 37 | 0c00000b, 38 | af940c60, 39 | 0c00000b, 40 | af950c60, 41 | 0c00000b, 42 | af960c60, 43 | 0c00000b, 44 | af970c60, 45 | 0c00000b, 46 | af980c60, 47 | 0c00000b, 48 | af990c60, 49 | 8c1d0000, 50 | 23bdffff, 51 | 17a0fffe, 52 | 0800000f, 53 | 00000000, 54 | 00000000, 55 | 00000000, 56 | 00000000, 57 | 00000000, 58 | 00000000, 59 | 00000000, 60 | 00000000, 61 | 00000000, 62 | 00000000, 63 | 00000000, 64 | 00000000, 65 | 00000000, 66 | 00000000, 67 | 00000000, 68 | 00000000, 69 | 00000000, 70 | 00000000, 71 | 00000000, 72 | 00000000, 73 | 00000000, 74 | 00000000, 75 | 00000000, 76 | 00000000, 77 | 00000000, 78 | 00000000, 79 | 00000000, 80 | 00000000, 81 | 00000000, 82 | 00000000, 83 | 00000000, 84 | 00000000, 85 | 00000000, 86 | 00000000, 87 | 00000000, 88 | 00000000, 89 | 00000000, 90 | 00000000, 91 | 00000000, 92 | 00000000, 93 | 00000000, 94 | 00000000, 95 | 00000000, 96 | 00000000, 97 | 00000000, 98 | 00000000, 99 | 00000000, 100 | 00000000, 101 | 00000000, 102 | 00000000, 103 | 00000000, 104 | 00000000, 105 | 00000000, 106 | 00000000, 107 | 00000000, 108 | 00000000, 109 | 00000000, 110 | 00000000, 111 | 00000000, 112 | 00000000, 113 | 00000000, 114 | 00000000, 115 | 00000000, 116 | 00000000, 117 | 00000000, 118 | 00000000, 119 | 00000000, 120 | 00000000, 121 | 00000000, 122 | 00000000, 123 | 00000000, 124 | 00000000, 125 | 00000000, 126 | 00000000, 127 | 00000000, 128 | 00000000, 129 | 00000000, 130 | 00000000, 131 | 00000000, 132 | 00000000, 133 | 00000000, 134 | 00000000, 135 | 00000000, 136 | 00000000, 137 | 00000000, 138 | 00000000, 139 | 00000000, 140 | 00000000, 141 | 00000000, 142 | 00000000, 143 | 00000000, 144 | 00000000, 145 | 00000000, 146 | 00000000, 147 | 00000000, 148 | 00000000, 149 | 00000000, 150 | 00000000, 151 | 00000000, 152 | 00000000, 153 | 00000000, 154 | 00000000, 155 | 00000000, 156 | 00000000, 157 | 00000000, 158 | 00000000, 159 | 00000000, 160 | 00000000, 161 | 00000000, 162 | 00000000, 163 | 00000000, 164 | 00000000, 165 | 00000000, 166 | 00000000, 167 | 00000000, 168 | 00000000, 169 | 00000000, 170 | 00000000, 171 | 00000000, 172 | 00000000, 173 | 00000000, 174 | 00000000, 175 | 00000000, 176 | 00000000, 177 | 00000000, 178 | 00000000, 179 | 00000000, 180 | 00000000, 181 | 00000000, 182 | 00000000, 183 | 00000000, 184 | 00000000, 185 | 00000000, 186 | 00000000, 187 | 00000000, 188 | 00000000, 189 | 00000000, 190 | 00000000, 191 | 00000000, 192 | 00000000, 193 | 00000000, 194 | 00000000, 195 | 00000000, 196 | 00000000, 197 | 00000000, 198 | 00000000, 199 | 00000000, 200 | 00000000, 201 | 00000000, 202 | 00000000, 203 | 00000000, 204 | 00000000, 205 | 00000000, 206 | 00000000, 207 | 00000000, 208 | 00000000, 209 | 00000000, 210 | 00000000, 211 | 00000000, 212 | 00000000, 213 | 00000000, 214 | 00000000, 215 | 00000000, 216 | 00000000, 217 | 00000000, 218 | 00000000, 219 | 00000000, 220 | 00000000, 221 | 00000000, 222 | 00000000, 223 | 00000000, 224 | 00000000, 225 | 00000000, 226 | 00000000, 227 | 00000000, 228 | 00000000, 229 | 00000000, 230 | 00000000, 231 | 00000000, 232 | 00000000, 233 | 00000000, 234 | 00000000, 235 | 00000000, 236 | 00000000, 237 | 00000000, 238 | 00000000, 239 | 00000000, 240 | 00000000, 241 | 00000000, 242 | 00000000, 243 | 00000000, 244 | 00000000, 245 | 00000000, 246 | 00000000, 247 | 00000000, 248 | 00000000, 249 | 00000000, 250 | 00000000, 251 | 00000000, 252 | 00000000, 253 | 00000000, 254 | 00000000, 255 | 00000000, 256 | 00000000, 257 | 00000000, 258 | 00000000 -------------------------------------------------------------------------------- /coe/lab_2.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 3c01ffff, 4 | 343cf000, 5 | 8c190004, 6 | 8c180008, 7 | 8c17000c, 8 | 8c160010, 9 | 8c150014, 10 | 8c140018, 11 | 8c13001c, 12 | 8c120020, 13 | 8c110024, 14 | 8c1d0000, 15 | 23bdffff, 16 | 17a0fffe, 17 | 03e00008, 18 | af980c60, 19 | 0c00000b, 20 | af970c60, 21 | 0c00000b, 22 | af960c60, 23 | 0c00000b, 24 | af950c60, 25 | 0c00000b, 26 | af940c60, 27 | 0c00000b, 28 | af930c60, 29 | 0c00000b, 30 | af920c60, 31 | 0c00000b, 32 | af910c60, 33 | 0c00000b, 34 | af920c60, 35 | 0c00000b, 36 | af930c60, 37 | 0c00000b, 38 | af940c60, 39 | 0c00000b, 40 | af950c60, 41 | 0c00000b, 42 | af960c60, 43 | 0c00000b, 44 | af970c60, 45 | 0c00000b, 46 | af980c60, 47 | 0c00000b, 48 | af990c60, 49 | 8c1d0000, 50 | 23bdffff, 51 | 17a0fffe, 52 | 0800000f, 53 | 00000000, 54 | 00000000, 55 | 00000000, 56 | 00000000, 57 | 00000000, 58 | 00000000, 59 | 00000000, 60 | 00000000, 61 | 00000000, 62 | 00000000, 63 | 00000000, 64 | 00000000, 65 | 00000000, 66 | 00000000, 67 | 00000000, 68 | 00000000, 69 | 00000000, 70 | 00000000, 71 | 00000000, 72 | 00000000, 73 | 00000000, 74 | 00000000, 75 | 00000000, 76 | 00000000, 77 | 00000000, 78 | 00000000, 79 | 00000000, 80 | 00000000, 81 | 00000000, 82 | 00000000, 83 | 00000000, 84 | 00000000, 85 | 00000000, 86 | 00000000, 87 | 00000000, 88 | 00000000, 89 | 00000000, 90 | 00000000, 91 | 00000000, 92 | 00000000, 93 | 00000000, 94 | 00000000, 95 | 00000000, 96 | 00000000, 97 | 00000000, 98 | 00000000, 99 | 00000000, 100 | 00000000, 101 | 00000000, 102 | 00000000, 103 | 00000000, 104 | 00000000, 105 | 00000000, 106 | 00000000, 107 | 00000000, 108 | 00000000, 109 | 00000000, 110 | 00000000, 111 | 00000000, 112 | 00000000, 113 | 00000000, 114 | 00000000, 115 | 00000000, 116 | 00000000, 117 | 00000000, 118 | 00000000, 119 | 00000000, 120 | 00000000, 121 | 00000000, 122 | 00000000, 123 | 00000000, 124 | 00000000, 125 | 00000000, 126 | 00000000, 127 | 00000000, 128 | 00000000, 129 | 00000000, 130 | 00000000, 131 | 00000000, 132 | 00000000, 133 | 00000000, 134 | 00000000, 135 | 00000000, 136 | 00000000, 137 | 00000000, 138 | 00000000, 139 | 00000000, 140 | 00000000, 141 | 00000000, 142 | 00000000, 143 | 00000000, 144 | 00000000, 145 | 00000000, 146 | 00000000, 147 | 00000000, 148 | 00000000, 149 | 00000000, 150 | 00000000, 151 | 00000000, 152 | 00000000, 153 | 00000000, 154 | 00000000, 155 | 00000000, 156 | 00000000, 157 | 00000000, 158 | 00000000, 159 | 00000000, 160 | 00000000, 161 | 00000000, 162 | 00000000, 163 | 00000000, 164 | 00000000, 165 | 00000000, 166 | 00000000, 167 | 00000000, 168 | 00000000, 169 | 00000000, 170 | 00000000, 171 | 00000000, 172 | 00000000, 173 | 00000000, 174 | 00000000, 175 | 00000000, 176 | 00000000, 177 | 00000000, 178 | 00000000, 179 | 00000000, 180 | 00000000, 181 | 00000000, 182 | 00000000, 183 | 00000000, 184 | 00000000, 185 | 00000000, 186 | 00000000, 187 | 00000000, 188 | 00000000, 189 | 00000000, 190 | 00000000, 191 | 00000000, 192 | 00000000, 193 | 00000000, 194 | 00000000, 195 | 00000000, 196 | 00000000, 197 | 00000000, 198 | 00000000, 199 | 00000000, 200 | 00000000, 201 | 00000000, 202 | 00000000, 203 | 00000000, 204 | 00000000, 205 | 00000000, 206 | 00000000, 207 | 00000000, 208 | 00000000, 209 | 00000000, 210 | 00000000, 211 | 00000000, 212 | 00000000, 213 | 00000000, 214 | 00000000, 215 | 00000000, 216 | 00000000, 217 | 00000000, 218 | 00000000, 219 | 00000000, 220 | 00000000, 221 | 00000000, 222 | 00000000, 223 | 00000000, 224 | 00000000, 225 | 00000000, 226 | 00000000, 227 | 00000000, 228 | 00000000, 229 | 00000000, 230 | 00000000, 231 | 00000000, 232 | 00000000, 233 | 00000000, 234 | 00000000, 235 | 00000000, 236 | 00000000, 237 | 00000000, 238 | 00000000, 239 | 00000000, 240 | 00000000, 241 | 00000000, 242 | 00000000, 243 | 00000000, 244 | 00000000, 245 | 00000000, 246 | 00000000, 247 | 00000000, 248 | 00000000, 249 | 00000000, 250 | 00000000, 251 | 00000000, 252 | 00000000, 253 | 00000000, 254 | 00000000, 255 | 00000000, 256 | 00000000, 257 | 00000000, 258 | 00000000 -------------------------------------------------------------------------------- /coe/lab_3.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 20020005, 4 | 2003000c, 5 | 2067fff7, 6 | 00e22025, 7 | 00642824, 8 | 00a42820, 9 | 10a7000a, 10 | 0064202a, 11 | 10800001, 12 | 20050000, 13 | 00e2202a, 14 | 00853820, 15 | 00e23822, 16 | ac670044, 17 | 8c020050, 18 | 08000011, 19 | 20020001, 20 | ac020054 -------------------------------------------------------------------------------- /coe/lab_4.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 20020005, 4 | 2003000c, 5 | 2067fff7, 6 | 00e22025, 7 | 00642824, 8 | 00a42820, 9 | 10a7000c, 10 | 0064202a, 11 | 10800002, 12 | 00000000, 13 | 20050000, 14 | 00e2202a, 15 | 00853820, 16 | 00e23822, 17 | ac670044, 18 | 8c020050, 19 | 08000013, 20 | 00000000, 21 | 20020001, 22 | ac020054, -------------------------------------------------------------------------------- /constr/constr.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[7]}] 2 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[6]}] 3 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[5]}] 4 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[4]}] 5 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[3]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[2]}] 7 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {ans[0]}] 9 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[7]}] 10 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[6]}] 11 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[5]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[4]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[3]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[2]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[1]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {num1[0]}] 17 | set_property IOSTANDARD LVCMOS33 [get_ports {op[2]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {op[1]}] 19 | set_property IOSTANDARD LVCMOS33 [get_ports {op[0]}] 20 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 21 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 22 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 23 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 24 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 25 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 26 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 27 | set_property PACKAGE_PIN W4 [get_ports {num1[0]}] 28 | set_property PACKAGE_PIN R4 [get_ports {num1[1]}] 29 | set_property PACKAGE_PIN T4 [get_ports {num1[2]}] 30 | set_property PACKAGE_PIN T5 [get_ports {num1[3]}] 31 | set_property PACKAGE_PIN U5 [get_ports {num1[4]}] 32 | set_property PACKAGE_PIN W6 [get_ports {num1[5]}] 33 | set_property PACKAGE_PIN W5 [get_ports {num1[6]}] 34 | set_property PACKAGE_PIN U6 [get_ports {num1[7]}] 35 | set_property PACKAGE_PIN Y7 [get_ports {op[2]}] 36 | set_property PACKAGE_PIN W9 [get_ports {op[1]}] 37 | set_property PACKAGE_PIN Y9 [get_ports {op[0]}] 38 | set_property PACKAGE_PIN A18 [get_ports {ans[7]}] 39 | set_property PACKAGE_PIN A20 [get_ports {ans[6]}] 40 | set_property PACKAGE_PIN B20 [get_ports {ans[5]}] 41 | set_property PACKAGE_PIN E18 [get_ports {ans[4]}] 42 | set_property PACKAGE_PIN F18 [get_ports {ans[3]}] 43 | set_property PACKAGE_PIN D19 [get_ports {ans[2]}] 44 | set_property PACKAGE_PIN E19 [get_ports {ans[1]}] 45 | set_property PACKAGE_PIN C19 [get_ports {ans[0]}] 46 | set_property PACKAGE_PIN F15 [get_ports {seg[6]}] 47 | set_property PACKAGE_PIN F13 [get_ports {seg[5]}] 48 | set_property PACKAGE_PIN F14 [get_ports {seg[4]}] 49 | set_property PACKAGE_PIN F16 [get_ports {seg[3]}] 50 | set_property PACKAGE_PIN E17 [get_ports {seg[2]}] 51 | set_property PACKAGE_PIN C14 [get_ports {seg[1]}] 52 | set_property PACKAGE_PIN C15 [get_ports {seg[0]}] 53 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 54 | set_property IOSTANDARD LVCMOS33 [get_ports rst] 55 | set_property PACKAGE_PIN Y18 [get_ports clk] 56 | set_property PACKAGE_PIN P20 [get_ports rst] 57 | -------------------------------------------------------------------------------- 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////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/25 19:30:17 7 | // Design Name: 8 | // Module Name: test_bench 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_bench( 24 | 25 | ); 26 | 27 | reg rst; 28 | reg clk; 29 | wire [7:0] ans; 30 | wire [6:0] seg; 31 | wire [9:0] led; 32 | initial 33 | begin 34 | clk = 1'b0; 35 | rst = 1'b1; 36 | #500; 37 | rst = 1'b0; 38 | end 39 | always #10 clk = ~clk; 40 | top top( 41 | .hclk(clk), 42 | .rst(rst), 43 | .seg(seg), 44 | .ans(ans), 45 | .led(led) 46 | ); 47 | endmodule 48 | -------------------------------------------------------------------------------- /sim/lab_3_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/07 13:54:42 7 | // Design Name: 8 | // Module Name: testbench 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module testbench(); 24 | reg clk; 25 | reg rst; 26 | 27 | wire[31:0] writedata,dataadr; 28 | wire memwrite; 29 | 30 | top dut(clk,rst,writedata,dataadr,memwrite); 31 | 32 | initial begin 33 | rst <= 1; 34 | #200; 35 | rst <= 0; 36 | end 37 | 38 | always begin 39 | clk <= 1; 40 | #10; 41 | clk <= 0; 42 | #10; 43 | 44 | end 45 | 46 | always @(negedge clk) begin 47 | if(memwrite) begin 48 | /* code */ 49 | if(dataadr === 84 & writedata === 7) begin 50 | /* code */ 51 | $display("Simulation succeeded"); 52 | $stop; 53 | end else if(dataadr !== 80) begin 54 | /* code */ 55 | $display("Simulation Failed"); 56 | $stop; 57 | end 58 | end 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /sim/lab_4_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/07 13:54:42 7 | // Design Name: 8 | // Module Name: testbench 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module testbench(); 24 | reg clk; 25 | reg rst; 26 | 27 | wire[31:0] writedata,dataadr; 28 | wire memwrite; 29 | 30 | top dut(clk,rst,writedata,dataadr,memwrite); 31 | 32 | initial begin 33 | rst <= 1; 34 | #200; 35 | rst <= 0; 36 | end 37 | 38 | always begin 39 | clk <= 1; 40 | #10; 41 | clk <= 0; 42 | #10; 43 | 44 | end 45 | 46 | always @(negedge clk) begin 47 | if(memwrite) begin 48 | /* code */ 49 | if(dataadr === 84 & writedata === 7) begin 50 | /* code */ 51 | $display("Simulation succeeded"); 52 | $stop; 53 | end else if(dataadr !== 80) begin 54 | /* code */ 55 | $display("Simulation Failed"); 56 | $stop; 57 | end 58 | end 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /src/lab_1_1/calculate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/24 16:59:00 7 | // Design Name: 8 | // Module Name: calculate 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module calculate( 24 | input wire [7:0] num1, 25 | input wire [2:0] op, 26 | output [31:0] result 27 | ); 28 | wire [31:0] num2; 29 | wire [31:0] Sign_extend; 30 | 31 | assign num2 = 32'h00000001; 32 | assign Sign_extend={{24{1'b0}},num1[7:0]}; 33 | assign result = (op == 3'b000)? Sign_extend + num2: 34 | (op == 3'b001)? Sign_extend - num2: 35 | (op == 3'b010)? Sign_extend & num2: 36 | (op == 3'b011)? Sign_extend | num2: 37 | (op == 3'b100)? ~Sign_extend: 32'h00000000; 38 | endmodule 39 | -------------------------------------------------------------------------------- /src/lab_1_1/display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/17 01:12:00 7 | // Design Name: 8 | // Module Name: display 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module display( 23 | input wire clk,reset, 24 | input wire [31:0]s, 25 | output wire [6:0]seg, 26 | output reg [7:0]ans 27 | ); 28 | reg [20:0]count; 29 | reg [4:0]digit; 30 | always@(posedge clk,posedge reset) 31 | if(reset) 32 | count = 0; 33 | else 34 | count = count + 1; 35 | 36 | always @(posedge clk) 37 | case(count[20:18]) 38 | 0:begin 39 | ans = 8'b11111110; 40 | digit = s[3:0]; 41 | end 42 | 43 | 1:begin 44 | ans = 8'b11111101; 45 | digit = s[7:4]; 46 | end 47 | 48 | 2:begin 49 | ans = 8'b11111011; 50 | digit =s[11:8]; 51 | end 52 | 53 | 3:begin 54 | ans = 8'b11110111; 55 | digit = s[15:12]; 56 | end 57 | 58 | 4:begin 59 | ans = 8'b11101111; 60 | digit = s[19:16]; 61 | end 62 | 63 | 5:begin 64 | ans = 8'b11011111; 65 | digit = s[23:20]; 66 | end 67 | 68 | 6:begin 69 | ans = 8'b10111111; 70 | digit =s[27:24]; 71 | end 72 | 73 | 7:begin 74 | ans = 8'b01111111; 75 | digit = s[31:28]; 76 | end 77 | endcase 78 | 79 | seg7 U4(.din(digit),.dout(seg)); 80 | endmodule -------------------------------------------------------------------------------- /src/lab_1_1/seg7.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/17 01:14:44 7 | // Design Name: 8 | // Module Name: seg7 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module seg7( 23 | input wire [3:0]din, 24 | output reg [6:0]dout 25 | ); 26 | 27 | always@(*) 28 | case(din) 29 | 5'h0:dout = 7'b000_0001; 30 | 5'h1:dout = 7'b100_1111; 31 | 5'h2:dout = 7'b001_0010; 32 | 5'h3:dout = 7'b000_0110; 33 | 5'h4:dout = 7'b100_1100; 34 | 5'h5:dout = 7'b010_0100; 35 | 5'h6:dout = 7'b010_0000; 36 | 5'h7:dout = 7'b000_1111; 37 | 5'h8:dout = 7'b000_0000; 38 | 5'h9:dout = 7'b000_0100; 39 | 5'ha:dout = 7'b000_1000; 40 | 5'hb:dout = 7'b110_0000; 41 | 5'hc:dout = 7'b011_0001; 42 | 5'hd:dout = 7'b100_0010; 43 | 5'he:dout = 7'b011_0000; 44 | 5'hf:dout = 7'b011_1000; 45 | default:dout = 7'b111_1111; 46 | endcase 47 | 48 | 49 | endmodule -------------------------------------------------------------------------------- /src/lab_1_1/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/25 10:35:04 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input clk, 25 | input rst, 26 | input [2:0] op, 27 | input [7:0] num1, 28 | output [7:0] ans, 29 | output [6:0] seg 30 | ); 31 | wire [31:0] s; 32 | calculate U1(.num1(num1),.op(op),.result(s)); 33 | 34 | display U2(.clk(clk),.reset(rst),.s(s),.ans(ans),.seg(seg)); 35 | endmodule 36 | -------------------------------------------------------------------------------- /src/lab_1_2/Rom.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/28 15:58:09 7 | // Design Name: 8 | // Module Name: Rom 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Rom( 24 | input [15:0] ins, 25 | input clk, 26 | input reset, 27 | output [6:0] seg, 28 | output [7:0] ans 29 | ); 30 | wire [31:0] InsData; 31 | Ins_ROM Ins_Rom(.clka(clk), // input wire clka 32 | .addra({{16{ins[15]}},ins[15:0]}), // input wire [15 : 0] addra 33 | .douta(InsData[31:0]) // output wire [31 : 0] douta 34 | ); 35 | display display_0(.clk(clk),.reset(reset),.s(InsData),.ans(ans),.seg(seg)); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /src/lab_1_2/display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/17 01:12:00 7 | // Design Name: 8 | // Module Name: display 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module display( 23 | input wire clk,reset, 24 | input wire [31:0]s, 25 | output wire [6:0]seg, 26 | output reg [7:0]ans 27 | ); 28 | reg [20:0]count; 29 | reg [4:0]digit; 30 | always@(posedge clk,posedge reset) 31 | if(reset) 32 | count = 0; 33 | else 34 | count = count + 1; 35 | 36 | always @(posedge clk) 37 | case(count[20:18]) 38 | 0:begin 39 | ans = 8'b11111110; 40 | digit = s[3:0]; 41 | end 42 | 43 | 1:begin 44 | ans = 8'b11111101; 45 | digit = s[7:4]; 46 | end 47 | 48 | 2:begin 49 | ans = 8'b11111011; 50 | digit =s[11:8]; 51 | end 52 | 53 | 3:begin 54 | ans = 8'b11110111; 55 | digit = s[15:12]; 56 | end 57 | 58 | 4:begin 59 | ans = 8'b11101111; 60 | digit = s[19:16]; 61 | end 62 | 63 | 5:begin 64 | ans = 8'b11011111; 65 | digit = s[23:20]; 66 | end 67 | 68 | 6:begin 69 | ans = 8'b10111111; 70 | digit =s[27:24]; 71 | end 72 | 73 | 7:begin 74 | ans = 8'b01111111; 75 | digit = s[31:28]; 76 | end 77 | endcase 78 | 79 | seg7 U4(.din(digit),.dout(seg)); 80 | endmodule -------------------------------------------------------------------------------- /src/lab_1_2/seg7.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/17 01:14:44 7 | // Design Name: 8 | // Module Name: seg7 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module seg7( 23 | input wire [3:0]din, 24 | output reg [6:0]dout 25 | ); 26 | 27 | always@(*) 28 | case(din) 29 | 5'h0:dout = 7'b000_0001; 30 | 5'h1:dout = 7'b100_1111; 31 | 5'h2:dout = 7'b001_0010; 32 | 5'h3:dout = 7'b000_0110; 33 | 5'h4:dout = 7'b100_1100; 34 | 5'h5:dout = 7'b010_0100; 35 | 5'h6:dout = 7'b010_0000; 36 | 5'h7:dout = 7'b000_1111; 37 | 5'h8:dout = 7'b000_0000; 38 | 5'h9:dout = 7'b000_0100; 39 | 5'ha:dout = 7'b000_1000; 40 | 5'hb:dout = 7'b110_0000; 41 | 5'hc:dout = 7'b011_0001; 42 | 5'hd:dout = 7'b100_0010; 43 | 5'he:dout = 7'b011_0000; 44 | 5'hf:dout = 7'b011_1000; 45 | default:dout = 7'b111_1111; 46 | endcase 47 | 48 | 49 | endmodule -------------------------------------------------------------------------------- /src/lab_2/calculate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/24 16:59:00 7 | // Design Name: 8 | // Module Name: calculate 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module calculate( 24 | input wire [7:0] num1, 25 | input wire [2:0] op, 26 | output [31:0] result 27 | ); 28 | wire [31:0] num2; 29 | wire [31:0] Sign_extend; 30 | 31 | assign num2 = 32'h00000001; 32 | assign Sign_extend={{24{1'b0}},num1[7:0]}; 33 | assign result = (op == 3'b000)? Sign_extend + num2: 34 | (op == 3'b001)? Sign_extend - num2: 35 | (op == 3'b010)? Sign_extend & num2: 36 | (op == 3'b011)? Sign_extend | num2: 37 | (op == 3'b100)? ~Sign_extend: 32'h00000000; 38 | endmodule 39 | -------------------------------------------------------------------------------- /src/lab_2/display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/17 01:12:00 7 | // Design Name: 8 | // Module Name: display 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module display( 23 | input wire clk,reset, 24 | input wire [31:0]s, 25 | output wire [6:0]seg, 26 | output reg [7:0]ans 27 | ); 28 | reg [20:0]count; 29 | reg [4:0]digit; 30 | always@(posedge clk,posedge reset) 31 | if(reset) 32 | count = 0; 33 | else 34 | count = count + 1; 35 | 36 | always @(posedge clk) 37 | case(count[20:18]) 38 | 0:begin 39 | ans = 8'b11111110; 40 | digit = s[3:0]; 41 | end 42 | 43 | 1:begin 44 | ans = 8'b11111101; 45 | digit = s[7:4]; 46 | end 47 | 48 | 2:begin 49 | ans = 8'b11111011; 50 | digit =s[11:8]; 51 | end 52 | 53 | 3:begin 54 | ans = 8'b11110111; 55 | digit = s[15:12]; 56 | end 57 | 58 | 4:begin 59 | ans = 8'b11101111; 60 | digit = s[19:16]; 61 | end 62 | 63 | 5:begin 64 | ans = 8'b11011111; 65 | digit = s[23:20]; 66 | end 67 | 68 | 6:begin 69 | ans = 8'b10111111; 70 | digit =s[27:24]; 71 | end 72 | 73 | 7:begin 74 | ans = 8'b01111111; 75 | digit = s[31:28]; 76 | end 77 | endcase 78 | 79 | seg7 U4(.din(digit),.dout(seg)); 80 | endmodule -------------------------------------------------------------------------------- /src/lab_2/ip/inst_rom/inst_rom.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | inst_rom 10 | 11 | 12 | 4096 13 | 9 14 | 9 15 | 1 16 | 4 17 | 0 18 | 1 19 | 9 20 | 0 21 | 1 22 | 0 23 | NONE 24 | 0 25 | 0 26 | 0 27 | ./ 28 | 0 29 | 0 30 | 0 31 | 0 32 | 0 33 | 0 34 | 0 35 | 0 36 | Estimated Power for IP : 3.375199 mW 37 | artix7 38 | 0 39 | 1 40 | 0 41 | 0 42 | 0 43 | 0 44 | 0 45 | 0 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 0 54 | inst_rom.mem 55 | inst_rom.mif 56 | 0 57 | 1 58 | 3 59 | 0 60 | 1 61 | 512 62 | 512 63 | 32 64 | 32 65 | 0 66 | 0 67 | CE 68 | CE 69 | ALL 70 | 0 71 | 0 72 | 0 73 | 1 74 | 0 75 | 0 76 | 0 77 | 1 78 | 1 79 | 512 80 | 512 81 | WRITE_FIRST 82 | WRITE_FIRST 83 | 32 84 | 32 85 | artix7 86 | 4 87 | Memory_Slave 88 | AXI4_Full 89 | false 90 | Minimum_Area 91 | false 92 | 9 93 | NONE 94 | ../../../../../coe/prgmip32.coe 95 | ALL 96 | inst_rom 97 | false 98 | false 99 | false 100 | false 101 | false 102 | false 103 | false 104 | false 105 | false 106 | Use_ENA_Pin 107 | Always_Enabled 108 | Single_Bit_Error_Injection 109 | true 110 | Native 111 | true 112 | no_mem_loaded 113 | Single_Port_ROM 114 | WRITE_FIRST 115 | WRITE_FIRST 116 | 0 117 | 0 118 | BRAM 119 | 0 120 | 100 121 | 100 122 | 0 123 | 0 124 | 0 125 | 0 126 | 8kx2 127 | false 128 | false 129 | 32 130 | 32 131 | false 132 | false 133 | false 134 | false 135 | 0 136 | false 137 | false 138 | CE 139 | CE 140 | SYNC 141 | false 142 | false 143 | false 144 | false 145 | false 146 | false 147 | false 148 | 512 149 | 32 150 | 32 151 | No_ECC 152 | false 153 | false 154 | false 155 | Stand_Alone 156 | artix7 157 | 158 | xc7a100t 159 | fgg484 160 | VERILOG 161 | 162 | MIXED 163 | -1 164 | 165 | TRUE 166 | TRUE 167 | IP_Flow 168 | 6 169 | TRUE 170 | . 171 | 172 | . 173 | 2017.1 174 | OUT_OF_CONTEXT 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | -------------------------------------------------------------------------------- /src/lab_2/seg7.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/17 01:14:44 7 | // Design Name: 8 | // Module Name: seg7 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module seg7( 23 | input wire [3:0]din, 24 | output reg [6:0]dout 25 | ); 26 | 27 | always@(*) 28 | case(din) 29 | 5'h0:dout = 7'b000_0001; 30 | 5'h1:dout = 7'b100_1111; 31 | 5'h2:dout = 7'b001_0010; 32 | 5'h3:dout = 7'b000_0110; 33 | 5'h4:dout = 7'b100_1100; 34 | 5'h5:dout = 7'b010_0100; 35 | 5'h6:dout = 7'b010_0000; 36 | 5'h7:dout = 7'b000_1111; 37 | 5'h8:dout = 7'b000_0000; 38 | 5'h9:dout = 7'b000_0100; 39 | 5'ha:dout = 7'b000_1000; 40 | 5'hb:dout = 7'b110_0000; 41 | 5'hc:dout = 7'b011_0001; 42 | 5'hd:dout = 7'b100_0010; 43 | 5'he:dout = 7'b011_0000; 44 | 5'hf:dout = 7'b011_1000; 45 | default:dout = 7'b111_1111; 46 | endcase 47 | 48 | 49 | endmodule -------------------------------------------------------------------------------- /src/lab_2/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/09/25 10:35:04 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input clk, 25 | input rst, 26 | input [2:0] op, 27 | input [7:0] num1, 28 | output [7:0] ans, 29 | output [6:0] seg 30 | ); 31 | wire [31:0] s; 32 | calculate U1(.num1(num1),.op(op),.result(s)); 33 | 34 | display U2(.clk(clk),.reset(rst),.s(s),.ans(ans),.seg(seg)); 35 | endmodule 36 | -------------------------------------------------------------------------------- /src/lab_3/adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:25:38 7 | // Design Name: 8 | // Module Name: adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module adder( 24 | input wire[31:0] a,b, 25 | output wire[31:0] y 26 | ); 27 | 28 | assign y = a + b; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_3/alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:52:16 7 | // Design Name: 8 | // Module Name: alu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module alu( 24 | input wire[31:0] a,b, 25 | input wire[2:0] op, 26 | output reg[31:0] y, 27 | output reg overflow, 28 | output wire zero 29 | ); 30 | 31 | wire[31:0] s,bout; 32 | assign bout = op[2] ? ~b : b; 33 | assign s = a + bout + op[2]; 34 | always @(*) begin 35 | case (op[1:0]) 36 | 2'b00: y <= a & bout; 37 | 2'b01: y <= a | bout; 38 | 2'b10: y <= s; 39 | 2'b11: y <= s[31]; 40 | default : y <= 32'b0; 41 | endcase 42 | end 43 | assign zero = (y == 32'b0); 44 | 45 | always @(*) begin 46 | case (op[2:1]) 47 | 2'b01:overflow <= a[31] & b[31] & ~s[31] | 48 | ~a[31] & ~b[31] & s[31]; 49 | 2'b11:overflow <= ~a[31] & b[31] & s[31] | 50 | a[31] & ~b[31] & ~s[31]; 51 | default : overflow <= 1'b0; 52 | endcase 53 | end 54 | endmodule 55 | -------------------------------------------------------------------------------- /src/lab_3/aludec.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/23 15:27:24 7 | // Design Name: 8 | // Module Name: aludec 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module aludec( 24 | input wire[5:0] funct, 25 | input wire[1:0] aluop, 26 | output reg[2:0] alucontrol 27 | ); 28 | always @(*) begin 29 | case (aluop) 30 | 2'b00: alucontrol <= 3'b010;//add (for lw/sw/addi) 31 | 2'b01: alucontrol <= 3'b110;//sub (for beq) 32 | default : case (funct) 33 | 6'b100000:alucontrol <= 3'b010; //add 34 | 6'b100010:alucontrol <= 3'b110; //sub 35 | 6'b100100:alucontrol <= 3'b000; //and 36 | 6'b100101:alucontrol <= 3'b001; //or 37 | 6'b101010:alucontrol <= 3'b111; //slt 38 | default: alucontrol <= 3'b000; 39 | endcase 40 | endcase 41 | 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /src/lab_3/controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/23 15:21:30 7 | // Design Name: 8 | // Module Name: controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module controller( 24 | input wire[5:0] op,funct, 25 | input wire zero, 26 | output wire memtoreg,memwrite, 27 | output wire pcsrc,alusrc, 28 | output wire regdst,regwrite, 29 | output wire jump, 30 | output wire[2:0] alucontrol 31 | ); 32 | wire[1:0] aluop; 33 | wire branch; 34 | 35 | maindec md(op,memtoreg,memwrite,branch,alusrc,regdst,regwrite,jump,aluop); 36 | aludec ad(funct,aluop,alucontrol); 37 | 38 | assign pcsrc = branch & zero; 39 | endmodule 40 | -------------------------------------------------------------------------------- /src/lab_3/datapath.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 15:12:22 7 | // Design Name: 8 | // Module Name: datapath 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module datapath( 24 | input wire clk,rst, 25 | input wire memtoreg,pcsrc, 26 | input wire alusrc,regdst, 27 | input wire regwrite,jump, 28 | input wire[2:0] alucontrol, 29 | output wire overflow,zero, 30 | output wire[31:0] pc, 31 | input wire[31:0] instr, 32 | output wire[31:0] aluout,writedata, 33 | input wire[31:0] readdata 34 | ); 35 | 36 | wire[4:0] writereg; 37 | wire[31:0] pcnext,pcnextbr,pcplus4,pcbranch; 38 | wire[31:0] signimm,signimmsh; 39 | wire[31:0] srca,srcb; 40 | wire[31:0] result; 41 | 42 | flopr #(32) pcreg(clk,rst,pcnext,pc); 43 | adder pcadd1(pc,32'b100,pcplus4); 44 | sl2 immsh(signimm,signimmsh); 45 | adder pcadd2(pcplus4,signimmsh,pcbranch); 46 | mux2 #(32) pcbrmux(pcplus4,pcbranch,pcsrc,pcnextbr); 47 | mux2 #(32) pcmux(pcnextbr,{pcplus4[31:28],instr[25:0],2'b00},jump,pcnext); 48 | 49 | regfile rf(clk,regwrite,instr[25:21],instr[20:16],writereg,result,srca,writedata); 50 | mux2 #(5) wrmux(instr[20:16],instr[15:11],regdst,writereg); 51 | mux2 #(32) resmux(aluout,readdata,memtoreg,result); 52 | signext se(instr[15:0],signimm); 53 | 54 | mux2 #(32) srcbmux(writedata,signimm,alusrc,srcb); 55 | alu alu(srca,srcb,alucontrol,aluout,overflow,zero); 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /src/lab_3/flopr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:32:42 7 | // Design Name: 8 | // Module Name: flopr 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module flopr #(parameter WIDTH = 8)( 24 | input wire clk,rst, 25 | input wire[WIDTH-1:0] d, 26 | output reg[WIDTH-1:0] q 27 | ); 28 | always @(negedge clk,posedge rst) begin 29 | if(rst) begin 30 | q <= 0; 31 | end else begin 32 | q <= d; 33 | end 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /src/lab_3/ip/.Xil/.inst_mem.xcix.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/lvyufeng/step_into_mips/bfb060a2924959b5f92d16be4c22a457b38ca589/src/lab_3/ip/.Xil/.inst_mem.xcix.lock -------------------------------------------------------------------------------- /src/lab_3/ip/data_mem/data_mem.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | data_mem 10 | 11 | 12 | 4096 13 | 1 14 | 0 15 | 0 16 | 0 17 | 18 | 1 19 | 100000000 20 | 0 21 | 0 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 1 31 | 1 32 | 1 33 | 1 34 | 1 35 | 0.000 36 | AXI4LITE 37 | READ_WRITE 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 1 44 | 0 45 | 0 46 | 0 47 | 48 | 1 49 | 100000000 50 | 0 51 | 0 52 | 0 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 0 59 | 0 60 | 1 61 | 1 62 | 1 63 | 1 64 | 1 65 | 0.000 66 | AXI4LITE 67 | READ_WRITE 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | OTHER 74 | NONE 75 | 8192 76 | 32 77 | 78 | OTHER 79 | NONE 80 | 8192 81 | 32 82 | 83 | 84 | 100000000 85 | 0.000 86 | 16 87 | 16 88 | 1 89 | 4 90 | 0 91 | 1 92 | 9 93 | 0 94 | 0 95 | 58 96 | NONE 97 | 0 98 | 0 99 | 0 100 | ./ 101 | 0 102 | 0 103 | 0 104 | 0 105 | 0 106 | 0 107 | 0 108 | 0 109 | Estimated Power for IP : 19.294452 mW 110 | artix7 111 | 0 112 | 0 113 | 0 114 | 0 115 | 1 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | data_mem.mem 128 | no_coe_file_loaded 129 | 0 130 | 0 131 | 0 132 | 0 133 | 1 134 | 65535 135 | 65535 136 | 32 137 | 32 138 | 0 139 | 0 140 | CE 141 | CE 142 | ALL 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 1 151 | 1 152 | 65535 153 | 65535 154 | WRITE_FIRST 155 | WRITE_FIRST 156 | 32 157 | 32 158 | artix7 159 | 4 160 | Memory_Slave 161 | AXI4_Full 162 | false 163 | Minimum_Area 164 | false 165 | 9 166 | NONE 167 | no_coe_file_loaded 168 | ALL 169 | data_mem 170 | false 171 | false 172 | false 173 | false 174 | false 175 | false 176 | false 177 | false 178 | false 179 | Always_Enabled 180 | Always_Enabled 181 | Single_Bit_Error_Injection 182 | false 183 | Native 184 | false 185 | no_mem_loaded 186 | Single_Port_RAM 187 | WRITE_FIRST 188 | WRITE_FIRST 189 | 0 190 | 0 191 | BRAM 192 | 0 193 | 100 194 | 100 195 | 50 196 | 0 197 | 0 198 | 0 199 | 8kx2 200 | false 201 | false 202 | 32 203 | 32 204 | false 205 | true 206 | false 207 | false 208 | 0 209 | false 210 | false 211 | CE 212 | CE 213 | SYNC 214 | false 215 | false 216 | false 217 | false 218 | false 219 | false 220 | false 221 | 65535 222 | 32 223 | 32 224 | No_ECC 225 | false 226 | false 227 | false 228 | Stand_Alone 229 | artix7 230 | 231 | xc7a100t 232 | fgg484 233 | VERILOG 234 | 235 | MIXED 236 | -1 237 | 238 | TRUE 239 | TRUE 240 | IP_Flow 241 | 1 242 | TRUE 243 | . 244 | 245 | . 246 | 2018.1 247 | OUT_OF_CONTEXT 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | -------------------------------------------------------------------------------- /src/lab_3/maindec.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/23 15:21:30 7 | // Design Name: 8 | // Module Name: maindec 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module maindec( 24 | input wire[5:0] op, 25 | 26 | output wire memtoreg,memwrite, 27 | output wire branch,alusrc, 28 | output wire regdst,regwrite, 29 | output wire jump, 30 | output wire[1:0] aluop 31 | ); 32 | reg[8:0] controls; 33 | assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,aluop} = controls; 34 | always @(*) begin 35 | case (op) 36 | 6'b000000:controls <= 9'b110000010;//R-TYRE 37 | 6'b100011:controls <= 9'b101001000;//LW 38 | 6'b101011:controls <= 9'b001010000;//SW 39 | 6'b000100:controls <= 9'b000100001;//BEQ 40 | 6'b001000:controls <= 9'b101000000;//ADDI 41 | 6'b000010:controls <= 9'b000000100;//J 42 | default: controls <= 9'b000000000;//illegal op 43 | endcase 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /src/lab_3/mips.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/07 10:58:03 7 | // Design Name: 8 | // Module Name: mips 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mips( 24 | input wire clk,rst, 25 | output wire[31:0] pc, 26 | input wire[31:0] instr, 27 | output wire memwrite, 28 | output wire[31:0] aluout,writedata, 29 | input wire[31:0] readdata 30 | ); 31 | 32 | wire memtoreg,alusrc,regdst,regwrite,jump,pcsrc,zero,overflow; 33 | wire[2:0] alucontrol; 34 | 35 | controller c(instr[31:26],instr[5:0],zero,memtoreg, 36 | memwrite,pcsrc,alusrc,regdst,regwrite,jump,alucontrol); 37 | datapath dp(clk,rst,memtoreg,pcsrc,alusrc, 38 | regdst,regwrite,jump,alucontrol,overflow,zero,pc,instr,aluout,writedata,readdata); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /src/lab_3/mux2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:44:10 7 | // Design Name: 8 | // Module Name: mux2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mux2 #(parameter WIDTH = 8)( 24 | input wire[WIDTH-1:0] d0,d1, 25 | input wire s, 26 | output wire[WIDTH-1:0] y 27 | ); 28 | 29 | assign y = s ? d1 : d0; 30 | endmodule 31 | -------------------------------------------------------------------------------- /src/lab_3/regfile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:20:09 7 | // Design Name: 8 | // Module Name: regfile 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module regfile( 24 | input wire clk, 25 | input wire we3, 26 | input wire[4:0] ra1,ra2,wa3, 27 | input wire[31:0] wd3, 28 | output wire[31:0] rd1,rd2 29 | ); 30 | 31 | reg [31:0] rf[31:0]; 32 | 33 | always @(posedge clk) begin 34 | if(we3) begin 35 | rf[wa3] <= wd3; 36 | end 37 | end 38 | 39 | assign rd1 = (ra1 != 0) ? rf[ra1] : 0; 40 | assign rd2 = (ra2 != 0) ? rf[ra2] : 0; 41 | endmodule 42 | -------------------------------------------------------------------------------- /src/lab_3/signext.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:29:33 7 | // Design Name: 8 | // Module Name: signext 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module signext( 24 | input wire[15:0] a, 25 | output wire[31:0] y 26 | ); 27 | 28 | assign y = {{16{a[15]}},a}; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_3/sl2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:28:02 7 | // Design Name: 8 | // Module Name: sl2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module sl2( 24 | input wire[31:0] a, 25 | output wire[31:0] y 26 | ); 27 | 28 | assign y = {a[29:0],2'b00}; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_3/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/07 13:50:53 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input wire clk,rst, 25 | output wire[31:0] writedata,dataadr, 26 | output wire memwrite 27 | ); 28 | 29 | wire[31:0] pc,instr,readdata; 30 | 31 | mips mips(clk,rst,pc,instr,memwrite,dataadr,writedata,readdata); 32 | inst_mem imem(clk,pc[7:2],instr); 33 | data_mem dmem(~clk,memwrite,dataadr,writedata,readdata); 34 | endmodule 35 | -------------------------------------------------------------------------------- /src/lab_4/adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:25:38 7 | // Design Name: 8 | // Module Name: adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module adder( 24 | input wire[31:0] a,b, 25 | output wire[31:0] y 26 | ); 27 | 28 | assign y = a + b; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_4/alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:52:16 7 | // Design Name: 8 | // Module Name: alu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module alu( 24 | input wire[31:0] a,b, 25 | input wire[2:0] op, 26 | output reg[31:0] y, 27 | output reg overflow, 28 | output wire zero 29 | ); 30 | 31 | wire[31:0] s,bout; 32 | assign bout = op[2] ? ~b : b; 33 | assign s = a + bout + op[2]; 34 | always @(*) begin 35 | case (op[1:0]) 36 | 2'b00: y <= a & bout; 37 | 2'b01: y <= a | bout; 38 | 2'b10: y <= s; 39 | 2'b11: y <= s[31]; 40 | default : y <= 32'b0; 41 | endcase 42 | end 43 | assign zero = (y == 32'b0); 44 | 45 | always @(*) begin 46 | case (op[2:1]) 47 | 2'b01:overflow <= a[31] & b[31] & ~s[31] | 48 | ~a[31] & ~b[31] & s[31]; 49 | 2'b11:overflow <= ~a[31] & b[31] & s[31] | 50 | a[31] & ~b[31] & ~s[31]; 51 | default : overflow <= 1'b0; 52 | endcase 53 | end 54 | endmodule 55 | -------------------------------------------------------------------------------- /src/lab_4/aludec.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/23 15:27:24 7 | // Design Name: 8 | // Module Name: aludec 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module aludec( 24 | input wire[5:0] funct, 25 | input wire[1:0] aluop, 26 | output reg[2:0] alucontrol 27 | ); 28 | always @(*) begin 29 | case (aluop) 30 | 2'b00: alucontrol <= 3'b010;//add (for lw/sw/addi) 31 | 2'b01: alucontrol <= 3'b110;//sub (for beq) 32 | default : case (funct) 33 | 6'b100000:alucontrol <= 3'b010; //add 34 | 6'b100010:alucontrol <= 3'b110; //sub 35 | 6'b100100:alucontrol <= 3'b000; //and 36 | 6'b100101:alucontrol <= 3'b001; //or 37 | 6'b101010:alucontrol <= 3'b111; //slt 38 | default: alucontrol <= 3'b000; 39 | endcase 40 | endcase 41 | 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /src/lab_4/controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/23 15:21:30 7 | // Design Name: 8 | // Module Name: controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module controller( 24 | input wire clk,rst, 25 | //decode stage 26 | input wire[5:0] opD,functD, 27 | output wire pcsrcD,branchD,equalD,jumpD, 28 | 29 | //execute stage 30 | input wire flushE, 31 | output wire memtoregE,alusrcE, 32 | output wire regdstE,regwriteE, 33 | output wire[2:0] alucontrolE, 34 | 35 | //mem stage 36 | output wire memtoregM,memwriteM, 37 | regwriteM, 38 | //write back stage 39 | output wire memtoregW,regwriteW 40 | 41 | ); 42 | 43 | //decode stage 44 | wire[1:0] aluopD; 45 | wire memtoregD,memwriteD,alusrcD, 46 | regdstD,regwriteD; 47 | wire[2:0] alucontrolD; 48 | 49 | //execute stage 50 | wire memwriteE; 51 | 52 | maindec md( 53 | opD, 54 | memtoregD,memwriteD, 55 | branchD,alusrcD, 56 | regdstD,regwriteD, 57 | jumpD, 58 | aluopD 59 | ); 60 | aludec ad(functD,aluopD,alucontrolD); 61 | 62 | assign pcsrcD = branchD & equalD; 63 | 64 | //pipeline registers 65 | floprc #(8) regE( 66 | clk, 67 | rst, 68 | flushE, 69 | {memtoregD,memwriteD,alusrcD,regdstD,regwriteD,alucontrolD}, 70 | {memtoregE,memwriteE,alusrcE,regdstE,regwriteE,alucontrolE} 71 | ); 72 | flopr #(8) regM( 73 | clk,rst, 74 | {memtoregE,memwriteE,regwriteE}, 75 | {memtoregM,memwriteM,regwriteM} 76 | ); 77 | flopr #(8) regW( 78 | clk,rst, 79 | {memtoregM,regwriteM}, 80 | {memtoregW,regwriteW} 81 | ); 82 | endmodule 83 | -------------------------------------------------------------------------------- /src/lab_4/datapath.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 15:12:22 7 | // Design Name: 8 | // Module Name: datapath 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module datapath( 24 | input wire clk,rst, 25 | //fetch stage 26 | output wire[31:0] pcF, 27 | input wire[31:0] instrF, 28 | //decode stage 29 | input wire pcsrcD,branchD, 30 | input wire jumpD, 31 | output wire equalD, 32 | output wire[5:0] opD,functD, 33 | //execute stage 34 | input wire memtoregE, 35 | input wire alusrcE,regdstE, 36 | input wire regwriteE, 37 | input wire[2:0] alucontrolE, 38 | output wire flushE, 39 | //mem stage 40 | input wire memtoregM, 41 | input wire regwriteM, 42 | output wire[31:0] aluoutM,writedataM, 43 | input wire[31:0] readdataM, 44 | //writeback stage 45 | input wire memtoregW, 46 | input wire regwriteW 47 | ); 48 | 49 | //fetch stage 50 | wire stallF; 51 | //FD 52 | wire [31:0] pcnextFD,pcnextbrFD,pcplus4F,pcbranchD; 53 | //decode stage 54 | wire [31:0] pcplus4D,instrD; 55 | wire forwardaD,forwardbD; 56 | wire [4:0] rsD,rtD,rdD; 57 | wire flushD,stallD; 58 | wire [31:0] signimmD,signimmshD; 59 | wire [31:0] srcaD,srca2D,srcbD,srcb2D; 60 | //execute stage 61 | wire [1:0] forwardaE,forwardbE; 62 | wire [4:0] rsE,rtE,rdE; 63 | wire [4:0] writeregE; 64 | wire [31:0] signimmE; 65 | wire [31:0] srcaE,srca2E,srcbE,srcb2E,srcb3E; 66 | wire [31:0] aluoutE; 67 | //mem stage 68 | wire [4:0] writeregM; 69 | //writeback stage 70 | wire [4:0] writeregW; 71 | wire [31:0] aluoutW,readdataW,resultW; 72 | 73 | //hazard detection 74 | hazard h( 75 | //fetch stage 76 | stallF, 77 | //decode stage 78 | rsD,rtD, 79 | branchD, 80 | forwardaD,forwardbD, 81 | stallD, 82 | //execute stage 83 | rsE,rtE, 84 | writeregE, 85 | regwriteE, 86 | memtoregE, 87 | forwardaE,forwardbE, 88 | flushE, 89 | //mem stage 90 | writeregM, 91 | regwriteM, 92 | memtoregM, 93 | //write back stage 94 | writeregW, 95 | regwriteW 96 | ); 97 | 98 | //next PC logic (operates in fetch an decode) 99 | mux2 #(32) pcbrmux(pcplus4F,pcbranchD,pcsrcD,pcnextbrFD); 100 | mux2 #(32) pcmux(pcnextbrFD, 101 | {pcplus4D[31:28],instrD[25:0],2'b00}, 102 | jumpD,pcnextFD); 103 | 104 | //regfile (operates in decode and writeback) 105 | regfile rf(clk,regwriteW,rsD,rtD,writeregW,resultW,srcaD,srcbD); 106 | 107 | //fetch stage logic 108 | pc #(32) pcreg(clk,rst,~stallF,pcnextFD,pcF); 109 | adder pcadd1(pcF,32'b100,pcplus4F); 110 | //decode stage 111 | flopenr #(32) r1D(clk,rst,~stallD,pcplus4F,pcplus4D); 112 | flopenrc #(32) r2D(clk,rst,~stallD,flushD,instrF,instrD); 113 | signext se(instrD[15:0],signimmD); 114 | sl2 immsh(signimmD,signimmshD); 115 | adder pcadd2(pcplus4D,signimmshD,pcbranchD); 116 | mux2 #(32) forwardamux(srcaD,aluoutM,forwardaD,srca2D); 117 | mux2 #(32) forwardbmux(srcbD,aluoutM,forwardbD,srcb2D); 118 | eqcmp comp(srca2D,srcb2D,equalD); 119 | 120 | assign opD = instrD[31:26]; 121 | assign functD = instrD[5:0]; 122 | assign rsD = instrD[25:21]; 123 | assign rtD = instrD[20:16]; 124 | assign rdD = instrD[15:11]; 125 | 126 | //execute stage 127 | floprc #(32) r1E(clk,rst,flushE,srcaD,srcaE); 128 | floprc #(32) r2E(clk,rst,flushE,srcbD,srcbE); 129 | floprc #(32) r3E(clk,rst,flushE,signimmD,signimmE); 130 | floprc #(5) r4E(clk,rst,flushE,rsD,rsE); 131 | floprc #(5) r5E(clk,rst,flushE,rtD,rtE); 132 | floprc #(5) r6E(clk,rst,flushE,rdD,rdE); 133 | 134 | mux3 #(32) forwardaemux(srcaE,resultW,aluoutM,forwardaE,srca2E); 135 | mux3 #(32) forwardbemux(srcbE,resultW,aluoutM,forwardbE,srcb2E); 136 | mux2 #(32) srcbmux(srcb2E,signimmE,alusrcE,srcb3E); 137 | alu alu(srca2E,srcb3E,alucontrolE,aluoutE); 138 | mux2 #(5) wrmux(rtE,rdE,regdstE,writeregE); 139 | 140 | //mem stage 141 | flopr #(32) r1M(clk,rst,srcb2E,writedataM); 142 | flopr #(32) r2M(clk,rst,aluoutE,aluoutM); 143 | flopr #(5) r3M(clk,rst,writeregE,writeregM); 144 | 145 | //writeback stage 146 | flopr #(32) r1W(clk,rst,aluoutM,aluoutW); 147 | flopr #(32) r2W(clk,rst,readdataM,readdataW); 148 | flopr #(5) r3W(clk,rst,writeregM,writeregW); 149 | mux2 #(32) resmux(aluoutW,readdataW,memtoregW,resultW); 150 | endmodule 151 | -------------------------------------------------------------------------------- /src/lab_4/eqcmp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/23 22:57:01 7 | // Design Name: 8 | // Module Name: eqcmp 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module eqcmp( 24 | input wire [31:0] a,b, 25 | output wire y 26 | ); 27 | 28 | assign y = (a == b) ? 1 : 0; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_4/flopenr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/23 22:54:57 7 | // Design Name: 8 | // Module Name: flopenr 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module flopenr #(parameter WIDTH = 8)( 24 | input wire clk,rst,en, 25 | input wire[WIDTH-1:0] d, 26 | output reg[WIDTH-1:0] q 27 | ); 28 | always @(posedge clk) begin 29 | if(rst) begin 30 | q <= 0; 31 | end else if(en) begin 32 | /* code */ 33 | q <= d; 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /src/lab_4/flopenrc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/22 09:59:26 7 | // Design Name: 8 | // Module Name: flopenrc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | //flip-flop with enable,rst,clear 23 | module flopenrc #(parameter WIDTH = 8)( 24 | input wire clk,rst,en,clear, 25 | input wire[WIDTH-1:0] d, 26 | output reg[WIDTH-1:0] q 27 | ); 28 | always @(posedge clk) begin 29 | if(rst) begin 30 | q <= 0; 31 | end else if(clear) begin 32 | q <= 0; 33 | end else if(en) begin 34 | /* code */ 35 | q <= d; 36 | end 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /src/lab_4/flopr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:32:42 7 | // Design Name: 8 | // Module Name: flopr 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module flopr #(parameter WIDTH = 8)( 24 | input wire clk,rst, 25 | input wire[WIDTH-1:0] d, 26 | output reg[WIDTH-1:0] q 27 | ); 28 | always @(posedge clk,posedge rst) begin 29 | if(rst) begin 30 | q <= 0; 31 | end else begin 32 | q <= d; 33 | end 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /src/lab_4/floprc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/22 09:53:32 7 | // Design Name: 8 | // Module Name: floprc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module floprc #(parameter WIDTH = 8)( 24 | input wire clk,rst,clear, 25 | input wire[WIDTH-1:0] d, 26 | output reg[WIDTH-1:0] q 27 | ); 28 | 29 | always @(posedge clk,posedge rst) begin 30 | if(rst) begin 31 | q <= 0; 32 | end else if (clear)begin 33 | q <= 0; 34 | end else begin 35 | q <= d; 36 | end 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /src/lab_4/hazard.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/22 10:23:13 7 | // Design Name: 8 | // Module Name: hazard 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module hazard( 24 | //fetch stage 25 | output wire stallF, 26 | //decode stage 27 | input wire[4:0] rsD,rtD, 28 | input wire branchD, 29 | output wire forwardaD,forwardbD, 30 | output wire stallD, 31 | //execute stage 32 | input wire[4:0] rsE,rtE, 33 | input wire[4:0] writeregE, 34 | input wire regwriteE, 35 | input wire memtoregE, 36 | output reg[1:0] forwardaE,forwardbE, 37 | output wire flushE, 38 | //mem stage 39 | input wire[4:0] writeregM, 40 | input wire regwriteM, 41 | input wire memtoregM, 42 | 43 | //write back stage 44 | input wire[4:0] writeregW, 45 | input wire regwriteW 46 | ); 47 | 48 | wire lwstallD,branchstallD; 49 | 50 | //forwarding sources to D stage (branch equality) 51 | assign forwardaD = (rsD != 0 & rsD == writeregM & regwriteM); 52 | assign forwardbD = (rtD != 0 & rtD == writeregM & regwriteM); 53 | 54 | //forwarding sources to E stage (ALU) 55 | 56 | always @(*) begin 57 | forwardaE = 2'b00; 58 | forwardbE = 2'b00; 59 | if(rsE != 0) begin 60 | /* code */ 61 | if(rsE == writeregM & regwriteM) begin 62 | /* code */ 63 | forwardaE = 2'b10; 64 | end else if(rsE == writeregW & regwriteW) begin 65 | /* code */ 66 | forwardaE = 2'b01; 67 | end 68 | end 69 | if(rtE != 0) begin 70 | /* code */ 71 | if(rtE == writeregM & regwriteM) begin 72 | /* code */ 73 | forwardbE = 2'b10; 74 | end else if(rtE == writeregW & regwriteW) begin 75 | /* code */ 76 | forwardbE = 2'b01; 77 | end 78 | end 79 | end 80 | 81 | //stalls 82 | assign #1 lwstallD = memtoregE & (rtE == rsD | rtE == rtD); 83 | assign #1 branchstallD = branchD & 84 | (regwriteE & 85 | (writeregE == rsD | writeregE == rtD) | 86 | memtoregM & 87 | (writeregM == rsD | writeregM == rtD)); 88 | assign #1 stallD = lwstallD | branchstallD; 89 | assign #1 stallF = stallD; 90 | //stalling D stalls all previous stages 91 | assign #1 flushE = stallD; 92 | //stalling D flushes next stage 93 | // Note: not necessary to stall D stage on store 94 | // if source comes from load; 95 | // instead, another bypass network could 96 | // be added from W to M 97 | endmodule 98 | -------------------------------------------------------------------------------- /src/lab_4/ip/data_mem/data_mem.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | data_mem 10 | 11 | 12 | 4096 13 | 1 14 | 0 15 | 0 16 | 0 17 | 18 | 1 19 | 100000000 20 | 0 21 | 0 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 1 31 | 1 32 | 1 33 | 1 34 | 1 35 | 0.000 36 | AXI4LITE 37 | READ_WRITE 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 1 44 | 0 45 | 0 46 | 0 47 | 48 | 1 49 | 100000000 50 | 0 51 | 0 52 | 0 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 0 59 | 0 60 | 1 61 | 1 62 | 1 63 | 1 64 | 1 65 | 0.000 66 | AXI4LITE 67 | READ_WRITE 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | OTHER 74 | NONE 75 | 8192 76 | 32 77 | READ_WRITE 78 | OTHER 79 | NONE 80 | 8192 81 | 32 82 | READ_WRITE 83 | 84 | 100000000 85 | 0.000 86 | 16 87 | 16 88 | 1 89 | 4 90 | 0 91 | 1 92 | 9 93 | 0 94 | 0 95 | 58 96 | NONE 97 | 0 98 | 0 99 | 0 100 | ./ 101 | 0 102 | 0 103 | 0 104 | 0 105 | 0 106 | 0 107 | 0 108 | 0 109 | Estimated Power for IP : 19.294452 mW 110 | artix7 111 | 0 112 | 0 113 | 0 114 | 0 115 | 1 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | data_mem.mem 128 | no_coe_file_loaded 129 | 0 130 | 0 131 | 0 132 | 0 133 | 1 134 | 65532 135 | 65532 136 | 32 137 | 32 138 | 0 139 | 0 140 | CE 141 | CE 142 | ALL 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 1 151 | 1 152 | 65532 153 | 65532 154 | WRITE_FIRST 155 | WRITE_FIRST 156 | 32 157 | 32 158 | artix7 159 | 4 160 | Memory_Slave 161 | AXI4_Full 162 | false 163 | Minimum_Area 164 | false 165 | 9 166 | NONE 167 | no_coe_file_loaded 168 | ALL 169 | data_mem 170 | false 171 | false 172 | false 173 | false 174 | false 175 | false 176 | false 177 | false 178 | false 179 | Always_Enabled 180 | Always_Enabled 181 | Single_Bit_Error_Injection 182 | false 183 | Native 184 | false 185 | no_mem_loaded 186 | Single_Port_RAM 187 | WRITE_FIRST 188 | WRITE_FIRST 189 | 0 190 | 0 191 | BRAM 192 | 0 193 | 100 194 | 100 195 | 50 196 | 0 197 | 0 198 | 0 199 | 8kx2 200 | false 201 | false 202 | 32 203 | 32 204 | false 205 | true 206 | false 207 | false 208 | 0 209 | false 210 | false 211 | CE 212 | CE 213 | SYNC 214 | false 215 | false 216 | false 217 | false 218 | false 219 | false 220 | false 221 | 65532 222 | 32 223 | 32 224 | No_ECC 225 | false 226 | false 227 | false 228 | Stand_Alone 229 | artix7 230 | 231 | xc7a100t 232 | fgg484 233 | VERILOG 234 | 235 | MIXED 236 | -1 237 | 238 | TRUE 239 | TRUE 240 | IP_Flow 241 | 0 242 | TRUE 243 | . 244 | 245 | . 246 | 2017.3 247 | OUT_OF_CONTEXT 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | -------------------------------------------------------------------------------- /src/lab_4/maindec.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/10/23 15:21:30 7 | // Design Name: 8 | // Module Name: maindec 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module maindec( 24 | input wire[5:0] op, 25 | 26 | output wire memtoreg,memwrite, 27 | output wire branch,alusrc, 28 | output wire regdst,regwrite, 29 | output wire jump, 30 | output wire[1:0] aluop 31 | ); 32 | reg[8:0] controls; 33 | assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,aluop} = controls; 34 | always @(*) begin 35 | case (op) 36 | 6'b000000:controls <= 9'b110000010;//R-TYRE 37 | 6'b100011:controls <= 9'b101001000;//LW 38 | 6'b101011:controls <= 9'b001010000;//SW 39 | 6'b000100:controls <= 9'b000100001;//BEQ 40 | 6'b001000:controls <= 9'b101000000;//ADDI 41 | 42 | 6'b000010:controls <= 9'b000000100;//J 43 | default: controls <= 9'b000000000;//illegal op 44 | endcase 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /src/lab_4/mips.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/07 10:58:03 7 | // Design Name: 8 | // Module Name: mips 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mips( 24 | input wire clk,rst, 25 | output wire[31:0] pcF, 26 | input wire[31:0] instrF, 27 | output wire memwriteM, 28 | output wire[31:0] aluoutM,writedataM, 29 | input wire[31:0] readdataM 30 | ); 31 | 32 | wire [5:0] opD,functD; 33 | wire regdstE,alusrcE,pcsrcD,memtoregE,memtoregM,memtoregW, 34 | regwriteE,regwriteM,regwriteW; 35 | wire [2:0] alucontrolE; 36 | wire flushE,equalD; 37 | 38 | controller c( 39 | clk,rst, 40 | //decode stage 41 | opD,functD, 42 | pcsrcD,branchD,equalD,jumpD, 43 | 44 | //execute stage 45 | flushE, 46 | memtoregE,alusrcE, 47 | regdstE,regwriteE, 48 | alucontrolE, 49 | 50 | //mem stage 51 | memtoregM,memwriteM, 52 | regwriteM, 53 | //write back stage 54 | memtoregW,regwriteW 55 | ); 56 | datapath dp( 57 | clk,rst, 58 | //fetch stage 59 | pcF, 60 | instrF, 61 | //decode stage 62 | pcsrcD,branchD, 63 | jumpD, 64 | equalD, 65 | opD,functD, 66 | //execute stage 67 | memtoregE, 68 | alusrcE,regdstE, 69 | regwriteE, 70 | alucontrolE, 71 | flushE, 72 | //mem stage 73 | memtoregM, 74 | regwriteM, 75 | aluoutM,writedataM, 76 | readdataM, 77 | //writeback stage 78 | memtoregW, 79 | regwriteW 80 | ); 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /src/lab_4/mux2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:44:10 7 | // Design Name: 8 | // Module Name: mux2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mux2 #(parameter WIDTH = 8)( 24 | input wire[WIDTH-1:0] d0,d1, 25 | input wire s, 26 | output wire[WIDTH-1:0] y 27 | ); 28 | 29 | assign y = s ? d1 : d0; 30 | endmodule 31 | -------------------------------------------------------------------------------- /src/lab_4/mux3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/23 23:04:23 7 | // Design Name: 8 | // Module Name: mux3 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mux3 #(parameter WIDTH = 8)( 24 | input wire[WIDTH-1:0] d0,d1,d2, 25 | input wire[1:0] s, 26 | output wire[WIDTH-1:0] y 27 | ); 28 | 29 | assign y = (s == 2'b00) ? d0 : 30 | (s == 2'b01) ? d1: 31 | (s == 2'b10) ? d2: d0; 32 | endmodule 33 | -------------------------------------------------------------------------------- /src/lab_4/pc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/26 21:25:26 7 | // Design Name: 8 | // Module Name: pc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module pc #(parameter WIDTH = 8)( 24 | input wire clk,rst,en, 25 | input wire[WIDTH-1:0] d, 26 | output reg[WIDTH-1:0] q 27 | ); 28 | always @(posedge clk,posedge rst) begin 29 | if(rst) begin 30 | q <= 0; 31 | end else if(en) begin 32 | /* code */ 33 | q <= d; 34 | end 35 | end 36 | endmodule -------------------------------------------------------------------------------- /src/lab_4/regfile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:20:09 7 | // Design Name: 8 | // Module Name: regfile 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module regfile( 24 | input wire clk, 25 | input wire we3, 26 | input wire[4:0] ra1,ra2,wa3, 27 | input wire[31:0] wd3, 28 | output wire[31:0] rd1,rd2 29 | ); 30 | 31 | reg [31:0] rf[31:0]; 32 | 33 | always @(negedge clk) begin 34 | if(we3) begin 35 | rf[wa3] <= wd3; 36 | end 37 | end 38 | 39 | assign rd1 = (ra1 != 0) ? rf[ra1] : 0; 40 | assign rd2 = (ra2 != 0) ? rf[ra2] : 0; 41 | endmodule 42 | -------------------------------------------------------------------------------- /src/lab_4/signext.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:29:33 7 | // Design Name: 8 | // Module Name: signext 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module signext( 24 | input wire[15:0] a, 25 | output wire[31:0] y 26 | ); 27 | 28 | assign y = {{16{a[15]}},a}; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_4/sl2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/02 14:28:02 7 | // Design Name: 8 | // Module Name: sl2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module sl2( 24 | input wire[31:0] a, 25 | output wire[31:0] y 26 | ); 27 | 28 | assign y = {a[29:0],2'b00}; 29 | endmodule 30 | -------------------------------------------------------------------------------- /src/lab_4/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2017/11/07 13:50:53 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input wire clk,rst, 25 | output wire[31:0] writedata,dataadr, 26 | output wire memwrite 27 | ); 28 | 29 | wire[31:0] pc,instr,readdata; 30 | 31 | mips mips(clk,rst,pc,instr,memwrite,dataadr,writedata,readdata); 32 | inst_mem imem(~clk,pc[7:2],instr); 33 | data_mem dmem(~clk,memwrite,dataadr,writedata,readdata); 34 | endmodule 35 | -------------------------------------------------------------------------------- /xpr/lab_1_1.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 100 | 101 | 102 | 103 | 104 | 112 | 113 | 114 | 115 | 116 | 119 | 120 | 122 | 123 | 125 | 126 | 128 | 129 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | -------------------------------------------------------------------------------- /xpr/lab_1_2.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 103 | 104 | 105 | 106 | 107 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 128 | 129 | 130 | 131 | 132 | 135 | 136 | 138 | 139 | 141 | 142 | 144 | 145 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | Vivado Synthesis Defaults 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | Default settings for Implementation. 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | -------------------------------------------------------------------------------- /xpr/lab_2.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 164 | 165 | 166 | 167 | 168 | 171 | 172 | 174 | 175 | 177 | 178 | 180 | 181 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | -------------------------------------------------------------------------------- /xpr/lab_3.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 167 | 168 | 169 | 170 | 171 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 230 | 231 | 232 | 233 | 234 | 237 | 238 | 240 | 241 | 243 | 244 | 246 | 247 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | Vivado Synthesis Defaults 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | Vivado Synthesis Defaults 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | Default settings for Implementation. 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | Default settings for Implementation. 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | --------------------------------------------------------------------------------