├── .gitignore ├── .gitmodules ├── Makefile ├── README.md ├── VexRiscv.v ├── VexRiscv.yaml ├── VexRiscv_Debug.v ├── VexRiscv_Debug.yaml ├── VexRiscv_Full.v ├── VexRiscv_Full.yaml ├── VexRiscv_FullDebug.v ├── VexRiscv_FullDebug.yaml ├── VexRiscv_G.v ├── VexRiscv_G.yaml ├── VexRiscv_IMA.v ├── VexRiscv_IMA.yaml ├── VexRiscv_IMA_wide.v ├── VexRiscv_IMA_wide.yaml ├── VexRiscv_Linux.v ├── VexRiscv_Linux.yaml ├── VexRiscv_LinuxDebug.v ├── VexRiscv_LinuxDebug.yaml ├── VexRiscv_Lite.v ├── VexRiscv_Lite.yaml ├── VexRiscv_LiteDebug.v ├── VexRiscv_LiteDebug.yaml ├── VexRiscv_Min.v ├── VexRiscv_Min.yaml ├── VexRiscv_MinDebug.v ├── VexRiscv_MinDebug.yaml ├── build.sbt ├── project ├── build.properties └── plugins.sbt └── src └── main └── scala └── vexriscv └── GenCoreDefault.scala /.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | *.log 3 | *.bak 4 | 5 | # sbt specific 6 | .cache/ 7 | .history/ 8 | .lib/ 9 | dist/* 10 | target 11 | lib_managed/ 12 | src_managed/ 13 | project/boot/ 14 | project/plugins/project/ 15 | 16 | # Scala-IDE specific 17 | .scala_dependencies 18 | .worksheet 19 | 20 | .idea 21 | out 22 | 23 | # Eclipse 24 | bin/ 25 | .classpath 26 | .project 27 | .settings 28 | .cache-main 29 | 30 | #User 31 | *.cf 32 | *.json 33 | *.vcd 34 | 35 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "ext/VexRiscv"] 2 | path = ext/VexRiscv 3 | url = https://github.com/SpinalHDL/VexRiscv 4 | [submodule "ext/SpinalHDL"] 5 | path = ext/SpinalHDL 6 | url = https://github.com/SpinalHDL/SpinalHDL 7 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | SRC := ${shell find . -type f -name \*.scala} 2 | 3 | all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_IMA.v 4 | 5 | VexRiscv.v: $(SRC) 6 | sbt compile "runMain vexriscv.GenCoreDefault" 7 | 8 | VexRiscv_Debug.v: $(SRC) 9 | sbt compile "runMain vexriscv.GenCoreDefault -d --outputFile VexRiscv_Debug" 10 | 11 | VexRiscv_Lite.v: $(SRC) 12 | sbt compile "runMain vexriscv.GenCoreDefault --iCacheSize 2048 --dCacheSize 0 --mulDiv true --singleCycleMulDiv false --outputFile VexRiscv_Lite" 13 | 14 | VexRiscv_LiteDebug.v: $(SRC) 15 | sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 2048 --dCacheSize 0 --mulDiv true --singleCycleMulDiv false --outputFile VexRiscv_LiteDebug" 16 | 17 | VexRiscv_Min.v: $(SRC) 18 | sbt compile "runMain vexriscv.GenCoreDefault --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_Min" 19 | 20 | VexRiscv_MinDebug.v: $(SRC) 21 | sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug" 22 | 23 | VexRiscv_Full.v: $(SRC) 24 | sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full" 25 | 26 | VexRiscv_FullDebug.v: $(SRC) 27 | sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug" 28 | 29 | VexRiscv_Linux.v: $(SRC) 30 | sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" 31 | 32 | VexRiscv_LinuxDebug.v: $(SRC) 33 | sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal -d --outputFile VexRiscv_LinuxDebug" 34 | 35 | VexRiscv_IMA.v: $(SRC) 36 | sbt compile "runMain vexriscv.GenCoreDefault --atomics true --prediction dynamic_target --dCacheSize 8192 --iCacheSize 8192 --earlyBranch true --pmpRegions 4 --pmpGranularity 4096 --csrPluginConfig secure --outputFile VexRiscv_IMA --privateNamespace true" 37 | 38 | VexRiscv_IMA_wide.v: $(SRC) 39 | sbt compile "runMain vexriscv.GenCoreDefault --atomics true --prediction dynamic_target --dCacheSize 8192 --iCacheSize 8192 --earlyBranch true --widenedBus true --pmpRegions 4 --pmpGranularity 4096 --csrPluginConfig secure --outputFile VexRiscv_IMA_wide --privateNamespace true" 40 | 41 | VexRiscv_G.v: $(SRC) 42 | sbt compile "runMain vexriscv.GenCoreDefault --atomics true --prediction dynamic_target --dCacheSize 8192 --iCacheSize 8192 --fpu true --withDouble true --pmpRegions 4 --pmpGranularity 4096 --csrPluginConfig secure --outputFile VexRiscv_G --privateNamespace true" 43 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | ## General informations 3 | This repository contain a Wishbone VexRiscv configuration in :
4 | src/main/scala/vexriscv GenCoreDefault.scala 5 | 6 | - RV32IM 7 | - 5 stage : F -> D -> E -> M -> WB + fully bypassed 8 | - single cycle ADD/SUB/Bitwise/Shift ALU 9 | - i$ : 4 kB 1 way 10 | - d$ : 4 kB 1 way + victim buffer 11 | - Branch prediction => Static 12 | - branch/jump done in the M stage 13 | - memory load values are bypassed in the WB stage (late result) 14 | - 33 cycle division with bypassing in the M stage (late result) 15 | - single cycle multiplication with bypassing in the WB stage (late result) 16 | - Light subset of the RISC-V machine CSR with an 32 bits external interrupt extension 17 | - Available in normal an -Debug, with the Debug bus exposed 18 | 19 | 20 | ## Requirements 21 | 22 | - Java 8 23 | - SBT (Scala build tool, kind of make file but for scala) 24 | 25 | On Debian => 26 | 27 | ```sh 28 | sudo add-apt-repository -y ppa:openjdk-r/ppa 29 | sudo apt-get update 30 | sudo apt-get install openjdk-8-jdk -y 31 | sudo update-alternatives --config java 32 | sudo update-alternatives --config javac 33 | 34 | echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list 35 | sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823 36 | sudo apt-get update 37 | sudo apt-get install sbt -y 38 | ``` 39 | 40 | ## Usages 41 | 42 | ##### Generate the verilog from default core configuration : 43 | 44 | ```sh 45 | sbt "runMain vexriscv.GenCoreDefault" 46 | ``` 47 | 48 | Note : The first time you run it it will take time to download all dependancies (including Scala itself). You have time to drink a coffee. 49 | 50 | ##### Cleaning SBT : 51 | 52 | ```sh 53 | sbt clean reload 54 | ``` 55 | 56 | ##### Updating the VexRiscv : 57 | 58 | The build.sbt file is the "makefile" of this scala project. In it you can update the following lines to change the VexRiscv version : 59 | 60 | ```scala 61 | lazy val vexRiscv = RootProject(uri("VexRiscvGitRepositoryUrl[#commitHash]")) 62 | ``` 63 | 64 | If you want you can also use a local folder as a VexRiscv version : 65 | 66 | ```scala 67 | lazy val vexRiscv = RootProject(file("local/path/to/the/VexRiscv")) 68 | ``` 69 | 70 | ##### Configuration options : 71 | 72 | VexRiscv supports several configuration options: 73 | 74 | * **-d**: If specified, builds VexRiscv with a debug bus 75 | * **-dCacheSize=**_cacheSize_: Specify the data cache size. Defaults to 4096. 76 | * **-iCacheSize=**_cacheSize_: Specify the instruction cache size. Defaults to 4096. 77 | * **-mulDiv=**true/false: Include multiplication/division circuitry. 78 | * **-singleCycleMulDiv=**true/false: If this option is true, multiplication, division, _and shifting_ are optimized for speed. Otherwise, they are optimized for area. 79 | 80 | As an example, you can build a VexRiscv core with a 2048-byte cache size by running: 81 | 82 | ```sh 83 | sbt "runMain vexriscv.GenCoreDefault -d --iCacheSize=2048" 84 | ``` 85 | 86 | `VexRiscv-Lite.v` was built using: 87 | 88 | ```sh 89 | sbt "runMain vexriscv.GenCoreDefault --iCacheSize 2048 --dCacheSize 0 --mulDiv true --singleCycleMulDiv false" 90 | ``` 91 | -------------------------------------------------------------------------------- /VexRiscv.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_Debug.yaml: -------------------------------------------------------------------------------- 1 | debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} 2 | iBus: !!vexriscv.BusReport 3 | flushInstructions: [4111, 19, 19, 19] 4 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} 5 | kind: cached 6 | -------------------------------------------------------------------------------- /VexRiscv_Full.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_FullDebug.yaml: -------------------------------------------------------------------------------- 1 | debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} 2 | iBus: !!vexriscv.BusReport 3 | flushInstructions: [4111, 19, 19, 19] 4 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} 5 | kind: cached 6 | -------------------------------------------------------------------------------- /VexRiscv_G.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 64, size: 8192} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_IMA.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_IMA_wide.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 64, size: 8192} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_Linux.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_LinuxDebug.yaml: -------------------------------------------------------------------------------- 1 | debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} 2 | iBus: !!vexriscv.BusReport 3 | flushInstructions: [4111, 19, 19, 19] 4 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} 5 | kind: cached 6 | -------------------------------------------------------------------------------- /VexRiscv_Lite.yaml: -------------------------------------------------------------------------------- 1 | iBus: !!vexriscv.BusReport 2 | flushInstructions: [4111, 19, 19, 19] 3 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} 4 | kind: cached 5 | -------------------------------------------------------------------------------- /VexRiscv_LiteDebug.yaml: -------------------------------------------------------------------------------- 1 | debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} 2 | iBus: !!vexriscv.BusReport 3 | flushInstructions: [4111, 19, 19, 19] 4 | info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} 5 | kind: cached 6 | -------------------------------------------------------------------------------- /VexRiscv_Min.v: -------------------------------------------------------------------------------- 1 | // Generator : SpinalHDL v1.3.5 git head : f0505d24810c8661a24530409359554b7cfa271a 2 | // Date : 09/06/2019, 12:34:08 3 | // Component : VexRiscv 4 | 5 | 6 | `define Src1CtrlEnum_defaultEncoding_type [1:0] 7 | `define Src1CtrlEnum_defaultEncoding_RS 2'b00 8 | `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 9 | `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 10 | `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 11 | 12 | `define AluCtrlEnum_defaultEncoding_type [1:0] 13 | `define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 14 | `define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 15 | `define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 16 | 17 | `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] 18 | `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 19 | `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 20 | `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 21 | 22 | `define Src2CtrlEnum_defaultEncoding_type [1:0] 23 | `define Src2CtrlEnum_defaultEncoding_RS 2'b00 24 | `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 25 | `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 26 | `define Src2CtrlEnum_defaultEncoding_PC 2'b11 27 | 28 | `define EnvCtrlEnum_defaultEncoding_type [0:0] 29 | `define EnvCtrlEnum_defaultEncoding_NONE 1'b0 30 | `define EnvCtrlEnum_defaultEncoding_XRET 1'b1 31 | 32 | `define ShiftCtrlEnum_defaultEncoding_type [1:0] 33 | `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 34 | `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 35 | `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 36 | `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 37 | 38 | `define BranchCtrlEnum_defaultEncoding_type [1:0] 39 | `define BranchCtrlEnum_defaultEncoding_INC 2'b00 40 | `define BranchCtrlEnum_defaultEncoding_B 2'b01 41 | `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 42 | `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 43 | 44 | module StreamFifoLowLatency ( 45 | input io_push_valid, 46 | output io_push_ready, 47 | input io_push_payload_error, 48 | input [31:0] io_push_payload_inst, 49 | output reg io_pop_valid, 50 | input io_pop_ready, 51 | output reg io_pop_payload_error, 52 | output reg [31:0] io_pop_payload_inst, 53 | input io_flush, 54 | output [0:0] io_occupancy, 55 | input clk, 56 | input reset); 57 | wire _zz_5_; 58 | wire [0:0] _zz_6_; 59 | reg _zz_1_; 60 | reg pushPtr_willIncrement; 61 | reg pushPtr_willClear; 62 | wire pushPtr_willOverflowIfInc; 63 | wire pushPtr_willOverflow; 64 | reg popPtr_willIncrement; 65 | reg popPtr_willClear; 66 | wire popPtr_willOverflowIfInc; 67 | wire popPtr_willOverflow; 68 | wire ptrMatch; 69 | reg risingOccupancy; 70 | wire empty; 71 | wire full; 72 | wire pushing; 73 | wire popping; 74 | wire [32:0] _zz_2_; 75 | wire [32:0] _zz_3_; 76 | reg [32:0] _zz_4_; 77 | assign _zz_5_ = (! empty); 78 | assign _zz_6_ = _zz_2_[0 : 0]; 79 | always @ (*) begin 80 | _zz_1_ = 1'b0; 81 | if(pushing)begin 82 | _zz_1_ = 1'b1; 83 | end 84 | end 85 | 86 | always @ (*) begin 87 | pushPtr_willIncrement = 1'b0; 88 | if(pushing)begin 89 | pushPtr_willIncrement = 1'b1; 90 | end 91 | end 92 | 93 | always @ (*) begin 94 | pushPtr_willClear = 1'b0; 95 | if(io_flush)begin 96 | pushPtr_willClear = 1'b1; 97 | end 98 | end 99 | 100 | assign pushPtr_willOverflowIfInc = 1'b1; 101 | assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); 102 | always @ (*) begin 103 | popPtr_willIncrement = 1'b0; 104 | if(popping)begin 105 | popPtr_willIncrement = 1'b1; 106 | end 107 | end 108 | 109 | always @ (*) begin 110 | popPtr_willClear = 1'b0; 111 | if(io_flush)begin 112 | popPtr_willClear = 1'b1; 113 | end 114 | end 115 | 116 | assign popPtr_willOverflowIfInc = 1'b1; 117 | assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); 118 | assign ptrMatch = 1'b1; 119 | assign empty = (ptrMatch && (! risingOccupancy)); 120 | assign full = (ptrMatch && risingOccupancy); 121 | assign pushing = (io_push_valid && io_push_ready); 122 | assign popping = (io_pop_valid && io_pop_ready); 123 | assign io_push_ready = (! full); 124 | always @ (*) begin 125 | if(_zz_5_)begin 126 | io_pop_valid = 1'b1; 127 | end else begin 128 | io_pop_valid = io_push_valid; 129 | end 130 | end 131 | 132 | assign _zz_2_ = _zz_3_; 133 | always @ (*) begin 134 | if(_zz_5_)begin 135 | io_pop_payload_error = _zz_6_[0]; 136 | end else begin 137 | io_pop_payload_error = io_push_payload_error; 138 | end 139 | end 140 | 141 | always @ (*) begin 142 | if(_zz_5_)begin 143 | io_pop_payload_inst = _zz_2_[32 : 1]; 144 | end else begin 145 | io_pop_payload_inst = io_push_payload_inst; 146 | end 147 | end 148 | 149 | assign io_occupancy = (risingOccupancy && ptrMatch); 150 | assign _zz_3_ = _zz_4_; 151 | always @ (posedge clk) begin 152 | if(reset) begin 153 | risingOccupancy <= 1'b0; 154 | end else begin 155 | if((pushing != popping))begin 156 | risingOccupancy <= pushing; 157 | end 158 | if(io_flush)begin 159 | risingOccupancy <= 1'b0; 160 | end 161 | end 162 | end 163 | 164 | always @ (posedge clk) begin 165 | if(_zz_1_)begin 166 | _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; 167 | end 168 | end 169 | 170 | endmodule 171 | 172 | module VexRiscv ( 173 | input [31:0] externalResetVector, 174 | input timerInterrupt, 175 | input softwareInterrupt, 176 | input [31:0] externalInterruptArray, 177 | output iBusWishbone_CYC, 178 | output iBusWishbone_STB, 179 | input iBusWishbone_ACK, 180 | output iBusWishbone_WE, 181 | output [29:0] iBusWishbone_ADR, 182 | input [31:0] iBusWishbone_DAT_MISO, 183 | output [31:0] iBusWishbone_DAT_MOSI, 184 | output [3:0] iBusWishbone_SEL, 185 | input iBusWishbone_ERR, 186 | output [1:0] iBusWishbone_BTE, 187 | output [2:0] iBusWishbone_CTI, 188 | output dBusWishbone_CYC, 189 | output dBusWishbone_STB, 190 | input dBusWishbone_ACK, 191 | output dBusWishbone_WE, 192 | output [29:0] dBusWishbone_ADR, 193 | input [31:0] dBusWishbone_DAT_MISO, 194 | output [31:0] dBusWishbone_DAT_MOSI, 195 | output reg [3:0] dBusWishbone_SEL, 196 | input dBusWishbone_ERR, 197 | output [1:0] dBusWishbone_BTE, 198 | output [2:0] dBusWishbone_CTI, 199 | input clk, 200 | input reset); 201 | wire _zz_163_; 202 | reg [31:0] _zz_164_; 203 | reg [31:0] _zz_165_; 204 | reg [31:0] _zz_166_; 205 | wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; 206 | wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; 207 | wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; 208 | wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; 209 | wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; 210 | wire _zz_167_; 211 | wire _zz_168_; 212 | wire _zz_169_; 213 | wire _zz_170_; 214 | wire _zz_171_; 215 | wire _zz_172_; 216 | wire _zz_173_; 217 | wire [1:0] _zz_174_; 218 | wire _zz_175_; 219 | wire _zz_176_; 220 | wire _zz_177_; 221 | wire _zz_178_; 222 | wire _zz_179_; 223 | wire _zz_180_; 224 | wire _zz_181_; 225 | wire _zz_182_; 226 | wire _zz_183_; 227 | wire _zz_184_; 228 | wire _zz_185_; 229 | wire _zz_186_; 230 | wire _zz_187_; 231 | wire _zz_188_; 232 | wire _zz_189_; 233 | wire _zz_190_; 234 | wire [1:0] _zz_191_; 235 | wire _zz_192_; 236 | wire [3:0] _zz_193_; 237 | wire [2:0] _zz_194_; 238 | wire [31:0] _zz_195_; 239 | wire [2:0] _zz_196_; 240 | wire [0:0] _zz_197_; 241 | wire [2:0] _zz_198_; 242 | wire [0:0] _zz_199_; 243 | wire [2:0] _zz_200_; 244 | wire [0:0] _zz_201_; 245 | wire [2:0] _zz_202_; 246 | wire [0:0] _zz_203_; 247 | wire [2:0] _zz_204_; 248 | wire [2:0] _zz_205_; 249 | wire [0:0] _zz_206_; 250 | wire [0:0] _zz_207_; 251 | wire [0:0] _zz_208_; 252 | wire [0:0] _zz_209_; 253 | wire [0:0] _zz_210_; 254 | wire [0:0] _zz_211_; 255 | wire [0:0] _zz_212_; 256 | wire [0:0] _zz_213_; 257 | wire [0:0] _zz_214_; 258 | wire [0:0] _zz_215_; 259 | wire [0:0] _zz_216_; 260 | wire [0:0] _zz_217_; 261 | wire [2:0] _zz_218_; 262 | wire [4:0] _zz_219_; 263 | wire [11:0] _zz_220_; 264 | wire [11:0] _zz_221_; 265 | wire [31:0] _zz_222_; 266 | wire [31:0] _zz_223_; 267 | wire [31:0] _zz_224_; 268 | wire [31:0] _zz_225_; 269 | wire [31:0] _zz_226_; 270 | wire [31:0] _zz_227_; 271 | wire [31:0] _zz_228_; 272 | wire [31:0] _zz_229_; 273 | wire [32:0] _zz_230_; 274 | wire [19:0] _zz_231_; 275 | wire [11:0] _zz_232_; 276 | wire [11:0] _zz_233_; 277 | wire [1:0] _zz_234_; 278 | wire [1:0] _zz_235_; 279 | wire [1:0] _zz_236_; 280 | wire [1:0] _zz_237_; 281 | wire [0:0] _zz_238_; 282 | wire [0:0] _zz_239_; 283 | wire [0:0] _zz_240_; 284 | wire [0:0] _zz_241_; 285 | wire [0:0] _zz_242_; 286 | wire [0:0] _zz_243_; 287 | wire [6:0] _zz_244_; 288 | wire _zz_245_; 289 | wire _zz_246_; 290 | wire [1:0] _zz_247_; 291 | wire [31:0] _zz_248_; 292 | wire _zz_249_; 293 | wire [0:0] _zz_250_; 294 | wire [0:0] _zz_251_; 295 | wire [0:0] _zz_252_; 296 | wire [0:0] _zz_253_; 297 | wire _zz_254_; 298 | wire [0:0] _zz_255_; 299 | wire [18:0] _zz_256_; 300 | wire [31:0] _zz_257_; 301 | wire [31:0] _zz_258_; 302 | wire _zz_259_; 303 | wire _zz_260_; 304 | wire [0:0] _zz_261_; 305 | wire [0:0] _zz_262_; 306 | wire [0:0] _zz_263_; 307 | wire [0:0] _zz_264_; 308 | wire _zz_265_; 309 | wire [0:0] _zz_266_; 310 | wire [15:0] _zz_267_; 311 | wire [31:0] _zz_268_; 312 | wire [31:0] _zz_269_; 313 | wire [31:0] _zz_270_; 314 | wire [31:0] _zz_271_; 315 | wire [31:0] _zz_272_; 316 | wire _zz_273_; 317 | wire [2:0] _zz_274_; 318 | wire [2:0] _zz_275_; 319 | wire _zz_276_; 320 | wire [0:0] _zz_277_; 321 | wire [12:0] _zz_278_; 322 | wire [31:0] _zz_279_; 323 | wire [31:0] _zz_280_; 324 | wire [31:0] _zz_281_; 325 | wire [31:0] _zz_282_; 326 | wire [31:0] _zz_283_; 327 | wire [31:0] _zz_284_; 328 | wire [31:0] _zz_285_; 329 | wire [0:0] _zz_286_; 330 | wire [0:0] _zz_287_; 331 | wire [0:0] _zz_288_; 332 | wire [0:0] _zz_289_; 333 | wire _zz_290_; 334 | wire [0:0] _zz_291_; 335 | wire [8:0] _zz_292_; 336 | wire [31:0] _zz_293_; 337 | wire [31:0] _zz_294_; 338 | wire [31:0] _zz_295_; 339 | wire [31:0] _zz_296_; 340 | wire [31:0] _zz_297_; 341 | wire [0:0] _zz_298_; 342 | wire [1:0] _zz_299_; 343 | wire [1:0] _zz_300_; 344 | wire [1:0] _zz_301_; 345 | wire _zz_302_; 346 | wire [0:0] _zz_303_; 347 | wire [5:0] _zz_304_; 348 | wire [31:0] _zz_305_; 349 | wire [31:0] _zz_306_; 350 | wire [31:0] _zz_307_; 351 | wire [31:0] _zz_308_; 352 | wire [31:0] _zz_309_; 353 | wire [31:0] _zz_310_; 354 | wire [31:0] _zz_311_; 355 | wire [31:0] _zz_312_; 356 | wire [31:0] _zz_313_; 357 | wire _zz_314_; 358 | wire [0:0] _zz_315_; 359 | wire [0:0] _zz_316_; 360 | wire [3:0] _zz_317_; 361 | wire [3:0] _zz_318_; 362 | wire _zz_319_; 363 | wire [0:0] _zz_320_; 364 | wire [2:0] _zz_321_; 365 | wire [31:0] _zz_322_; 366 | wire [31:0] _zz_323_; 367 | wire [31:0] _zz_324_; 368 | wire _zz_325_; 369 | wire [0:0] _zz_326_; 370 | wire [0:0] _zz_327_; 371 | wire _zz_328_; 372 | wire _zz_329_; 373 | wire [0:0] _zz_330_; 374 | wire [0:0] _zz_331_; 375 | wire [5:0] _zz_332_; 376 | wire [5:0] _zz_333_; 377 | wire _zz_334_; 378 | wire _zz_335_; 379 | wire [31:0] _zz_336_; 380 | wire [31:0] _zz_337_; 381 | wire [31:0] _zz_338_; 382 | wire [31:0] _zz_339_; 383 | wire [31:0] _zz_340_; 384 | wire [31:0] _zz_341_; 385 | wire [31:0] _zz_342_; 386 | wire [31:0] _zz_343_; 387 | wire [31:0] _zz_344_; 388 | wire [31:0] _zz_345_; 389 | wire [31:0] _zz_346_; 390 | wire [0:0] _zz_347_; 391 | wire [3:0] _zz_348_; 392 | wire [0:0] _zz_349_; 393 | wire [0:0] _zz_350_; 394 | wire _zz_351_; 395 | wire [31:0] _zz_352_; 396 | wire [31:0] _zz_353_; 397 | wire [31:0] _zz_354_; 398 | wire [31:0] _zz_355_; 399 | wire [31:0] _zz_356_; 400 | wire [31:0] _zz_357_; 401 | wire [31:0] _zz_358_; 402 | wire _zz_359_; 403 | wire [0:0] _zz_360_; 404 | wire [10:0] _zz_361_; 405 | wire [31:0] _zz_362_; 406 | wire [31:0] _zz_363_; 407 | wire [31:0] _zz_364_; 408 | wire _zz_365_; 409 | wire [0:0] _zz_366_; 410 | wire [4:0] _zz_367_; 411 | wire [31:0] _zz_368_; 412 | wire [31:0] _zz_369_; 413 | wire [31:0] _zz_370_; 414 | wire [31:0] _zz_371_; 415 | wire [31:0] _zz_372_; 416 | wire decode_SRC2_FORCE_ZERO; 417 | wire [31:0] writeBack_FORMAL_PC_NEXT; 418 | wire [31:0] memory_FORMAL_PC_NEXT; 419 | wire [31:0] execute_FORMAL_PC_NEXT; 420 | wire [31:0] decode_FORMAL_PC_NEXT; 421 | wire [31:0] decode_RS1; 422 | wire decode_CSR_WRITE_OPCODE; 423 | wire [31:0] execute_BRANCH_CALC; 424 | wire [1:0] memory_MEMORY_ADDRESS_LOW; 425 | wire [1:0] execute_MEMORY_ADDRESS_LOW; 426 | wire execute_BRANCH_DO; 427 | wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; 428 | wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; 429 | wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; 430 | wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; 431 | wire [31:0] memory_MEMORY_READ_DATA; 432 | wire decode_SRC_LESS_UNSIGNED; 433 | wire [31:0] writeBack_REGFILE_WRITE_DATA; 434 | wire [31:0] execute_REGFILE_WRITE_DATA; 435 | wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; 436 | wire `AluCtrlEnum_defaultEncoding_type _zz_4_; 437 | wire `AluCtrlEnum_defaultEncoding_type _zz_5_; 438 | wire `AluCtrlEnum_defaultEncoding_type _zz_6_; 439 | wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; 440 | wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_7_; 441 | wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8_; 442 | wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9_; 443 | wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; 444 | wire `Src2CtrlEnum_defaultEncoding_type _zz_10_; 445 | wire `Src2CtrlEnum_defaultEncoding_type _zz_11_; 446 | wire `Src2CtrlEnum_defaultEncoding_type _zz_12_; 447 | wire decode_IS_CSR; 448 | wire [31:0] decode_RS2; 449 | wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; 450 | wire `EnvCtrlEnum_defaultEncoding_type _zz_14_; 451 | wire `EnvCtrlEnum_defaultEncoding_type _zz_15_; 452 | wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; 453 | wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; 454 | wire `EnvCtrlEnum_defaultEncoding_type _zz_17_; 455 | wire `EnvCtrlEnum_defaultEncoding_type _zz_18_; 456 | wire `EnvCtrlEnum_defaultEncoding_type _zz_19_; 457 | wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; 458 | wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; 459 | wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; 460 | wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; 461 | wire decode_MEMORY_STORE; 462 | wire decode_BYPASSABLE_EXECUTE_STAGE; 463 | wire decode_CSR_READ_OPCODE; 464 | wire execute_BYPASSABLE_MEMORY_STAGE; 465 | wire decode_BYPASSABLE_MEMORY_STAGE; 466 | wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; 467 | wire `BranchCtrlEnum_defaultEncoding_type _zz_23_; 468 | wire `BranchCtrlEnum_defaultEncoding_type _zz_24_; 469 | wire `BranchCtrlEnum_defaultEncoding_type _zz_25_; 470 | wire execute_CSR_READ_OPCODE; 471 | wire execute_CSR_WRITE_OPCODE; 472 | wire execute_IS_CSR; 473 | wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; 474 | wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; 475 | wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; 476 | wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; 477 | wire _zz_28_; 478 | wire _zz_29_; 479 | wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; 480 | wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; 481 | wire [31:0] memory_BRANCH_CALC; 482 | wire memory_BRANCH_DO; 483 | wire [31:0] _zz_31_; 484 | wire [31:0] execute_PC; 485 | wire [31:0] execute_RS1; 486 | wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; 487 | wire `BranchCtrlEnum_defaultEncoding_type _zz_32_; 488 | wire _zz_33_; 489 | wire decode_RS2_USE; 490 | wire decode_RS1_USE; 491 | wire execute_REGFILE_WRITE_VALID; 492 | wire execute_BYPASSABLE_EXECUTE_STAGE; 493 | wire memory_REGFILE_WRITE_VALID; 494 | wire [31:0] memory_INSTRUCTION; 495 | wire memory_BYPASSABLE_MEMORY_STAGE; 496 | wire writeBack_REGFILE_WRITE_VALID; 497 | reg [31:0] _zz_34_; 498 | wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; 499 | wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_; 500 | wire _zz_36_; 501 | wire [31:0] _zz_37_; 502 | wire [31:0] _zz_38_; 503 | wire execute_SRC_LESS_UNSIGNED; 504 | wire execute_SRC2_FORCE_ZERO; 505 | wire execute_SRC_USE_SUB_LESS; 506 | wire [31:0] _zz_39_; 507 | wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; 508 | wire `Src2CtrlEnum_defaultEncoding_type _zz_40_; 509 | wire [31:0] _zz_41_; 510 | wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; 511 | wire `Src1CtrlEnum_defaultEncoding_type _zz_42_; 512 | wire [31:0] _zz_43_; 513 | wire decode_SRC_USE_SUB_LESS; 514 | wire decode_SRC_ADD_ZERO; 515 | wire _zz_44_; 516 | wire [31:0] execute_SRC_ADD_SUB; 517 | wire execute_SRC_LESS; 518 | wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; 519 | wire `AluCtrlEnum_defaultEncoding_type _zz_45_; 520 | wire [31:0] _zz_46_; 521 | wire [31:0] execute_SRC2; 522 | wire [31:0] execute_SRC1; 523 | wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; 524 | wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_; 525 | wire [31:0] _zz_48_; 526 | wire _zz_49_; 527 | reg _zz_50_; 528 | wire [31:0] _zz_51_; 529 | wire [31:0] _zz_52_; 530 | wire [31:0] decode_INSTRUCTION_ANTICIPATED; 531 | reg decode_REGFILE_WRITE_VALID; 532 | wire decode_LEGAL_INSTRUCTION; 533 | wire decode_INSTRUCTION_READY; 534 | wire _zz_53_; 535 | wire `Src2CtrlEnum_defaultEncoding_type _zz_54_; 536 | wire `ShiftCtrlEnum_defaultEncoding_type _zz_55_; 537 | wire _zz_56_; 538 | wire _zz_57_; 539 | wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; 540 | wire _zz_59_; 541 | wire _zz_60_; 542 | wire `EnvCtrlEnum_defaultEncoding_type _zz_61_; 543 | wire `AluCtrlEnum_defaultEncoding_type _zz_62_; 544 | wire _zz_63_; 545 | wire _zz_64_; 546 | wire `Src1CtrlEnum_defaultEncoding_type _zz_65_; 547 | wire _zz_66_; 548 | wire _zz_67_; 549 | wire _zz_68_; 550 | wire _zz_69_; 551 | wire `BranchCtrlEnum_defaultEncoding_type _zz_70_; 552 | wire _zz_71_; 553 | wire writeBack_MEMORY_STORE; 554 | reg [31:0] _zz_72_; 555 | wire writeBack_MEMORY_ENABLE; 556 | wire [1:0] writeBack_MEMORY_ADDRESS_LOW; 557 | wire [31:0] writeBack_MEMORY_READ_DATA; 558 | wire memory_MMU_FAULT; 559 | wire [31:0] memory_MMU_RSP_physicalAddress; 560 | wire memory_MMU_RSP_isIoAccess; 561 | wire memory_MMU_RSP_allowRead; 562 | wire memory_MMU_RSP_allowWrite; 563 | wire memory_MMU_RSP_allowExecute; 564 | wire memory_MMU_RSP_exception; 565 | wire memory_MMU_RSP_refilling; 566 | wire [31:0] memory_PC; 567 | wire memory_ALIGNEMENT_FAULT; 568 | wire [31:0] memory_REGFILE_WRITE_DATA; 569 | wire memory_MEMORY_STORE; 570 | wire memory_MEMORY_ENABLE; 571 | wire [31:0] _zz_73_; 572 | wire [31:0] _zz_74_; 573 | wire _zz_75_; 574 | wire _zz_76_; 575 | wire _zz_77_; 576 | wire _zz_78_; 577 | wire _zz_79_; 578 | wire _zz_80_; 579 | wire execute_MMU_FAULT; 580 | wire [31:0] execute_MMU_RSP_physicalAddress; 581 | wire execute_MMU_RSP_isIoAccess; 582 | wire execute_MMU_RSP_allowRead; 583 | wire execute_MMU_RSP_allowWrite; 584 | wire execute_MMU_RSP_allowExecute; 585 | wire execute_MMU_RSP_exception; 586 | wire execute_MMU_RSP_refilling; 587 | wire _zz_81_; 588 | wire [31:0] execute_SRC_ADD; 589 | wire [1:0] _zz_82_; 590 | wire [31:0] execute_RS2; 591 | wire [31:0] execute_INSTRUCTION; 592 | wire execute_MEMORY_STORE; 593 | wire execute_MEMORY_ENABLE; 594 | wire execute_ALIGNEMENT_FAULT; 595 | wire _zz_83_; 596 | wire decode_MEMORY_ENABLE; 597 | reg [31:0] _zz_84_; 598 | reg [31:0] _zz_85_; 599 | wire [31:0] decode_PC; 600 | wire [31:0] _zz_86_; 601 | wire [31:0] _zz_87_; 602 | wire [31:0] _zz_88_; 603 | wire [31:0] decode_INSTRUCTION; 604 | wire [31:0] _zz_89_; 605 | wire [31:0] writeBack_PC; 606 | wire [31:0] writeBack_INSTRUCTION; 607 | reg decode_arbitration_haltItself; 608 | reg decode_arbitration_haltByOther; 609 | reg decode_arbitration_removeIt; 610 | reg decode_arbitration_flushAll; 611 | wire decode_arbitration_isValid; 612 | wire decode_arbitration_isStuck; 613 | wire decode_arbitration_isStuckByOthers; 614 | wire decode_arbitration_isFlushed; 615 | wire decode_arbitration_isMoving; 616 | wire decode_arbitration_isFiring; 617 | reg execute_arbitration_haltItself; 618 | wire execute_arbitration_haltByOther; 619 | reg execute_arbitration_removeIt; 620 | reg execute_arbitration_flushAll; 621 | reg execute_arbitration_isValid; 622 | wire execute_arbitration_isStuck; 623 | wire execute_arbitration_isStuckByOthers; 624 | wire execute_arbitration_isFlushed; 625 | wire execute_arbitration_isMoving; 626 | wire execute_arbitration_isFiring; 627 | reg memory_arbitration_haltItself; 628 | wire memory_arbitration_haltByOther; 629 | reg memory_arbitration_removeIt; 630 | reg memory_arbitration_flushAll; 631 | reg memory_arbitration_isValid; 632 | wire memory_arbitration_isStuck; 633 | wire memory_arbitration_isStuckByOthers; 634 | wire memory_arbitration_isFlushed; 635 | wire memory_arbitration_isMoving; 636 | wire memory_arbitration_isFiring; 637 | wire writeBack_arbitration_haltItself; 638 | wire writeBack_arbitration_haltByOther; 639 | reg writeBack_arbitration_removeIt; 640 | wire writeBack_arbitration_flushAll; 641 | reg writeBack_arbitration_isValid; 642 | wire writeBack_arbitration_isStuck; 643 | wire writeBack_arbitration_isStuckByOthers; 644 | wire writeBack_arbitration_isFlushed; 645 | wire writeBack_arbitration_isMoving; 646 | wire writeBack_arbitration_isFiring; 647 | wire [31:0] lastStageInstruction /* verilator public */ ; 648 | wire [31:0] lastStagePc /* verilator public */ ; 649 | wire lastStageIsValid /* verilator public */ ; 650 | wire lastStageIsFiring /* verilator public */ ; 651 | reg IBusSimplePlugin_fetcherHalt; 652 | wire IBusSimplePlugin_fetcherflushIt; 653 | reg IBusSimplePlugin_incomingInstruction; 654 | wire IBusSimplePlugin_pcValids_0; 655 | wire IBusSimplePlugin_pcValids_1; 656 | wire IBusSimplePlugin_pcValids_2; 657 | wire IBusSimplePlugin_pcValids_3; 658 | wire iBus_cmd_valid; 659 | wire iBus_cmd_ready; 660 | wire [31:0] iBus_cmd_payload_pc; 661 | wire iBus_rsp_valid; 662 | wire iBus_rsp_payload_error; 663 | wire [31:0] iBus_rsp_payload_inst; 664 | wire IBusSimplePlugin_decodeExceptionPort_valid; 665 | reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; 666 | wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; 667 | wire IBusSimplePlugin_mmuBus_cmd_isValid; 668 | wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress; 669 | wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation; 670 | wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; 671 | wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; 672 | wire IBusSimplePlugin_mmuBus_rsp_allowRead; 673 | wire IBusSimplePlugin_mmuBus_rsp_allowWrite; 674 | wire IBusSimplePlugin_mmuBus_rsp_allowExecute; 675 | wire IBusSimplePlugin_mmuBus_rsp_exception; 676 | wire IBusSimplePlugin_mmuBus_rsp_refilling; 677 | wire IBusSimplePlugin_mmuBus_end; 678 | wire IBusSimplePlugin_mmuBus_busy; 679 | wire IBusSimplePlugin_redoBranch_valid; 680 | wire [31:0] IBusSimplePlugin_redoBranch_payload; 681 | reg DBusSimplePlugin_memoryExceptionPort_valid; 682 | reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; 683 | wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; 684 | wire DBusSimplePlugin_mmuBus_cmd_isValid; 685 | wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; 686 | wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; 687 | wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; 688 | wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; 689 | wire DBusSimplePlugin_mmuBus_rsp_allowRead; 690 | wire DBusSimplePlugin_mmuBus_rsp_allowWrite; 691 | wire DBusSimplePlugin_mmuBus_rsp_allowExecute; 692 | wire DBusSimplePlugin_mmuBus_rsp_exception; 693 | wire DBusSimplePlugin_mmuBus_rsp_refilling; 694 | wire DBusSimplePlugin_mmuBus_end; 695 | wire DBusSimplePlugin_mmuBus_busy; 696 | reg DBusSimplePlugin_redoBranch_valid; 697 | wire [31:0] DBusSimplePlugin_redoBranch_payload; 698 | wire decodeExceptionPort_valid; 699 | wire [3:0] decodeExceptionPort_payload_code; 700 | wire [31:0] decodeExceptionPort_payload_badAddr; 701 | wire BranchPlugin_jumpInterface_valid; 702 | wire [31:0] BranchPlugin_jumpInterface_payload; 703 | wire BranchPlugin_branchExceptionPort_valid; 704 | wire [3:0] BranchPlugin_branchExceptionPort_payload_code; 705 | wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; 706 | reg CsrPlugin_jumpInterface_valid; 707 | reg [31:0] CsrPlugin_jumpInterface_payload; 708 | wire CsrPlugin_exceptionPendings_0; 709 | wire CsrPlugin_exceptionPendings_1; 710 | wire CsrPlugin_exceptionPendings_2; 711 | wire CsrPlugin_exceptionPendings_3; 712 | wire externalInterrupt; 713 | wire contextSwitching; 714 | reg [1:0] CsrPlugin_privilege; 715 | wire CsrPlugin_forceMachineWire; 716 | wire CsrPlugin_allowInterrupts; 717 | wire CsrPlugin_allowException; 718 | wire IBusSimplePlugin_jump_pcLoad_valid; 719 | wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; 720 | wire [3:0] _zz_90_; 721 | wire [3:0] _zz_91_; 722 | wire _zz_92_; 723 | wire _zz_93_; 724 | wire _zz_94_; 725 | wire IBusSimplePlugin_fetchPc_preOutput_valid; 726 | wire IBusSimplePlugin_fetchPc_preOutput_ready; 727 | wire [31:0] IBusSimplePlugin_fetchPc_preOutput_payload; 728 | wire _zz_95_; 729 | wire IBusSimplePlugin_fetchPc_output_valid; 730 | wire IBusSimplePlugin_fetchPc_output_ready; 731 | wire [31:0] IBusSimplePlugin_fetchPc_output_payload; 732 | reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; 733 | reg IBusSimplePlugin_fetchPc_inc; 734 | reg IBusSimplePlugin_fetchPc_propagatePc; 735 | reg [31:0] IBusSimplePlugin_fetchPc_pc; 736 | reg IBusSimplePlugin_fetchPc_samplePcNext; 737 | reg _zz_96_; 738 | reg IBusSimplePlugin_iBusRsp_stages_0_input_valid; 739 | reg IBusSimplePlugin_iBusRsp_stages_0_input_ready; 740 | wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; 741 | wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; 742 | wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; 743 | wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; 744 | reg IBusSimplePlugin_iBusRsp_stages_0_halt; 745 | wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; 746 | wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; 747 | wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; 748 | wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; 749 | wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; 750 | wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; 751 | wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; 752 | wire IBusSimplePlugin_iBusRsp_stages_1_halt; 753 | wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; 754 | wire _zz_97_; 755 | wire _zz_98_; 756 | wire _zz_99_; 757 | wire _zz_100_; 758 | reg _zz_101_; 759 | reg IBusSimplePlugin_iBusRsp_readyForError; 760 | wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; 761 | wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready; 762 | wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; 763 | wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; 764 | wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; 765 | wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; 766 | wire IBusSimplePlugin_injector_decodeInput_valid; 767 | wire IBusSimplePlugin_injector_decodeInput_ready; 768 | wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; 769 | wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; 770 | wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; 771 | wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; 772 | reg _zz_102_; 773 | reg [31:0] _zz_103_; 774 | reg _zz_104_; 775 | reg [31:0] _zz_105_; 776 | reg _zz_106_; 777 | reg IBusSimplePlugin_injector_nextPcCalc_valids_0; 778 | reg IBusSimplePlugin_injector_nextPcCalc_valids_1; 779 | reg IBusSimplePlugin_injector_nextPcCalc_valids_2; 780 | reg IBusSimplePlugin_injector_nextPcCalc_valids_3; 781 | reg IBusSimplePlugin_injector_nextPcCalc_valids_4; 782 | reg IBusSimplePlugin_injector_decodeRemoved; 783 | reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; 784 | reg IBusSimplePlugin_cmd_valid; 785 | wire IBusSimplePlugin_cmd_ready; 786 | wire [31:0] IBusSimplePlugin_cmd_payload_pc; 787 | reg [2:0] IBusSimplePlugin_pendingCmd; 788 | wire [2:0] IBusSimplePlugin_pendingCmdNext; 789 | reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; 790 | reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; 791 | reg IBusSimplePlugin_mmu_joinCtx_allowRead; 792 | reg IBusSimplePlugin_mmu_joinCtx_allowWrite; 793 | reg IBusSimplePlugin_mmu_joinCtx_allowExecute; 794 | reg IBusSimplePlugin_mmu_joinCtx_exception; 795 | reg IBusSimplePlugin_mmu_joinCtx_refilling; 796 | reg [2:0] IBusSimplePlugin_rspJoin_discardCounter; 797 | wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; 798 | wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; 799 | wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; 800 | wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; 801 | wire iBus_rsp_takeWhen_valid; 802 | wire iBus_rsp_takeWhen_payload_error; 803 | wire [31:0] iBus_rsp_takeWhen_payload_inst; 804 | wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; 805 | reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; 806 | wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; 807 | wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; 808 | wire IBusSimplePlugin_rspJoin_join_valid; 809 | wire IBusSimplePlugin_rspJoin_join_ready; 810 | wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; 811 | wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; 812 | wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; 813 | wire IBusSimplePlugin_rspJoin_join_payload_isRvc; 814 | reg IBusSimplePlugin_rspJoin_exceptionDetected; 815 | reg IBusSimplePlugin_rspJoin_redoRequired; 816 | wire _zz_107_; 817 | wire dBus_cmd_valid; 818 | wire dBus_cmd_ready; 819 | wire dBus_cmd_payload_wr; 820 | wire [31:0] dBus_cmd_payload_address; 821 | wire [31:0] dBus_cmd_payload_data; 822 | wire [1:0] dBus_cmd_payload_size; 823 | wire dBus_rsp_ready; 824 | wire dBus_rsp_error; 825 | wire [31:0] dBus_rsp_data; 826 | wire _zz_108_; 827 | reg execute_DBusSimplePlugin_skipCmd; 828 | reg [31:0] _zz_109_; 829 | reg [3:0] _zz_110_; 830 | wire [3:0] execute_DBusSimplePlugin_formalMask; 831 | reg [31:0] writeBack_DBusSimplePlugin_rspShifted; 832 | wire _zz_111_; 833 | reg [31:0] _zz_112_; 834 | wire _zz_113_; 835 | reg [31:0] _zz_114_; 836 | reg [31:0] writeBack_DBusSimplePlugin_rspFormated; 837 | wire [24:0] _zz_115_; 838 | wire _zz_116_; 839 | wire _zz_117_; 840 | wire _zz_118_; 841 | wire _zz_119_; 842 | wire `BranchCtrlEnum_defaultEncoding_type _zz_120_; 843 | wire `Src1CtrlEnum_defaultEncoding_type _zz_121_; 844 | wire `AluCtrlEnum_defaultEncoding_type _zz_122_; 845 | wire `EnvCtrlEnum_defaultEncoding_type _zz_123_; 846 | wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_124_; 847 | wire `ShiftCtrlEnum_defaultEncoding_type _zz_125_; 848 | wire `Src2CtrlEnum_defaultEncoding_type _zz_126_; 849 | wire [4:0] decode_RegFilePlugin_regFileReadAddress1; 850 | wire [4:0] decode_RegFilePlugin_regFileReadAddress2; 851 | wire [31:0] decode_RegFilePlugin_rs1Data; 852 | wire [31:0] decode_RegFilePlugin_rs2Data; 853 | reg lastStageRegFileWrite_valid /* verilator public */ ; 854 | wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; 855 | wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; 856 | reg _zz_127_; 857 | reg [31:0] execute_IntAluPlugin_bitwise; 858 | reg [31:0] _zz_128_; 859 | reg [31:0] _zz_129_; 860 | wire _zz_130_; 861 | reg [19:0] _zz_131_; 862 | wire _zz_132_; 863 | reg [19:0] _zz_133_; 864 | reg [31:0] _zz_134_; 865 | reg [31:0] execute_SrcPlugin_addSub; 866 | wire execute_SrcPlugin_less; 867 | reg execute_LightShifterPlugin_isActive; 868 | wire execute_LightShifterPlugin_isShift; 869 | reg [4:0] execute_LightShifterPlugin_amplitudeReg; 870 | wire [4:0] execute_LightShifterPlugin_amplitude; 871 | wire [31:0] execute_LightShifterPlugin_shiftInput; 872 | wire execute_LightShifterPlugin_done; 873 | reg [31:0] _zz_135_; 874 | reg _zz_136_; 875 | reg _zz_137_; 876 | wire _zz_138_; 877 | reg _zz_139_; 878 | reg [4:0] _zz_140_; 879 | wire execute_BranchPlugin_eq; 880 | wire [2:0] _zz_141_; 881 | reg _zz_142_; 882 | reg _zz_143_; 883 | wire [31:0] execute_BranchPlugin_branch_src1; 884 | wire _zz_144_; 885 | reg [10:0] _zz_145_; 886 | wire _zz_146_; 887 | reg [19:0] _zz_147_; 888 | wire _zz_148_; 889 | reg [18:0] _zz_149_; 890 | reg [31:0] _zz_150_; 891 | wire [31:0] execute_BranchPlugin_branch_src2; 892 | wire [31:0] execute_BranchPlugin_branchAdder; 893 | wire [1:0] CsrPlugin_misa_base; 894 | wire [25:0] CsrPlugin_misa_extensions; 895 | reg [1:0] CsrPlugin_mtvec_mode; 896 | reg [29:0] CsrPlugin_mtvec_base; 897 | reg [31:0] CsrPlugin_mepc; 898 | reg CsrPlugin_mstatus_MIE; 899 | reg CsrPlugin_mstatus_MPIE; 900 | reg [1:0] CsrPlugin_mstatus_MPP; 901 | reg CsrPlugin_mip_MEIP; 902 | reg CsrPlugin_mip_MTIP; 903 | reg CsrPlugin_mip_MSIP; 904 | reg CsrPlugin_mie_MEIE; 905 | reg CsrPlugin_mie_MTIE; 906 | reg CsrPlugin_mie_MSIE; 907 | reg CsrPlugin_mcause_interrupt; 908 | reg [3:0] CsrPlugin_mcause_exceptionCode; 909 | reg [31:0] CsrPlugin_mtval; 910 | reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; 911 | reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; 912 | wire _zz_151_; 913 | wire _zz_152_; 914 | wire _zz_153_; 915 | reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; 916 | reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; 917 | reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; 918 | reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; 919 | reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; 920 | reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; 921 | reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; 922 | reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; 923 | reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; 924 | reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; 925 | wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; 926 | wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; 927 | wire [1:0] _zz_154_; 928 | wire _zz_155_; 929 | wire [1:0] _zz_156_; 930 | wire _zz_157_; 931 | reg CsrPlugin_interrupt_valid; 932 | reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; 933 | reg [1:0] CsrPlugin_interrupt_targetPrivilege; 934 | wire CsrPlugin_exception; 935 | wire CsrPlugin_lastStageWasWfi; 936 | reg CsrPlugin_pipelineLiberator_done; 937 | wire CsrPlugin_interruptJump /* verilator public */ ; 938 | reg CsrPlugin_hadException; 939 | reg [1:0] CsrPlugin_targetPrivilege; 940 | reg [3:0] CsrPlugin_trapCause; 941 | reg [1:0] CsrPlugin_xtvec_mode; 942 | reg [29:0] CsrPlugin_xtvec_base; 943 | wire execute_CsrPlugin_inWfi /* verilator public */ ; 944 | reg execute_CsrPlugin_wfiWake; 945 | wire execute_CsrPlugin_blockedBySideEffects; 946 | reg execute_CsrPlugin_illegalAccess; 947 | reg execute_CsrPlugin_illegalInstruction; 948 | reg [31:0] execute_CsrPlugin_readData; 949 | wire execute_CsrPlugin_writeInstruction; 950 | wire execute_CsrPlugin_readInstruction; 951 | wire execute_CsrPlugin_writeEnable; 952 | wire execute_CsrPlugin_readEnable; 953 | wire [31:0] execute_CsrPlugin_readToWriteData; 954 | reg [31:0] execute_CsrPlugin_writeData; 955 | wire [11:0] execute_CsrPlugin_csrAddress; 956 | reg [31:0] externalInterruptArray_regNext; 957 | reg [31:0] _zz_158_; 958 | wire [31:0] _zz_159_; 959 | reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; 960 | reg execute_to_memory_MMU_RSP_isIoAccess; 961 | reg execute_to_memory_MMU_RSP_allowRead; 962 | reg execute_to_memory_MMU_RSP_allowWrite; 963 | reg execute_to_memory_MMU_RSP_allowExecute; 964 | reg execute_to_memory_MMU_RSP_exception; 965 | reg execute_to_memory_MMU_RSP_refilling; 966 | reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; 967 | reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; 968 | reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; 969 | reg decode_to_execute_MEMORY_ENABLE; 970 | reg execute_to_memory_MEMORY_ENABLE; 971 | reg memory_to_writeBack_MEMORY_ENABLE; 972 | reg decode_to_execute_CSR_READ_OPCODE; 973 | reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; 974 | reg decode_to_execute_MEMORY_STORE; 975 | reg execute_to_memory_MEMORY_STORE; 976 | reg memory_to_writeBack_MEMORY_STORE; 977 | reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; 978 | reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; 979 | reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; 980 | reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; 981 | reg [31:0] decode_to_execute_RS2; 982 | reg decode_to_execute_IS_CSR; 983 | reg [31:0] decode_to_execute_INSTRUCTION; 984 | reg [31:0] execute_to_memory_INSTRUCTION; 985 | reg [31:0] memory_to_writeBack_INSTRUCTION; 986 | reg [31:0] decode_to_execute_PC; 987 | reg [31:0] execute_to_memory_PC; 988 | reg [31:0] memory_to_writeBack_PC; 989 | reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; 990 | reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; 991 | reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; 992 | reg execute_to_memory_ALIGNEMENT_FAULT; 993 | reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; 994 | reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; 995 | reg decode_to_execute_SRC_LESS_UNSIGNED; 996 | reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; 997 | reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; 998 | reg execute_to_memory_BRANCH_DO; 999 | reg decode_to_execute_SRC_USE_SUB_LESS; 1000 | reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; 1001 | reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; 1002 | reg decode_to_execute_REGFILE_WRITE_VALID; 1003 | reg execute_to_memory_REGFILE_WRITE_VALID; 1004 | reg memory_to_writeBack_REGFILE_WRITE_VALID; 1005 | reg [31:0] execute_to_memory_BRANCH_CALC; 1006 | reg decode_to_execute_CSR_WRITE_OPCODE; 1007 | reg [31:0] decode_to_execute_RS1; 1008 | reg [31:0] decode_to_execute_FORMAL_PC_NEXT; 1009 | reg [31:0] execute_to_memory_FORMAL_PC_NEXT; 1010 | reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; 1011 | reg execute_to_memory_MMU_FAULT; 1012 | reg decode_to_execute_SRC2_FORCE_ZERO; 1013 | wire iBus_cmd_m2sPipe_valid; 1014 | wire iBus_cmd_m2sPipe_ready; 1015 | wire [31:0] iBus_cmd_m2sPipe_payload_pc; 1016 | reg _zz_160_; 1017 | reg [31:0] _zz_161_; 1018 | wire dBus_cmd_halfPipe_valid; 1019 | wire dBus_cmd_halfPipe_ready; 1020 | wire dBus_cmd_halfPipe_payload_wr; 1021 | wire [31:0] dBus_cmd_halfPipe_payload_address; 1022 | wire [31:0] dBus_cmd_halfPipe_payload_data; 1023 | wire [1:0] dBus_cmd_halfPipe_payload_size; 1024 | reg dBus_cmd_halfPipe_regs_valid; 1025 | reg dBus_cmd_halfPipe_regs_ready; 1026 | reg dBus_cmd_halfPipe_regs_payload_wr; 1027 | reg [31:0] dBus_cmd_halfPipe_regs_payload_address; 1028 | reg [31:0] dBus_cmd_halfPipe_regs_payload_data; 1029 | reg [1:0] dBus_cmd_halfPipe_regs_payload_size; 1030 | reg [3:0] _zz_162_; 1031 | `ifndef SYNTHESIS 1032 | reg [95:0] decode_SRC1_CTRL_string; 1033 | reg [95:0] _zz_1__string; 1034 | reg [95:0] _zz_2__string; 1035 | reg [95:0] _zz_3__string; 1036 | reg [63:0] decode_ALU_CTRL_string; 1037 | reg [63:0] _zz_4__string; 1038 | reg [63:0] _zz_5__string; 1039 | reg [63:0] _zz_6__string; 1040 | reg [39:0] decode_ALU_BITWISE_CTRL_string; 1041 | reg [39:0] _zz_7__string; 1042 | reg [39:0] _zz_8__string; 1043 | reg [39:0] _zz_9__string; 1044 | reg [23:0] decode_SRC2_CTRL_string; 1045 | reg [23:0] _zz_10__string; 1046 | reg [23:0] _zz_11__string; 1047 | reg [23:0] _zz_12__string; 1048 | reg [31:0] _zz_13__string; 1049 | reg [31:0] _zz_14__string; 1050 | reg [31:0] _zz_15__string; 1051 | reg [31:0] _zz_16__string; 1052 | reg [31:0] decode_ENV_CTRL_string; 1053 | reg [31:0] _zz_17__string; 1054 | reg [31:0] _zz_18__string; 1055 | reg [31:0] _zz_19__string; 1056 | reg [71:0] decode_SHIFT_CTRL_string; 1057 | reg [71:0] _zz_20__string; 1058 | reg [71:0] _zz_21__string; 1059 | reg [71:0] _zz_22__string; 1060 | reg [31:0] decode_BRANCH_CTRL_string; 1061 | reg [31:0] _zz_23__string; 1062 | reg [31:0] _zz_24__string; 1063 | reg [31:0] _zz_25__string; 1064 | reg [31:0] memory_ENV_CTRL_string; 1065 | reg [31:0] _zz_26__string; 1066 | reg [31:0] execute_ENV_CTRL_string; 1067 | reg [31:0] _zz_27__string; 1068 | reg [31:0] writeBack_ENV_CTRL_string; 1069 | reg [31:0] _zz_30__string; 1070 | reg [31:0] execute_BRANCH_CTRL_string; 1071 | reg [31:0] _zz_32__string; 1072 | reg [71:0] execute_SHIFT_CTRL_string; 1073 | reg [71:0] _zz_35__string; 1074 | reg [23:0] execute_SRC2_CTRL_string; 1075 | reg [23:0] _zz_40__string; 1076 | reg [95:0] execute_SRC1_CTRL_string; 1077 | reg [95:0] _zz_42__string; 1078 | reg [63:0] execute_ALU_CTRL_string; 1079 | reg [63:0] _zz_45__string; 1080 | reg [39:0] execute_ALU_BITWISE_CTRL_string; 1081 | reg [39:0] _zz_47__string; 1082 | reg [23:0] _zz_54__string; 1083 | reg [71:0] _zz_55__string; 1084 | reg [39:0] _zz_58__string; 1085 | reg [31:0] _zz_61__string; 1086 | reg [63:0] _zz_62__string; 1087 | reg [95:0] _zz_65__string; 1088 | reg [31:0] _zz_70__string; 1089 | reg [31:0] _zz_120__string; 1090 | reg [95:0] _zz_121__string; 1091 | reg [63:0] _zz_122__string; 1092 | reg [31:0] _zz_123__string; 1093 | reg [39:0] _zz_124__string; 1094 | reg [71:0] _zz_125__string; 1095 | reg [23:0] _zz_126__string; 1096 | reg [31:0] decode_to_execute_BRANCH_CTRL_string; 1097 | reg [71:0] decode_to_execute_SHIFT_CTRL_string; 1098 | reg [31:0] decode_to_execute_ENV_CTRL_string; 1099 | reg [31:0] execute_to_memory_ENV_CTRL_string; 1100 | reg [31:0] memory_to_writeBack_ENV_CTRL_string; 1101 | reg [23:0] decode_to_execute_SRC2_CTRL_string; 1102 | reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; 1103 | reg [63:0] decode_to_execute_ALU_CTRL_string; 1104 | reg [95:0] decode_to_execute_SRC1_CTRL_string; 1105 | `endif 1106 | 1107 | (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; 1108 | assign _zz_167_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); 1109 | assign _zz_168_ = (execute_arbitration_isValid && execute_IS_CSR); 1110 | assign _zz_169_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00)); 1111 | assign _zz_170_ = (! execute_arbitration_isStuckByOthers); 1112 | assign _zz_171_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); 1113 | assign _zz_172_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); 1114 | assign _zz_173_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); 1115 | assign _zz_174_ = writeBack_INSTRUCTION[29 : 28]; 1116 | assign _zz_175_ = (IBusSimplePlugin_fetchPc_preOutput_valid && IBusSimplePlugin_fetchPc_preOutput_ready); 1117 | assign _zz_176_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling); 1118 | assign _zz_177_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); 1119 | assign _zz_178_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); 1120 | assign _zz_179_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); 1121 | assign _zz_180_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); 1122 | assign _zz_181_ = (1'b1 || (! 1'b1)); 1123 | assign _zz_182_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); 1124 | assign _zz_183_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); 1125 | assign _zz_184_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); 1126 | assign _zz_185_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); 1127 | assign _zz_186_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); 1128 | assign _zz_187_ = ((_zz_151_ && 1'b1) && (! 1'b0)); 1129 | assign _zz_188_ = ((_zz_152_ && 1'b1) && (! 1'b0)); 1130 | assign _zz_189_ = ((_zz_153_ && 1'b1) && (! 1'b0)); 1131 | assign _zz_190_ = (! dBus_cmd_halfPipe_regs_valid); 1132 | assign _zz_191_ = writeBack_INSTRUCTION[13 : 12]; 1133 | assign _zz_192_ = execute_INSTRUCTION[13]; 1134 | assign _zz_193_ = (_zz_90_ - (4'b0001)); 1135 | assign _zz_194_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; 1136 | assign _zz_195_ = {29'd0, _zz_194_}; 1137 | assign _zz_196_ = (IBusSimplePlugin_pendingCmd + _zz_198_); 1138 | assign _zz_197_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); 1139 | assign _zz_198_ = {2'd0, _zz_197_}; 1140 | assign _zz_199_ = iBus_rsp_valid; 1141 | assign _zz_200_ = {2'd0, _zz_199_}; 1142 | assign _zz_201_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))); 1143 | assign _zz_202_ = {2'd0, _zz_201_}; 1144 | assign _zz_203_ = iBus_rsp_valid; 1145 | assign _zz_204_ = {2'd0, _zz_203_}; 1146 | assign _zz_205_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); 1147 | assign _zz_206_ = _zz_115_[2 : 2]; 1148 | assign _zz_207_ = _zz_115_[3 : 3]; 1149 | assign _zz_208_ = _zz_115_[4 : 4]; 1150 | assign _zz_209_ = _zz_115_[5 : 5]; 1151 | assign _zz_210_ = _zz_115_[8 : 8]; 1152 | assign _zz_211_ = _zz_115_[10 : 10]; 1153 | assign _zz_212_ = _zz_115_[14 : 14]; 1154 | assign _zz_213_ = _zz_115_[15 : 15]; 1155 | assign _zz_214_ = _zz_115_[18 : 18]; 1156 | assign _zz_215_ = _zz_115_[19 : 19]; 1157 | assign _zz_216_ = _zz_115_[24 : 24]; 1158 | assign _zz_217_ = execute_SRC_LESS; 1159 | assign _zz_218_ = (3'b100); 1160 | assign _zz_219_ = execute_INSTRUCTION[19 : 15]; 1161 | assign _zz_220_ = execute_INSTRUCTION[31 : 20]; 1162 | assign _zz_221_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; 1163 | assign _zz_222_ = ($signed(_zz_223_) + $signed(_zz_226_)); 1164 | assign _zz_223_ = ($signed(_zz_224_) + $signed(_zz_225_)); 1165 | assign _zz_224_ = execute_SRC1; 1166 | assign _zz_225_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); 1167 | assign _zz_226_ = (execute_SRC_USE_SUB_LESS ? _zz_227_ : _zz_228_); 1168 | assign _zz_227_ = (32'b00000000000000000000000000000001); 1169 | assign _zz_228_ = (32'b00000000000000000000000000000000); 1170 | assign _zz_229_ = (_zz_230_ >>> 1); 1171 | assign _zz_230_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; 1172 | assign _zz_231_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; 1173 | assign _zz_232_ = execute_INSTRUCTION[31 : 20]; 1174 | assign _zz_233_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; 1175 | assign _zz_234_ = (_zz_154_ & (~ _zz_235_)); 1176 | assign _zz_235_ = (_zz_154_ - (2'b01)); 1177 | assign _zz_236_ = (_zz_156_ & (~ _zz_237_)); 1178 | assign _zz_237_ = (_zz_156_ - (2'b01)); 1179 | assign _zz_238_ = execute_CsrPlugin_writeData[7 : 7]; 1180 | assign _zz_239_ = execute_CsrPlugin_writeData[3 : 3]; 1181 | assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3]; 1182 | assign _zz_241_ = execute_CsrPlugin_writeData[11 : 11]; 1183 | assign _zz_242_ = execute_CsrPlugin_writeData[7 : 7]; 1184 | assign _zz_243_ = execute_CsrPlugin_writeData[3 : 3]; 1185 | assign _zz_244_ = ({3'd0,_zz_162_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); 1186 | assign _zz_245_ = 1'b1; 1187 | assign _zz_246_ = 1'b1; 1188 | assign _zz_247_ = {_zz_94_,_zz_93_}; 1189 | assign _zz_248_ = (32'b00000000000000000000000001011000); 1190 | assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); 1191 | assign _zz_250_ = _zz_119_; 1192 | assign _zz_251_ = ((decode_INSTRUCTION & _zz_257_) == (32'b00000000000000000000000000000000)); 1193 | assign _zz_252_ = ((decode_INSTRUCTION & _zz_258_) == (32'b00000000000000000101000000010000)); 1194 | assign _zz_253_ = (1'b0); 1195 | assign _zz_254_ = ({_zz_259_,_zz_260_} != (2'b00)); 1196 | assign _zz_255_ = ({_zz_261_,_zz_262_} != (2'b00)); 1197 | assign _zz_256_ = {(_zz_263_ != _zz_264_),{_zz_265_,{_zz_266_,_zz_267_}}}; 1198 | assign _zz_257_ = (32'b00000000000000000000000000100000); 1199 | assign _zz_258_ = (32'b00000000000000000111000001010100); 1200 | assign _zz_259_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); 1201 | assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); 1202 | assign _zz_261_ = ((decode_INSTRUCTION & _zz_268_) == (32'b00000000000000000000000000100000)); 1203 | assign _zz_262_ = ((decode_INSTRUCTION & _zz_269_) == (32'b00000000000000000000000000100000)); 1204 | assign _zz_263_ = ((decode_INSTRUCTION & _zz_270_) == (32'b00000000000000000000000000100000)); 1205 | assign _zz_264_ = (1'b0); 1206 | assign _zz_265_ = ((_zz_271_ == _zz_272_) != (1'b0)); 1207 | assign _zz_266_ = (_zz_273_ != (1'b0)); 1208 | assign _zz_267_ = {(_zz_274_ != _zz_275_),{_zz_276_,{_zz_277_,_zz_278_}}}; 1209 | assign _zz_268_ = (32'b00000000000000000000000000110100); 1210 | assign _zz_269_ = (32'b00000000000000000000000001100100); 1211 | assign _zz_270_ = (32'b00000000000000000000000000100000); 1212 | assign _zz_271_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); 1213 | assign _zz_272_ = (32'b00000000000000000001000000000000); 1214 | assign _zz_273_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); 1215 | assign _zz_274_ = {((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000000000001000000)),{(_zz_280_ == _zz_281_),(_zz_282_ == _zz_283_)}}; 1216 | assign _zz_275_ = (3'b000); 1217 | assign _zz_276_ = (_zz_117_ != (1'b0)); 1218 | assign _zz_277_ = ((_zz_284_ == _zz_285_) != (1'b0)); 1219 | assign _zz_278_ = {({_zz_286_,_zz_287_} != (2'b00)),{(_zz_288_ != _zz_289_),{_zz_290_,{_zz_291_,_zz_292_}}}}; 1220 | assign _zz_279_ = (32'b00000000000000000000000001000100); 1221 | assign _zz_280_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); 1222 | assign _zz_281_ = (32'b00000000000000000010000000010000); 1223 | assign _zz_282_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100)); 1224 | assign _zz_283_ = (32'b01000000000000000000000000110000); 1225 | assign _zz_284_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010000)); 1226 | assign _zz_285_ = (32'b00000000000000000000000001010000); 1227 | assign _zz_286_ = ((decode_INSTRUCTION & _zz_293_) == (32'b00000000000000000110000000010000)); 1228 | assign _zz_287_ = ((decode_INSTRUCTION & _zz_294_) == (32'b00000000000000000100000000010000)); 1229 | assign _zz_288_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000010000000010000)); 1230 | assign _zz_289_ = (1'b0); 1231 | assign _zz_290_ = ((_zz_296_ == _zz_297_) != (1'b0)); 1232 | assign _zz_291_ = ({_zz_298_,_zz_299_} != (3'b000)); 1233 | assign _zz_292_ = {(_zz_300_ != _zz_301_),{_zz_302_,{_zz_303_,_zz_304_}}}; 1234 | assign _zz_293_ = (32'b00000000000000000110000000010100); 1235 | assign _zz_294_ = (32'b00000000000000000101000000010100); 1236 | assign _zz_295_ = (32'b00000000000000000110000000010100); 1237 | assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010000)); 1238 | assign _zz_297_ = (32'b00000000000000000000000000010000); 1239 | assign _zz_298_ = ((decode_INSTRUCTION & _zz_305_) == (32'b00000000000000000000000001000000)); 1240 | assign _zz_299_ = {(_zz_306_ == _zz_307_),(_zz_308_ == _zz_309_)}; 1241 | assign _zz_300_ = {(_zz_310_ == _zz_311_),(_zz_312_ == _zz_313_)}; 1242 | assign _zz_301_ = (2'b00); 1243 | assign _zz_302_ = ({_zz_314_,_zz_118_} != (2'b00)); 1244 | assign _zz_303_ = ({_zz_315_,_zz_316_} != (2'b00)); 1245 | assign _zz_304_ = {(_zz_317_ != _zz_318_),{_zz_319_,{_zz_320_,_zz_321_}}}; 1246 | assign _zz_305_ = (32'b00000000000000000000000001010000); 1247 | assign _zz_306_ = (decode_INSTRUCTION & (32'b00000000000000000011000001000000)); 1248 | assign _zz_307_ = (32'b00000000000000000000000001000000); 1249 | assign _zz_308_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); 1250 | assign _zz_309_ = (32'b00000000000000000000000000000000); 1251 | assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); 1252 | assign _zz_311_ = (32'b00000000000000000000000000100100); 1253 | assign _zz_312_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100)); 1254 | assign _zz_313_ = (32'b00000000000000000001000000010000); 1255 | assign _zz_314_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); 1256 | assign _zz_315_ = ((decode_INSTRUCTION & _zz_322_) == (32'b00000000000000000000000000000100)); 1257 | assign _zz_316_ = _zz_118_; 1258 | assign _zz_317_ = {(_zz_323_ == _zz_324_),{_zz_325_,{_zz_326_,_zz_327_}}}; 1259 | assign _zz_318_ = (4'b0000); 1260 | assign _zz_319_ = ({_zz_328_,_zz_329_} != (2'b00)); 1261 | assign _zz_320_ = ({_zz_330_,_zz_331_} != (2'b00)); 1262 | assign _zz_321_ = {(_zz_332_ != _zz_333_),{_zz_334_,_zz_335_}}; 1263 | assign _zz_322_ = (32'b00000000000000000000000001000100); 1264 | assign _zz_323_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); 1265 | assign _zz_324_ = (32'b00000000000000000000000000000000); 1266 | assign _zz_325_ = ((decode_INSTRUCTION & _zz_336_) == (32'b00000000000000000000000000000000)); 1267 | assign _zz_326_ = (_zz_337_ == _zz_338_); 1268 | assign _zz_327_ = (_zz_339_ == _zz_340_); 1269 | assign _zz_328_ = ((decode_INSTRUCTION & _zz_341_) == (32'b00000000000000000010000000000000)); 1270 | assign _zz_329_ = ((decode_INSTRUCTION & _zz_342_) == (32'b00000000000000000001000000000000)); 1271 | assign _zz_330_ = (_zz_343_ == _zz_344_); 1272 | assign _zz_331_ = (_zz_345_ == _zz_346_); 1273 | assign _zz_332_ = {_zz_116_,{_zz_347_,_zz_348_}}; 1274 | assign _zz_333_ = (6'b000000); 1275 | assign _zz_334_ = ({_zz_349_,_zz_350_} != (2'b00)); 1276 | assign _zz_335_ = (_zz_351_ != (1'b0)); 1277 | assign _zz_336_ = (32'b00000000000000000000000000011000); 1278 | assign _zz_337_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); 1279 | assign _zz_338_ = (32'b00000000000000000010000000000000); 1280 | assign _zz_339_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); 1281 | assign _zz_340_ = (32'b00000000000000000001000000000000); 1282 | assign _zz_341_ = (32'b00000000000000000010000000010000); 1283 | assign _zz_342_ = (32'b00000000000000000101000000000000); 1284 | assign _zz_343_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); 1285 | assign _zz_344_ = (32'b00000000000000000001000001010000); 1286 | assign _zz_345_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); 1287 | assign _zz_346_ = (32'b00000000000000000010000001010000); 1288 | assign _zz_347_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000)); 1289 | assign _zz_348_ = {((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)),{_zz_117_,{(_zz_352_ == _zz_353_),(_zz_354_ == _zz_355_)}}}; 1290 | assign _zz_349_ = _zz_116_; 1291 | assign _zz_350_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); 1292 | assign _zz_351_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); 1293 | assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); 1294 | assign _zz_353_ = (32'b00000000000000000000000000000100); 1295 | assign _zz_354_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); 1296 | assign _zz_355_ = (32'b00000000000000000000000000000000); 1297 | assign _zz_356_ = (32'b00000000000000000001000001111111); 1298 | assign _zz_357_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); 1299 | assign _zz_358_ = (32'b00000000000000000010000001110011); 1300 | assign _zz_359_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); 1301 | assign _zz_360_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); 1302 | assign _zz_361_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_362_) == (32'b00000000000000000000000000000011)),{(_zz_363_ == _zz_364_),{_zz_365_,{_zz_366_,_zz_367_}}}}}}; 1303 | assign _zz_362_ = (32'b00000000000000000101000001011111); 1304 | assign _zz_363_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); 1305 | assign _zz_364_ = (32'b00000000000000000000000001100011); 1306 | assign _zz_365_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); 1307 | assign _zz_366_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); 1308 | assign _zz_367_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_368_) == (32'b00000000000000000101000000110011)),{(_zz_369_ == _zz_370_),(_zz_371_ == _zz_372_)}}}}; 1309 | assign _zz_368_ = (32'b10111110000000000111000001111111); 1310 | assign _zz_369_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); 1311 | assign _zz_370_ = (32'b00000000000000000000000000110011); 1312 | assign _zz_371_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111)); 1313 | assign _zz_372_ = (32'b00010000001000000000000001110011); 1314 | always @ (posedge clk) begin 1315 | if(_zz_50_) begin 1316 | RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; 1317 | end 1318 | end 1319 | 1320 | always @ (posedge clk) begin 1321 | if(_zz_245_) begin 1322 | _zz_164_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; 1323 | end 1324 | end 1325 | 1326 | always @ (posedge clk) begin 1327 | if(_zz_246_) begin 1328 | _zz_165_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; 1329 | end 1330 | end 1331 | 1332 | StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( 1333 | .io_push_valid(iBus_rsp_takeWhen_valid), 1334 | .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), 1335 | .io_push_payload_error(iBus_rsp_takeWhen_payload_error), 1336 | .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst), 1337 | .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), 1338 | .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), 1339 | .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), 1340 | .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst), 1341 | .io_flush(_zz_163_), 1342 | .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), 1343 | .clk(clk), 1344 | .reset(reset) 1345 | ); 1346 | always @(*) begin 1347 | case(_zz_247_) 1348 | 2'b00 : begin 1349 | _zz_166_ = CsrPlugin_jumpInterface_payload; 1350 | end 1351 | 2'b01 : begin 1352 | _zz_166_ = DBusSimplePlugin_redoBranch_payload; 1353 | end 1354 | 2'b10 : begin 1355 | _zz_166_ = BranchPlugin_jumpInterface_payload; 1356 | end 1357 | default : begin 1358 | _zz_166_ = IBusSimplePlugin_redoBranch_payload; 1359 | end 1360 | endcase 1361 | end 1362 | 1363 | `ifndef SYNTHESIS 1364 | always @(*) begin 1365 | case(decode_SRC1_CTRL) 1366 | `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; 1367 | `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; 1368 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; 1369 | `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; 1370 | default : decode_SRC1_CTRL_string = "????????????"; 1371 | endcase 1372 | end 1373 | always @(*) begin 1374 | case(_zz_1_) 1375 | `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; 1376 | `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; 1377 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; 1378 | `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; 1379 | default : _zz_1__string = "????????????"; 1380 | endcase 1381 | end 1382 | always @(*) begin 1383 | case(_zz_2_) 1384 | `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; 1385 | `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; 1386 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; 1387 | `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; 1388 | default : _zz_2__string = "????????????"; 1389 | endcase 1390 | end 1391 | always @(*) begin 1392 | case(_zz_3_) 1393 | `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; 1394 | `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; 1395 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; 1396 | `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; 1397 | default : _zz_3__string = "????????????"; 1398 | endcase 1399 | end 1400 | always @(*) begin 1401 | case(decode_ALU_CTRL) 1402 | `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; 1403 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; 1404 | `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; 1405 | default : decode_ALU_CTRL_string = "????????"; 1406 | endcase 1407 | end 1408 | always @(*) begin 1409 | case(_zz_4_) 1410 | `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_4__string = "ADD_SUB "; 1411 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_4__string = "SLT_SLTU"; 1412 | `AluCtrlEnum_defaultEncoding_BITWISE : _zz_4__string = "BITWISE "; 1413 | default : _zz_4__string = "????????"; 1414 | endcase 1415 | end 1416 | always @(*) begin 1417 | case(_zz_5_) 1418 | `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_5__string = "ADD_SUB "; 1419 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_5__string = "SLT_SLTU"; 1420 | `AluCtrlEnum_defaultEncoding_BITWISE : _zz_5__string = "BITWISE "; 1421 | default : _zz_5__string = "????????"; 1422 | endcase 1423 | end 1424 | always @(*) begin 1425 | case(_zz_6_) 1426 | `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_6__string = "ADD_SUB "; 1427 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_6__string = "SLT_SLTU"; 1428 | `AluCtrlEnum_defaultEncoding_BITWISE : _zz_6__string = "BITWISE "; 1429 | default : _zz_6__string = "????????"; 1430 | endcase 1431 | end 1432 | always @(*) begin 1433 | case(decode_ALU_BITWISE_CTRL) 1434 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; 1435 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; 1436 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; 1437 | default : decode_ALU_BITWISE_CTRL_string = "?????"; 1438 | endcase 1439 | end 1440 | always @(*) begin 1441 | case(_zz_7_) 1442 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_7__string = "XOR_1"; 1443 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_7__string = "OR_1 "; 1444 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_7__string = "AND_1"; 1445 | default : _zz_7__string = "?????"; 1446 | endcase 1447 | end 1448 | always @(*) begin 1449 | case(_zz_8_) 1450 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8__string = "XOR_1"; 1451 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8__string = "OR_1 "; 1452 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8__string = "AND_1"; 1453 | default : _zz_8__string = "?????"; 1454 | endcase 1455 | end 1456 | always @(*) begin 1457 | case(_zz_9_) 1458 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9__string = "XOR_1"; 1459 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9__string = "OR_1 "; 1460 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9__string = "AND_1"; 1461 | default : _zz_9__string = "?????"; 1462 | endcase 1463 | end 1464 | always @(*) begin 1465 | case(decode_SRC2_CTRL) 1466 | `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; 1467 | `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; 1468 | `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; 1469 | `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; 1470 | default : decode_SRC2_CTRL_string = "???"; 1471 | endcase 1472 | end 1473 | always @(*) begin 1474 | case(_zz_10_) 1475 | `Src2CtrlEnum_defaultEncoding_RS : _zz_10__string = "RS "; 1476 | `Src2CtrlEnum_defaultEncoding_IMI : _zz_10__string = "IMI"; 1477 | `Src2CtrlEnum_defaultEncoding_IMS : _zz_10__string = "IMS"; 1478 | `Src2CtrlEnum_defaultEncoding_PC : _zz_10__string = "PC "; 1479 | default : _zz_10__string = "???"; 1480 | endcase 1481 | end 1482 | always @(*) begin 1483 | case(_zz_11_) 1484 | `Src2CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS "; 1485 | `Src2CtrlEnum_defaultEncoding_IMI : _zz_11__string = "IMI"; 1486 | `Src2CtrlEnum_defaultEncoding_IMS : _zz_11__string = "IMS"; 1487 | `Src2CtrlEnum_defaultEncoding_PC : _zz_11__string = "PC "; 1488 | default : _zz_11__string = "???"; 1489 | endcase 1490 | end 1491 | always @(*) begin 1492 | case(_zz_12_) 1493 | `Src2CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; 1494 | `Src2CtrlEnum_defaultEncoding_IMI : _zz_12__string = "IMI"; 1495 | `Src2CtrlEnum_defaultEncoding_IMS : _zz_12__string = "IMS"; 1496 | `Src2CtrlEnum_defaultEncoding_PC : _zz_12__string = "PC "; 1497 | default : _zz_12__string = "???"; 1498 | endcase 1499 | end 1500 | always @(*) begin 1501 | case(_zz_13_) 1502 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE"; 1503 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET"; 1504 | default : _zz_13__string = "????"; 1505 | endcase 1506 | end 1507 | always @(*) begin 1508 | case(_zz_14_) 1509 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE"; 1510 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET"; 1511 | default : _zz_14__string = "????"; 1512 | endcase 1513 | end 1514 | always @(*) begin 1515 | case(_zz_15_) 1516 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE"; 1517 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET"; 1518 | default : _zz_15__string = "????"; 1519 | endcase 1520 | end 1521 | always @(*) begin 1522 | case(_zz_16_) 1523 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE"; 1524 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET"; 1525 | default : _zz_16__string = "????"; 1526 | endcase 1527 | end 1528 | always @(*) begin 1529 | case(decode_ENV_CTRL) 1530 | `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; 1531 | `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; 1532 | default : decode_ENV_CTRL_string = "????"; 1533 | endcase 1534 | end 1535 | always @(*) begin 1536 | case(_zz_17_) 1537 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE"; 1538 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET"; 1539 | default : _zz_17__string = "????"; 1540 | endcase 1541 | end 1542 | always @(*) begin 1543 | case(_zz_18_) 1544 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE"; 1545 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET"; 1546 | default : _zz_18__string = "????"; 1547 | endcase 1548 | end 1549 | always @(*) begin 1550 | case(_zz_19_) 1551 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE"; 1552 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET"; 1553 | default : _zz_19__string = "????"; 1554 | endcase 1555 | end 1556 | always @(*) begin 1557 | case(decode_SHIFT_CTRL) 1558 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; 1559 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; 1560 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; 1561 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; 1562 | default : decode_SHIFT_CTRL_string = "?????????"; 1563 | endcase 1564 | end 1565 | always @(*) begin 1566 | case(_zz_20_) 1567 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; 1568 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; 1569 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; 1570 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; 1571 | default : _zz_20__string = "?????????"; 1572 | endcase 1573 | end 1574 | always @(*) begin 1575 | case(_zz_21_) 1576 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; 1577 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; 1578 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; 1579 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; 1580 | default : _zz_21__string = "?????????"; 1581 | endcase 1582 | end 1583 | always @(*) begin 1584 | case(_zz_22_) 1585 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; 1586 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; 1587 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; 1588 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; 1589 | default : _zz_22__string = "?????????"; 1590 | endcase 1591 | end 1592 | always @(*) begin 1593 | case(decode_BRANCH_CTRL) 1594 | `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; 1595 | `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; 1596 | `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; 1597 | `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; 1598 | default : decode_BRANCH_CTRL_string = "????"; 1599 | endcase 1600 | end 1601 | always @(*) begin 1602 | case(_zz_23_) 1603 | `BranchCtrlEnum_defaultEncoding_INC : _zz_23__string = "INC "; 1604 | `BranchCtrlEnum_defaultEncoding_B : _zz_23__string = "B "; 1605 | `BranchCtrlEnum_defaultEncoding_JAL : _zz_23__string = "JAL "; 1606 | `BranchCtrlEnum_defaultEncoding_JALR : _zz_23__string = "JALR"; 1607 | default : _zz_23__string = "????"; 1608 | endcase 1609 | end 1610 | always @(*) begin 1611 | case(_zz_24_) 1612 | `BranchCtrlEnum_defaultEncoding_INC : _zz_24__string = "INC "; 1613 | `BranchCtrlEnum_defaultEncoding_B : _zz_24__string = "B "; 1614 | `BranchCtrlEnum_defaultEncoding_JAL : _zz_24__string = "JAL "; 1615 | `BranchCtrlEnum_defaultEncoding_JALR : _zz_24__string = "JALR"; 1616 | default : _zz_24__string = "????"; 1617 | endcase 1618 | end 1619 | always @(*) begin 1620 | case(_zz_25_) 1621 | `BranchCtrlEnum_defaultEncoding_INC : _zz_25__string = "INC "; 1622 | `BranchCtrlEnum_defaultEncoding_B : _zz_25__string = "B "; 1623 | `BranchCtrlEnum_defaultEncoding_JAL : _zz_25__string = "JAL "; 1624 | `BranchCtrlEnum_defaultEncoding_JALR : _zz_25__string = "JALR"; 1625 | default : _zz_25__string = "????"; 1626 | endcase 1627 | end 1628 | always @(*) begin 1629 | case(memory_ENV_CTRL) 1630 | `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; 1631 | `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; 1632 | default : memory_ENV_CTRL_string = "????"; 1633 | endcase 1634 | end 1635 | always @(*) begin 1636 | case(_zz_26_) 1637 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE"; 1638 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET"; 1639 | default : _zz_26__string = "????"; 1640 | endcase 1641 | end 1642 | always @(*) begin 1643 | case(execute_ENV_CTRL) 1644 | `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; 1645 | `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; 1646 | default : execute_ENV_CTRL_string = "????"; 1647 | endcase 1648 | end 1649 | always @(*) begin 1650 | case(_zz_27_) 1651 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE"; 1652 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET"; 1653 | default : _zz_27__string = "????"; 1654 | endcase 1655 | end 1656 | always @(*) begin 1657 | case(writeBack_ENV_CTRL) 1658 | `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; 1659 | `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; 1660 | default : writeBack_ENV_CTRL_string = "????"; 1661 | endcase 1662 | end 1663 | always @(*) begin 1664 | case(_zz_30_) 1665 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE"; 1666 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET"; 1667 | default : _zz_30__string = "????"; 1668 | endcase 1669 | end 1670 | always @(*) begin 1671 | case(execute_BRANCH_CTRL) 1672 | `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; 1673 | `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; 1674 | `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; 1675 | `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; 1676 | default : execute_BRANCH_CTRL_string = "????"; 1677 | endcase 1678 | end 1679 | always @(*) begin 1680 | case(_zz_32_) 1681 | `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC "; 1682 | `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B "; 1683 | `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL "; 1684 | `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR"; 1685 | default : _zz_32__string = "????"; 1686 | endcase 1687 | end 1688 | always @(*) begin 1689 | case(execute_SHIFT_CTRL) 1690 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; 1691 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; 1692 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; 1693 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; 1694 | default : execute_SHIFT_CTRL_string = "?????????"; 1695 | endcase 1696 | end 1697 | always @(*) begin 1698 | case(_zz_35_) 1699 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1"; 1700 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1 "; 1701 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1 "; 1702 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1 "; 1703 | default : _zz_35__string = "?????????"; 1704 | endcase 1705 | end 1706 | always @(*) begin 1707 | case(execute_SRC2_CTRL) 1708 | `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; 1709 | `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; 1710 | `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; 1711 | `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; 1712 | default : execute_SRC2_CTRL_string = "???"; 1713 | endcase 1714 | end 1715 | always @(*) begin 1716 | case(_zz_40_) 1717 | `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS "; 1718 | `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI"; 1719 | `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS"; 1720 | `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC "; 1721 | default : _zz_40__string = "???"; 1722 | endcase 1723 | end 1724 | always @(*) begin 1725 | case(execute_SRC1_CTRL) 1726 | `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; 1727 | `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; 1728 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; 1729 | `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; 1730 | default : execute_SRC1_CTRL_string = "????????????"; 1731 | endcase 1732 | end 1733 | always @(*) begin 1734 | case(_zz_42_) 1735 | `Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; 1736 | `Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU "; 1737 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT"; 1738 | `Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1 "; 1739 | default : _zz_42__string = "????????????"; 1740 | endcase 1741 | end 1742 | always @(*) begin 1743 | case(execute_ALU_CTRL) 1744 | `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; 1745 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; 1746 | `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; 1747 | default : execute_ALU_CTRL_string = "????????"; 1748 | endcase 1749 | end 1750 | always @(*) begin 1751 | case(_zz_45_) 1752 | `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB "; 1753 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU"; 1754 | `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE "; 1755 | default : _zz_45__string = "????????"; 1756 | endcase 1757 | end 1758 | always @(*) begin 1759 | case(execute_ALU_BITWISE_CTRL) 1760 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; 1761 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; 1762 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; 1763 | default : execute_ALU_BITWISE_CTRL_string = "?????"; 1764 | endcase 1765 | end 1766 | always @(*) begin 1767 | case(_zz_47_) 1768 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1"; 1769 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 "; 1770 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1"; 1771 | default : _zz_47__string = "?????"; 1772 | endcase 1773 | end 1774 | always @(*) begin 1775 | case(_zz_54_) 1776 | `Src2CtrlEnum_defaultEncoding_RS : _zz_54__string = "RS "; 1777 | `Src2CtrlEnum_defaultEncoding_IMI : _zz_54__string = "IMI"; 1778 | `Src2CtrlEnum_defaultEncoding_IMS : _zz_54__string = "IMS"; 1779 | `Src2CtrlEnum_defaultEncoding_PC : _zz_54__string = "PC "; 1780 | default : _zz_54__string = "???"; 1781 | endcase 1782 | end 1783 | always @(*) begin 1784 | case(_zz_55_) 1785 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_55__string = "DISABLE_1"; 1786 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_55__string = "SLL_1 "; 1787 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_55__string = "SRL_1 "; 1788 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_55__string = "SRA_1 "; 1789 | default : _zz_55__string = "?????????"; 1790 | endcase 1791 | end 1792 | always @(*) begin 1793 | case(_zz_58_) 1794 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; 1795 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; 1796 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; 1797 | default : _zz_58__string = "?????"; 1798 | endcase 1799 | end 1800 | always @(*) begin 1801 | case(_zz_61_) 1802 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_61__string = "NONE"; 1803 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_61__string = "XRET"; 1804 | default : _zz_61__string = "????"; 1805 | endcase 1806 | end 1807 | always @(*) begin 1808 | case(_zz_62_) 1809 | `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_62__string = "ADD_SUB "; 1810 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_62__string = "SLT_SLTU"; 1811 | `AluCtrlEnum_defaultEncoding_BITWISE : _zz_62__string = "BITWISE "; 1812 | default : _zz_62__string = "????????"; 1813 | endcase 1814 | end 1815 | always @(*) begin 1816 | case(_zz_65_) 1817 | `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS "; 1818 | `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU "; 1819 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT"; 1820 | `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 "; 1821 | default : _zz_65__string = "????????????"; 1822 | endcase 1823 | end 1824 | always @(*) begin 1825 | case(_zz_70_) 1826 | `BranchCtrlEnum_defaultEncoding_INC : _zz_70__string = "INC "; 1827 | `BranchCtrlEnum_defaultEncoding_B : _zz_70__string = "B "; 1828 | `BranchCtrlEnum_defaultEncoding_JAL : _zz_70__string = "JAL "; 1829 | `BranchCtrlEnum_defaultEncoding_JALR : _zz_70__string = "JALR"; 1830 | default : _zz_70__string = "????"; 1831 | endcase 1832 | end 1833 | always @(*) begin 1834 | case(_zz_120_) 1835 | `BranchCtrlEnum_defaultEncoding_INC : _zz_120__string = "INC "; 1836 | `BranchCtrlEnum_defaultEncoding_B : _zz_120__string = "B "; 1837 | `BranchCtrlEnum_defaultEncoding_JAL : _zz_120__string = "JAL "; 1838 | `BranchCtrlEnum_defaultEncoding_JALR : _zz_120__string = "JALR"; 1839 | default : _zz_120__string = "????"; 1840 | endcase 1841 | end 1842 | always @(*) begin 1843 | case(_zz_121_) 1844 | `Src1CtrlEnum_defaultEncoding_RS : _zz_121__string = "RS "; 1845 | `Src1CtrlEnum_defaultEncoding_IMU : _zz_121__string = "IMU "; 1846 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_121__string = "PC_INCREMENT"; 1847 | `Src1CtrlEnum_defaultEncoding_URS1 : _zz_121__string = "URS1 "; 1848 | default : _zz_121__string = "????????????"; 1849 | endcase 1850 | end 1851 | always @(*) begin 1852 | case(_zz_122_) 1853 | `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_122__string = "ADD_SUB "; 1854 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_122__string = "SLT_SLTU"; 1855 | `AluCtrlEnum_defaultEncoding_BITWISE : _zz_122__string = "BITWISE "; 1856 | default : _zz_122__string = "????????"; 1857 | endcase 1858 | end 1859 | always @(*) begin 1860 | case(_zz_123_) 1861 | `EnvCtrlEnum_defaultEncoding_NONE : _zz_123__string = "NONE"; 1862 | `EnvCtrlEnum_defaultEncoding_XRET : _zz_123__string = "XRET"; 1863 | default : _zz_123__string = "????"; 1864 | endcase 1865 | end 1866 | always @(*) begin 1867 | case(_zz_124_) 1868 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_124__string = "XOR_1"; 1869 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_124__string = "OR_1 "; 1870 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_124__string = "AND_1"; 1871 | default : _zz_124__string = "?????"; 1872 | endcase 1873 | end 1874 | always @(*) begin 1875 | case(_zz_125_) 1876 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_125__string = "DISABLE_1"; 1877 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_125__string = "SLL_1 "; 1878 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_125__string = "SRL_1 "; 1879 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_125__string = "SRA_1 "; 1880 | default : _zz_125__string = "?????????"; 1881 | endcase 1882 | end 1883 | always @(*) begin 1884 | case(_zz_126_) 1885 | `Src2CtrlEnum_defaultEncoding_RS : _zz_126__string = "RS "; 1886 | `Src2CtrlEnum_defaultEncoding_IMI : _zz_126__string = "IMI"; 1887 | `Src2CtrlEnum_defaultEncoding_IMS : _zz_126__string = "IMS"; 1888 | `Src2CtrlEnum_defaultEncoding_PC : _zz_126__string = "PC "; 1889 | default : _zz_126__string = "???"; 1890 | endcase 1891 | end 1892 | always @(*) begin 1893 | case(decode_to_execute_BRANCH_CTRL) 1894 | `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; 1895 | `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; 1896 | `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; 1897 | `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; 1898 | default : decode_to_execute_BRANCH_CTRL_string = "????"; 1899 | endcase 1900 | end 1901 | always @(*) begin 1902 | case(decode_to_execute_SHIFT_CTRL) 1903 | `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; 1904 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; 1905 | `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; 1906 | `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; 1907 | default : decode_to_execute_SHIFT_CTRL_string = "?????????"; 1908 | endcase 1909 | end 1910 | always @(*) begin 1911 | case(decode_to_execute_ENV_CTRL) 1912 | `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; 1913 | `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; 1914 | default : decode_to_execute_ENV_CTRL_string = "????"; 1915 | endcase 1916 | end 1917 | always @(*) begin 1918 | case(execute_to_memory_ENV_CTRL) 1919 | `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; 1920 | `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; 1921 | default : execute_to_memory_ENV_CTRL_string = "????"; 1922 | endcase 1923 | end 1924 | always @(*) begin 1925 | case(memory_to_writeBack_ENV_CTRL) 1926 | `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; 1927 | `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; 1928 | default : memory_to_writeBack_ENV_CTRL_string = "????"; 1929 | endcase 1930 | end 1931 | always @(*) begin 1932 | case(decode_to_execute_SRC2_CTRL) 1933 | `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; 1934 | `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; 1935 | `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; 1936 | `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; 1937 | default : decode_to_execute_SRC2_CTRL_string = "???"; 1938 | endcase 1939 | end 1940 | always @(*) begin 1941 | case(decode_to_execute_ALU_BITWISE_CTRL) 1942 | `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; 1943 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; 1944 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; 1945 | default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; 1946 | endcase 1947 | end 1948 | always @(*) begin 1949 | case(decode_to_execute_ALU_CTRL) 1950 | `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; 1951 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; 1952 | `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; 1953 | default : decode_to_execute_ALU_CTRL_string = "????????"; 1954 | endcase 1955 | end 1956 | always @(*) begin 1957 | case(decode_to_execute_SRC1_CTRL) 1958 | `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; 1959 | `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; 1960 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; 1961 | `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; 1962 | default : decode_to_execute_SRC1_CTRL_string = "????????????"; 1963 | endcase 1964 | end 1965 | `endif 1966 | 1967 | assign decode_SRC2_FORCE_ZERO = _zz_44_; 1968 | assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; 1969 | assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; 1970 | assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; 1971 | assign decode_FORMAL_PC_NEXT = _zz_86_; 1972 | assign decode_RS1 = _zz_52_; 1973 | assign decode_CSR_WRITE_OPCODE = _zz_29_; 1974 | assign execute_BRANCH_CALC = _zz_31_; 1975 | assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; 1976 | assign execute_MEMORY_ADDRESS_LOW = _zz_82_; 1977 | assign execute_BRANCH_DO = _zz_33_; 1978 | assign decode_SRC1_CTRL = _zz_1_; 1979 | assign _zz_2_ = _zz_3_; 1980 | assign memory_MEMORY_READ_DATA = _zz_73_; 1981 | assign decode_SRC_LESS_UNSIGNED = _zz_67_; 1982 | assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; 1983 | assign execute_REGFILE_WRITE_DATA = _zz_46_; 1984 | assign decode_ALU_CTRL = _zz_4_; 1985 | assign _zz_5_ = _zz_6_; 1986 | assign decode_ALU_BITWISE_CTRL = _zz_7_; 1987 | assign _zz_8_ = _zz_9_; 1988 | assign decode_SRC2_CTRL = _zz_10_; 1989 | assign _zz_11_ = _zz_12_; 1990 | assign decode_IS_CSR = _zz_68_; 1991 | assign decode_RS2 = _zz_51_; 1992 | assign _zz_13_ = _zz_14_; 1993 | assign _zz_15_ = _zz_16_; 1994 | assign decode_ENV_CTRL = _zz_17_; 1995 | assign _zz_18_ = _zz_19_; 1996 | assign decode_SHIFT_CTRL = _zz_20_; 1997 | assign _zz_21_ = _zz_22_; 1998 | assign decode_MEMORY_STORE = _zz_57_; 1999 | assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_60_; 2000 | assign decode_CSR_READ_OPCODE = _zz_28_; 2001 | assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; 2002 | assign decode_BYPASSABLE_MEMORY_STAGE = _zz_63_; 2003 | assign decode_BRANCH_CTRL = _zz_23_; 2004 | assign _zz_24_ = _zz_25_; 2005 | assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; 2006 | assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; 2007 | assign execute_IS_CSR = decode_to_execute_IS_CSR; 2008 | assign memory_ENV_CTRL = _zz_26_; 2009 | assign execute_ENV_CTRL = _zz_27_; 2010 | assign writeBack_ENV_CTRL = _zz_30_; 2011 | assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; 2012 | assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; 2013 | assign execute_PC = decode_to_execute_PC; 2014 | assign execute_RS1 = decode_to_execute_RS1; 2015 | assign execute_BRANCH_CTRL = _zz_32_; 2016 | assign decode_RS2_USE = _zz_56_; 2017 | assign decode_RS1_USE = _zz_66_; 2018 | assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; 2019 | assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; 2020 | assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; 2021 | assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; 2022 | assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; 2023 | assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; 2024 | always @ (*) begin 2025 | _zz_34_ = execute_REGFILE_WRITE_DATA; 2026 | if(_zz_167_)begin 2027 | _zz_34_ = _zz_135_; 2028 | end 2029 | if(_zz_168_)begin 2030 | _zz_34_ = execute_CsrPlugin_readData; 2031 | end 2032 | end 2033 | 2034 | assign execute_SHIFT_CTRL = _zz_35_; 2035 | assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; 2036 | assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; 2037 | assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; 2038 | assign _zz_39_ = execute_PC; 2039 | assign execute_SRC2_CTRL = _zz_40_; 2040 | assign execute_SRC1_CTRL = _zz_42_; 2041 | assign decode_SRC_USE_SUB_LESS = _zz_59_; 2042 | assign decode_SRC_ADD_ZERO = _zz_64_; 2043 | assign execute_SRC_ADD_SUB = _zz_38_; 2044 | assign execute_SRC_LESS = _zz_36_; 2045 | assign execute_ALU_CTRL = _zz_45_; 2046 | assign execute_SRC2 = _zz_41_; 2047 | assign execute_SRC1 = _zz_43_; 2048 | assign execute_ALU_BITWISE_CTRL = _zz_47_; 2049 | assign _zz_48_ = writeBack_INSTRUCTION; 2050 | assign _zz_49_ = writeBack_REGFILE_WRITE_VALID; 2051 | always @ (*) begin 2052 | _zz_50_ = 1'b0; 2053 | if(lastStageRegFileWrite_valid)begin 2054 | _zz_50_ = 1'b1; 2055 | end 2056 | end 2057 | 2058 | assign decode_INSTRUCTION_ANTICIPATED = _zz_89_; 2059 | always @ (*) begin 2060 | decode_REGFILE_WRITE_VALID = _zz_69_; 2061 | if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin 2062 | decode_REGFILE_WRITE_VALID = 1'b0; 2063 | end 2064 | end 2065 | 2066 | assign decode_LEGAL_INSTRUCTION = _zz_71_; 2067 | assign decode_INSTRUCTION_READY = 1'b1; 2068 | assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; 2069 | always @ (*) begin 2070 | _zz_72_ = writeBack_REGFILE_WRITE_DATA; 2071 | if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin 2072 | _zz_72_ = writeBack_DBusSimplePlugin_rspFormated; 2073 | end 2074 | end 2075 | 2076 | assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; 2077 | assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; 2078 | assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; 2079 | assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; 2080 | assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; 2081 | assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; 2082 | assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; 2083 | assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; 2084 | assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; 2085 | assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; 2086 | assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; 2087 | assign memory_PC = execute_to_memory_PC; 2088 | assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; 2089 | assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; 2090 | assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; 2091 | assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; 2092 | assign execute_MMU_FAULT = _zz_81_; 2093 | assign execute_MMU_RSP_physicalAddress = _zz_74_; 2094 | assign execute_MMU_RSP_isIoAccess = _zz_75_; 2095 | assign execute_MMU_RSP_allowRead = _zz_76_; 2096 | assign execute_MMU_RSP_allowWrite = _zz_77_; 2097 | assign execute_MMU_RSP_allowExecute = _zz_78_; 2098 | assign execute_MMU_RSP_exception = _zz_79_; 2099 | assign execute_MMU_RSP_refilling = _zz_80_; 2100 | assign execute_SRC_ADD = _zz_37_; 2101 | assign execute_RS2 = decode_to_execute_RS2; 2102 | assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; 2103 | assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; 2104 | assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; 2105 | assign execute_ALIGNEMENT_FAULT = _zz_83_; 2106 | assign decode_MEMORY_ENABLE = _zz_53_; 2107 | always @ (*) begin 2108 | _zz_84_ = memory_FORMAL_PC_NEXT; 2109 | if(DBusSimplePlugin_redoBranch_valid)begin 2110 | _zz_84_ = DBusSimplePlugin_redoBranch_payload; 2111 | end 2112 | if(BranchPlugin_jumpInterface_valid)begin 2113 | _zz_84_ = BranchPlugin_jumpInterface_payload; 2114 | end 2115 | end 2116 | 2117 | always @ (*) begin 2118 | _zz_85_ = decode_FORMAL_PC_NEXT; 2119 | if(IBusSimplePlugin_redoBranch_valid)begin 2120 | _zz_85_ = IBusSimplePlugin_redoBranch_payload; 2121 | end 2122 | end 2123 | 2124 | assign decode_PC = _zz_88_; 2125 | assign decode_INSTRUCTION = _zz_87_; 2126 | assign writeBack_PC = memory_to_writeBack_PC; 2127 | assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; 2128 | always @ (*) begin 2129 | decode_arbitration_haltItself = 1'b0; 2130 | if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin 2131 | decode_arbitration_haltItself = 1'b1; 2132 | end 2133 | end 2134 | 2135 | always @ (*) begin 2136 | decode_arbitration_haltByOther = 1'b0; 2137 | if((decode_arbitration_isValid && (_zz_136_ || _zz_137_)))begin 2138 | decode_arbitration_haltByOther = 1'b1; 2139 | end 2140 | if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin 2141 | decode_arbitration_haltByOther = decode_arbitration_isValid; 2142 | end 2143 | if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin 2144 | decode_arbitration_haltByOther = 1'b1; 2145 | end 2146 | end 2147 | 2148 | always @ (*) begin 2149 | decode_arbitration_removeIt = 1'b0; 2150 | if(_zz_169_)begin 2151 | decode_arbitration_removeIt = 1'b1; 2152 | end 2153 | if(decode_arbitration_isFlushed)begin 2154 | decode_arbitration_removeIt = 1'b1; 2155 | end 2156 | end 2157 | 2158 | always @ (*) begin 2159 | decode_arbitration_flushAll = 1'b0; 2160 | if(IBusSimplePlugin_redoBranch_valid)begin 2161 | decode_arbitration_flushAll = 1'b1; 2162 | end 2163 | end 2164 | 2165 | always @ (*) begin 2166 | execute_arbitration_haltItself = 1'b0; 2167 | if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_108_)))begin 2168 | execute_arbitration_haltItself = 1'b1; 2169 | end 2170 | if(_zz_167_)begin 2171 | if(_zz_170_)begin 2172 | if(! execute_LightShifterPlugin_done) begin 2173 | execute_arbitration_haltItself = 1'b1; 2174 | end 2175 | end 2176 | end 2177 | if(_zz_168_)begin 2178 | if(execute_CsrPlugin_blockedBySideEffects)begin 2179 | execute_arbitration_haltItself = 1'b1; 2180 | end 2181 | end 2182 | end 2183 | 2184 | assign execute_arbitration_haltByOther = 1'b0; 2185 | always @ (*) begin 2186 | execute_arbitration_removeIt = 1'b0; 2187 | if(execute_arbitration_isFlushed)begin 2188 | execute_arbitration_removeIt = 1'b1; 2189 | end 2190 | end 2191 | 2192 | always @ (*) begin 2193 | execute_arbitration_flushAll = 1'b0; 2194 | if(BranchPlugin_jumpInterface_valid)begin 2195 | execute_arbitration_flushAll = 1'b1; 2196 | end 2197 | if(_zz_171_)begin 2198 | execute_arbitration_flushAll = 1'b1; 2199 | end 2200 | end 2201 | 2202 | always @ (*) begin 2203 | memory_arbitration_haltItself = 1'b0; 2204 | if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin 2205 | memory_arbitration_haltItself = 1'b1; 2206 | end 2207 | end 2208 | 2209 | assign memory_arbitration_haltByOther = 1'b0; 2210 | always @ (*) begin 2211 | memory_arbitration_removeIt = 1'b0; 2212 | if(_zz_171_)begin 2213 | memory_arbitration_removeIt = 1'b1; 2214 | end 2215 | if(memory_arbitration_isFlushed)begin 2216 | memory_arbitration_removeIt = 1'b1; 2217 | end 2218 | end 2219 | 2220 | always @ (*) begin 2221 | memory_arbitration_flushAll = 1'b0; 2222 | if(DBusSimplePlugin_redoBranch_valid)begin 2223 | memory_arbitration_flushAll = 1'b1; 2224 | end 2225 | if(_zz_172_)begin 2226 | memory_arbitration_flushAll = 1'b1; 2227 | end 2228 | if(_zz_173_)begin 2229 | memory_arbitration_flushAll = 1'b1; 2230 | end 2231 | end 2232 | 2233 | assign writeBack_arbitration_haltItself = 1'b0; 2234 | assign writeBack_arbitration_haltByOther = 1'b0; 2235 | always @ (*) begin 2236 | writeBack_arbitration_removeIt = 1'b0; 2237 | if(writeBack_arbitration_isFlushed)begin 2238 | writeBack_arbitration_removeIt = 1'b1; 2239 | end 2240 | end 2241 | 2242 | assign writeBack_arbitration_flushAll = 1'b0; 2243 | assign lastStageInstruction = writeBack_INSTRUCTION; 2244 | assign lastStagePc = writeBack_PC; 2245 | assign lastStageIsValid = writeBack_arbitration_isValid; 2246 | assign lastStageIsFiring = writeBack_arbitration_isFiring; 2247 | always @ (*) begin 2248 | IBusSimplePlugin_fetcherHalt = 1'b0; 2249 | if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode}}} != (4'b0000)))begin 2250 | IBusSimplePlugin_fetcherHalt = 1'b1; 2251 | end 2252 | if(_zz_172_)begin 2253 | IBusSimplePlugin_fetcherHalt = 1'b1; 2254 | end 2255 | if(_zz_173_)begin 2256 | IBusSimplePlugin_fetcherHalt = 1'b1; 2257 | end 2258 | end 2259 | 2260 | assign IBusSimplePlugin_fetcherflushIt = 1'b0; 2261 | always @ (*) begin 2262 | IBusSimplePlugin_incomingInstruction = 1'b0; 2263 | if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin 2264 | IBusSimplePlugin_incomingInstruction = 1'b1; 2265 | end 2266 | if(IBusSimplePlugin_injector_decodeInput_valid)begin 2267 | IBusSimplePlugin_incomingInstruction = 1'b1; 2268 | end 2269 | end 2270 | 2271 | always @ (*) begin 2272 | CsrPlugin_jumpInterface_valid = 1'b0; 2273 | if(_zz_172_)begin 2274 | CsrPlugin_jumpInterface_valid = 1'b1; 2275 | end 2276 | if(_zz_173_)begin 2277 | CsrPlugin_jumpInterface_valid = 1'b1; 2278 | end 2279 | end 2280 | 2281 | always @ (*) begin 2282 | CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); 2283 | if(_zz_172_)begin 2284 | CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; 2285 | end 2286 | if(_zz_173_)begin 2287 | case(_zz_174_) 2288 | 2'b11 : begin 2289 | CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; 2290 | end 2291 | default : begin 2292 | end 2293 | endcase 2294 | end 2295 | end 2296 | 2297 | assign CsrPlugin_forceMachineWire = 1'b0; 2298 | assign CsrPlugin_allowInterrupts = 1'b1; 2299 | assign CsrPlugin_allowException = 1'b1; 2300 | assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000)); 2301 | assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; 2302 | assign _zz_91_ = (_zz_90_ & (~ _zz_193_)); 2303 | assign _zz_92_ = _zz_91_[3]; 2304 | assign _zz_93_ = (_zz_91_[1] || _zz_92_); 2305 | assign _zz_94_ = (_zz_91_[2] || _zz_92_); 2306 | assign IBusSimplePlugin_jump_pcLoad_payload = _zz_166_; 2307 | assign _zz_95_ = (! IBusSimplePlugin_fetcherHalt); 2308 | assign IBusSimplePlugin_fetchPc_output_valid = (IBusSimplePlugin_fetchPc_preOutput_valid && _zz_95_); 2309 | assign IBusSimplePlugin_fetchPc_preOutput_ready = (IBusSimplePlugin_fetchPc_output_ready && _zz_95_); 2310 | assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_preOutput_payload; 2311 | always @ (*) begin 2312 | IBusSimplePlugin_fetchPc_propagatePc = 1'b0; 2313 | if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_iBusRsp_stages_1_input_ready))begin 2314 | IBusSimplePlugin_fetchPc_propagatePc = 1'b1; 2315 | end 2316 | end 2317 | 2318 | always @ (*) begin 2319 | IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_195_); 2320 | if(IBusSimplePlugin_jump_pcLoad_valid)begin 2321 | IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; 2322 | end 2323 | IBusSimplePlugin_fetchPc_pc[0] = 1'b0; 2324 | IBusSimplePlugin_fetchPc_pc[1] = 1'b0; 2325 | end 2326 | 2327 | always @ (*) begin 2328 | IBusSimplePlugin_fetchPc_samplePcNext = 1'b0; 2329 | if(IBusSimplePlugin_fetchPc_propagatePc)begin 2330 | IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; 2331 | end 2332 | if(IBusSimplePlugin_jump_pcLoad_valid)begin 2333 | IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; 2334 | end 2335 | if(_zz_175_)begin 2336 | IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; 2337 | end 2338 | end 2339 | 2340 | assign IBusSimplePlugin_fetchPc_preOutput_valid = _zz_96_; 2341 | assign IBusSimplePlugin_fetchPc_preOutput_payload = IBusSimplePlugin_fetchPc_pc; 2342 | always @ (*) begin 2343 | IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; 2344 | if(IBusSimplePlugin_mmuBus_busy)begin 2345 | IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0; 2346 | end 2347 | end 2348 | 2349 | assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; 2350 | assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; 2351 | assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; 2352 | always @ (*) begin 2353 | IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; 2354 | if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin 2355 | IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; 2356 | end 2357 | if(_zz_176_)begin 2358 | IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; 2359 | end 2360 | end 2361 | 2362 | assign _zz_97_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); 2363 | always @ (*) begin 2364 | IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_97_); 2365 | if(IBusSimplePlugin_mmuBus_busy)begin 2366 | IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0; 2367 | end 2368 | end 2369 | 2370 | assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_97_); 2371 | assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; 2372 | assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; 2373 | assign _zz_98_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); 2374 | assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_98_); 2375 | assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_98_); 2376 | assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; 2377 | assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_99_; 2378 | assign _zz_99_ = ((1'b0 && (! _zz_100_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); 2379 | assign _zz_100_ = _zz_101_; 2380 | assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_100_; 2381 | assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; 2382 | always @ (*) begin 2383 | IBusSimplePlugin_iBusRsp_readyForError = 1'b1; 2384 | if(IBusSimplePlugin_injector_decodeInput_valid)begin 2385 | IBusSimplePlugin_iBusRsp_readyForError = 1'b0; 2386 | end 2387 | if((! IBusSimplePlugin_pcValids_0))begin 2388 | IBusSimplePlugin_iBusRsp_readyForError = 1'b0; 2389 | end 2390 | end 2391 | 2392 | assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); 2393 | assign IBusSimplePlugin_injector_decodeInput_valid = _zz_102_; 2394 | assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_103_; 2395 | assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_104_; 2396 | assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_105_; 2397 | assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_106_; 2398 | assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst); 2399 | assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; 2400 | assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; 2401 | assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; 2402 | assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; 2403 | assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); 2404 | assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); 2405 | assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc; 2406 | assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; 2407 | assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100)); 2408 | assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; 2409 | assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; 2410 | assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; 2411 | assign IBusSimplePlugin_pendingCmdNext = (_zz_196_ - _zz_200_); 2412 | always @ (*) begin 2413 | IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111))); 2414 | if(_zz_176_)begin 2415 | IBusSimplePlugin_cmd_valid = 1'b0; 2416 | end 2417 | end 2418 | 2419 | assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; 2420 | assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; 2421 | assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; 2422 | assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || (IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt)); 2423 | assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)}; 2424 | assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)))); 2425 | assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error; 2426 | assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst; 2427 | assign _zz_163_ = (IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt); 2428 | assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; 2429 | assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; 2430 | assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; 2431 | assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; 2432 | always @ (*) begin 2433 | IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; 2434 | if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin 2435 | IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; 2436 | end 2437 | end 2438 | 2439 | assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; 2440 | always @ (*) begin 2441 | IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; 2442 | if(_zz_177_)begin 2443 | IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; 2444 | end 2445 | end 2446 | 2447 | always @ (*) begin 2448 | IBusSimplePlugin_rspJoin_redoRequired = 1'b0; 2449 | if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin 2450 | IBusSimplePlugin_rspJoin_redoRequired = 1'b1; 2451 | end 2452 | end 2453 | 2454 | assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); 2455 | assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; 2456 | assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; 2457 | assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; 2458 | assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; 2459 | assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); 2460 | assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); 2461 | assign _zz_107_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired)); 2462 | assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_107_); 2463 | assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_107_); 2464 | assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; 2465 | assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; 2466 | assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; 2467 | assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; 2468 | assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError); 2469 | assign IBusSimplePlugin_redoBranch_payload = decode_PC; 2470 | always @ (*) begin 2471 | IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx); 2472 | if(_zz_177_)begin 2473 | IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100); 2474 | end 2475 | end 2476 | 2477 | assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)}; 2478 | assign IBusSimplePlugin_decodeExceptionPort_valid = ((IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError) && (! IBusSimplePlugin_fetcherHalt)); 2479 | assign _zz_108_ = 1'b0; 2480 | assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); 2481 | always @ (*) begin 2482 | execute_DBusSimplePlugin_skipCmd = 1'b0; 2483 | if(execute_ALIGNEMENT_FAULT)begin 2484 | execute_DBusSimplePlugin_skipCmd = 1'b1; 2485 | end 2486 | if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin 2487 | execute_DBusSimplePlugin_skipCmd = 1'b1; 2488 | end 2489 | end 2490 | 2491 | assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_108_)); 2492 | assign dBus_cmd_payload_wr = execute_MEMORY_STORE; 2493 | assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; 2494 | always @ (*) begin 2495 | case(dBus_cmd_payload_size) 2496 | 2'b00 : begin 2497 | _zz_109_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; 2498 | end 2499 | 2'b01 : begin 2500 | _zz_109_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; 2501 | end 2502 | default : begin 2503 | _zz_109_ = execute_RS2[31 : 0]; 2504 | end 2505 | endcase 2506 | end 2507 | 2508 | assign dBus_cmd_payload_data = _zz_109_; 2509 | assign _zz_82_ = dBus_cmd_payload_address[1 : 0]; 2510 | always @ (*) begin 2511 | case(dBus_cmd_payload_size) 2512 | 2'b00 : begin 2513 | _zz_110_ = (4'b0001); 2514 | end 2515 | 2'b01 : begin 2516 | _zz_110_ = (4'b0011); 2517 | end 2518 | default : begin 2519 | _zz_110_ = (4'b1111); 2520 | end 2521 | endcase 2522 | end 2523 | 2524 | assign execute_DBusSimplePlugin_formalMask = (_zz_110_ <<< dBus_cmd_payload_address[1 : 0]); 2525 | assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); 2526 | assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; 2527 | assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; 2528 | assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); 2529 | assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; 2530 | assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); 2531 | assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; 2532 | assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; 2533 | assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead; 2534 | assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; 2535 | assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; 2536 | assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception; 2537 | assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling; 2538 | assign _zz_73_ = dBus_rsp_data; 2539 | always @ (*) begin 2540 | DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; 2541 | if(_zz_178_)begin 2542 | DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; 2543 | end 2544 | if(memory_ALIGNEMENT_FAULT)begin 2545 | DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; 2546 | end 2547 | if(memory_MMU_RSP_refilling)begin 2548 | DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; 2549 | end else begin 2550 | if(memory_MMU_FAULT)begin 2551 | DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; 2552 | end 2553 | end 2554 | if(_zz_179_)begin 2555 | DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; 2556 | end 2557 | end 2558 | 2559 | always @ (*) begin 2560 | DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); 2561 | if(_zz_178_)begin 2562 | DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); 2563 | end 2564 | if(memory_ALIGNEMENT_FAULT)begin 2565 | DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_205_}; 2566 | end 2567 | if(! memory_MMU_RSP_refilling) begin 2568 | if(memory_MMU_FAULT)begin 2569 | DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); 2570 | end 2571 | end 2572 | end 2573 | 2574 | assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; 2575 | always @ (*) begin 2576 | DBusSimplePlugin_redoBranch_valid = 1'b0; 2577 | if(memory_MMU_RSP_refilling)begin 2578 | DBusSimplePlugin_redoBranch_valid = 1'b1; 2579 | end 2580 | if(_zz_179_)begin 2581 | DBusSimplePlugin_redoBranch_valid = 1'b0; 2582 | end 2583 | end 2584 | 2585 | assign DBusSimplePlugin_redoBranch_payload = memory_PC; 2586 | always @ (*) begin 2587 | writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; 2588 | case(writeBack_MEMORY_ADDRESS_LOW) 2589 | 2'b01 : begin 2590 | writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; 2591 | end 2592 | 2'b10 : begin 2593 | writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; 2594 | end 2595 | 2'b11 : begin 2596 | writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; 2597 | end 2598 | default : begin 2599 | end 2600 | endcase 2601 | end 2602 | 2603 | assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); 2604 | always @ (*) begin 2605 | _zz_112_[31] = _zz_111_; 2606 | _zz_112_[30] = _zz_111_; 2607 | _zz_112_[29] = _zz_111_; 2608 | _zz_112_[28] = _zz_111_; 2609 | _zz_112_[27] = _zz_111_; 2610 | _zz_112_[26] = _zz_111_; 2611 | _zz_112_[25] = _zz_111_; 2612 | _zz_112_[24] = _zz_111_; 2613 | _zz_112_[23] = _zz_111_; 2614 | _zz_112_[22] = _zz_111_; 2615 | _zz_112_[21] = _zz_111_; 2616 | _zz_112_[20] = _zz_111_; 2617 | _zz_112_[19] = _zz_111_; 2618 | _zz_112_[18] = _zz_111_; 2619 | _zz_112_[17] = _zz_111_; 2620 | _zz_112_[16] = _zz_111_; 2621 | _zz_112_[15] = _zz_111_; 2622 | _zz_112_[14] = _zz_111_; 2623 | _zz_112_[13] = _zz_111_; 2624 | _zz_112_[12] = _zz_111_; 2625 | _zz_112_[11] = _zz_111_; 2626 | _zz_112_[10] = _zz_111_; 2627 | _zz_112_[9] = _zz_111_; 2628 | _zz_112_[8] = _zz_111_; 2629 | _zz_112_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; 2630 | end 2631 | 2632 | assign _zz_113_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); 2633 | always @ (*) begin 2634 | _zz_114_[31] = _zz_113_; 2635 | _zz_114_[30] = _zz_113_; 2636 | _zz_114_[29] = _zz_113_; 2637 | _zz_114_[28] = _zz_113_; 2638 | _zz_114_[27] = _zz_113_; 2639 | _zz_114_[26] = _zz_113_; 2640 | _zz_114_[25] = _zz_113_; 2641 | _zz_114_[24] = _zz_113_; 2642 | _zz_114_[23] = _zz_113_; 2643 | _zz_114_[22] = _zz_113_; 2644 | _zz_114_[21] = _zz_113_; 2645 | _zz_114_[20] = _zz_113_; 2646 | _zz_114_[19] = _zz_113_; 2647 | _zz_114_[18] = _zz_113_; 2648 | _zz_114_[17] = _zz_113_; 2649 | _zz_114_[16] = _zz_113_; 2650 | _zz_114_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; 2651 | end 2652 | 2653 | always @ (*) begin 2654 | case(_zz_191_) 2655 | 2'b00 : begin 2656 | writeBack_DBusSimplePlugin_rspFormated = _zz_112_; 2657 | end 2658 | 2'b01 : begin 2659 | writeBack_DBusSimplePlugin_rspFormated = _zz_114_; 2660 | end 2661 | default : begin 2662 | writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; 2663 | end 2664 | endcase 2665 | end 2666 | 2667 | assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress; 2668 | assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; 2669 | assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; 2670 | assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; 2671 | assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; 2672 | assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; 2673 | assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; 2674 | assign IBusSimplePlugin_mmuBus_busy = 1'b0; 2675 | assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; 2676 | assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; 2677 | assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; 2678 | assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; 2679 | assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; 2680 | assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; 2681 | assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; 2682 | assign DBusSimplePlugin_mmuBus_busy = 1'b0; 2683 | assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); 2684 | assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); 2685 | assign _zz_118_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); 2686 | assign _zz_119_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); 2687 | assign _zz_115_ = {(((decode_INSTRUCTION & _zz_248_) == (32'b00000000000000000000000000000000)) != (1'b0)),{({_zz_119_,_zz_249_} != (2'b00)),{({_zz_250_,_zz_251_} != (2'b00)),{(_zz_252_ != _zz_253_),{_zz_254_,{_zz_255_,_zz_256_}}}}}}; 2688 | assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_356_) == (32'b00000000000000000001000001110011)),{(_zz_357_ == _zz_358_),{_zz_359_,{_zz_360_,_zz_361_}}}}}}} != (18'b000000000000000000)); 2689 | assign _zz_120_ = _zz_115_[1 : 0]; 2690 | assign _zz_70_ = _zz_120_; 2691 | assign _zz_69_ = _zz_206_[0]; 2692 | assign _zz_68_ = _zz_207_[0]; 2693 | assign _zz_67_ = _zz_208_[0]; 2694 | assign _zz_66_ = _zz_209_[0]; 2695 | assign _zz_121_ = _zz_115_[7 : 6]; 2696 | assign _zz_65_ = _zz_121_; 2697 | assign _zz_64_ = _zz_210_[0]; 2698 | assign _zz_63_ = _zz_211_[0]; 2699 | assign _zz_122_ = _zz_115_[12 : 11]; 2700 | assign _zz_62_ = _zz_122_; 2701 | assign _zz_123_ = _zz_115_[13 : 13]; 2702 | assign _zz_61_ = _zz_123_; 2703 | assign _zz_60_ = _zz_212_[0]; 2704 | assign _zz_59_ = _zz_213_[0]; 2705 | assign _zz_124_ = _zz_115_[17 : 16]; 2706 | assign _zz_58_ = _zz_124_; 2707 | assign _zz_57_ = _zz_214_[0]; 2708 | assign _zz_56_ = _zz_215_[0]; 2709 | assign _zz_125_ = _zz_115_[21 : 20]; 2710 | assign _zz_55_ = _zz_125_; 2711 | assign _zz_126_ = _zz_115_[23 : 22]; 2712 | assign _zz_54_ = _zz_126_; 2713 | assign _zz_53_ = _zz_216_[0]; 2714 | assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); 2715 | assign decodeExceptionPort_payload_code = (4'b0010); 2716 | assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; 2717 | assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; 2718 | assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; 2719 | assign decode_RegFilePlugin_rs1Data = _zz_164_; 2720 | assign decode_RegFilePlugin_rs2Data = _zz_165_; 2721 | assign _zz_52_ = decode_RegFilePlugin_rs1Data; 2722 | assign _zz_51_ = decode_RegFilePlugin_rs2Data; 2723 | always @ (*) begin 2724 | lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring); 2725 | if(_zz_127_)begin 2726 | lastStageRegFileWrite_valid = 1'b1; 2727 | end 2728 | end 2729 | 2730 | assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7]; 2731 | assign lastStageRegFileWrite_payload_data = _zz_72_; 2732 | always @ (*) begin 2733 | case(execute_ALU_BITWISE_CTRL) 2734 | `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin 2735 | execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); 2736 | end 2737 | `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin 2738 | execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); 2739 | end 2740 | default : begin 2741 | execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); 2742 | end 2743 | endcase 2744 | end 2745 | 2746 | always @ (*) begin 2747 | case(execute_ALU_CTRL) 2748 | `AluCtrlEnum_defaultEncoding_BITWISE : begin 2749 | _zz_128_ = execute_IntAluPlugin_bitwise; 2750 | end 2751 | `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin 2752 | _zz_128_ = {31'd0, _zz_217_}; 2753 | end 2754 | default : begin 2755 | _zz_128_ = execute_SRC_ADD_SUB; 2756 | end 2757 | endcase 2758 | end 2759 | 2760 | assign _zz_46_ = _zz_128_; 2761 | assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); 2762 | always @ (*) begin 2763 | case(execute_SRC1_CTRL) 2764 | `Src1CtrlEnum_defaultEncoding_RS : begin 2765 | _zz_129_ = execute_RS1; 2766 | end 2767 | `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin 2768 | _zz_129_ = {29'd0, _zz_218_}; 2769 | end 2770 | `Src1CtrlEnum_defaultEncoding_IMU : begin 2771 | _zz_129_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; 2772 | end 2773 | default : begin 2774 | _zz_129_ = {27'd0, _zz_219_}; 2775 | end 2776 | endcase 2777 | end 2778 | 2779 | assign _zz_43_ = _zz_129_; 2780 | assign _zz_130_ = _zz_220_[11]; 2781 | always @ (*) begin 2782 | _zz_131_[19] = _zz_130_; 2783 | _zz_131_[18] = _zz_130_; 2784 | _zz_131_[17] = _zz_130_; 2785 | _zz_131_[16] = _zz_130_; 2786 | _zz_131_[15] = _zz_130_; 2787 | _zz_131_[14] = _zz_130_; 2788 | _zz_131_[13] = _zz_130_; 2789 | _zz_131_[12] = _zz_130_; 2790 | _zz_131_[11] = _zz_130_; 2791 | _zz_131_[10] = _zz_130_; 2792 | _zz_131_[9] = _zz_130_; 2793 | _zz_131_[8] = _zz_130_; 2794 | _zz_131_[7] = _zz_130_; 2795 | _zz_131_[6] = _zz_130_; 2796 | _zz_131_[5] = _zz_130_; 2797 | _zz_131_[4] = _zz_130_; 2798 | _zz_131_[3] = _zz_130_; 2799 | _zz_131_[2] = _zz_130_; 2800 | _zz_131_[1] = _zz_130_; 2801 | _zz_131_[0] = _zz_130_; 2802 | end 2803 | 2804 | assign _zz_132_ = _zz_221_[11]; 2805 | always @ (*) begin 2806 | _zz_133_[19] = _zz_132_; 2807 | _zz_133_[18] = _zz_132_; 2808 | _zz_133_[17] = _zz_132_; 2809 | _zz_133_[16] = _zz_132_; 2810 | _zz_133_[15] = _zz_132_; 2811 | _zz_133_[14] = _zz_132_; 2812 | _zz_133_[13] = _zz_132_; 2813 | _zz_133_[12] = _zz_132_; 2814 | _zz_133_[11] = _zz_132_; 2815 | _zz_133_[10] = _zz_132_; 2816 | _zz_133_[9] = _zz_132_; 2817 | _zz_133_[8] = _zz_132_; 2818 | _zz_133_[7] = _zz_132_; 2819 | _zz_133_[6] = _zz_132_; 2820 | _zz_133_[5] = _zz_132_; 2821 | _zz_133_[4] = _zz_132_; 2822 | _zz_133_[3] = _zz_132_; 2823 | _zz_133_[2] = _zz_132_; 2824 | _zz_133_[1] = _zz_132_; 2825 | _zz_133_[0] = _zz_132_; 2826 | end 2827 | 2828 | always @ (*) begin 2829 | case(execute_SRC2_CTRL) 2830 | `Src2CtrlEnum_defaultEncoding_RS : begin 2831 | _zz_134_ = execute_RS2; 2832 | end 2833 | `Src2CtrlEnum_defaultEncoding_IMI : begin 2834 | _zz_134_ = {_zz_131_,execute_INSTRUCTION[31 : 20]}; 2835 | end 2836 | `Src2CtrlEnum_defaultEncoding_IMS : begin 2837 | _zz_134_ = {_zz_133_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; 2838 | end 2839 | default : begin 2840 | _zz_134_ = _zz_39_; 2841 | end 2842 | endcase 2843 | end 2844 | 2845 | assign _zz_41_ = _zz_134_; 2846 | always @ (*) begin 2847 | execute_SrcPlugin_addSub = _zz_222_; 2848 | if(execute_SRC2_FORCE_ZERO)begin 2849 | execute_SrcPlugin_addSub = execute_SRC1; 2850 | end 2851 | end 2852 | 2853 | assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); 2854 | assign _zz_38_ = execute_SrcPlugin_addSub; 2855 | assign _zz_37_ = execute_SrcPlugin_addSub; 2856 | assign _zz_36_ = execute_SrcPlugin_less; 2857 | assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); 2858 | assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); 2859 | assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); 2860 | assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); 2861 | always @ (*) begin 2862 | case(execute_SHIFT_CTRL) 2863 | `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin 2864 | _zz_135_ = (execute_LightShifterPlugin_shiftInput <<< 1); 2865 | end 2866 | default : begin 2867 | _zz_135_ = _zz_229_; 2868 | end 2869 | endcase 2870 | end 2871 | 2872 | always @ (*) begin 2873 | _zz_136_ = 1'b0; 2874 | if(_zz_139_)begin 2875 | if((_zz_140_ == decode_INSTRUCTION[19 : 15]))begin 2876 | _zz_136_ = 1'b1; 2877 | end 2878 | end 2879 | if(_zz_180_)begin 2880 | if(_zz_181_)begin 2881 | if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin 2882 | _zz_136_ = 1'b1; 2883 | end 2884 | end 2885 | end 2886 | if(_zz_182_)begin 2887 | if(_zz_183_)begin 2888 | if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin 2889 | _zz_136_ = 1'b1; 2890 | end 2891 | end 2892 | end 2893 | if(_zz_184_)begin 2894 | if(_zz_185_)begin 2895 | if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin 2896 | _zz_136_ = 1'b1; 2897 | end 2898 | end 2899 | end 2900 | if((! decode_RS1_USE))begin 2901 | _zz_136_ = 1'b0; 2902 | end 2903 | end 2904 | 2905 | always @ (*) begin 2906 | _zz_137_ = 1'b0; 2907 | if(_zz_139_)begin 2908 | if((_zz_140_ == decode_INSTRUCTION[24 : 20]))begin 2909 | _zz_137_ = 1'b1; 2910 | end 2911 | end 2912 | if(_zz_180_)begin 2913 | if(_zz_181_)begin 2914 | if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin 2915 | _zz_137_ = 1'b1; 2916 | end 2917 | end 2918 | end 2919 | if(_zz_182_)begin 2920 | if(_zz_183_)begin 2921 | if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin 2922 | _zz_137_ = 1'b1; 2923 | end 2924 | end 2925 | end 2926 | if(_zz_184_)begin 2927 | if(_zz_185_)begin 2928 | if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin 2929 | _zz_137_ = 1'b1; 2930 | end 2931 | end 2932 | end 2933 | if((! decode_RS2_USE))begin 2934 | _zz_137_ = 1'b0; 2935 | end 2936 | end 2937 | 2938 | assign _zz_138_ = (_zz_49_ && writeBack_arbitration_isFiring); 2939 | assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); 2940 | assign _zz_141_ = execute_INSTRUCTION[14 : 12]; 2941 | always @ (*) begin 2942 | if((_zz_141_ == (3'b000))) begin 2943 | _zz_142_ = execute_BranchPlugin_eq; 2944 | end else if((_zz_141_ == (3'b001))) begin 2945 | _zz_142_ = (! execute_BranchPlugin_eq); 2946 | end else if((((_zz_141_ & (3'b101)) == (3'b101)))) begin 2947 | _zz_142_ = (! execute_SRC_LESS); 2948 | end else begin 2949 | _zz_142_ = execute_SRC_LESS; 2950 | end 2951 | end 2952 | 2953 | always @ (*) begin 2954 | case(execute_BRANCH_CTRL) 2955 | `BranchCtrlEnum_defaultEncoding_INC : begin 2956 | _zz_143_ = 1'b0; 2957 | end 2958 | `BranchCtrlEnum_defaultEncoding_JAL : begin 2959 | _zz_143_ = 1'b1; 2960 | end 2961 | `BranchCtrlEnum_defaultEncoding_JALR : begin 2962 | _zz_143_ = 1'b1; 2963 | end 2964 | default : begin 2965 | _zz_143_ = _zz_142_; 2966 | end 2967 | endcase 2968 | end 2969 | 2970 | assign _zz_33_ = _zz_143_; 2971 | assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); 2972 | assign _zz_144_ = _zz_231_[19]; 2973 | always @ (*) begin 2974 | _zz_145_[10] = _zz_144_; 2975 | _zz_145_[9] = _zz_144_; 2976 | _zz_145_[8] = _zz_144_; 2977 | _zz_145_[7] = _zz_144_; 2978 | _zz_145_[6] = _zz_144_; 2979 | _zz_145_[5] = _zz_144_; 2980 | _zz_145_[4] = _zz_144_; 2981 | _zz_145_[3] = _zz_144_; 2982 | _zz_145_[2] = _zz_144_; 2983 | _zz_145_[1] = _zz_144_; 2984 | _zz_145_[0] = _zz_144_; 2985 | end 2986 | 2987 | assign _zz_146_ = _zz_232_[11]; 2988 | always @ (*) begin 2989 | _zz_147_[19] = _zz_146_; 2990 | _zz_147_[18] = _zz_146_; 2991 | _zz_147_[17] = _zz_146_; 2992 | _zz_147_[16] = _zz_146_; 2993 | _zz_147_[15] = _zz_146_; 2994 | _zz_147_[14] = _zz_146_; 2995 | _zz_147_[13] = _zz_146_; 2996 | _zz_147_[12] = _zz_146_; 2997 | _zz_147_[11] = _zz_146_; 2998 | _zz_147_[10] = _zz_146_; 2999 | _zz_147_[9] = _zz_146_; 3000 | _zz_147_[8] = _zz_146_; 3001 | _zz_147_[7] = _zz_146_; 3002 | _zz_147_[6] = _zz_146_; 3003 | _zz_147_[5] = _zz_146_; 3004 | _zz_147_[4] = _zz_146_; 3005 | _zz_147_[3] = _zz_146_; 3006 | _zz_147_[2] = _zz_146_; 3007 | _zz_147_[1] = _zz_146_; 3008 | _zz_147_[0] = _zz_146_; 3009 | end 3010 | 3011 | assign _zz_148_ = _zz_233_[11]; 3012 | always @ (*) begin 3013 | _zz_149_[18] = _zz_148_; 3014 | _zz_149_[17] = _zz_148_; 3015 | _zz_149_[16] = _zz_148_; 3016 | _zz_149_[15] = _zz_148_; 3017 | _zz_149_[14] = _zz_148_; 3018 | _zz_149_[13] = _zz_148_; 3019 | _zz_149_[12] = _zz_148_; 3020 | _zz_149_[11] = _zz_148_; 3021 | _zz_149_[10] = _zz_148_; 3022 | _zz_149_[9] = _zz_148_; 3023 | _zz_149_[8] = _zz_148_; 3024 | _zz_149_[7] = _zz_148_; 3025 | _zz_149_[6] = _zz_148_; 3026 | _zz_149_[5] = _zz_148_; 3027 | _zz_149_[4] = _zz_148_; 3028 | _zz_149_[3] = _zz_148_; 3029 | _zz_149_[2] = _zz_148_; 3030 | _zz_149_[1] = _zz_148_; 3031 | _zz_149_[0] = _zz_148_; 3032 | end 3033 | 3034 | always @ (*) begin 3035 | case(execute_BRANCH_CTRL) 3036 | `BranchCtrlEnum_defaultEncoding_JAL : begin 3037 | _zz_150_ = {{_zz_145_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; 3038 | end 3039 | `BranchCtrlEnum_defaultEncoding_JALR : begin 3040 | _zz_150_ = {_zz_147_,execute_INSTRUCTION[31 : 20]}; 3041 | end 3042 | default : begin 3043 | _zz_150_ = {{_zz_149_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; 3044 | end 3045 | endcase 3046 | end 3047 | 3048 | assign execute_BranchPlugin_branch_src2 = _zz_150_; 3049 | assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); 3050 | assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; 3051 | assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && (! memory_arbitration_isStuckByOthers)) && memory_BRANCH_DO); 3052 | assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; 3053 | assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); 3054 | assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); 3055 | assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; 3056 | always @ (*) begin 3057 | CsrPlugin_privilege = (2'b11); 3058 | if(CsrPlugin_forceMachineWire)begin 3059 | CsrPlugin_privilege = (2'b11); 3060 | end 3061 | end 3062 | 3063 | assign CsrPlugin_misa_base = (2'b01); 3064 | assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); 3065 | assign _zz_151_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); 3066 | assign _zz_152_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); 3067 | assign _zz_153_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); 3068 | assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); 3069 | assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); 3070 | assign _zz_154_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; 3071 | assign _zz_155_ = _zz_234_[0]; 3072 | assign _zz_156_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; 3073 | assign _zz_157_ = _zz_236_[0]; 3074 | always @ (*) begin 3075 | CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; 3076 | if(_zz_169_)begin 3077 | CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; 3078 | end 3079 | if(decode_arbitration_isFlushed)begin 3080 | CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; 3081 | end 3082 | end 3083 | 3084 | always @ (*) begin 3085 | CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; 3086 | if(execute_arbitration_isFlushed)begin 3087 | CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; 3088 | end 3089 | end 3090 | 3091 | always @ (*) begin 3092 | CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; 3093 | if(_zz_171_)begin 3094 | CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; 3095 | end 3096 | if(memory_arbitration_isFlushed)begin 3097 | CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; 3098 | end 3099 | end 3100 | 3101 | always @ (*) begin 3102 | CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; 3103 | if(writeBack_arbitration_isFlushed)begin 3104 | CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; 3105 | end 3106 | end 3107 | 3108 | assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; 3109 | assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; 3110 | assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; 3111 | assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; 3112 | assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); 3113 | assign CsrPlugin_lastStageWasWfi = 1'b0; 3114 | always @ (*) begin 3115 | CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3); 3116 | if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin 3117 | CsrPlugin_pipelineLiberator_done = 1'b0; 3118 | end 3119 | if(CsrPlugin_hadException)begin 3120 | CsrPlugin_pipelineLiberator_done = 1'b0; 3121 | end 3122 | end 3123 | 3124 | assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); 3125 | always @ (*) begin 3126 | CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; 3127 | if(CsrPlugin_hadException)begin 3128 | CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; 3129 | end 3130 | end 3131 | 3132 | always @ (*) begin 3133 | CsrPlugin_trapCause = CsrPlugin_interrupt_code; 3134 | if(CsrPlugin_hadException)begin 3135 | CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; 3136 | end 3137 | end 3138 | 3139 | always @ (*) begin 3140 | CsrPlugin_xtvec_mode = (2'bxx); 3141 | case(CsrPlugin_targetPrivilege) 3142 | 2'b11 : begin 3143 | CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; 3144 | end 3145 | default : begin 3146 | end 3147 | endcase 3148 | end 3149 | 3150 | always @ (*) begin 3151 | CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); 3152 | case(CsrPlugin_targetPrivilege) 3153 | 2'b11 : begin 3154 | CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; 3155 | end 3156 | default : begin 3157 | end 3158 | endcase 3159 | end 3160 | 3161 | assign contextSwitching = CsrPlugin_jumpInterface_valid; 3162 | assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); 3163 | assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); 3164 | assign execute_CsrPlugin_inWfi = 1'b0; 3165 | assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); 3166 | always @ (*) begin 3167 | execute_CsrPlugin_illegalAccess = 1'b1; 3168 | case(execute_CsrPlugin_csrAddress) 3169 | 12'b101111000000 : begin 3170 | execute_CsrPlugin_illegalAccess = 1'b0; 3171 | end 3172 | 12'b001100000000 : begin 3173 | execute_CsrPlugin_illegalAccess = 1'b0; 3174 | end 3175 | 12'b001101000001 : begin 3176 | execute_CsrPlugin_illegalAccess = 1'b0; 3177 | end 3178 | 12'b001100000101 : begin 3179 | if(execute_CSR_WRITE_OPCODE)begin 3180 | execute_CsrPlugin_illegalAccess = 1'b0; 3181 | end 3182 | end 3183 | 12'b001101000100 : begin 3184 | execute_CsrPlugin_illegalAccess = 1'b0; 3185 | end 3186 | 12'b001101000011 : begin 3187 | if(execute_CSR_READ_OPCODE)begin 3188 | execute_CsrPlugin_illegalAccess = 1'b0; 3189 | end 3190 | end 3191 | 12'b111111000000 : begin 3192 | if(execute_CSR_READ_OPCODE)begin 3193 | execute_CsrPlugin_illegalAccess = 1'b0; 3194 | end 3195 | end 3196 | 12'b001100000100 : begin 3197 | execute_CsrPlugin_illegalAccess = 1'b0; 3198 | end 3199 | 12'b001101000010 : begin 3200 | if(execute_CSR_READ_OPCODE)begin 3201 | execute_CsrPlugin_illegalAccess = 1'b0; 3202 | end 3203 | end 3204 | default : begin 3205 | end 3206 | endcase 3207 | if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin 3208 | execute_CsrPlugin_illegalAccess = 1'b1; 3209 | end 3210 | if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin 3211 | execute_CsrPlugin_illegalAccess = 1'b0; 3212 | end 3213 | end 3214 | 3215 | always @ (*) begin 3216 | execute_CsrPlugin_illegalInstruction = 1'b0; 3217 | if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin 3218 | if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin 3219 | execute_CsrPlugin_illegalInstruction = 1'b1; 3220 | end 3221 | end 3222 | end 3223 | 3224 | always @ (*) begin 3225 | execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); 3226 | case(execute_CsrPlugin_csrAddress) 3227 | 12'b101111000000 : begin 3228 | execute_CsrPlugin_readData[31 : 0] = _zz_158_; 3229 | end 3230 | 12'b001100000000 : begin 3231 | execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; 3232 | execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; 3233 | execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; 3234 | end 3235 | 12'b001101000001 : begin 3236 | execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; 3237 | end 3238 | 12'b001100000101 : begin 3239 | end 3240 | 12'b001101000100 : begin 3241 | execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; 3242 | execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; 3243 | execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; 3244 | end 3245 | 12'b001101000011 : begin 3246 | execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; 3247 | end 3248 | 12'b111111000000 : begin 3249 | execute_CsrPlugin_readData[31 : 0] = _zz_159_; 3250 | end 3251 | 12'b001100000100 : begin 3252 | execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; 3253 | execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; 3254 | execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; 3255 | end 3256 | 12'b001101000010 : begin 3257 | execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; 3258 | execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; 3259 | end 3260 | default : begin 3261 | end 3262 | endcase 3263 | end 3264 | 3265 | assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); 3266 | assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); 3267 | assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); 3268 | assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); 3269 | assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; 3270 | always @ (*) begin 3271 | case(_zz_192_) 3272 | 1'b0 : begin 3273 | execute_CsrPlugin_writeData = execute_SRC1; 3274 | end 3275 | default : begin 3276 | execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); 3277 | end 3278 | endcase 3279 | end 3280 | 3281 | assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; 3282 | assign _zz_159_ = (_zz_158_ & externalInterruptArray_regNext); 3283 | assign externalInterrupt = (_zz_159_ != (32'b00000000000000000000000000000000)); 3284 | assign _zz_25_ = decode_BRANCH_CTRL; 3285 | assign _zz_23_ = _zz_70_; 3286 | assign _zz_32_ = decode_to_execute_BRANCH_CTRL; 3287 | assign _zz_22_ = decode_SHIFT_CTRL; 3288 | assign _zz_20_ = _zz_55_; 3289 | assign _zz_35_ = decode_to_execute_SHIFT_CTRL; 3290 | assign _zz_19_ = decode_ENV_CTRL; 3291 | assign _zz_16_ = execute_ENV_CTRL; 3292 | assign _zz_14_ = memory_ENV_CTRL; 3293 | assign _zz_17_ = _zz_61_; 3294 | assign _zz_27_ = decode_to_execute_ENV_CTRL; 3295 | assign _zz_26_ = execute_to_memory_ENV_CTRL; 3296 | assign _zz_30_ = memory_to_writeBack_ENV_CTRL; 3297 | assign _zz_12_ = decode_SRC2_CTRL; 3298 | assign _zz_10_ = _zz_54_; 3299 | assign _zz_40_ = decode_to_execute_SRC2_CTRL; 3300 | assign _zz_9_ = decode_ALU_BITWISE_CTRL; 3301 | assign _zz_7_ = _zz_58_; 3302 | assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL; 3303 | assign _zz_6_ = decode_ALU_CTRL; 3304 | assign _zz_4_ = _zz_62_; 3305 | assign _zz_45_ = decode_to_execute_ALU_CTRL; 3306 | assign _zz_3_ = decode_SRC1_CTRL; 3307 | assign _zz_1_ = _zz_65_; 3308 | assign _zz_42_ = decode_to_execute_SRC1_CTRL; 3309 | assign decode_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,{execute_arbitration_flushAll,decode_arbitration_flushAll}}} != (4'b0000)); 3310 | assign execute_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,execute_arbitration_flushAll}} != (3'b000)); 3311 | assign memory_arbitration_isFlushed = ({writeBack_arbitration_flushAll,memory_arbitration_flushAll} != (2'b00)); 3312 | assign writeBack_arbitration_isFlushed = (writeBack_arbitration_flushAll != (1'b0)); 3313 | assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); 3314 | assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); 3315 | assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); 3316 | assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); 3317 | assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); 3318 | assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); 3319 | assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); 3320 | assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); 3321 | assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); 3322 | assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); 3323 | assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); 3324 | assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); 3325 | assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); 3326 | assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); 3327 | assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); 3328 | assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); 3329 | assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); 3330 | assign iBus_cmd_m2sPipe_valid = _zz_160_; 3331 | assign iBus_cmd_m2sPipe_payload_pc = _zz_161_; 3332 | assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); 3333 | assign iBusWishbone_CTI = (3'b000); 3334 | assign iBusWishbone_BTE = (2'b00); 3335 | assign iBusWishbone_SEL = (4'b1111); 3336 | assign iBusWishbone_WE = 1'b0; 3337 | assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); 3338 | assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; 3339 | assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; 3340 | assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); 3341 | assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); 3342 | assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; 3343 | assign iBus_rsp_payload_error = 1'b0; 3344 | assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; 3345 | assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; 3346 | assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; 3347 | assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; 3348 | assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; 3349 | assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; 3350 | assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); 3351 | assign dBusWishbone_CTI = (3'b000); 3352 | assign dBusWishbone_BTE = (2'b00); 3353 | always @ (*) begin 3354 | case(dBus_cmd_halfPipe_payload_size) 3355 | 2'b00 : begin 3356 | _zz_162_ = (4'b0001); 3357 | end 3358 | 2'b01 : begin 3359 | _zz_162_ = (4'b0011); 3360 | end 3361 | default : begin 3362 | _zz_162_ = (4'b1111); 3363 | end 3364 | endcase 3365 | end 3366 | 3367 | always @ (*) begin 3368 | dBusWishbone_SEL = _zz_244_[3:0]; 3369 | if((! dBus_cmd_halfPipe_payload_wr))begin 3370 | dBusWishbone_SEL = (4'b1111); 3371 | end 3372 | end 3373 | 3374 | assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; 3375 | assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; 3376 | assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); 3377 | assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; 3378 | assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; 3379 | assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); 3380 | assign dBus_rsp_data = dBusWishbone_DAT_MISO; 3381 | assign dBus_rsp_error = 1'b0; 3382 | always @ (posedge clk) begin 3383 | if(reset) begin 3384 | IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; 3385 | IBusSimplePlugin_fetchPc_inc <= 1'b0; 3386 | _zz_96_ <= 1'b0; 3387 | _zz_101_ <= 1'b0; 3388 | _zz_102_ <= 1'b0; 3389 | IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; 3390 | IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; 3391 | IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; 3392 | IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; 3393 | IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; 3394 | IBusSimplePlugin_injector_decodeRemoved <= 1'b0; 3395 | IBusSimplePlugin_pendingCmd <= (3'b000); 3396 | IBusSimplePlugin_rspJoin_discardCounter <= (3'b000); 3397 | _zz_127_ <= 1'b1; 3398 | execute_LightShifterPlugin_isActive <= 1'b0; 3399 | _zz_139_ <= 1'b0; 3400 | CsrPlugin_mstatus_MIE <= 1'b0; 3401 | CsrPlugin_mstatus_MPIE <= 1'b0; 3402 | CsrPlugin_mstatus_MPP <= (2'b11); 3403 | CsrPlugin_mie_MEIE <= 1'b0; 3404 | CsrPlugin_mie_MTIE <= 1'b0; 3405 | CsrPlugin_mie_MSIE <= 1'b0; 3406 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; 3407 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; 3408 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; 3409 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; 3410 | CsrPlugin_interrupt_valid <= 1'b0; 3411 | CsrPlugin_hadException <= 1'b0; 3412 | execute_CsrPlugin_wfiWake <= 1'b0; 3413 | _zz_158_ <= (32'b00000000000000000000000000000000); 3414 | execute_arbitration_isValid <= 1'b0; 3415 | memory_arbitration_isValid <= 1'b0; 3416 | writeBack_arbitration_isValid <= 1'b0; 3417 | memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); 3418 | memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); 3419 | _zz_160_ <= 1'b0; 3420 | dBus_cmd_halfPipe_regs_valid <= 1'b0; 3421 | dBus_cmd_halfPipe_regs_ready <= 1'b1; 3422 | end else begin 3423 | if(IBusSimplePlugin_fetchPc_propagatePc)begin 3424 | IBusSimplePlugin_fetchPc_inc <= 1'b0; 3425 | end 3426 | if(IBusSimplePlugin_jump_pcLoad_valid)begin 3427 | IBusSimplePlugin_fetchPc_inc <= 1'b0; 3428 | end 3429 | if(_zz_175_)begin 3430 | IBusSimplePlugin_fetchPc_inc <= 1'b1; 3431 | end 3432 | if(IBusSimplePlugin_fetchPc_samplePcNext)begin 3433 | IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; 3434 | end 3435 | _zz_96_ <= 1'b1; 3436 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3437 | _zz_101_ <= 1'b0; 3438 | end 3439 | if(_zz_99_)begin 3440 | _zz_101_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; 3441 | end 3442 | if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin 3443 | _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; 3444 | end 3445 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3446 | _zz_102_ <= 1'b0; 3447 | end 3448 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3449 | IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; 3450 | end 3451 | if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin 3452 | IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; 3453 | end 3454 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3455 | IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; 3456 | end 3457 | if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin 3458 | IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; 3459 | end 3460 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3461 | IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; 3462 | end 3463 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3464 | IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; 3465 | end 3466 | if((! execute_arbitration_isStuck))begin 3467 | IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; 3468 | end 3469 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3470 | IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; 3471 | end 3472 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3473 | IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; 3474 | end 3475 | if((! memory_arbitration_isStuck))begin 3476 | IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; 3477 | end 3478 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3479 | IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; 3480 | end 3481 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3482 | IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; 3483 | end 3484 | if((! writeBack_arbitration_isStuck))begin 3485 | IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; 3486 | end 3487 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3488 | IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; 3489 | end 3490 | if(decode_arbitration_removeIt)begin 3491 | IBusSimplePlugin_injector_decodeRemoved <= 1'b1; 3492 | end 3493 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3494 | IBusSimplePlugin_injector_decodeRemoved <= 1'b0; 3495 | end 3496 | IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; 3497 | IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_202_); 3498 | if((IBusSimplePlugin_jump_pcLoad_valid || IBusSimplePlugin_fetcherflushIt))begin 3499 | IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_204_); 3500 | end 3501 | _zz_127_ <= 1'b0; 3502 | if(_zz_167_)begin 3503 | if(_zz_170_)begin 3504 | execute_LightShifterPlugin_isActive <= 1'b1; 3505 | if(execute_LightShifterPlugin_done)begin 3506 | execute_LightShifterPlugin_isActive <= 1'b0; 3507 | end 3508 | end 3509 | end 3510 | if(execute_arbitration_removeIt)begin 3511 | execute_LightShifterPlugin_isActive <= 1'b0; 3512 | end 3513 | _zz_139_ <= _zz_138_; 3514 | if((! decode_arbitration_isStuck))begin 3515 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; 3516 | end else begin 3517 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; 3518 | end 3519 | if((! execute_arbitration_isStuck))begin 3520 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); 3521 | end else begin 3522 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; 3523 | end 3524 | if((! memory_arbitration_isStuck))begin 3525 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); 3526 | end else begin 3527 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; 3528 | end 3529 | if((! writeBack_arbitration_isStuck))begin 3530 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); 3531 | end else begin 3532 | CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; 3533 | end 3534 | CsrPlugin_interrupt_valid <= 1'b0; 3535 | if(_zz_186_)begin 3536 | if(_zz_187_)begin 3537 | CsrPlugin_interrupt_valid <= 1'b1; 3538 | end 3539 | if(_zz_188_)begin 3540 | CsrPlugin_interrupt_valid <= 1'b1; 3541 | end 3542 | if(_zz_189_)begin 3543 | CsrPlugin_interrupt_valid <= 1'b1; 3544 | end 3545 | end 3546 | CsrPlugin_hadException <= CsrPlugin_exception; 3547 | if(_zz_172_)begin 3548 | case(CsrPlugin_targetPrivilege) 3549 | 2'b11 : begin 3550 | CsrPlugin_mstatus_MIE <= 1'b0; 3551 | CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; 3552 | CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; 3553 | end 3554 | default : begin 3555 | end 3556 | endcase 3557 | end 3558 | if(_zz_173_)begin 3559 | case(_zz_174_) 3560 | 2'b11 : begin 3561 | CsrPlugin_mstatus_MPP <= (2'b00); 3562 | CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; 3563 | CsrPlugin_mstatus_MPIE <= 1'b1; 3564 | end 3565 | default : begin 3566 | end 3567 | endcase 3568 | end 3569 | execute_CsrPlugin_wfiWake <= ({_zz_153_,{_zz_152_,_zz_151_}} != (3'b000)); 3570 | if((! writeBack_arbitration_isStuck))begin 3571 | memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; 3572 | end 3573 | if((! writeBack_arbitration_isStuck))begin 3574 | memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; 3575 | end 3576 | if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin 3577 | execute_arbitration_isValid <= 1'b0; 3578 | end 3579 | if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin 3580 | execute_arbitration_isValid <= decode_arbitration_isValid; 3581 | end 3582 | if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin 3583 | memory_arbitration_isValid <= 1'b0; 3584 | end 3585 | if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin 3586 | memory_arbitration_isValid <= execute_arbitration_isValid; 3587 | end 3588 | if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin 3589 | writeBack_arbitration_isValid <= 1'b0; 3590 | end 3591 | if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin 3592 | writeBack_arbitration_isValid <= memory_arbitration_isValid; 3593 | end 3594 | case(execute_CsrPlugin_csrAddress) 3595 | 12'b101111000000 : begin 3596 | if(execute_CsrPlugin_writeEnable)begin 3597 | _zz_158_ <= execute_CsrPlugin_writeData[31 : 0]; 3598 | end 3599 | end 3600 | 12'b001100000000 : begin 3601 | if(execute_CsrPlugin_writeEnable)begin 3602 | CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; 3603 | CsrPlugin_mstatus_MPIE <= _zz_238_[0]; 3604 | CsrPlugin_mstatus_MIE <= _zz_239_[0]; 3605 | end 3606 | end 3607 | 12'b001101000001 : begin 3608 | end 3609 | 12'b001100000101 : begin 3610 | end 3611 | 12'b001101000100 : begin 3612 | end 3613 | 12'b001101000011 : begin 3614 | end 3615 | 12'b111111000000 : begin 3616 | end 3617 | 12'b001100000100 : begin 3618 | if(execute_CsrPlugin_writeEnable)begin 3619 | CsrPlugin_mie_MEIE <= _zz_241_[0]; 3620 | CsrPlugin_mie_MTIE <= _zz_242_[0]; 3621 | CsrPlugin_mie_MSIE <= _zz_243_[0]; 3622 | end 3623 | end 3624 | 12'b001101000010 : begin 3625 | end 3626 | default : begin 3627 | end 3628 | endcase 3629 | if(iBus_cmd_ready)begin 3630 | _zz_160_ <= iBus_cmd_valid; 3631 | end 3632 | if(_zz_190_)begin 3633 | dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; 3634 | dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); 3635 | end else begin 3636 | dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); 3637 | dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; 3638 | end 3639 | end 3640 | end 3641 | 3642 | always @ (posedge clk) begin 3643 | if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin 3644 | _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; 3645 | _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; 3646 | _zz_105_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; 3647 | _zz_106_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; 3648 | end 3649 | if(IBusSimplePlugin_injector_decodeInput_ready)begin 3650 | IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; 3651 | end 3652 | if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin 3653 | IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; 3654 | IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; 3655 | IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; 3656 | IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; 3657 | IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; 3658 | IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; 3659 | IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; 3660 | end 3661 | if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin 3662 | $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); 3663 | end 3664 | if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin 3665 | $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); 3666 | end 3667 | if(_zz_167_)begin 3668 | if(_zz_170_)begin 3669 | execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); 3670 | end 3671 | end 3672 | if(_zz_138_)begin 3673 | _zz_140_ <= _zz_48_[11 : 7]; 3674 | end 3675 | CsrPlugin_mip_MEIP <= externalInterrupt; 3676 | CsrPlugin_mip_MTIP <= timerInterrupt; 3677 | CsrPlugin_mip_MSIP <= softwareInterrupt; 3678 | CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); 3679 | if(writeBack_arbitration_isFiring)begin 3680 | CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); 3681 | end 3682 | if(_zz_169_)begin 3683 | CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); 3684 | CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); 3685 | end 3686 | if(_zz_171_)begin 3687 | CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_157_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); 3688 | CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_157_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); 3689 | end 3690 | if(_zz_186_)begin 3691 | if(_zz_187_)begin 3692 | CsrPlugin_interrupt_code <= (4'b0111); 3693 | CsrPlugin_interrupt_targetPrivilege <= (2'b11); 3694 | end 3695 | if(_zz_188_)begin 3696 | CsrPlugin_interrupt_code <= (4'b0011); 3697 | CsrPlugin_interrupt_targetPrivilege <= (2'b11); 3698 | end 3699 | if(_zz_189_)begin 3700 | CsrPlugin_interrupt_code <= (4'b1011); 3701 | CsrPlugin_interrupt_targetPrivilege <= (2'b11); 3702 | end 3703 | end 3704 | if(_zz_172_)begin 3705 | case(CsrPlugin_targetPrivilege) 3706 | 2'b11 : begin 3707 | CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); 3708 | CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; 3709 | CsrPlugin_mepc <= writeBack_PC; 3710 | if(CsrPlugin_hadException)begin 3711 | CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; 3712 | end 3713 | end 3714 | default : begin 3715 | end 3716 | endcase 3717 | end 3718 | externalInterruptArray_regNext <= externalInterruptArray; 3719 | if((! memory_arbitration_isStuck))begin 3720 | execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; 3721 | execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; 3722 | execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; 3723 | execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; 3724 | execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; 3725 | execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; 3726 | execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; 3727 | end 3728 | if((! execute_arbitration_isStuck))begin 3729 | decode_to_execute_BRANCH_CTRL <= _zz_24_; 3730 | end 3731 | if((! execute_arbitration_isStuck))begin 3732 | decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; 3733 | end 3734 | if((! memory_arbitration_isStuck))begin 3735 | execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; 3736 | end 3737 | if((! execute_arbitration_isStuck))begin 3738 | decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; 3739 | end 3740 | if((! memory_arbitration_isStuck))begin 3741 | execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; 3742 | end 3743 | if((! writeBack_arbitration_isStuck))begin 3744 | memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; 3745 | end 3746 | if((! execute_arbitration_isStuck))begin 3747 | decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; 3748 | end 3749 | if((! execute_arbitration_isStuck))begin 3750 | decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; 3751 | end 3752 | if((! execute_arbitration_isStuck))begin 3753 | decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; 3754 | end 3755 | if((! memory_arbitration_isStuck))begin 3756 | execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; 3757 | end 3758 | if((! writeBack_arbitration_isStuck))begin 3759 | memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; 3760 | end 3761 | if((! execute_arbitration_isStuck))begin 3762 | decode_to_execute_SHIFT_CTRL <= _zz_21_; 3763 | end 3764 | if((! execute_arbitration_isStuck))begin 3765 | decode_to_execute_ENV_CTRL <= _zz_18_; 3766 | end 3767 | if((! memory_arbitration_isStuck))begin 3768 | execute_to_memory_ENV_CTRL <= _zz_15_; 3769 | end 3770 | if((! writeBack_arbitration_isStuck))begin 3771 | memory_to_writeBack_ENV_CTRL <= _zz_13_; 3772 | end 3773 | if((! execute_arbitration_isStuck))begin 3774 | decode_to_execute_RS2 <= decode_RS2; 3775 | end 3776 | if((! execute_arbitration_isStuck))begin 3777 | decode_to_execute_IS_CSR <= decode_IS_CSR; 3778 | end 3779 | if((! execute_arbitration_isStuck))begin 3780 | decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; 3781 | end 3782 | if((! memory_arbitration_isStuck))begin 3783 | execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; 3784 | end 3785 | if((! execute_arbitration_isStuck))begin 3786 | decode_to_execute_PC <= decode_PC; 3787 | end 3788 | if((! memory_arbitration_isStuck))begin 3789 | execute_to_memory_PC <= _zz_39_; 3790 | end 3791 | if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin 3792 | memory_to_writeBack_PC <= memory_PC; 3793 | end 3794 | if((! execute_arbitration_isStuck))begin 3795 | decode_to_execute_SRC2_CTRL <= _zz_11_; 3796 | end 3797 | if((! execute_arbitration_isStuck))begin 3798 | decode_to_execute_ALU_BITWISE_CTRL <= _zz_8_; 3799 | end 3800 | if((! execute_arbitration_isStuck))begin 3801 | decode_to_execute_ALU_CTRL <= _zz_5_; 3802 | end 3803 | if((! memory_arbitration_isStuck))begin 3804 | execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; 3805 | end 3806 | if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin 3807 | execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_; 3808 | end 3809 | if((! execute_arbitration_isStuck))begin 3810 | decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; 3811 | end 3812 | if((! writeBack_arbitration_isStuck))begin 3813 | memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; 3814 | end 3815 | if((! execute_arbitration_isStuck))begin 3816 | decode_to_execute_SRC1_CTRL <= _zz_2_; 3817 | end 3818 | if((! memory_arbitration_isStuck))begin 3819 | execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; 3820 | end 3821 | if((! execute_arbitration_isStuck))begin 3822 | decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; 3823 | end 3824 | if((! memory_arbitration_isStuck))begin 3825 | execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; 3826 | end 3827 | if((! writeBack_arbitration_isStuck))begin 3828 | memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; 3829 | end 3830 | if((! execute_arbitration_isStuck))begin 3831 | decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; 3832 | end 3833 | if((! memory_arbitration_isStuck))begin 3834 | execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; 3835 | end 3836 | if((! writeBack_arbitration_isStuck))begin 3837 | memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; 3838 | end 3839 | if((! memory_arbitration_isStuck))begin 3840 | execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; 3841 | end 3842 | if((! execute_arbitration_isStuck))begin 3843 | decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; 3844 | end 3845 | if((! execute_arbitration_isStuck))begin 3846 | decode_to_execute_RS1 <= decode_RS1; 3847 | end 3848 | if((! execute_arbitration_isStuck))begin 3849 | decode_to_execute_FORMAL_PC_NEXT <= _zz_85_; 3850 | end 3851 | if((! memory_arbitration_isStuck))begin 3852 | execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; 3853 | end 3854 | if((! writeBack_arbitration_isStuck))begin 3855 | memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_; 3856 | end 3857 | if((! memory_arbitration_isStuck))begin 3858 | execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; 3859 | end 3860 | if((! execute_arbitration_isStuck))begin 3861 | decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; 3862 | end 3863 | case(execute_CsrPlugin_csrAddress) 3864 | 12'b101111000000 : begin 3865 | end 3866 | 12'b001100000000 : begin 3867 | end 3868 | 12'b001101000001 : begin 3869 | if(execute_CsrPlugin_writeEnable)begin 3870 | CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; 3871 | end 3872 | end 3873 | 12'b001100000101 : begin 3874 | if(execute_CsrPlugin_writeEnable)begin 3875 | CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; 3876 | CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; 3877 | end 3878 | end 3879 | 12'b001101000100 : begin 3880 | if(execute_CsrPlugin_writeEnable)begin 3881 | CsrPlugin_mip_MSIP <= _zz_240_[0]; 3882 | end 3883 | end 3884 | 12'b001101000011 : begin 3885 | end 3886 | 12'b111111000000 : begin 3887 | end 3888 | 12'b001100000100 : begin 3889 | end 3890 | 12'b001101000010 : begin 3891 | end 3892 | default : begin 3893 | end 3894 | endcase 3895 | if(iBus_cmd_ready)begin 3896 | _zz_161_ <= iBus_cmd_payload_pc; 3897 | end 3898 | if(_zz_190_)begin 3899 | dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; 3900 | dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; 3901 | dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; 3902 | dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; 3903 | end 3904 | end 3905 | 3906 | endmodule 3907 | 3908 | -------------------------------------------------------------------------------- /VexRiscv_Min.yaml: -------------------------------------------------------------------------------- 1 | {} 2 | -------------------------------------------------------------------------------- /VexRiscv_MinDebug.yaml: -------------------------------------------------------------------------------- 1 | debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} 2 | -------------------------------------------------------------------------------- /build.sbt: -------------------------------------------------------------------------------- 1 | val spinalVersion = "1.6.0" 2 | 3 | lazy val root = (project in file(".")). 4 | settings( 5 | inThisBuild(List( 6 | organization := "com.github.spinalhdl", 7 | scalaVersion := "2.11.12", 8 | version := "0.1.0-SNAPSHOT" 9 | )), 10 | name := "VexRiscvOnWishbone", 11 | 12 | libraryDependencies ++= Seq( 13 | compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion) 14 | ) 15 | ).dependsOn(vexRiscv) 16 | 17 | lazy val vexRiscv = RootProject(file("ext/VexRiscv")) 18 | fork := true 19 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.2.7 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/GenCoreDefault.scala: -------------------------------------------------------------------------------- 1 | package vexriscv 2 | 3 | import spinal.core._ 4 | import spinal.core.internals.{ExpressionContainer, PhaseAllocateNames, PhaseContext} 5 | import spinal.lib._ 6 | import spinal.lib.sim.Phase 7 | import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} 8 | import vexriscv.ip.fpu.FpuParameter 9 | import vexriscv.plugin.CsrAccess.WRITE_ONLY 10 | import vexriscv.plugin._ 11 | 12 | import scala.collection.mutable.ArrayBuffer 13 | 14 | object SpinalConfig extends spinal.core.SpinalConfig( 15 | defaultConfigForClockDomains = ClockDomainConfig( 16 | resetKind = spinal.core.SYNC 17 | ) 18 | ){ 19 | //Insert a compilation phase which will add a (* ram_style = "block" *) on all synchronous rams. 20 | phasesInserters += {(array) => array.insert(array.indexWhere(_.isInstanceOf[PhaseAllocateNames]) + 1, new ForceRamBlockPhase)} 21 | } 22 | 23 | case class ArgConfig( 24 | debug : Boolean = false, 25 | iCacheSize : Int = 4096, 26 | dCacheSize : Int = 4096, 27 | widenedBus : Boolean = false, 28 | pmpRegions : Int = 0, 29 | pmpGranularity : Int = 256, 30 | mulDiv : Boolean = true, 31 | atomics: Boolean = false, 32 | fpu : Boolean = false, 33 | withDouble: Boolean = false, 34 | singleCycleMulDiv : Boolean = true, 35 | singleCycleShift : Boolean = true, 36 | earlyBranch : Boolean = false, 37 | bypass : Boolean = true, 38 | externalInterruptArray : Boolean = true, 39 | resetVector : BigInt = null, 40 | machineTrapVector : BigInt = null, 41 | prediction : BranchPrediction = STATIC, 42 | outputFile : String = "VexRiscv", 43 | privateNamespace : Boolean = false, 44 | csrPluginConfig : String = "small", 45 | dBusCachedRelaxedMemoryTranslationRegister : Boolean = false, 46 | dBusCachedEarlyWaysHits : Boolean = true 47 | ) 48 | 49 | object GenCoreDefault{ 50 | val predictionMap = Map( 51 | "none" -> NONE, 52 | "static" -> STATIC, 53 | "dynamic" -> DYNAMIC, 54 | "dynamic_target" -> DYNAMIC_TARGET 55 | ) 56 | 57 | def main(args: Array[String]) { 58 | 59 | // Allow arguments to be passed ex: 60 | // sbt compile "run-main vexriscv.GenCoreDefault -d --iCacheSize=1024" 61 | val parser = new scopt.OptionParser[ArgConfig]("VexRiscvGen") { 62 | // ex :-d or --debug 63 | opt[Unit]('d', "debug") action { (_, c) => c.copy(debug = true) } text("Enable debug") 64 | // ex : -iCacheSize=XXX 65 | opt[Int]("iCacheSize") action { (v, c) => c.copy(iCacheSize = v) } text("Set instruction cache size, 0 mean no cache") 66 | // ex : -dCacheSize=XXX 67 | opt[Int]("dCacheSize") action { (v, c) => c.copy(dCacheSize = v) } text("Set data cache size, 0 mean no cache") 68 | opt[Boolean]("widenedBus") action { (v, c) => c.copy(widenedBus = v) } text("Enable 64-bits D$/I$") 69 | opt[Int]("pmpRegions") action { (v, c) => c.copy(pmpRegions = v) } text("Number of PMP regions, 0 disables PMP") 70 | opt[Int]("pmpGranularity") action { (v, c) => c.copy(pmpGranularity = v) } text("Granularity of PMP regions (in bytes)") 71 | opt[Boolean]("mulDiv") action { (v, c) => c.copy(mulDiv = v) } text("set RV32IM") 72 | opt[Boolean]("singleCycleMulDiv") action { (v, c) => c.copy(singleCycleMulDiv = v) } text("If true, MUL/DIV are single-cycle") 73 | opt[Boolean]("singleCycleShift") action { (v, c) => c.copy(singleCycleShift = v) } text("If true, SHIFTS are single-cycle") 74 | opt[Boolean]("earlyBranch") action { (v, c) => c.copy(earlyBranch = v) } text("If true, branching is performed in execute stage instead of memory stage") 75 | opt[Boolean]("bypass") action { (v, c) => c.copy(bypass = v) } text("set pipeline interlock/bypass") 76 | opt[Boolean]("externalInterruptArray") action { (v, c) => c.copy(externalInterruptArray = v) } text("switch between regular CSR and array like one") 77 | opt[Boolean]("dBusCachedRelaxedMemoryTranslationRegister") action { (v, c) => c.copy(dBusCachedRelaxedMemoryTranslationRegister = v) } text("If set, it give the d$ it's own address register between the execute/memory stage.") 78 | opt[Boolean]("dBusCachedEarlyWaysHits") action { (v, c) => c.copy(dBusCachedEarlyWaysHits = v) } text("If set, the d$ way hit calculation is done in the memory stage, else in the writeback stage.") 79 | opt[String]("resetVector") action { (v, c) => c.copy(resetVector = BigInt(if(v.startsWith("0x")) v.tail.tail else v, 16)) } text("Specify the CPU reset vector in hexadecimal. If not specified, an 32 bits input is added to the CPU to set durring instanciation") 80 | opt[String]("machineTrapVector") action { (v, c) => c.copy(machineTrapVector = BigInt(if(v.startsWith("0x")) v.tail.tail else v, 16)) } text("Specify the CPU machine trap vector in hexadecimal. If not specified, it take a unknown value when the design boot") 81 | opt[String]("prediction") action { (v, c) => c.copy(prediction = predictionMap(v)) } text("switch between regular CSR and array like one") 82 | opt[String]("outputFile") action { (v, c) => c.copy(outputFile = v) } text("output file name") 83 | opt[Boolean]("privateNamespace") action { (v, c) => c.copy(privateNamespace = v) } text("use a private namespace") 84 | opt[String]("csrPluginConfig") action { (v, c) => c.copy(csrPluginConfig = v) } text("switch between 'small', 'all', 'linux' and 'linux-minimal' version of control and status registers configuration") 85 | opt[Boolean]("atomics") action { (v, c) => c.copy(atomics = v) } text("set RV32I[A]") 86 | opt[Boolean]("fpu") action { (v, c) => c.copy(fpu = v) } text("set RV32I[F]") 87 | opt[Boolean]("withDouble") action { (v, c) => c.copy(withDouble = v) } text("set RV32I[D] instead of RV32I[F]") 88 | } 89 | val argConfig = parser.parse(args, ArgConfig()).get 90 | val linux = argConfig.csrPluginConfig.startsWith("linux") 91 | val widened_bus = argConfig.fpu && argConfig.withDouble || argConfig.widenedBus 92 | 93 | SpinalConfig.copy(netlistFileName = argConfig.outputFile + ".v", privateNamespace=argConfig.privateNamespace).generateVerilog { 94 | // Generate CPU plugin list 95 | val plugins = ArrayBuffer[Plugin[VexRiscv]]() 96 | 97 | plugins ++= List( 98 | if(argConfig.iCacheSize <= 0){ 99 | new IBusSimplePlugin( 100 | resetVector = argConfig.resetVector, 101 | prediction = argConfig.prediction, 102 | cmdForkOnSecondStage = false, 103 | cmdForkPersistence = false, //Not required as the wishbone bridge ensure it 104 | memoryTranslatorPortConfig = if(linux) MmuPortConfig(portTlbSize = 4) else null 105 | ) 106 | }else { 107 | new IBusCachedPlugin( 108 | resetVector = argConfig.resetVector, 109 | relaxedPcCalculation = false, 110 | prediction = argConfig.prediction, 111 | memoryTranslatorPortConfig = if(linux) MmuPortConfig(portTlbSize = 4) else null, 112 | config = InstructionCacheConfig( 113 | cacheSize = argConfig.iCacheSize, 114 | bytePerLine = if(widened_bus) 64 else 32, 115 | wayCount = 1, 116 | addressWidth = 32, 117 | cpuDataWidth = 32, 118 | memDataWidth = if(widened_bus) 64 else 32, 119 | catchIllegalAccess = true, 120 | catchAccessFault = true, 121 | asyncTagMemory = false, 122 | twoCycleRam = argConfig.fpu && argConfig.withDouble, 123 | twoCycleCache = true 124 | ) 125 | ) 126 | }, 127 | 128 | if(argConfig.dCacheSize <= 0){ 129 | new DBusSimplePlugin( 130 | catchAddressMisaligned = true, 131 | catchAccessFault = true, 132 | withLrSc = linux || argConfig.atomics, 133 | memoryTranslatorPortConfig = if(linux) MmuPortConfig(portTlbSize = 4) else null 134 | ) 135 | }else { 136 | new DBusCachedPlugin( 137 | dBusCmdMasterPipe = true, 138 | dBusCmdSlavePipe = true, 139 | dBusRspSlavePipe = false, 140 | relaxedMemoryTranslationRegister = argConfig.dBusCachedRelaxedMemoryTranslationRegister, 141 | config = new DataCacheConfig( 142 | cacheSize = argConfig.dCacheSize, 143 | bytePerLine = if(widened_bus) 64 else 32, 144 | wayCount = 1, 145 | addressWidth = 32, 146 | cpuDataWidth = if(widened_bus) 64 else 32, 147 | memDataWidth = if(widened_bus) 64 else 32, 148 | catchAccessError = true, 149 | catchIllegal = true, 150 | catchUnaligned = true, 151 | withLrSc = linux || argConfig.atomics, 152 | withAmo = linux || argConfig.atomics, 153 | earlyWaysHits = argConfig.dBusCachedEarlyWaysHits, 154 | withWriteAggregation = false 155 | ), 156 | memoryTranslatorPortConfig = if(linux) MmuPortConfig(portTlbSize = 4) else null, 157 | csrInfo = true 158 | ) 159 | }, 160 | if(linux) new MmuPlugin( 161 | ioRange = (x => x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF) 162 | ) else if (argConfig.pmpRegions > 0) new PmpPlugin( 163 | regions = argConfig.pmpRegions, granularity = argConfig.pmpGranularity, ioRange = _.msb 164 | ) else new StaticMemoryTranslatorPlugin( 165 | ioRange = _.msb 166 | ), 167 | new DecoderSimplePlugin( 168 | catchIllegalInstruction = true 169 | ), 170 | new RegFilePlugin( 171 | regFileReadyKind = plugin.SYNC, 172 | zeroBoot = false 173 | ), 174 | new IntAluPlugin, 175 | new SrcPlugin( 176 | separatedAddSub = false, 177 | executeInsertion = true 178 | ), 179 | if(argConfig.singleCycleShift) { 180 | new FullBarrelShifterPlugin 181 | }else { 182 | new LightShifterPlugin 183 | }, 184 | new HazardSimplePlugin( 185 | bypassExecute = argConfig.bypass, 186 | bypassMemory = argConfig.bypass, 187 | bypassWriteBack = argConfig.bypass, 188 | bypassWriteBackBuffer = argConfig.bypass, 189 | pessimisticUseSrc = false, 190 | pessimisticWriteRegFile = false, 191 | pessimisticAddressMatch = false 192 | ), 193 | new BranchPlugin( 194 | earlyBranch = argConfig.earlyBranch, 195 | catchAddressMisaligned = true 196 | ), 197 | new CsrPlugin( 198 | argConfig.csrPluginConfig match { 199 | case "small" => CsrPluginConfig.small(mtvecInit = argConfig.machineTrapVector).copy(mtvecAccess = WRITE_ONLY) 200 | case "secure" => CsrPluginConfig.secure(mtvecInit = argConfig.machineTrapVector) 201 | case "all" => CsrPluginConfig.all(mtvecInit = argConfig.machineTrapVector) 202 | case "linux" => CsrPluginConfig.linuxFull(mtVecInit = argConfig.machineTrapVector).copy(ebreakGen = false) 203 | case "linux-minimal" => CsrPluginConfig.linuxMinimal(mtVecInit = argConfig.machineTrapVector).copy(ebreakGen = false) 204 | } 205 | ), 206 | new YamlPlugin(argConfig.outputFile.concat(".yaml")) 207 | ) 208 | 209 | if(argConfig.mulDiv) { 210 | if(argConfig.singleCycleMulDiv) { 211 | plugins ++= List( 212 | new MulPlugin, 213 | new DivPlugin 214 | ) 215 | }else { 216 | plugins ++= List( 217 | new MulDivIterativePlugin( 218 | genMul = true, 219 | genDiv = true, 220 | mulUnrollFactor = 1, 221 | divUnrollFactor = 1 222 | ) 223 | ) 224 | } 225 | } 226 | 227 | if(argConfig.fpu) { 228 | plugins ++= List( 229 | new FpuPlugin( 230 | externalFpu = false, 231 | p = new FpuParameter( 232 | withDouble = argConfig.withDouble 233 | ) 234 | ) 235 | ) 236 | } 237 | 238 | if(argConfig.externalInterruptArray) plugins ++= List( 239 | new ExternalInterruptArrayPlugin( 240 | machineMaskCsrId = 0xBC0, 241 | machinePendingsCsrId = 0xFC0, 242 | supervisorMaskCsrId = 0x9C0, 243 | supervisorPendingsCsrId = 0xDC0 244 | ) 245 | ) 246 | 247 | // Add in the Debug plugin, if requested 248 | if(argConfig.debug) { 249 | plugins += new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))) 250 | } 251 | 252 | // CPU configuration 253 | val cpuConfig = VexRiscvConfig(plugins.toList) 254 | 255 | // CPU instantiation 256 | val cpu = new VexRiscv(cpuConfig) 257 | 258 | // Rename CPU to variant name, to avoid confusion 259 | if (argConfig.privateNamespace) { 260 | cpu.setDefinitionName(argConfig.outputFile) 261 | } 262 | 263 | // CPU modifications to be an Wishbone 264 | cpu.rework { 265 | for (plugin <- cpuConfig.plugins) plugin match { 266 | case plugin: IBusSimplePlugin => { 267 | plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus 268 | master(plugin.iBus.toWishbone()).setName("iBusWishbone") 269 | } 270 | case plugin: IBusCachedPlugin => { 271 | plugin.iBus.setAsDirectionLess() 272 | master(plugin.iBus.toWishbone()).setName("iBusWishbone") 273 | } 274 | case plugin: DBusSimplePlugin => { 275 | plugin.dBus.setAsDirectionLess() 276 | master(plugin.dBus.toWishbone()).setName("dBusWishbone") 277 | } 278 | case plugin: DBusCachedPlugin => { 279 | plugin.dBus.setAsDirectionLess() 280 | master(plugin.dBus.toWishbone()).setName("dBusWishbone") 281 | } 282 | case _ => 283 | } 284 | } 285 | 286 | cpu 287 | } 288 | } 289 | } 290 | 291 | 292 | class ForceRamBlockPhase() extends spinal.core.internals.Phase{ 293 | override def impl(pc: PhaseContext): Unit = { 294 | pc.walkBaseNodes{ 295 | case mem: Mem[_] => { 296 | var asyncRead = false 297 | mem.dlcForeach[MemPortStatement]{ 298 | case _ : MemReadAsync => asyncRead = true 299 | case _ => 300 | } 301 | if(!asyncRead) mem.addAttribute("ram_style", "block") 302 | } 303 | case _ => 304 | } 305 | } 306 | override def hasNetlistImpact: Boolean = false 307 | } --------------------------------------------------------------------------------